TLV62585DRLR [TI]
采用 2x2 QFN 或 SOT563 封装的 2.5V-5.5V 输入、3A 高效降压转换器 | DRL | 6 | -40 to 125;
| 型号： | TLV62585DRLR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 采用 2x2 QFN 或 SOT563 封装的 2.5V-5.5V 输入、3A 高效降压转换器 | DRL | 6 | -40 to 125 转换器 |
| 文件： | 总28页 (文件大小：1867K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TLV62585
ZHCSGK2F –NOVEMBER 2019–REVISED NOVEMBER 2019
采用 QFN 或 SOT563 封装的 TLV62585 3A 高效
同步降压转换器
1 特性
3 说明
1
•
•
•
•
•
•
•
•
•
•
•
•
•
效率高达 95%
TLV62585 器件是一款高频同步降压转换器，经优化具
有解决方案尺寸紧凑和高效率两大优点。该器件集成了
可提供高达 3A 输出电流的开关。在中等负载至重负载
情况下，该转换器将以 1.5MHz 典型开关频率在脉宽
调制 (PWM) 模式下运行。在轻载情况下，该器件自动
进入节能模式 (PSM)，从而在整个负载电流范围内保
持高效率。关断时，流耗减少至 2μA 以下。
低 RDS(ON) 电源开关：56mΩ/32mΩ
输入电压范围为 2.5V 至 5.5V
可调输出电压范围为 0.6V 至 VIN
可实现轻负载效率的省电模式
可实现最低压降的 100% 占空比
35μA 工作静态电流
1.5MHz 典型开关频率
短路保护 (HICCUP)
内部补偿电路可实现紧凑型解决方案和较少外部组件
数。内部软启动电路可限制启动期间的浪涌电流。此
外， 还内置了 其他功能，如短路保护、热关断保护、
输出放电和电源良好指示。
输出放电
电源正常状态输出
热关断保护
该器件采用 2mm × 2mm QFN 封装或 1.6mm ×
1.6mm SOT563 封装。
采用 2mm × 2mm QFN 封装或 1.6mm x 1.6mm
SOT563 封装
•
使用 TLV62585 并借助 WEBENCH® 电源设计器创
建定制设计方案
器件信息(1)
器件型号
TLV62585RWT
TLV62585DRL
TLV62585PDRL
封装
QFN (12)
封装尺寸（标称值）
2.00mm × 2.00mm
2 应用
SOT563 (6)
1.60mm x 1.60mm
•
•
•
•
•
通用负载点电源
电池供电型应用
(1) 如需了解所有可用封装，请参阅产品说明书末尾的可订购产品
附录。
无线路由器、固态硬盘
机顶盒、多功能打印机
电机控制
空白
空白
空白
典型应用原理图
5V 输入电压效率
VPG
TLV62585
100
PG
R3
1 Mꢀ
VOUT
1.8 V / 3.0 A
VIN
2.5 V to 5.5 V
L1
1.0 µH
95
90
85
VIN
SW
C1
10 µF
C2
10 µF
C3*
R1
200 kꢀ
EN
FB
PGND
AGND
R2
100 kꢀ
C3: Optional
80
VOUT = 1.2 V
VOUT = 1.8 V
VOUT = 2.5 V
VOUT = 3.3 V
75
70
0
0.5
1
1.5
Load (A)
2
2.5
3
D008
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLVSDE5
TLV62585
ZHCSGK2F –NOVEMBER 2019–REVISED NOVEMBER 2019
www.ti.com.cn
目录
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 4
6.5 Electrical Characteristics.......................................... 5
6.6 Typical Characteristics.............................................. 5
Detailed Description .............................................. 6
7.1 Overview ................................................................... 6
7.2 Functional Block Diagram ......................................... 6
7.3 Feature Description................................................... 6
7.4 Device Functional Modes.......................................... 7
8
9
Application and Implementation .......................... 8
8.1 Application Information.............................................. 8
8.2 Typical Application ................................................... 8
Power Supply Recommendations...................... 14
10 Layout................................................................... 14
10.1 Layout Guidelines ................................................. 14
10.2 Layout Example .................................................... 14
10.3 Thermal Considerations........................................ 15
11 器件和文档支持 ..................................................... 16
11.1 器件支持................................................................ 16
11.2 文档支持................................................................ 16
11.3 接收文档更新通知 ................................................. 16
11.4 支持资源................................................................ 16
11.5 商标....................................................................... 16
11.6 静电放电警告......................................................... 16
11.7 Glossary................................................................ 16
12 机械、封装和可订购信息....................................... 17
7
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from Revision E (June 2018) to Revision F
Page
•
Changed Temperature Range for 1% Accuracy from 25°C to 0°C-85°C............................................................................... 5
Changes from Revision D (April 2018) to Revision E
Page
•
•
将 TLV62585DRL 和 TLV62585PDRL 从产品预发布 更改为生产 数据 ................................................................................. 1
已添加 PCB layout recommendation for TLV62585PDRL ................................................................................................... 14
Changes from Revision C (November 2017) to Revision D
Page
•
•
•
•
向器件信息 表添加了 TLV62585DRL 和 TLV62585PDRL...................................................................................................... 1
Added DRL and PDRL devices to the Pin Configurations and Functions.............................................................................. 3
Added the DRL Thermal Information ..................................................................................................................................... 4
Added 图 22 ......................................................................................................................................................................... 13
Changes from Revision B (September 2017) to Revision C
Page
•
Changed HBM From: ±1000 To: ±2000 in the ESD Ratings table......................................................................................... 4
Changes from Revision A (August 2017) to Revision B
Page
•
•
将器件状态从“预告信息”更改为“生产数据”.............................................................................................................................. 1
Changed HBM From: TBD To: ±1000 in the ESD Ratings table ........................................................................................... 4
Changes from Original (July 2017) to Revision A
Page
•
•
将器件状态从“生产”更改为“预告信息” ..................................................................................................................................... 1
Changed HBM From: ±2000 To: TBD in the ESD Ratings table ........................................................................................... 4
2
Copyright © 2019, Texas Instruments Incorporated
TLV62585
www.ti.com.cn
ZHCSGK2F –NOVEMBER 2019–REVISED NOVEMBER 2019
5 Pin Configuration and Functions
DRL Package
6-Pin (SOT563)
Top View
PDRL Package
6-Pin (SOT563)
Top View
GND
SW
1
2
3
6
5
4
NC
FB
EN
GND
SW
1
2
3
6
5
4
PG
FB
EN
VIN
VIN
Not to scale
Not to scale
RWT Package
12-Pin (QFN)
Top View
VIN
SW
1
2
3
4
10
9
8
7
6
PG
EN
FB
SW
11
PGND
AGND
PGND
12
5
NC
Not to scale
Pin Functions
PIN
DRL
(QFN) (SOT563) (SOT563)
I/O
DESCRIPTION
RWT
PDRL
NAME
VIN
1, 10
3
3
PWR Power supply voltage pin.
Switch pin connected to the internal FET switches and inductor terminal. Connect the
inductor of the output filter to this pin.
SW
2, 11
2
2
PWR
GND
PGND
AGND
NC
-
1
-
1
-
PWR Ground pin.
3, 12
4
PWR Power ground pin.
-
-
-
-
Ground pin.
5, 6
6
-
No connection pin. Leave these pins open, or connect those pins to the output or to
AGND.
FB
7
5
5
I
Feedback pin for the internal control loop. Connect this pin to an external feedback
divider.
Device enable logic input. Logic high enables the device, logic low disables the device
and turns it into shutdown. Do not leave floating.
EN
PG
8
9
4
-
4
6
I
Power good open drain output pin. The pull-up resistor can not be connected to any
voltage higher than 5.5 V. If unused, leave it floating or connect to AGND.
O
Copyright © 2019, Texas Instruments Incorporated
3
TLV62585
ZHCSGK2F –NOVEMBER 2019–REVISED NOVEMBER 2019
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
MIN
–0.3
–0.3
–0.3
–3.0
–40
MAX
UNIT
VIN, EN, PG
6
FB
Voltage at Pins(1)
SW (DC)
3
VIN + 0.3
9
V
SW (AC, less than 10ns)(2)
Operating Junction, TJ
Temperature
150
°C
°C
Storage, Tstg
–65
150
(1) All voltage values are with respect to network ground terminal.
(2) While switching
6.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-
±2000
±500
001(1)
Electrostatic
discharge
V(ESD)
V
Charged device model (CDM), per JEDEC specification
JESD22-C101(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
MIN
2.5
NOM
MAX
5.5
VIN
1
UNIT
V
VIN
Input voltage range
VOUT
ISINK_PG
IOUT
TJ
Output voltage range
Sink current at PG pin
Output current
0.6
V
mA
A
0
3
Operating junction temperature
–40
125
°C
6.4 Thermal Information
TLV62585
THERMAL METRIC(1)
UNIT
RWT [QFN]
95.7
DRL [SOT]
132.7
43.8
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
74.1
29.4
27.3
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
5.8
1.2
ψJB
29.7
26.6
RθJC(bot)
N/A
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
4
Copyright © 2019, Texas Instruments Incorporated
TLV62585
www.ti.com.cn
ZHCSGK2F –NOVEMBER 2019–REVISED NOVEMBER 2019
6.5 Electrical Characteristics
TJ = 25 °C, and VIN = 5 V, unless otherwise noted.
PARAMETER
SUPPLY
TEST CONDITIONS
MIN
TYP
MAX UNIT
IQ
Quiescent current into VIN
No load, device not switching
35
0.7
2.3
150
150
20
µA
ISD
Shutdown current into VIN
EN = Low
VIN falling
2
µA
V
Under voltage lock out threshold
Under voltage lock out hysteresis
Thermal shutdown threshold
Thermal shutdown hysteresis
2.45
VUVLO
mV
°C
°C
TJ rising
TJSD
LOGIC INTERFACE EN
VIH
VIL
High-level input voltage
Low-level input voltage
VIN = 2.5 V to 5.5 V
VIN = 2.5 V to 5.5 V
1.2
V
V
0.4
0.4
SOFT START, POWER GOOD
tSS
Soft start time
Time from EN high to 95% of VOUT nominal
VOUT rising, referenced to VOUT nominal
VOUT falling, referenced to VOUT nominal
Isink = 1 mA
900
95%
90%
µs
VPG
Power good threshold
VPG,OL Low-level output voltage
IPG,LKG Input leakage current into PG pin
tPG,DLY Power good delay
OUTPUT
V
VPG = 5.0 V
0.01
40
µA
µs
VFB falling
PWM mode, 2.5 V ≤ VIN ≤ 5.5 V, 0°C to 85°C
PWM mode, 2.5 V ≤ VIN ≤ 5.5 V, -40°C to 125°C
VFB = 0.6 V
594
588
600
600
0.01
10
606
612
VFB
Feedback regulation voltage
mV
IFB,LKG Feedback input leakage current
RDIS Output discharge FET on-resistance
POWER SWITCH
µA
EN = Low, VOUT = 1.8 V
Ω
High-side FET on-resistance
56
32
mΩ
mΩ
A
RDS(on)
Low-side FET on-resistance
High-side FET switch current limit
PWM switching frequency
ILIM
fSW
4
4.6
1.5
VOUT = 1.8V, IOUT = 1 A
MHz
6.6 Typical Characteristics
50
45
40
35
30
25
20
15
10
5
1.0
VIN = 2.5V
VIN = 3.0V
VIN = 3.6V
0.8
VIN = 5.0V
0.6
0.4
TJ = -40°C
TJ = 0°C
TJ = 25°C
TJ = 85°C
TJ = 105°C
TJ = 125°C
0.2
0
0.0
2.5
3.0
3.5
4.0
Input Voltage (V)
4.5
5.0
5.5
-40
-10
20
Junction Temperature (°C)
50
80
110
140
D001
D002
图 1. Quiescent Current vs Input Voltage
图 2. Shutdown Current vs Junction Temperature
版权 © 2019, Texas Instruments Incorporated
5
TLV62585
ZHCSGK2F –NOVEMBER 2019–REVISED NOVEMBER 2019
www.ti.com.cn
7 Detailed Description
7.1 Overview
The TLV62585 is a high-efficiency synchronous step-down converter. The device operates with an adaptive off-
time with peak current control scheme. The device operates at typically 1.5-MHz frequency pulse width
modulation (PWM) at moderate to heavy load currents. Based on the VIN/VOUT ratio, a simple circuit sets the
required off time for the low-side MOSFET. It makes the switching frequency relatively constant regardless of the
variation of input voltage, output voltage, and load current.
7.2 Functional Block Diagram
PG
VIN
VPG
VFB
+
Thermal
Shutdown
UVLO
Soft Start
œ
GND
Hiccup
Counter
EN
Control Logic
Peak Current Detect
VREF
SW
+
_
Gate
Drive
Modulator
Output
Discharge
FB
EN
VSW
VIN
TOFF
Zero Current Detect
GND
GND
图 3. Functional Block Diagram
7.3 Feature Description
7.3.1 Power Save Mode
The device automatically enters Power Save Mode to improve efficiency at light load when the inductor current
becomes discontinuous. In Power Save Mode, the converter reduces switching frequency and minimizes current
consumption. In Power Save Mode, the output voltage rises slightly above the nominal output voltage. This effect
is minimized by increasing the output capacitor, or adding a feed forward capacitor, as shown in 图 14.
7.3.2 100% Duty Cycle Low Dropout Operation
The device offers low input-to-output voltage difference by entering 100% duty cycle mode. In this mode, the
high-side MOSFET switch is constantly turned on and the low-side MOSFET is switched off. The minimum input
voltage to maintain output regulation, depending on the load current and output voltage, is calculated as:
VIN(MIN) = VOUT + IOUT x RDS(ON) + RL
Where
•
•
RDS(ON) = High side FET on-resistance
RL = Inductor ohmic resistance (DCR)
(1)
6
版权 © 2019, Texas Instruments Incorporated
TLV62585
www.ti.com.cn
ZHCSGK2F –NOVEMBER 2019–REVISED NOVEMBER 2019
Feature Description (接下页)
7.3.3 Soft Start
After enabling the device, internal soft startup circuitry ramps up the output voltage which reaches nominal output
voltage during a startup time. This avoids excessive inrush current and creates a smooth output voltage rise
slope. It also prevents excessive voltage drops of primary cells and rechargeable batteries with high internal
impedance.
The TLV62585 is able to start into a pre-biased output capacitor. The converter starts with the applied bias
voltage and ramps the output voltage to its nominal value.
7.3.4 Switch Current Limit and Short Circuit Protection (HICCUP)
The switch current limit prevents the device from high inductor current and from drawing excessive current from
the battery or input voltage rail. Excessive current might occur with a shorted or saturated inductor or a over load
or shorted output circuit condition. If the inductor current reaches the threshold ILIM, the high-side MOSFET is
turned off and the low-side MOSFET is turned on to ramp down the inductor current with an adaptive off-time.
When this switch current limits is triggered 32 times, the device reduces the current limit for further 32 cycles and
then stops switching to protect the output. The device then automatically start a new startup after a typical delay
time of 500 μs has passed. This is named HICCUP short circuit protection. The devices repeat this mode until
the high load condition disappears. HICCUP protection is also enabled during the startup.
7.3.5 Undervoltage Lockout
To avoid misoperation of the device at low input voltages, an undervoltage lockout (UVLO) is implemented,
which shuts down the device at voltages lower than VUVLO with a hysteresis of 150 mV.
7.3.6 Thermal Shutdown
The device goes into thermal shutdown and stops switching when the junction temperature exceeds TJSD. When
the device temperature falls below the threshold by 20°C, the device returns to normal operation automatically.
7.4 Device Functional Modes
7.4.1 Enable and Disable
The device is enabled by setting the EN pin to a logic HIGH. Accordingly, shutdown mode is forced if the EN pin
is pulled LOW with a shutdown current of typically 0.7 μA.
In shutdown mode, the internal power switches as well as the entire control circuitry are turned off. An internal
output discharge FET discharges the output through the SW pin smoothly.
7.4.2 Power Good
The TLV62585 has a power good output. The power good goes high impedance once the output is above 95%
of the nominal voltage, and is driven low once the output voltage falls below typically 90% of the nominal voltage.
The PG pin is an open-drain output and is specified to sink up to 1 mA. The power good output requires a pull-up
resistor connecting to any voltage rail less than 5.5 V. The PG signal can be used for sequencing of multiple rails
by connecting it to the EN pin of other converters. Leave the PG pin unconnected when not used.
表 1. PG Pin Logic
LOGIC STATUS
DEVICE CONDITIONS
HIGH Z
LOW
EN = High, VFB ≥ VPG
EN = High, VFB ≤ VPG
EN = Low
√
Enable
√
√
√
√
Shutdown
Thermal Shutdown
UVLO
1.4 V < VIN < 2.3 V
Power Supply Removal
VIN ≤ 1.4 V
√
版权 © 2019, Texas Instruments Incorporated
7
TLV62585
ZHCSGK2F –NOVEMBER 2019–REVISED NOVEMBER 2019
www.ti.com.cn
8 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TLV62585 is a synchronous step-down converter in which output voltage is adjusted by component
selection. The following section discusses the design of the external components to complete the power supply
design for several input and output voltage options by using typical applications as a reference.
8.2 Typical Application
VPG
TLV62585
PG
R3
1 Mꢀ
VOUT
1.8 V / 3.0 A
VIN
2.5 V to 5.5 V
L1
1.0 µH
VIN
SW
C3*
C1
10 µF
C2
10 µF
R1
200 kꢀ
EN
FB
PGND
AGND
R2
100 kꢀ
C3: Optional
图 4. 1.8-V Output Voltage Application
8.2.1 Design Requirements
For this design example, use the parameters listed in 表 2 as the input parameters.
表 2. Design Parameters
DESIGN PARAMETER
Input voltage
EXAMPLE VALUE
2.5 V to 5.5 V
1.8 V
Output voltage
Maximum output current
3 A
表 3 lists the components used for the example.
(1)
表 3. List of Components
REFERENCE
DESCRIPTION
MANUFACTURER
C1
C2
C3
L1
10 µF, Ceramic capacitor, 10 V, X7R, size 0805, GRM21BR71A106ME51
22 µF, Ceramic capacitor, 6.3 V, X7T, size 0805, GRM21BD70J226ME44
Optional
Murata
Murata
Std
1 µH, Power Inductor, size 4 mm × 4 mm × 1.5 mm, XFL4020-102ME
Depending on the output voltage, 1%, size 0603;
100 kΩ, Chip resistor, 1/16 W, 1%, size 0603;
Coilcraft
Std
R1
R2
R3
Std
1 MΩ, Chip resistor, 1/16 W, 1%, size 0603
Std
(1) See Third-Party Products disclaimer.
8
版权 © 2019, Texas Instruments Incorporated
TLV62585
www.ti.com.cn
ZHCSGK2F –NOVEMBER 2019–REVISED NOVEMBER 2019
8.2.2 Detailed Design Procedure
8.2.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the TLV62585 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
•
•
•
•
Run electrical simulations to see important waveforms and circuit performance
Run thermal simulations to understand board thermal performance
Export customized schematic and layout into popular CAD formats
Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
8.2.2.2 Setting The Output Voltage
The output voltage is set by an external resistor divider according to 公式 2:
R1
R2
R1
R2
æ
ö
÷
ø
æ
ö
÷
ø
VOUT = VFB ´ 1+
= 0.6V ´ 1+
ç
ç
è
è
(2)
R2 must not be higher than 100 kΩ to achieve high efficiency at light load while providing acceptable noise
sensitivity.
8.2.2.3 Output Filter Design
The inductor and the output capacitor together provide a low-pass filter. To simplify the selection process, 表 4
outlines possible inductor and capacitor value combinations for most applications.
表 4. Matrix of Output Capacitor and Inductor Combinations
NOMINAL COUT [µF](2)(3)
NOMINAL L [µH](1)
10
22
47
100
0.47
1
(4)
+
+
+
2.2
(1) Inductor tolerance and current derating is anticipated. The effective inductance can vary by 20% and
–30%.
(2) For low output voltage applications (< 1.8 V), more output capacitance is recommended (usually ≥ 22
μF) for smaller ripple. For output capacitance higher than 47 µF, a feed forward capacitor is needed.
(3) Capacitance tolerance and bias voltage derating is anticipated. The effective capacitance can vary by
20% and –50%.
(4) Typical application configuration. Other '+' mark indicates recommended filter combinations.
版权 © 2019, Texas Instruments Incorporated
9
TLV62585
ZHCSGK2F –NOVEMBER 2019–REVISED NOVEMBER 2019
www.ti.com.cn
8.2.2.4 Inductor Selection
The main parameter for the inductor selection is the inductor value and then the saturation current of the
inductor. To calculate the maximum inductor current under static load conditions, 公式 3 is given.
DIL
IL,MAX = IOUT,MAX
+
2
VOUT
1-
V
IN
DIL = VOUT
´
L ´ fSW
where
•
•
•
•
IOUT,MAX = Maximum output current
ΔIL = Inductor current ripple
fSW = Switching frequency
L = Inductor value
(3)
TI recommends choosing the saturation current for the inductor 20% to 30% higher than the IL,MAX, out of 公式 3.
A higher inductor value is also useful to lower ripple current but increases the transient response time as well.
8.2.2.5 Input and Output Capacitor Selection
The architecture of the TLV62585 allows use of tiny ceramic-type output capacitors with low equivalent series
resistance (ESR). These capacitors provide low output voltage ripple and are thus recommended. To keep its
resistance up to high frequencies and to achieve narrow capacitance variation with temperature, it is
recommended to use X7R or X5R dielectric.
The input capacitor is the low impedance energy source for the converter that helps provide stable operation. A
low ESR multilayer ceramic capacitor is recommended for best filtering. For most applications, 10-μF input
capacitor is sufficient; a larger value reduces input voltage ripple.
The TLV62585 is designed to operate with an output capacitor of 10 μF to 47 μF, as outlined in 表 4.
A feed forward capacitor reduces the output ripple in PSM and improves the load transient response. A 22-pF
capacitor is good for the 1.8-V output typical application.
10
版权 © 2019, Texas Instruments Incorporated
TLV62585
www.ti.com.cn
ZHCSGK2F –NOVEMBER 2019–REVISED NOVEMBER 2019
8.2.3 Application Curves
VIN = 5 V, VOUT = 1.8 V, TA = 25 ºC, unless otherwise noted.
100
95
90
85
80
75
100
95
90
85
80
75
70
65
60
70
VIN = 2.5V
VIN = 3.3V
VIN = 5.0V
VIN = 2.5V
VIN = 3.3V
VIN = 5.0V
65
60
1m
10m
100m
Load (A)
1
3
1m
10m
100m
Load (A)
1
3
D004
D005
VOUT = 1.2 V
VOUT = 1.8 V
图 5. Efficiency
图 6. Efficiency
100
100
95
90
85
80
75
70
65
60
95
90
85
80
75
70
65
60
VIN = 3.3V
VIN = 5.0V
VIN = 5 V
10m
1m
10m
100m
1
3
1m
100m
1
3
Load (A)
Load (A)
D006
D007
VOUT = 2.5 V
VOUT = 3.3 V
图 7. Efficiency
图 8. Efficiency
0.5
1.0
0.4
0.3
0.2
0.1
0
0.5
0.0
-0.1
-0.2
-0.3
-0.4
-0.5
-0.5
IOUT = 0.5A
IOUT = 1.0A
IOUT = 3.0A
VOUT = 1.8 V
VOUT = 3.3 V
-1.0
0.5
1
1.5
2
2.5
3
2.5
3.0
3.5
4.0
Input Voltage (V)
4.5
5.0
5.5
Load (A)
D009
D010
VIN = 5 V
VOUT = 1.8 V
图 9. Load Regulation
图 10. Line Regulation
版权 © 2019, Texas Instruments Incorporated
11
TLV62585
ZHCSGK2F –NOVEMBER 2019–REVISED NOVEMBER 2019
www.ti.com.cn
2000
1500
1000
500
2000
1500
1000
500
0
VOUT = 1.2V
VOUT = 1.2V
VOUT = 1.8V
VOUT = 2.5V
VOUT = 3.3V
VOUT = 1.8V
VOUT = 2.5V
VOUT = 3.3V
0
0
0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7
Load (A)
3
2.5
3
3.5
4
Input Voltage (V)
4.5
5
5.5
D011
D012
VIN = 5 V
IOUT = 1 A
图 11. Switching Frequency
图 12. Switching Frequency
ICOIL
ICOIL
0.5A/DIV
0.5A/DIV
VOUT
50mV/DIV
AC
VOUT
50mV/DIV
AC
VSW
VSW
5V/DIV
5V/DIV
Time - 5ꢀs/DIV
Time - 5ꢀs/DIV
D014
D019
IOUT = 0.1 A
IOUT = 0.1 A
C3 = 22 pF
图 13. PSM Operation
图 14. PSM Operation with A Feedforward Capacitor
VEN
ICOIL
2V/DIV
0.5A/DIV
VOUT
10mV/DIV
AC
VOUT
1V/DIV
ICOIL
VSW
2A/DIV
5V/DIV
Time - 500ns/DIV
Time - 500ꢀs/DIV
D013
D015
IOUT = 3 A
ROUT = 0.6 Ω
图 16. Start-Up and Shut-Down with Load
图 15. PWM Operation
12
版权 © 2019, Texas Instruments Incorporated
TLV62585
www.ti.com.cn
ZHCSGK2F –NOVEMBER 2019–REVISED NOVEMBER 2019
VEN
2V/DIV
ILOAD
2A/DIV
VOUT
1V/DIV
VOUT
0.1V/DIV
ICOIL
0.5A/DIV
Time - 500ꢀs/DIV
Time - 100ꢀs/DIV
D016
D017
No Load
图 17. Start-Up and Shut-Down without Load
IOUT = 0.1 A to 3 A
图 18. Load Transient
Entry
Recovery
ILOAD
2A/DIV
VOUT
1V/DIV
VOUT
0.1V/DIV
ILOAD
2A/DIV
Time - 100ꢀs/DIV
Time - 500ꢀs/DIV
D018
D020
IOUT = 0.1 A to 3 A
C3 = 22 pF
IOUT = 0.1 A
图 20. Output Short Protection (HICCUP)
图 19. Load Transient with A Feedforward Capacitor
Entry
VOUT
1V/DIV
ILOAD
2A/DIV
Time - 10ꢀs/DIV
D021
IOUT = 0.1 A
图 21. Output Short Protection (HICCUP) - Zoom In
图 22. Temperature Rise of DRL Package on EVM
版权 © 2019, Texas Instruments Incorporated
13
TLV62585
ZHCSGK2F –NOVEMBER 2019–REVISED NOVEMBER 2019
www.ti.com.cn
9 Power Supply Recommendations
The device is designed to operate from an input voltage supply range from 2.5 V to 5.5 V. Ensure that the input
power supply has a sufficient current rating for the application.
10 Layout
10.1 Layout Guidelines
The printed-circuit-board (PCB) layout is an important step to maintain the high performance of the TLV62585
device.
•
The input/output capacitors and the inductor should be placed as close as possible to the IC. This keeps the
power traces short. Routing these power traces direct and wide results in low trace resistance and low
parasitic inductance.
•
•
•
The low side of the input and output capacitors must be connected properly to the GND pin to avoid a ground
potential shift.
The sense traces connected to FB is a signal trace. Special care should be taken to avoid noise being
induced. Keep these traces away from SW nodes.
A common ground should be used. GND layers might be used for shielding.
See 图 23 and 图 24 for the recommended PCB layout.
10.2 Layout Example
Vin
C1
U1
L1
R2 R1
C2
GND
Vout
图 24. PCB Layout Recommendation (TLV62585PDRL)
图 23. PCB Layout Recommendation (TLV62585RWT)
14
版权 © 2019, Texas Instruments Incorporated
TLV62585
www.ti.com.cn
ZHCSGK2F –NOVEMBER 2019–REVISED NOVEMBER 2019
10.3 Thermal Considerations
Implementation of integrated circuits in low-profile and fine-pitch surface-mount packages typically requires
special attention to power dissipation. Many system-dependent issues such as thermal coupling, airflow, added
heat sinks and convection surfaces, and the presence of other heat-generating components affect the power
dissipation limits of a given component.
Two basic approaches for enhancing thermal performance are:
•
•
Improving the power dissipation capability of the PCB design
Introducing airflow in the system
The big copper planes connecting to the pads of the IC on the PCB improve the thermal performance of the
device. For more details on how to use the thermal parameters, see: .
•
Thermal Characteristics Application Notes, SZZA017 and SPRA953
版权 © 2019, Texas Instruments Incorporated
15
TLV62585
ZHCSGK2F –NOVEMBER 2019–REVISED NOVEMBER 2019
www.ti.com.cn
11 器件和文档支持
11.1 器件支持
11.1.1 第三方产品免责声明
TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此类
产品或服务单独或与任何 TI 产品或服务一起的表示或认可。
11.1.2 使用 WEBENCH® 工具创建定制设计方案
单击此处，使用 TLV62585 器件并借助 WEBENCH® 电源设计器创建定制设计方案。
1. 首先输入输入电压 (VIN)、输出电压 (VOUT) 和输出电流 (IOUT) 要求。
2. 使用优化器拨盘优化该设计的关键参数，如效率、尺寸和成本。
3. 将生成的设计与德州仪器 (TI) 的其他可行的解决方案进行比较。
WEBENCH 电源设计器可提供定制原理图以及罗列实时价格和组件供货情况的物料清单。
在多数情况下，可执行以下操作：
•
•
•
•
运行电气仿真，观察重要波形以及电路性能
运行热性能仿真，了解电路板热性能
将定制原理图和布局方案以常用 CAD 格式导出
打印设计方案的 PDF 报告并与同事共享
有关 WEBENCH 工具的详细信息，请访问 www.ti.com.cn/WEBENCH。
11.2 文档支持
11.2.1 相关文档
请参阅如下相关文档：
•
•
《热工特性应用手册》
《热工特性应用手册》
11.3 接收文档更新通知
要接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。点击右上角的提醒我 (Alert me) 注册后，即可每
周定期收到已更改的产品信息。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
11.4 支持资源
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.5 商标
E2E is a trademark of Texas Instruments.
WEBENCH is a registered trademark of Texas Instruments.
11.6 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
11.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
16
版权 © 2019, Texas Instruments Incorporated
TLV62585
www.ti.com.cn
ZHCSGK2F –NOVEMBER 2019–REVISED NOVEMBER 2019
12 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。
版权 © 2019, Texas Instruments Incorporated
17
PACKAGE OPTION ADDENDUM
www.ti.com
15-Sep-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TLV62585DRLR
TLV62585DRLT
TLV62585PDRLR
TLV62585PDRLT
TLV62585RWTR
TLV62585RWTT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOT-5X3
SOT-5X3
SOT-5X3
SOT-5X3
VQFN-HR
VQFN-HR
DRL
DRL
DRL
DRL
RWT
RWT
6
6
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
Call TI | SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
1BQ
1BQ
1BP
1BP
17BI
17BI
Samples
Samples
Samples
Samples
Samples
Samples
Call TI | SN
Call TI | SN
Call TI | SN
Call TI | SN
Call TI | SN
6
6
12
12
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
15-Sep-2022
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
10-Oct-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TLV62585DRLR
TLV62585DRLT
TLV62585PDRLR
TLV62585PDRLT
TLV62585RWTR
SOT-5X3
SOT-5X3
SOT-5X3
SOT-5X3
DRL
DRL
DRL
DRL
RWT
6
6
3000
250
180.0
180.0
180.0
180.0
180.0
8.4
8.4
8.4
8.4
8.4
2.0
2.0
2.0
2.0
2.3
1.8
1.8
1.8
1.8
2.3
0.75
0.75
0.75
0.75
1.15
4.0
4.0
4.0
4.0
4.0
8.0
8.0
8.0
8.0
8.0
Q3
Q3
Q3
Q3
Q2
6
3000
250
6
VQFN-
HR
12
3000
TLV62585RWTR
TLV62585RWTT
TLV62585RWTT
VQFN-
HR
RWT
RWT
RWT
12
12
12
3000
250
180.0
180.0
180.0
8.4
8.4
8.4
2.3
2.3
2.3
2.3
2.3
2.3
1.15
1.15
1.15
4.0
4.0
4.0
8.0
8.0
8.0
Q2
Q2
Q2
VQFN-
HR
VQFN-
HR
250
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
10-Oct-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TLV62585DRLR
TLV62585DRLT
TLV62585PDRLR
TLV62585PDRLT
TLV62585RWTR
TLV62585RWTR
TLV62585RWTT
TLV62585RWTT
SOT-5X3
SOT-5X3
SOT-5X3
SOT-5X3
VQFN-HR
VQFN-HR
VQFN-HR
VQFN-HR
DRL
DRL
DRL
DRL
RWT
RWT
RWT
RWT
6
6
3000
250
210.0
210.0
210.0
210.0
182.0
210.0
182.0
210.0
185.0
185.0
185.0
185.0
182.0
185.0
182.0
185.0
35.0
35.0
35.0
35.0
20.0
35.0
20.0
35.0
6
3000
250
6
12
12
12
12
3000
3000
250
250
Pack Materials-Page 2
PACKAGE OUTLINE
RWT0012A
VQFN-HR - 1 mm max height
S
C
A
L
E
5
.
0
0
0
PLASTIC QUAD FLATPACK - NO LEAD
2.1
1.9
B
A
PIN 1 INDEX AREA
2.1
1.9
1.0
0.8
C
SEATING PLANE
0.08 C
0.05
0.00
0.55
0.45
0.4
0.3
2X
2X
(0.1) TYP
5
6X 0.5
4
6
12
11
2X
SYMM
1.5
0.5
PIN 1 ID
9
1
10
0.3
0.2
0.1
0.24
0.20
10X
2X
SYMM
C A B
0.05
0.45
8X
0.35
4223084/B 10/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
RWT0012A
VQFN-HR - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
SYMM
10
2X (0.55)
8X (0.6)
10X (0.25)
1
9
(0.5)
11
12
SYMM
(R0.05) TYP
(1.85)
2X (0.22)
6X (0.5)
6
4
5
2X (0.5)
(1.8)
LAND PATTERN EXAMPLE
SCALE:30X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
SOLDER MASK
DEFINED
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4223084/B 10/2018
NOTES: (continued)
3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).
4. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, it is recommended that vias under
paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
RWT0012A
VQFN-HR - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
2X (0.55)
10
8X (0.6)
9
10X (0.25)
1
(0.5)
11
12
SYMM
(R0.05) TYP
(1.85)
6X (0.5)
2X (0.22)
6
4
5
SYMM
2X (0.5)
(1.8)
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
SCALE:30X
4223084/B 10/2018
NOTES: (continued)
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
PACKAGE OUTLINE
DRL0006A
SOT - 0.6 mm max height
S
C
A
L
E
8
.
0
0
0
PLASTIC SMALL OUTLINE
1.7
1.5
PIN 1
ID AREA
A
1
6
4X 0.5
1.7
1.5
2X 1
NOTE 3
4
3
1.3
1.1
0.3
6X
0.05
TYP
0.00
B
0.1
0.6 MAX
C
SEATING PLANE
0.05 C
0.18
0.08
6X
SYMM
SYMM
0.27
0.15
6X
0.1
0.05
C A B
0.4
0.2
6X
4223266/C 12/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MO-293 Variation UAAD
www.ti.com
EXAMPLE BOARD LAYOUT
DRL0006A
SOT - 0.6 mm max height
PLASTIC SMALL OUTLINE
6X (0.67)
SYMM
1
6
6X (0.3)
SYMM
4X (0.5)
4
3
(R0.05) TYP
(1.48)
LAND PATTERN EXAMPLE
SCALE:30X
0.05 MIN
AROUND
0.05 MAX
AROUND
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDERMASK DETAILS
4223266/C 12/2021
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
7. Land pattern design aligns to IPC-610, Bottom Termination Component (BTC) solder joint inspection criteria.
www.ti.com
EXAMPLE STENCIL DESIGN
DRL0006A
SOT - 0.6 mm max height
PLASTIC SMALL OUTLINE
6X (0.67)
SYMM
1
6
6X (0.3)
SYMM
4X (0.5)
4
3
(R0.05) TYP
(1.48)
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
SCALE:30X
4223266/C 12/2021
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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