TLV627432 [TI]
具有超低静态电流的 2.15V 至 5.5V、400mA 高效降压转换器;
| 型号： | TLV627432 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有超低静态电流的 2.15V 至 5.5V、400mA 高效降压转换器 转换器 |
| 文件： | 总31页 (文件大小：2587K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TLV627432
ZHCSKJ9B –JUNE 2016 –REVISED MARCH 2021
TLV627432 具有超低静态电流的高效降压转换器
1 特性
3 说明
• 输入电压范围：2.15V 至5.5V
• 高达400mA 的输出电流
• 工作静态电流很低
• 10µA 输出电流时的效率高达90%
• 节能模式操作
• 可选输出电压
TLV627432 是一款高效降压转换器，具有典型值为
360nA 的超低工作静态电流。该器件经过优化，可与
2.2µH 电感和10µF 输出电容配合使用。该器件采用
DCS-Control 技术，开关频率典型值为1.2MHz。在节
能模式下，该器件可将轻负载效率向下扩展至10µA 负
载电流及以下。TLV627432 的输出电流为300mA。
TLV627432 提供了八个可编程的输出电压，可通过三
个选择引脚在1.2V 至3.3V 范围内进行选择。
TLV627432 经优化，使用一个小型输出电容即可获得
低输出电压纹波和低噪声。一旦输入电压接近输出电
压，器件便会进入无纹波100% 模式，以防止输出纹
波电压增大。在此工作模式下，器件会停止开关操作并
导通高侧MOSFET。
– 八个电压选项（1.2V 至3.3V）
• 输出电压放电
• 低输出电压纹波
• 自动转换至无纹波100% 模式
• 射频(RF) 友好型DCS-Control
• 总体解决方案尺寸小于10mm2
• 小型1.57mm × 0.88mm 8 焊球WCSP 封装
器件信息
封装(1)
2 应用
封装尺寸（标称值）
器件型号
• 可穿戴设备
• 健身追踪器
• 智能手表
• 健康监测
TLV627432
DSBGA (8)
1.57mm × 0.88mm
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
®
• 低功耗蓝牙、RF4CE、Zigbee
• 高效率、超低功耗应用
• 能量收集
VIN
100
95
90
85
80
75
70
TLV627432
L 2.2 mH
2.15 V to 5.5 V
VOUT
Low Power
MCU & RF
VIN
SW
CIN
EN
VOS
4.7 mF
COUT
10 mF
VSEL1
VSEL2
VSEL3
GND
VIN = 5.0V
65
60
VIN = 4.2V
典型应用
55
VIN = 3.6V
50
45
40
0.001
0.01
0.1
1
10
100
1000
IOUT [mA]
C001
效率
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLVSDH5
TLV627432
ZHCSKJ9B –JUNE 2016 –REVISED MARCH 2021
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Table of Contents
8.4 Device Functional Modes..........................................10
9 Application and Implementation..................................12
9.1 Application Information............................................. 12
9.2 Typical Application ................................................... 12
10 Power Supply Recommendations..............................18
11 Layout...........................................................................19
11.1 Layout Guidelines................................................... 19
11.2 Layout Example...................................................... 19
12 Device and Documentation Support..........................20
12.1 Device Support....................................................... 20
12.2 接收文档更新通知................................................... 20
12.3 支持资源..................................................................20
12.4 Trademarks.............................................................20
12.5 静电放电警告.......................................................... 20
12.6 术语表..................................................................... 20
13 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Device Comparison Table ..............................................3
6 Pin Configuration and Functions...................................4
7 Specifications.................................................................. 6
7.1 Absolute Maximum Ratings........................................ 6
7.2 ESD Ratings .............................................................. 6
7.3 Recommended Operating Conditions.........................6
7.4 Thermal Information ...................................................6
7.5 Electrical Characteristics.............................................7
7.6 Timing Requirements..................................................8
7.7 Typical Characteristics................................................8
8 Detailed Description........................................................9
8.1 Overview.....................................................................9
8.2 Functional Block Diagram...........................................9
8.3 Feature Description.....................................................9
Information.................................................................... 21
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision A (December 2019) to Revision B (March 2021)
Page
• 更新了整个文档的表、图和交叉参考的编号格式。.............................................................................................1
Changes from Revision * (June 2016) to Revision A (December 2019)
Page
• 首次公开发布的文档........................................................................................................................................... 1
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5 Device Comparison Table
OUTPUT
CURRENT
PACKAGE
MARKING
TA
PART NUMBER
OUTPUT VOLTAGE SETTINGS (VSEL 1 - 3)
TLV627432
1.2 V, 1.5 V, 1.8 V, 2.1 V, 2.5 V, 2.8 V, 3.0 V, 3.3 V
400 mA
160322
–40°C to 85°C
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6 Pin Configuration and Functions
1
2
SW
EN
VIN
GND
VOS
A
B
C
D
VSEL1
VSEL2
VSEL3
图6-1. 8-Pin DSBGA YFP Package (Top View)
表6-1. Pin Functions
PIN
I/O
DESCRIPTION
NAME
NO
VIN
A2
PWR VIN power supply pin. Connect the input capacitor close to this pin for best noise and voltage spike
suppression. A ceramic capacitor of 4.7 µF is required.
SW
A1
B2
C2
OUT
The switch pin is connected to the internal MOSFET switches. Connect the inductor to this terminal.
GND
VOS
PWR GND supply pin. Connect this pin close to the GND terminal of the input and output capacitor.
IN
Feedback pin for the internal feedback divider network and regulation loop. Discharges VOUT when the
converter is disabled. Connect this pin directly to the output capacitor with a short trace.
VSEL3
VSEL2
VSEL1
EN
D2
D1
C1
B1
IN
IN
IN
IN
Output voltage selection pins. See 表6-2 for VOUT selection. These pin must be terminated. The pins can
be dynamically changed during operation.
High level enables the devices, low level turns the device off. The pin must be terminated.
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表6-2. Output Voltage Setting
Output Voltage Setting VOUT [V]
VSEL Setting
TLV627432
VSEL3
VSEL2
VSEL1
1.2
1.5
1.8
2.1
2.5
2.8
3.0
3.3
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
–0.3
–0.3
–0.3
–0.3
–40
–65
MAX
UNIT
VIN
6
V
SW
Pin voltage(2)
VIN +0.3V
VIN +0.3V
3.7
V
V
EN, VSEL1-3
VOS
Operating junction temperature, TJ
Storage temperature, Tstg
V
125
°C
°C
150
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network ground terminal GND.
7.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all
pins(1)
±2000
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per JEDEC specification
JESD22-C101, all pins(2)
±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. The human body
model is a 100-pF capacitor discharged through a 1.5-kΩresistor into each pin.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
MIN NOM MAX UNIT
VIN
IOUT
TJ
Supply voltage VIN
2.15
5.5
300
400
V
5.5V ≥VIN ≥(VOUTnom + 0.7V) ≥2.15V
5.5V ≥VIN ≥(VOUTnom + 0.7V) ≥3V
Device output current
mA
Operating junction temperature range
-40
125 °C
7.4 Thermal Information
TLV627432
YFP Package
(DSBGA)
THERMAL METRIC(1)
UNIT
8 PINS
103
1.0
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
20
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.3
ψJT
20
ψJB
RθJC(bot)
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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7.5 Electrical Characteristics
VIN = 3.6V, TA = –40°C to 85°C typical values are at TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNIT
SUPPLY
EN = VIN, IOUT = 0µA, VOUT = 1.8V, device not switching
EN = VIN, IOUT = 0mA, VOUT = 1.8V , device switching
EN = GND, shutdown current into VIN
Rising VIN
360 1800
460
Operating quiescent
current
IQ
nA
nA
V
ISD
Shutdown current
70 1000
VTH_ UVLO+
VTH_UVLO-
2.075
1.925
2.15
2
Undervoltage
lockout threshold
Falling VIN
INPUTS (EN, VSEL1-3)
High level input
threshold
VIH TH
VIL TH
1.1
25
V
2.2V ≤VIN ≤5.5V
2.2V ≤VIN ≤5.5V
Low level input
threshold
0.4
V
IIN
Input bias Current
10
nA
POWER SWITCHES
High side MOSFET
on-resistance
0.45
0.22
650
650
1.12
0.65
800
RDS(ON)
IOUT = 50mA
Ω
Low Side MOSFET
on-resistance
High side MOSFET
switch current limit
590
3.0V ≤VIN ≤5.5V
ILIMF
mA
Low side MOSFET
switch current limit
OUTPUT VOLTAGE DISCHARGE
MOSFET on-
RDSCH_VOS
EN = GND, IVOS = -10mA into VOS pin
EN = VIN, VOUT = 2V
30
65
Ω
resistance
Bias current into
VOS pin
IIN_VOS
40 1010
nA
AUTO 100% MODE TRANSITION
Auto 100% Mode
VTH_100+
leave detection
Rising VIN,100% Mode is left with VIN = VOUT + VTH_100+
Falling VIN, 100% Mode is entered with VIN = VOUT + VTH_100-
150
85
250
350
290
threshold (1)
mV
Auto 100% Mode
enter detection
threshold (1)
VTH_100-
200
OUTPUT
High side softstart
switch current limit
80
150
150
200
ILIM_softstart
EN=low to high
mA
V
Low side softstart
switch current limit
Output voltage
range
Output voltages are selected with pins VSEL 1 - 3
1.2
3.3
IOUT = 10mA, VOUT = 1.8V
IOUT = 100mA, VOUT = 1.8V
-2.5
0%
0%
2.5
2
Output voltage
accuracy
–2
VOUT
DC output voltage
load regulation
VOUT = 1.8V
0.001
0
%/mA
%/V
DC output voltage
line regulation
VOUT = 1.8V, IOUT = 100mA, 2.5V ≤VIN ≤5.0V
(1) VIN is compared to the programmed output voltage (VOUT). When VIN–VOUT falls below VTH_100- the device enters 100% Mode by
turning the high side MOSFET on. The 100% Mode is exited when VIN–VOUT exceeds VTH_100+ and the device starts switching. The
hysteresis for the 100% Mode detection threshold VTH_100+ - VTH_100- will always be positive and will be approximately 50 mV(typ)
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7.6 Timing Requirements
VIN = 3.6V, TJ = –40°C to 85°C typical values are at TA = 25°C (unless otherwise noted)
PARAMETER
Minimum ON time
TEST CONDITIONS
MIN
TYP MAX
UNIT
ns
tONmin
VOUT = 2.0V, IOUT = 0 mA
225
50
tOFFmin
Minimum OFF time
ns
Regulator start up
delay time
tStartup_delay
tSoftstart
From transition EN = low to high until device starts switching
10
25
ms
µs
Softstart time
700 1200
2.5V ≤VIN ≤5.5V, EN = VIN
7.7 Typical Characteristics
700
250
VIN = 2.2 V
VIN = 2.5 V
VIN = 3.6 V
VIN = 5.5 V
VIN = 6.0 V
VIN = 2.2 V
VIN = 2.5 V
VIN = 3.6 V
VIN = 5.5 V
225
600
200
VIN = 6.0 V
175
150
125
100
75
500
400
300
200
50
25
0
-60
-40
-20
0
20
40
60
80
100
-60
-40
-20
0
20
40
60
80
100
Temperature (èC)
Temperature (èC)
D002
D001
EN = GND
EN = VIN, VOUT = 1.8V Device Not Switching
图7-2. Shutdown Current ISD vs Temperature
图7-1. Quiescent Current vs Temperature
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.5
0.45
0.4
0.35
0.3
0.25
0.2
0.15
0.1
0.2
VIN = 2.2 V
VIN = 2.5 V
VIN = 3.6 V
VIN = 2.2 V
VIN = 2.5 V
VIN = 3.6 V
0.05
0
0.1
0
-60
-40
-20
0
20
40
60
80
100
-60
-40
-20
0
20
40
60
80
100
Temperature (èC)
Temperature (èC)
D004
D003
图7-4. Low-side RDSON vs Temperature
图7-3. High Side RDSON vs Temperature
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8 Detailed Description
8.1 Overview
The TLV627432 is a high frequency step down converter with ultra low quiescent current. The device operates
with a quasi fixed switching frequency typically at 1.2 MHz. Using TI's DCS-Control™ topology the device
extends the high efficiency operation area down to a few microamperes of load current during Power Save Mode
Operation.
8.2 Functional Block Diagram
Ultra Low Power
Reference
EN
Softstart
VOS
UVLO
EN
VOUT
Discharge
VOS
VSEL1
VSEL2
VSEL3
Internal
VFB feedback
divider
Auto 100% Mode
Comp
UVLO
Comp
100%
̶
network*
VIN
̶
VIN
Mode
UVLO
+
VTH_100
+
VTH_UVLO
Power Stage
PMOS
Current
Limit Comparator
VIN
SW
Timer
UVLO
DCS
Control
VIN
VOS
Limit
Min. On
High Side
Min. OFF
VOS
Direct Control
& Compensation
Control
Logic
EN
Gate Driver
Anti
Shoot-Through
VFB
̶
VREF
+
NMOS
Limit
Error
amplifier
Main
Comparator
Low Side
GND
Current
Limit Comparator
* typical 50 MW
8.3 Feature Description
8.3.1 DCS-Control™
TI's ™DCS-Control (Direct Control with Seamless Transition into Power Save Mode) is an advanced regulation
topology, which combines the advantages of hysteretic and voltage mode control. Characteristics of DCS-
Control™ are excellent AC load regulation and transient response, low output ripple voltage and a seamless
transition between PFM and PWM mode operation. DCS-Control™ includes an AC loop which senses the output
voltage (VOS pin) and directly feeds the information to a fast comparator stage. This comparator sets the
switching frequency, which is constant for steady state operating conditions, and provides immediate response
to dynamic load changes. In order to achieve accurate DC load regulation, a voltage feedback loop is used. The
internally compensated regulation network achieves fast and stable operation with small external components
and low ESR capacitors.
The DCS-Control™ topology supports PWM (Pulse Width Modulation) mode for medium and high load
conditions and a Power Save Mode at light loads. During PWM mode, it operates in continuous conduction
mode. The switching frequency is typically 1.2 MHz with a controlled frequency variation depending on the input
voltage and load current. If the load current decreases, the converter seamlessly enters Power Save Mode to
maintain high efficiency down to very light loads. In Power Save Mode, the switching frequency varies linearly
with the load current. Since DCS-Control™ supports both operation modes within one single building block, the
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transition from PWM to Power Save Mode is seamless with minimum output voltage ripple. The TLV627432
offers both excellent DC voltage and superior load transient regulation, combined with low output voltage ripple,
minimizing interference with RF circuits.
8.3.2 Power Save Mode Operation
In Power Save Mode the device operates in PFM (Pulse Frequency Modulation) that generates a single
switching pulse to ramp up the inductor current and recharges the output capacitor, followed by a sleep period
where most of the internal circuits are shutdown to achieve lowest operating quiescent current. During this time,
the load current is supported by the output capacitor. The duration of the sleep period depends on the load
current and the inductor peak current. During the sleep periods, the current consumption of TLV627432 is
reduced to 360 nA. This low quiescent current consumption is achieved by an ultra low power voltage reference,
an integrated high impedance feedback divider network and an optimized Power Save Mode operation.
8.3.3 Output Voltage Selection
The TLV627432 doesn't require an external resistor divider network to program the output voltage. The device
integrates a high impedance feedback resistor divider network that is programmed by the pins VSEL1-3.
TLV627432 supports an output voltage range from 1.2 V to 3.3 V. The output voltage is programmed according
to 表 6-2. The output voltage can be changed during operation. This can be used for simple dynamic output
voltage scaling.
8.3.4 Output Voltage Discharge of the Buck Converter
The device provides automatic output voltage discharge when EN is pulled low or the UVLO is triggered. The
output of the buck converter is discharged over VOS. Because of this the output voltage will ramp up from zero
once the device is enabled again. This is very helpful for accurate start-up sequencing.
8.3.5 Undervoltage Lockout UVLO
To avoid misoperation of the device at low input voltages, an undervoltage lockout is used. The UVLO shuts
down the device at a maximum voltage level of 2.0 V. The device will start at a UVLO level of 2.15 V.
8.3.6 Short circuit protection
The TLV627432 integrates a current limit on the high side, as well on the low side MOSFETs to protect the
device against overload or short circuit conditions. The peak current in the switches is monitored cycle by cycle.
If the high side MOSFET current limit is reached, the high side MOSFET is turned off and the low side MOSFET
is turned on until the switch current decreases below the low side MOSFET current limit. Once the low side
MOSFET current limit trips, the low side MOSFET is turned off and the high side MOSFET turns on again.
8.4 Device Functional Modes
8.4.1 Enable and Shutdown
The device is turned on with EN=high. With EN=low the device enters shutdown. This pin must be terminated.
8.4.2 Device Start-up and Softstart
The device has an internal softstart to minimize input voltage drop during start-up. This allows the operation from
high impedance battery cells. Once the device is enabled the device starts switching after a typical delay time of
10ms. Then the softstart time of typical 700 µs begins with a reduced current limit of typical 150 mA. When this
time passed by the device enters full current limit operation. This allows a smooth start-up and the device can
start into full load current. Furthermore, larger output capacitors impact the start-up behaviour of the DC/DC
converter. Especially when the output voltage does not reach its nominal value after the typical soft-start time of
700 µs, has passed.
8.4.3 Automatic Transition Into No Ripple 100% Mode
Once the input voltage comes close to the output voltage, the DC/DC converter stops switching and enters
100% duty cycle operation. It connects the output VOUT via the inductor and the internal high side MOSFET
switch to the input VIN, once the input voltage VIN falls below the 100% mode enter threshold, VTH_100-. The
DC/DC regulator is turned off, switching stops and therefore no output voltage ripple is generated. Since the
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output is connected to the input, the output voltage follows the input voltage minus the voltage drop across the
internal high side switch and the inductor. Once the input voltage increases and trips the 100% mode exit
threshold, VTH_100+ , the DC/DC regulator turns on and starts switching again. See 图8-1 and 图9-14.
VIN
VIN,
VOUT
100%
Mode
100%
Mode
VTH_100+
VTH_100-
Step Down Operation
VOUT
tracks VIN
VOUT
tracks VIN
VUVLO+
VUVLO-
VOUT
discharge
tsoftstart
图8-1. Automatic Transition into 100% Mode
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9 Application and Implementation
备注
以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。
9.1 Application Information
The TLV627432 is a high efficiency step down converter with ultra low quiescent current of typically 360 nA. The
device operates with a tiny 2.2-µH inductor and 10-µF output capacitor over the entire recommended operation
range. A dedicated measurement set-up is required for the light load efficiency measurement and device
quiescent current due to the operation in the sub microampere range. In this range any leakage current in the
measurement set-up will impact the measurement results.
9.2 Typical Application
VIN
TLV627432
L 2.2 mH
2.15 V to 5.5 V
VOUT
Low Power
MCU & RF
VIN
SW
CIN
EN
VOS
4.7 mF
COUT
10 mF
VSEL1
VSEL2
VSEL3
GND
图9-1. TLV627432 Typical Application Circuit
9.2.1 Design Requirements
The TLV627432 is a highly integrated DC/DC converter. The output voltage is set via a VSEL pin interface. The
design guideline provides a component selection to operate the device within the recommended operating
conditions.
表9-1 shows the list of components for the Application Characteristic Curves
表9-1. Components for Application Characteristic Curves
Reference
TLV627432
CIN
Description
Value
Manufacturer (1)
Texas Instruments
Murata
360nA Iq step down converter
Ceramic capacitor, GRM155R61C475ME15
Ceramic capacitor, GRM155R60J106ME11
Inductor DFE201610C
4.7 µF
10 µF
2.2 µH
COUT
L
Murata
Toko
(1) See Third-Party Products Disclaimer
9.2.2 Detailed Design Procedure
The first step in the design procedure is the selection of the output filter components. To simplify this process, 表
9-2 outlines possible inductor and capacitor value combinations.
表9-2. Recommended LC Output Filter Combinations
Output Capacitor Value [µF](1)
Inductor Value
[µH](2)
4.7µF
10µF
22µF
47µF
100µF
(3)
2.2
√
√
√
√
(1) Capacitance tolerance and bias voltage de-rating is anticipated. The effective capacitance varies by +20% and –50%.
(2) Inductor tolerance and current de-rating is anticipated. The effective inductance can vary by 20% and -30%.
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(3) Typical application configuration. Other check marks indicate alternative filter combinations.
9.2.2.1 Inductor Selection
The inductor value affects the peak-to-peak ripple current, the PWM-to-PFM transition point, the output voltage
ripple and the efficiency. The selected inductor has to be rated for its DC resistance and saturation current. The
inductor ripple current (ΔIL) decreases with higher inductance and increases with higher VIN or VOUT and can be
estimated according to 方程式1.
方程式 2 calculates the maximum inductor current under static load conditions. The saturation current of the
inductor should be rated higher than the maximum inductor current, as calculated with 方程式 2. This is
recommended because during a heavy load transient the inductor current rises above the calculated value. A
more conservative way is to select the inductor saturation current according to the high-side MOSFET switch
current limit, ILIMF
.
Vout
Vin
1-
DIL = Vout ´
L ´ ¦
(1)
(2)
DI
L
I
= I
+
Lmax
outmax
2
where
• f = switching frequency
• L = inductor value
• ΔIL= Peak to Peak inductor ripple current
• ILmax = Maximum Inductor current
The table below shows a list of possible inductors.
表9-3. List of Possible Inductors
INDUCTANCE [µH] DIMENSIONS [mm3]
INDCUTOR TYPE
ISAT/DCR
SUPPLIER
TOKO
COMMENT
2.2
2.2
2.2
2.2
2.0 x 1.6 x 1.0
2.0 × 1.25 × 1.0
2.0 x 1.2 x 1.0
1.6 x 0.8 x 0.8
DFE201610C
1.4 A/170 mΩ
0.7 A/230 mΩ
0.7 A/200 mΩ
0.7 A/300 mΩ
MIPSZ2012D 2R2
744 797 752 22
FDK
Efficiency plot
Wurth Electronik
TOKO
MDT1608-CH2R2M
9.2.2.2 Output Capacitor Selection
The DCS-Control™ scheme of the TLV627432 allows the use of tiny ceramic capacitors. Ceramic capacitors
with low ESR values have the lowest output voltage ripple and are recommended. The output capacitor requires
either an X7R or X5R dielectric. At light load currents, the converter operates in Power Save Mode and the
output voltage ripple is dependent on the output capacitor value. A larger output capacitors can be used
reducing the output voltage ripple. The leakage current of the output capacitor adds to the overall quiescent
current.
9.2.2.3 Input Capacitor Selection
Because the buck converter has a pulsating input current, a low ESR input capacitor is required for best input
voltage filtering to minimize input voltage spikes. For most applications a 4.7-µF input capacitor is sufficient. The
input capacitor can be increased without any limit for better input voltage filtering. The leakage current of the
input capacitor adds to the overall quiescent current. 表9-4 shows a selection of input and output capacitors.
表9-4. List of Possible Capacitors
SIZE
CAPACITOR TYPE
SUPPLIER
CAPACITANCE [μF]
4.7
0402
GRM155R61C475ME15
Murata
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表9-4. List of Possible Capacitors (continued)
SIZE
CAPACITOR TYPE
SUPPLIER
CAPACITANCE [μF]
10
0402
GRM155R60J106ME11
Murata
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9.2.3 Application Curves
100
95
90
85
80
75
70
65
60
55
50
45
40
100
95
90
85
80
75
70
65
60
55
50
45
40
35
30
VIN = 5.0V
VIN = 4.2V
VIN = 3.6V
VIN = 3.0V
VIN = 5.0V
VIN = 4.2V
VIN = 3.6V
0.001
0.01
0.1
1
10
100
1000
0
0
0
1
10
100
1000
IOUT [mA]
IOUT [mA]
C001
C001
图9-2. Efficiency vs Load Current, VOUT = 3.3 V
图9-3. Efficiency vs Load Current; VOUT = 1.8 V
90
85
80
75
70
1800
VIN = 5.0 V
VIN = 3.6 V
1600
1400
1200
1000
800
600
400
200
0
VIN = 5.0V
65
60
55
50
45
40
35
30
VIN = 4.2V
VIN = 3.6V
VIN = 3.0V
0.001
0.01
0.1
1
10
100
1000
IOUT [mA]
C001
0
50
100
150
200
250
300
350
IOUT (mA)
D011
图9-4. Efficiency vs Load Current; VOUT = 1.2 V
图9-5. Switching Frequency vs Load Current
VOUT = 3.3 V
1600
1400
1200
1000
800
1400
1200
1000
800
600
VIN = 5.0 V
VIN = 3.6 V
VIN = 3.0 V
VIN = 2.2 V
600
400
200
0
400
VIN = 5.0 V
VIN = 3.6 V
VIN = 3.0 V
VIN = 2.0 V
200
0
0
50
100
150
200
250
300
350
0
50
100
150
200
250
300 350
IOUT (mA)
IOUT (mA)
D012
D013
图9-6. Switching Frequency vs Load Current
图9-7. Switching Frequency vs Load Current
VOUT = 1.8 V
VOUT = 1.2 V
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图9-8. PFM (Power Save Mode) Mode Operation
图9-9. PWM Mode Operation
IL
IL
图9-11. Startup Into 300 mA Electronic Load
图9-10. Startup Into 100 mA Electronic Load
Soft-Start Delay
EN Delay + Soft-Start Delay
IL
IL
图9-12. Load Transient Response; 100 mA to 290
图9-13. Load Transient Response; 5 mA to 290 mA
mA
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图9-14. 100% Mode Entry and Leave Operation
IOUT = 30 mA
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10 Power Supply Recommendations
The power supply must provide a current rating according to the supply voltage, output voltage and output
current of the TLV627432.
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11 Layout
11.1 Layout Guidelines
• As for all switching power supplies, the layout is an important step in the design. Care must be taken in board
layout to get the specified performance.
• It is critical to provide a low inductance, impedance ground path. Therefore, use wide and short traces for the
main current paths.
• The input capacitor should be placed as close as possible to the IC pins VIN and GND. This is the most
critical component placement.
• The VOS line is a sensitive high impedance line and should be connected to the output capacitor and routed
away from noisy components and traces (e.g. SW line) or other noise sources.
11.2 Layout Example
VOUT
GND
COUT
L
CIN
VIN
图11-1. Recommended PCB Layout
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12 Device and Documentation Support
12.1 Device Support
12.1.1 第三方产品免责声明
TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此
类产品或服务单独或与任何TI 产品或服务一起的表示或认可。
12.2 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
12.3 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
12.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
12.5 静电放电警告
静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理
和安装程序，可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参
数更改都可能会导致器件与其发布的规格不相符。
12.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
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13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OUTLINE
YFP0008-C01
DSBGA - 0.531 mm max height
SCALE 10.000
DIE SIZE BALL GRID ARRAY
B
E
A
BALL A1
CORNER
D
0.341
0.283
C
0.531 MAX
SEATING PLANE
0.05 C
0.19
0.13
SYMM
D
C
B
SYMM
1.2
D: Max = 1.592 mm, Min = 1.531 mm
E: Max = 0.896 mm, Min = 0.836 mm
TYP
0.4 TYP
A
0.25
0.21
1
2
8X
0.015
0.4 TYP
C A B
4226583/A 03/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
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EXAMPLE BOARD LAYOUT
YFP0008-C01
DSBGA - 0.531 mm max height
DIE SIZE BALL GRID ARRAY
(0.4) TYP
8X ( 0.23)
1
2
A
(0.4) TYP
B
C
SYMM
D
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 50X
0.05 MIN
0.05 MAX
METAL UNDER
SOLDER MASK
( 0.23)
METAL
(
0.23)
EXPOSED
METAL
SOLDER MASK
OPENING
EXPOSED
METAL
SOLDER MASK
OPENING
SOLDER MASK
DEFINED
NON-SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
NOT TO SCALE
4226583/A 03/2021
NOTES: (continued)
3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
See Texas Instruments Literature No. SNVA009 (www.ti.com/lit/snva009).
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EXAMPLE STENCIL DESIGN
YFP0008-C01
DSBGA - 0.531 mm max height
DIE SIZE BALL GRID ARRAY
(0.4) TYP
(R0.05) TYP
8X ( 0.25)
1
2
A
(0.4) TYP
B
C
SYMM
METAL
TYP
D
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
SCALE: 50X
4226583/A 03/2021
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
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PACKAGE OPTION ADDENDUM
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11-Mar-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TLV627432YFPR
ACTIVE
DSBGA
YFP
8
3000 RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 85
160322
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Mar-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TLV627432YFPR
DSBGA
YFP
8
3000
180.0
8.4
0.98
1.68
0.59
4.0
8.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Mar-2021
*All dimensions are nominal
Device
Package Type Package Drawing Pins
DSBGA YFP
SPQ
Length (mm) Width (mm) Height (mm)
182.0 182.0 20.0
TLV627432YFPR
8
3000
Pack Materials-Page 2
PACKAGE OUTLINE
YFP0008
DSBGA - 0.5 mm max height
SCALE 10.000
DIE SIZE BALL GRID ARRAY
B
E
A
BALL A1
CORNER
D
0.30
0.25
C
0.5 MAX
SEATING PLANE
0.05 C
0.19
0.13
SYMM
D
C
B
SYMM
1.2
TYP
D: Max = 1.592 mm, Min =1.531 mm
E: Max = 0.896 mm, Min =0.836 mm
0.4 TYP
A
0.25
8X
1
2
0.21
0.4 TYP
0.015
C A B
4225242/A 08/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
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EXAMPLE BOARD LAYOUT
YFP0008
DSBGA - 0.5 mm max height
DIE SIZE BALL GRID ARRAY
(0.4) TYP
8X ( 0.23)
1
2
A
(0.4) TYP
B
C
SYMM
D
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 50X
0.05 MIN
0.05 MAX
METAL UNDER
SOLDER MASK
(
0.23)
METAL
(
0.23)
EXPOSED
METAL
SOLDER MASK
OPENING
EXPOSED
METAL
SOLDER MASK
OPENING
SOLDER MASK
DEFINED
NON-SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
NOT TO SCALE
4225242/A 08/2019
NOTES: (continued)
3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
See Texas Instruments Literature No. SNVA009 (www.ti.com/lit/snva009).
www.ti.com
EXAMPLE STENCIL DESIGN
YFP0008
DSBGA - 0.5 mm max height
DIE SIZE BALL GRID ARRAY
(0.4) TYP
(R0.05) TYP
8X ( 0.25)
1
2
A
(0.4) TYP
B
C
SYMM
METAL
TYP
D
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
SCALE: 50X
4225242/A 08/2019
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
www.ti.com
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