TLV6700QDSERQ1 [TI]
TLV6700-Q1 Micropower, 18-V Window Comparator With 400-mV Reference;
| 型号： | TLV6700QDSERQ1 |
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TEXAS INSTRUMENTS |
| 描述： | TLV6700-Q1 Micropower, 18-V Window Comparator With 400-mV Reference |
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TLV6700-Q1
SNVSBG5 – NOVEMBER 2020
TLV6700-Q1 Micropower, 18-V Window Comparator With 400-mV Reference
1 Features
3 Description
•
•
Qualified for automotive applications
AEC-Q100 qualified with the following results:
– Device temperature Grade 1: –40°C to 125°C
ambient operating temperature range
– Device HBM ESD classification level H2
– Device CDM ESD classification level C6
Wide supply voltage range: 1.8 V to 18 V
Adjustable threshold: down to 400 mV
High threshold accuracy:
The TLV6700-Q1 is
a
high voltage window
comparator that operates over a 1.8 V to 18 V range.
The device has two high-accuracy comparators with
an internal 400-mV reference and two open-drain
outputs rated to 18 V. The TLV6700-Q1 can be used
as a window comparator or as two independent
comparators; the monitored voltage can be set with
the use of external resistors.
•
•
•
OUTA is driven low when the voltage at INA+ drops
below (VITP – VHYS), and goes high when the voltage
returns above the respective threshold (VITP). OUTB
is driven low when the voltage at INB– rises above V
ITP, and goes high when the voltage drops below the
respective threshold (VITP – VHYS). Both comparators
in the TLV6700-Q1 include built-in hysteresis to reject
brief glitches, thereby ensuring stable output
operation without false triggering.
– 0.5% Max at 25°C
– 1.0% Max over temperature
Low quiescent current: 5.5 µA (Typ)
Open-drain outputs
Internal hysteresis: 5.5 mV (Typ)
Temperature range: –40°C to 125°C
Package:
•
•
•
•
•
– thin SOT-23-6
– Leadless WSON-6
The TLV6700-Q1 is available in a Thin SOT-23-6 and
leadless WSON-6; the comparators are specified over
the junction temperature range of –40°C to 125°C.
2 Applications
Device Information (1)
•
•
•
•
Emergency call (eCall)
Automotive head unit
Instrument cluster
PART NUMBER
PACKAGE
SOT-23 (6)
WSON (6)
BODY SIZE (NOM)
2.90 mm × 1.60 mm
1.50 mm × 1.50 mm
TLV6700-Q1
On-board (OBC) & wireless charger
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
VPULL-UP
(Up To 18 V)
1.8 V to 18 V
VDD
OUTA
INA+
VIT+
INA+
OUTB
INB–
INBœ
VIT+
Reference
Output Response
GND
Simplified Block Diagram
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TLV6700-Q1
SNVSBG5 – NOVEMBER 2020
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Table of Contents
1 Features............................................................................1
2 Applications.....................................................................1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Device Comparison Table...............................................3
6 Pin Configuration and Functions...................................4
7 Specifications.................................................................. 5
7.1 Absolute Maximum Ratings........................................ 5
7.2 ESD Ratings............................................................... 5
7.3 Recommended Operating Conditions.........................5
7.4 Thermal Information....................................................5
7.5 Electrical Characteristics.............................................6
7.6 Timing Requirements..................................................7
7.7 Switching Characteristics............................................7
7.8 Timing Diagrams ........................................................7
7.9 Typical Characteristics................................................8
8 Detailed Description......................................................10
8.1 Overview...................................................................10
8.2 Functional Block Diagram.........................................10
8.3 Feature Description...................................................10
8.4 Device Functional Modes..........................................12
9 Application and Implementation..................................13
9.1 Application Information............................................. 13
9.2 Typical Application.................................................... 16
9.3 Do's and Don'ts.........................................................18
10 Power Supply Recommendations..............................19
11 Layout...........................................................................20
11.1 Layout Guidelines................................................... 20
11.2 Layout Example...................................................... 20
12 Device and Documentation Support..........................21
12.1 Device Support....................................................... 21
12.2 Receiving Notification of Documentation Updates..21
12.3 Support Resources................................................. 21
12.4 Trademarks.............................................................21
12.5 Electrostatic Discharge Caution..............................21
12.6 Glossary..................................................................21
13 Mechanical, Packaging, and Orderable
Information.................................................................... 21
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
DATE
November 2020
REVISION
NOTES
*
Initial Release
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5 Device Comparison Table
Table 5-1. Industrial TLV67xx Comparator Family
OPERATING
VOLTAGE RANGE
THRESHOLD ACCURACY OVER
TEMPERATURE
PART NUMBER
CONFIGURATION
TLV6700
TLV6703
TLV6710
TLV6713
Window
1.8 V to 18 V
1.8 V to 18 V
1.8 V to 36 V
1.8 V to 36 V
1%
1%
Non-Inverting Single Channel
Window
0.75%
0.75%
Non-Inverting Single Channel
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6 Pin Configuration and Functions
OUTA
1
2
3
6
5
4
OUTB
VDD
GND
INA+
INB-
Figure 6-1. DDC Package, SOT-23-6, Top View
OUTB
VDD
1
2
3
6
5
4
OUTA
GND
INA+
INB-
Figure 6-2. DSE Package, WSON-6, Top View
Table 6-1. Pin Functions
PIN
DDC
2
I/O
DESCRIPTION
NAME
DSE
GND
5
—
Ground
This pin is connected to the voltage to be monitored with the use of an external resistor
divider. When the voltage at this terminal drops below the threshold voltage (VITP – V
HYS), OUTA is driven low.
INA+
INB–
3
4
1
4
3
6
I
I
This pin is connected to the voltage to be monitored with the use of an external resistor
divider. When the voltage at this terminal exceeds the threshold voltage (VITP), OUTB is
driven low.
INA+ comparator open-drain output. OUTA is driven low when the voltage at this
comparator is below (VITP – VHYS). The output goes high when the sense voltage
returns above the respective threshold (VITP).
OUTA
O
INB– comparator open-drain output. OUTB is driven low when the voltage at this
comparator exceeds VITP. The output goes high when the sense voltage returns below
the respective threshold (VITP – VHYS).
OUTB
VDD
6
5
1
2
O
I
Supply voltage input. Connect a 1.8-V to 18-V supply to VDD to power the device. Good
analog design practice is to place a 0.1-µF ceramic capacitor close to this pin.
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7 Specifications
7.1 Absolute Maximum Ratings
over operating temperature range (unless otherwise noted)(1)
MIN
–0.3
–0.3
–0.3
MAX
20
UNIT
V
VDD
Voltage(2)
OUTA, OUTB
20
V
INA+, INB–
7
V
Current
Output terminal current
40
mA
°C
°C
Operating junction temperature, TJ
Storage temperature, Tstg
–40
–65
125
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) All voltages are with respect to network ground terminal.
7.2 ESD Ratings
VALUE
±2500
±1000
UNIT
Human body model (HBM), per AEC Q100-002 (1)
Charged-device model (CDM), per AEC Q100-011
V(ESD)
Electrostatic discharge
V
(1) JEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
7.3 Recommended Operating Conditions
over operating temperature range (unless otherwise noted)
MIN
1.8
0
NOM
MAX UNIT
VDD
VI
Supply voltage
Input voltage
Output voltage
18
6.5
18
V
V
V
INA+, INB–
VO
OUTA, OUTB
0
7.4 Thermal Information
DDC
DSE (WSON)
THERMAL METRIC(1)
UNIT
(SOT)
6 PINS
204.6
50.5
54.3
0.8
6 PINS
194.9
128.9
153.8
11.9
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top) Junction-to-case (top) thermal resistance
RθJB
ψJT
Junction-to-board thermal resistance
Junction-to-top characterization parameter
Junction-to-board characterization parameter
ψJB
52.8
N/A
157.4
N/A
RθJC(bot) Junction-to-case (bottom) thermal resistance
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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7.5 Electrical Characteristics
Over the operating temperature range of TJ = –40°C to 125°C, and 1.8 V < VDD < 18 V, unless otherwise noted.
Typical values are at TJ = 25°C and VDD = 5 V.
PARAMETER
TEST CONDITIONS
VOLmax = 0.2 V, I(OUTA/B) = 15 µA
VDD = 1.8V and 18 V, TJ = 25°C
MIN
TYP
MAX UNIT
V(POR) Power-on reset voltage(1)
0.8
402.5
404
397.5
400
12
V
398
396
400
VIT+
Positive-going input threshold voltage
mV
VDD = 1.8V and 18 V, TJ = –40°C to 125°C
VDD = 1.8V and 18 V, TJ = 25°C
391.6
387
394.5
VIT–
Negative-going input threshold voltage
mV
VDD = 1.8V and 18 V, TJ = –40°C to 125°C
Vhys
Hysteresis voltage (hys = VIT+ – VIT–
Input current (at the INA+ terminal)
Input current (at the INB– terminal)
)
5.5
1
mV
nA
nA
I(INA+)
I(INB–)
VDD = 1.8 V and 18 V, VI = 6.5 V
VDD = 1.8 V and 18 V, VI = 0.1 V
VDD = 1.8 V, IO = 3 mA
VDD = 5 V, IO = 5 mA
VDD = 1.8 V and 18 V, VO = VDD
VDD = 1.8 V, VO = 18 V
VDD = 1.8 V, no load
VDD = 5 V
–25
–15
25
1
15
250
250
300
300
11
VOL
Low-level output voltage
mV
nA
Ilkg(OD) Open-drain output leakage-current
5.5
6
13
IDD
Supply current
µA
VDD = 12 V
6
13
VDD = 18 V
7
13
Start-up delay(2)
150
450
1.7
µs
V
UVLO Undervoltage lockout(3)
VDD falling
1.3
(1) The lowest supply voltage (VDD) at which output is active; tr(VDD) > 15 µs/V. Below V(POR), the output cannot be determined.
(2) During power on, VDD must exceed 1.8 V for 450 µs (max) before the output is in a correct state.
(3) When VDD falls below UVLO, OUTA is driven low and OUTB goes to high impedance. The outputs cannot be determined below V(POR)
.
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7.6 Timing Requirements
over operating temperature range (unless otherwise noted)
MIN
NOM MAX UNIT
VDD = 5 V, 10-mV input overdrive,
RP = 10 kΩ, VOH = 0.9 × VDD, VOL = 400 mV,
see Figure 7-1
tPHL
High-to-low propagation delay(1)
Low-to-high propagation delay(1)
18
29
µs
µs
VDD = 5 V, 10-mV input overdrive,
RP = 10 kΩ, VOH = 0.9 × VDD, VOL = 400 mV,
see Figure 7-1
tPLH
(1) High-to-low and low-to-high refers to the transition at the input terminals (INA+ and INB–).
7.7 Switching Characteristics
Over operating temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
VDD = 5 V, 10-mV input overdrive,
RP = 10 kΩ, VO = (0.1 to 0.9) × VDD
tr
tf
Output rise time
2.2
µs
VDD = 5 V, 10-mV input overdrive,
RP = 10 kΩ, VO = (0.1 to 0.9) × VDD
Output fall time
0.22
µs
7.8 Timing Diagrams
VDD
VIT+
Vhys
INA+
OUTA
tPHL
tPLH
tPLH
VIT+
Vhys
INB–
OUTB
tPLH
tPHL
Figure 7-1. Timing Diagram
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7.9 Typical Characteristics
at TJ = 25°C and VDD = 5 V (unless otherwise noted)
401
400.6
400.2
399.8
399.4
399
10
9
VDD = 1.8 V
VDD = 5 V
VDD = 1.2 V
VDD = 18 V
8
7
6
5
4
3
-40èC
0èC
2
1
0
25èC
85èC
125èC
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (èC)
0
2
4
6
8
10
Supply Voltage (V)
12
14
16
18
D003
D001
Figure 7-3. Rising Input Threshold Voltage (VIT+) vs
Temperature
Figure 7-2. Supply Current (IDD) vs Supply Voltage (VDD
)
9
31
VDD = 1.8 V, INB- to OUTB
VDD = 18 V, INB- to OUTB
VDD = 1.8 V, INA+ to OUTA
VDD = 18 V, INA+ to OUTA
29
27
25
23
21
19
17
15
13
11
9
8
7
6
5
4
3
VDD = 1.8 V
VDD = 5 V
VDD = 12 V
VDD = 18 V
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (èC)
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (èC)
D004
D005
Figure 7-4. Hysteresis (Vhys) vs Temperature
Figure 7-5. Propagation Delay vs Temperature (High-to-Low
Transition at the Inputs)
30
28
26
24
22
20
18
16
14
12
10
8
20
INA+
INB–
18
16
14
12
10
8
6
VDD = 1.8 V, INB- to OUTB
VDD = 18 V, INB- to OUTB
VDD = 1.8 V, INA+ to OUTA
VDD = 18 V, INA+ to OUTA
4
2
0
2.5
4
5.5
7
8.5
Positive-Going Input Threshold Overdrive (%)
10 11.5
13 14.5 16
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (èC)
D007
D006
INA+ = negative spike below VIT–
INB– = positive spike above VIT+
Figure 7-7. Minimum Pulse Duration vs Threshold Overdrive
Voltage
Figure 7-6. Propagation Delay vs Temperature (Low-to-High
Transition at the Inputs)
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7.9 Typical Characteristics (continued)
at TJ = 25°C and VDD = 5 V (unless otherwise noted)
11
10
9
2000
1750
1500
1250
1000
750
VDD = 1.8 V
VDD = 5 V
VDD = 18 V
8
7
6
5
4
-40èC
0èC
25èC
85èC
125èC
500
3
250
2
0
1
0
5
10
15
20
25
Output Sink Current (mA)
30
35
40
0
4
8
12
16
20
24
Output Sink Current (mA)
28
32
36
40
D009
D008
Figure 7-9. Output Voltage Low (VOL) vs Output Sink Current (–
40°C)
Figure 7-8. Supply Current (IDD) vs Output Sink Current
2000
2000
VDD = 1.8 V
VDD = 5 V
VDD = 18 V
VDD = 1.8 V
VDD = 5 V
VDD = 18 V
1750
1500
1250
1000
750
500
250
0
1750
1500
1250
1000
750
500
250
0
0
5
10
15
20
25
Output Sink Current (mA)
30
35
40
0
5
10
15
20
25
Output Sink Current (mA)
30
35
40
D010
D011
Figure 7-10. Output Voltage Low (VOL) vs Output Sink Current
(0°C)
Figure 7-11. Output Voltage Low (VOL) vs Output Sink Current
(25°C)
2000
2000
VDD = 1.8 V
VDD = 5 V
VDD = 18 V
VDD = 1.8 V
VDD = 5 V
VDD = 18 V
1750
1500
1250
1000
750
500
250
0
1750
1500
1250
1000
750
500
250
0
0
5
10
15
Output Sink Current (mA)
20
25
30
35
40
0
5
10
15
Output Sink Current (mA)
20
25
30
35
40
D012
D013
Figure 7-12. Output Voltage Low (VOL) vs Output Sink Current
(85°C)
Figure 7-13. Output Voltage Low (VOL) vs Output Sink Current
(125°C)
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8 Detailed Description
8.1 Overview
The TLV6700-Q1 device combines two comparators for overvoltage and undervoltage detection. The TLV6700-
Q1 has a wide-supply voltage range (1.8 V to 18 V) with a high-accuracy rising-input threshold of 400 mV (1%
over temperature) and built-in hysteresis. The outputs are also rated to 18 V, independant of supply voltage, and
can sink up to 40 mA.
The TLV6700-Q1 is designed to assert the output signals, as shown in Table 8-1. Each input terminal can be set
to monitor any voltage above 0.4 V using an external resistor divider network. Each input pin has very low input
leakage current, allowing the use of large resistor dividers without sacrificing system accuracy. With the use of
two input terminals of different polarities, the TLV6700-Q1 forms a window comparator. The relationship between
the inputs and the outputs is shown in Table 8-1. Broad voltage thresholds can be supported that allow the
device to be used in a wide array of applications.
Table 8-1. TLV6700 Truth Table
CONDITION
INA+ > VIT+
INA+ < VIT–
INB– > VIT+
INB– < VIT–
OUTPUT
OUTA high
OUTA low
OUTB low
OUTB high
OUTPUT STATE
Output A high impedance
Output A sinking
Output B sinking
Output B high impedance
8.2 Functional Block Diagram
VDD
INA+
OUTA
OUTB
INB–
Reference
GND
8.3 Feature Description
8.3.1 Inputs (INA+, INB–)
The TLV6700-Q1 device combines two comparators. Each comparator has one external input (inverting and
noninverting); the other input is connected to the internal reference. The comparator rising threshold is designed
and trimmed to be equal to the reference voltage (400 mV). Both comparators also have a built-in falling
hysteresis that makes the device less sensitive to supply rail noise and ensures stable operation.
The comparator inputs can swing from ground to 6.5 V, regardless of the device supply voltage used. Although
not required in most cases, good analog design practice is to place a 1-nF to 10-nF bypass capacitor at the
comparator input for extremely noisy applications to reduce sensitivity to transients and layout parasitics.
For comparator A, the corresponding output (OUTA) is driven to logic low when the input INA+ voltage drops
below (VIT+ – Vhys). When the voltage exceeds VIT+, the output (OUTA) goes to a high-impedance state; see
Figure 7-1.
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For comparator B, the corresponding output (OUTB) is driven to logic low when the voltage at input INB–
exceeds VIT+. When the voltage drops below VIT+ – Vhys the output (OUTB) goes to a high-impedance state; see
Figure 7-1. Together, these comparators form a window-detection function as discussed in the Section 8.3.3
section.
8.3.2 Outputs (OUTA, OUTB)
In a typical TLV6700-Q1 application, the outputs are connected to a GPIO input of the processor (such as a
digital signal processor [DSP], central processing unit [CPU], field-programmable gate array [FPGA], or
application-specific integrated circuit [ASIC]).
The TLV6700-Q1 device provides two open-drain outputs (OUTA and OUTB). Pullup resistors must be used to
hold these lines high when the output goes to high impedance (not asserted). By connecting pullup resistors to
the proper voltage rails, the outputs can be connected to other devices at the correct interface-voltage levels.
The TLV6700-Q1 outputs can be pulled up to 18 V, independent of the device supply voltage. By using wired-OR
logic, OUTA and OUTB can merge into one logic signal that goes low if either outputs are asserted because of a
fault condition.
Table 8-1 and the Section 8.3.1 section describe how the outputs are asserted or deasserted. See Figure 7-1 for
a timing diagram that describes the relationship between threshold voltages and the respective output.
8.3.3 Window Comparator
The inverting and noninverting configuration of the comparators forms a window-comparator detection circuit
using a resistor divider network, as illustrated in Figure 8-1 and Figure 8-2. The input terminals can monitor any
system voltage above 400 mV with the use of a resistor divider network. The INA+ and INB– terminals monitor
for undervoltage and overvoltage conditions, respectively.
Figure 8-1. Window Comparator Block Diagram
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Overvoltage
Limit
VMON
Undervoltage
Limit
OUTB
OUTA
Figure 8-2. Window Comparator Timing Diagram
8.3.4 Immunity to Input Terminal Voltage Transients
The TLV6700-Q1 device is relatively immune to short voltage transient spikes on the input terminals. Sensitivity
to transients depends on both transient duration and amplitude; see the Minimum Pulse Duration vs Threshold
Overdrive Voltage curve (Figure 7-7) in the Section 7.9 section.
8.4 Device Functional Modes
8.4.1 Normal Operation (VDD > UVLO)
When the voltage on VDD is greater than 1.8 V for at least 150 µs, the OUTA and OUTB signals correspond to
the voltage on INA+ and INB– as listed in Table 8-1.
8.4.2 Undervoltage Lockout (V(POR) < VDD < UVLO)
When the voltage on VDD is less than the device UVLO voltage, and greater than the power-on reset voltage, V
(POR), the OUTA and OUTB signals are asserted and high impedance, respectively, regardless of the voltage on
INA+ and INB–.
8.4.3 Power-On Reset (VDD < V(POR)
)
When the voltage on VDD is lower than the required voltage to internally pull the asserted output to GND (V
(POR)), both outputs are in a high-impedance state.
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9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
9.1 Application Information
The TLV6700-Q1 device is a wide-supply voltage window comparator that operates over a VDD range of 1.8 V to
18 V. The device has two high-accuracy comparators with an internal 400-mV reference and two open-drain
outputs rated to 18 V for overvoltage and undervoltage detection. The device can be used either as a window
comparator or as two independent voltage monitors. The monitored voltages are set with the use of external
resistors.
9.1.1 VPULLUP to a Voltage Other Than VDD
The outputs are often tied to VDD through a resistor. However, some applications may require the outputs to be
pulled up to a higher or lower voltage than VDD to correctly interface with the input terminals of other devices.
Figure 9-1. Interfacing to Voltages Other Than VDD
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9.1.2 Monitoring VDD
Many applications monitor the same rail that is powering VDD. In these applications the resistor divider is simply
connected to the VDD rail.
Figure 9-2. Monitoring the Same Voltage as VDD
9.1.3 Monitoring a Voltage Other Than VDD
Some applications monitor rails other than the one that is powering V DD. In these types of applications the
resistor divider used to set the desired thresholds is connected to the rail that is being monitored.
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The inputs can monitor a voltage higher than VDDmax with the use of an external resistor divider network.
Figure 9-3. Monitoring a Voltage Other Than VDD
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9.2 Typical Application
The TLV6700-Q1 device is a wide-supply voltage window comparator that operates over a VDD range of 1.8 to
18 V. The monitored voltages are set with the use of external resistors, so the device can be used either as a
window comparator or as two independent overvoltage and undervoltage monitors.
V
V
DD
PULLUP
C1
0.1 µF
R4
49.9 kꢀ
R5
49.9 kꢀ
U1
TLV6700DDC
R1
2.21 Mꢀ
V
DD
OUTA
5
1
INA+
OUTB
GND
3
4
6
2
INBœ
R2
13.7 kꢀ
R3
69.8 kꢀ
Figure 9-4. Typical Application Schematic
9.2.1 Design Requirements
For this design example, use the values summarized in Table 9-1 as the input parameters.
Table 9-1. Design Parameters
PARAMETER
DESIGN REQUIREMENT
DESIGN RESULT
12-V nominal rail with maximum rising and
falling thresholds of ±10%
VMON(UV)= 10.99 V (8.33%) ±2.94%,
VMON(OV)= 13.14 V (8.33%) ±2.94%
Monitored voltage
9.2.2 Detailed Design Procedure
9.2.2.1 Resistor Divider Selection
Use Equation 1 through Equation 4 to calculate the resistor divider values and target threshold voltages.
RT = R1 + R2 + R3
(1)
Select a value for RT such that the current through the divider is approximately 100 times higher than the input
current at the INA+ and INB– terminals. The resistors can have high values to minimize current consumption as
a result of low-input bias current without adding significant error to the resistive divider. See the application note
Optimizing Resistor Dividers at a Comparator Input (SLVA450) for details on sizing input resistors.
Use Equation 2 to calculate the value of R3.
RT
R3 =
´ VIT+
VMON(OV)
(2)
where:
VMON(OV) is the target voltage at which an overvoltage condition is detected
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Use Equation 3 or Equation 4 to calculate the value of R2.
RT
R2 =
´ VIT+ - R3
VMON (no UV)
(3)
where:
VMON(no UV) is the target voltage at which an undervoltage condition is removed as VMON rises
RT
R2 =
´ (VIT+ - Vhys
)
- R3
VMON(UV)
(4)
where:
VMON(UV) is the target voltage at which an undervoltage condition is detected
The worst-case tolerance can be calculated by referring to Equation 13 in application report SLVA450,
Optimizing Resistor Dividers at a Comparator Input (available for download at www.ti.com). An example of the
rising threshold error, VMON(OV), is given in Equation 5.
VIT+(INB)
0.4
13.2
% ACC = % TOL(VIT+(INB)) + 2 ´
´ % TOLR = 1% + 2 ´
1-
1-
´ 1% = 2.94%
VMON(OV)
(5)
9.2.2.2 Pullup Resistor Selection
To ensure proper voltage levels, the pullup resistor value is selected by ensuring that the pullup voltage divided
by the resistor does not exceed the sink-current capability of the device. This confirmation is calculated by
verifying that the pullup voltage minus the output-leakage current (Ilkg(OD)) multiplied by the resistor is greater the
desired logic-high voltage. These values are specified in the Section 7.5 table.
Use Equation 6 to calculate the value of the pullup resistor.
(VHI - VPU)
VPU
IO
³ RPU
³
Ilkg(OD)
(6)
9.2.2.3 Input Supply Capacitor
Although an input capacitor is not required for stability, connecting a 0.1-μF low equivalent series resistance
(ESR) capacitor across the V DD terminal and GND terminal is good analog design practice. A higher-value
capacitor may be necessary if large, fast rise-time load transients are anticipated, or if the device is not located
close to the power source.
9.2.2.4 Input Capacitors
Although not required in most cases, for extremely noisy applications, placing a 1-nF to 10-nF bypass capacitor
from the comparator inputs (INA+, INB–) to the GND terminal is good analog design practice. This capacitor
placement reduces device sensitivity to transients.
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9.2.3 Application Curves
At TJ = 25°C
OUTB
C2
(2 V/div)
C2
(2 V/div)
OUTB
OUTA
OUTA
C1
(2 V/div)
C1
(2 V/div)
C3
(2 V/div)
C3
(2 V/div)
VDD
VDD
Time (100 µs/div)
V(INA+) = 390 mV
Time (100 µs/div)
V(INA+) = 410 mV V(INB–) = 390 mV
G013
G014
VDD = 5 V
V(INB–) = 410 mV
VDD = 5 V
Figure 9-5. Start-Up Delay (OUT Pulled Up to VDD
)
Figure 9-6. Start-Up Delay (OUT Pulled Up to VDD)
9.3 Do's and Don'ts
It is good analog design practice to have a 0.1-µF decoupling capacitor from VDD to GND.
If the monitored rail is noisy, connect decoupling capacitors from the comparator inputs to GND.
Do not use resistors for the voltage divider that cause the current through them to be less than 100 times the
input current of the comparators without also accounting for the effect to the accuracy.
Do not use pullup resistors that are too small, because the larger current sunk by the output then exceeds the
desired low-level output voltage (VOL).
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10 Power Supply Recommendations
The TLV6700-Q1 has a 20 V absolute maximum rating on the VDD pin, with a recommended operating condition
of 18V. If the voltage supply that is providing power to VDD is susceptible to any large voltage transient that may
exceed 20 V, or if the supply exhibits high voltage slew rates greater than 1 V/µs, take additional precautions.
Place an RC filter between the supply and VDD to filter any high-frequency transient surges on the VDD pin. A
100-Ω resistor and 0.01-µF capacitor is required in these cases, as shown in Figure 10-1.
100 Ω
0.01 ꢀF
+
œ
VPULLUP
R1
VDD
INA
INB
OUTA
OUTB
R2
R3
GND
Figure 10-1. Using an RC Filter to Remove High-Frequency Disturbances on VDD
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11 Layout
11.1 Layout Guidelines
Placing a 0.1-µF capacitor close to the VDD terminal to reduce the input impedance to the device is good analog
design practice. The pullup resistors can be separated if separate logic functions are needed (as shown in
Figure 11-1) or both resistors can be tied to a single pullup resistor if a logical AND function is desired.
11.2 Layout Example
Figure 11-1. TLV6700 Layout Schematic
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12 Device and Documentation Support
12.1 Device Support
12.1.1 Development Support
The DIP Adapter Evaluation Module allows conversion of the SOT-23-6 package to a standard DIP-6 pinout for
ease of prototyping and bench evaluation.
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.6 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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15-Nov-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
3000
3000
(1)
(2)
(3)
(4/5)
(6)
TLV6700QDDCRQ1
TLV6700QDSERQ1
ACTIVE SOT-23-THIN
DDC
6
6
Green (RoHS
& no Sb/Br)
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
2DI1
K6
ACTIVE
WSON
DSE
Green (RoHS
& no Sb/Br)
NIPDAUAG
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
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15-Nov-2020
OTHER QUALIFIED VERSIONS OF TLV6700-Q1 :
Catalog: TLV6700
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Addendum-Page 2
PACKAGE OUTLINE
DDC0006A
SOT - 1.1 max height
S
C
A
L
E
4
.
0
0
0
SOT
3.05
2.55
1.1 MAX
1.75
1.45
0.1 C
B
A
PIN 1
INDEX AREA
1
6
4X 0.95
1.9
3.05
2.75
4
3
0.5
0.3
0.1
6X
TYP
0.0
0.2
C A B
0 -8 TYP
C
0.25
GAGE PLANE
SEATING PLANE
0.20
TYP
0.12
0.6
0.3
TYP
4214841/A 08/2016
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Reference JEDEC MO-193.
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EXAMPLE BOARD LAYOUT
DDC0006A
SOT - 1.1 max height
SOT
SYMM
6X (1.1)
1
6
6X (0.6)
SYMM
4X (0.95)
4
3
(R0.05) TYP
(2.7)
LAND PATTERN EXAMPLE
EXPLOSED METAL SHOWN
SCALE:15X
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
SOLDERMASK DETAILS
4214841/A 08/2016
NOTES: (continued)
4. Publication IPC-7351 may have alternate designs.
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
DDC0006A
SOT - 1.1 max height
SOT
SYMM
6X (1.1)
1
6
6X (0.6)
SYMM
4X(0.95)
4
3
(R0.05) TYP
(2.7)
SOLDER PASTE EXAMPLE
BASED ON 0.125 THICK STENCIL
SCALE:15X
4214841/A 08/2016
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.
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