TLV6710 [TI]
采用集成基准的低功耗高电压窗口比较器;
| 型号： | TLV6710 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 采用集成基准的低功耗高电压窗口比较器 比较器 |
| 文件： | 总28页 (文件大小：1533K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TLV6710
ZHCSHH2B –JANUARY 2018–REVISED OCTOBER 2018
具有 400mV 基准电压的 TLV6710 微功耗、36V 窗口比较器
1 特性
3 说明
1
•
高电源电压范围：1.8V 至 36V
可调节阈值：低至 400mV
高阈值精度：
TLV6710 是一款高电压窗口比较器，工作电压范围为
1.8V 至 36V。此器件具有两个内部基准电压为 400mV
的高精度比较器和两个额定电压为 25V 的开漏输出
TLV6710 可以作为一个窗口比较器使用，也可以作为
两个独立的比较器使用。可以使用外部电阻器设定监控
电压。
•
•
–
–
0.25%（典型值）
在工作温度范围内最大值为 0.75%
•
•
•
•
•
低静态电流：7μA（典型值）
漏极开路输出
当 INA+ 上的电压下降至低于 (VITP - VHYS)时，OUTA
被驱动至低电平，当电压返回到相应阈值 (VITP) 之上
时，OUTA 变为高电平。当 INB- 上的电压上升至高于
内部滞后：5.5mV（典型值）
温度范围：-40°C 至 125°C
封装：超薄 SOT-23-6
VITP时，OUTB 被驱动至低电平，当电压下降至低于相
应阈值 (VITP - VHYS) 时，OUTB 变为高电平。
2 应用
TLV6710 中的两个比较器都具有内置迟滞来抑制短时
毛刺脉冲，确保稳定的输出运行，不会引起误触发。
•
•
•
•
•
•
•
•
笔记本电脑和平板电脑
智能手机
TLV6710 采用薄型 SOT-23-6 封装，额定结温范围为
–40°C 至 125°C。
数码相机
视频游戏控制器
中继器和断路器
便携式医疗设备
门窗传感器
器件信息(1)
器件编号
TLV6710
封装
SOT-23 (6)
封装尺寸（标称值）
2.90mm × 1.60mm
便携式和电池供电类产品
(1) 如需了解所有可用封装，请参阅数据表末尾的封装选项附录。
简化框图
VPULL-UP
(Up To 25 V)
1.8 V to 36 V
VDD
OUTA
INA+
OUTB
INB–
Reference
GND
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SNVSAV4
TLV6710
ZHCSHH2B –JANUARY 2018–REVISED OCTOBER 2018
www.ti.com.cn
目录
8.4 Device Functional Modes........................................ 11
Application and Implementation ........................ 12
9.1 Application Information............................................ 12
9.2 Typical Application ................................................. 15
9.3 Do's and Don'ts....................................................... 17
1
2
3
4
5
6
7
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
器件比较表............................................................... 3
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
7.1 Absolute Maximum Ratings ..................................... 4
7.2 ESD Ratings.............................................................. 4
7.3 Recommended Operating Conditions....................... 4
7.4 Thermal Information.................................................. 4
7.5 Electrical Characteristics........................................... 5
7.6 Timing Requirements................................................ 6
7.7 Typical Characteristics.............................................. 7
Detailed Description ............................................ 10
8.1 Overview ................................................................. 10
8.2 Functional Block Diagram ....................................... 10
8.3 Feature Description................................................. 11
9
10 Power Supply Recommendations ..................... 18
11 Layout................................................................... 19
11.1 Layout Guidelines ................................................. 19
11.2 Layout Example .................................................... 19
12 器件和文档支持 ..................................................... 20
12.1 器件支持................................................................ 20
12.2 文档支持................................................................ 20
12.3 接收文档更新通知 ................................................. 20
12.4 社区资源................................................................ 20
12.5 商标....................................................................... 20
12.6 静电放电警告......................................................... 20
12.7 术语表 ................................................................... 20
13 机械、封装和可订购信息....................................... 20
8
4 修订历史记录
Changes from Revision A (April 2018) to Revision B
Page
•
将首页上 简化方框图、说明和应用信息部分的 输出 说明文字 从 36V 更改为 25V。............................................................ 1
Changes from Original (January 2018) to Revision A
Page
•
将“预告信息”更改为“生产数据” ............................................................................................................................................... 1
2
版权 © 2018, Texas Instruments Incorporated
TLV6710
www.ti.com.cn
ZHCSHH2B –JANUARY 2018–REVISED OCTOBER 2018
5 器件比较表
表 1. TLV67xx 集成比较器系列
器件编号
TLV6700
TLV6703
TLV6710
TLV6713
配置
窗口
工作电压范围
1.8V 至 18V
1.8V 至 18V
1.8V 至 36V
1.8V 至 36V
整个温度范围内的精度阈值
1%
1%
同相单通道
窗口
0.75%
0.75%
同相单通道
6 Pin Configuration and Functions
DDC Package
SOT-6
(Top View)
OUTA
GND
INA
1
2
3
6
5
4
OUTB
VDD
INB
Pin Functions
PIN
I/O
DESCRIPTION
NAME
NO.
GND
2
—
I
Ground
Comparator A input. This pin is connected to the voltage to be monitored with the use of an
external resistor divider. When the voltage at this terminal drops below the threshold voltage
VIT–(INA), OUTA is driven low.
INA
INB
3
4
Comparator B input. This pin is connected to the voltage to be monitored with the use of an
external resistor divider. When the voltage at this terminal exceeds the threshold voltage
VIT+(INB), OUTB is driven low.
I
INA comparator open-drain output. OUTA is driven low when the voltage at this comparator
OUTA
OUTB
VDD
1
6
5
O
O
I
is less than VIT–(INA). The output goes high when the sense voltage rises above VIT+(INA)
INB comparator open-drain output. OUTB is driven low when the voltage at this comparator
exceeds VIT+(INB). The output goes high when the sense voltage falls below VIT–(INB)
.
.
Supply voltage input. Connect a 1.8-V to 36-V supply to VDD to power the device. It is good
analog design practice to place a 0.1-µF ceramic capacitor close to this pin.
Copyright © 2018, Texas Instruments Incorporated
3
TLV6710
ZHCSHH2B –JANUARY 2018–REVISED OCTOBER 2018
www.ti.com.cn
7 Specifications
7.1 Absolute Maximum Ratings
Over operating junction temperature range, unless otherwise noted.(1)
MIN
–0.3
–0.3
–0.3
MAX
+40
+28
+7
UNIT
V
VDD
Voltage(2)
VOUTA, VOUTB
V
VINA, VINB
V
Current
Output pin current
Operating junction, TJ
Storage temperature, Tstg
40
mA
°C
°C
–40
–65
+125
+150
Temperature
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are with respect to network ground terminal.
7.2 ESD Ratings
VALUE
±2000
±500
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
V(ESD)
Electrostatic discharge
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating junction temperature range (unless otherwise noted)
MIN
1.8
0
NOM
MAX
36
UNIT
V
VDD
Supply pin voltage
Input pin voltage
VINA, VINB
VOUTA, VOUTB
IOUTA, IOUTB
TJ
1.7
V
Output pin voltage
Output pin current
Junction temperature
0
25
V
0
10
mA
°C
–40
+25
+125
7.4 Thermal Information
TLV6710
DDC (SOT)
6 PINS
201.6
47.8
THERMAL METRIC(1)
UNITS
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
51.2
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.7
ψJB
50.8
RθJC(bot)
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report (SPRA953).
4
Copyright © 2018, Texas Instruments Incorporated
TLV6710
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ZHCSHH2B –JANUARY 2018–REVISED OCTOBER 2018
7.5 Electrical Characteristics
Over the operating temperature range of TJ = –40°C to +125°C, 1.8 V ≤ VDD < 36 V, and pullup resistors RP1,2 = 100 kΩ,
unless otherwise noted. Typical values are at TJ = 25°C and VDD = 12 V.
PARAMETER
Supply voltage range
Power-on reset voltage(1)
TEST CONDITIONS
MIN
TYP
MAX UNIT
VDD
1.8
36
0.8
V
V
V(POR)
VIT–(INA)
VOL ≤ 0.2 V
INA pin negative input threshold voltage VDD = 1.8 V to 36 V
397
400
400
403
413
mV
mV
VIT+(INA) INA pin positive input threshold voltage VDD = 1.8 V to 36 V
405.5
INA pin hysteresis voltage
VHYS(INA)
2
5.5
12
mV
(HYS = VIT+(INA) – VIT–(INA)
)
VIT–(INB)
INB pin negative input threshold voltage VDD = 1.8 V to 36 V
387
397
394.5
400
400
403
mV
mV
VIT+(INB) INB pin positive input threshold voltage VDD = 1.8 V to 36 V
INB pin hysteresis voltage
VHYS(INB)
2
5.2
12
mV
(HYS = VIT+(INB) – VIT–(INB)
)
VDD = 1.8 V, IOUT = 3 mA
130
150
+1
+1
10
250
250
+25
+15
300
11
mV
mV
nA
nA
nA
µA
V
VOL
Low-level output voltage
VDD = 5 V, IOUT = 5 mA
VDD = 1.8 V and 36 V, VINA, VINB = 6.5 V
VDD = 1.8 V and 36 V, VINA, VINB = 0.1 V
VDD = 1.8 V and 36 V, VOUT = 25 V
VDD = 1.8 V – 36 V
–25
–15
IIN
Input current (at INA, INB pins)
ID(leak)
IDD
Open-drain output leakage current
Supply current
Undervoltage lockout(2)
8
UVLO
VDD falling
1.3
1.5
1.7
(1) The lowest supply voltage (VDD) at which output is active; tr(VDD) > 15 µs/V. If less than V(POR), the output is undetermined.
(2) When VDD falls below UVLO, OUTA is driven low and OUTB goes to high impedance. The outputs cannot be determined if less than
V(POR)
.
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ZHCSHH2B –JANUARY 2018–REVISED OCTOBER 2018
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7.6 Timing Requirements
PARAMETER
TEST CONDITION
MIN
TYP
MAX UNIT
VDD = 24 V, ±10-mV input overdrive,
RL = 100 kΩ, VOH = 0.9 × VDD, VOL = 250 mV
.tpd(HL)
tpd(LH)
High-to-low propagation delay(1)
9.9
µs
VDD = 24 V, ±10-mV input overdrive,
RL = 100 kΩ, VOH = 0.9 × VDD, VOL = 250 mV
Low-to-high propagation delay(1)
Startup delay
28.1
155
2.7
µs
µs
µs
(2)
td(start)
tr
VDD = 5 V
VDD = 12 V, 10-mV input overdrive,
RL = 100 kΩ, CL = 10 pF, VO = (0.1 to 0.9) × VDD
Output rise time
VDD = 12 V, 10-mV input overdrive,
RL = 100 kΩ, CL = 10 pF, VO = (0.9 to 0.1) × VDD
tf
Output fall time
0.12
µs
(1) High-to-low and low-to-high refers to the transition at the input pins (INA and INB).
(2) During power on, VDD must exceed 1.8 V for at least 150 µs (typ) before the output state reflects the input condition.
VDD
V(POR)
VIT+(INA)
VITœ(INA)
VHYS
INA
OUTA
tpd(LH)
tpd(HL)
tpd(LH)
VIT+(INB)
VITœ(INB)
VHYS
INB
OUTB
tpd(LH)
tpd(HL)
td(start)
Figure 1. Timing Diagram
6
Copyright © 2018, Texas Instruments Incorporated
TLV6710
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ZHCSHH2B –JANUARY 2018–REVISED OCTOBER 2018
7.7 Typical Characteristics
At TJ = 25°C and VDD = 12 V, unless otherwise noted.
10
8
22
20
18
16
14
12
10
8
INA
INB
6
4
TJ = -40èC
TJ = 0èC
6
2
4
TJ = 25èC
TJ = 85èC
TJ = 125èC
2
0
0
0
6
12
18
24
30
36
0
5
10
15
20
25
30
35
40
45
50
Supply Voltage (V)
Overdrive (%)
D001
D011
VDD = 24 V
Figure 2. Supply Current vs Supply Voltage
Figure 3. Minimum Pulse Duration vs
Threshold Overdrive Voltage(1) (1)
400.2
400.05
399.9
408.5
408
VDD = 1.8 V
VDD = 12 V
VDD = 36 V
407.5
407
406.5
406
399.75
399.6
405.5
405
VDD = 1.8 V
VDD = 12 V
VDD = 36 V
399.45
404.5
404
399.3
-40
-20
0
20
40
60
80
100 120 140
-40
-20
0
20
40
60
80
100 120 140
TJ (èC)
TJ (èC)
D005
D002
Figure 4. INA Positive Input Threshold Voltage (VIT+(INA)) vs
Temperature
Figure 5. INA Negative Input Threshold Voltage (VIT–(INA)) vs
Temperature
400.35
395.7
395.4
395.1
394.8
394.5
394.2
393.9
393.6
VDD = 1.8 V
VDD = 12 V
VDD = 36 V
400.2
400.05
399.9
399.75
399.6
393.3
VDD = 1.8 V
VDD = 12 V
VDD = 36 V
392.7
393
399.45
-40
-20
0
20
40
60
80
100 120 140
-40
-20
0
20
40
60
80
100 120 140
TJ (èC)
TJ (èC)
D004
D003
Figure 6. INB Positive Input Threshold Voltage (VIT+(INB)) vs
Temperature
Figure 7. INB Negative Input Threshold Voltage (VIT–(INB)) vs
Temperature
(1) Minimum pulse duration required to trigger output high-to-low transition. INA = negative spike below VIT– and INB = positive spike above
VIT+
.
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ZHCSHH2B –JANUARY 2018–REVISED OCTOBER 2018
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Typical Characteristics (continued)
At TJ = 25°C and VDD = 12 V, unless otherwise noted.
3500
4500
4000
3500
3000
2500
2000
1500
1000
500
3000
2500
2000
1500
1000
500
0
0
D022
D020
VIT+(INA) Threshold Voltage (mV)
VIT-(INA) Threshold Voltage (mV)
VDD = 1.8 V
VDD = 1.8 V
Figure 8. INA Positive Input Threshold Voltage (VIT+(INA)
)
Figure 9. INA Negative Input Threshold Voltage (VIT–(INA))
Distribution
Distribution
3000
3500
3000
2500
2000
1500
1000
500
2500
2000
1500
1000
500
0
0
D021
D023
VIT+(INB) Threshold Voltage (mV)
VIT-(INB) Threshold Voltage (mV)
VDD = 1.8 V
VDD = 1.8 V
Figure 10. INB Positive Input Threshold Voltage (VIT+(INB)
)
Figure 11. INB Negative Input Threshold Voltage (VIT–(INB)
)
Distribution
Distribution
12
3.3
VDD = 1.8 V, INA to OUTA
VDD = 1.8 V, INA to OUTA
VDD = 36 V, INA to OUTA
VDD = 1.8 V, INB to OUTB
VDD = 36 V, INA to OUTA
VDD = 1.8 V, INB to OUTB
11
3
VDD = 36 V, INB to OUTB
VDD = 36 V, INB to OUTB
10
2.7
9
8
7
6
5
2.4
2.1
1.8
1.5
1.2
-40
-20
0
20
40
60
80
100 120 140
-40
-20
0
20
40
60
80
100 120 140
TJ (èC)
TJ (èC)
D007
D008
Input step ±200 mV
Input step ±200 mV
Figure 12. Propagation Delay vs Temperature
(High-to-Low Transition at the Inputs)
Figure 13. Propagation Delay vs Temperature
(Low-to-High Transition at the Inputs)
8
Copyright © 2018, Texas Instruments Incorporated
TLV6710
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ZHCSHH2B –JANUARY 2018–REVISED OCTOBER 2018
Typical Characteristics (continued)
At TJ = 25°C and VDD = 12 V, unless otherwise noted.
0.6
0.5
0.4
0.3
0.2
0.1
0
TJ = -40èC
TJ = 0èC
TJ = -40èC
TJ = 0èC
TJ = 25èC
TJ = 85èC
TJ = 125èC
0.5
TJ = 25èC
TJ = 85èC
TJ = 125èC
0.4
0.3
0.2
0.1
0
0
1
2
3
4
5
6
7
8
9
10
0
1
2
3
4
5
6
7
8
9
10
IOUT (mA)
IOUT (mA)
D009
D010
VDD = 1.8 V
VDD = 12 V
Figure 14. Output Voltage Low vs Output Sink Current
Figure 15. Output Voltage Low vs Output Sink Current
210
195
180
165
150
135
120
Startup
Delay
Period
VDD (2 V/div)
OUTA (2 V/div)
OUTB (2 V/div)
-40
-20
0
20
40
TJ (èC)
60
80
100 120 140
Time (50 µs/div)
D025
VDD = 5 V, VINA = 390 mV, VINB = 410 mV, VPULLUP = 3.3 V
VDD = 5 V
Figure 17. Start-Up Delay
Figure 16. Start-Up Delay vs Temperature
Startup
Delay
Period
VDD (2 V/div)
OUTA (2 V/div)
OUTB (2 V/div)
Time (50 µs/div)
VDD = 5 V, VINA = 410 mV, VINB = 390 mV, VPULLUP = 3.3 V
Figure 18. Start-Up Delay
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8 Detailed Description
8.1 Overview
The TLV6710 combines two comparators (referred to as A and B) and a precision reference for overvoltage and
undervoltage detection. The TLV6710 features a wide supply voltage range (1.8 V to 36 V) and high-accuracy
window threshold voltages of 400 mV (0.75% over temperature) with built-in hysteresis. The outputs are rated to
25 V and can sink up to 10 mA.
Set each input pin (INA, INB) to monitor any voltage above 0.4 V by using an external resistor divider network.
Each input pin has very low input leakage current, allowing the use of large resistor dividers without sacrificing
system accuracy. To form a window comparator, use the two input pins and three resistors (see the Window
Comparator Considerations section). In this configuration, the TLV6710 is designed to assert the output signals
when the monitored voltage is within the window band. Each input can also be used independently. The
relationship between the inputs and the outputs is shown in Table 2. Broad voltage thresholds are supported that
enable the device to be used in a wide array of applications.
Table 2. Truth Table
CONDITION
INA > VIT+(INA)
INA < VIT–(INA)
INB > VIT+(INB)
INB < VIT–(INB)
OUTPUT
OUTA high
OUTA low
OUTB low
OUTB high
OUTPUT STATE
Output A high impedance
Output A sinking
Output B sinking
Output B high impedance
8.2 Functional Block Diagram
VDD
INA
OUTA
A
OUTB
B
INB
Reference
GND
10
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8.3 Feature Description
8.3.1 Inputs (INA, INB)
The TLV6710 combines two comparators with a precision reference voltage. Each comparator has one external
input; the other input is connected to the internal reference. The rising threshold on INB and the falling threshold
on INA are designed and trimmed to be equal to the reference voltage (400 mV). This configuration optimizes the
device accuracy when used as a window comparator. Both comparators also have built-in hysteresis that proves
immunity to noise and ensures stable operation.
The comparator inputs swings from ground to 1.7 V (7.0 V absolute maximum), regardless of the device supply
voltage used. Although not required in most cases, it is good analog design practice to place a 1-nF to 10-nF
bypass capacitor at the comparator input for noisy applications in order to reduce sensitivity to transient voltage
changes on the monitored signal.
For comparator A, the corresponding output (OUTA) is driven to logic low when the input INA voltage drops
below VIT–(INA). When the voltage exceeds VIT+(INA), OUTA goes to a high-impedance state; see Figure 1.
For comparator B, the corresponding output (OUTB) is driven to logic low when the voltage at input INB exceeds
VIT+(INB). When the voltage drops below VIT–(INB) OUTB goes to a high-impedance state; see Figure 1. Together,
these two comparators form a window-detection function as described in the Window Comparator Considerations
section.
8.3.2 Outputs (OUTA, OUTB)
In a typical TLV6710 application, the outputs are connected to a GPIO input of the processor (such as a digital
signal processor [DSP], central processing unit [CPU], field-programmable gate array [FPGA], or application-
specific integrated circuit [ASIC]).
The TLV6710 provides two open-drain outputs (OUTA and OUTB); use pullup resistors to hold these lines high
when the output goes to a high-impedance state. Connect pullup resistors to the proper voltage rails to enable
the outputs to be connected to other devices at correct interface voltage levels. The TLV6710 outputs can be
pulled up to 25 V, independent of the device supply voltage. To ensure proper voltage levels, give some
consideration when choosing the pullup resistor values. The pullup resistor value is determined by VOL, output
capacitive loading, and output leakage current (ID(leak)). These values are specified in the Electrical
Characteristics table. Use wired-OR logic to merge OUTA and OUTB into one logic signal.
Table 2 and the Inputs (INA, INB) section describe how the outputs are asserted or high impedance. See
Figure 1 for a timing diagram that describes the relationship between threshold voltages and the respective
output.
8.4 Device Functional Modes
8.4.1 Normal Operation (VDD > UVLO)
When the voltage on VDD is greater than 1.8 V for at least 155 µs, the OUTA and OUTB signals correspond to
the voltage on INA and INB as listed in Table 2.
8.4.2 Undervoltage Lockout (V(POR) < VDD < UVLO)
When the voltage on VDD is less than the device UVLO voltage, and greater than the power-on reset voltage,
V(POR), the OUTA and OUTB signals are asserted and high impedance, respectively, regardless of the voltage on
INA and INB.
8.4.3 Power On Reset (VDD < V(POR)
)
When the voltage on VDD is lower than the required voltage to internally pull the asserted output to GND
(V(POR)), both outputs are in a high-impedance state.
Copyright © 2018, Texas Instruments Incorporated
11
TLV6710
ZHCSHH2B –JANUARY 2018–REVISED OCTOBER 2018
www.ti.com.cn
9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The TLV6710 device is a wide-supply voltage window comparator that operates over a VDD range of 1.8 V to
36 V. The device has two high-accuracy comparators with an internal 400-mV reference and two open-drain
outputs rated to 25 V for overvoltage and undervoltage detection. The device can be used either as a
window comparator or as two independent voltage monitors. The monitored voltages are set with the use of
external resistors.
9.1.1 Window Comparator Considerations
The inverting and noninverting configuration of the comparators forms a window-comparator detection circuit
using a resistor divider network, as shown in Figure 19 and Figure 20. The input pins can monitor any system
voltage above 400 mV with the use of a resistor divider network. INA and INB monitor for undervoltage and
overvoltage conditions, respectively.
VMON
1.8 V to 25 V
R1
RP1
(2.21 MW)
VDD
Device
GND
(50 kW)
INA
OUTA
R2
(13.7 kW)
OUT
INB
OUTB
UV VMON OV
R3
(69.8 kW)
Figure 19. Window Comparator Block Diagram
VMON(OV)
Overvoltage
Limit
VMON(OV_HYS)
VMON
VMON(UV_HYS)
VMON(UV)
Undervoltage
Limit
OUTB
OUTA
Figure 20. Window Comparator Timing Diagram
12
Copyright © 2018, Texas Instruments Incorporated
TLV6710
www.ti.com.cn
ZHCSHH2B –JANUARY 2018–REVISED OCTOBER 2018
Application Information (continued)
The TLV6710 flags the overvoltage or undervoltage condition with the greatest accuracy. The highest accuracy
threshold voltages are VIT–(INA) and VIT+(INB), and correspond with the falling undervoltage flag, and the rising
overvoltage flag, respectively. These thresholds represent the accuracy when the monitored voltage is within the
valid window (both OUTA and OUTB are in a high-impedance state), and correspond to the VMON(UV) and
VMON(OV) trigger voltages, respectively. If the monitored voltage is outside of the valid window (VMON is less than
the undervoltage limit, VMON(UV), or greater than overvoltage limit, VMON(OV)), then the input threshold voltages to
re-enter the valid window are VIT+(INA) or VIT–(INB), and correspond with the VMON(UV_HYS) and VMON(OV_HYS)
monitored voltages, respectively.
The resistor divider values and target threshold voltage can be calculated by using Equation 1 through
Equation 4:
RTOTAL = R1 + R2 + R3
(1)
Choose an RTOTAL value so that the current through the divider is approximately 100 times higher than the input
current at the INA and INB pins. Resistors with high values minimize current consumption; however, the input
bias current degrades accuracy if the current through the resistors is too low. See application report Optimizing
Resistor Dividers at a Comparator Input (SLVA450), for details on sizing input resistors.
R3 is determined by Equation 2:
RTOTAL
R3 =
VIT+(INB)
VMON(OV)
where
•
VMON(OV) is the target voltage at which an overvoltage condition is detected.
(2)
R2 is determined by either Equation 3 or Equation 4:
RTOTAL
R2 =
VIT+(INA) - R3
VMON(UV_HYS)
where
•
VMON(UV_HYS) is the target voltage at which an undervoltage condition is removed as VMON rises.
(3)
(4)
RTOTAL
R2 =
VIT-(INA) - R3
VMON(UV)
where
•
VMON(UV) is the target voltage at which an undervoltage condition is detected.
9.1.2 Input and Output Configurations
Figure 21 to Figure 23 show examples of the various input and output configurations.
Copyright © 2018, Texas Instruments Incorporated
13
TLV6710
ZHCSHH2B –JANUARY 2018–REVISED OCTOBER 2018
www.ti.com.cn
Application Information (continued)
VPULLUP
1.8 V to 36 V
(up to 25 V)
VDD
INA
OUTA
Device
OUTB
INB
GND
Figure 21. Interfacing to Voltages Other than VDD
1.8 V to 25 V
VDD
INA
OUTA
Device
INB
OUTB
GND
Figure 22. Monitoring the Same Voltage as VDD
14
Copyright © 2018, Texas Instruments Incorporated
TLV6710
www.ti.com.cn
ZHCSHH2B –JANUARY 2018–REVISED OCTOBER 2018
Application Information (continued)
VMON
1.8 V to 25 V
VDD
R1
INA
OUTA
R2
Device
INB
OUTB
R3
GND
NOTE: The inputs can monitor a voltage higher than VDD (max) with the use of an external resistor divider network.
Figure 23. Monitoring a Voltage Other than VDD
9.1.3 Immunity to Input Pin Voltage Transients
The TLV6710 is immune to short voltage transient spikes on the input pins. Sensitivity to transients depends on
both transient duration and amplitude; see Figure 3, Minimum Pulse Duration vs Threshold Overdrive Voltage.
9.2 Typical Application
VMON
24 V
0.01 ꢀF
+
VPULLUP
3.3 V
œ
2.0 MΩ
6.81 kΩ
30.9 kΩ
VDD
Device
GND
100 kΩ
100 kΩ
INA
INB
OUTA
OUTB
Figure 24. 24-V, 10% Window Comparator
Copyright © 2018, Texas Instruments Incorporated
15
TLV6710
ZHCSHH2B –JANUARY 2018–REVISED OCTOBER 2018
www.ti.com.cn
Typical Application (continued)
9.2.1 Design Requirements
Table 3. Design Parameters
PARAMETER
DESIGN REQUIREMENT
DESIGN RESULT
24-V nominal, rising (VMON(OV)) and
falling (VMON(UV)) threshold
±10% nominal (26.4 V and 21.6 V,
respectively)
Monitored voltage
VMON(OV) = 26.4 V ±2.7%, VMON(UV) = 21.6 V ±2.7%
Output logic voltage
3.3-V CMOS
30 µA
3.3-V CMOS
24 µA
Maximum current consumption
9.2.2 Detailed Design Procedure
1. Determine the minimum total resistance of the resistor network necessary to achieve the current
consumption specification by using Equation 1. For this example, the current flow through the resistor
network was chosen to be 13 µA; a lower current can be selected, however, care should be taken to avoid
leakage currents that are artifacts of the manufacturing process. Leakage currents significantly impact the
accuracy if they are greater than 1% of the resistor network current.
VMON(OV)
26.4 V
RTOTAL
=
=
= 2.03 Mꢀ
I
13 mA
where
•
•
VMON(OV) is the target voltage at which an overvoltage condition is detected as VMON rises.
I is the current flowing through the resistor network.
(5)
2. After RTOTAL is determined, R3 can be calculated using Equation 6. Select the nearest 1% resistor value for
R3. In this case, 30.9 kΩ is the closest value.
RTOTAL
2.03 MW
R3 =
VIT+(INB)
=
0.4 V = 30.7 kW
26.4 V
VMON(OV)
(6)
3. Use Equation 7 to calculate R2. Select the nearest 1% resistor value for R2. In this case, 6.81 kΩ is the
closest value.
RTOTAL
2.03 MW
21.6 V
R2 =
ñ VIT-(INA+) -R3 =
ñ0.4 V -30.9 kꢀ = 6.69 kꢀ
VMON(UV)
(7)
4. Use Equation 8 to calculate R1. Select the nearest 1% resistor value for R1. In this case, 2 MΩ is the closest
value.
R1 =RTOTAL -R2 -R3 = 2.03 Mꢀ-6.81 kꢀ-30.9 kꢀ =1.99 Mꢀ
(8)
5. The worst-case tolerance can be calculated by referring to Equation 13 in application report Optimizing
Resistor Dividers at a Comparator Input (SLVA450). An example of the rising threshold error, VMON(OV), is
given in Equation 9:
≈
’
V
0.4
≈
’
IT+(INB)
% ACC = % TOL(VIT+(INB) ) + 2 • ∆1-
÷• % TOLR= 0.75 % + 2 • 1-
• 1% = 2.72 %
∆
÷
◊
∆
÷
VMON(OV)
26.4
«
«
◊
where
•
•
•
% TOL(VIT+(INB)) is the tolerance of the INB positive threshold.
% ACC is the total tolerance of the VMON(OV) voltage.
% TOLR is the tolerance of the resistors selected.
(9)
6. When the outputs switch to the high-Z state, the rise time of the OUTA or OUTB node depends on the pullup
resistance and the capacitance on the node. Choose pullup resistors that satisfy the downstream timing
requirements; 100-kΩ resistors are a good choice for low-capacitive loads.
9.2.3 Application Curve
16
Copyright © 2018, Texas Instruments Incorporated
TLV6710
www.ti.com.cn
ZHCSHH2B –JANUARY 2018–REVISED OCTOBER 2018
VDD (10 V/div)
OUTA (2 V/div)
OUTB (2 V/div)
Time (5 ms/div)
Figure 25. 24-V Window Monitor Output Response
9.3 Do's and Don'ts
It is good analog design practice to have a 0.1-µF decoupling capacitor from VDD to GND.
If the monitored rail is noisy, connect decoupling capacitors from the comparator inputs to GND.
Do not use resistors for the voltage divider that cause the current through them to be less than 100 times the
input current of the comparators without also accounting for the effect to the accuracy.
Do not use pullup resistors that are too small, because the larger current sunk by the output then exceeds the
desired low-level output voltage (VOL).
Copyright © 2018, Texas Instruments Incorporated
17
TLV6710
ZHCSHH2B –JANUARY 2018–REVISED OCTOBER 2018
www.ti.com.cn
10 Power Supply Recommendations
The TLV6710 has a 40-V absolute maximum rating on the VDD pin, with a recommended operating condition of
36 V. If the voltage supply that is providing power to VDD is susceptible to any large voltage transient that may
exceed 40 V, or if the supply exhibits high voltage slew rates greater than 1 V/µs, take additional precautions.
Place an RC filter between the supply and VDD to filter any high-frequency transient surges on the VDD pin. A
100-Ω resistor and 0.01-µF capacitor is required in these cases, as shown in Figure 26.
100 Ω
0.01 ꢀF
+
œ
VPULLUP
R1
VDD
INA
INB
OUTA
OUTB
R2
R3
GND
Figure 26. Using an RC Filter to Remove High-Frequency Disturbances on VDD
18
Copyright © 2018, Texas Instruments Incorporated
TLV6710
www.ti.com.cn
ZHCSHH2B –JANUARY 2018–REVISED OCTOBER 2018
11 Layout
11.1 Layout Guidelines
•
•
•
Place R1, R2, and R3 close to the device to minimize noise coupling into the INA and INB nodes.
Place the VDD decoupling capacitor close to the device.
Avoid using long traces for the VDD supply node. The VDD capacitor (CVDD), along with parasitic inductance
from the supply to the capacitor, may form an LC tank and create ringing with peak voltages above the
maximum VDD voltage. If this is unavoidable, see Figure 26 for an example of filtering VDD.
11.2 Layout Example
Pullup
Voltage
RP1
RP2
Overvoltage
Flag
Undervoltage
Flag
6
1
CVDD
Input
Supply
5
4
2
3
R1
R2
R3
Monitored
Voltage
Figure 27. Recommended Layout
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19
TLV6710
ZHCSHH2B –JANUARY 2018–REVISED OCTOBER 2018
www.ti.com.cn
12 器件和文档支持
12.1 器件支持
12.1.1 开发支持
DIP 适配器评估模块可以将 SOT-23-6 封装转换为标准 DIP-6 引脚排列以便轻松构建原型和进行工作台评估。
12.2 文档支持
12.2.1 相关文档
请参阅如下相关文档：
《优化比较器输入上的电阻分压器》(SLVA450)
12.3 接收文档更新通知
要接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我 进行注册，即可每周接收产
品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
12.4 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，
并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
设计支持
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。
12.5 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.6 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
12.7 术语表
SLYZ022 — TI 术语表。
这份术语表列出并解释术语、缩写和定义。
13 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。
20
版权 © 2018, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TLV6710DDCR
TLV6710DDCT
ACTIVE SOT-23-THIN
ACTIVE SOT-23-THIN
DDC
DDC
6
6
3000 RoHS & Green
250 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
1I61
1I61
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Jan-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TLV6710DDCR
TLV6710DDCT
SOT-
23-THIN
DDC
DDC
6
6
3000
250
180.0
8.4
3.2
3.2
1.4
4.0
8.0
Q3
SOT-
180.0
8.4
3.2
3.2
1.4
4.0
8.0
Q3
23-THIN
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Jan-2021
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TLV6710DDCR
TLV6710DDCT
SOT-23-THIN
SOT-23-THIN
DDC
DDC
6
6
3000
250
213.0
213.0
191.0
191.0
35.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
DDC0006A
SOT-23 - 1.1 max height
S
C
A
L
E
4
.
0
0
0
SMALL OUTLINE TRANSISTOR
3.05
2.55
1.1
0.7
1.75
1.45
0.1 C
B
A
PIN 1
INDEX AREA
1
6
4X 0.95
1.9
3.05
2.75
4
3
0.5
0.3
0.1
6X
TYP
0.0
0.2
C A B
C
0 -8 TYP
0.25
GAGE PLANE
SEATING PLANE
0.20
0.12
TYP
0.6
0.3
TYP
4214841/C 04/2022
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Reference JEDEC MO-193.
www.ti.com
EXAMPLE BOARD LAYOUT
DDC0006A
SOT-23 - 1.1 max height
SMALL OUTLINE TRANSISTOR
SYMM
6X (1.1)
1
6
6X (0.6)
SYMM
4X (0.95)
4
3
(R0.05) TYP
(2.7)
LAND PATTERN EXAMPLE
EXPLOSED METAL SHOWN
SCALE:15X
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
SOLDERMASK DETAILS
4214841/C 04/2022
NOTES: (continued)
4. Publication IPC-7351 may have alternate designs.
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DDC0006A
SOT-23 - 1.1 max height
SMALL OUTLINE TRANSISTOR
SYMM
6X (1.1)
1
6
6X (0.6)
SYMM
4X(0.95)
4
3
(R0.05) TYP
(2.7)
SOLDER PASTE EXAMPLE
BASED ON 0.125 THICK STENCIL
SCALE:15X
4214841/C 04/2022
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.
www.ti.com
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Copyright © 2022，德州仪器 (TI) 公司
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