TLV6742IDSGR_技术文档

TLV6741, TLV6742

SBOS817I – JUNE 2017 – REVISED AUGUST 2021

TLV6741, TLV6742, TLV6744 10-MHz, Low Broadband Noise, RRO, Operational

Amplifier

1 Features

3 Description

•

Low broadband noise: 3.5 nV/√Hz

Gain bandwidth: 10 MHz

Low input bias current: ±3 pA

Low offset voltage: 0.15 mV

Low offset voltage drift: ±0.2 µV/°C

Rail-to-rail output

Unity-gain stable

Low I_Q:

– TLV6741: 890 µA/ch

– TLV6742/4: 990 µA/ch

Wide supply range:

The TLV674x family includes single (TLV6741), dual

(TLV6742), and quad-channel (TLV6744) general-

purpose CMOS operational amplifiers (op amp) that

provide a low noise figure of 3.5 nV/√Hz and a

wide bandwidth of 10 MHz. The low noise and

wide bandwidth make the TLV674x family of devices

attractive for a variety of precision applications

that require a good balance between cost and

performance. Additionally, the input bias current of the

TLV674x family supports applications with high source

impedance.

•

– TLV6741: 2.25 V to 5.5 V

– TLV6742/4: 1.7 V to 5.5 V

Robust EMIRR performance: 71 dB at 2.4 GHz

The robust design of the TLV674x family provides

ease-of-use to the circuit designer due to its unity-gain

stability, integrated RFI/EMI rejection filter, no phase

reversal in overdrive conditions and high electrostatic

discharge (ESD) protection (2-kV HBM). Additionally,

the resistive open-loop output impedance makes them

easy to stabilize with much higher capacitive loads.

2 Applications

•

Solid state drive

Wearables (non-medical)

Professional audio amplifier (rack mount)

Transimpedance Amplifier Circuit

Test and measurement

Motor drives

This op amp family is optimized for low-voltage

operation as low as 2.25 V (±1.125 V) for the

TLV6741 and 1.7 V (±0.85 V) for the TLV6742 and

TLV6744. All of the devices operate up to 5.5 V (±2.75

V), and are specified over the temperature range of

–40°C to 125°C.

Pressure transmitter

Lab and field instrumentation

Bridge amplifier circuit

Gaming applications

The single-channel TLV6741 is available in a small-

size SC70-5 package. The dual-channel TLV6742 is

available in multiple package options including a tiny

1.5 mm × 2.0 mm X2QFN package.

100

70

50

Device Information

30

20

PART NUMBER⁽¹⁾

PACKAGE

BODY SIZE (NOM)

1.25 mm × 2.00 mm

3.91 mm × 4.90 mm

3.00 mm × 4.40 mm

3.00 mm × 3.00 mm

1.60 mm × 2.90 mm

2.00 mm × 2.00 mm

1.50 mm × 2.00 mm

TLV6741

SC70 (5)

10

7

SOIC (8)

TSSOP (8)

VSSOP (8)

SOT-23 (8)

WSON (8)

X2QFN (10)

5

TLV6742

3

2

TLV6742S

1

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

10

100

1k

Frequency (Hz)

10k

100k

D012

Noise Spectral Density vs Frequency

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

TLV6741, TLV6742

SBOS817I – JUNE 2017 – REVISED AUGUST 2021

www.ti.com

Table of Contents

1 Features............................................................................1

2 Applications.....................................................................1

3 Description.......................................................................1

4 Revision History.............................................................. 2

5 Device Comparison Table...............................................4

6 Pin Configuration and Functions...................................5

7 Specifications.................................................................. 7

7.1 Absolute Maximum Ratings ....................................... 7

7.2 ESD Ratings .............................................................. 7

7.3 Recommended Operating Conditions ........................7

7.4 Thermal Information for Single Channel .................... 7

7.5 Thermal Information for Dual Channel .......................8

7.6 Electrical Characteristics ............................................9

7.7 TLV6741: Typical Characteristics..............................12

7.8 TLV6742: Typical Characteristics..............................18

8 Detailed Description......................................................26

8.1 Overview...................................................................26

8.2 Functional Block Diagram.........................................26

8.3 Feature Description...................................................26

8.4 Device Functional Modes..........................................31

9 Application and Implementation..................................32

9.1 Application Information............................................. 32

9.2 Single-Supply Electret Microphone Preamplifier

With Speech Filter.......................................................32

10 Power Supply Recommendations..............................35

11 Layout...........................................................................36

11.1 Layout Guidelines................................................... 36

11.2 Layout Example...................................................... 37

12 Device and Documentation Support..........................39

12.1 Documentation Support.......................................... 39

12.2 Receiving Notification of Documentation Updates..39

12.3 Support Resources................................................. 39

12.4 Trademarks.............................................................39

12.5 Electrostatic Discharge Caution..............................39

12.6 Glossary..................................................................39

13 Mechanical, Packaging, and Orderable

Information.................................................................... 40

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision H (February 2021) to Revision I (August 2021)

Page

•

Removed preview tag from TLV6742 VSSOP in Device Information section ....................................................1

Removed preview tag to VSSOP (DGK) in Device Comparison Table section.................................................. 4

Changes from Revision G (April 2020) to Revision H (February 2021)

Page

•

Updated the numbering format for tables, figures, and cross-references throughout the document..................1

Removed preview tag from TLV6742S X2QFN in Device Information section ..................................................1

Removed preview note from X2QFN for TLV6742S in Pin Configuration and Functions section...................... 5

Removed Table of TLV6741 Graphs and Table of TLV6742 Graphs tables from the Specifications section....12

Removed Related Links section from the Device and Documentation Support section...................................39

Changes from Revision F (January 2020) to Revision G (April 2020)

Page

•

Added end equipment links in Application section..............................................................................................1

Deleted preview tags for TSSOP, SOT-23, WSON, and X2QFN packages in Device Information section ....... 1

Deleted VSSOP (8) package in Device Information section ..............................................................................1

Added preview tag to TLV6742S X2QFN in Device Information section ........................................................... 1

Deleted VSSOP (DGK) in Device Comparison Table section.............................................................................4

Added preview tag to X2QFN (RUG) in Device Comparison Table section....................................................... 4

Deleted DGK package in pinout drawing for TLV6742 package in Pin Configuration and Functions section.... 5

Deleted DGK VSSOP in Thermal Information for Dual Channel section............................................................7

Added shutdown electrical characteristic information........................................................................................9

Deleted example layout for VSSOP-8 (DGK) package in Layout Example section..........................................37

Changes from Revision E (December 2019) to Revision F (January 2020)

Page

•

Deleted TLV6744 product folder link from the data sheet page header............................................................. 1

2

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Changes from Revision D (January 2019) to Revision E (December 2019)

Page

•

Added I_Qdefinition for TLV6742 and TLV744 in Features section......................................................................1

Added EMIRR, Supply Range, I_Q, and Offset Voltage Drift to Features section................................................ 1

Changed Noise Spectral Density vs Frequency plot on front page to the TLV6742 and TLV6744 noise plot.... 1

Changed wording of Description section to incorporate release of TLV6742 and TLV6744 devices .................1

Changed TLV6742 packages in Device Information ..........................................................................................1

Added Device Comparison Table section...........................................................................................................4

Added note regarding single supply operation to Pin Functions: TLV6741 table............................................... 5

Added pin out drawings for TLV6742 packages in Pin Configuration and Functions section.............................5

Added pin functions for TLV6742 packages....................................................................................................... 5

Added X2QFN Package Drawing and Pin Functions for TLV6742S in Pin Configuration and Functions section

............................................................................................................................................................................5

Added TLV6742 typical characteristic graphs in the Specifications section..................................................... 12

Changed wording throughout Detailed Description section to incorporate addition of TLV6742 and TLV6744

devices..............................................................................................................................................................26

Added EMI Rejection section with description information to Detailed Description section............................. 27

Added Electrical Overstress section and diagram to Detailed Description section.......................................... 28

Added Typical Specification and Distributions section to Detailed Description section.................................... 29

Added Shutdown Function section with description for TLV6742S to Detailed Description section.................30

Added Packages With an Exposed Thermal Pad section to Detailed Description section...............................30

Changed wording in Application and Implementation section to include the addition of TLV6742 and TLV6744

..........................................................................................................................................................................32

Added TLV6742 and TLV6744 information to Power Supply Recommendations section................................ 35

Added dual channel layout example in the Layout section...............................................................................37

•

Changes from Revision C (October 2017) to Revision D (January 2019)

Page

Changed Operating temperature from 125 to 150 in Absolute Maximum Ratings ........................................... 7

Added Junction temperature spec to Absolute Maximum Ratings .................................................................... 7

•

Changes from Revision B (October 2017) to Revision C (October 2017)

Page

•

Added test conditions to input offset voltage parameter in Electrical Characteristics table................................9

Changed typical input current noise density value from 2 fA√HZ to 23 fA√Hz................................................... 9

Changed total supply voltage total from 5V to 5.5V in Electrical Characteristics condition statement............... 9

Deleted "Vs = 2.25 V to 5.5 V" test conditions for common-mode rejection ratio parameter in Electrical

Characteristics ...................................................................................................................................................9

Deleted "C_L= 0" test condition from Figure 7-25 and Figure 7-26, Figure 7-27 and Figure 7-28 ....................12

Changed voltage step from 5 V to 2 V in Figure 7-32 ......................................................................................12

•

Changes from Revision A (September 2017) to Revision B (October 2017)

Changed Human-body model (HBM) value from: ±1000 to ±3000 and Charged-device mode (CDM) value

from ±250 to ±1000.............................................................................................................................................7

Page

•

Changes from Revision * (June 2017) to Revision A (September 2017)

Page

•

Changed device document status from: Advance Information to: Production Data........................................... 1

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5 Device Comparison Table

PACKAGE LEADS

NO. OF

DEVICE

SOIC

D

SC-70

DCK

VSSOP

DGK

WSON

DSG

TSSOP

PW

SOT-23

DDF

X2QFN

RUG

CHANNELS

TLV6741

TLV6742

TLV6742S

1

2

—

8

5

—

8

—

8

—

8

—

8

—

10

—

4

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6 Pin Configuration and Functions

IN+

Vœ

1

2

3

5

V+

INœ

4

OUT

Not to scale

Figure 6-1. TLV6741 DCK Package

5-Pin SC70

Top View

Table 6-1. Pin Functions: TLV6741

I/O

DESCRIPTION

NAME

IN+

NO.

1

I

Noninverting input

Inverting input

IN–

3

I

OUT

V+

4

O

—

Output

5

Positive (highest) supply

V–

2

Negative (lowest) supply or ground (for single-supply operation)

OUT1

1

2

3

4

8

7

6

5

V+

OUT1

IN1œ

IN1+

Vœ

1

2

3

4

8

7

6

5

V+

IN1œ

IN1+

Vœ

OUT2

IN2œ

IN2+

OUT2

IN2œ

IN2+

Thermal

Pad

Not to scale

Figure 6-2. TLV6742 D, DGK, PW, and DDF Package

8-Pin SOIC, VSSOP, TSSOP, and SOT-23

Top View

Connect thermal pad to V–. See Section 8.3.8 for more

information.

Figure 6-3. TLV6742 DSG Package

8-Pin WSON With Exposed Thermal Pad

Top View

Table 6-2. Pin Functions: TLV6742

I/O

DESCRIPTION

NAME

IN1–

NO.

2

I

Inverting input, channel 1

IN1+

IN2–

3

Noninverting input, channel 1

Inverting input, channel 2

Noninverting input, channel 2

Output, channel 1

6

I

IN2+

OUT1

OUT2

5

I

1

O

7

Output, channel 2

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Table 6-2. Pin Functions: TLV6742 (continued)

I/O

DESCRIPTION

NAME

NO.

4

V–

V+

—

Negative (lowest) supply or ground (for single-supply operation)

Positive (highest) supply

8

Vœ

SHDN1

SHDN2

IN2+

1

2

3

4

9

8

7

6

IN1œ

OUT1

V+

OUT2

Not to scale

Figure 6-4. TLV6742S RUG Package

10-Pin X2QFN

Top View

Table 6-3. Pin Functions: TLV6742S

I/O

DESCRIPTION

NAME

NO.

IN1–

IN1+

IN2–

IN2+

OUT1

OUT2

9

10

5

I

Inverting input, channel 1

Noninverting input, channel 1

Inverting input, channel 2

Noninverting input, channel 2

Output, channel 1

I

4

I

8

O

6

Output, channel 2

Shutdown: low = amp disabled, high = amp enabled. Channel 1. See Section 8.3.7 for more

information.

SHDN1

SHDN2

2

3

I

Shutdown: low = amp disabled, high = amp enabled. Channel 2. See Section 8.3.7 for more

information.

V–

V+

1

7

I or —

I

Negative (lowest) supply or ground (for single-supply operation)

Positive (highest) supply

6

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7 Specifications

7.1 Absolute Maximum Ratings

over operating ambient temperature range (unless otherwise noted) ⁽¹⁾

MIN

0

MAX

6

UNIT

V

Supply voltage, V_S= (V+) – (V–)

Common-mode voltage ⁽³⁾

(V–) – 0.5

(V+) + 0.5

V_S+ 0.2

10

V

Signal input pins

Differential voltage ^{(3) (4)}

Current ⁽³⁾

V

–10

–55

–65

mA

Output short-circuit ⁽²⁾

Continuous

Operating ambient temperature, T_A

Junction temperature, T_J

Storage temperature, T_stg

150

°C

(1) Operating the device beyond the ratings listed under Absolute Maximum Ratings will cause permanent damage to the device.

These are stress ratings only, based on process and design limitations, and this device has not been designed to function outside

the conditions indicated under Recommended Operating Conditions. Exposure to any condition outside Recommended Operating

Conditions for extended periods, including absolute-maximum-rated conditions, may affect device reliability and performance.

(2) Short-circuit to ground, one amplifier per package.

(3) Input pins are diode-clamped to the power-supply rails. Input signals that may swing more than 0.5 V beyond the supply rails must be

current limited to 10 mA or less.

(4) Differential input voltages greater than 0.25 V applied continuously can result in a shift to the input offset voltage above the maximum

specification of this parameter. The magnitude of this effect increases as the ambient operating temperature rises.

7.2 ESD Ratings

VALUE

±3000

±2000

UNIT

TLV6741: Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 ⁽¹⁾

TLV6742: Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 ⁽¹⁾

V_(ESD)

Electrostatic discharge

V

All Devices: Charged-device model (CDM), per JEDEC specification JESD22-C101

±1500

(2)

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating ambient temperature range (unless otherwise noted)

MIN

1.7⁽¹⁾

2.25

(V–)

–40

MAX

UNIT

V_S

V_I

Supply voltage, (V+) – (V–) , for TLV6742 and TLV6744

Supply voltage, (V+) – (V–), for TLV6741 only

Input voltage range

5.5

V

(V+) – 1.2

125

V

T_A

Specified temperature

°C

(1) Operation between 1.7V and 1.8V is only recommened for T_A= 0 - 85 ℃

7.4 Thermal Information for Single Channel

THERMAL METRIC ⁽¹⁾

TLV6741

DCK

(SC70)

UNIT

5 PINS

240.9

151.7

64

R_θJA

R_θJC(top)

R_θJB

ψ_JT

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

℃/W

Junction-to-top characterization parameter

Junction-to-board characterization parameter

34.8

ψ_JB

63.3

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7.4 Thermal Information for Single Channel (continued)

TLV6741

DCK

(SC70)

THERMAL METRIC ⁽¹⁾

UNIT

5 PINS

R_θJC(bot)

Junction-to-case (bottom) thermal resistance

n/a

℃/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report SPRA953C.

7.5 Thermal Information for Dual Channel

TLV6742, TLV6742S

D

DDF

(SOT-23-8)

DSG

(WSON)

PW

(TSSOP)

DGK

(VSSOP)

RUG

(X2QFN)

THERMAL METRIC ⁽¹⁾

UNIT

(SOIC)

8 PINS

10 PINS

Junction-to-ambient thermal

resistance

R_θJA

131.1

153.8

78.2

185.6

177.0

140.3

°C/W

Junction-to-case (top) thermal

resistance

R_θJC(top)

R_θJB

73.2

74.5

24.4

73.3

n/a

80.2

73.1

6.6

97.5

44.6

4.7

74.5

116.3

12.6

114.6

n/a

68.6

98.7

12.4

97.1

n/a

52.6

69.7

1.0

Junction-to-board thermal

resistance

Junction-to-top

characterization parameter

ψ_JT

Junction-to-board

characterization parameter

ψ_JB

72.7

n/a

44.6

19.8

67.5

n/a

Junction-to-case (bottom)

thermal resistance

R_θJC(bot)

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report, SPRA953C.

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7.6 Electrical Characteristics

TLV6742/4 Specifications: V_S= (V+) – (V–) = 1.8 V to 5.5 V (±0.9 V to ±2.75 V) at T_A= 25°C, R_L= 10 kΩ connected to V_S/

2, V_CM= V_S/ 2, and V_{O UT}= V_S/ 2, unless otherwise noted.

TLV6741 Specifications: V_S= (V+) – (V–) = 5.5 V at T_A= 25°C, R_L= 10 kΩ connected to V_S/ 2, V_CM= V_S/ 2, and V_{O UT}

=

V_S/ 2, unless otherwise noted.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

OFFSET VOLTAGE

±0.15

±1.0

±1.2

V_OS

Input offset voltage

V_S= 5.0 V

mV

T_A= –40°C to 125°C

TLV6742/4⁽³⁾

TLV6741⁽²⁾

±0.35

±0.2

±0.32

±0.7

130

dV_OS/dT

PSRR

Input offset voltage drift

µV/℃

TLV6742/4⁽³⁾

TLV6741⁽²⁾

V_CM= V–

f = 20 kHz

±6.3

±5.8

Input offset voltage

versus power supply

μV/V

dB

TLV6742/4⁽³⁾

Channel separation

INPUT BIAS CURRENT

TLV6741⁽²⁾

TLV6742/4⁽³⁾

TLV6741⁽²⁾

TLV6742/4⁽³⁾

±10

±3

I_B

Input bias current

pA

±10

±0.5

I_OS

Input offset current

Input voltage noise

NOISE

E_N

1.2

0.227

30

μV_PP

f = 0.1 to 10 Hz

f = 10 Hz

µV_RMS

TLV6742/4⁽³⁾

TLV6741⁽²⁾

5.0

f = 1 kHz

Input voltage noise

density

e_N

TLV6742/4⁽³⁾

TLV6741⁽²⁾

4.6

nV/√Hz

3.7

f = 10 kHz

f = 1 kHz

TLV6742/4⁽³⁾

3.5

i_N

Input current noise

23

fA/√Hz

V

INPUT VOLTAGE RANGE

Common-mode voltage

range

V_CM

(V–)

(V+) -1.2

(V–) < V_CM< (V+) – 1.2 V

TLV6741⁽²⁾

95

87

94

120

100

110

Common-mode

rejection ratio

CMRR

V_S= 1.8 V, (V–) < V_CM< (V+) – 1.2 V

V_S= 5.5, (V–) < V_CM< (V+) – 1.2 V

dB

TLV6742/4⁽³⁾

INPUT CAPACITANCE

Z_ID

Differential

10 || 6

MΩ || pF

GΩ || pF

Z_ICM

Common-mode

OPEN-LOOP GAIN

(V–) + 40 mV < V_O< (V+) – 40 mV, R_L= 10 kΩ to

V_S/2

125

130

120

140

120

140

TLV6741⁽²⁾

(V–) + 150 mV < V_O< (V+) – 150 mV, R_L= 2 kΩ

to V_S/2

110

107

V_S= 1.8 V, (V–) + 150 mV < V_O< (V+) – 150 mV,

R_L= 2 kΩ to V_S/2

A_OL

Open-loop voltage gain

dB

V_S= 5.5 V, (V–) + 150 mV < V_O< (V+) – 150 mV,

R_L= 2 kΩ to V_S/2

TLV6742/4⁽³⁾

V_S= 1.8 V, (V–) + 40m V < V_O< (V+) – 40 mV, R_L

= 10 kΩ to V_S/2

110

V_S= 5.5 V, (V–) + 40m V < V_O< (V+) – 40 mV, R_L

= 10 kΩ to V_S/2

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7.6 Electrical Characteristics (continued)

TLV6742/4 Specifications: V_S= (V+) – (V–) = 1.8 V to 5.5 V (±0.9 V to ±2.75 V) at T_A= 25°C, R_L= 10 kΩ connected to V_S/

2, V_CM= V_S/ 2, and V_{O UT}= V_S/ 2, unless otherwise noted.

TLV6741 Specifications: V_S= (V+) – (V–) = 5.5 V at T_A= 25°C, R_L= 10 kΩ connected to V_S/ 2, V_CM= V_S/ 2, and V_{O UT}

=

V_S/ 2, unless otherwise noted.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

FREQUENCY RESPONSE

GBW

SR

Gain-bandwidth product

10

MHz

V/μs

Slew rate

V_S= 5.5 V, G = +1, C_L= 20 pF

4.5

To 0.1%, V_S= 5.5 V, V_STEP= 2 V, G = +1, CL =

20pF

0.65

1.2

t_S

Settling time

μs

To 0.01%, V_S= 5.5 V, V_STEP= 2 V, G = +1, CL =

20pF

Phase margin

G = +1, R_L= 10kΩ, C_L= 20 pF

55

0.2

°

Overload recovery time V_IN× gain > V_S

μs

TLV6741⁽²⁾

0.00035%

0.00015%

Total harmonic

distortion + noise

V_S= 5.5 V, V_CM= 2.5 V, V_O= 1 V_RMS, G = +1, f =

THD+N

TLV6742/4⁽³⁾

1 kHz, R_L= 10 kΩ

f = 1 GHz

Electro-magnetic

interference rejection

ratio

EMIRR

TLV6742/4⁽³⁾

TLV6741⁽²⁾

51

dB

OUTPUT

Positive/Negative rail

headroom

V_S= 5.5 V, R_L= 10k

8

10

V_S= 5.5 V, R_L= no load

V_S= 5.5 V, R_L= 2 kΩ

V_S= 5.5 V, R_L= 10 kΩ

V_S= 5.5 V, R_L= no load

7

35

14

7

Positive rail headroom

Voltage output swing

from rail

mV

5

TLV6742/4⁽³⁾

Negative rail headroom V_S= 5.5 V, R_L= 2 kΩ

V_S= 5.5 V, R_L= 10 kΩ

35

14

5

I_SC

Short-circuit current

Capacitive load drive

±68

mA

Ω

See Figure

7-58

C_LOAD

f = 10 MHz, I_O= 0 A

f = 2 MHz, I_O= 0 A

TLV6741⁽²⁾

160

165

Open-loop output

impedance

Z_O

TLV6742/4⁽³⁾

POWER SUPPLY

890

990

10

TLV6741⁽²⁾

T_A= –40°C to 125°C

V_S= 5.5 V, I_O= 0 A

1100

1200

1250

Quiescent current per

amplifier

I_Q

µA

μs

TLV6742/4⁽³⁾

T_A= –40°C to 125°C

Turn-On Time

At T_A= 25°C, V_S= 5.5 V, V_Sramp rate > 0.3 V/µs TLV6742/4⁽³⁾

10

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7.6 Electrical Characteristics (continued)

TLV6742/4 Specifications: V_S= (V+) – (V–) = 1.8 V to 5.5 V (±0.9 V to ±2.75 V) at T_A= 25°C, R_L= 10 kΩ connected to V_S/

2, V_CM= V_S/ 2, and V_{O UT}= V_S/ 2, unless otherwise noted.

TLV6741 Specifications: V_S= (V+) – (V–) = 5.5 V at T_A= 25°C, R_L= 10 kΩ connected to V_S/ 2, V_CM= V_S/ 2, and V_{O UT}

=

V_S/ 2, unless otherwise noted.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

SHUTDOWN

Quiescent current per

amplifier

I_QSD

All amplifiers disabled, SHDN = V–

1

3.5

µA

Output impedance

during shutdown

Z_SHDN

Amplifier disabled

10 || 6

GΩ || pF

Logic high threshold

voltage (amplifier

enabled)

(V–) + 1.1

V

V_IH

V

Logic low threshold

voltage (amplifier

disabled)

(V–) + 0.2

V

V_IL

Amplifier enable time

(full shutdown) ⁽¹⁾

G = +1, V_CM= V-, V_O= 0.1 × V_S/2

15

8

t_ON

Amplifier enable time

(partial shutdown)⁽¹⁾

µs

t_OFF

Amplifier disable time ⁽¹⁾V_CM= V-, V_O= V_S/2

3

0.4

(V+) ≥ SHDN ≥ (V–) + 0.9 V

(V–) ≤ SHDN ≤ (V–) + 0.7 V

SHDN pin input bias

current (per pin)

µA

0.25

(1) Disable time (t_OFF) and enable time (t_ON) are defined as the time interval between the 50% point of the signal applied to the SHDN pin

and the point at which the output voltage reaches the 10% (disable) or 90% (enable) level.

(2) This electrical characteristic only applies to the single-channel, TLV6741

(3) This electrical characteristic only applies to the dual-channel TLV6742 and quad-channel TLV6744

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7.7 TLV6741: Typical Characteristics

at T_A= 25°C, V_S= 5.5 V, R_L= 10 kΩ connected to V_S/ 2, V_CM= V_S/ 2, and V_OUT= V_S/ 2, unless otherwise noted.

40%

80

70

60

50

40

30

20

10

0

35%

30%

25%

20%

15%

10%

5%

0

0.4

0.8

1.2

Offset Voltage Drift (mV/èC)

Figure 7-2. Offset Voltage Drift Distribution

1.6

2

2.4

2.8

D001

D002

Offset Voltage(µV)

Figure 7-1. Offset Voltage Production Distribution

200

6

100

0

4

2

-100

-200

-300

-400

0

-2

-4

-6

-60 -40 -20

0

20

40

60

80 100 120 140

-4

-3

-2

-1

0

Input Common Mode Voltage (V)

1

2

3

4

Temperature (èC)

D003

D004

Figure 7-3. Offset Voltage vs Temperature

Figure 7-4. Offset Voltage vs Common-Mode Voltage

0.5

0.4

0.3

0.2

0.1

0

300

200

100

0

-100

-200

-300

-400

-500

-0.1

-0.2

-0.3

-0.4

-0.5

-2.5

-2

-1.5

-1

-0.5

0

0.5

Input Common Mode Voltage (V)

1

1.5

2

1.5

2.5

3.5

V_S(V)

4.5

5.5

D004

D005

Figure 7-5. Offset Voltage vs Common-Mode Voltage

Figure 7-6. Offset Voltage vs Power Supply

12

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7.7 TLV6741: Typical Characteristics (continued)

at T_A= 25°C, V_S= 5.5 V, R_L= 10 kΩ connected to V_S/ 2, V_CM= V_S/ 2, and V_OUT= V_S/ 2, unless otherwise noted.

8

6

20

0

I_B-

I_B+

I_OS

I_B-

I_B+

I_OS

4

-20

-40

-60

-80

-100

-120

2

0

-2

-4

-6

-8

-4

-3

-2

-1

0

V_CM(V)

1

2

3

4

0

50

100

Temperature (èC)

150

D043

D044

Figure 7-7. I_Band I_OSvs Common-Mode Voltage

Figure 7-8. I_Band I_OSvs Temperature

100

75

40

30

75

50

25

0

20

50

10

25

0

-10

-20

-30

-40

-25

-50

-75

-25

-50

-75

Gain = -1

Gain = 10

Gain = +1

Gain

Phase

1k

10k

100k

Frequency (Hz)

1M

10M

1k

10k

100k

Frequency (Hz)

1M

10M

D006

D007

Figure 7-10. Closed-Loop Gain vs Frequency

C_L= 10 pF

Figure 7-9. Open-Loop Gain and Phase vs Frequency

120

100

80

60

40

20

0

3

PSRR- (dB)

PSRR+ (dB)

2.5

2

1.5

-40°C

125°C

25°C

1

0.5

0

85°C

-0.5

-1

85°C

25°C

-40°C

125°C

-1.5

-2

-2.5

-3

1k

10k

100k

1M

10

15

20

25

30

35

40

Output Current (mA)

45

50

55

60

Frequency (Hz)

D011

D010

Figure 7-12. PSRR vs Frequency (Referred to Input)

Figure 7-11. V_Ovs I Sourcing and Sinking

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7.7 TLV6741: Typical Characteristics (continued)

at T_A= 25°C, V_S= 5.5 V, R_L= 10 kΩ connected to V_S/ 2, V_CM= V_S/ 2, and V_OUT= V_S/ 2, unless otherwise noted.

120

110

100

90

80

70

60

50

40

30

20

10

0

10

5

0

-5

-10

1k

10k

100k

1M

-50

0

50

Temperature (èC)

100

150

Frequency (Hz)

D011

D012

Figure 7-13. CMRR vs Frequency (Referred to Input)

V_S= 5.5 V, T_A= –40°C to 125°C, V_CM= 0 V to 4.3 V

Figure 7-14. CMRR vs Temperature

100

10

1

10

100

1k

Frequency (Hz)

10k

100k

Time (1 s/div)

D015

D014

Figure 7-16. Input Voltage Noise Spectral Density vs Frequency

Figure 7-15. 0.1-Hz to 10-Hz Flicker Noise

-95

-97

-99

-97

-99

-101

-103

-105

-101

-103

-105

100

1k

Frequency (Hz)

10k

100

1k

Frequency (Hz)

10k

D017

V_S= 5.5 V, V_ICM= 2.5 V, R_L= 2 kΩ,

V_S= 5.5 V, V_ICM= 2.5 V, R_L= 10 kΩ,

Gain = 1, BW = 80 kHz, V_OUT= 0.5 Vrms

Figure 7-17. THD + N vs Frequency

Figure 7-18. THD + N vs Frequency

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7.7 TLV6741: Typical Characteristics (continued)

at T_A= 25°C, V_S= 5.5 V, R_L= 10 kΩ connected to V_S/ 2, V_CM= V_S/ 2, and V_OUT= V_S/ 2, unless otherwise noted.

0

1000

950

900

850

800

750

700

650

600

550

500

Gain = +1, R_L= 2 kW

Gain = +1, R_L= 10 kW

Gain = -1, R_L= 2 kW

Gain = -1, R_L= 10 kW

-20

-40

-60

-80

-100

-120

0.001

0.01

0.1

V_OUT(rms)

1

5

1.5

2

2.5

3

3.5

4

Supply Voltage (V)

4.5

5

5.5

D018

D020

V_S= 5.5 V, V_ICM= 2.5 V,

Figure 7-20. Quiescent Current vs Supply Voltage

BW = 80 kHz, V_OUT= 0.5 Vrms

Figure 7-19. THD + N vs Amplitude

1000

950

10

A_VDD= 5.5 V

A_VDD= 1.8 V

9

8

7

6

5

4

3

2

1

0

900

850

800

750

700

650

600

550

500

-50

0

50

Temperature (èC)

100

150

-60 -40 -20

0

20

40

60

80 100 120 140

Temperature (èC)

D021

D022

Figure 7-21. Quiescent Current vs Temperature

R_L= 2 kΩ

Figure 7-22. Open-Loop Gain vs Temperature

1000

100

10

200

160

120

80

40

0

0.5

1

1.5

2

2.5

3

3.5

4

4.5

5

5.5

1k

10k

100k

Frequency (Hz)

1M

10M

Output Voltage (V)

C023

D024

Figure 7-23. Open-Loop Gain vs Output Voltage

A_VDD= 5.5 V, V_ICM= V_OCM= 2.75 V

Figure 7-24. Open-Loop Output Impedance vs Frequency

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7.7 TLV6741: Typical Characteristics (continued)

at T_A= 25°C, V_S= 5.5 V, R_L= 10 kΩ connected to V_S/ 2, V_CM= V_S/ 2, and V_OUT= V_S/ 2, unless otherwise noted.

50

40

30

20

10

0

50

40

30

20

10

0

Overshoot (+)

Overshoot (-)

Overshoot (+)

Overshoot (-)

0

10

20

30

40

Capacitive Load (pF)

50

60

70

80

90 100

0

10

20

30

40

Capacitance (pF)

50

60

70

80

90 100

D025

V_S= 5.5 V, V_ICM= 2.75 V,

V_OCM= 2.75 V, G = 1, 100-mV output step

V_S= 1.8 V, V_ICM= 0.9 V

V_OCM= 0.9 V, G = 1, 100-mV output step

Figure 7-25. Small-Signal Overshoot vs Load Capacitance

Figure 7-26. Small-Signal Overshoot vs Load Capacitance

50

40

30

20

10

40

30

20

10

Overshoot (+)

Overshoot (-)

Overshoot (+)

Overshoot (-)

0

10

20

30

40

Capacitive Load (pF)

50

60

70

80

90 100

0

10

20

30

40

Capacitance (pF)

50

60

70

80

90 100

D025

V_S= 5.5 V, V_ICM= 2.75 V,

V_OCM= 2.75 V, Gain = –1, 100-mV output step

V_S= 1.8 V, V_ICM= 0.9 V

V_OCM= 0.9 V, Gain = –1, 100-mV output step

Figure 7-27. Small-Signal Overshoot vs Load Capacitance

Figure 7-28. Small-Signal Overshoot vs Load Capacitance

Input

Output

Input

Output

Time (2 ms/div)

Time (25 ms/div)

D028

D027

Figure 7-30. Overload Recovery

Figure 7-29. No Phase Reversal

16

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7.7 TLV6741: Typical Characteristics (continued)

at T_A= 25°C, V_S= 5.5 V, R_L= 10 kΩ connected to V_S/ 2, V_CM= V_S/ 2, and V_OUT= V_S/ 2, unless otherwise noted.

V_IN

V_OUT

V_IN

V_OUT

Time (1 ms/div)

Time (2 ms/div)

D030

D031

V_S= 1.8 V, V_ICM= 0.9 V, V_OCM= 0.9 V

C_L= 30 pF, Gain = 1, V_IN= 100-mVpp

V_S= 5.5 V, V_OCM= 2.75 V, C_L= 10 pF

V_ICM= 2.75 V, Gain = 1, 2-V step

Figure 7-31. Small-Signal Step Response

Figure 7-32. Large Signal Step Response

Time (0.2 ms/div)

Time (0.1 ms/div)

D032

D033

V_S= 5.5 V, V_ICM= 2.75 V, V_OCM= 2.75 V

C_L= 0, Gain = 1, 5-V step

V_S= 5.5 V, V_ICM= 2.75 V, V_OCM= 2.75 V

C_L= 0, Gain = 1, 5-V step

Figure 7-33. Large Signal Settling Time (Positive)

Figure 7-34. Large Signal Settling Time (Negative)

100

6

Sourcing

Sinking

V_S= 1.8 V

V_S= 5.5 V

80

60

5

4

3

2

1

0

40

20

0

-20

-40

-60

-80

-100

-50

0

50

Temperature (èC)

100

150

1

10

100

1k

10k

Frequency (Hz)

100k

1M

10M 100M

D034

D035

Figure 7-35. Short-Circuit Current vs Temperature

V_ICM= V_S/ 2, V_OCM= V_S/ 2,

C_L= 10 pF, Gain = 1

Figure 7-36. Maximum Output Voltage vs Frequency

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7.7 TLV6741: Typical Characteristics (continued)

at T_A= 25°C, V_S= 5.5 V, R_L= 10 kΩ connected to V_S/ 2, V_CM= V_S/ 2, and V_OUT= V_S/ 2, unless otherwise noted.

120

100

80

60

50

40

30

20

10

0

60

40

V_S= 1.8 V

V_S= 5.5 V

20

10M

100M

Frequency (Hz)

1G

10G

0

20

40

60

Capacitive Load (pF)

D036

D037

Figure 7-37. Electromagnetic Interference Rejection Ratio

Referred to Noninverting Input (EMIRR+) vs Frequency

V_ICM= V_OCM= V_S/ 2

Figure 7-38. Phase Margin vs Capacitive Load

7.8 TLV6742: Typical Characteristics

at T_A= 25°C, V_S= ±2.75 V, R_L= 10 kΩ connected to V_S/ 2, V_CM= V_S/ 2, and V_OUT= V_S/ 2, unless otherwise noted.

2500

2250

2000

1750

1500

1250

1000

750

22

20

18

16

14

12

10

8

6

4

500

2

250

0

-500 -400 -300 -200 -100

0

0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5

0

Offset Voltage (µV)

100 200 300 400 500

D002

Offset Voltage Drift (mV/èC)

D001

Figure 7-40. Offset Voltage Drift Distribution

V_CM= V–

Figure 7-39. Offset Voltage Production Distribution

18

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7.8 TLV6742: Typical Characteristics (continued)

at T_A= 25°C, V_S= ±2.75 V, R_L= 10 kΩ connected to V_S/ 2, V_CM= V_S/ 2, and V_OUT= V_S/ 2, unless otherwise noted.

200

160

120

80

4800

4000

3200

2400

1600

800

40

0

-40

-80

-120

-160

-200

-800

-1600

-2400

-3200

-4000

-40

-20

0

20

40

60

80

100 120 140

-40

-20

0

20

40 60

Temperature (°C)

80

100 120 140

Temperature (èC)

D003

D004

V_CM= V–

V_CM= V+

Figure 7-41. Offset Voltage vs Temperature (PMOS Input Pair)

Figure 7-42. Offset Voltage vs Temperature (NMOS Input Pair)

5000

4000

3000

2000

1000

0

200

160

120

80

40

0

-40

-80

-120

-160

-200

-1000

-2000

-3000

-4000

-3 -2.4 -1.8 -1.2 -0.6

0

Input Common Mode Voltage (V)

0.6 1.2 1.8 2.4

3

-3 -2.5 -2 -1.5 -1 -0.5

0

0.5

Input Common Mode Voltage (V)

1

1.5

2

D005

D006

Figure 7-44. Offset Voltage vs Common-Mode Voltage (PMOS

Input Pair)

Over full common-mode voltage range

Figure 7-43. Offset Voltage vs Common-Mode Voltage (Full

Range)

300

240

180

120

60

4000

3000

2000

1000

0

-60

-1000

-2000

-3000

-4000

-120

-180

-240

-300

1.8

1.9

2

2.1

2.2

Input Common Mode Voltage (V)

2.3

2.4

1.5

2

2.5

3

3.5

4

Supply Voltage (V)

4.5

5

5.5

6

D007

D008

Figure 7-45. Offset Voltage vs Common-Mode Voltage

(Transition Region)

Figure 7-46. Offset Voltage vs Power Supply

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7.8 TLV6742: Typical Characteristics (continued)

at T_A= 25°C, V_S= ±2.75 V, R_L= 10 kΩ connected to V_S/ 2, V_CM= V_S/ 2, and V_OUT= V_S/ 2, unless otherwise noted.

50

40

320

280

240

200

160

120

80

I_B-

I_B+

I_OS

30

20

10

0

-10

-20

-30

-40

-50

40

I_B-

I_B+

I_OS

0

-40

-3 -2.5 -2 -1.5 -1 -0.5 0 0.5

V_CM(V)

1

1.5

2

2.5

3

-40

-20

0

20

40 60

Temperature (°C)

80

100 120 140

D009

D010

Figure 7-47. I_Band I_OSvs Common-Mode Voltage

Figure 7-48. I_Band I_OSvs Temperature

100

70

50

30

20

10

7

5

3

2

1

10

Time (1 s/div)

100

1k

Frequency (Hz)

10k

100k

D011

D012

Figure 7-49. 0.1-Hz to 10-Hz Flicker Noise

Figure 7-50. Input Voltage Noise Spectral Density vs Frequency

130

110

90

120

CMRR

PSRR+

PSRR-

115

110

105

100

70

50

30

10

-40

-20

0

20

40 60

Temperature (°C)

80

100 120 140

1k

10k

100k

Frequency (Hz)

1M

10M

D014

D013

Figure 7-51. CMRR and PSRR vs Frequency (Referred to Input)

V_S= 5.5 V, V_CM= V– to (V+) – 1.2 V

Figure 7-52. CMRR vs Temperature

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7.8 TLV6742: Typical Characteristics (continued)

at T_A= 25°C, V_S= ±2.75 V, R_L= 10 kΩ connected to V_S/ 2, V_CM= V_S/ 2, and V_OUT= V_S/ 2, unless otherwise noted.

130

125

120

115

110

120

100

80

210

180

150

120

90

Gain

Phase

60

40

20

60

0

30

-20

100

0

-40

-20

0

20

40 60

Temperature (°C)

80

100 120 140

1k

10k 100k

Frequency (Hz)

1M

10M

D015

D016

V_CM= V–

C_L= 10 pF

Figure 7-53. PSRR vs Temperature

Figure 7-54. Open-Loop Gain and Phase vs Frequency

0.66

0.6

80

60

V_S=1.8V R_L=10kW

V_S=1.8V R_L=2kW

V_S=5.5V R_L=10kW

V_S=5.5V R_L=2kW

0.54

0.48

0.42

0.36

0.3

40

20

0

-20

-40

-60

-80

0.24

0.18

0.12

0.06

G = 1

G = -1

G = 10

G = 100

G = 1000

1k

10k

100k

Frequency (Hz)

1M

10M

-40

-20

0

20

40 60

Temperature (°C)

80

100 120 140

D017

D018

Figure 7-56. Open-Loop Gain vs Temperature

C_L= 10 pF

Figure 7-55. Closed-Loop Gain vs Frequency

180

55

50

45

40

35

30

160

140

120

100

80

60

40

20

0

-20

-0.5

0.5

1.5

2.5 3.5

Output Voltage (V)

4.5

5.5

10

20

30

40

50

Capacitive Load (pF)

60

70

80

90

100

D019

D020

Figure 7-57. Open-Loop Gain vs Output Voltage

Figure 7-58. Phase Margin vs Capacitive Load

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7.8 TLV6742: Typical Characteristics (continued)

at T_A= 25°C, V_S= ±2.75 V, R_L= 10 kΩ connected to V_S/ 2, V_CM= V_S/ 2, and V_OUT= V_S/ 2, unless otherwise noted.

4

3

60

50

40

30

20

10

0

Input

Output

R_ISO= 0W, Overshoot (-)

R_ISO= 0W,Overshoot (+)

R_ISO= 50W, Overshoot (-)

R_ISO= 50W,Overshoot (+)

2

1

0

-1

-2

-3

-4

0

20

40 60

Capacitive Load (pF)

80

100

Time (10 µs/div)

D021

D022

Figure 7-59. No Phase Reversal

V_CM= V_S/ 2, R_L= 1 kΩ

Gain = –1, 100-mV output step

Figure 7-60. Small-Signal Overshoot vs Load Capacitance

70

5

R_ISO= 0W, Overshoot (-)

R_ISO= 0W,Overshoot (+)

R_ISO= 50W, Overshoot (-)

R_ISO= 50W,Overshoot (+)

60

50

40

30

20

10

0

2.5

0

-2.5

Input

Output

-5

Time (10 µs/div)

0

25

50 75

Capacitive Load (pF)

100

125

D024

D023

V_IN=0.6 Vpp, G = –10, V_IN× gain > V_S

V_CM= V_S/ 2, R_L= 1 kΩ

Gain = +1, 100-mV output step

Figure 7-62. Overload Recovery

Figure 7-61. Small-Signal Overshoot vs Load Capacitance

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7.8 TLV6742: Typical Characteristics (continued)

at T_A= 25°C, V_S= ±2.75 V, R_L= 10 kΩ connected to V_S/ 2, V_CM= V_S/ 2, and V_OUT= V_S/ 2, unless otherwise noted.

0.1

0.08

0.06

0.04

0.02

0

0.1

0.08

0.06

0.04

0.02

0

Input

Output

Input

Output

-0.02

-0.04

-0.06

-0.08

-0.1

-0.02

-0.04

-0.06

-0.08

-0.1

Time (1 µs/div)

D025

D027

C_L= 20 pF, Gain = 1, V_IN= 100-mVpp , R_L= 1 kΩ

C_L= 20 pF, Gain = –1, V_IN= 100-mVpp, R_L= 1 kΩ

Figure 7-63. Small-Signal Step Response

Figure 7-64. Small-Signal Step Response

1.25

1

1.25

1

Input

Output

Input

Output

0.75

0.5

0.75

0.5

0.25

0

0.25

0

-0.25

-0.5

-0.75

-1

-0.25

-0.5

-0.75

-1

-1.25

Time (1 µs/div)

D026

D028

C_L= 20 pF, Gain = +1, V_IN= 2-V step, R_L= 1 kΩ

C_L= 20 pF, Gain = –1, V_IN= 2-V step, R_L= 1 kΩ

Figure 7-65. Large Signal Step Response

Figure 7-66. Large Signal Step Response

0.1% Settling Time

Step Applied at t = 0

Time (0.25 ms/div)

D029

D050

C_L= 20 pF, Gain = 1, V_IN= 2-V step

C_L= 20 pF, Gain = –1, V_IN= 2-V step

Figure 7-67. Large Signal Settling Time (Positive)

Figure 7-68. Large Signal Settling Time (Negative)

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7.8 TLV6742: Typical Characteristics (continued)

at T_A= 25°C, V_S= ±2.75 V, R_L= 10 kΩ connected to V_S/ 2, V_CM= V_S/ 2, and V_OUT= V_S/ 2, unless otherwise noted.

-80

-84

-40

R_L= 600 W

R_L= 2 kW

R_L= 10 kW

-88

-60

-92

-96

-100

-104

-108

-112

-116

-120

-80

-100

R_L= 10 kW

R_L= 2 kW

R_L= 600 W

-120

100

1k

Frequency (Hz)

10k

1m

10m

100m

V_OUT(rms)

1

D030

D031

V_CM= 2.5 V

Gain = +1, BW = 80 kHz, V_OUT= 0.5 Vrms

BW = 80 kHz

Figure 7-69. THD + N vs Frequency

Figure 7-70. THD + N vs Amplitude

3

2.8

2.6

2.4

2.2

2

0

-0.2

-0.4

-0.6

-0.8

-1

-40è

25è

85è

125è

85è

125è

1.8

1.6

1.4

1.2

1

-1.2

-1.4

-1.6

-1.8

-2

0.8

0.6

0.4

0.2

0

-2.2

-2.4

-2.6

-2.8

-3

0

5

10 15 20 25 30 35 40 45 50 55 60 65 70 75 80

Output Current (mA)

0

5

10 15 20 25 30 35 40 45 50 55 60 65 70 75 80

Output Current (mA)

D032

D033

Figure 7-71. V_OUTvs Sourcing Current

Figure 7-72. V_OUTvs Sinking Current

6

5

4

3

2

1

0

80

75

70

65

60

55

50

1

10

100

1k

10k

Frequency (Hz)

100k

1M

10M 100M

-40

-20

0

20

40 60

Temperature (°C)

80

100 120 140

D034

D035

Figure 7-74. Short-Circuit Current vs Temperature

C_L= 10 pF, Gain = +1, V_S= 5.5 V

Figure 7-73. Maximum Output Voltage vs Frequency

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7.8 TLV6742: Typical Characteristics (continued)

at T_A= 25°C, V_S= ±2.75 V, R_L= 10 kΩ connected to V_S/ 2, V_CM= V_S/ 2, and V_OUT= V_S/ 2, unless otherwise noted.

1000

990

980

970

960

950

940

930

920

910

900

1000

990

980

970

960

950

940

930

920

910

900

1.5

2

2.5

3

3.5

Supply Voltage (V)

4

4.5

5

5.5

6

-40

-20

0

20

40 60

Temperature (°C)

80

100 120 140

D036

D037

Figure 7-75. Quiescent Current vs Supply Voltage

1200

Figure 7-76. Quiescent Current vs Temperature

-50

-60

1100

1000

900

800

700

600

500

400

300

200

100

0

-70

-80

-90

-100

-110

-120

-130

-140

-150

1k

10k

100k

Frequency (Hz)

1M

10M

100

1k

10k 100k

Frequency (Hz)

1M

10M

D038

D040

Figure 7-77. Open-Loop Output Impedance vs Frequency

A_VDD= 5.5 V, V_ICM= V_OCM= 2.75 V

Figure 7-78. Channel Separation vs Frequency

120

100

80

60

40

20

0

6.5

5.5

4.5

3.5

2.5

1.5

0.5

-0.5

Supply Voltage

Output

10M

100M

Frequency (Hz)

1G

10G

Time (5 ms/div)

D039

D041

Figure 7-79. Electromagnetic Interference Rejection Ratio

Referred to Noninverting Input (EMIRR+) vs Frequency

V_S= 0 to 5.5 V, V_OUT= 0 to 2.75 V

Figure 7-80. Turn-On Time

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8 Detailed Description

8.1 Overview

The TLV674x family is an ultra low-noise, rail-to-rail output operational amplifier family. These devices operate

from a supply voltage of 2.25 V to 5.5 V (TLV6741) and 1.7 V to 5.5 V (TLV6742 and TLV6744), are unity-gain

stable, and suitable for a wide range of general-purpose applications. The input common-mode voltage range

includes the negative rail and allows the TLV674x op amp family to be used in most single-supply applications.

Rail-to-rail output swing significantly increases dynamic range, especially in low-supply applications, and makes

it suitable for many audio applications as well as driving sampling analog-to-digital converters (ADCs).

8.2 Functional Block Diagram

V+

Reference

Current

V_IN+

V_IN-

V_BIAS1

Class AB

Control

Circuitry

V_O

V_BIAS2

V-

(Ground)

8.3 Feature Description

8.3.1 THD+ Noise Performance

TLV674x operational amplifier family has excellent distortion characteristics. TLV6742 and TLV6744 THD +

Noise is below 0.00015% (G = +1, V_O= 1 V_RMS, V_CM= 1.8 V, V_S= 5.5 V) throughout the audio frequency range,

20 Hz to 20 kHz with a 10-kΩ load. TLV6741 THD + Noise is below 0.00035% (G = +1, V_O= 1 V_RMS, V_CM= 2.5

V, V_S= 5.5 V) throughout the audio frequency range, 20 Hz to 20 kHz, with a 10-kΩ load. Broadband noise of

3.5 nV/√ Hz (TLV6742/4) and 3.7 nV/√ Hz (TLV6741) is extremely low for a 10-MHz general purpose amplifier.

8.3.2 Operating Voltage

The TLV674x operational amplifier family is fully specified and assured for operation from 1.7 V to 5.5 V

(TLV6742/4) and 2.25 V to 5.5 V (TLV6741). In addition, many specifications apply from –40°C to 125°C.

Power-supply pins should be bypassed with 0.1-µF ceramic capacitors.

8.3.3 Rail-to-Rail Output

Designed as a low-power, low-voltage operational amplifier, the TLV674x devices deliver a robust output

drive capability. A class AB output stage with common-source transistors achieves full rail-to-rail output swing

capability. For resistive loads of 10-kΩ, the output swings to within a few mV of either supply rail, regardless of

the applied power-supply voltage. Different load conditions change the ability of the amplifier to swing close to

the rails, see Figure 7-11.

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8.3.4 EMI Rejection

The TLV674x uses integrated electromagnetic interference (EMI) filtering to reduce the effects of EMI from

sources such as wireless communications and densely-populated boards with a mix of analog signal chain and

digital components. EMI immunity can be improved with circuit design techniques; the TLV674x benefits from

these design improvements. Texas Instruments has developed the ability to accurately measure and quantify the

immunity of an operational amplifier over a broad frequency spectrum extending from 10 MHz to 6 GHz. Figure

8-1 shows the results of this testing on the TLV674x. Table 8-1 shows the EMIRR IN+ values for the TLV674x at

particular frequencies commonly encountered in real-world applications. The EMI Rejection Ratio of Operational

Amplifiers application report contains detailed information on the topic of EMIRR performance as it relates to op

amps and is available for download from www.ti.com.

120

100

80

60

40

20

0

10M

100M

Frequency (Hz)

1G

10G

D039

Figure 8-1. EMIRR Testing

Table 8-1. TLV674x EMIRR IN+ for Frequencies of Interest

FREQUENCY

APPLICATION OR ALLOCATION

EMIRR IN+

Mobile radio, mobile satellite, space operation, weather, radar, ultra-high frequency (UHF)

applications

400 MHz

59.5 dB

Global system for mobile communications (GSM) applications, radio communication, navigation,

GPS (to 1.6 GHz), GSM, aeronautical mobile, UHF applications

900 MHz

1.8 GHz

2.4 GHz

3.6 GHz

5 GHz

68.9 dB

77.8 dB

78.0 dB

88.8 dB

87.6 dB

GSM applications, mobile personal communications, broadband, satellite, L-band (1 GHz to 2 GHz)

802.11b, 802.11g, 802.11n, Bluetooth^®, mobile personal communications, industrial, scientific and

medical (ISM) radio band, amateur radio and satellite, S-band (2 GHz to 4 GHz)

Radiolocation, aero communication and navigation, satellite, mobile, S-band

802.11a, 802.11n, aero communication and navigation, mobile communication, space and satellite

operation, C-band (4 GHz to 8 GHz)

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8.3.5 Electrical Overstress

Designers often ask questions about the capability of an operational amplifier to withstand electrical overstress

(EOS). These questions tend to focus on the device inputs, but may involve the supply voltage pins or even

the output pin. Each of these different pin functions have electrical stress limits determined by the voltage

breakdown characteristics of the particular semiconductor fabrication process and specific circuits connected to

the pin. Additionally, internal electrostatic discharge (ESD) protection is built into these circuits to protect them

from accidental ESD events both before and during product assembly.

Having a good understanding of this basic ESD circuitry and its relevance to an electrical overstress event is

helpful. Figure 8-2 shows an illustration of the ESD circuits contained in the TLV674x (indicated by the dashed

line area). The ESD protection circuitry involves several current-steering diodes connected from the input and

output pins and routed back to the internal power-supply lines, where the diodes meet at an absorption device

or the power-supply ESD cell, internal to the operational amplifier. This protection circuitry is intended to remain

inactive during normal circuit operation.

TVS

R_F

+V_S

V_DD

OPAx990

100 Ω

R₁

R_S

INœ

œ

IN+

+

Power-Supply

ESD Cell

R_L

I_D

+

V_IN

œ

V_SS

œV_S

TVS

Figure 8-2. Equivalent Internal ESD Circuitry Relative to a Typical Circuit Application

An ESD event is very short in duration and very high voltage (for example; 1 kV, 100 ns), whereas an EOS

event is long in duration and lower voltage (for example; 50 V, 100 ms). The ESD diodes are designed for

out-of-circuit ESD protection (that is, during assembly, test, and storage of the device before being soldered to

the PCB). During an ESD event, the ESD signal is passed through the ESD steering diodes to an absorption

circuit (labeled ESD power-supply circuit). The ESD absorption circuit clamps the supplies to a safe level.

Although this behavior is necessary for out-of-circuit protection, excessive current and damage is caused if

activated in-circuit. A transient voltage suppressor (TVS) can be used to prevent against damage caused by

turning on the ESD absorption circuit during an in-circuit ESD event. Using the appropriate current limiting

resistors and TVS diodes allows for the use of device ESD diodes to protect against EOS events.

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The TLV674x family incorporates internal electrostatic discharge (ESD) protection circuits on all pins, as shown

above. These ESD protection diodes also provide in-circuit, input overdrive protection, as long as the current is

limited to 10 mA as stated in Section 7.1. Figure 8-3 shows how a series input resistor may be added to the

driven input to limit the input current. The added resistor contributes thermal noise at the amplifier input and its

value should be kept to a minimum in noise-sensitive applications.

V+

I_OVERLOAD

10-mA max

V_OUT

Device

V_IN

5 kW

Figure 8-3. Input Current Protection

8.3.6 Typical Specifications and Distributions

Designers often have questions about a typical specification of an amplifier in order to design a more robust

circuit. Due to natural variation in process technology and manufacturing procedures, every specification of an

amplifier will exhibit some amount of deviation from the ideal value, like an amplifier's input offset voltage. These

deviations often follow Gaussian ("bell curve"), or normal, distributions and circuit designers can leverage this

information to guardband their system, even when there is not a minimum or maximum specification in Section

7.6.

0.00312% 0.13185%

0.13185% 0.00312%

0.00002%

2.145% 13.59% 34.13% 34.13% 13.59% 2.145%

1

1 1 1 1 1 1 1 1

1

ꢀ-61 ꢀ-51 ꢀ-41 ꢀ-31 ꢀ-21 ꢀ-1

ꢀ+1 ꢀ+21 ꢀ+31 ꢀ+41 ꢀ+51 ꢀ+61

ꢀ

Figure 8-4. Ideal Gaussian Distribution

Figure 8-4 shows an example distribution, where µ, or mu, is the mean of the distribution, and where σ,

or sigma, is the standard deviation of a system. For a specification that exhibits this kind of distribution,

approximately two-thirds (68.26%) of all units can be expected to have a value within one standard deviation, or

one sigma, of the mean (from µ–σ to µ+σ).

Depending on the specification, values listed in the typical column of Section 7.6 are represented in different

ways. As a general rule of thumb, if a specification naturally has a nonzero mean (for example, like gain

bandwidth), then the typical value is equal to the mean (µ). However, if a specification naturally has a mean near

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zero (like input offset voltage), then the typical value is equal to the mean plus one standard deviation (µ + σ) in

order to most accurately represent the typical value.

You can use this chart to calculate approximate probability of a specification in a unit; for example, for TLV6742,

the typical input voltage offset is 150 µV, so 68.2% of all TLV6742 devices are expected to have an offset from

–150 µV to 150 µV.

Specifications with a value in the minimum or maximum column are assured by TI, and units outside these limits

will be removed from production material. For example, the TLV6742 device has a maximum offset voltage of

1.0 mV at 25°C, and even though this corresponds to 5 σ (≈1 in 1.7 million units), which is extremely unlikely, TI

assures that any unit with a larger offset than 1.0 mV will be removed from production material.

For specifications with no value in the minimum or maximum column, consider selecting a sigma value of

sufficient guardband for your application, and design worst-case conditions using this value. For example, the

6σ value corresponds to about 1 in 500 million units, which is an extremely unlikely chance, and could be an

option as a wide guardband to design a system around. In this case, the TLV6742 does not have a maximum or

minimum for offset voltage drift, but based on Figure 7-40 and the typical value of 0.2 µV/°C in Section 7.6, it can

be calculated that the 6-σ value for offset voltage drift is about 1.0 µV/°C. When designing for worst-case system

conditions, this value can be used to estimate the worst possible offset across temperature without having an

actual minimum or maximum value.

However, process variation and adjustments over time can shift typical means and standard deviations, and

unless there is a value in the minimum or maximum specification column, TI cannot assure the performance of a

device. This information should be used only to estimate the performance of a device.

8.3.7 Shutdown Function

The TLV674xS devices feature SHDN pins that disable the op amp, placing it into a low-power standby mode.

In this mode, the op amp typically consumes less than 1 µA. The SHDN pins are active-low, meaning that

shutdown mode is enabled when the input to the SHDN pin is a valid logic low.

The SHDN pins are referenced to the negative supply voltage of the op amp. The threshold of the shutdown

feature lies around 800 mV (typical) above the negative rail. Hysteresis has been included in the switching

threshold to ensure smooth switching characteristics. To ensure optimal shutdown behavior, the SHDN pins

should be driven with valid logic signals. A valid logic low is defined as a voltage between V– and V– + 0.2 V. A

valid logic high is defined as a voltage between V– + 1.2 V and V+. The shutdown pin must either be connected

to a valid high or a low voltage or driven, and not left as an open circuit. There is no internal pull-up to enable the

amplifier.

The SHDN pins are high-impedance CMOS inputs. Dual op amp versions are independently controlled, and

quad op amp versions are controlled in pairs with logic inputs. For battery-operated applications, this feature

may be used to greatly reduce the average current and extend battery life. The enable time is 15 µs for full

shutdown of all channels; disable time is 3 µs. When disabled, the output assumes a high-impedance state. This

architecture allows the TLV674xS to be operated as a gated amplifier (or to have the device output multiplexed

onto a common analog output bus). Shutdown time (t_OFF) depends on loading conditions and increases as load

resistance increases. To ensure shutdown (disable) within a specific shutdown time, the specified 10-kΩ load

to midsupply (V_S/ 2) is required. If using the TLV674xS without a load, the resulting turnoff time is significantly

increased.

8.3.8 Packages With an Exposed Thermal Pad

The TLV674x family is available in packages such as the WSON-8 (DSG) which feature an exposed thermal

pad. Inside the package, the die is attached to this thermal pad using an electrically conductive compound. For

this reason, when using a package with an exposed thermal pad, the thermal pad must either be connected to

V– or left floating. Attaching the thermal pad to a potential other than V– is not allowed, and performance of the

device is not assured when doing so.

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8.4 Device Functional Modes

The TLV674x family has a single functional mode. The TLV6742 and TLV6744 are powered on as long as the

power-supply voltage is between 1.7 V (±0.85 V) and 5.5 V (±2.75 V).The TLV6741 is powered on as long as the

power-supply voltage is between 2.25 V (±1.125 V) and 5.5 V (±2.75 V).

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9 Application and Implementation

Note

Information in the following applications sections is not part of the TI component specification, and

TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining

suitability of components for their purposes. Customers should validate and test their design

implementation to confirm system functionality.

9.1 Application Information

The TLV674x family features 10-MHz bandwidth and 4.5-V/µs slew rate with only 890-µA (TLV6741), 990-µA

(TLV6742/4) of supply current per channel, providing good AC performance at very-low-power consumption.

DC applications are well served with a very-low input noise voltage of 3.5 nV /vHz (TLV6742/4), 3.7 nV / vHz

(TLV6741) at 10 kHz, low input bias current, and a typical input offset voltage of 0.15 mV.

9.2 Single-Supply Electret Microphone Preamplifier With Speech Filter

Electret microphones are commonly used in portable electronics because of their small size, low cost, and

relatively good signal-to-noise ratio (SNR). The small package size, low operating voltage and excellent AC

performance of the TLV674x family make it an excellent choice for preamplifier circuits for electret microphones.

The circuit shown in Figure 9-1 is a single-supply preamplifier circuit for electret microphones, highlighting the

TLV6741 device.

3V

R₁

200 kꢀ

R_BIAS

2.2 kꢀ

3V

Electret

Microphone

+

TLV6741

V_OUT

C_IN

68 nF

R₂

200 kꢀ

R_F10 kꢀ

R_G

78.7 ꢀ

C_F3.3 nF

C_G

10 µF

Figure 9-1. Microphone Preamplifier

9.2.1 Design Requirements

The design requirements are as follows:

•

Supply voltage: 3 V

Input: 7.93 mV_RMS(0.63 Pa with a –38 dB SPL microphone)

Output: 1 V_RMS

Bandwidth: 300 Hz to 3 kHz

9.2.2 Detailed Design Procedure

The transfer function defining the relationship between V_OUTand the AC input signal is shown in Equation 1:

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≈

’

÷

◊

R

F

V

= V

ì 1+

∆

OUT

IN _ AC

R

«

G

(1)

The required gain can be calculated based on the expected input signal level and desired output level as shown

in Equation 2:

V_OUT

1V_RMS

V

G_OPA

=

=126

V_{IN _ AC}7.93mV_RMS

(2)

Select a standard 10-kΩ feedback resistor and calculate R_G.

R_F

10kW

V

126 -1

V

R_G=

=

= 80W ç 78.7W (closest standard value)

G_OPA-1

(3)

To minimize the attenuation in the desired passband from 300 Hz to 3 kHz, set the upper (f_H) and lower (f_L) cutoff

frequencies outside of the desired bandwidth as:

f_L= 200 Hz

(4)

and

f_H= 5 kHz

(5)

Select C_Gto set the f_Lcutoff frequency using Equation 6:

1

C_G=

=

= 10.11mF ç10mF

2ìp ì R_Gì f_L2ìp ì 78.7Wì 200Hz

(6)

(7)

Select C_Fto set the f_Hcutoff frequency using Equation 7:

1

C_F=

=

= 3.18nF ç 3.3nF (Standard Value)

2ì

p

ì R_Fì f_H2ì

p

ì10kWì5kHz

The input signal cutoff frequency should be set low enough such that low-frequency sound waves still pass

through. Therefore select C_INto achieve a 30-Hz cutoff frequency (f_IN) using Equation 8:

1

C_IN=

=

= 53nF ç 68nF (Standard Value)

2ì

p

ì(R || R₂)ì f_IN2ì

p

ì100kWì30Hz

1

(8)

The measured transfer function for the microphone preamplifier circuit is shown in Figure 9-2 and the measured

THD+N performance of the microphone preamplifier circuit is shown in Figure 9-3.

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SBOS817I – JUNE 2017 – REVISED AUGUST 2021

www.ti.com

9.2.3 Application Curves

50

40

30

20

10

0

œ20

œ40

œ60

œ80

œ10

20

200

2000

Frequency (Hz)

20000

0.005

0.05

0.5

5

RMS Output Voltage (V)

C039

C040

Figure 9-2. Gain vs Frequency

Figure 9-3. THD + N vs RMS Output Voltage

34

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10 Power Supply Recommendations

The TLV6742 and TLV6744 devices are specified for operation from 1.7 V to 5.5 V (±0.85 V to ±2.75 V). The

TLV6741 device is specified for operation from 2.25 V to 5.5 V (±1.125 V to ±2.75 V). Many specifications of the

TLV674x family apply from –40°C to 125°C.

CAUTION

Supply voltages larger than 7 V can permanently damage the device (see Section 7.1).

Place 0.1-µF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or

high-impedance power supplies. For more detailed information on bypass capacitor placement, see Section

11.1.

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www.ti.com

11 Layout

11.1 Layout Guidelines

For best operational performance of the device, use good PCB layout practices, including:

•

Noise can propagate into analog circuitry through the power pins of the circuit as a whole and the operational

amplifier. Bypass capacitors are used to reduce the coupled noise by providing low-impedance power

sources local to the analog circuitry.

– Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as

close to the device as possible. A single bypass capacitor from V+ to ground is applicable for single-

supply applications.

•

Separate grounding for analog and digital portions of the circuitry is one of the simplest and most effective

methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes.

A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically separate digital

and analog grounds, paying attention to the flow of the ground current.

To reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible.

If these traces cannot be kept separate, crossing the sensitive trace perpendicularly is much better than

crossing in parallel with the noisy trace.

•

Place the external components as close to the device as possible. Keeping RF and RG close to the inverting

input minimizes parasitic capacitance, as shown in Figure 11-1.

Keep the length of input traces as short as possible. Always remember that the input traces are the most

sensitive part of the circuit.

Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce

leakage currents from nearby traces that are at different potentials.

36

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11.2 Layout Example

GND

OUTPUT

V-

GND

Figure 11-1. Operational Amplifier Board Layout for Noninverting Configuration

V-

C3

INPUT

OUTPUT

U1

TLV6741

2

1

3

R3

+

4

œ

C4

C2

V+

R1

C1

R2

Figure 11-2. Schematic Used for Layout Example

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GND

V+

INPUT A

OUTPUT B

V-

GND

Figure 11-3. Example Layout for VSSOP-8 (DGK) Package

38

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12 Device and Documentation Support

12.1 Documentation Support

12.1.1 Related Documentation

For related documentation see the following:

•

QFN/SON PCB Attachment.

Quad Flatpack No-Lead Logic Packages.

EMI Rejection Ratio of Operational Amplifiers.

12.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on

Subscribe to updates to register and receive a weekly digest of any product information that has changed. For

change details, review the revision history included in any revised document.

12.3 Support Resources

TI E2E^™support forums are an engineer's go-to source for fast, verified answers and design help — straight

from the experts. Search existing answers or ask your own question to get the quick design help you need.

Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do

not necessarily reflect TI's views; see TI's Terms of Use.

12.4 Trademarks

TI E2E^™is a trademark of Texas Instruments.

Bluetooth^®is a registered trademark of Bluetooth SIG, Inc.

All trademarks are the property of their respective owners.

12.5 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric changes could cause the device not to meet its published

specifications.

12.6 Glossary

TI Glossary

This glossary lists and explains terms, acronyms, and definitions.

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13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

40

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PACKAGE MATERIALS INFORMATION

www.ti.com

10-Sep-2021

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

TLV6741DCKR

TLV6741DCKT

TLV6742IDDFR

SC70

DCK

DDF

5

8

3000

250

178.0

180.0

9.0

8.4

2.4

3.2

2.5

3.2

1.2

1.4

4.0

8.0

Q3

SOT-

3000

23-THIN

TLV6742IDGKR

TLV6742IDR

VSSOP

SOIC

DGK

D

8

2500

3000

2000

3000

330.0

180.0

330.0

178.0

12.4

8.4

5.3

6.4

3.4

5.2

1.4

2.1

8.0

4.0

8.0

4.0

12.0

8.0

Q1

Q2

Q1

TLV6742IDSGR

TLV6742IPWR

TLV6742SIRUGR

WSON

TSSOP

X2QFN

DSG

PW

8

2.3

1.15

1.6

8

12.4

8.4

7.0

3.6

12.0

8.0

RUG

10

1.75

2.25

0.56

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

10-Sep-2021

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

TLV6741DCKR

TLV6741DCKT

TLV6742IDDFR

TLV6742IDGKR

TLV6742IDR

SC70

DCK

DDF

DGK

D

5

3000

250

190.0

210.0

366.0

853.0

210.0

853.0

205.0

190.0

185.0

364.0

449.0

185.0

449.0

200.0

30.0

35.0

50.0

35.0

33.0

SOT-23-THIN

VSSOP

SOIC

8

3000

2500

3000

2000

3000

8

TLV6742IDSGR

TLV6742IPWR

TLV6742SIRUGR

WSON

DSG

PW

8

TSSOP

X2QFN

8

RUG

10

Pack Materials-Page 2

PACKAGE OUTLINE

D0008A

SOIC - 1.75 mm max height

SCALE 2.800

SMALL OUTLINE INTEGRATED CIRCUIT

C

SEATING PLANE

.228-.244 TYP

[5.80-6.19]

.004 [0.1] C

A

PIN 1 ID AREA

6X .050

[1.27]

8

1

2X

.189-.197

[4.81-5.00]

NOTE 3

.150

[3.81]

4X (0 -15 )

4

5

8X .012-.020

[0.31-0.51]

B

.150-.157

[3.81-3.98]

NOTE 4

.069 MAX

[1.75]

.010 [0.25]

C A B

.005-.010 TYP

[0.13-0.25]

4X (0 -15 )

SEE DETAIL A

.010

[0.25]

.004-.010

[0.11-0.25]

0 - 8

.016-.050

[0.41-1.27]

DETAIL A

TYPICAL

(.041)

[1.04]

4214825/C 02/2019

NOTES:

1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.

Dimensioning and tolerancing per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed .006 [0.15] per side.

4. This dimension does not include interlead flash.

5. Reference JEDEC registration MS-012, variation AA.

www.ti.com

EXAMPLE BOARD LAYOUT

D0008A

SOIC - 1.75 mm max height

SMALL OUTLINE INTEGRATED CIRCUIT

8X (.061 )

[1.55]

SYMM

SEE

DETAILS

1

8

8X (.024)

[0.6]

SYMM

(R.002 ) TYP

[0.05]

5

4

6X (.050 )

[1.27]

(.213)

[5.4]

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:8X

SOLDER MASK

OPENING

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

METAL

EXPOSED

METAL

EXPOSED

METAL

.0028 MAX

[0.07]

.0028 MIN

[0.07]

ALL AROUND

SOLDER MASK

DEFINED

NON SOLDER MASK

DEFINED

SOLDER MASK DETAILS

4214825/C 02/2019

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com

EXAMPLE STENCIL DESIGN

D0008A

SOIC - 1.75 mm max height

SMALL OUTLINE INTEGRATED CIRCUIT

8X (.061 )

[1.55]

SYMM

1

8

8X (.024)

[0.6]

SYMM

(R.002 ) TYP

[0.05]

5

4

6X (.050 )

[1.27]

(.213)

[5.4]

SOLDER PASTE EXAMPLE

BASED ON .005 INCH [0.125 MM] THICK STENCIL

SCALE:8X

4214825/C 02/2019

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

9. Board assembly site may have different recommendations for stencil design.

www.ti.com

GENERIC PACKAGE VIEW

DSG 8

2 x 2, 0.5 mm pitch

WSON - 0.8 mm max height

PLASTIC SMALL OUTLINE - NO LEAD

This image is a representation of the package family, actual package may vary.

Refer to the product data sheet for package details.

4224783/A

www.ti.com

PACKAGE OUTLINE

DSG0008A

WSON - 0.8 mm max height

SCALE 5.500

PLASTIC SMALL OUTLINE - NO LEAD

2.1

1.9

B

A

PIN 1 INDEX AREA

2.1

1.9

0.32

0.18

0.4

0.2

ALTERNATIVE TERMINAL SHAPE

TYPICAL

C

0.8 MAX

SEATING PLANE

0.08 C

0.05

0.00

EXPOSED

THERMAL PAD

(0.2) TYP

0.9 0.1

5

4

6X 0.5

2X

1.5

9

1.6 0.1

8

1

0.32

0.18

8X

0.4

0.2

PIN 1 ID

8X

0.1

C A B

C

0.05

4218900/D 04/2020

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

www.ti.com

EXAMPLE BOARD LAYOUT

DSG0008A

WSON - 0.8 mm max height

PLASTIC SMALL OUTLINE - NO LEAD

(0.9)

(

0.2) VIA

8X (0.5)

TYP

1

8

8X (0.25)

(0.55)

SYMM

9

(1.6)

6X (0.5)

5

4

SYMM

(1.9)

(R0.05) TYP

LAND PATTERN EXAMPLE

SCALE:20X

0.07 MIN

ALL AROUND

0.07 MAX

ALL AROUND

SOLDER MASK

OPENING

METAL

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

NON SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4218900/D 04/2020

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

www.ti.com

EXAMPLE STENCIL DESIGN

DSG0008A

WSON - 0.8 mm max height

PLASTIC SMALL OUTLINE - NO LEAD

8X (0.5)

METAL

8

SYMM

1

8X (0.25)

(0.45)

SYMM

9

(0.7)

6X (0.5)

5

4

(R0.05) TYP

(0.9)

(1.9)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD 9:

87% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE

SCALE:25X

4218900/D 04/2020

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

PACKAGE OUTLINE

PW0008A

TSSOP - 1.2 mm max height

S

C

A

L

E

2

.

8

0

SMALL OUTLINE PACKAGE

C

6.6

6.2

SEATING PLANE

TYP

PIN 1 ID

AREA

A

0.1 C

6X 0.65

8

5

1

3.1

2.9

NOTE 3

2X

1.95

4

0.30

0.19

8X

4.5

4.3

1.2 MAX

B

0.1

C A

B

NOTE 4

(0.15) TYP

SEE DETAIL A

0.25

GAGE PLANE

0.15

0.05

0.75

0.50

0 - 8

DETAIL A

TYPICAL

4221848/A 02/2015

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed 0.15 mm per side.

4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.

5. Reference JEDEC registration MO-153, variation AA.

www.ti.com

EXAMPLE BOARD LAYOUT

PW0008A

TSSOP - 1.2 mm max height

SMALL OUTLINE PACKAGE

8X (1.5)

SYMM

8X (0.45)

(R0.05)

1

4

TYP

8

SYMM

6X (0.65)

5

(5.8)

LAND PATTERN EXAMPLE

SCALE:10X

SOLDER MASK

OPENING

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

METAL

0.05 MAX

ALL AROUND

0.05 MIN

ALL AROUND

SOLDER MASK

DEFINED

NON SOLDER MASK

DEFINED

SOLDER MASK DETAILS

NOT TO SCALE

4221848/A 02/2015

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com

EXAMPLE STENCIL DESIGN

PW0008A

TSSOP - 1.2 mm max height

SMALL OUTLINE PACKAGE

8X (1.5)

SYMM

(R0.05) TYP

8X (0.45)

1

4

8

SYMM

6X (0.65)

5

(5.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

SCALE:10X

4221848/A 02/2015

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

9. Board assembly site may have different recommendations for stencil design.

www.ti.com

PACKAGE OUTLINE

DDF0008A

SOT-23 - 1.1 mm max height

S

C

A

L

E

4

.

0

PLASTIC SMALL OUTLINE

C

2.95

2.65

SEATING PLANE

TYP

PIN 1 ID

AREA

0.1 C

A

6X 0.65

8

1

2.95

2.85

NOTE 3

2X

1.95

4

5

0.4

0.2

8X

0.1

C A

B

1.65

1.55

B

1.1 MAX

0.20

0.08

TYP

SEE DETAIL A

0.25

GAGE PLANE

0.1

0.0

0 - 8

0.6

0.3

DETAIL A

TYPICAL

4222047/B 11/2015

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed 0.15 mm per side.

www.ti.com

EXAMPLE BOARD LAYOUT

DDF0008A

SOT-23 - 1.1 mm max height

PLASTIC SMALL OUTLINE

8X (1.05)

SYMM

1

8

8X (0.45)

SYMM

6X (0.65)

5

4

(R0.05)

TYP

(2.6)

LAND PATTERN EXAMPLE

SCALE:15X

SOLDER MASK

OPENING

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

METAL

SOLDER MASK

DEFINED

NON SOLDER MASK

DEFINED

SOLDER MASK DETAILS

4222047/B 11/2015

NOTES: (continued)

4. Publication IPC-7351 may have alternate designs.

5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com

EXAMPLE STENCIL DESIGN

DDF0008A

SOT-23 - 1.1 mm max height

PLASTIC SMALL OUTLINE

8X (1.05)

SYMM

(R0.05) TYP

8

1

8X (0.45)

SYMM

6X (0.65)

5

4

(2.6)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

SCALE:15X

4222047/B 11/2015

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

7. Board assembly site may have different recommendations for stencil design.

www.ti.com

IMPORTANT NOTICE AND DISCLAIMER

TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE

DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”

AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY

IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD

PARTY INTELLECTUAL PROPERTY RIGHTS.

These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate

TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable

standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you

permission to use these resources only for development of an application that uses the TI products described in the resource. Other

reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party

intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages,

costs, losses, and liabilities arising out of your use of these resources.

TI’s products are provided subject to TI’s Terms of Sale (https:www.ti.com/legal/termsofsale.html) or other applicable terms available either

on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s

applicable warranties or warranty disclaimers for TI products.IMPORTANT NOTICE

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	TLV6742IDSGR
厂家：	TEXAS INSTRUMENTS
描述：	Dual, 5.5-V, 10-MHz, low noise (4.6-nV/√Hz) operational amplifier \| DSG \| 8 \| -40 to 125
文件：	总64页 (文件大小：5390K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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