TLV701 [TI]
用于提供 3V 和 3.3V 输出的 150mA、24V、超低 IQ、低压降稳压器;
| 型号： | TLV701 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 用于提供 3V 和 3.3V 输出的 150mA、24V、超低 IQ、低压降稳压器 电源电路 线性稳压器IC |
| 文件： | 总13页 (文件大小：592K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TLV701xx
www.ti.com
SBVS161 –NOVEMBER 2011
24-V Input Voltage, 150-mA, Ultralow IQ Low-Dropout Regulators
1
FEATURES
DESCRIPTION
The TLV701xx series of low-dropout (LDO) regulators
are ultralow quiescent current devices designed for
extremely power-sensitive applications. Quiescent
current is virtually constant over the complete load
current and ambient temperature range. These
devices are an ideal power management attachment
to low-power microcontrollers, such as the MSP430.
23
•
Wide Input Voltage Range: 2.5 V to 24 V
Low 3.2-μA Quiescent Current
•
•
•
•
•
Ground Pin Current: 3.4 μA at 100-mA IOUT
Stable with Any Capacitor (> 0.47 μF)
Available in SOT23-5 Package
Operating Junction Temperature:
–40°C to +125°C
The TLV701xx operates over a wide operating input
voltage of 2.5 V to 24 V. Thus, it is an excellent
choice for both battery-powered systems as well as
industrial applications that see large line transients.
APPLICATIONS
•
•
•
•
•
•
•
•
•
Ultralow Power Microcontrollers
E-Meters
The TLV701xx is available in a 3-mm × 3-mm
SOT23-5 package that is ideal for cost-effective
board manufacturing.
Fire Alarms/Smoke Detector Systems
Handset Peripherals
Industrial/Automotive Applications
Remote Controllers
Zigbee™ Networks
PDAs
Portable, Battery-Powered Equipment
DBV PACKAGE
SOT23
(TOP VIEW)
TLV70133
VIN
OUT
IN
MSP430
GND
OUT
GND
IN
1
2
3
5
4
NC
NC
1 mF
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
3
Zigbee is a trademark of ZigBee Alliance.
All other trademarks are the property of their respective owners.
PRODUCT PREVIEW information concerns products in the
formative or design phase of development. Characteristic data and
other specifications are design goals. Texas Instruments reserves
the right to change or discontinue these products without notice.
Copyright © 2011, Texas Instruments Incorporated
TLV701xx
SBVS161 –NOVEMBER 2011
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
AVAILABLE OPTIONS(1)
PRODUCT
VOUT
TLV701xxyyyz
XX is nominal output voltage (for example, 30 = 3.0 V)
YYY is Package Designator
Z is Package Quantity
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the
device product folder at www.ti.com.
ABSOLUTE MAXIMUM RATINGS(1)
Over operating free-air temperature range, unless otherwise noted.
VALUE
MIN
UNIT
MAX
Voltage(2)
IN
–0.3
24
V
Current source
OUT
Internally limited
Operating junction, TJ
Storage, Tstg
–40
–65
+150
+150
°C
°C
Temperature
Human body model (HBM)
QSS 009-105 (JESD22-A114A)
2
kV
V
Electrostatic Discharge Rating(3)
Charged device model (CDM)
QSS 009-147 (JESD22-C101B.01)
500
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods my affect device reliability.
(2) All voltages are with respect to network ground terminal.
(3) ESD testing is performed according to the respective JESD22 JEDEC standard.
THERMAL INFORMATION
TLV701XX
THERMAL METRIC(1)
DBV
5 PINS
213.1
110.9
97.4
UNITS
θJA
Junction-to-ambient thermal resistance
θJCtop
θJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
22.0
ψJB
78.4
θJCbot
n/a
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
2
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Copyright © 2011, Texas Instruments Incorporated
TLV701xx
www.ti.com
SBVS161 –NOVEMBER 2011
ELECTRICAL CHARACTERISTICS: TA = +25°C
All values are at TA = +25°C, VIN = VOUT(nom) + 1 V, IOUT = 1 mA, and COUT = 1 µF, unless otherwise noted.
TLV701xx
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
24
5
UNIT
V
Input voltage range
Output voltage range
DC output accuracy
Line regulation
VO
1.2
V
VOUT
–2
2
%
ΔVO for ΔVIN
VOUT(NOM) + 1 V < VIN < 24 V
1 mA < IOUT < 10 mA
1 mA < IOUT < 50 mA
1 mA < IOUT < 100 mA
IOUT = 10 mA
20
6
50
mV
mV
mV
mV
mV
mV
mA
µA
µA
dB
ΔVO for ΔIOUT Load regulation
19
29
75
400
50
VDO
ICL
Dropout voltage(1)
IOUT = 50 mA
Output current limit
Ground pin current
VOUT = 0 V
160
1000
4.5
IOUT = 0 mA
3.2
3.4
60
IGND
PSRR
IOUT = 100 mA
5.5
Power-supply rejection ratio
f = 100 kHz, COUT = 10 µF
(1) VIN = VOUT(NOM) – 0.1 V.
FUNCTIONAL BLOCK DIAGRAM
VIN
VOUT
Current
Sense
ILIM
R1
_
+
GND
R2
VREF = 1.205 V
Bandgap
Reference
R2 = 840 kW
Copyright © 2011, Texas Instruments Incorporated
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3
TLV701xx
SBVS161 –NOVEMBER 2011
www.ti.com
PIN CONFIGURATIONS
DBV PACKAGE
SOT23-5
(TOP VIEW)
5
4
1
2
3
OUT
GND
IN
NC
NC
Table 1. Pin Descriptions
TLV701xx
NAME
GND
IN
DBV
DESCRIPTION
2
3
Ground
Unregulated input voltage.
Regulated output voltage.
Any capacitor 1 µF or greater between this pin and ground is needed for stability.
OUT
NC
1
4, 5
No connection. This pin can be left open or tied to ground for improved thermal performance.
4
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Copyright © 2011, Texas Instruments Incorporated
TLV701xx
www.ti.com
SBVS161 –NOVEMBER 2011
TYPICAL CHARACTERISTICS
LOAD REGULATION
(VOUT = 3.0 V)
LINE REGULATION
3.1
3.08
3.06
3.04
3.02
3.0
3.3
VOUT = 3.0 V
IOUT = 5 mA
3.2
3.1
3
2.98
2.96
2.94
2.92
2.9
2.9
-40°C
-40°C
2.8
2.7
+25°C
+85°C
+25°C
+85°C
0
30
60
90
120
150
4
8
12
16
20
24
Input Voltage (V)
Output Current (mA)
Figure 1.
Figure 2.
OUTPUT VOLTAGE vs
JUNCTION TEMPERATURE
DROPOUT VOLTAGE vs INPUT VOLTAGE
3.165
3.132
3.099
3.066
3.033
3.0
120
100
80
60
40
20
0
IOUT = 10 mA
VIN = 4.0 V
VNOM = 3 V
IOUT = 10 mA
2.967
2.934
2.901
2.868
2.835
IOUT = 80 mA
-40°C
+25°C
+85°C
-40 -25 -10
5
20 35 50 65 80 95 110 125
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
3
Junction Temperature (°C)
Input Voltage (V)
Figure 3.
Figure 4.
DROPOUT VOLTAGE vs OUTPUT CURRENT
GROUND CURRENT vs JUNCTION TEMPERATURE
4.5
2100
1800
1500
1200
900
600
300
0
VIN = 4.0 V
VOUT = 3.0 V
COUT = 1 mF
4
3.5
3
2.5
2
-40°C
+25°C
+85°C
-40 -25 -10
5
20 35 50 65 80 95 110 125
0
30
60
90
120
150
Output Current (mA)
Junction Temperature (°C)
Figure 5.
Figure 6.
Copyright © 2011, Texas Instruments Incorporated
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5
TLV701xx
SBVS161 –NOVEMBER 2011
www.ti.com
TYPICAL CHARACTERISTICS (continued)
CURRENT LIMIT vs
GROUND PIN CURRENT vs OUTPUT CURRENT
JUNCTION TEMPERATURE
250
200
150
100
50
4.5
4
VOUT = 3.0 V
VOUT = 3.0 V, VIN = 4.5 V
-40°C
+25°C
+85°C
3.5
3
2.5
2
1.5
1
-40°C
+25°C
+85°C
0.5
0
0
0
30
60
90
120
150
Temperature (°C)
Output Current (mA)
Figure 7.
Figure 8.
OUTPUT SPECTRAL NOISE DENSITY vs
FREQUENCY
PSRR vs FREQUENCY
100
8
7
6
5
4
3
2
1
0
VIN = 4.0 V
VIN = 4.0 V
90
80
70
60
50
40
30
20
10
0
VOUT = 3.0 V
COUT = 10 mF
TJ = +25°C
VOUT = 3.0 V
IOUT = 1 mA
COUT = 1 mF
IOUT = 1 mA
IOUT = 50 mA
IOUT = 50 mA
100
1 k
10 k
100 k
10
100
1 k
10 k
100 k
1 M
10 M
Frequency (Hz)
Frequency (Hz)
Figure 9.
Figure 10.
LINE TRANSIENT RESPONSE
LOAD TRANSIENT RESPONSE
VIN = 3.0 V
VIN = 4.0 V
100
IOUT = 50 mA
VOUT = 3.0 V
COUT = 10 mF
COUT = 10 mF
200
0
50
0
-200
-50
5.3
4.3
100
50
0
Time (50 ms/div)
Time (0.5 ms/div)
Figure 11.
Figure 12.
6
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Copyright © 2011, Texas Instruments Incorporated
TLV701xx
www.ti.com
SBVS161 –NOVEMBER 2011
APPLICATION INFORMATION
The TLV701xx series of devices belong to a family of ultralow, IQ, low-dropout (LDO) regulators. IQ remains fairly
constant over the complete output load current and temperature range. The devices are ensured to operate over
a temperature range of –40°C to +125°C.
INPUT AND OUTPUT CAPACITOR REQUIREMENTS
The TLV701 requires a 1-µF or larger capacitor connected between OUT and GND for stability. Ceramic or
tantalum capacitors can be used. Larger value capacitors result in better transient and noise performance.
Although an input capacitor is not required for stability, when a 0.1-µF or larger capacitor is placed between IN
and GND, it counteracts reactive input sources and improves transient and noise performance. Higher value
capacitors are necessary if large, fast rise time load transients are anticipated.
BOARD LAYOUT RECOMMENDATIONS
Input and output capacitors should be placed as close to the device pins as possible. To avoid interference of
noise and ripple on the board, it is recommended that the board be designed with separate ground planes for VIN
and VOUT, with the ground plane connected only at the device GND pin. In addition, the ground connection for
the output capacitor should be connected directly to the device GND pin.
POWER DISSIPATION AND JUNCTION TEMPERATURE
To ensure reliable operation, worst-case junction temperature should not exceed +125°C. This restriction limits
the power dissipation the regulator can handle in any given application. To ensure the junction temperature is
within acceptable limits, calculate the maximum allowable dissipation, PD(max), and the actual dissipation, PD,
which must be less than or equal to PD(max)
.
The maximum power dissipation limit is determined using Equation 1:
T max * T
+
J
A
P
D(max)
R
qJA
(1)
where:
TJmax is the maximum allowable junction temperature.
θJA is the thermal resistance junction-to-ambient for the package.
R
TA is the ambient temperature.
The regulator dissipation is calculated using Equation 2:
+ ǒV
Ǔ
I
P
* V
D
IN
OUT
OUT
(2)
Power dissipation that results from quiescent current is negligible.
REGULATOR PROTECTION
The TLV701xx series of LDO regulators use a PMOS-pass transistor that has a built-in back diode that conducts
reverse current when the input voltage drops below the output voltage (for example, during power-down). Current
is conducted from the output to the input and is not internally limited. If extended reverse voltage operation is
anticipated, external limiting might be appropriate.
The TLV701xx features internal current limiting. During normal operation, the TLV701xx limits output current to
approximately 250 mA. When current limiting engages, the output voltage scales back linearly until the
overcurrent condition ends. Take care not to exceed the rated maximum operating junction temperature of
+125°C. Continuously running the device under conditions where the junction temperature exceeds +125°C
degrades device reliability.
The ability to remove heat from the die is different for each package type, presenting different considerations in
the printed circuit board (PCB) layout. The PCB area around the device that is free of other components moves
the heat from the device to the ambient air. Using heavier copper increases the effectiveness in removing heat
from the device. The addition of plated through-holes to heat-dissipating layers also improves heatsink
effectiveness. Power dissipation depends on input voltage and load conditions. Power dissipation (PD) is equal to
the product of the output current and the voltage drop across the output pass element, as shown in Equation 2.
Copyright © 2011, Texas Instruments Incorporated
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7
PACKAGE OPTION ADDENDUM
www.ti.com
16-Dec-2011
PACKAGING INFORMATION
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
TLV70130DBVR
TLV70130DBVT
TLV70133DBVR
TLV70133DBVT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOT-23
SOT-23
SOT-23
SOT-23
DBV
DBV
DBV
DBV
5
5
5
5
3000
250
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
3000
250
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
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provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
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TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Dec-2011
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TLV70130DBVR
TLV70130DBVT
TLV70133DBVR
TLV70133DBVT
SOT-23
SOT-23
SOT-23
SOT-23
DBV
DBV
DBV
DBV
5
5
5
5
3000
250
178.0
178.0
178.0
178.0
9.0
9.0
9.0
9.0
3.23
3.23
3.23
3.23
3.17
3.17
3.17
3.17
1.37
1.37
1.37
1.37
4.0
4.0
4.0
4.0
8.0
8.0
8.0
8.0
Q3
Q3
Q3
Q3
3000
250
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Dec-2011
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TLV70130DBVR
TLV70130DBVT
TLV70133DBVR
TLV70133DBVT
SOT-23
SOT-23
SOT-23
SOT-23
DBV
DBV
DBV
DBV
5
5
5
5
3000
250
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
18.0
18.0
18.0
18.0
3000
250
Pack Materials-Page 2
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