TLV7081YKAR [TI]
毫微功耗微封装低电压比较器 | YKA | 4 | -40 to 125;
| 型号： | TLV7081YKAR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 毫微功耗微封装低电压比较器 | YKA | 4 | -40 to 125 比较器 |
| 文件： | 总22页 (文件大小：1318K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TLV7081
ZHCSIE1A –MAY 2018–REVISED JUNE 2018
TLV7081 纳瓦级功率 4 凸点 WCSP 小尺寸比较器
1 特性
3 说明
TLV7081 是一款单通道纳瓦级功率比较器，工作电压
1
•
•
•
•
•
•
•
•
宽电源电压范围：1.7V 至 5.5V
低至 1.7V。该比较器采用 0.7mm × 0.7mm 超小型
WCSP 封装，使 TLV7081 适用于空间关键型设计，例
如智能手机和其他便携式或电池供电 应用。
370nA 静态电源电流
4µs 低传播延迟
漏极开路输出
TLV7081 具有 不依赖电源电压的广泛输入电压范围。
拥有不依赖电源电压的输入范围使 TLV7081 即使在没
有通电的情况下也可直接连接电源。
独立输入电压范围最高可达 5.6V
内部磁滞：10mV
温度范围：-40°C 至 +125°C
封装：
TLV7081 具有可上拉到 V+ 之上的漏极开路输出级，
因此适用于电平转换器和双极至单端转换器。
–
0.7mm × 0.7mm WCSP (4)
器件信息 (1)
器件型号
TLV7081
封装
WCSP (4)
封装尺寸（标称值）
2 应用
0.7mm × 0.7mm
•
•
•
•
•
•
•
•
智能手机
笔记本电脑和平板电脑
光学模块
小尺寸、低功耗比较器系列
每通道的
系列
tPD
输出类型
封装
IQ
数码相机
TLV7081
TLV7031
TLV7041
TLV7011
TLV7021
370nA
335nA
335nA
5µA
4µs
3µs
漏极开路
推挽
WCSP
X2SON
X2SON
X2SON
X2SON
中继器和断路器
便携式医疗设备
门窗传感器
3µs
漏极开路
推挽
260ns
260ns
视频游戏控制器
5µA
漏极开路
(1) 如需了解所有可用封装，请参阅产品说明书末尾的封装选项附
录。
欠压检测
IS 与 电源电压间的关系
600
1.8V
Regulator
500
400
Output
Logic Levels
0V & 1.8V
Lithium
Ion
Battery
GPIO (
)
RPU
R1
300
GPIO (input)
PE ASIC
+
Temp -40°C
Temp 25°C
Temp 85°C
Temp 125°C
200
TLV7081
R2
100
1.5
2
2.5
3
3.5
4
4.5
5
5.5
VS (V)
is_v
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TLV7081
ZHCSIE1A –MAY 2018–REVISED JUNE 2018
www.ti.com.cn
目录
7.3 Feature Description................................................. 10
7.4 Device Functional Modes........................................ 10
Application and Implementation ........................ 12
8.1 Application Information............................................ 12
8.2 Typical Applications ................................................ 12
Layout ................................................................... 14
9.1 Layout Guidelines ................................................... 14
9.2 Layout Example ...................................................... 14
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 4
6.5 Electrical Characteristics........................................... 5
6.6 Switching Characteristics.......................................... 5
6.7 Timing Diagrams....................................................... 6
6.8 Typical Characteristics.............................................. 7
Detailed Description ............................................ 10
7.1 Overview ................................................................. 10
7.2 Functional Block Diagram ....................................... 10
8
9
10 器件和文档支持 ..................................................... 15
10.1 文档支持 ............................................................... 15
10.2 接收文档更新通知 ................................................. 15
10.3 社区资源................................................................ 15
10.4 Trademarks........................................................... 15
10.5 Electrostatic Discharge Caution............................ 15
10.6 术语表 ................................................................... 15
11 机械、封装和可订购信息....................................... 15
7
4 修订历史记录
Changes from Original (December 2017) to Revision A
Page
•
•
已更改 将“预告信息”更改成了“生产数据” ................................................................................................................................ 1
Added note to the Timing Diagrams section .......................................................................................................................... 6
2
Copyright © 2018, Texas Instruments Incorporated
TLV7081
www.ti.com.cn
ZHCSIE1A –MAY 2018–REVISED JUNE 2018
5 Pin Configuration and Functions
YKA Package
4-Bump DSBGA
Top View
Top View
A
B
OUT
IN
V+
V-
Pin Functions
PIN
I/O
DESCRIPTION
NAME
OUT
V+
Number
A1
O
P
P
I
Comparator output: OUT is open-drain.
B1
Positive (highest) power supply; functions as an external reference voltage
Negative (lowest) power supply
V–
B2
IN
A2
Comparator input: IN is the noninverting input
Copyright © 2018, Texas Instruments Incorporated
3
TLV7081
ZHCSIE1A –MAY 2018–REVISED JUNE 2018
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
– 0.3
– 0.3
MAX
6
UNIT
V
Supply voltage VS = (V+) - (V-)
Input (IN) to (V–)(2)
6
V
Current into input (IN)
±10
6
mA
V
Output (OUT) to (V–)
– 0.3
Output short-circuit duration(3)
Junction temperature, TJ
Storage temperature, Tstg
10
s
150
150
°C
°C
– 65
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Input signals that can swing more than 0.3 V below (V–) must be current-limited to 10 mA or less.
(3) Short-circuit to ground, one comparator per package.
6.2 ESD Ratings
VALUE
±1500
±500
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
Electrostatic
discharge
V(ESD)
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
5.5
UNIT
Supply voltage VS = (V+) - (V-)
Open-Drain PULL-UP voltage VPULL-UP
Ambient temperature, TA
1.7
V
V
5.5
–40
125
°C
6.4 Thermal Information
TLV7081
THERMAL METRIC(1)
YKA (DSBGA)
UNIT
4 PINS
207
1.8
RθJA
RθJC(top)
RθJB
ΨJT
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
73.2
1
Junction-to-top characterization parameter
Junction-to-board characterization parameter
ΨJB
73.3
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
4
Copyright © 2018, Texas Instruments Incorporated
TLV7081
www.ti.com
ZHCSIE1A –MAY 2018–REVISED JUNE 2018
6.5 Electrical Characteristics
Over the operating temperature range of TA = –40°C to +125°C, VS = 3.3 V, and VPULL-UP = V+ (unless otherwise
noted). Typical values are at TA = 25°C. Voltage at input pin (IN) is referenced to (V-).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VS = 1.8 V and 3.3 V, TA = –40°C to
+125°C
VIO
Input Offset Voltage
–10
±1
10
mV
dVIO/dT
VHYS
VIN
Input Offset Voltage Drift
Input Hysteresis Voltage
TA = –40°C to +125°C
±3
10
µV/℃
mV
V
(1)
Input Voltage Range
0
5.6
IN = 5.6 V, positive value means current
entering pin (IN)
IBIAS
Input bias current
3
pA
pA
IN = 5.6 V, VS = 0 V, positive value means
current entering pin (IN)
ILEAK
CI
Input leakage current
Input Capacitance
4
1.9
pF
V
Sinking 200 µA, measured relative to (V-)
Sinking 2 mA, measured relative to (V-)
VS = 5 V
0.1
0.4
VOL
Low-Level Output Voltage
V
IO-SC
Short-circuit sink current
Output Leakage Current
45
130
75
mA
IN = (V+) + 0.1V (output high), VPULL-UP
= (V+)
IO-LKG
PSRR
pA
dB
Power Supply Rejection Ratio VS = 1.8 V to 5 V
no load, IN = (V+) – 0.1V (output low),
370
470
630
TA = 25°C
IS
Supply Current
nA
no load, IN = (V+) – 0.1V (output low),
TA = –40°C to +125°C
(1) Over Operating Supply Voltage Range (Vs): 1.7 V to 5.5 V
6.6 Switching Characteristics
Typical values are at TA = 25°C, VS = 3.3 V; CL = 15 pF, (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
High-to-low propagation
delay
tPHL
tPLH
Input overdrive = –100 mV
4
µs
(1)
Low-to-high propagation
Input overdrive = +100 mV, RPULL-UP
4.99 kΩ
=
4
µs
(1)
delay
tF
Output fall time
Measured from 20% to 80%
7
1
ns
(2)
tON
Start-up delay
ms
(1) High-to-low and low-to-high refers to the transition at the input pin (IN).
(2) During power on, VS must exceed 1.7 V for 1 ms before the output is in a correct state.
Copyright © 2018, Texas Instruments Incorporated
5
TLV7081
ZHCSIE1A –MAY 2018–REVISED JUNE 2018
www.ti.com
6.7 Timing Diagrams
VPULL-UP
VPULL-UP
(Vt ) + 1.7V
REF
tON
(Vt )
REF
VPULL-UP
OUT
+
OUT
50%
(Vt )
Figure 1. Start-up Delay
VPULL-UP
REF + 100 mV
REF
IN
REF
OUT
+
+
IN
œ
REF t 100 mV
tpHL
tpLH
VPULL-UP
80%
80%
50%
50%
OUT
20%
20%
Vt
tF
tR
Figure 2. Timing Diagram
NOTE
The propagation delays tpLH and tpHL include the contribution of input offset and hysteresis.
6
Copyright © 2018, Texas Instruments Incorporated
TLV7081
www.ti.com
ZHCSIE1A –MAY 2018–REVISED JUNE 2018
6.8 Typical Characteristics
TA = 25°C, VS = 3.3 V, RPULL-UP = 4.99 kΩ, CL = 15 pF
9
7.5
6
9
TA = -40èC
TA = 25èC
TA = 125èC
TA = -40èC
TA = 25èC
TA = 125èC
7.5
6
4.5
3
4.5
3
1.5
1.5
10
20
30 40 50 70 100
Input Overdrive (mV)
200 300
500
10
20
30 40 50 70 100
Input Overdrive (mV)
200 300
500
tPLH
tPHL
VS = 1.8 V
VS = 1.8 V
Figure 3. Propagation Delay (L-H) vs. Input Overdrive
Figure 4. Propagation Delay (H-L) vs. Input Overdrive
9
9
TA = -40èC
TA = 25èC
TA = 125èC
TA = -40èC
TA = 25èC
TA = 125èC
7.5
6
7.5
6
4.5
3
4.5
3
1.5
1.5
10
20
30 40 50 70 100
Input Overdrive (mV)
200 300
500
10
20
30 40 50 70 100
Input Overdrive (mV)
200 300
500
tPLH
tPHL
VS = 3.3 V
VS = 3.3 V
Figure 5. Propagation Delay (L-H) vs. Input Overdrive
Figure 6. Propagation Delay (H-L) vs. Input Overdrive
1x105
5000
1000
100
10
1x104
1x103
1x102
1x101
1
TA = -40èC
TA = 25èC
TA = 85èC
TA = 125èC
0.1
VPULL-UP = 1.8 V
VPULL-UP = 3.3 V
VPULL-UP = 5.0 V
0.01
1x100
2x10-1
0.002
0.1
1
10
-40
0
40
80
120
160
IN (V)
Temperature (°C)
ibia
ilea
VS = 3.3 V
Figure 7. Input Bias Current vs. IN
Figure 8. Output Leakage Current vs. Temperature
Copyright © 2018, Texas Instruments Incorporated
7
TLV7081
ZHCSIE1A –MAY 2018–REVISED JUNE 2018
www.ti.com
Typical Characteristics (continued)
TA = 25°C, VS = 3.3 V, RPULL-UP = 4.99 kΩ, CL = 15 pF
2
5
1
1
0.1
0.1
TA = -40°C
TA = -40°C
TA = 25°C
TA = 125°C
TA = 25°C
TA = 125°C
0.01
0.01
0.1
0.005
1
10
20
0.1
1
10
50
Iout (Sink) (mA)
Iout (Sink) (mA)
vout
vout
VS = 1.8 V
VS = 3.3 V
Figure 9. Output Voltage Low vs. Output Sink Current
Figure 10. Output Voltage Low vs. Output Sink Current
0.2
10
Temp -40°C
Temp 25°C
Temp 85°C
0.16
Temp 125°C
1
0.12
0.08
0.04
0
0.1
TA = -40°C
TA = 25°C
TA = 125°C
0.01
0.005
1.5
2
2.5
3
3.5
4
4.5
5
5.5
0.1
1
10
100
VS (V)
Iout (Sink) (mA)
vio_
vout
VS = 5 V
Figure 12. Input Offset vs. VS
Figure 11. Output Voltage Low vs. Output Sink Current
0.16
11
10
9
Temp -40°C
Temp 25°C
Temp 85°C
Temp 125°C
VS = 1.8v
VS = 3.3v
VS = 5v
0.14
0.12
0.1
0.08
0.06
0.04
0.02
0
8
7
6
1.5
-40
-20
0
20
40
60
80
100 120 140
2
2.5
3
3.5
4
4.5
5
5.5
Temperature (°C)
VS (V)
vio_
vhys
Figure 13. Input Offset vs. Temperature
Figure 14. Hysteresis vs VS
8
Copyright © 2018, Texas Instruments Incorporated
TLV7081
www.ti.com
ZHCSIE1A –MAY 2018–REVISED JUNE 2018
Typical Characteristics (continued)
TA = 25°C, VS = 3.3 V, RPULL-UP = 4.99 kΩ, CL = 15 pF
20
15
10
5
11
10.5
10
9.5
9
8.5
8
7.5
VS = 1.8v
VS = 3.3v
VS = 5v
7
0
6.5
5
-3.
3
5
-2.
2
5
-1.
1
-
5
-0.
0
1
2
3
4
-40
-20
0
20
40
60
80
100 120 140
-
-
0.5
1.5
2.5
3.5
Temperature (°C)
vos_
vhys
Input Offset (mV)
Distribution Taken from 7,990 Comparators
Figure 15. Hysteresis vs. Temperature
Figure 16. Input Offset Histogram
25
20
15
10
5
600
500
400
300
200
100
Temp -40°C
Temp 25°C
Temp 85°C
Temp 125°C
0
8
9
0
2
4
1.5
2
2.5
3
3.5
VS (V)
4
4.5
5
5.5
1
7.4 7.6 7.8
8.2 8.4 8.6 8.8
9.2 9.4 9.6 9.8
10. 10.
vhys
is_v
Hysteresis (mV)
IN = (V+) - 0.1V (output low), No load.
Distribution Taken from 7,990 Comparators
Figure 18. Supply Current vs. VS
Figure 17. Hysteresis Histogram
600
550
500
450
400
350
300
VS = 1.8v
VS = 3.3v
VS = 5v
-40
-20
0
20
40
60
80
100
120
Temperature (°C)
is_t
IN = (V+) - 0.1V (output low), No load.
Figure 19. Supply Current vs. Temperature
Copyright © 2018, Texas Instruments Incorporated
9
TLV7081
ZHCSIE1A –MAY 2018–REVISED JUNE 2018
www.ti.com
7 Detailed Description
7.1 Overview
The TLV7081 is a single-channel, nano-power comparator that does not need a dedicated power supply
connection, and can operate down to 1.7 V. The comparator is available in an ultra-small, WCSP package
measuring 0.7 mm × 0.7 mm, making the TLV7081 applicable for space-critical designs like smartphones and
other portable or battery-powered applications.
The TLV7081 features a wide input-voltage range that is independent of supply voltage. Having an input range
that is independent of supply voltage allows the TLV7081 to be directly connected to sources that are active
even if the TLV7081 is not powered.
The TLV7081 has an open-drain output stage that can be pulled beyond V+, making it appropriate for level
translators and bipolar to single-ended converters.
7.2 Functional Block Diagram
VREF
VPULL-UP
TLV7081
V+
IN
OUT
+
Bias
POR
V-
7.3 Feature Description
The TLV7081 is a single-channel, nano-power comparator that operates down to 1.7 V. The inverting input is
internally tied to V+ which helps to streamline applications which use supply as the reference. The non-inverting
input IN extends to 5.6 V which is independent of the power supply V+ (1.7 V - 5.5 V) and it's available in an
ultra-small, WCSP package measuring 0.7 mm × 0.7 mm.
7.4 Device Functional Modes
The TLV7081 has a power-on-reset (POR) circuit. While the power supply (VS) is greater than VPOR (typically 1V)
and less than the minimum operating supply voltage, either upon ramp-up or ramp-down, the POR circuitry is
activated.
The POR circuit keeps the output high impedance (logical high) while activated.
When the supply voltage is greater than, or equal to, the minimum supply voltage, the comparator output reflects
the state of the input IN.
10
Copyright © 2018, Texas Instruments Incorporated
TLV7081
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ZHCSIE1A –MAY 2018–REVISED JUNE 2018
Device Functional Modes (continued)
7.4.1 Inputs
The TLV7081 input extends from V- to 5.6 V which is independent of supply. The input IN can be any voltage
within these limits and no phase inversion of the comparator output occurs.
The input of TLV7081 is fault tolerant. It maintains the same high input impedance when V+ is unpowered or
ramping up. The input can be safely driven up to the specified maximum voltage (5.6 V) with V+ = 0 V or any
value up to the maximum specified.
The input bias current is typically 3 pA for input IN voltages between 0 and 5.6 V. The comparator inputs are
protected from undervoltage by internal diodes connected to V-. As the input voltage goes under V-, the
protection diodes become forward biased and begin to conduct causing the input bias current to increase
exponentially. Input bias current typically doubles for every 10°C temperature increase.
7.4.2 Internal Hysteresis
The device hysteresis transfer curve is shown in Figure 20. This curve is a function of three components: VTH
,
VOS, and VHYST
:
•
•
VTH is the actual set voltage or threshold trip voltage.
VOS is the internal offset voltage between IN and V+. This voltage is added to VTH to form the actual trip point
at which the comparator must respond to change output states.
•
VHYST is the internal hysteresis (or trip window) that is designed to reduce comparator sensitivity to noise
(10 mV typical).
VTH + VOS - (VHYST / 2)
VTH + VOS
VTH + VOS + (VHYST / 2)
Figure 20. Hysteresis Transfer Curve
7.4.3 Output
The TLV7081 features an open-drain output stage enabling the output logic levels to be pulled up to an external
source up to 5.5 V independently of the supply voltage.
Copyright © 2018, Texas Instruments Incorporated
11
TLV7081
ZHCSIE1A –MAY 2018–REVISED JUNE 2018
www.ti.com
8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TLV7081 is a 4-pin, nano-power comparator with open-drain output that is well suited for monitoring battery
voltages. The TLV7081's benefits include a small package footprint and a unique input stage that allows the
comparator input to be driven by a voltage source even when the operating voltage for the comparator is turned-
off (zero volts).
8.2 Typical Applications
8.2.1 Nano-Power Battery Monitor
The application of the TLV7081 for an under-voltage detection circuit is shown in Figure 21.
VPULL-UP
REF
1.7 to 5.5 V
TLV7081
VDD
UV
V+
IN
OUT
-
+
Micro-
Controller
Battery
Vœ
Copyright © 2017, Texas Instruments Incorporated
Figure 21. Under-Voltage Detection
8.2.1.1 Design Requirements
For this design, follow these design requirements:
•
•
•
The supply voltage connected to pin (V+) serves as the reference voltage for the comparator and can be any
voltage between 1.7 V and 5.5 V.
The voltage applied to the input pin (IN) can be any voltage in the range of 0 V to 5.6 V. This voltage range is
uniquely independent of the supply voltage applied to pin (V+).
The comparator output pin (OUT) requires a pull-up resistor that sets the output-high logic level (VOH) for the
comparator. VPULL-UP should be connected to the supply voltage of the microcontroller which is monitoring the
comparator output and serves as the level-shifting block for the logic levels in the application.
12
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TLV7081
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ZHCSIE1A –MAY 2018–REVISED JUNE 2018
Typical Applications (continued)
8.2.1.2 Detailed Design Procedure
Instead of being powered directly from the battery, the TLV7081 is powered directly from a voltage reference that
exists in the system. The input to the comparator (IN) is allowed to operate above and below the reference
voltage due to the unique analog front end of the TLV7081. When the battery voltage is above the reference
threshold, the output of the comparator is high and when the battery drops below the threshold of the reference,
the output of the comparator goes low (see Figure 22 for details). For simplicity, the integrated hysteresis of the
comparator is not shown in the timing diagram. Integrated hysteresis is helpful in avoiding glitches at the
comparator output when operating in noisy environments or when the input voltage changes thresholds very
slowly. An open-drain output configuration allows the output logic level of the comparator to be level-shifted to
match the logic level of the receiving device.
8.2.1.3 Application Curve
When the voltage applied to the input pin (IN) falls below the reference threshold (REF), the output pin (OUT) is
pulled low to ground (V-). Moreover, when the input voltage rises above REF, the output of the comparator goes
into a high impedance state and the OUT pin is pulled high by the pull-up resistor and VPULL-UP supply voltage.
IN
REF
VPULL-UP
OUT
(V-)
Figure 22. Under-Voltage Timing Results
8.2.2 Battery Monitoring in Portable Electronics
A recommended circuit diagram for monitoring a battery voltage in a personal electronic device is shown in
Figure 23. In this diagram, the GPIO pin of an application specific integrated circuit (ASIC) serves as the supply
voltage and the voltage reference for the TLV7081. Using a GPIO pin to power the TLV7081 is possible because
of the low quiescent current of the TLV7081. In systems where power consumption needs to be further reduced,
the GPIO pin can be used to power-cycle the TLV7081.
1.8V
Regulator
Output
Logic Levels
0V & 1.8V
Lithium
Ion
GPIO (
)
RPU
R1
Battery
GPIO (input)
PE ASIC
+
TLV7081
R2
Figure 23. Battery Monitor
Copyright © 2018, Texas Instruments Incorporated
13
TLV7081
ZHCSIE1A –MAY 2018–REVISED JUNE 2018
www.ti.com
9 Layout
9.1 Layout Guidelines
A power supply bypass capacitor of 100 nF is recommended when supply output impedance is high, supply
traces are long, or when excessive noise is expected on the supply lines. Bypass capacitors are also
recommended when the comparator output drives a long trace or is required to drive a capacitive load. Due to
the fast rising and falling edge rates and high-output sink and source capability of the TLV7081 output stages,
higher than normal quiescent current can be drawn from the power supply. Under this circumstance, the system
would benefit from a bypass capacitor across the supply pins.
9.2 Layout Example
Figure 24. Layout Example
14
Copyright © 2018, Texas Instruments Incorporated
TLV7081
www.ti.com
ZHCSIE1A –MAY 2018–REVISED JUNE 2018
10 器件和文档支持
10.1 文档支持
10.1.1 相关文档
请参阅如下相关文档：
•
•
•
•
•
TLV7081
TLV7031
TLV7041
TLV7011
TLV7021
10.2 接收文档更新通知
要接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我 进行注册，即可每周接收产
品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
10.3 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，
并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
设计支持
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。
10.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
10.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
10.6 术语表
SLYZ022 — TI 术语表。
这份术语表列出并解释术语、缩写和定义。
11 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此产品说明书的浏览器版本，请查阅左侧的导航栏。
Copyright © 2018, Texas Instruments Incorporated
15
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TLV7081YKAR
ACTIVE
DSBGA
YKA
4
3000 RoHS & Green SAC396 | SNAGCU
Level-1-260C-UNLIM
-40 to 125
W
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Aug-2020
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TLV7081YKAR
TLV7081YKAR
DSBGA
DSBGA
YKA
YKA
4
4
3000
3000
180.0
180.0
8.4
8.4
0.8
0.8
0.8
0.8
0.47
0.47
4.0
4.0
8.0
8.0
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Aug-2020
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TLV7081YKAR
TLV7081YKAR
DSBGA
DSBGA
YKA
YKA
4
4
3000
3000
182.0
182.0
182.0
182.0
20.0
20.0
Pack Materials-Page 2
PACKAGE OUTLINE
YKA0004
DSBGA - 0.4 mm max height
SCALE 14.000
DIE SIZE BALL GRID ARRAY
A
D
B
E
BALL A1
CORNER
0.4 MAX
C
SEATING PLANE
0.05 C
0.18
0.13
BALL TYP
0.35 TYP
B
A
SYMM
0.35
TYP
D: Max = 0.73 mm, Min = 0.67 mm
E: Max = 0.73 mm, Min = 0.67 mm
1
2
0.25
0.15
C A B
4X
0.015
SYMM
4221909/B 08/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
YKA0004
DSBGA - 0.4 mm max height
DIE SIZE BALL GRID ARRAY
(0.35) TYP
4X ( 0.2)
(0.35) TYP
2
1
A
B
SYMM
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:60X
(
0.2)
0.0325 MIN
0.0325 MAX
METAL UNDER
SOLDER MASK
METAL
EXPOSED
METAL
(
0.2)
SOLDER MASK
OPENING
EXPOSED
METAL
SOLDER MASK
OPENING
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
NOT TO SCALE
4221909/B 08/2018
NOTES: (continued)
3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
For more information, see Texas Instruments literature number SNVA009 (www.ti.com/lit/snva009).
www.ti.com
EXAMPLE STENCIL DESIGN
YKA0004
DSBGA - 0.4 mm max height
DIE SIZE BALL GRID ARRAY
(0.35) TYP
4X ( 0.21)
(R0.05) TYP
2
1
A
B
SYMM
(0.35)
TYP
METAL
TYP
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.075 mm - 0.1 mm THICK STENCIL
SCALE:60X
4221909/B 08/2018
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
www.ti.com
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