TLV73311PQDRVRQ1 [TI]
具有使能功能的汽车类 300mA、低 IQ、低压降稳压器 | DRV | 6 | -40 to 150;
| 型号： | TLV73311PQDRVRQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有使能功能的汽车类 300mA、低 IQ、低压降稳压器 | DRV | 6 | -40 to 150 光电二极管 输出元件 稳压器 调节器 |
| 文件： | 总31页 (文件大小：2786K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TLV733P-Q1
ZHCSFD8F – AUGUST 2016 – REVISED OCTOBER 2020
TLV733P-Q1
无电容 300mA 低压降 (LDO) 线性稳压器
1 特性
3 说明
•
符合面向汽车应用的 AEC-Q100 标准：
TLV733P-Q1 系列低压降 (LDO) 线性稳压器尺寸超小
且静态电流较低，可提供 300mA 拉电流，线路和负载
瞬态性能优异。此类器件可提供典型值为 1% 的精度。
– 温度等级 1: – 40 ° C 至 125 ° C 、 T A
•
器件结温范围：
–40°C 至 150°C
TLV733P-Q1 系列采用现代无电容架构设计，无需使
用输入或输出电容即可确保运行稳定。移除输出电容有
助于减小解决方案的尺寸，并且可以消除启动时的浪涌
电流。此外，如果必须使用陶瓷电容，TLV733P-Q1
系列依然可以稳定运行。使用输出电容时，TLV733P-
Q1 系列还可以在器件上电和使能期间提供折返电流控
制。该功能对于电池供电类器件尤为重要。
•
•
•
•
输入电压范围：1.4V 至 5.5V
有无电容器均可实现稳定运行
折返过流保护
封装：
– 2.0mm × 2.0mm WSON-6
– 2.9mm × 1.6mm SOT-23
非常低的压降：300mA 时为 125mV (3.3VOUT
精度：典型值为 1%，最大值为 1.4%
低 IQ：34µA
TLV733P-Q1 系列提供有源下拉电路，处于禁用状态
时可使输出负载快速放电。
•
•
•
•
)
TLV733P-Q1 系列采用 6 引脚 DRV (WSON) 和 5 引脚
DBV (SOT-23) 封装。
可提供固定输出电压：
1.0V 至 3.3V
器件信息 (1)
•
•
高 PSRR：1kHz 时为 50dB
有源输出放电
封装尺寸（标称值）
器件型号
封装
WSON (6)
SOT-23 (5)
2.00mm × 2.00mm
2.90mm × 1.60mm
TLV733P-Q1
2 应用
•
•
•
摄像头模块
(1) 如需了解所有可用封装，请参阅数据表末尾的封装选项附录。
汽车信息娱乐系统
导航系统
180
VOUT = 3.3 V
VOUT = 1.8 V
IN
OUT
GND
160
140
120
100
80
COUT
CIN
TLV733P-Q1
EN
Optional
Optional
ON
OFF
60
典型应用电路
40
20
0
0
30
60
90 120 150 180 210 240 270 300
IOUT (mA)
D020
压降电压与输出电流间的关系
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SBVS283
TLV733P-Q1
ZHCSFD8F – AUGUST 2016 – REVISED OCTOBER 2020
www.ti.com.cn
Table of Contents
7.3 Feature Description...................................................13
7.4 Device Functional Modes..........................................14
8 Application and Implementation..................................15
8.1 Application Information............................................. 15
8.2 Typical Applications.................................................. 16
9 Layout.............................................................................18
9.1 Layout Guidelines..................................................... 18
9.2 Layout Examples...................................................... 18
10 Device and Documentation Support..........................19
10.1 Device Support....................................................... 19
10.2 Receiving Notification of Documentation Updates..19
10.3 Support Resources................................................. 19
10.4 Trademarks.............................................................19
10.5 Electrostatic Discharge Caution..............................19
10.6 Glossary..................................................................19
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................4
6 Specifications.................................................................. 5
6.1 Absolute Maximum Ratings........................................ 5
6.2 ESD Ratings............................................................... 5
6.3 Recommended Operating Conditions.........................5
6.4 Thermal Information....................................................5
6.5 Electrical Characteristics.............................................6
6.6 Timing Requirements..................................................7
6.7 Typical Characteristics................................................8
7 Detailed Description......................................................12
7.1 Overview...................................................................12
7.2 Functional Block Diagram.........................................12
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision E (July 2019) to Revision F (October 2020)
Page
更新了整个文档的表和图的编号格式.................................................................................................................. 1
更改了特定于汽车的特性 项目符号.....................................................................................................................1
•
•
• Changed storage temperature max parameter from 160°C to 150°C................................................................ 5
• Added classificaton levels to ESD Ratings table................................................................................................ 5
Changes from Revision D (December 2018) to Revision E (July 2019)
Page
• Changed description of EN pin in Pin Functions table........................................................................................4
• Deleted typical specifications from VEN(HI) and VEN(LO) parameters in Electrical Characteristics table..............6
• Added maximum specification to ILIM parameter in Electrical Characteristics table........................................... 6
• Added and Output Enable to title and changed first paragraph of Shutdown and Output Enable section....... 13
Changes from Revision C (October 2018) to Revision D (December 2018)
Page
•
将 DBV 封装状态更改为“量产数据”................................................................................................................1
Changes from Revision B (August 2018) to Revision C (October 2018)
Page
•
向文档添加了 DBV 封装（“预发布”状态）..................................................................................................... 1
Changes from Revision A (August 2016) to Revision B (August 2018)
Page
•
添加了器件结温范围 特性项目符号.....................................................................................................................1
• Changed TJ maximum specification from 135°C to 150°C ................................................................................5
• Changed Electrical Characteristics conditions statement from TJ, TA = –40°C to +125°C to TJ = –40°C to
+150°C, TA = –40°C to +125°C ........................................................................................................................6
• Added last 6 rows to VDO parameter ................................................................................................................. 6
• Added second row to IGND parameter, added temperature range to first row test conditions ..........................6
• Changed Typical Characteristics condition statement from TJ = –40°C to +125°C to TJ = –40°C to +150°C ..
8
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• Changed operating junction temperature from –40°C to +135°C to –40°C to +150°C in Overview section....
12
• Changed junction temperature limit from 135°C to 150°C in Thermal Shutdown section................................ 13
Changes from Revision * (August 2016) to Revision A (August 2016)
Page
•
已投入量产..........................................................................................................................................................1
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5 Pin Configuration and Functions
IN
GND
EN
1
2
3
5
OUT
OUT
NC
1
2
3
6
5
4
IN
GND
NC
EN
GND
4
NC
Not to scale
Not to scale
NC – No internal connection.
图 5-2. DBV Package, 5-Pin SOT-23, Top View
图 5-1. DRV Package, 6-Pin WSON, Top View
表 5-1. Pin Functions
NO.
NAME
EN
DRV
4
DBV
I/O
DESCRIPTION
Enable pin. Drive EN greater than VEN(HI) to turn on the regulator.
Drive EN less than VEN(LO) to put the LDO into shutdown mode.
3
2
1
4
I
GND
IN
3
Ground pin
—
Input pin. A small capacitor is recommended from this pin to ground.
See the Input and Output Capacitor Selection section for more details.
6
I
NC
2, 5
No internal connection
—
Regulated output voltage pin. For best transient response, use a small 1-μF ceramic
capacitor from this pin to ground. See the Input and Output Capacitor Selection section for
more details.
OUT
1
5
O
The thermal pad is electrically connected to the GND node.
Connect to the GND plane for improved thermal performance.
Thermal pad
—
—
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6 Specifications
6.1 Absolute Maximum Ratings
over operating junction temperature range (unless otherwise noted); all voltages are with respect to GND(1)
MIN
–0.3
–0.3
–0.3
MAX
UNIT
V
VIN
6.0
VIN + 0.3
3.6
Voltage
VEN
VOUT
IOUT
Current
Internally limited
Indefinite
150
A
Output short-circuit duration
Operating junction, TJ
Storage, Tstg
–40
–65
Temperature
°C
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
6.2 ESD Ratings
VALUE
±2000
±500
UNIT
Human-body model (HBM), per AEC Q100-002(1), classification level 2
Electrostatic
discharge
V(ESD)
All pins
V
Charged-device model (CDM), per AEC Q100-011,
classification level C4B
Corner pins (1, 3, 4, and 6)
±750
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating junction temperature range (unless otherwise noted)
MIN
1.4
1.0
0
NOM
MAX
5.5
UNIT
V
VIN
VOUT
IOUT
VEN
TJ
Input range
Output range
3.3
V
Output current
Enable range
300
VIN
mA
V
0
Junction temperature
Ambient temperature
150
125
°C
°C
–40
–40
TA
6.4 Thermal Information
TLV733P-Q1
THERMAL METRIC(1)
DRV (WSON)
6 PINS
92.5
DBV (SOT-23)
5 PINS
198.3
118.4
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
123.9
61.9
65.8
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
9.7
42.4
ψJT
62.3
65.5
ψJB
RθJC(bot)
30.9
n/a
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Electrical Characteristics
at operating temperature range (TJ = –40°C to +150°C, TA = –40°C to +125°C), VIN = VOUT(nom) + 0.5 V or 2.0 V (whichever
is greater), IOUT = 1 mA, VEN = VIN, and CIN = COUT = 1 µF (unless otherwise noted); all typical values are at TJ = 25°C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VIN
Input voltage
1.4
5.5
V
TJ = 25°C
1%
–1%
–1.4%
DC output accuracy
Undervoltage lockout
1.4%
1.4
–40°C ≤ TJ ≤ 150°C
VIN rising
1.3
UVLO
V
VIN falling
1.25
ΔVI = VOUT(nom) + 0.5 V or 2.0 V (whichever is greater) to
5.5 V
Line regulation
Load regulation
1
mV
mV
ΔVO(ΔVI)
ΔVO(ΔIO)
25
ΔIO = 1 mA to 300 mA
510
450
VOUT = 1.1 V, –40°C ≤ TJ ≤ +125°C
1.2 V ≤ VOUT < 1.5 V, –40°C ≤ TJ ≤
125°C
1.5 V ≤ VOUT < 1.8 V, –40°C ≤ TJ ≤
125°C
400
300
290
1.8 V ≤ VOUT < 2.5 V, –40°C ≤ TJ ≤
125°C
2.5 V ≤ VOUT < 3.3 V, –40°C ≤ TJ ≤
125°C
VOUT = 0.98 ×
125
270
560
VOUT = 3.3 V, –40°C ≤ TJ ≤ 125°C
VDO
Dropout voltage(1)
VOUT(nom)
,
mV
VOUT = 1.1 V, –40°C ≤ TJ ≤ 150°C
IOUT = 300 mA
1.2 V ≤ VOUT < 1.5 V, –40°C ≤ TJ ≤
150°C
490
440
340
330
1.5 V ≤ VOUT < 1.8 V, –40°C ≤ TJ ≤
150°C
1.8 V ≤ VOUT < 2.5 V, –40°C ≤ TJ ≤
150°C
2.5 V ≤ VOUT < 3.3 V, –40°C ≤ TJ ≤
150°C
320
62
78
1
VOUT = 3.3 V, –40°C ≤ TJ ≤ 150°C
34
IOUT = 0 mA, –40°C ≤ TJ ≤ 125°C
IOUT = 0 mA, –40°C ≤ TJ ≤ 150°C
IGND
Ground pin current
Shutdown current
µA
µA
ISHDN
0.1
68
V
EN ≤ 0.35 V, 2.0 V ≤ VIN ≤ 5.5 V, TJ = 25°C
f = 100 Hz
Power-supply
rejection ratio
VOUT = 1.8 V,
IOUT = 300 mA
PSRR
f = 10 kHz
35
dB
f = 100 kHz
28
Vn
Output noise voltage BW = 10 Hz to 100 kHz, VOUT = 1.8 V, IOUT = 10 mA
120
µVRMS
V
EN pin high voltage
(enabled)
VEN(HI)
0.9
EN pin low voltage
(disabled)
VEN(LO)
IEN
0.35
700
V
EN pin current
VEN = 5.5 V
VIN = 2.3 V
0.01
120
µA
Pulldown resistor
Output current limit
Ω
ILIM
IOS
360
mA
VOUT shorted to GND, VOUT = 1.0 V
VOUT shorted to GND, VOUT = 3.3 V
150
170
Short-circuit current
limit
mA
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at operating temperature range (TJ = –40°C to +150°C, TA = –40°C to +125°C), VIN = VOUT(nom) + 0.5 V or 2.0 V (whichever
is greater), IOUT = 1 mA, VEN = VIN, and CIN = COUT = 1 µF (unless otherwise noted); all typical values are at TJ = 25°C
PARAMETER
TEST CONDITIONS
Shutdown, temperature increasing
Reset, temperature decreasing
MIN
TYP
160
140
MAX
UNIT
Tsd
Thermal shutdown
°C
(1) Dropout voltage for the TLV73310P is not valid at room temperature. The device engages undervoltage lockout (VIN < UVLOFALL
)
before the dropout condition is met.
6.6 Timing Requirements
MIN NOM MAX UNIT
Time from EN assertion to 98% × VOUT(nom), VOUT = 1.0 V, IOUT = 0 mA
Time from EN assertion to 98% × VOUT(nom), VOUT = 3.3 V, IOUT = 0 mA
250
tSTR
Startup time
µs
800
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6.7 Typical Characteristics
at operating temperature range (TJ = –40°C to +150°C), VIN = VOUT(nom) + 0.5 V or 2.0 V (whichever is greater),
IOUT = 1 mA, VEN = VIN, and CIN = COUT = 1 µF (unless otherwise noted)
1.816
1.814
1.812
1.81
70
65
60
55
50
45
40
35
30
25
TJ = -40èC
TJ = 0èC
TJ = 25èC
TJ = 85èC
TJ = 125èC
TJ = -40èC
TJ = 0èC
TJ = 25èC
TJ = 85èC
TJ = 125èC
1.808
1.806
1.804
1.802
1.8
1.798
1.796
2
2.5
3
3.5
VIN (V)
4
4.5
5
5.5
0
30
60
90 120 150 180 210 240 270 300
IOUT (mA)
D019
D012
图 6-1. 1.8-V Regulation vs VIN (Line Regulation)
图 6-2. Ground Pin Current vs IOUT and
and Temperature
Temperature
40
100
TJ = 25èC
TJ = -40èC
TJ = 0èC
TJ = 25èC
35
TJ = 85èC
30
25
20
15
10
5
10
1
TJ = 125èC
0.1
0.01
0
0.5
1
1.5
2
2.5
3
VIN (V)
3.5
4
4.5
5
5.5
0
1
2
3
VIN (V)
4
5
6
D013
D015
IOUT = 0 mA
图 6-3. Ground Pin Current vs VIN
图 6-4. Shutdown Current vs VIN and Temperature
0.675
0.65
1
0.9
0.8
0.7
0.6
0.5
0.4
VEN(LO)
VEN(HI)
0.625
0.6
0.575
0.55
0.525
0.5
0.3
0.2
0.1
0
TJ = -40°C
TJ = 0°C
TJ = 25°C
TJ = 85°C
TJ = 125°C
0.475
0.45
0.425
-40
-20
0
20
40
TJ (èC)
60
80
100 120 140
150 200 250 300 350 400 450 500 550 600 650 700
Output Current (mA)
D014
D023
图 6-5. Enable Threshold vs Temperature
图 6-6. Output Voltage vs 1.0-V Foldback Current
Limit and Temperature
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2
1.75
1.5
3.5
3
2.5
2
1.25
1
1.5
1
0.75
0.5
TJ = -40°C
TJ = 0°C
TJ = 25°C
TJ = 85°C
TJ = 125°C
TJ = -40°C
TJ = 0°C
TJ = 25°C
TJ = 85°C
TJ = 125°C
0.25
0.5
0
0
150
200
250
300 350
Output Current (mA)
400
450
500
150
200
250
300 350
Output Current (mA)
400
450
500
D021
D022
图 6-7. Output Voltage vs 1.8-V Foldback Current
图 6-8. Output Voltage vs 3.3-V Foldback Current
Limit and Temperature
Limit and Temperature
10
80
VOUT = 1 V
VOUT = 1.8 V
VOUT = 3.3 V
No Output Capacitor
1-mF Output Capacitor
70
60
50
40
30
20
10
0
1
0.1
0.01
0.005
10
100
1k 10k
Frequency (Hz)
100k
1M
10
100
1k 10k
Frequency (Hz)
100k
1M
D016
D017
IOUT = 300 mA
IOUT = 300 mA
图 6-10. Output Spectral Noise Density vs
图 6-9. Power-Supply Rejection Ratio vs Frequency
Frequency and Output Voltage
VIN (2 V/div)
VIN (2 V/div)
VOUT (1 V/div,
AC Coupled)
VOUT (1 V/div,
AC Coupled)
Time (20 µs/div)
Time (20 µs/div)
IOUT = 10 mA, 1-µF output capacitor
IOUT = 300 mA, 1-µF output capacitor
图 6-11. Line Transient
图 6-12. Line Transient
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VOUT (200 mV/div,
AC Coupled)
VOUT (200 mV/div,
AC Coupled)
ILOAD (100 mA/div)
ILOAD (100 mA/div)
Time (20 µs/div)
Time (20 µs/div)
VIN = 2.0 V, 1-µF output capacitor, output current slew rate =
0.25 A/µs
VIN = 2.0 V, no output capacitor, output current slew rate =
0.25 A/µs
图 6-13. 1.0-V, 50-mA to 300-mA Load Transient
图 6-14. 1.0 V, 50-mA to 300-mA Load Transient
VOUT (100 mV/div,
AC Coupled)
VOUT (100 mV/div,
AC coupled)
ILOAD (100 mA/div)
ILOAD (200 mA/div)
Time (20 µs/div)
Time (50 µs/div)
VIN = 3.8 V,1-µF output capacitor, output current slew rate =
0.25 A/µs
VIN = 3.8 V, no output capacitor, output current slew rate =
0.25 A/µs
图 6-15. 3.3 V, 50-mA to 300-mA Load Transient
图 6-16. 3.3 V, 50-mA to 300-mA Load Transient
VEN (500 mV/div)
VIN (1 V/div)
VOUT (1 V/div)
ILOAD (200 mA/div)
VOUT (500 mV/div)
Time (100 µs/div)
Time (100 µs/div)
RL = 6.2 Ω, 1-µF output capacitor
RL = 6.2 Ω, VEN = VIN, 1-µF output capacitor
图 6-18. Startup with EN
图 6-17. VIN Power-Up and Power-Down
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VOUT (500 mV/div)
VEN (500 mV/div)
VOUT (500 mV/div)
ILOAD (200 mA/div)
Time (100 µs/div)
Time (100 µs/div)
1-µF output capacitor
IOUT = 300 mA, 1-µF output capacitor
图 6-20. Foldback Current Limit Response
图 6-19. Shutdown Response with Enable
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7 Detailed Description
7.1 Overview
The TLV733P-Q1 belongs to a family of low dropout (LDO) linear regulators. These devices consume low
quiescent current and deliver excellent line and load transient performance. These characteristics, combined
with low noise and good PSRR with low dropout voltage, make this family of devices ideal for portable consumer
applications.
This family of regulators offers foldback current limit, shutdown, and thermal protection. The operating junction
temperature for this family of devices is –40°C to +150°C.
7.2 Functional Block Diagram
IN
OUT
Current
Limit
Thermal
Shutdown
UVLO
120 W
Band Gap
EN
Logic
TLV733P-Q1
GND
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7.3 Feature Description
7.3.1 Undervoltage Lockout (UVLO)
The TLV733P-Q1 family uses an undervoltage lockout (UVLO) circuit that disables the output until the input
voltage is greater than the rising UVLO voltage. This circuit ensures that the device does not exhibit any
unpredictable behavior when the supply voltage is lower than the operational range of the internal circuitry.
During UVLO disable, the output is connected to ground with a 120-Ω pulldown resistor.
7.3.2 Shutdown and Output Enable
The enable pin (EN) is active high. Enable the device by forcing the EN pin to exceed VEN(HI). Turn off the device
by forcing the EN pin to drop below VEN(LO). If shutdown capability is not required, connect EN to IN. There is no
internal pulldown resistor connected to the EN pin.
The TLV733P-Q1 has an internal pulldown MOSFET that connects a 120-Ω resistor to ground when the device
is disabled. The discharge time after disabling depends on the output capacitance (COUT) and the load
resistance (RL) in parallel with the 120-Ω pulldown resistor. The time constant is calculated in 方程式 1:
120 · RL
t =
· COUT
120 + RL
(1)
7.3.3 Internal Foldback Current Limit
The TLV733P-Q1 has an internal foldback current limit that protects the regulator during fault conditions. The
current allowed through the device is reduced when the output voltage falls. When the output is shorted, the
LDO supplies a typical current of 150 mA. The output voltage is not regulated when the device is in current limit.
In this condition, the output voltage is the product of the regulated current and the load resistance. When the
device output is shorted, the PMOS pass transistor dissipates power [(VIN – VOUT) × IOS] until thermal shutdown
is triggered and the device turns off. After the device cools down, the internal thermal shutdown circuit turns the
device back on. If the fault condition continues, the device cycles between current limit and thermal shutdown;
see the Thermal Information table for more details.
The foldback current-limit circuit limits the current allowed through the device to current levels lower than the
minimum current limit at a nominal VOUT current limit (ILIM) during startup. See 图 6-6 to 图 6-8 for typical
foldback current limit values. If the output is loaded by a constant-current load during startup, or if the output
voltage is negative when the device is enabled, then the load current demanded by the load can exceed the
foldback current limit and the device may not rise to the full output voltage. For constant-current loads, disable
the output load until the TLV733P-Q1 has fully risen to the nominal output voltage.
The TLV733P-Q1 PMOS pass element has an intrinsic body diode that conducts current when the voltage at the
OUT pin exceeds the voltage at the IN pin. Do not force the output voltage to exceed the input voltage because
excessively high current can flow through the body diode.
7.3.4 Thermal Shutdown
Thermal shutdown protection disables the output when the junction temperature rises to approximately 160°C.
Disabling the device eliminates the power dissipated by the device, allowing the device to cool. When the
junction temperature cools to approximately 140°C, the output circuitry is again enabled. Depending on power
dissipation, thermal resistance, and ambient temperature, the thermal protection circuit can cycle on and off.
This cycling limits regulator dissipation, protecting the device from damage as a result of overheating.
Activating the thermal shutdown feature usually indicates excessive power dissipation as a result of the product
of the (VIN – VOUT) voltage and the load current. For reliable operation, limit junction temperature to 150°C
(maximum). To estimate the margin of safety in a complete design, increase the ambient temperature until the
thermal protection is triggered; use worst-case loads and signal conditions.
The TLV733P-Q1 internal protection circuitry protects against overload conditions but is not intended to be
activated in normal operation. Continuously running the TLV733P-Q1 into thermal shutdown degrades device
reliability.
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7.4 Device Functional Modes
7.4.1 Normal Operation
The device regulates to the nominal output voltage under the following conditions:
• The input voltage has previously exceeded the UVLO rising voltage and has not decreased below the UVLO
falling threshold.
• The input voltage is greater than the nominal output voltage added to the dropout voltage.
• The enable voltage has previously exceeded the enable rising threshold voltage and has not decreased
below the enable falling threshold.
• The output current is less than the current limit.
• The device junction temperature is less than the thermal shutdown temperature.
7.4.2 Dropout Operation
If the input voltage is lower than the nominal output voltage plus the specified dropout voltage, but all other
conditions are met for normal operation, the device operates in dropout mode. In this condition, the output
voltage is the same as the input voltage minus the dropout voltage. The transient performance of the device is
significantly degraded because the pass device is in a triode state and no longer controls the current through the
LDO. Line or load transients in dropout can result in large output voltage deviations.
7.4.3 Disabled
The device is disabled under the following conditions:
• The input voltage is less than the UVLO falling voltage, or has not yet exceeded the UVLO rising threshold.
• The enable voltage is less than the enable falling threshold voltage or has not yet exceeded the enable rising
threshold.
• The device junction temperature is greater than the thermal shutdown temperature.
When the device is disabled, the active pulldown resistor discharges the output.
表 7-1 shows the conditions that lead to the different modes of operation.
表 7-1. Device Functional Mode Comparison
PARAMETER
OPERATING MODE
VIN
VEN
IOUT
TJ
VIN > VOUT(nom) + VDO
and VIN > UVLORISE
Normal mode
Dropout mode
VEN > VEN(HI)
VEN > VEN(HI)
IOUT < ILIM
IOUT < ILIM
TJ < 160°C
TJ < 160°C
UVLORISE < VIN < VOUT(nom) + VDO
Disabled mode
(any true condition
disables the device)
VIN < UVLOFALL
VEN < VEN(LO)
TJ > 160°C
—
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8 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
8.1 Application Information
8.1.1 Input and Output Capacitor Selection
The TLV733P-Q1 uses an advanced internal control loop to obtain stable operation both with and without the
use of input or output capacitors. Dynamic performance is improved with the use of an output capacitor, and can
be improved with an input capacitor. An output capacitance of 0.1 μF or larger generally provides good dynamic
response. Use X5R- and X7R-type ceramic capacitors because these capacitors have minimal variation in value
and equivalent series resistance (ESR) over temperature.
Although an input capacitor is not required for stability, increased output impedance from the input supply can
compromise the performance of the TLV733P-Q1. Good analog design practice is to connect a 0.1-µF to 1-µF
capacitor from IN to GND. This capacitor counteracts reactive input sources and improves transient response,
input ripple, and PSRR. Use an input capacitor if the source impedance is greater than 0.5 Ω. Use a higher-
value capacitor if large, fast rise-time load transients are anticipated, or if the device is located several inches
from the input power source.
图 8-1 shows the transient performance improvements with an external 1-µF capacitor on the output versus no
output capacitor. The data in this figure are taken with an increasing load step from 50 mA to 300 mA, and the
peak output voltage deviation (load transient response) is measured. For low output current slew rates,
(< 0.1 A/µs), the transient performance of the device is similar with or without an output capacitor. When the
current slew rate is increased, the peak voltage deviation is significantly increased. For loads that exhibit fast
current slew rates above 0.1 A/µs, use an output capacitor. For best performance, the maximum recommended
output capacitance is 100 µF.
35
1-mF COUT
COUT Removed
30
25
20
15
10
5
0
0.01
0.1
Output Load Transient Slew Rate (A/ms)
1
D027
Output current stepped from 50 mA to 300 mA, output voltage change measured at positive dI/dt
图 8-1. Output Voltage Deviation vs Load Step Slew Rate
Some applications benefit from the removal of the output capacitor. In addition to space and cost savings, the
removal of the output capacitor lowers inrush current as a result of eliminating the required current flow into the
output capacitor at startup. In these cases, take care to ensure that the load is tolerant of the additional output
voltage deviations.
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8.1.2 Dropout Voltage
The TLV733P-Q1 uses a PMOS pass transistor to achieve low dropout. When (VIN – VOUT) is less than the
dropout voltage (VDO), the PMOS pass device is in the linear region of operation and the input-to-output
resistance is the RDS(ON) of the PMOS pass element. VDO scales approximately with output current because the
PMOS device behaves like a resistor in dropout mode. As with any linear regulator, PSRR and transient
response degrade when (VIN – VOUT) approaches dropout operation.
8.2 Typical Applications
8.2.1 DC-DC Converter Post Regulation
VOUT
1.8 V
VOUT
1.5 V
IN
OUT
CIN
1 µF
COUT
1 µF
DC-DC
Converter
Load
TLV733P-Q1
EN
GND
ON
OFF
图 8-2. DC-DC Converter Post Regulation
8.2.1.1 Design Requirements
表 8-1. Design Parameters
PARAMETER
DESIGN REQUIREMENT
Input voltage
Output voltage
1.8 V, ±5%
1.5 V, ±1%
Output current
200-mA dc, 300-mA peak
< 10%, 1-A/µs load step from 50 mA to 200 mA
85°C
Output voltage transient deviation
Maximum ambient temperature
8.2.1.2 Design Considerations
The TLV733P-Q1 can provide post regulation after a dc-dc converter, as shown in 图 8-2. For this application,
input and output capacitors are required to achieve the output voltage transient requirements. Capacitance
values of 1 µF are selected to give the maximum output capacitance in a small, low-cost package.
8.2.1.3 Application Curve
图 8-3 shows the TLV733P-Q1 startup, regulation, and shutdown as specified in 图 8-2.
VIN (500 mV/div)
VOUT (500 mV/div)
IOUT (100 mA/div)
Time (50 µs/div)
图 8-3. 1.8-V to 1.5-V Regulation at 300 mA
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8.2.2 Capacitor-Free Operation from a Battery Input Supply
IN
OUT
TLV733P-Q1
VBAT
Load
EN
GND
图 8-4. Capacitor-Free Operation from a Battery Input Supply
8.2.2.1 Design Requirements
表 8-2. Design Parameters
PARAMETER
Input voltage
DESIGN REQUIREMENT
3.0 V to 1.8 V (two 1.5-V batteries)
1.0 V, ±1%
Output voltage
Input current
200 mA, maximum
100-mA dc
Output load
Maximum ambient temperature
70°C
8.2.2.2 Design Considerations
The TLV733P-Q1 can be directly powered off of a battery, as shown in 图 8-4. An input capacitor is not required
for this design because of the direct low impedance connection to the battery.
Eliminating the output capacitor allows for the minimal possible inrush current during startup, ensuring that the
200-mA maximum input current is not exceeded.
8.2.2.3 Application Curve
图 8-5 shows no inrush with the capacitor-free startup.
VIN (1 V/div)
VOUT (500 mV/div)
IIN (100 mA/div)
Time (50 µs/div)
图 8-5. No Inrush Startup, 3.0-V to 1.0-V Regulation
Power Supply Recommendations
Connect a low output impedance power supply directly to the IN pin of the TLV733P-Q1. Inductive impedances
between the input supply and the IN pin can create significant voltage excursions at the IN pin during startup or
load transient events. If inductive impedances are unavoidable, use an input capacitor.
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9 Layout
9.1 Layout Guidelines
• Place input and output capacitors as close to the device as possible.
• Use copper planes for device connections, in order to optimize thermal performance.
• Place thermal vias around the device to distribute the heat.
图 9-1 and 图 9-2 show examples of how the TLV733P-Q1 is laid out on a printed circuit board (PCB).
9.2 Layout Examples
Input Capacitor
Input
Trace
Enable
Trace
Grounded
Thermal Plane
NC
EN
Input Ground
Plane
IN
Thermal Pad
GND
NC
Output Trace
OUT
Grounded
Thermal Plane
Output Ground
Plane
Output Capacitor
Designates thermal vias.
图 9-1. WSON Layout Example
VOUT
VIN
5
1
CIN
COUT
2
3
4
EN
GND PLANE
Represents via used for
application specific connections
图 9-2. SOT-23 Layout Example
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10 Device and Documentation Support
10.1 Device Support
10.1.1 Development Support
10.1.1.1 Evaluation Module
An evaluation module (EVM) is available to assist in the initial circuit performance evaluation using the TLV733P-
Q1. The TLV73312PEVM-643 evaluation module (and related user guide) can be requested at the Texas
Instruments website through the product folders or purchased directly from the TI eStore.
10.1.2 Device Nomenclature
表 10-1. Device Nomenclature (1) (2)
PRODUCT
VOUT
xx(x) is the nominal output voltage. For output voltages with a resolution of 100 mV, two digits are used
in the ordering number; otherwise, three digits are used (for example, 28 = 2.8 V; 125 = 1.25 V).
P indicates an active output discharge feature. All members of the TLV733P-Q1 family will actively
discharge the output when the device is disabled.
TLV733P-Q1xx(x)PyyyzQ1
yyy is the package designator.
z is the package quantity. R is for reel (3000 pieces), T is for tape (250 pieces).
(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or visit the
device product folder on www.ti.com.
(2) Output voltages from 1.0 V to 3.3 V in 50-mV increments are available. Contact the factory for details and availability.
10.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
10.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
10.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
10.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
10.6 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TLV73310PQDBVRQ1
TLV73310PQDRVRQ1
TLV73311PQDBVRQ1
TLV73311PQDRVRQ1
TLV73312PQDBVRQ1
TLV73312PQDRVRQ1
TLV73315PQDBVRQ1
TLV73315PQDRVRQ1
TLV73318PQDBVRQ1
TLV73318PQDRVRQ1
TLV73325PQDBVRQ1
TLV73325PQDRVRQ1
TLV73328PQDBVRQ1
TLV73328PQDRVRQ1
TLV73330PQDBVRQ1
TLV73333PQDBVRQ1
TLV73333PQDRVRQ1
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOT-23
WSON
SOT-23
WSON
SOT-23
WSON
SOT-23
WSON
SOT-23
WSON
SOT-23
WSON
SOT-23
WSON
SOT-23
SOT-23
WSON
DBV
DRV
DBV
DRV
DBV
DRV
DBV
DRV
DBV
DRV
DBV
DRV
DBV
DRV
DBV
DBV
DRV
5
6
5
6
5
6
5
6
5
6
5
6
5
6
5
5
6
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-1-260C-UNLIM
Level-2-260C-1 YEAR
Level-1-260C-UNLIM
Level-2-260C-1 YEAR
Level-1-260C-UNLIM
Level-2-260C-1 YEAR
Level-1-260C-UNLIM
Level-2-260C-1 YEAR
Level-1-260C-UNLIM
Level-2-260C-1 YEAR
Level-1-260C-UNLIM
Level-2-260C-1 YEAR
Level-1-260C-UNLIM
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-1-260C-UNLIM
-40 to 125
-40 to 150
-40 to 125
-40 to 150
-40 to 125
-40 to 150
-40 to 125
-40 to 150
-40 to 125
-40 to 150
-40 to 125
-40 to 150
-40 to 125
-40 to 150
-40 to 125
-40 to 125
-40 to 150
1P5F
12P
NIPDAUAG
NIPDAU
1P6F
12Q
NIPDAUAG
NIPDAU
1P7F
12R
NIPDAUAG
NIPDAU
1P8F
12S
NIPDAUAG
NIPDAU
1P9F
12T
NIPDAUAG
NIPDAU
1PAF
12U
NIPDAUAG
NIPDAU
1PBF
12V
NIPDAUAG
NIPDAU
1PCF
1PDF
12W
NIPDAU
NIPDAUAG
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
18-Mar-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TLV73310PQDBVRQ1 SOT-23
TLV73310PQDRVRQ1 WSON
TLV73311PQDBVRQ1 SOT-23
TLV73311PQDRVRQ1 WSON
TLV73312PQDBVRQ1 SOT-23
TLV73312PQDRVRQ1 WSON
TLV73315PQDBVRQ1 SOT-23
TLV73315PQDRVRQ1 WSON
TLV73318PQDBVRQ1 SOT-23
TLV73318PQDRVRQ1 WSON
TLV73325PQDBVRQ1 SOT-23
TLV73325PQDRVRQ1 WSON
TLV73328PQDBVRQ1 SOT-23
TLV73328PQDRVRQ1 WSON
DBV
DRV
DBV
DRV
DBV
DRV
DBV
DRV
DBV
DRV
DBV
DRV
DBV
DRV
DBV
DBV
DRV
5
6
5
6
5
6
5
6
5
6
5
6
5
6
5
5
6
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
180.0
179.0
180.0
179.0
180.0
179.0
180.0
179.0
180.0
179.0
180.0
179.0
180.0
179.0
180.0
180.0
180.0
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
3.2
2.2
3.2
2.2
3.2
2.2
3.2
2.2
3.2
2.2
3.2
2.2
3.2
2.2
3.2
3.2
2.2
3.2
2.2
3.2
2.2
3.2
2.2
3.2
2.2
3.2
2.2
3.2
2.2
3.2
2.2
3.2
3.2
2.2
1.4
1.2
1.4
1.2
1.4
1.2
1.4
1.2
1.4
1.2
1.4
1.2
1.4
1.2
1.4
1.4
1.2
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
Q3
Q2
Q3
Q2
Q3
Q2
Q3
Q2
Q3
Q2
Q3
Q2
Q3
Q2
Q3
Q3
Q2
TLV73330PQDBVRQ1 SOT-23
TLV73333PQDBVRQ1 SOT-23
TLV73333PQDRVRQ1
WSON
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
18-Mar-2021
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TLV73310PQDBVRQ1
TLV73310PQDRVRQ1
TLV73311PQDBVRQ1
TLV73311PQDRVRQ1
TLV73312PQDBVRQ1
TLV73312PQDRVRQ1
TLV73315PQDBVRQ1
TLV73315PQDRVRQ1
TLV73318PQDBVRQ1
TLV73318PQDRVRQ1
TLV73325PQDBVRQ1
TLV73325PQDRVRQ1
TLV73328PQDBVRQ1
TLV73328PQDRVRQ1
TLV73330PQDBVRQ1
TLV73333PQDBVRQ1
TLV73333PQDRVRQ1
SOT-23
WSON
SOT-23
WSON
SOT-23
WSON
SOT-23
WSON
SOT-23
WSON
SOT-23
WSON
SOT-23
WSON
SOT-23
SOT-23
WSON
DBV
DRV
DBV
DRV
DBV
DRV
DBV
DRV
DBV
DRV
DBV
DRV
DBV
DRV
DBV
DBV
DRV
5
6
5
6
5
6
5
6
5
6
5
6
5
6
5
5
6
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
210.0
200.0
210.0
200.0
210.0
200.0
210.0
200.0
210.0
200.0
210.0
200.0
210.0
200.0
210.0
210.0
200.0
185.0
183.0
185.0
183.0
185.0
183.0
185.0
183.0
185.0
183.0
185.0
183.0
185.0
183.0
185.0
185.0
183.0
35.0
25.0
35.0
25.0
35.0
25.0
35.0
25.0
35.0
25.0
35.0
25.0
35.0
25.0
35.0
35.0
25.0
Pack Materials-Page 2
PACKAGE OUTLINE
DBV0005A
SOT-23 - 1.45 mm max height
S
C
A
L
E
4
.
0
0
0
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
0.1 C
1.75
1.45
1.45
0.90
B
A
PIN 1
INDEX AREA
1
2
5
(0.1)
2X 0.95
1.9
3.05
2.75
1.9
(0.15)
4
3
0.5
5X
0.3
0.15
0.00
(1.1)
TYP
0.2
C A B
NOTE 5
0.25
GAGE PLANE
0.22
0.08
TYP
8
0
TYP
0.6
0.3
TYP
SEATING PLANE
4214839/G 03/2023
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.25 mm per side.
5. Support pin may differ or may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X (0.95)
4
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214839/G 03/2023
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X(0.95)
4
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214839/G 03/2023
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
GENERIC PACKAGE VIEW
DRV 6
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4206925/F
PACKAGE OUTLINE
DRV0006D
WSON - 0.8 mm max height
SCALE 5.500
PLASTIC SMALL OUTLINE - NO LEAD
2.1
1.9
A
B
PIN 1 INDEX AREA
2.1
1.9
0.8
0.7
C
SEATING PLANE
0.08 C
(0.2) TYP
0.05
0.00
1
0.1
EXPOSED
THERMAL PAD
3
4
6
2X
7
1.3
1.6 0.1
1
4X 0.65
0.35
0.25
6X
PIN 1 ID
(OPTIONAL)
0.3
0.2
6X
0.1
C A B
C
0.05
4225563/A 12/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
DRV0006D
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
6X (0.45)
6X (0.3)
(1)
1
7
6
SYMM
(1.6)
(1.1)
4X (0.65)
4
3
SYMM
(1.95)
(R0.05) TYP
(
0.2) VIA
TYP
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:25X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
EXPOSED
METAL
EXPOSED
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4225563/A 12/2019
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If some or all are implemented, recommended via locations are shown.
www.ti.com
EXAMPLE STENCIL DESIGN
DRV0006D
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
SYMM
7
6X (0.45)
METAL
1
6
6X (0.3)
(0.45)
SYMM
4X (0.65)
(0.7)
4
3
(R0.05) TYP
(1)
(1.95)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD #7
88% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:30X
4225563/A 12/2019
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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