TLV74133PDBVR [TI]
具有主动输出放电和使能功能的 150mA、低压降稳压器 | DBV | 5 | -40 to 125;
| 型号： | TLV74133PDBVR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有主动输出放电和使能功能的 150mA、低压降稳压器 | DBV | 5 | -40 to 125 光电二极管 输出元件 稳压器 调节器 |
| 文件： | 总33页 (文件大小：1525K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Support &
Community
Product
Folder
Order
Now
Tools &
Software
Technical
Documents
TLV741P
ZHCSGF1A –JULY 2017–REVISED SEPTEMBER 2018
具有折返式电流限制的 TLV741P 150mA 低压差稳压器
1 特性
3 说明
1
•
•
•
•
输入电压范围：1.4V 至 5.5V
TLV741P 低压降线性稳压器 (LDO) 是一款低静态电流
器件，具有出色的线路和负载瞬态性能，适用于功耗敏
使用 1µF 陶瓷电容器实现稳定工作
折返过流保护
感型 应用。此器件提供了 1% 的典型精度。
封装：
TLV741P 旨在使用小型的 1µF 输出电容器实现稳定工
作。
–
–
5 引脚 SOT-23
4 引脚 X2SON
TLV741P 可在器件加电和使能期间提供浪涌电流控
制。TLV741P 将输入电流限制为定义的电流限值，从
而防止从输入电源流出的电流过大。该功能对于电池供
电型器件尤为重要。
•
•
•
•
超低压降：150mA 时为 230mV
准确度：1%
低 IQ：50µA
可提供固定输出电压：
1V 至 3.3V
TLV741P 采用标准 DBV (SOT-23) 和 DQN (X2SON)
封装。TLV741P 提供了有源下拉电路，用于对输出负
载进行快速放电。
•
•
高 PSRR：1kHz 时为 65dB
有源输出放电（仅限 P 版本）
器件信息(1)
2 应用
器件名称
TLV741P
封装
SOT-23 (5)
X2SON (4)
封装尺寸
•
•
•
掌上电脑 (PDA) 和电池供电便携式设备
2.90mm × 1.60mm
1.00mm x 1.00mm
MP3 播放器和其它手持产品
无线局域网 (WLAN) 及其他 PC 附加卡
(1) 如需了解所有可用封装，请参阅数据表末尾的封装选项附录。
典型应用电路
压降电压与输出电流间的关系
350
VOUT = 1.8 V
VOUT = 3.3 V
IN
OUT
300
TLV741P
COUT
CIN
250
200
150
100
50
EN
GND
ON
OFF
0
0
15
30
45
60
Output Current (mA)
75
90 105 120 135 150
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SBVS309
TLV741P
ZHCSGF1A –JULY 2017–REVISED SEPTEMBER 2018
www.ti.com.cn
目录
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 4
6.5 Electrical Characteristics........................................... 5
6.6 Typical Characteristics.............................................. 7
Detailed Description ............................................ 11
7.1 Overview ................................................................. 11
7.2 Functional Block Diagram ....................................... 11
7.3 Feature Description................................................. 12
7.4 Device Functional Modes........................................ 13
8
9
Application and Implementation ........................ 14
8.1 Application Information............................................ 14
8.2 Typical Application .................................................. 15
8.3 What to Do and What Not to Do ............................. 16
Power Supply Recommendations...................... 17
10 Layout................................................................... 17
10.1 Layout Guidelines ................................................. 17
10.2 Layout Examples................................................... 17
10.3 Power Dissipation ................................................. 18
11 器件和文档支持 ..................................................... 19
11.1 文档支持................................................................ 19
11.2 接收文档更新通知 ................................................. 19
11.3 社区资源................................................................ 19
11.4 商标....................................................................... 19
11.5 静电放电警告......................................................... 19
11.6 术语表 ................................................................... 19
12 机械、封装和可订购信息....................................... 19
7
4 修订历史记录
Changes from Original (July 2017) to Revision A
Page
•
已添加 在数据表中添加 DQN (X2SON) 封装.......................................................................................................................... 1
2
Copyright © 2017–2018, Texas Instruments Incorporated
TLV741P
www.ti.com.cn
ZHCSGF1A –JULY 2017–REVISED SEPTEMBER 2018
5 Pin Configuration and Functions
DBV Package
5-Pin SOT-23
Top View
DQN Package
4-Pin X2SON With Exposed Thermal Pad
Top View
OUT
GND
1
4
3
IN
IN
GND
EN
1
2
3
5
OUT
NC
Thermal Pad
4
2
EN
Not to scale
Not to scale
Pin Functions
PIN
NO.
I/O
DESCRIPTION
NAME
SOT-23
X2SON
Enable pin. Driving EN over 0.9 V turns on the regulator.
Driving EN below 0.4 V puts the regulator into shutdown mode.
EN
GND
IN
3
2
1
4
3
2
I
—
I
Ground pin
Input pin. Use a small capacitor from this pin to ground. See the Input and Output Capacitor
Considerations section for more details.
4
NC
—
—
No internal connection
Regulated output voltage pin. For best transient response, use a small 1-µF ceramic capacitor
from this pin to ground. See the Input and Output Capacitor Considerations section for more
details.
OUT
5
1
O
Thermal
pad
The thermal pad is electrically connected to the GND node. Connect the thermal pad to the
ground plane for improved thermal performance.
—
—
—
Copyright © 2017–2018, Texas Instruments Incorporated
3
TLV741P
ZHCSGF1A –JULY 2017–REVISED SEPTEMBER 2018
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
over operating junction temperature range (unless otherwise noted). All voltages are with respect to GND.(1)
MIN
MAX
UNIT
Input, VIN
–0.3
–0.3
–0.3
6
Voltage
Enable, VEN
VIN + 0.3
3.6
V
Output, VOUT
Current
Maximum output, IOUT(max)
Internally limited
Indefinite
Output short-circuit duration
Total power dissipation
Continuous, PD(tot)
Junction, TJ
See Thermal Information
–55
–55
125
150
Temperature
°C
Storage, Tstg
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1)
±2000
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per JEDEC specification JESD22-C101,
all pins(2)
±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating junction temperature range (unless otherwise noted)
MIN
1.4
0
NOM
MAX
5.5
UNIT
VIN
Input voltage
V
V
VEN
IOUT
CIN
Enable range
VIN
Output current
0
150
mA
µF
µF
°C
Input capacitor
0
1
COUT
TJ
Output capacitor
Operating junction temperature
1
100
125
–40
6.4 Thermal Information
TLV741P
THERMAL METRIC(1)
DQN (X2SON)
DBV (SOT-23)
5 PINS
249
UNIT
4 PINS
228.5
210.4
174.7
21.2
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
172.7
76.7
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
49.7
ψJB
174.5
140.6
75.8
RθJC(bot)
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report
4
Copyright © 2017–2018, Texas Instruments Incorporated
TLV741P
www.ti.com.cn
ZHCSGF1A –JULY 2017–REVISED SEPTEMBER 2018
6.5 Electrical Characteristics
over operating temperature range TJ = –40°C to +125°C, VIN(nom) = VOUT(nom) + 0.5 V or VIN(nom) = 2 V (whichever is greater),
IOUT = 1 mA, VEN = VIN, and COUT = 1 µF (unless otherwise noted). Typical values are at TJ = 25°C.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Output voltage
range
VOUT
1
3.3
V
V
OUT ≥ 1.8 V
–1%
–20
1%
20
TJ = 25°C
VOUT < 1.8 V
TJ = 25°C
mV
mV
DC output accuracy
V
OUT ≥ 1.2 V
–1.5%
–50
1.5%
50
–40°C ≤ TJ ≤ 125°C
VOUT < 1.2 V
–40°C ≤ TJ ≤ 125°C
Maximum {VOUT(nom) + 0.5 V
VIN = 2 V} ≤ VIN ≤ 5.5 V
ΔVOUT(ΔVIN)
Line regulation
Load regulation
1
10
5
30
mV
mV
ΔVOUT(ΔIOUT)
0 mA ≤ IOUT ≤ 150 mA
1 V ≤ VOUT < 1.8 V
IOUT = 150 mA
600
900
VOUT = 1.1 V
IOUT = 100 mA
470
70
600
575
481
445
1.8 V ≤ VOUT < 2.1 V
IOUT = 30 mA
1.8 V ≤ VOUT < 2.1 V
IOUT = 150 mA
350
90
2.1 V ≤ VOUT < 2.5 V
IOUT = 30 mA
VOUT = 0.98 × VOUT(nom)
,
TJ = –40°C to 85°C
2.1 V ≤ VOUT < 2.5 V
IOUT = 150 mA
290
50
2.5 V ≤ VOUT < 3 V
IOUT = 30 mA
2.5 V ≤ VOUT < 3 V
IOUT = 150 mA
246
46
VDO
Dropout voltage
mV
3 V ≤ VOUT < 3.6 V
IOUT = 30 mA
3 V ≤ VOUT < 3.6 V
IOUT = 150 mA
230
600
470
350
290
246
420
1020
720
1 V ≤ VOUT < 1.8 V
IOUT = 150 mA
VOUT = 1.1 V
IOUT = 100 mA
1.8 V ≤ VOUT < 2.1 V
IOUT = 150 mA
695
VOUT = 0.98 × VOUT(nom)
TJ = –40°C to 125°C
2.1 V ≤ VOUT < 2.5 V
IOUT = 150 mA
601
2.5 V ≤ VOUT < 3 V
IOUT = 150 mA
565
3 V ≤ VOUT < 3.6 V
IOUT = 150 mA
230
50
540
75
1
IGND
Ground pin current
Shutdown current
IOUT = 0 mA
µA
µA
V
EN ≤ 0.4 V, 2 V ≤ VIN ≤ 5.5 V
ISHUTDOWN
0.1
TJ = 25°C
f = 100 Hz
f = 10 kHz
f = 1 MHz
70
55
55
VIN = 3.3 V
VOUT = 2.8 V
IOUT = 30 mA
Power-supply
rejection ratio
PSRR
dB
BW = 100 Hz to 100 kHz
VIN = 2.3 V
VOUT = 1.8 V
Vn
Output noise voltage
Start-up time(1)
73
µVRMS
IOUT = 10 mA
COUT = 1 μF
IOUT = 150 mA
tSTR
100
µs
(1) Start-up time is the time from EN assertion to (0.98 × VOUT(nom)).
Copyright © 2017–2018, Texas Instruments Incorporated
5
TLV741P
ZHCSGF1A –JULY 2017–REVISED SEPTEMBER 2018
www.ti.com.cn
Electrical Characteristics (continued)
over operating temperature range TJ = –40°C to +125°C, VIN(nom) = VOUT(nom) + 0.5 V or VIN(nom) = 2 V (whichever is greater),
IOUT = 1 mA, VEN = VIN, and COUT = 1 µF (unless otherwise noted). Typical values are at TJ = 25°C.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Enable high
(enabled)
VHI
0.9
VIN
V
Enable low
(disabled)
VLO
0
0.4
V
IEN
EN pin current
EN = 5.5 V
VIN = 4 V
0.01
120
µA
RPULLDOWN
Pulldown resistor
Ω
VIN = 3.8 V
VOUT = 3.3 V
TJ = –40 to 85°C
180
180
180
VIN = 2.25 V
VOUT = 1.8 V
TJ = –40 to 85°C
ILIM
Output current limit
mA
VIN = 2 V
VOUT = 1.2 V
TJ = –40 to 85°C
ISC
Short-circuit current VOUT = 0 V
Shutdown, temperature increasing
Reset, temperature decreasing
40
158
140
mA
°C
TSD
Thermal shutdown
6
版权 © 2017–2018, Texas Instruments Incorporated
TLV741P
www.ti.com.cn
ZHCSGF1A –JULY 2017–REVISED SEPTEMBER 2018
6.6 Typical Characteristics
over operating temperature range TJ = –40°C to +125°C, VIN = VOUT(nom) + 0.5 V or 2 V (whichever is greater), IOUT = 10 mA,
VEN = VIN, COUT = 1 µF, and VOUT(nom) = 1.8 V (unless otherwise noted). Typical values are at TJ = 25°C.
1.802
1.801
1.8
1.8
1.798
1.796
1.794
1.792
1.79
TJ = -40èC
TJ = 0èC
TJ = 25èC
TJ = 85èC
TJ = 125èC
TJ = -40èC
TJ = 0èC
TJ = 25èC
TJ = 85èC
TJ = 125èC
1.799
1.798
1.797
1.796
1.795
1.794
1.793
1.788
1.786
2
2.5
3
3.5
4
4.5
5
5.5
0
20
40
60
80
100
120
140
160
Input Voltage (V)
Output Current (mA)
图 1. 1.8-V Line Regulation vs VIN and Temperature
图 2. 1.8-V Load Regulation vs IOUT and Temperature
1.798
500
TJ = -40èC
TJ = 0èC
TJ = 25èC
TJ = 85èC
TJ = 125èC
1.7975
1.797
400
300
200
100
0
1.7965
1.796
1.7955
1.795
1.7945
1.794
-40
-20
0
20
40
60
80
100 120 140
0
25
50
75
100
125
150
Temperature (èC)
Output Current (mA)
图 3. 1.8-V Output Voltage Over Temperature
图 4. 1.8-V Dropout Voltage vs IOUT and Temperature
400
350
300
250
200
150
100
50
65
TJ = -40èC
TJ = 0èC
TJ = 25èC
TJ = 85èC
TJ = 125èC
TJ = -40èC
TJ = 0èC
TJ = 25èC
TJ = 85èC
TJ = 125èC
62.5
60
57.5
55
52.5
50
47.5
45
42.5
40
37.5
35
32.5
30
0
0
25
50
75
100
125
150
2
2.5
3
3.5
4
4.5
5
5.5
Output Current (mA)
Input Voltage (V)
图 5. 3.3-V Dropout Voltage vs IOUT and Temperature
图 6. Ground Pin Current vs VIN and Temperature
版权 © 2017–2018, Texas Instruments Incorporated
7
TLV741P
ZHCSGF1A –JULY 2017–REVISED SEPTEMBER 2018
www.ti.com.cn
Typical Characteristics (接下页)
over operating temperature range TJ = –40°C to +125°C, VIN = VOUT(nom) + 0.5 V or 2 V (whichever is greater), IOUT = 10 mA,
VEN = VIN, COUT = 1 µF, and VOUT(nom) = 1.8 V (unless otherwise noted). Typical values are at TJ = 25°C.
80
75
70
65
60
55
50
45
40
35
500
300
200
100
50
30
20
10
5
TJ = -40èC
TJ = 0èC
TJ = 25èC
TJ = 85èC
TJ = 125èC
TJ = -40èC
TJ = 0èC
TJ = 25èC
TJ = 85èC
TJ = 125èC
3
2
1
0
20
40
60
80
100
120
140
160
2
2.5
3
3.5
4
4.5
5
5.5
Output Current (mA)
Input Voltage (V)
图 7. Ground Pin Current vs IOUT and Temperature
图 8. Shutdown Current vs VIN and Temperature
90
85
80
75
70
65
60
55
50
45
40
35
30
25
20
15
10
100
90
80
70
60
50
40
30
20
10
0
IOUT = 10 mA
IOUT = 50 mA
IOUT = 100 mA
IOUT = 150 mA
COUT = 1 µF, IOUT = 150 mA
COUT = 1 µF, IOUT = 30 mA
-10
1E+1
1E+2
1E+3 1E+4 1E+5
Frequency (Hz)
1E+6
1E+7
1E+1
1E+2
1E+3
1E+4
1E+5
1E+6
1E+7
Frequency (Hz)
图 9. Power-Supply Rejection Ratio Over COUT
图 10. Power-Supply Rejection Ratio Over IOUT
5
6
5
4
3
2
1
0
0.024
COUT = 1 µF
3
2
0.016
0.008
0
1
0.5
0.3
0.2
0.1
-0.008
-0.016
-0.024
0.05
0.03
0.02
VIN = 4.5-5.5 V
VOUT = 3.3 V
0.01
0.005
-0.003 -0.0015
0
0.0015
Time (s)
0.003
0.0045
0.006
1E+1
1E+2
1E+3 1E+4 1E+5
Frequency (Hz)
1E+6
1E+7
D011
COUT = 1 µF
IOUT = 0 mA
图 11. Output Spectral Noise Density
图 12. Line Transient
8
版权 © 2017–2018, Texas Instruments Incorporated
TLV741P
www.ti.com.cn
ZHCSGF1A –JULY 2017–REVISED SEPTEMBER 2018
Typical Characteristics (接下页)
over operating temperature range TJ = –40°C to +125°C, VIN = VOUT(nom) + 0.5 V or 2 V (whichever is greater), IOUT = 10 mA,
VEN = VIN, COUT = 1 µF, and VOUT(nom) = 1.8 V (unless otherwise noted). Typical values are at TJ = 25°C.
6
5
4
3
2
1
0.06
0.045
0.03
0.015
0
6.4
5.6
4.8
4
0.06
VIN
VOUT
0.045
0.03
0.015
0
3.2
2.4
1.6
0.8
-0.015
-0.03
-0.045
-0.06
-0.015
VIN = 4.5-5.5 V
VOUT = 3.3 V
0
-0.03
0.006
0
-0.003 -0.0015
0
0.0015
Time (s)
0.003
0.0045
-0.0014
-0.001
-0.0006
-0.0002
0.0002
0.0006
Time (s)
D012
IOUT = 150 mA
图 14. Line Transient
IOUT = 1 mA
图 13. Line Transient
0.24
0.045
0.03
0.015
0
0.52
0.47
0.42
0.37
0.32
0.27
0.22
0.17
0.12
0.07
0.02
-0.03
0.05
0.04
0.03
0.02
0.01
0
IOUT = 0 mA - 20 mA
VOUT = 3.3 V
IOUT = 0 mA - 100 mA
VOUT = 3.3 V
0.19
0.14
0.09
0.04
-0.01
-0.01
-0.02
-0.03
-0.04
-0.05
-0.06
-0.015
-0.03
1.5
-0.5 -0.25
0
0.25
0.5
0.75
1
1.25
-0.5 -0.25
0
0.25
0.5
0.75
1
1.25
1.5
Time (s)
Time (s)
D015
D0146
IOUT = 0 mA - 20 mA
VOUT = 3.3 V
图 15. Load Transient
图 16. Load Transient
0.52
0.05
0.04
0.03
0.02
0.01
0
3.5
3
IOUT = 10 mA - 150 mA
VOUT = 3.3 V
0.47
0.42
0.37
0.32
0.27
0.22
0.17
0.12
0.07
0.02
-0.03
2.5
2
-0.01
-0.02
-0.03
-0.04
-0.05
-0.06
1.5
1
0.5
0
0
50
100
150
Output Current (mA)
200
250
300
-0.5 -0.25
0
0.25
0.5
Time (s)
0.75
1
1.25
1.5
D016
TLV74133P
IOUT = 10 mA - 150 mA
VOUT = 3.3 V
图 17. Load Transient
图 18. 3.3-V Output Voltage vs Output Current
(Foldback Current Limit)
版权 © 2017–2018, Texas Instruments Incorporated
9
TLV741P
ZHCSGF1A –JULY 2017–REVISED SEPTEMBER 2018
www.ti.com.cn
Typical Characteristics (接下页)
over operating temperature range TJ = –40°C to +125°C, VIN = VOUT(nom) + 0.5 V or 2 V (whichever is greater), IOUT = 10 mA,
VEN = VIN, COUT = 1 µF, and VOUT(nom) = 1.8 V (unless otherwise noted). Typical values are at TJ = 25°C.
2
1.75
1.5
1.25
1
4
3
2
1
0
VIN
VOUT
0.75
0.5
0.25
0
0
50
100
150 200
Output Current (mA)
250
300
350
0
0.5
1
Time (s)
1.5
2
TLV74118P
TLV74118P
IOUT = 150 mA
图 19. 1.8-V Output Voltage vs Output Current
图 20. VIN Power-Up and Power-Down
(Foldback Current Limit)
Channel 1
2 V/div
Channel 1
100 mV/div
VIN
VIN
EN
Channel 2
2 V/div
Channel 2
1 V/div
EN
VOUT
Channel 3
1 V/div
VOUT
Channel 4
50 mA/div
Channel 3
1 V/div
Channel 4
100 mA/div
ILOAD
IOUT
Time (50 ms/div)
Time (100 ms/div)
VIN = 3 V
VOUT = 1.8 V
No load
CIN = COUT = 1 µF
VIN = 2.3 V
COUT = 10 µF
VOUT = 1.8 V
IOUT = 90 mA
CIN = 1 µF
TPS74118P
TLV74118P
from design
图 22. Shutdown Response With Enable
图 21. Start-Up With EN
10
版权 © 2017–2018, Texas Instruments Incorporated
TLV741P
www.ti.com.cn
ZHCSGF1A –JULY 2017–REVISED SEPTEMBER 2018
7 Detailed Description
7.1 Overview
The TLV741P belongs to a new family of next-generation value low-dropout (LDO) regulators. The TLV741P
consumes low quiescent current and delivers excellent line and load transient performance. These
characteristics, combined with low noise, very good PSRR with little (VIN – VOUT) headroom makes the device
suitable for RF portable applications.
This regulator offers current limit and thermal protection. Device operating junction temperature is –40°C to
+125°C.
7.2 Functional Block Diagram
IN
OUT
Current
Limit
Thermal
Shutdown
UVLO
120 W
Bandgap
EN
Logic
TLV741P
GND
版权 © 2017–2018, Texas Instruments Incorporated
11
TLV741P
ZHCSGF1A –JULY 2017–REVISED SEPTEMBER 2018
www.ti.com.cn
7.3 Feature Description
7.3.1 Undervoltage Lockout (UVLO)
The TLV741P uses a UVLO circuit that disables the output until the input voltage is greater than the rising UVLO
voltage. The circuit makes sure that the device does not exhibit any unpredictable behavior when the supply
voltage is lower than the operational range of the internal circuitry, VIN(min). During UVLO disable, the output of
the TLV741P version is connected to ground with a 120-Ω pulldown resistor.
7.3.2 Shutdown
The enable pin (EN) is active high. Enable the device by forcing the EN pin to exceed VEN(high) (0.9 V, minimum).
Turn off the device by forcing the EN pin to drop below 0.4 V. If shutdown capability is not required, connect EN
to IN.
The TLV741P has an internal pulldown MOSFET that connects a 120-Ω resistor to ground when the device is
disabled. The discharge time after disabling depends on the output capacitance (COUT) and the load resistance
(RL) in parallel with the 120-Ω pulldown resistor. The time constant is calculated in 公式 1.
120 · RL
t =
· COUT
120 + RL
(1)
7.3.3 Foldback Current Limit
The TLV741P has an internal foldback current limit that helps protect the regulator during fault conditions. The
current supplied by the device is gradually reduced while the output voltage decreases. When the output shorts,
the LDO supplies a typical current of 40 mA. Output voltage is not regulated when the device is in current limit,
and is calculated by 公式 2:
VOUT = ILIMIT ´ RLOAD
(2)
The PMOS pass transistor dissipates [(VIN – VOUT) × ILIMIT] until thermal shutdown is triggered and the device
turns off. The internal thermal shutdown circuit turns on the device during cool down. If the fault condition
continues, the device cycles between current limit and thermal shutdown. See Thermal Protection for more
details.
The TLV741P PMOS pass element has a built-in body diode that conducts current when the voltage at OUT
exceeds the voltage at IN. This current is not limited, so if extended reverse voltage operation is anticipated, TI
recommends externally limiting the rated output current to 5%.
7.3.4 Thermal Protection
Thermal protection disables the output when the junction temperature rises to approximately 158°C, allowing the
device to cool. When the junction temperature cools to approximately 140°C, the output circuitry is again
enabled. Depending on power dissipation, thermal resistance, and ambient temperature, the thermal protection
circuit may cycle on and off. This cycling limits regulator dissipation, which protects the device from damage as a
result of overheating.
Any tendency to activate the thermal protection circuit indicates excessive power dissipation or an inadequate
heat sink. For reliable operation, junction temperature must be limited to 125°C maximum. To estimate the
margin of safety in a complete design (including heat sink), increase the ambient temperature until the thermal
protection is triggered; use worst-case loads and signal conditions.
The TLV741P internal protection circuitry is designed to protect against overload conditions. This circuitry is not
intended to replace proper heat sinking. Continuously running the TLV741P into thermal shutdown degrades
device reliability.
12
版权 © 2017–2018, Texas Instruments Incorporated
TLV741P
www.ti.com.cn
ZHCSGF1A –JULY 2017–REVISED SEPTEMBER 2018
7.4 Device Functional Modes
7.4.1 Normal Operation
The device regulates to the nominal output voltage under the following conditions:
•
•
•
The input voltage is at least as high as VIN(min).
The input voltage is greater than the nominal output voltage added to the dropout voltage.
The enable voltage has previously exceeded the enable rising threshold voltage and has not decreased
below the enable falling threshold.
•
•
The output current is less than the current limit.
The device junction temperature is less than the maximum specified junction temperature.
7.4.2 Dropout Operation
If the input voltage is lower than the nominal output voltage plus the specified dropout voltage, but all other
conditions are met for normal operation, the device operates in dropout mode. In this mode of operation, the
output voltage is the same as the input voltage minus the dropout voltage. The transient performance of the
device is significantly degraded because the pass device is in the linear region and no longer controls the current
through the LDO. Line or load transients in dropout can result in large output voltage deviations.
7.4.3 Disabled
The device is disabled under the following conditions:
•
The enable voltage is less than the enable falling threshold voltage or has not yet exceeded the enable rising
threshold.
•
The device junction temperature is greater than the thermal shutdown temperature.
表 1 lists conditions that result in different operating modes.
表 1. Device Functional Mode Comparison
PARAMETER
VEN
OPERATING MODE
Normal mode
VIN
IOUT
IOUT < ILIM
—
TJ
VIN > VOUT(nom) + VDO and
VIN > VIN(min)
VEN > VEN(high)
VEN > VEN(high)
TJ < 125°C
TJ < 125°C
Dropout mode
VIN(min) < VIN < VOUT(nom) + VDO
Disabled mode
(any true condition disables the
device)
—
VEN < VEN(low)
—
TJ > 158°C
版权 © 2017–2018, Texas Instruments Incorporated
13
TLV741P
ZHCSGF1A –JULY 2017–REVISED SEPTEMBER 2018
www.ti.com.cn
8 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
8.1.1 Input and Output Capacitor Considerations
The TLV741P uses an advanced internal control loop to obtain stable operation by using an input or output
capacitor. An output capacitance of 1 μF or larger generally provides good dynamic response. TI recommends
using X5R- and X7R-type ceramic capacitors because these capacitors have minimal variation in value and
equivalent series resistance (ESR) over temperature.
Although an input capacitor is not required for stability, it is good analog design practice to connect a 0.1-µF to
1-µF capacitor from IN to GND. This capacitor counteracts reactive input sources and improves transient
response, input ripple, and PSRR. TI recommends using an input capacitor if the source impedance is more than
0.5 Ω. A higher-value capacitor may be necessary if large, fast, rise-time load transients are anticipated or if the
device is located several inches from the input power source.
8.1.2 Dropout Voltage
The TLV741P uses a PMOS pass transistor to achieve low dropout. When (VIN – VOUT) is less than the dropout
voltage (VDO), the PMOS pass device is in the linear region of operation and the input-to-output resistance is the
RDS(on) of the PMOS pass element. VDO scales approximately with output current because the PMOS device
behaves like a resistor in dropout. As with any linear regulator, PSRR and transient response are degraded as
(VIN – VOUT) approaches dropout.
8.1.3 Transient Response
As with any regulator, increasing the size of the output capacitor reduces over- and undershoot magnitude but
increases the duration of the transient response.
14
版权 © 2017–2018, Texas Instruments Incorporated
TLV741P
www.ti.com.cn
ZHCSGF1A –JULY 2017–REVISED SEPTEMBER 2018
8.2 Typical Application
Several versions of the TLV741P are suitable for powering the MSP430 microcontroller.
图 23 shows a diagram of the TLV741P powering an MSP430 microcontroller. 表 2 lists potential applications of
some voltage versions.
VO
(1.8 V to 3.6 V)
VI
MSP430
OUT
IN
1 µF
0.1 µF
EN
GND
图 23. TLV741P Powering a Microcontroller
表 2. Typical MSP430 Applications
VOUT
(TYPICAL)
DEVICE
APPLICATION
TLV741P18P
TLV741P25P
1.8 V
Allows for lowest power consumption with many MSP430s
2.5 V
2.2-V supply required by many MSP430s for flash programming and erasing
8.2.1 Design Requirements
表 3 lists the design requirements.
表 3. Design Parameters
PARAMETER
Input voltage
DESIGN REQUIREMENT
4.2 V to 3 V (Lithium Ion battery)
Output voltage
DC output current
1.8 V, ±1%
10 mA
Peak output current
75 mA
Maximum ambient temperature
65°C
8.2.2 Detailed Design Procedure
An input capacitor is not required for this design because of the low impedance connection directly to the battery.
A small output capacitor allows for the minimal possible inrush current during start-up, and makes sure that the
180-mA maximum input current limit is not exceeded.
See 图 29 to verify that the maximum junction temperature is not exceeded.
版权 © 2017–2018, Texas Instruments Incorporated
15
TLV741P
ZHCSGF1A –JULY 2017–REVISED SEPTEMBER 2018
www.ti.com.cn
8.2.3 Application Curves
4
3
2
1
0
100
90
80
70
60
50
40
30
20
10
COUT = 1 µF, IOUT = 150 mA
COUT = 1 µF, IOUT = 30 mA
0
10
100
1k
Frequency (Hz)
10k
100k
-10
1E+1
1E+2
1E+3 1E+4
Frequency (Hz)
1E+5
1E+6
1E+7
VOUT = 1.8 V
IOUT = 10 mA
图 24. Power-Supply Rejection Ratio vs Frequency
图 25. Output Spectral Noise Density
4
VIN
VOUT
3
2
1
0
0
0.5
1
Time (s)
1.5
2
IOUT = 150 mA
图 26. VINPower Up and Power Down
8.3 What to Do and What Not to Do
Place at least one 1-µF ceramic capacitor as close as possible to the OUT pin of the regulator for best transient
performance.
Place at least one 1-µF capacitor as close as possible to the IN pin for best transient performance.
Do not place the output capacitor more than 10 mm away from the regulator.
Do not exceed the absolute maximum ratings.
Do not continuously operate the device in current limit or near thermal shutdown.
16
版权 © 2017–2018, Texas Instruments Incorporated
TLV741P
www.ti.com.cn
ZHCSGF1A –JULY 2017–REVISED SEPTEMBER 2018
9 Power Supply Recommendations
This device is designed to operate from an input voltage supply range from 1.4 V to 5.5 V. The input voltage
range must provide adequate headroom for the device to have a regulated output. This input supply must be
well-regulated and stable. If the input supply is noisy, additional input capacitors with low ESR can help improve
the output noise performance.
10 Layout
10.1 Layout Guidelines
10.1.1 Board Layout Recommendations to Improve PSRR and Noise Performance
Input and output capacitors must be placed as close to the device pins as possible. To improve AC performance
(such as PSRR, output noise, and transient response), TI recommends that the board be designed with separate
ground planes for VIN and VOUT, with the ground plane connected only at the device GND pin. In addition, the
output capacitor ground connection must be connected directly to the device GND pin. High-ESR capacitors may
degrade PSRR performance.
10.2 Layout Examples
VOUT
VIN
TLV741P
IN
OUT
(1)
COUT
(1)
CIN
EN
GND
GND PLANE
Represents via used for
application-specific connections
(1) Not required.
图 27. X2SON Layout Example
VOUT
VIN
OUT
IN
CIN
COUT
GND
EN
NC
GND PLANE
Represents via used for
application-specific connections
图 28. SOT-23 Layout Example
版权 © 2017–2018, Texas Instruments Incorporated
17
TLV741P
ZHCSGF1A –JULY 2017–REVISED SEPTEMBER 2018
www.ti.com.cn
10.3 Power Dissipation
The ability to remove heat from the die is different for each package type, presenting different considerations in
the printed-circuit-board (PCB) layout. The PCB area around the device that is free of other components moves
the heat from the device to the ambient air. Performance data for JEDEC low- and high-K boards are given in
Thermal Information. Using heavier copper increases the effectiveness in removing heat from the device. The
addition of plated through-holes to heat-dissipating layers also improves the heat sink effectiveness.
Power dissipation depends on input voltage and load conditions. Power dissipation (PD) can be approximated by
the product of the output current times the voltage drop across the output pass element (VIN to VOUT), as shown
in 公式 3:
P = V - VOUT ´ I
OUT
(
)
D
IN
(3)
图 29 shows the maximum ambient temperature versus the power dissipation of the TLV741P. This figure
assumes the device is soldered on a JEDEC standard, high-K layout with no airflow over the board. Actual board
thermal impedances vary widely. If the application requires high power dissipation, having a thorough
understanding of the board temperature and thermal impedances is helpful to make sure the TLV741P does not
operate above a junction temperature of 125°C.
130
TLV741P DQN, High-K Layout
TLV741P DBV, High-K Layout
120
110
100
90
80
70
60
50
0
0.05
0.1
0.15
0.2
Power Dissipation (W)
0.25
0.3
0.35
图 29. Maximum Ambient Temperature vs Device Power Dissipation
Estimate junction temperature by using the ΨJT and ΨJB thermal metrics, shown inThermal Information. These
metrics are a more accurate representation of the heat transfer characteristics of the die and the package than
RθJA. The junction temperature can be estimated with 公式 4:
YJT: TJ = TT + YJT · PD
YJB: TJ = TB + YJB · PD
where
•
•
•
PD is the power dissipation shown by 公式 3,
TT is the temperature at the center-top of the device package,
TB is the PCB temperature measured 1 mm away from the device package on the PCB surface.
(4)
注
Both TT and TB can be measured on actual application boards using a thermogun (an
infrared thermometer).
For more information about measuring TT and TB, see Using New Thermal Metrics , available for download at
www.ti.com.
18
版权 © 2017–2018, Texas Instruments Incorporated
TLV741P
www.ti.com.cn
ZHCSGF1A –JULY 2017–REVISED SEPTEMBER 2018
11 器件和文档支持
11.1 文档支持
11.1.1 相关文档
请参阅如下相关文档：
通用低压降 (LDO) 线性稳压器 EVM 用户指南
11.2 接收文档更新通知
要接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我 进行注册，即可每周接收产
品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
11.3 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，
并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
设计支持
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。
11.4 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
11.6 术语表
SLYZ022 — TI 术语表。
这份术语表列出并解释术语、缩写和定义。
12 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。
版权 © 2017–2018, Texas Instruments Incorporated
19
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TLV741105PDBVR
TLV74110PDBVR
TLV74110PDQNR
TLV74111PDBVR
TLV74111PDQNR
TLV74112PDBVR
TLV74112PDQNR
TLV74115PDBVR
TLV74115PDQNR
TLV74118PDBVR
TLV74118PDQNR
TLV74125PDBVR
TLV74125PDQNR
TLV741285PDBVR
TLV741285PDQNR
TLV74128PDBVR
TLV74128PDQNR
TLV74130PDBVR
TLV74130PDQNR
TLV74133PDBVR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOT-23
SOT-23
X2SON
SOT-23
X2SON
SOT-23
X2SON
SOT-23
X2SON
SOT-23
X2SON
SOT-23
X2SON
SOT-23
X2SON
SOT-23
X2SON
SOT-23
X2SON
SOT-23
DBV
DBV
DQN
DBV
DQN
DBV
DQN
DBV
DQN
DBV
DQN
DBV
DQN
DBV
DQN
DBV
DQN
DBV
DQN
DBV
5
5
4
5
4
5
4
5
4
5
4
5
4
5
4
5
4
5
4
5
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
1NFT
1C9T
8T
SN
NIPDAU
SN
1DHT
8R
NIPDAU
SN
1DIT
8Q
NIPDAU
SN
1DJT
8P
NIPDAU
SN
1DKT
8O
NIPDAU
SN
1DLT
8N
NIPDAU
SN
1DMT
8M
NIPDAU
SN
1DNT
8L
NIPDAU
SN
1DOT
8K
NIPDAU
SN
1CAT
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TLV74133PDQNR
ACTIVE
X2SON
DQN
4
3000 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
8J
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
18-Jun-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TLV741105PDBVR
TLV74110PDBVR
TLV74110PDQNR
TLV74111PDBVR
TLV74111PDQNR
TLV74112PDBVR
TLV74112PDQNR
TLV74115PDBVR
TLV74115PDQNR
TLV74118PDBVR
TLV74118PDQNR
TLV74125PDBVR
TLV74125PDQNR
TLV741285PDBVR
TLV741285PDQNR
TLV74128PDBVR
SOT-23
SOT-23
X2SON
SOT-23
X2SON
SOT-23
X2SON
SOT-23
X2SON
SOT-23
X2SON
SOT-23
X2SON
SOT-23
X2SON
SOT-23
DBV
DBV
DQN
DBV
DQN
DBV
DQN
DBV
DQN
DBV
DQN
DBV
DQN
DBV
DQN
DBV
5
5
4
5
4
5
4
5
4
5
4
5
4
5
4
5
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
3.2
3.2
3.2
3.2
1.4
1.4
0.5
1.4
0.5
1.4
0.5
1.4
0.5
1.4
0.5
1.4
0.5
1.4
0.5
1.4
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
Q3
Q3
Q2
Q3
Q2
Q3
Q2
Q3
Q2
Q3
Q2
Q3
Q2
Q3
Q2
Q3
1.16
3.2
1.16
3.2
1.16
3.2
1.16
3.2
1.16
3.2
1.16
3.2
1.16
3.2
1.16
3.2
1.16
3.2
1.16
3.2
1.16
3.2
1.16
3.2
1.16
3.2
1.16
3.2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
18-Jun-2023
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TLV74128PDQNR
TLV74130PDBVR
TLV74130PDQNR
TLV74133PDBVR
TLV74133PDQNR
X2SON
SOT-23
X2SON
SOT-23
X2SON
DQN
DBV
DQN
DBV
DQN
4
5
4
5
4
3000
3000
3000
3000
3000
180.0
180.0
180.0
180.0
180.0
8.4
8.4
8.4
8.4
8.4
1.16
3.2
1.16
3.2
0.5
1.4
0.5
1.4
0.5
4.0
4.0
4.0
4.0
4.0
8.0
8.0
8.0
8.0
8.0
Q2
Q3
Q2
Q3
Q2
1.16
3.2
1.16
3.2
1.16
1.16
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
18-Jun-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TLV741105PDBVR
TLV74110PDBVR
TLV74110PDQNR
TLV74111PDBVR
TLV74111PDQNR
TLV74112PDBVR
TLV74112PDQNR
TLV74115PDBVR
TLV74115PDQNR
TLV74118PDBVR
TLV74118PDQNR
TLV74125PDBVR
TLV74125PDQNR
TLV741285PDBVR
TLV741285PDQNR
TLV74128PDBVR
TLV74128PDQNR
TLV74130PDBVR
SOT-23
SOT-23
X2SON
SOT-23
X2SON
SOT-23
X2SON
SOT-23
X2SON
SOT-23
X2SON
SOT-23
X2SON
SOT-23
X2SON
SOT-23
X2SON
SOT-23
DBV
DBV
DQN
DBV
DQN
DBV
DQN
DBV
DQN
DBV
DQN
DBV
DQN
DBV
DQN
DBV
DQN
DBV
5
5
4
5
4
5
4
5
4
5
4
5
4
5
4
5
4
5
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
210.0
210.0
210.0
210.0
210.0
210.0
210.0
210.0
210.0
210.0
210.0
210.0
210.0
210.0
210.0
210.0
210.0
210.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
Pack Materials-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
18-Jun-2023
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TLV74130PDQNR
TLV74133PDBVR
TLV74133PDQNR
X2SON
SOT-23
X2SON
DQN
DBV
DQN
4
5
4
3000
3000
3000
210.0
210.0
210.0
185.0
185.0
185.0
35.0
35.0
35.0
Pack Materials-Page 4
PACKAGE OUTLINE
X2SON - 0.4 mm max height
DQN0004A
PLASTIC SMALL OUTLINE - NO LEAD
1.05
0.95
A
B
1
1.05
0.95
PIN 1
INDEX AREA
C
0.4 MAX
SEATING PLANE
0.08
NOTE 6
+0.12
-0.1
0.05
0.00
0.48
(0.05) TYP
NOTE 6
2
1
3
EXPOSED
THERMAL PAD
5
2X 0.65
(0.07) TYP
NOTE 5
4
0.28
PIN 1 ID
(OPTIONAL)
NOTE 4
4X
0.15
(0.11)
0.3
0.2
0.1
C A B
0.05
C
0.30
0.15
3X
4215302/E 12/2016
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.
4. Features may not exist. Recommend use of pin 1 marking on top of package for orientation purposes.
5. Shape of exposed side leads may differ.
6. Number and location of exposed tie bars may vary.
www.ti.com
EXAMPLE BOARD LAYOUT
X2SON - 0.4 mm max height
DQN0004A
PLASTIC SMALL OUTLINE - NO LEAD
(0.86)
SYMM
SEE DETAIL
4X
4X (0.36)
(0.03)
4
4X (0.21)
1
5
SYMM
(0.65)
4X (0.18)
2
3
(
0.48)
(0.22) TYP
EXPOSED METAL
CLEARANCE
LAND PATTERN EXAMPLE
SCALE: 40X
0.05 MIN
ALL AROUND
SOLDER MASK
OPENING
EXPOSED METAL
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
SOLDER MASK DETAIL
4215302/E 12/2016
NOTES: (continued)
7. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271)
.
8. If any vias are implemented, it is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
X2SON - 0.4 mm max height
DQN0004A
PLASTIC SMALL OUTLINE - NO LEAD
(0.9)
SYMM
4X (0.4)
4X (0.03)
4
1
4X (0.21)
5
SYMM
(0.65)
SOLDER MASK
EDGE
4X (0.22)
2
3
(
0.45)
4X (0.235)
SOLDER PASTE EXAMPLE
BASED ON 0.075 - 0.1mm THICK STENCIL
EXPOSED PAD
88% PRINTED SOLDER COVERAGE BY AREA
SCALE: 60X
4215302/E 12/2016
NOTES: (continued)
9. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
PACKAGE OUTLINE
DBV0005A
SOT-23 - 1.45 mm max height
S
C
A
L
E
4
.
0
0
0
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
0.1 C
1.75
1.45
1.45
0.90
B
A
PIN 1
INDEX AREA
1
2
5
(0.1)
2X 0.95
1.9
3.05
2.75
1.9
(0.15)
4
3
0.5
5X
0.3
0.15
0.00
(1.1)
TYP
0.2
C A B
NOTE 5
0.25
GAGE PLANE
0.22
0.08
TYP
8
0
TYP
0.6
0.3
TYP
SEATING PLANE
4214839/G 03/2023
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.25 mm per side.
5. Support pin may differ or may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X (0.95)
4
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214839/G 03/2023
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X(0.95)
4
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214839/G 03/2023
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
重要声明和免责声明
TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，
不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担
保。
这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。
这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。
您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成
本、损失和债务，TI 对此概不负责。
TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改
TI 针对 TI 产品发布的适用的担保或担保免责声明。
TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE
邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2023，德州仪器 (TI) 公司
相关型号：
©2020 ICPDF网 联系我们和版权申明