TLV76033DBZR [TI]
100mA、30V 低压降稳压器 | DBZ | 3 | -40 to 125;
| 型号： | TLV76033DBZR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 100mA、30V 低压降稳压器 | DBZ | 3 | -40 to 125 光电二极管 输出元件 稳压器 调节器 |
| 文件： | 总23页 (文件大小：1302K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TLV760
ZHCSGW3A –JUNE 2017–REVISED OCTOBER 2017
TLV760 100mA 30V 固定输出线性电压调整器
1 特性
3 说明
1
•
•
•
•
•
•
高达 30V 的宽输入电压范围
TLV760 是一款集成的线性电压调整器，能够以高达
30V 的输入电压运行。在运行温度范围内，TLV760 可
在 100mA 满负载下具有 1.2V 的最大压降。TLV760
的标准封装是 3 引脚 SOT-23 封装。
高达 100mA 的输出电流
提供固定输出电压 3.3V、5V、12V 和 15V 版本
运行结温范围为 −40°C 至 +125°C
接 0.1µF及以上 的陶瓷电容器保持稳定工作
有效的热保护和电流限制
TLV760 提供 3.3V、5V、12V 和 15V 版本。TLV760
系列的 SOT-23 封装允许器件用于空间受限的 应用。
TLV760 是 LM78Lxx 系列和类似器件的小尺寸替代产
品。
2 应用
•
•
•
•
•
用于开关直流/直流转换器的后置稳压器
TLV760 用于对遭受高达 30V 的电源瞬态和尖峰的 应
用 （例如电器和自动化应用）中的数字和模拟电路进
行 偏置。该器件具有可靠的内部热保护功能，可以保
护其自身免受由接地短路、环境温度升高、高负载或高
压降事件等情况导致的潜在损害。
用于数字和模拟电路的偏置电源
家用电器
电动工具
工厂和楼宇自动化
器件信息(1)
器件型号
TLV760
封装
SOT-23 (3)
封装尺寸（标称值）
2.92mm × 1.30mm
(1) 如需了解所有可用封装，请参阅产品说明书末尾的可订购产品
附录。
空白
空白
空白
典型应用电路
VIN = 5 V
VOUT = 3.3 V
IN
OUT
GND
TLV760
CIN
0.1 µF
COUT
0.1 µF
Copyright © 2017, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SNVSAV1
TLV760
ZHCSGW3A –JUNE 2017–REVISED OCTOBER 2017
www.ti.com.cn
目录
7.4 Device Functional Modes........................................ 10
Application and Implementation ........................ 11
8.1 Application Information............................................ 11
8.2 Typical Application ................................................. 12
Power Supply Recommendations...................... 14
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 4
6.5 Electrical Characteristics........................................... 5
6.6 Typical Characteristics.............................................. 6
Detailed Description .............................................. 9
7.1 Overview ................................................................... 9
7.2 Functional Block Diagram ......................................... 9
7.3 Feature Description................................................... 9
8
9
10 Layout................................................................... 14
10.1 Layout Guidelines ................................................. 14
10.2 Layout Example .................................................... 14
11 器件和文档支持 ..................................................... 15
11.1 器件支持................................................................ 15
11.2 接收文档更新通知 ................................................. 15
11.3 社区资源................................................................ 15
11.4 商标....................................................................... 15
11.5 静电放电警告......................................................... 15
11.6 Glossary................................................................ 15
12 机械、封装和可订购信息....................................... 15
7
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from Original (June 2017) to Revision A
Page
•
Changed description of pin 1 to "OUT" and pin 2 to "IN" to correct error ............................................................................. 3
2
Copyright © 2017, Texas Instruments Incorporated
TLV760
www.ti.com.cn
ZHCSGW3A –JUNE 2017–REVISED OCTOBER 2017
5 Pin Configuration and Functions
DBZ Package
3-Pin SOT-23
Top View
Pin Functions
PIN
I/O
DESCRIPTION
NO.
NAME
Output voltage, a ceramic capacitor greater than or equal to 0.1 μF is need for the stability of the
1
OUT
O
device.(1)
2
3
IN
I
Input voltage supply — TI recommends a capacitor of value greater than 0.1 µF at the input.(1)
GND
—
Common ground
(1) See External Capacitors for more details.
Copyright © 2017, Texas Instruments Incorporated
3
TLV760
ZHCSGW3A –JUNE 2017–REVISED OCTOBER 2017
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings(1)
MIN
MAX
UNIT
V
Input voltage (IN to GND)
Output Voltage (OUT)
Output Current
–0.3
35
VIN + 0.3
Internally limited(2)
150
V
mA
°C
Junction temperature
Storage temperature, Tstg
–40
−65
150
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings(1) may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) See Recommended Operating Conditions section for more details.
6.2 ESD Ratings
VALUE
±2000
±500
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
Electrostatic
discharge
V(ESD)
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
30
UNIT
V
Maximum input voltage (IN to GND)
Output current (IOUT
)
100
mA
µF
Input and output capacitor (COUT
)
0.1
Junction temperature, TJ
–40
125
°C
6.4 Thermal Information
TLV760
THERMAL METRIC(1)
DBZ (SOT-23)
3 PINS
275.2
UNIT
RθJA
RθJC(top)
RθJB
ψJT
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
92.8
Junction-to-board thermal resistance
56.8
Junction-to-top characterization parameter
Junction-to-board characterization parameter
2.9
ψJB
55.6
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
4
Copyright © 2017, Texas Instruments Incorporated
TLV760
www.ti.com.cn
ZHCSGW3A –JUNE 2017–REVISED OCTOBER 2017
6.5 Electrical Characteristics
Typical and other limits apply for TA = TJ = 25°C, VOUT(NOM) = 3.3 V, 5 V, 12 V, and 15 V, unless otherwise specified.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VIN = VOUT(NOM)+ 1.5 V,
1 mA ≤ IOUT ≤ 100 mA
–4%
4%
Output voltage
accuracy
VOUT
V
VIN = VOUT(NOM) + 1.5 V,
1 mA ≤ IOUT ≤ 100 mA,
−40°C ≤ TJ ≤ 125°C
–5%
5%
VOUT(NOM) + 1.5 V ≤ VIN ≤ 30 V VOUT(NOM) = 3.3 V, 5 V
10
14
20
45
30
45
45
80
ΔV(ΔVIN)
Line regulation
IOUT = 1 mA ,
−40°C ≤ TJ ≤ 125°C
mV
VOUT(NOM) = 12 V, 15 V
VIN =VOUT(NOM) + 1.5 V ,
10 mA ≤ IOUT ≤ 100 mA,
−40°C ≤ TJ ≤ 125°C
VOUT(NOM) = 3.3 V, 5 V
VOUT(NOM) = 12 V, 15 V
ΔV(ΔIOUT) Load regulation
mV
mA
VOUT(NOM) + 1.5 V ≤ VIN ≤ 30 V, no load,
−40°C ≤ TJ ≤ 125°C
IGND
VDO
TSD
Ground pin current
Dropout voltage
2
5
IOUT = 10 mA
0.7
0.9
1
IOUT = 10 mA , −40°C ≤ TJ ≤ 125°C
IOUT = 100 mA
V
0.9
1.1
1.2
IOUT = 100 mA, −40°C ≤ TJ ≤ 125°C
Thermal shutdown
temperature
°C
150
Copyright © 2017, Texas Instruments Incorporated
5
TLV760
ZHCSGW3A –JUNE 2017–REVISED OCTOBER 2017
www.ti.com.cn
6.6 Typical Characteristics
Unless indicated otherwise, VIN = VNOM + 1.5 V, CIN = 0.1 µF, COUT = 0.1 µF, and TA = 25°C.
Figure 1. Dropout Voltage vs Load Current
Figure 2. Dropout Voltage vs Junction Temperature
Figure 3. Ground Pin Current vs Input Voltage
Figure 4. Ground Pin Current vs Input Voltage
Figure 5. Ground Pin Current vs Load Current
Figure 6. Ground Pin Current vs Junction Temperature
6
Copyright © 2017, Texas Instruments Incorporated
TLV760
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ZHCSGW3A –JUNE 2017–REVISED OCTOBER 2017
Typical Characteristics (continued)
Unless indicated otherwise, VIN = VNOM + 1.5 V, CIN = 0.1 µF, COUT = 0.1 µF, and TA = 25°C.
Figure 7. Input Current vs Input Voltage
Figure 8. Input Current vs Input Voltage
Figure 9. Output Voltage vs Input Voltage
Figure 10. Output Voltage vs Input Voltage
Figure 11. Output Short-Circuit Current
Figure 12. Output Short-Circuit Current
Copyright © 2017, Texas Instruments Incorporated
7
TLV760
ZHCSGW3A –JUNE 2017–REVISED OCTOBER 2017
www.ti.com.cn
Typical Characteristics (continued)
Unless indicated otherwise, VIN = VNOM + 1.5 V, CIN = 0.1 µF, COUT = 0.1 µF, and TA = 25°C.
Figure 14. Power Supply Rejection Ratio
Figure 13. Power Supply Rejection Ratio
120
100
80
60
40
20
0
3.5
3
2.5
2
1.5
1
0.5
0
5.8
8.3
10.8 13.3 15.8 18.3 20.8 23.3 25.7
VIN (V)
D001
VOUT(Red) = 3.3 V
IOUT(Black) = 100 mA
Figure 16. Output Current vs Input Voltage
Figure 15. DC Load Regulation
2
1
0.1
3.3 V 0 mA
3.3 V 10 mA
3.3 V 100 mA
0.01
0.005
10
100
1K
10K 100K
Frequency (Hz)
1M
10M
D002
CIN = 1 µF
COUT = 0.1 µF
VOUT = 3.3 V
Figure 17. Output Spectral Noise Density vs Frequency
8
Copyright © 2017, Texas Instruments Incorporated
TLV760
www.ti.com.cn
ZHCSGW3A –JUNE 2017–REVISED OCTOBER 2017
7 Detailed Description
7.1 Overview
The TLV760 is an integrated linear-voltage regulator with inputs that can be as high as 30 V. The TLV760
features quasi LDO architecture, which allows the usage of low ESR capacitors at the output. A ceramic
capacitor with a capacitance value greater than or equal to 0.1 µF is adequate to keep the linear regulator in
stable operation. The device has a rugged active junction thermal protection mechanism.
7.2 Functional Block Diagram
IN
OUT
Current
Limit and
Thermal
Protection
Bandgap
Reference
GND
Copyright © 2017, Texas Instruments Incorporated
7.3 Feature Description
7.3.1 Thermal Protection
The TLV760 contains an active thermal protection mechanism, which limits the junction temperature to 150°C.
This protection comes into action when the thermal junction temperature of the device tries to exceed 150°C.
The output current of the device is limited or folded back to maintain the junction temperature.
The thermal protection follows Equation 1
P = (TJ - TA ) / RqJA
D
where
•
•
•
PD = (VIN – VOUT )IOUT
TJ is the junction temperature
RθJA is the junction-to-ambient thermal resistance
(1)
When a high drop out condition occurs resulting in higher power dissipation across the device the output current
is limited to maintain a constant junction temperature of 150°C. This rugged feature protects the device from
higher power dissipation applications as well as the short to ground at the output.
This internal protection circuitry of TLV760 is intended to protect the devices against thermal overload conditions.
The circuitry is not intended to replace proper heat sinking. Continuously running the TLV760 into thermal
protection degrades device reliability.
For reliable operation, limit junction temperature to a maximum of 125°C. To estimate the thermal margin in a
given layout, increase the ambient temperature until the thermal protection is triggered using worst case load and
highest input voltage conditions.
Copyright © 2017, Texas Instruments Incorporated
9
TLV760
ZHCSGW3A –JUNE 2017–REVISED OCTOBER 2017
www.ti.com.cn
Feature Description (continued)
7.3.2 Dropout Voltage
The TLV760 is a bipolar device with quasi LDO architecture. Being a bipolar device the dropout voltage of the
device does not change significantly with output load current. The device has a maximum dropout across
temperature of 1.2 V at 100-mA load current, which is a significant improvement over the traditional LM78Lxx
devices.
7.4 Device Functional Modes
7.4.1 Normal Operation
The TLV760 operates with an input up to 30 V. Its tiny SOT-23 package and quasi-LDO architecture makes it
suitable for providing a very tiny 100-mA bias supply. The device regulates to the nominal output voltage when
all of the following conditions are met.
•
•
•
The input voltage is greater than the nominal output voltage plus the dropout voltage (VOUT(NOM) + VDO).
The output current is less than or equal to 100 mA.
The device junction temperature is less than the thermal protection temperature of 150°C.
10
Copyright © 2017, Texas Instruments Incorporated
TLV760
www.ti.com.cn
ZHCSGW3A –JUNE 2017–REVISED OCTOBER 2017
8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TLV760 is a fixed output device which need only input and output capacitors to function. This section
discusses the key aspects to implement this linear regulator in typical applications.
8.1.1 Fixed Output
TLV760 comes in fixed output voltage options, 3.3 V, 5 V, 12 V and 15 V. To ensure the proper regulated output,
the input voltage should be greater than VOUT(nom) + VDO
.
8.1.2 External Capacitors
8.1.2.1 Input and Output Capacitor Requirements
A minimum input and output capacitance value of 0.1 µF is required for stability and adequate transient
performance. There is no specific equivalent series resistance (ESR) limitation, although excessively high ESR
compromises transient performance. There is no specific limitation on a maximum capacitance value on the input
or the output. However while selecting a capacitor, derating factors on the capacitance value should be
considered. Use C0G, X7R, or X5R-type ceramic capacitors because these capacitors have minimal variation in
capacitance value and ESR over temperature.
8.1.2.2 Load-Step Transient Response
The load-step transient response is the output voltage response by the linear regulator to a step change in load
current. The depth of charge depletion immediately after the load step is directly proportional to the amount of
output capacitance. However, larger output capacitances decrease any voltage dip or peak occurring during a
load step, the control-loop bandwidth is also decreased, thereby slowing the response time. TI recommends to
optimally scale output capacitors for a specific application and test for the output load transients.
8.1.3 Power Dissipation
Proper consideration should be given to device power dissipation, location of the circuit on the printed circuit
board (PCB), and correct sizing of the thermal plane to ensure the device reliability. The PCB area around the
regulator must be as free as possible of other heat-generating devices that cause added thermal stresses. To
first-order approximation, power dissipation in the regulator depends on the input-to-output voltage difference and
load conditions. Power dissipation can be calculated using The thermal protection follows Equation 1:
P = (TJ - TA ) / RqJA
D
where
•
•
•
PD = (VIN – VOUT )IOUT
TJ is the junction temperature
RθJA is the junction-to-ambient thermal resistance
(2)
Thus, at a given load current, input and output voltage, maximum power dissipation determines the maximum
allowable ambient temperature (TA) for the device, and vice versa. Power dissipation and junction temperature
are most often related by the junction-to-ambient thermal resistance (RθJA) of the combined PCB and device
package and the temperature of the ambient air (TA).
RθJA is highly dependent on the heat-spreading capability built into the particular PCB design, and therefore
varies according to the total copper area, copper weight, and location of the planes. The RθJA recorded in
Thermal Information is determined by the JEDEC standard, PCB, and copper-spreading area and is only used as
a relative measure of package thermal performance.
Copyright © 2017, Texas Instruments Incorporated
11
TLV760
ZHCSGW3A –JUNE 2017–REVISED OCTOBER 2017
www.ti.com.cn
Application Information (continued)
TLV760 integrates a rugged protection where the TJ is limited to 150°C. The maximum power dissipation
depends on the ambient temperature and can be calculated using PD = (TJ – TA) / RθJA, for example, substituting
the absolute maximum junction temperature, 150°C for TJ, 50°C for TA, and 275.2 °C/W for RθJA, the maximum
power that can be dissipated is 363 mW. More power can be safely dissipated at lower ambient temperatures.
Less power can be safely dissipated at higher ambient temperatures. The power dissipation can be increased by
3.6 mW for each °C below 50°C ambient. It must be derated by 3.6 mW for each °C above 50°C ambient. Proper
heat sinking enables the safe dissipation of more power.
8.2 Typical Application
VIN = 6.5 V
VOUT = 5 V
IN
OUT
GND
TLV760
CIN
0.1 µF
COUT
0.1 µF
Copyright © 2017, Texas Instruments Incorporated
Figure 18. Typical Appication for the 5-V Option
8.2.1 Design Requirements
For typical TLV760 applications, use the parameters in Table 1.
Table 1. Design Parameters
DESIGN PARAMETER
Input voltage
EXAMPLE VALUE
6.5 V
5 V
Output voltage
Output current
100 mA
8.2.2 Detailed Design Procedure
The output for TLV76050 is internally set to 5 V. Input and output capacitors can be selected in accordance with
the External Capacitors. Ceramic capacitances of 0.1 µF for both input and output are selected.
See the Layout section for an example of how to PCB layout the TLV760 to achieve best performance.
12
Copyright © 2017, Texas Instruments Incorporated
TLV760
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ZHCSGW3A –JUNE 2017–REVISED OCTOBER 2017
8.2.3 Application Curves
Unless indicated otherwise, VIN = 6.5 V, VOUT = 5 V, COUT = 0.1 µF, and TA = 25°C.
Figure 19. Line Transient Response
Figure 21. Load Transient Response
Figure 23. Load Transient Response
Figure 20. Line Transient Response
Figure 22. Load Transient Response
Figure 24. Load Transient Response
Copyright © 2017, Texas Instruments Incorporated
13
TLV760
ZHCSGW3A –JUNE 2017–REVISED OCTOBER 2017
www.ti.com.cn
9 Power Supply Recommendations
The TLV760 is designed to operate from input voltage up to 30 V. If the input power supply has ripples,
additional input and output capacitors with low ESR can help improve the PSRR at higher frequencies.
10 Layout
10.1 Layout Guidelines
General guidelines for linear regulator designs are to place all circuit components on the same side of the circuit
board and as near as practical to the respective TLV760 pin connections. Place ground return connections to the
input and output capacitors, and to the TLV760 ground pin as close as possible to each other, connected by a
wide, component-side, copper surface. The use of vias and long traces to create TLV760 circuit connections is
strongly discouraged and negatively affects system performance.
Use a ground reference plane, either embedded in the PCB itself or located on the bottom side of the PCB
opposite the components. This reference plane serves to assure accuracy of the output voltage and to shield
noise; it behaves similarly to a thermal plane to spread heat from the linear regulator. In most applications, this
ground plane is necessary to meet thermal requirements.
10.2 Layout Example
VOUT
VIN
1
2
/
Lb
/
hÜÇ
3
GND PLANE
Figure 25. Layout Guideline for TLV760
14
版权 © 2017, Texas Instruments Incorporated
TLV760
www.ti.com.cn
ZHCSGW3A –JUNE 2017–REVISED OCTOBER 2017
11 器件和文档支持
11.1 器件支持
11.1.1 相关文档
请参阅如下相关文档：
《AN-1148 线性稳压器：工作原理和补偿》
11.1.2 Spice 模型
分析模拟电路和系统的性能时，使用 SPICE 模型对电路性能进行计算机仿真非常有用。您可以通过 TLV760 产品
文件夹在仿真模型下获取 TLV760 的 SPICE 模型。
11.1.3 器件命名规则
表 2. 订购信息(1)
产品
说明
XX 是电压符号
YYY 是封装符号。
Z 为封装数量。
TLV760XXYYYZ
(1) 欲获得最新的封装和订货信息，请参阅本文档末尾的封装选项附录，或者访问 www.ti.com 查看器件产品文件夹。
11.2 接收文档更新通知
要接收文档更新通知，请转至 TI.com 上的器件产品文件夹。单击右上角的通知我 进行注册，即可每周接收产品信
息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
11.3 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，
并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
设计支持
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。
11.4 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。这些数据如有变更，恕不另行通知
和修订此文档。如欲获取此产品说明书的浏览器版本，请参阅左侧的导航。
版权 © 2017, Texas Instruments Incorporated
15
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TLV76012DBZR
TLV76012DBZT
TLV76015DBZR
TLV76015DBZT
TLV76033DBZR
TLV76033DBZT
TLV76050DBZR
TLV76050DBZT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
DBZ
DBZ
DBZ
DBZ
DBZ
DBZ
DBZ
DBZ
3
3
3
3
3
3
3
3
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
18G
18G
18C
18C
18H
18H
18I
SN
SN
SN
SN
SN
SN
SN
18I
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TLV76012DBZR
TLV76012DBZT
TLV76015DBZR
TLV76015DBZT
TLV76033DBZR
TLV76033DBZT
TLV76050DBZR
TLV76050DBZT
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
DBZ
DBZ
DBZ
DBZ
DBZ
DBZ
DBZ
DBZ
3
3
3
3
3
3
3
3
3000
250
178.0
178.0
178.0
178.0
178.0
178.0
178.0
178.0
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
2.9
2.9
2.9
2.9
2.9
2.9
2.9
2.9
1.22
1.22
1.22
1.22
1.22
1.22
1.22
1.22
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
Q3
Q3
Q3
Q3
Q3
Q3
Q3
Q3
3000
250
3000
250
3000
250
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TLV76012DBZR
TLV76012DBZT
TLV76015DBZR
TLV76015DBZT
TLV76033DBZR
TLV76033DBZT
TLV76050DBZR
TLV76050DBZT
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
DBZ
DBZ
DBZ
DBZ
DBZ
DBZ
DBZ
DBZ
3
3
3
3
3
3
3
3
3000
250
208.0
208.0
208.0
208.0
208.0
208.0
208.0
208.0
191.0
191.0
191.0
191.0
191.0
191.0
191.0
191.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
3000
250
3000
250
3000
250
Pack Materials-Page 2
PACKAGE OUTLINE
DBZ0003A
SOT-23 - 1.12 mm max height
S
C
A
L
E
4
.
0
0
0
SMALL OUTLINE TRANSISTOR
C
2.64
2.10
1.12 MAX
1.4
1.2
B
A
0.1 C
PIN 1
INDEX AREA
1
0.95
(0.125)
3.04
2.80
1.9
3
(0.15)
NOTE 4
2
0.5
0.3
3X
0.10
0.01
(0.95)
TYP
0.2
C A B
0.25
GAGE PLANE
0.20
0.08
TYP
0.6
0.2
TYP
SEATING PLANE
0 -8 TYP
4214838/D 03/2023
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Reference JEDEC registration TO-236, except minimum foot length.
4. Support pin may differ or may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
DBZ0003A
SOT-23 - 1.12 mm max height
SMALL OUTLINE TRANSISTOR
PKG
3X (1.3)
1
3X (0.6)
SYMM
3
2X (0.95)
2
(R0.05) TYP
(2.1)
LAND PATTERN EXAMPLE
SCALE:15X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214838/D 03/2023
NOTES: (continued)
4. Publication IPC-7351 may have alternate designs.
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBZ0003A
SOT-23 - 1.12 mm max height
SMALL OUTLINE TRANSISTOR
PKG
3X (1.3)
1
3X (0.6)
SYMM
3
2X(0.95)
2
(R0.05) TYP
(2.1)
SOLDER PASTE EXAMPLE
BASED ON 0.125 THICK STENCIL
SCALE:15X
4214838/D 03/2023
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.
www.ti.com
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