TLV76618QWDRBRQ1 [TI]
TLV766-Q1 500-mA, 16-V Linear Voltage Regulator;型号: | TLV76618QWDRBRQ1 |
厂家: | TEXAS INSTRUMENTS |
描述: | TLV766-Q1 500-mA, 16-V Linear Voltage Regulator |
文件: | 总32页 (文件大小:3065K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
TLV766-Q1
SBVS382 – DECEMBER 2020
TLV766-Q1 500-mA, 16-V Linear Voltage Regulator
1 Features
3 Description
•
AEC-Q100 qualified for automotive applications:
The TLV766-Q1 is a wide input linear voltage
regulator supporting an input voltage range from 2.5 V
to 16 V and up to 500 mA of load current. The output
range is from 0.8 V to 12 V or up to 14.6 V with the
adjustable version.
– Temperature grade 1: –40°C to +125°C, TA
– Junction temperature: –40°C to +150°C, TJ
Input voltage range: 2.5 V to 16 V (18 V max)
Output voltage range:
•
•
The wide input voltage range makes the device a
good choice for operating from transformer secondary
windings and regulated rails such as 10 V or 12 V.
Additionally, the wide output voltage range allows the
device to generate the bias voltage for silicon carbide
(SiC) gate drivers and microphones as well as power
microcontrollers (MCUs) and processors.
– 0.8 V to 14.6 V (adjustable)
– 1.2 V to 12 V (fixed)
1% output accuracy over load and temperature
Low quiescent current (IQ):
– 50 µA (typ) with no load
•
•
– 4 µA (max) when disabled
•
•
•
•
•
High PSRR: 70 dB at 1 kHz, 46 dB at 1 MHz
Internal soft-start time: 500 µs (typical)
Fold-back current limiting and thermal protection
Stable with a 1-µF or larger capacitor
Package: 8-pin, 3-mm × 3-mm WSON with
wettable flanks
The TLV766-Q1 has a 1% output accuracy that is
required for powering digital loads with tight supply
requirements.
The internal soft-start circuit reduces inrush current
during startup, thus allowing for smaller input
capacitance.
– Low thermal resistance (RθJA): 51.9°C/W
Wide bandwidth PSRR performance is greater than
70 dB at 1 kHz and 46 dB at 1 MHz, which helps
attenuate the switching frequency of an upstream
DC/DC converter and minimizes post regulator
filtering. The high ripple rejection from 20 Hz to
20 kHz make the device a good choice for powering
audio components.
2 Applications
•
•
•
•
DC/DC converters
Inverter and motor controls
On-board (OBC) and wireless chargers
Automotive head units
The TLV766-Q1 is available in a 8-pin, 3-mm × 3-mm
VSON (DRB) package with wettable flanks and low
thermal resistance.
Device Information (1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
TLV766-Q1
VSON (8)
3.00 mm × 3.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
100
90
80
70
60
50
40
30
20
OUT
FB
IN
TLV766-Q1
CIN
R1 CFF COUT
EN
GND
R2
IOUT
100 mA
0
10
10
100
1k
10k
Frequency (Hz)
100k
1M
10M
Typical Application Circuit
PSRR Performance
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TLV766-Q1
SBVS382 – DECEMBER 2020
www.ti.com
Table of Contents
1 Features............................................................................1
2 Applications.....................................................................1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings ....................................... 4
6.2 ESD Ratings .............................................................. 4
6.3 Recommended Operating Conditions ........................5
6.4 Thermal Information ...................................................5
6.5 Electrical Characteristics ............................................6
6.6 Typical Characteristics................................................7
7 Detailed Description......................................................11
7.1 Overview................................................................... 11
7.2 Functional Block Diagrams....................................... 11
7.3 Feature Description...................................................12
7.4 Device Functional Modes..........................................15
8 Application and Implementation..................................16
8.1 Application Information............................................. 16
8.2 Typical Application.................................................... 19
9 Power Supply Recommendations................................20
10 Layout...........................................................................21
10.1 Layout Guidelines .................................................. 21
10.2 Layout Examples.................................................... 21
11 Device and Documentation Support..........................22
11.1 Device Support........................................................22
11.2 Documentation Support.......................................... 22
11.3 Receiving Notification of Documentation Updates..22
11.4 Support Resources................................................. 22
11.5 Trademarks............................................................. 22
11.6 Electrostatic Discharge Caution..............................22
11.7 Glossary..................................................................22
12 Mechanical, Packaging, and Orderable
Information.................................................................... 23
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
DATE
REVISION
NOTES
December 2020
*
Initial release.
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5 Pin Configuration and Functions
OUT
NC
1
2
3
4
8
7
6
5
IN
OUT
NC
1
2
3
4
8
7
6
5
IN
NC
GND
EN
NC
GND
EN
Thermal
Pad
Thermal
Pad
FB
SNS
GND
GND
Not to scale
Not to scale
Figure 5-1. DRB Package (Adjustable Version),
8-Pin WSON, Top View
Figure 5-2. DRB Package (Fixed Version),
8-Pin WSON, Top View
Table 5-1. Pin Functions
PIN
I/O
DESCRIPTION
DRB
DRB
NAME
(Adjustable)
(Fixed)
Enable pin. Driving the enable pin high enables the device. Driving this pin low
disables the device. High and low thresholds are listed in the Electrical
Characteristics table. This pin has an internal pullup resistor and can be left
floating to enable the device or the pin can be connected to the input pin.
EN
5
3
5
Input
Input
Feedback pin. Input to the control-loop error amplifier. This pin is used to set the
output voltage of the device with the use of external resistors. Do not float this
pin. For adjustable-voltage version devices only.
FB
—
GND
NC
4, 6
2, 7
4, 6
2, 7
—
—
Ground pin. All ground pins must be grounded.
NC pin. Not internally connected. This pin can be either floated or connected to
GND for best thermal performance.
Input pin. Use the recommended capacitor value as listed in the Recommended
Operating Conditions table. Place the input capacitor as close to the IN and GND
pins of the device as possible.
IN
8
1
8
1
3
Input
Output
Input
—
Output pin. Use the recommended capacitor value as listed in the
Recommended Operating Conditions table. Place the output capacitor as close
to the OUT and GND pins of the device as possible.
OUT
Output sense pin. Connect the SNS pin to the OUT pin, or to remotely sense the
output voltage at the load, connect the SNS pin to the load. Do not float this pin.
For fixed-voltage version devices only.
SNS
—
Exposed pad of the package. Connect this pad to ground or leave floating.
Connect the thermal pad to a large-area ground plane for best thermal
performance.
Thermal pad
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6 Specifications
6.1 Absolute Maximum Ratings
Over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.3
MAX
18
UNIT
Input pin, IN
Output pin, OUT(3)
–0.3
VIN + 0.3
VIN + 0.3
3
Voltage(2)
Sense pin, SNS(3)
Feedback pin, FB
Enable pin, EN
–0.3
V
–0.3
–0.3
18
Current
Maximum output current
Ambient (TA)
Internally limited
–40
A
125
150
150
Temperature
Operating junction (TJ)
–50
°C
Storage (TSTG
)
–65
(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) All voltages with respect to GND.
(3) VIN + 0.3 V or 18 V (whichever is smaller).
6.2 ESD Ratings
VALUE
±2000
±500
UNIT
Human body model (HBM), per AEC Q100-002(1)
V(ESD)
Electrostatic discharge
All pins
V
Charged-device model (CDM),
per AEC Q100-011
Corner pins
±750
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
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6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
2.5
0
NOM
MAX
16
UNIT
V
VIN
Input voltage
VEN
Enable voltage
16
V
VOUT
IOUT
Output voltage
0.8
0
14.6
500
220
500
V
Output current
mA
µF
mΩ
µF
pF
µA
°C
°C
COUT
COUT ESR
CIN
Output capacitor(1)
1
2.2
Output capacitor ESR
2
Input capacitor
1
CFF
Feed-forward capacitor (optional(2), for adjustable device only)
Feedback divider current(2) (adjustable device only)
Ambient temperature range
Junction temperature range
10
IFB_DIVIDER
TA
5
–40
–40
125
150
TJ
(1) Effective output capacitance of 0.5 µF minimum required for stability.
(2) CFF required for stability if the feedback divider current < 5 µA. Feedback divider current = VOUT / (R1 + R2). See the Feed-Forward
Capacitor (CFF) section for details.
6.4 Thermal Information
TLV766-Q1
THERMAL METRIC(1)
DRB (VSON)
8 PINS
51.9
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
66.2
24.4
ΨJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
2.7
ΨJB
24.3
RθJC(bot)
6.9
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Electrical Characteristics
specified at TJ = –40°C to 150°C, VIN = VOUT(nom) + 1.5 V or VIN = 2.5 V (whichever is greater), FB/SNS tied to OUT, IOUT = 10
mA, VEN = 2 V, CIN = 1.0 µF, and COUT = 1.0 µF (unless otherwise noted); typical values are at TJ= 25ºC
PARAMETER
TEST CONDITIONS
MIN TYP MAX UNIT
TJ = 25°C
–0.5
–1
0.5
1
VOUT
Output accuracy
%
TJ = –40°C to
150°C
VIN ≥ 2.5 V, 1 mA ≤ IOUT ≤ 500 mA
VFB
VREF
IFB
Feedback voltage
0.8
V
%
TJ = 25°C
–0.5
–1
0.5
1
Internal reference (adjustable device)
TJ = –40°C to 150°C
Feedback pin current
VFB = 1 V
–20
1
50
nA
ΔVOUT(ΔVIN) Line regulation(1)
VOUT(NOM) +1.5 V ≤ VIN ≤ 16 V, IOUT = 10 mA
1 mA ≤ IOUT ≤ 500 mA
0.02 %/V
0.5 %/A
0.75
ΔVOUT(ΔIOUT) Load regulation
–0.5
0.3
0.55
50
0.1
VDO
ICL
Dropout voltage(2)
IOUT = 500 mA
Output current limit
Short-circuit current limit
VOUT = 0.9 x VOUT(NOM)
VOUT = 0 V
0.7
125
50
0.8
200
80
A
ISC
mA
Adjustable output device, IOUT = 0 mA
Fixed output devices, IOUT = 0 mA
VEN ≤ 0.4 V, VIN = 16 V
2.5 V ≤ VIN ≤ 16 V
25
IQ
Quiescent current
µA
25
60
95
ISHUTDOWN
VEN(HIGH)
VEN(LOW)
IEN
Shutdown current
0.1
1.2
1.6
4
µA
V
Enable pin logic high
Enable pin logic low
Enable pullup current
Output pulldown current
Power-supply rejection ratio
2.5 V ≤ VIN ≤ 16 V
0.4
800
1.6
V
VEN = 0 V
200
0.9
400
1.4
70
nA
mA
dB
IPULLDOWN
PSRR
VIN = 16 V, VOUT = 2.5 V, VEN = 0 V
VIN = 3.3 V, VOUT = 1.8 V, IOUT = 300 mA, f = 120 Hz
BW = 10 Hz to 100 kHz, VIN = 3.3 V, VOUT = 0.8 V,
IOUT = 100 mA
Vn
Output noise voltage
60
µVRMS
VUVLO+
UVLO threshold rising
UVLO threshold falling
UVLO hysteresis
VIN rising
VIN falling
2
2.22
2.4
2.3
V
V
VUVLO-
1.9 2.09
VUVLO(HYS)
100
130
180
160
200
mV
ºC
ºC
TSD(shutdown) Thermal shutdown temperature
TSD(reset) Thermal shutdown reset temperature
Temperature increasing
Temperature falling
(1) Line regulation is measured with VIN = VOUT(NOM) + 1.5 V or 2.5 V (whichever is greater).
(2) VDO is measured with VIN = 95% x VOUT(nom) for fixed output devices. VDO is not measured for fixed output devices when VOUT < 2.5 V.
For the adjustable output device, VDO is measured with VFB = 95% x VFB(nom) and VIN = 2.5 V.
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6.6 Typical Characteristics
at operating temperature TJ = 25°C, VIN = VOUT(NOM) + 1.5 V or 2.5 V (whichever is greater), IOUT = 10 mA, VEN = 2.0 V, CIN
=
1.0 µF, and COUT = 1.0 µF (unless otherwise noted)
0.2
0.2
0.1
0
0.1
0
-0.1
-0.2
-0.3
-0.1
-0.2
-0.3
-0.4
TJ
-50èC
-40èC
0èC
25èC
85èC
125èC
150èC
-50°C
-40°C
0°C
25°C
85°C
125°C
150°C
-0.4
0
0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Output Current (A)
2.5
4
5.5
7
8.5 10 11.5 13 14.5 16
Input Voltage (V)
VIN = 2.5 V
IOUT = 10 mA
Figure 6-1. VOUT Accuracy vs IOUT
Figure 6-2. VOUT Accuracy vs VIN
5
4
3
2
1
80
70
60
50
40
30
20
TJ
-50°C
-40°C
0°C
25°C
85°C
125°C
150°C
TJ
-50°C
-40°C
0°C
25°C
85°C
125°C
150°C
0
0
2.5
4.5
6.5
8.5 10.5
Input Voltage (V)
12.5
14.5
16
2
4
6
8
10
Input Voltage (V)
12
14
16
IOUT = 0 mA, adjustable-voltage version devices
Figure 6-4. IQ vs VIN
Figure 6-3. ISHUTDOWN vs VIN
90
80
70
60
50
40
30
2
1.6
1.2
0.8
0.4
0
VOUT
2.8 V
3.3 V
-50èC
-40èC
0èC
25èC
85èC
125èC
150èC
0.8 V
1.8 V
5.0 V
0
0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Output Current (A)
-50
-25
0
25
50
75
Temperature (°C)
100
125
150
VIN = 5 V
IOUT = 0 mA, fixed-voltage version devices
Figure 6-6. IGND vs IOUT
Figure 6-5. IQ vs Temperature
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6.6 Typical Characteristics (continued)
at operating temperature TJ = 25°C, VIN = VOUT(NOM) + 1.5 V or 2.5 V (whichever is greater), IOUT = 10 mA, VEN = 2.0 V, CIN
1.0 µF, and COUT = 1.0 µF (unless otherwise noted)
=
2
150
130
110
90
TJ
-50°C
-40°C
0°C
25°C
85°C
125°C
150°C
1.6
1.2
0.8
0.4
0
70
50
30
10
-50èC
-40èC
0èC
85èC
150èC
25èC
125èC
-10
0
0.5
1
1.5
Input Voltage (V)
2
2.5
3
0
0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Output Current (A)
IOUT = 0 mA
VIN = 2.5 V
Figure 6-8. IQ Increase Below Minimum VIN
Figure 6-7. IGND vs IOUT
300
200
700
30
20
40
35
30
25
20
15
10
5
IOUT
VOUT
VIN
600
VOUT
500
100
0
400
300
200
100
0
10
-100
-200
-300
-400
-500
-600
-700
-800
-900
0
-10
-20
-30
-40
-50
-100
-200
-300
-400
-500
0
100 200 300 400 500 600 700 800 900 1000
Time (µs)
0
100 200 300 400 500 600 700 800 900 1000
Time (µs)
0
D021
D038
VIN = 5 V, VOUT = 3.3 V, CFF = 10 pF, ramp rate = 0.4 A/µs
VOUT = 3.3 V, IOUT = 33 µA, VIN ramp rate = 1.6 V/µs
Figure 6-9. IOUT Transient From 0 mA to 100 mA
Figure 6-10. VIN Transient From 5 V to 16 V
0.8
0.9
-50èC
-40èC
0èC
25èC
85èC
125èC
150èC
-50èC
-40èC
0èC
25èC
85èC
125èC
150èC
0.75
0.6
0.45
0.3
0.15
0
0.7
0.6
0.5
0.4
0.3
0
0.1
0.2 0.3
Output Current (A)
0.4
0.5
2.5
4
5.5
7
8.5
10
Input Voltage (V)
11.5
13
14.5
16
VIN = 2.5 V
Figure 6-12. VDO vs IOUT
IOUT = 0.5 A
Figure 6-11. VDO vs VIN
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6.6 Typical Characteristics (continued)
at operating temperature TJ = 25°C, VIN = VOUT(NOM) + 1.5 V or 2.5 V (whichever is greater), IOUT = 10 mA, VEN = 2.0 V, CIN
=
1.0 µF, and COUT = 1.0 µF (unless otherwise noted)
5.5
5.5
5
VOUT
VIN
VEN
VOUT
VIN
VEN
5
4.5
4
4.5
4
3.5
3
3.5
3
2.5
2
2.5
2
1.5
1
1.5
1
0.5
0
0.5
0
-0.5
-0.5
0
0.5
1
1.5
2
2.5
Time (ms)
3
3.5
4
4.5
5
0
0.5
1
1.5
2
2.5
Time (ms)
3
3.5
4
4.5
5
D004
D032
EN pulled up internally, VOUT = 0.8 V
VOUT = 3.3 V
Figure 6-14. Startup With VEN Floating
Figure 6-13. Startup With Separate VEN and VIN
0.9
0.85
0.8
0.9
0.85
0.8
VEN(HIGH)
VEN(LOW)
0.75
0.7
0.75
0.7
0.65
0.6
0.65
0.6
VEN(HIGH)
VEN(LOW)
-50
-25
0
25
50
75
100
125
150
-50
-25
0
25
50
75
100
125
150
Temperature (èC)
Temperature (èC)
VIN = 2.5 V
VIN = 16 V
Figure 6-15. VEN Thresholds vs Temperature
Figure 6-16. VEN Thresholds vs Temperature
2.3
2.25
2.2
100
90
80
70
60
50
40
30
20
10
0
VUVLO+ (VIN rising)
VUVLO- (VIN falling)
2.15
2.1
CFF
0 nF
1.0 nF
2.05
2
-50
-25
0
25
50
75
100
125
150
10
100
1k
10k
Frequency (Hz)
100k
1M
10M
Temperature (èC)
VOUT = 3.3 V, VIN = 4.8 V, IOUT = 0.33 A
Figure 6-18. PSRR vs Frequency and CFF
Figure 6-17. UVLO Thresholds vs Temperature
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6.6 Typical Characteristics (continued)
at operating temperature TJ = 25°C, VIN = VOUT(NOM) + 1.5 V or 2.5 V (whichever is greater), IOUT = 10 mA, VEN = 2.0 V, CIN
1.0 µF, and COUT = 1.0 µF (unless otherwise noted)
=
20
10
5
700
600
500
400
300
200
100
2
1
0.5
0.2
0.1
0.05
VOUT
0.8 V, RMS Noise = 66.4 mVRMS
3.3 V, RMS Noise = 216.5 mVRMS
0.02
0.01
TJ
-50°C
-40°C
0°C
25°C
85°C
125°C
150°C
0.005
10
100
1k
10k
Frequency (Hz)
100k
1M
10M
2.5
4.5
6.5
8.5 10.5
Input Voltage (V)
12.5
14.5
16
CFF = 0 nF, IOUT = 0.1 A, RMS noise BW = 10 Hz to 100 kHz
VEN = 0 V
Figure 6-19. Output Noise (Vn) vs Frequency and VOUT
Figure 6-20. IEN vs VIN
1.5
1.4
1.3
1.2
100
90
80
70
60
50
40
30
20
10
0
VIN
2.5 V
7.5 V
12.5 V
16 V
1.1
TJ
-50°C
-40°C
0°C
25°C
85°C
125°C
150°C
1
-10
-50
0.9
2.5
-25
0
25
50
75
Temperature (°C)
100
125
150
4.5
6.5
8.5 10.5
Input Voltage (V)
12.5
14.5
16
VFB = 1.0 V
Figure 6-22. IFB vs Temperature
VOUT = 2.5 V
Figure 6-21. IPULLDOWN vs VIN
9
8
0.75
0.5
9
8
0.75
0.5
0.25
0
7
0.25
0
7
6
6
5
-0.25
-0.5
-0.75
-1
5
-0.25
-0.5
VOUT
IIN
VIN
VOUT
IIN
VIN
VEN
4
4
3
3
-0.75
-1
VEN
2
2
1
-1.25
-1.5
-1.75
1
-1.25
-1.5
0
0
-1
-1
-1.75
0
0.5
1
1.5
2
2.5
Time (ms)
3
3.5
4
4.5
5
0
0.5
1
1.5
2
2.5
Time (ms)
3
3.5
4
4.5
5
D003
D031
VOUT = 3.3 V, IOUT = 33 µA
VOUT = 3.3 V, IOUT = 33 µA
Figure 6-24. Startup Inrush Current With COUT = 47 µF
Figure 6-23. Startup Inrush Current With COUT = 22 µF
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7 Detailed Description
7.1 Overview
The TLV766-Q1 is a low quiescent current, high PSRR linear regulator capable of handling up to 500 mA of load
current. Unlike typical high current linear regulators, the TLV766-Q1 consumes significantly less quiescent
current. This device is ideal for high current applications that require very sensitive power-supply rails.
This device features an integrated foldback current limit, thermal shutdown, output enable, internal output
pulldown, and undervoltage lockout (UVLO). This device delivers excellent line and load transient performance.
This device is low noise and exhibits very good PSRR. The operating ambient temperature range of the device is
–40°C to +125°C.
7.2 Functional Block Diagrams
Current Limit
IN
OUT
Internal
Controller
UVLO
FB
0.8-V
Reference
EN
Thermal
Shutdown
Output
Pulldown
GND
Figure 7-1. Adjustable-Version Block Diagram
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Current Limit
IN
OUT
SNS
R1
2 pF
Internal
Controller
UVLO
R2
0.8-V
Reference
EN
Thermal
Shutdown
Output
Pulldown
Internal Resistors
R1 531 kΩ or 1.062 MΩ
R2
66.9 kΩ œ 8.5 MΩ
GND
Figure 7-2. Fixed-Version Block Diagram
7.3 Feature Description
7.3.1 Output Enable
The enable pin for the device is an active-high pin. The output voltage is enabled when the voltage of the enable
pin is greater than the high-level input voltage of the EN pin and disabled with the enable pin voltage is less than
the low-level input voltage of the EN pin. If independent control of the output voltage is not needed, connect the
enable pin to the input of the device.
This device has an internal pullup current on the EN pin. The EN pin can be left floating to enable the device.
The device has an internal pulldown circuit that activates when the device is disabled to actively discharge the
output voltage.
7.3.2 Dropout Voltage
Dropout voltage (VDO) is defined as the input voltage minus the output voltage (VIN – VOUT) at the rated output
current (IRATED), where the pass transistor is fully on. IRATED is the maximum IOUT listed in the Recommended
Operating Conditions table. The pass transistor is in the ohmic or triode region of operation, and acts as a
switch. The dropout voltage indirectly specifies a minimum input voltage greater than the nominal programmed
output voltage at which the output voltage is expected to stay in regulation. If the input voltage falls to less than
the nominal output regulation, then the output voltage falls as well.
For a CMOS regulator, the dropout voltage is determined by the drain-source on-state resistance (RDS(ON)) of the
pass transistor. Therefore, if the linear regulator operates at less than the rated current, the dropout voltage for
that current scales accordingly. The following equation calculates the RDS(ON) of the device.
VDO
RDS(ON)
=
IRATED
(1)
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7.3.3 Foldback Current Limit
The device has an internal current limit circuit that protects the regulator during transient high-load current faults
or shorting events. The current limit is a hybrid brickwall-foldback scheme. The current limit transitions from a
brickwall scheme to a foldback scheme at the foldback voltage (VFOLDBACK). In a high-load current fault with the
output voltage above VFOLDBACK, the brickwall scheme limits the output current to the current limit (ICL). When
the voltage drops below VFOLDBACK, a foldback current limit activates that scales back the current as the output
voltage approaches GND. When the output is shorted, the device supplies a typical current called the short-
circuit current limit (ISC). ICL and ISC are listed in the Electrical Characteristics table.
For this device, VFOLDBACK = 50% × VOUT(nom)
.
The output voltage is not regulated when the device is in current limit. When a current limit event occurs, the
device begins to heat up because of the increase in power dissipation. When the device is in brickwall current
limit, the pass transistor dissipates power [(VIN – VOUT) × ICL]. When the device output is shorted and the output
is below VFOLDBACK, the pass transistor dissipates power [(VIN – VOUT) × ISC]. If thermal shutdown is triggered,
the device turns off. After the device cools down, the internal thermal shutdown circuit turns the device back on.
If the output current fault condition continues, the device cycles between current limit and thermal shutdown. For
more information on current limits, see the Know Your Limits application report.
Figure 7-3 shows a diagram of the foldback current limit.
VOUT
Brickwall
VOUT(NOM)
VFOLDBACK
Foldback
0 V
IOUT
IRATED
0 mA
ISC
ICL
Figure 7-3. Foldback Current Limit
7.3.4 Undervoltage Lockout (UVLO)
The device has an independent undervoltage lockout (UVLO) circuit that monitors the input voltage, allowing a
controlled and consistent turn on and off of the output voltage. To prevent the device from turning off if the input
drops during turn on, the UVLO has hysteresis as specified in the Electrical Characteristics table.
7.3.5 Output Pulldown
The device has an output pulldown circuit. VOUT pulldown sink to ground capability is listed in the Electrical
Characteristics table. The output pulldown activates under the following conditions:
•
•
Device disabled
1.0 V < VIN < VUVLO
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The output pulldown current for this device is 1.2 mA typical, as listed in the Electrical Characteristics table of the
Specifications section.
Do not rely on the output pulldown circuit for discharging a large amount of output capacitance after the input
supply has collapsed because reverse current can flow from the output to the input. This reverse current flow
can cause damage to the device. See the Reverse Current section for more details.
7.3.6 Thermal Shutdown
The device contains a thermal shutdown protection circuit to disable the device when the junction temperature
(TJ) of the pass transistor rises to TSD(shutdown) (typical). Thermal shutdown hysteresis assures that the device
resets (turns on) when the temperature falls to TSD(reset) (typical).
The thermal time-constant of the semiconductor die is fairly short, thus the device may cycle on and off when
thermal shutdown is reached until power dissipation is reduced. Power dissipation during startup can be high
from large VIN – VOUT voltage drops across the device or from high inrush currents charging large output
capacitors. Under some conditions, the thermal shutdown protection disables the device before startup
completes.
For reliable operation, limit the junction temperature to the maximum listed in the Recommended Operating
Conditions table. Operation above this maximum temperature causes the device to exceed its operational
specifications. Although the internal protection circuitry of the device is designed to protect against thermal
overall conditions, this circuitry is not intended to replace proper heat sinking. Continuously running the device
into thermal shutdown or above the maximum recommended junction temperature reduces long-term reliability.
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7.4 Device Functional Modes
7.4.1 Device Functional Mode Comparison
The Device Functional Mode Comparison table shows the conditions that lead to the different modes of
operation. See the Electrical Characteristics table for parameter values.
Table 7-1. Device Functional Mode Comparison
PARAMETER
OPERATING MODE
VIN
VEN
IOUT
TJ
Normal operation
Dropout operation
VIN > VOUT(nom) + VDO and VIN > VIN(min)
VIN(min) < VIN < VOUT(nom) + VDO
VEN > VEN(HI)
VEN > VEN(HI)
IOUT < IOUT(max)
IOUT < IOUT(max)
TJ < TSD(shutdown)
TJ < TSD(shutdown)
Disabled
(any true condition
disables the device)
VIN < VUVLO
VEN < VEN(LOW)
Not applicable
TJ > TSD(shutdown)
7.4.2 Normal Operation
The device regulates to the nominal output voltage when the following conditions are met:
•
The input voltage is greater than the set MID_OUT output voltage plus the VMID_OUT dropout voltage
(VMID_OUT(nom) + VDO(MID_OUT)
)
•
The current sourced from OUT or MID_OUT is less than the current limits (IOUT < ICL(OUT) or IMID_OUT
ICL(MID_OUT)) respectively
<
•
•
The device junction temperature is less than the thermal shutdown temperature (TJ < TSD)
The enable voltage has previously exceeded the enable rising threshold voltage and has not yet decreased
to less than the enable falling threshold or the EN pin is left floating
7.4.3 Dropout Operation
If the input voltage is lower than the set MID_OUT voltage plus the specified VDO(MID_OUT) dropout voltage, but
all other conditions are met for normal operation, the device operates in VMID_OUT dropout mode. When the
devcie operates in this mode while VMID_OUT voltage is still higher than VOUT(nom) + VDO(OUT), then VOUT is still in
regulation however VMID_OUT voltage is in its dropout mode. In VMID_OUT dropout mode, VMID_OUT voltage tracks
the input voltage and during this mode, the transient performance of VMID_OUT voltage becomes significantly
degraded because the MID_OUT pass transistor is in the ohmic or triode region, and acts as a switch. Also
VMID_OUT line or load transients can result in large VMID_OUT voltage deviations.
The devcie enters VDO(OUT) dropout mode when the input voltage is lower than the set MID_OUT voltage and
VMID_OUT is lower than VOUT(nom) + VDO(OUT). In VOUT dropout mode, VOUT voltage tracks VMID_OUT voltage which
in return tracks the input voltage. During this mode, the transient performance of both VMID_OUT and VOUT
voltages becomes significantly degraded because the pass transistors are in the ohmic or triode region and
acting as switches. Also line or load transients can result in large VMID_OUT and VOUT voltages deviations.
When the device is in a steady dropout state (defined as when the device is in dropout, VIN < VOUT(NOM) + VDO
,
directly after being in a normal regulation state, but not during startup), the pass transistor is driven into the
ohmic or triode region. When the input voltage returns to a value greater than or equal to the nominal output
voltage plus the dropout voltage (VOUT(NOM) + VDO), the output voltage can overshoot for a short period of time
while the device pulls the pass transistor back into the linear region.
7.4.4 Disabled
The output of the device can be shutdown by forcing the voltage of the enable pin to less than the maximum EN
pin low-level input voltage (see the Electrical Characteristics table). When disabled, the pass transistor is turned
off, internal circuits are shutdown, and the output voltage is actively discharged to ground by an internal
discharge circuit from the output to ground.
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8 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
8.1 Application Information
8.1.1 Adjustable Device Feedback Resistors
The adjustable-version device requires external feedback divider resistors to set the output voltage. VOUT is set
using the feedback divider resistors, R1 and R2, according to the following equation:
VOUT = VFB × (1 + R1 / R2)
(2)
To ignore the FB pin current error term in the VOUT equation, set the feedback divider current to 100x the FB pin
current listed in the Electrical Characteristics table. This setting provides the maximum feedback divider series
resistance, as shown in the following equation:
R1 + R2 ≤ VOUT / (IFB × 100)
(3)
8.1.2 Recommended Capacitor Types
The device is designed to be stable using low equivalent series resistance (ESR) ceramic capacitors at the input
and output. Multilayer ceramic capacitors have become the industry standard for these types of applications and
are recommended, but must be used with good judgment. Ceramic capacitors that employ X7R-, X5R-, and
C0G-rated dielectric materials provide relatively good capacitive stability across temperature, whereas the use of
Y5V-rated capacitors is discouraged because of large variations in capacitance.
Regardless of the ceramic capacitor type selected, the effective capacitance varies with operating voltage and
temperature. As a rule of thumb, expect the effective capacitance to decrease by as much as 50%. The input
and output capacitors recommended in the Recommended Operating Conditions table account for an effective
capacitance of approximately 50% of the nominal value.
8.1.3 Input and Output Capacitor Requirements
Although an input capacitor is not required for stability, good analog design practice is to connect a capacitor
from IN to GND. This capacitor counteracts reactive input sources and improves transient response, input ripple,
and PSRR. An input capacitor is recommended if the source impedance is more than 0.5 Ω. A higher value
capacitor may be necessary if large, fast rise-time load or line transients are anticipated or if the device is
located several inches from the input power source.
Dynamic performance of the device is improved with the use of an output capacitor. Use an output capacitor
within the range specified in the Recommended Operating Conditions table for stability.
8.1.4 Reverse Current
Excessive reverse current can damage this device. Reverse current flows through the intrinsic body diode of the
pass transistor instead of the normal conducting channel. At high magnitudes, this current flow degrades the
long-term reliability of the device.
Conditions where reverse current can occur are outlined in this section, all of which can exceed the absolute
maximum rating of VOUT ≤ VIN + 0.3 V.
•
•
•
If the device has a large COUT and the input supply collapses with little or no load current
The output is biased when the input supply is not established
The output is biased above the input supply
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If reverse current flow is expected in the application, external protection is recommended to protect the device.
Reverse current is not limited in the device, so external limiting is required if extended reverse voltage operation
is anticipated.
Figure 8-1 shows one approach for protecting the device.
Schottky Diode
Internal Body Diode
IN
OUT
Device
COUT
CIN
GND
Figure 8-1. Example Circuit for Reverse Current Protection Using a Schottky Diode
8.1.5 Feed-Forward Capacitor (CFF)
For the adjustable-voltage version device, a feed-forward capacitor (CFF) can be connected from the OUT pin to
the FB pin. CFF improves transient, noise, and PSRR performance, but is not required for regulator stability.
Recommended CFF values are listed in the Recommended Operating Conditions table. A higher capacitance
CFF can be used; however, the startup time increases. For a detailed description of CFF tradeoffs, see the Pros
and Cons of Using a Feedforward Capacitor with a Low-Dropout Regulator application report.
CFF and R1 form a zero in the loop gain at frequency fZ, while CFF, R1, and R2 form a pole in the loop gain at
frequency fP. CFF zero and pole frequencies can be calculated from the following equations:
fZ = 1 / (2 × π × CFF × R1)
(4)
(5)
fP = 1 / (2 × π × CFF × (R1 || R2))
CFF ≥ 10 pF is required for stability if the feedback divider current is less than 5 µA. Equation 6 calculates the
feedback divider current.
IFB_Divider = VOUT / (R1 + R2)
(6)
To avoid startup time increases from CFF, limit the product CFF × R1 < 50 µs.
For an output voltage of 0.8 V with the FB pin tied to the OUT pin, no CFF is used.
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8.1.6 Power Dissipation (PD)
Circuit reliability requires consideration of the device power dissipation, location of the circuit on the printed
circuit board (PCB), and correct sizing of the thermal plane. The PCB area around the regulator must have few
or no other heat-generating devices that cause added thermal stress.
To first-order approximation, power dissipation in the regulator depends on the input-to-output voltage difference
and load conditions. The following equation calculates power dissipation (PD).
PD = (VIN – VOUT) × IOUT
(7)
Note
Power dissipation can be minimized, and therefore greater efficiency can be achieved, by correct
selection of the system voltage rails. For the lowest power dissipation use the minimum input voltage
required for correct output regulation.
For devices with a thermal pad, the primary heat conduction path for the device package is through the thermal
pad to the PCB. Solder the thermal pad to a copper pad area under the device. This pad area must contain an
array of plated vias that conduct heat to additional copper planes for increased heat dissipation.
The maximum power dissipation determines the maximum allowable ambient temperature (TA) for the device.
According to the following equation, power dissipation and junction temperature are most often related by the
junction-to-ambient thermal resistance (RθJA) of the combined PCB and device package and the temperature of
the ambient air (TA).
TJ = TA + (RθJA × PD)
(8)
Thermal resistance (RθJA) is highly dependent on the heat-spreading capability built into the particular PCB
design, and therefore varies according to the total copper area, copper weight, and location of the planes. The
junction-to-ambient thermal resistance listed in the Thermal Information table is determined by the JEDEC
standard PCB and copper-spreading area, and is used as a relative measure of package thermal performance.
8.1.7 Estimating Junction Temperature
The JEDEC standard now recommends the use of psi (Ψ) thermal metrics to estimate the junction temperatures
of the linear regulator when in-circuit on a typical PCB board application. These metrics are not thermal
resistance parameters and instead offer a practical and relative way to estimate junction temperature. These psi
metrics are determined to be significantly independent of the copper area available for heat-spreading. The
Thermal Information table lists the primary thermal metrics, which are the junction-to-top characterization
parameter (ψJT) and junction-to-board characterization parameter (ψJB). These parameters provide two methods
for calculating the junction temperature (TJ), as described in the following equations. Use the junction-to-top
characterization parameter (ψJT) with the temperature at the center-top of device package (TT) to calculate the
junction temperature. Use the junction-to-board characterization parameter (ψJB) with the PCB surface
temperature 1 mm from the device package (TB) to calculate the junction temperature.
TJ = TT + ψJT × PD
(9)
where:
•
•
PD is the dissipated power
TT is the temperature at the center-top of the device package
TJ = TB + ψJB × PD
(10)
where:
•
TB is the PCB surface temperature measured 1 mm from the device package and centered on the package
edge
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For detailed information on the thermal metrics and how to use them, see the Semiconductor and IC Package
Thermal Metrics application report
8.2 Typical Application
This section discusses implementing this device for a typical application. Figure 8-2 shows the application circuit.
OUT
FB
IN
TLV766-Q1
CIN
R1 CFF COUT
EN
GND
R2
Figure 8-2. Typical Application Circuit
8.2.1 Design Requirements
Table 8-1 summarizes the design requirements for this application.
Table 8-1. Design Parameters
PARAMETER
Input voltage
Output voltage
Output current
DESIGN REQUIREMENT
5 V
3.3 V
100 mA
8.2.2 Detailed Design Procedure
8.2.2.1 Transient Response
As with any regulator, increasing the size of the output capacitor reduces overshoot and undershoot magnitude.
If load transients are expected with ramp rates greater than 0.5 A/µs, use a 2.2-µF or larger output capacitor.
8.2.2.2 Choose Feedback Resistors
For this design example, VOUT is set to 3.3 V. The following equations set the feedback divider resistors for the
desired output voltage:
VOUT = VFB × (1 + R1 / R2)
R1 + R2 ≤ VOUT / (IFB × 100)
(11)
(12)
For improved output accuracy, use Equation 12 and IFB = 50 nA as listed in the Electrical Characteristics table in
the Specifications section to calculate the upper limit for series feedback resistance (R1 + R2 ≤ 660 kΩ).
The control-loop error amplifier drives the FB pin to the same voltage as the internal reference (VFB = 0.8 V, as
listed in the Electrical Characteristics table). Use Equation 11 to determine the ratio of R1 / R2 = 3.125. Use this
ratio and solve Equation 12 for R2. Now calculate the upper limit for R2 ≤ 160 kΩ. Select a standard value
resistor for R2 = 160 kΩ.
Reference Equation 11 and solve for R1:
R1 = (VOUT / VFB – 1) × R2
(13)
From Equation 13, R1 = 500 kΩ can be determined. Select a standard value resistor for R1 = 499 kΩ. VOUT
3.3 V (as determined by Equation 11).
=
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8.2.3 Application Curves
300
200
700
600
500
400
300
200
100
0
100
90
80
70
60
50
40
30
20
10
0
IOUT
VOUT
100
0
-100
-200
-300
-400
-500
-600
-700
-800
-900
-100
-200
-300
-400
-500
IOUT
100 mA
10
100
1k
10k
Frequency (Hz)
100k
1M
10M
0
100 200 300 400 500 600 700 800 900 1000
Time (µs)
D021
VIN = 5 V, VOUT = 3.3 V, COUT = 1 µF, CFF = 0 pF
VIN = 5 V, VOUT = 3.3 V, COUT = 1 µF, CFF = 10 pF
Figure 8-4. PSRR Performance
Figure 8-3. Load Transient Response, IOUT 0 mA to
100 mA
9 Power Supply Recommendations
This device is designed to operate from an input supply voltage range of 2.5 V to 16 V. To ensure that the output
voltage is well regulated and dynamic performance is optimum, the input supply must be at least VOUT(nom)
+
1.5 V or 2.5 V, whichever is greater. Connect a low output impedance power supply directly to the input pin of the
TLV766-Q1.
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10 Layout
10.1 Layout Guidelines
•
•
•
Place input and output capacitors as close to the device as possible
Use copper planes for device connections to IN, OUT, and GND pins to optimize thermal performance
Place thermal vias around the device to distribute heat
10.2 Layout Examples
OUT
NC
IN
NC
FB
GND
EN
GND
Denotes a via
Figure 10-1. Layout Example for the Adjustable Version
OUT
NC
IN
NC
SNS
GND
GND
EN
Denotes a via
Figure 10-2. Layout Example for the Fixed Version
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Device Nomenclature
Table 11-1. Available Options (1)
PRODUCT
VOUT
xx(x) is the nominal output voltage. For output voltages with a resolution of 100 mV, two
digits are used in the ordering number; otherwise, three digits are used (for example, 33
= 3.3 V; 125 = 1.25 V). 01 indicates the adjustable output version.
W indicates a wettable flanks package.
TLV766xx(x)QWyyyRQ1
yyy is the package designator.
R is the package quantity. R is for the large quantity reel.
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the
device product folder at www.ti.com.
11.2 Documentation Support
11.2.1 Related Documentation
For related documentation see the following:
•
•
Texas Instruments, TLV767EVM-014 Evaluation Module user's guide
Texas Instruments, Pros and Cons of Using a Feedforward Capacitor with a Low-Dropout Regulator
application report
•
•
Texas Instruments, Know Your Limits application report
Texas Instruments, Universal Low-Dropout (LDO) Linear Voltage Regulator MultiPkgLDOEVM-823 Evaluation
Module user's guide
11.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
11.4 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.5 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
11.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.7 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
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12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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20-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TLV76601QWDRBRQ1
ACTIVE
SON
DRB
8
3000 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 150
V76601
TLV76612QWDRBRQ1
TLV76618QWDRBRQ1
TLV76633QWDRBRQ1
PREVIEW
PREVIEW
ACTIVE
SON
SON
SON
DRB
DRB
DRB
8
8
8
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
NIPDAU
NIPDAU
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 150
-40 to 150
-40 to 150
V76612
V76618
V76633
TLV76650QWDRBRQ1
ACTIVE
SON
DRB
8
3000 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 150
V76650
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
20-Dec-2020
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Dec-2020
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TLV76601QWDRBRQ1
TLV76633QWDRBRQ1
TLV76650QWDRBRQ1
SON
SON
SON
DRB
DRB
DRB
8
8
8
3000
3000
3000
330.0
330.0
330.0
12.4
12.4
12.4
3.3
3.3
3.3
3.3
3.3
3.3
1.1
1.1
1.1
8.0
8.0
8.0
12.0
12.0
12.0
Q2
Q2
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Dec-2020
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TLV76601QWDRBRQ1
TLV76633QWDRBRQ1
TLV76650QWDRBRQ1
SON
SON
SON
DRB
DRB
DRB
8
8
8
3000
3000
3000
367.0
367.0
367.0
367.0
367.0
367.0
35.0
35.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
VSON - 1 mm max height
DRB0008J
PLASTIC QUAD FLAT PACK- NO LEAD
3.1
2.9
B
A
PIN 1 INDEX AREA
3.1
2.9
0.1 MIN
(0.13)
SECTION A-A
TYPICAL
1 MAX
C
SEATING PLANE
0.08 C
0.05
0.00
1.75
1.55
(0.2) TYP
6X 0.65
(0.19)
4
5
SYMM
9
2.5
2.3
1.95
1
8
0.36
0.26
8X
PIN 1 ID
(OPTIONAL)
0.1
0.05
C A B
C
SYMM
0.5
0.3
8X
4225036/A 06/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
VSON - 1 mm max height
DRB0008J
PLASTIC QUAD FLAT PACK- NO LEAD
(2.8)
(1.65)
8X (0.6)
8X (0.31)
SYMM
1
8
6X (0.65)
SYMM
9
(1.95) (2.4)
(0.95)
(R0.05) TYP
4
5
(Ø 0.2) VIA
TYP
(0.575)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 20X
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
METAL
SOLDER MASK
OPENING
EXPOSED METAL
EXPOSED METAL
SOLDER MASK
OPENING
METAL
NON- SOLDER MASK
SOLDER MASK
DEFINED
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4225036/A 06/2019
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
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EXAMPLE STENCIL DESIGN
VSON - 1 mm max height
DRB0008J
PLASTIC QUAD FLAT PACK- NO LEAD
(2.8)
2X
(1.51)
8X (0.6)
8X (0.31)
SYMM
1
8
2X
(1.06)
6X (0.65)
SYMM
(1.95)
(0.63)
9
(R0.05) TYP
4
5
METAL
TYP
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
81% PRINTED COVERAGE BY AREA
SCALE: 20X
4225036/A 06/2019
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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