TLV853 [TI]
具有低电平有效开漏复位功能的 3 引脚电压监控器;
| 型号： | TLV853 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有低电平有效开漏复位功能的 3 引脚电压监控器 监控 |
| 文件： | 总25页 (文件大小：1213K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TLV803, TLV853, TLV863
ZHCS187E –APRIL 2011 –REVISED DECEMBER 2020
TLV8x3 具有低电平有效的开漏复位功能的3 引脚电压监控器
1 特性
3 说明
• 3 引脚SOT23 封装
TLV8x3 系列监控电路主要为数字信号处理器(DSP) 以
及基于处理器的系统提供电路初始化和时序监控。
• 电源电流：9µA（典型值）
• 精密电源电压监控器：
2.5V、3V、3.3V、5V
• 固定延时时间为200ms 的
上电复位发生器
• 与MAX803 引脚兼容
• 温度范围：–40°C 至+125°C
• 开漏、RESET 输出
TLV803、TLV853 和 TLV863 在功能上是等效的。
TLV853 和 TLV863 分别提供了与 TLV803 不同的替代
引脚分配。新款 TLV803E 器件是所有这 3 种器件的引
脚对引脚替代品。
上电期间，RESET 会在电源电压 (VDD) 超出 1.1V 时
置为有效。因此只要满足以下条件，监控电路就会监视
VDD 并将RESET 保持为有效状态：VDD 保持在阈值电
压VIT 以下。内部定时器将使输出延迟恢复至待机状态
2 应用
（高电平），以确保系统正常复位。延迟时间 (td(typ)
=
• 工厂自动化
• 便携式和电池供电类设备
• 机顶盒
• 服务器
• 电器
200ms) 从 VDD 超过阈值电压 VIT 后开始。当电源电压
降至阈值电压 VIT 以下时，输出再次变为激活状态（低
电平）。该系列中的所有器件均具有一个通过内部分压
器设定的固定感测阈值电压(VIT)。
• 电表
• 楼宇自动化
该产品系列专为 2.5V、3V、 3.3 以及 5V 电源电压而
设计。这些器件采用 3 引脚小外形尺寸晶体管
(SOT)-23 封装。TLV803 器件的额定工作温度范围为
-40°C 至+125°C。
器件信息(1)
封装尺寸（标称值）
器件型号
TLV8x3
封装
SOT-23 (3)
2.92mm × 1.30mm
(1) 如需了解所有可用封装，请参阅数据表末尾的封装选项附录。
3.3-V LDO
OUT
3.3 V
5 V
IN
GND
VDD
DSP/FPGA/ASIC
VDD
TLV803S
RESET
GND
RESET
GND
典型应用
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SBVS157
TLV803, TLV853, TLV863
ZHCS187E –APRIL 2011 –REVISED DECEMBER 2020
www.ti.com.cn
Table of Contents
8.4 Device Functional Modes............................................9
9 Application and Implementation..................................10
9.1 Application Information............................................. 10
9.2 Typical Application.................................................... 11
10 Power Supply Recommendations..............................12
11 Layout...........................................................................13
11.1 Layout Guidelines................................................... 13
11.2 Layout Example...................................................... 13
12 Device and Documentation Support..........................14
12.1 Device Support....................................................... 14
12.2 Documentation Support.......................................... 14
12.3 Related Links.......................................................... 14
12.4 支持资源..................................................................14
12.5 Trademarks.............................................................15
12.6 静电放电警告.......................................................... 15
12.7 术语表..................................................................... 15
13 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Device Comparison.........................................................4
6 Pin Configuration and Functions...................................4
Pin Functions.................................................................... 4
7 Specifications.................................................................. 5
7.1 Absolute Maximum Ratings(1) ....................................5
7.2 ESD Ratings............................................................... 5
7.3 Thermal Information....................................................5
7.4 Recommended Operating Conditions.........................5
7.5 Electrical Characteristics.............................................6
7.6 Switching Characteristics............................................6
7.7 Typical Characteristics................................................7
8 Detailed Description........................................................8
8.1 Overview.....................................................................8
8.2 Functional Block Diagram...........................................8
8.3 Feature Description.....................................................8
Information.................................................................... 15
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision D (November 2020) to Revision E (December 2020)
Page
• Corrected missed VDD change from 7 to 6.5 in Absolute Maximum Ratings in note 2......................................5
Changes from Revision C (September 2015) to Revision D (November 2020)
Page
• 更新了整个文档中的表格、图和交叉参考的编号格式.........................................................................................1
• 向说明 部分添加了有关 TLV803E 的描述...........................................................................................................1
• Changed VDD from 7 to 6.5 in Absolute Maximum Ratings ..............................................................................5
• Changed VOL@ 500μA from 0.2 to 0.3 in Electrical Characteristics ................................................................ 6
• Changed IOH from 100 nA to 350 nA in Electrical Characteristics .....................................................................6
• Changed tw from 1 to 10 μs in Switching Characteristics .................................................................................6
• Deleted figure Minimum Pulse Duration At VDD vs Overdrive Voltage in Typical Characteristics.......................7
• Changed figure from Pulse Duration to VOL, IOL in the Typical Application Section......................................... 12
Changes from Revision B (August 2011) to Revision C (September 2015)
Page
• 向数据表添加了 TLV853 器件.............................................................................................................................1
• 更改了页眉中显示的器件型号，以显示单个TLV803 器件，而不是标有字母的器件版本...................................1
• 添加了器件信息 表和 ESD 等级 表.....................................................................................................................1
• 添加了详细说明、应用和实现、电源相关建议、布局、器件和文档支持 以及机械、封装和可订购信息 部分....1
• 更改了应用 部分的列表项...................................................................................................................................1
• 删除了首页中的引脚排列并将其移至引脚配置和功能 部分................................................................................ 1
• Changed "free-air temperature" to "junction temperature" in Absolute Maximum Ratings condition
statement ...........................................................................................................................................................5
• Deleted Soldering temperature from Absolute Maximum Ratings table ............................................................5
• Changed Thermal Information table; updated thermal resistance values for all parameters ............................ 5
• Changed "free-air temperature" to "junction temperature" in Electrical Characteristics condition statement .... 6
• Changed temperature noted in Switching Characteristics condition statement .................................................6
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SBVS157
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TLV803, TLV853, TLV863
ZHCS187E –APRIL 2011 –REVISED DECEMBER 2020
www.ti.com.cn
Changes from Revision A (June 2011) to Revision B (August 2011)
Page
• 向说明 部分添加了有关TLV863 的段落............................................................................................................. 1
• 在首页中添加了 TLV863 引脚排列......................................................................................................................1
• Added TLV863 to Thermal Information...............................................................................................................5
• Added TLV863M to Negative-Going Input Threshold Voltage parameter...........................................................6
• Added TLV863M to Hysteresis parameter..........................................................................................................6
• Added TLV863 to Functional Block Diagram......................................................................................................8
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Product Folder Links: TLV803 TLV853 TLV863
English Data Sheet: SBVS157
TLV803, TLV853, TLV863
ZHCS187E –APRIL 2011 –REVISED DECEMBER 2020
www.ti.com.cn
5 Device Comparison
表5-1. Device Threshold Options
DEVICE
TLV803Z
TLV803R
TLV803S
TLV803M
TLV853M
TLV863M
THRESHOLD VOLTAGE
2.25 V
2.64 V
2.93 V
4.38 V
4.38 V
4.38 V
表5-2. Device Family Comparison
DEVICE
TLV803
TLV809
TLV810
FUNCTION
Open-Drain, RESET Output
Push-Pull, RESET Output
Push-Pull, RESET Output
6 Pin Configuration and Functions
1
GND
1
2
RESET
3
VDD
3
VDD
2
RESET
GND
图6-1. TLV803: DBZ Package
3-Pin SOT-23
图6-2. TLV853: DBZ Package
3-Pin SOT-23
Top View
Top View
1
2
RESET
3
GND
VDD
图6-3. TLV863: DBZ Package
3-Pin SOT-23
Top View
Pin Functions
PIN
I/O
DESCRIPTION
NAME
GND
TLV803
TLV853
TLV863
1
2
3
Ground pin.
—
RESET is an open-drain output that is driven to a low impedance state
when RESET is asserted. RESET remains low (asserted) for the delay time
(td) after VDD exceeds VIT–. Use a 10-kΩ to 1-MΩ pullup resistor on this
RESET
VDD
2
1
3
1
2
O
pin. The pullup voltage is not limited by VDD
.
Supply voltage pin. It is good analog design practice to place a 0.1-µF
ceramic capacitor close to this pin.
3
I
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English Data Sheet: SBVS157
TLV803, TLV853, TLV863
ZHCS187E –APRIL 2011 –REVISED DECEMBER 2020
www.ti.com.cn
7 Specifications
7.1 Absolute Maximum Ratings(1)
over operating junction temperature range (unless otherwise noted)
MIN
0
MAX
6.5
UNIT
VDD(2)
Voltage
V
All other pins(2)
+6.5
5
–0.3
Maximum low output current, IOL
Maximum high output current, IOH
Current
–5
±20
±20
125
150
mA
°C
Input clamp current, IIK (VI < 0 or VI > VDD
)
Output clamp current, IOK (VO < 0 or VO > VDD
Operating junction temperature range, TJ
Storage temperature range, Tstg
)
–40
–65
Temperature
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to GND. For reliable operation the device should not be operated at 6.5 V for more than t = 1000h
continuously
7.2 ESD Ratings
VALUE
±2000
±500
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Electrostatic
discharge
V(ESD)
V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Thermal Information
TLV8x3
THERMAL METRIC(1)
DBZ (SOT-23)
3 PINS
328.5
135.4
58.3
UNITS
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
5.2
ψJT
59.6
ψJB
RθJC(bot)
N/A
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
7.4 Recommended Operating Conditions
at specified temperature range (unless otherwise noted)
MIN
1.1
MAX UNIT
VDD
TJ
Supply voltage
6
V
Operating junction temperature
125
°C
–40
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English Data Sheet: SBVS157
TLV803, TLV853, TLV863
ZHCS187E –APRIL 2011 –REVISED DECEMBER 2020
www.ti.com.cn
7.5 Electrical Characteristics
over recommended operating junction temperature range (unless otherwise noted)
PARAMETER
Low-level output voltage
Power-up reset voltage(1)
TEST CONDITIONS
VDD = 2 V to 6 V, IOL = 500 µA
VDD = 3.3 V, IOL = 2 mA
MIN
TYP
MAX UNIT
0.3
VOL
0.4
0.4
V
V
VDD = 6 V, IOL = 4 mA
IOL = 50 µA, VOL < 0.2 V
1.1
2.20
2.58
2.87
4.28
TLV803Z
TLV803R
TLV803S
TLV8x3M
TLV803Z
TLV803R
TLV803S
TLV8x3M
2.25
2.64
2.93
4.38
30
2.30
2.70
2.99
4.48
Negative-going input
threshold voltage(2)
VIT–
V
TJ = –40°C to +125°C
35
Vhys
Hysteresis
TJ = 25°C, IOL = 50 µA
mV
40
60
VDD = 2 V, output unconnected
VDD = 6 V, output unconnected
VDD = 6 V
9
15
30
IDD
IOH
Supply current
µA
nA
20
Output leakage current
350
(1) The lowest supply voltage at which RESET becomes valid. tr,VDD ≤66.7 V/ms.
(2) To ensure best stability of the threshold voltage, place a bypass capacitor (0.1-µF ceramic) near the supply terminals.
7.6 Switching Characteristics
over operating temperature range (unless otherwise noted)
PARAMETER
Pulse duration at VDD
Delay time
TEST CONDITIONS
MIN
TYP
10
MAX UNIT
tw
td
VDD = 1.08 VIT– to 0.92 VIT–
µs
120
200
280
ms
VDD ≥VIT– + 0.2 V; see Timing Diagram
VDD
VIT-
1.1 V
t
RESET
1
0
t
td
td
For VDD < 1.1 V Undefined
Behavior of RESET Output
图7-1. Timing Diagram
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English Data Sheet: SBVS157
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7.7 Typical Characteristics
at TJ = 25°C, VIT– = 4.38 V, and VDD = 5.0 V (unless otherwise noted)
1.2
1
25
20
15
10
5
+125°C
+85°C
+25°C
0°C
+125°C
+85°C
+25°C
0°C
0.8
0.6
0.4
0.2
0
-40°C
-40°C
VDD = 2.5 V
4
0
0
1
2
3
5
0
1
2
3
4
5
6
IOL (mA)
VDD (V)
图7-2. Low-Level Output Voltage vs Low-Level
图7-3. Supply Current vs Supply Voltage
Output Current
1.001
1
220
TLV803M
TLV803Z
210
0.999
0.998
0.997
0.996
0.995
0.994
200
190
180
170
160
-40 -25 -10
5
20 35 50 65 80 95 110 125
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
Temperature (°C)
图7-4. Normalized to 25°C Negative-Going Input
图7-5. Delay Time vs Temperature
Threshold Voltage vs Temperature
0.8
RESET Pulled Up to VDD
+125°C
+85°C
+25°C
0°C
0.7
with 22.1-kW Resistor
0.6
0.5
0.4
0.3
0.2
0.1
0
-40°C
0
0.25
0.5
0.75
1
1.25
1.5
VDD (V)
图7-6. Power-Up Low-Level Output Voltage vs Supply Voltage
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English Data Sheet: SBVS157
TLV803, TLV853, TLV863
ZHCS187E –APRIL 2011 –REVISED DECEMBER 2020
www.ti.com.cn
8 Detailed Description
8.1 Overview
The TLV803 family of supervisory circuits provides circuit initialization and timing supervision. The TLV853 and
TLV863 are both functionally equivalent to the TLV803. These devices output a logic low whenever VDD drops
below the negative-going threshold voltage (VIT–). The output, RESET, remains low for approximately 200 ms
after the VDD voltage exceeds the positive-going threshold voltage (VIT– + Vhys). These devices are designed to
ignore fast transients on the VDD pin.
8.2 Functional Block Diagram
TLV8x3
R1
Reset
Logic
+
_
+
RESET
VDD
GND
Timer
R2
Oscillator
Reference
Voltage
of 1.137 V
8.3 Feature Description
8.3.1 VDD Transient Rejection
The TLV803 has built-in rejection of fast transients on the VDD pin. The rejection of transients depends on both
the duration and the amplitude of the transient. The amplitude of the transient is measured from the bottom of
the transient to the negative threshold voltage of the TLV803, as shown in 图8-1.
VDD
VIT-
Transient
Amplitude
tw
Duration
图8-1. Voltage Transient Measurement
The TLV803 does not respond to transients that are fast duration/low amplitude or long duration/small amplitude.
Transients meeting or longer than the tw specified in the switching characteristics section triggers a reset.
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8.3.2 Reset During Power Up and Power Down
The TLV803 output is valid when VDD is greater than 1.1 V. When VDD is less than 1.1 V, the output transistor
turns off and becomes high impedance. The voltage on the RESET pin rises to the voltage level connected to
the pull-up resistor. 图 8-2 shows a typical waveform for power-up, assuming the RESET pin has a pull-up
resistor connected to the VDD pin.
VIT- + VHYS
VDD
1.1 V
td
RESET
Valid Output
图8-2. Power-Up Response
8.3.3 Bidirectional Reset Pins
Some microcontrollers have bidirectional reset pins that act as both inputs and outputs. In a situation where the
TLV803 is pulling the RESET line low while the microcontroller is trying the force the RESET line high, a series
resistor should be placed between the output of the TLV803 and the RESET pin of the microcontroller to protect
against excessive current flow. 图 8-3 shows the connection of the TLV803 to a microcontroller using a series
resistor to drive a bidirectional RESET line.
3.3 V
VCC
Microprocessor
VDD
100 kW
47 kW
TLV803S
RESET
RST
GND
图8-3. Connection To Bidirectional Reset Pin
8.4 Device Functional Modes
8.4.1 Normal Operation (VDD > Power-Up Reset Voltage)
When the voltage on VDD is greater than 1.1 V, the RESET signal asserts when VDD is less than VIT– and
deasserts when VDD is greater thanVIT–
.
8.4.2 Power On Reset (VDD < Power-Up Reset Voltage)
When the voltage on VDD is lower than the required voltage to internally pull the asserted output to GND
(power-up reset voltage), both outputs are in a high-impedance state.
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English Data Sheet: SBVS157
TLV803, TLV853, TLV863
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9 Application and Implementation
备注
以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。
9.1 Application Information
9.1.1 Monitoring Multiple Supplies
Because the TLV803 has an open-drain output, multiple TLV803 outputs can be directly tied together to form a
logical OR-ing function for the RESET line. Only one pull-up resistor is required for this configuration. 图 9-1
shows two TLV803s connected together to provide monitoring of a 3.3-V power rail and a 5.0-V power rail. A
reset is generated if either power rail falls below the threshold voltage of its corresponding TLV803.
5.0 V
3.3 V
0.1 mF
VDD
VIO
VCORE
100 kW
Microprocessor
RST
TLV803M
RESET
GND
3.3 V
0.1 mF
VDD
TLV803S
RESET
GND
图9-1. Multiple Voltage Rail Monitoring
9.1.2 Output Level Shifting
The RESET output of the TLV803 can be pulled to a maximum voltage of 6 V and can be pulled higher in voltage
than VDD. It is useful to provide level shifting of the output for cases where the monitored voltage is less than the
useful logic levels of the load. 图9-2 shows the TLV803Z used to monitor a 2.5-V power rail, with a logic RESET
input to a microprocessor that is connected to 5.0 V and has 5.0-V logic levels.
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2.5 V
5.0 V
0.1 mF
VDD
10 kW
Microprocessor
RST
TLV803Z
RESET
GND
图9-2. Output Voltage Level Shifting
9.2 Typical Application
图9-3 shows TLV803S being used to monitor the supply rail for a DSP, FPGA, or ASIC.
3.3-V LDO
3.3 V
OUT
5 V
IN
GND
VDD
DSP/FPGA/ASIC
VDD
TLV803S
RESET
RESET
GND
GND
图9-3. Typical Application
9.2.1 Design Requirements
This design calls for a 3.3-V rail to be monitored. The design resets if the supply rail falls below 2.93 V. The
output must satisfy 3.3-V CMOS logic.
9.2.2 Detailed Design Procedure
Select the TLV803S to satisfy the voltage threshold requirement.
Place a pullup resistor on RESET to VDD in order to satisfy the output logic requirement.
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English Data Sheet: SBVS157
TLV803, TLV853, TLV863
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9.2.3 Application Curves
1.2
+125°C
+85°C
+25°C
0°C
1
0.8
0.6
0.4
0.2
-40°C
VDD = 2.5 V
4 5
0
0
1
2
3
IOL (mA)
图9-4. Low-Level Output Voltage vs Low-Level Output Current
10 Power Supply Recommendations
These devices are designed to operate from an input voltage supply range between 1.1 V and 6 V.
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11 Layout
11.1 Layout Guidelines
Place the CIN decoupling capacitor close to the device.
11.2 Layout Example
RPU
VDD
RESET
TLV803
CIN
GND Plane
图11-1. Layout Example (DBZ Package)
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12 Device and Documentation Support
12.1 Device Support
12.1.1 Development Support
12.1.1.1 Evaluation Modules
An evaluation module (EVM) is available to assist in the initial circuit performance evaluation using the TLV803.
The TLV803SEVM-019 evaluation module (and related user guide) can be requested at the Texas Instruments
website through the product folders or purchased directly from the TI eStore.
12.1.1.2 Spice Models
Computer simulation of circuit performance using SPICE is often useful when analyzing the performance of
analog circuits and systems. SPICE models for the TLV803, TLV853, and TLV863 are available through the
respective device product folders under Tools & Software.
12.2 Documentation Support
12.2.1 Related Documentation
• TLV803SEVM-019 User's Guide. Literature number SLVU461.
12.3 Related Links
表 12-1 lists quick access links. Categories include technical documents, support and community resources,
tools and software, and quick access to sample or buy.
表12-1. Related Links
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TLV803
TLV853
TLV863
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
12.4 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SBVS157
14
Submit Document Feedback
Product Folder Links: TLV803 TLV853 TLV863
TLV803, TLV853, TLV863
ZHCS187E –APRIL 2011 –REVISED DECEMBER 2020
www.ti.com.cn
12.5 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
12.6 静电放电警告
静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理
和安装程序，可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参
数更改都可能会导致器件与其发布的规格不相符。
12.7 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2023 Texas Instruments Incorporated
Submit Document Feedback
15
Product Folder Links: TLV803 TLV853 TLV863
English Data Sheet: SBVS157
PACKAGE OPTION ADDENDUM
www.ti.com
28-Apr-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TLV803MDBZR
TLV803MDBZT
TLV803RDBZR
ACTIVE
ACTIVE
ACTIVE
SOT-23
SOT-23
SOT-23
DBZ
DBZ
DBZ
3
3
3
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
NIPDAUAG | SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
-40 to 125
VOUQ
Samples
Samples
Samples
NIPDAUAG | SN
VOUQ
VOSQ
NIPDAU | SN
| NIPDAUAG
TLV803RDBZT
TLV803SDBZR
ACTIVE
ACTIVE
SOT-23
SOT-23
DBZ
DBZ
3
3
NIPDAUAG | SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
VOSQ
VOTQ
Samples
Samples
NIPDAU | SN
| NIPDAUAG
TLV803SDBZT
TLV803ZDBZR
ACTIVE
ACTIVE
SOT-23
SOT-23
DBZ
DBZ
3
3
NIPDAUAG | SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
VOTQ
VORQ
Samples
Samples
NIPDAU | SN
| NIPDAUAG
TLV803ZDBZT
TLV853MDBZR
TLV853MDBZT
TLV863MDBZR
TLV863MDBZT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
DBZ
DBZ
DBZ
DBZ
DBZ
3
3
3
3
3
NIPDAUAG | SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
VORQ
ZGM4
ZGM4
VTWM
VTWM
Samples
Samples
Samples
Samples
Samples
NIPDAU | SN
NIPDAU | SN
NIPDAUAG | SN
NIPDAUAG | SN
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
28-Apr-2023
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Jul-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TLV803MDBZR
TLV803MDBZR
TLV803MDBZT
TLV803RDBZR
TLV803RDBZT
TLV803RDBZT
TLV803SDBZR
TLV803SDBZT
TLV803SDBZT
TLV803ZDBZR
TLV803ZDBZR
TLV803ZDBZR
TLV803ZDBZT
TLV853MDBZR
TLV853MDBZR
TLV853MDBZT
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
DBZ
DBZ
DBZ
DBZ
DBZ
DBZ
DBZ
DBZ
DBZ
DBZ
DBZ
DBZ
DBZ
DBZ
DBZ
DBZ
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3000
3000
250
179.0
178.0
179.0
180.0
179.0
178.0
180.0
178.0
179.0
180.0
179.0
178.0
179.0
179.0
178.0
179.0
8.4
9.0
8.4
8.4
8.4
9.0
8.4
9.0
8.4
8.4
8.4
9.0
8.4
8.4
9.0
8.4
3.15
3.15
3.15
2.9
2.95
2.77
2.95
3.35
2.95
2.77
3.35
2.77
2.95
3.35
2.95
2.77
2.95
2.95
2.77
2.95
1.22
1.22
1.22
1.35
1.22
1.22
1.35
1.22
1.22
1.35
1.22
1.22
1.22
1.22
1.22
1.22
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
Q3
Q3
Q3
Q3
Q3
Q3
Q3
Q3
Q3
Q3
Q3
Q3
Q3
Q3
Q3
Q3
3000
250
3.15
3.15
2.9
250
3000
250
3.15
3.15
2.9
250
3000
3000
3000
250
3.15
3.15
3.15
3.15
3.15
3.15
3000
3000
250
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Jul-2023
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TLV863MDBZR
TLV863MDBZR
TLV863MDBZT
SOT-23
SOT-23
SOT-23
DBZ
DBZ
DBZ
3
3
3
3000
3000
250
178.0
179.0
179.0
9.0
8.4
8.4
3.15
3.15
3.15
2.77
2.95
2.95
1.22
1.22
1.22
4.0
4.0
4.0
8.0
8.0
8.0
Q3
Q3
Q3
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Jul-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TLV803MDBZR
TLV803MDBZR
TLV803MDBZT
TLV803RDBZR
TLV803RDBZT
TLV803RDBZT
TLV803SDBZR
TLV803SDBZT
TLV803SDBZT
TLV803ZDBZR
TLV803ZDBZR
TLV803ZDBZR
TLV803ZDBZT
TLV853MDBZR
TLV853MDBZR
TLV853MDBZT
TLV863MDBZR
TLV863MDBZR
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
DBZ
DBZ
DBZ
DBZ
DBZ
DBZ
DBZ
DBZ
DBZ
DBZ
DBZ
DBZ
DBZ
DBZ
DBZ
DBZ
DBZ
DBZ
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3000
3000
250
200.0
180.0
200.0
210.0
200.0
180.0
210.0
180.0
200.0
210.0
200.0
180.0
203.0
200.0
180.0
200.0
180.0
200.0
183.0
180.0
183.0
185.0
183.0
180.0
185.0
180.0
183.0
185.0
183.0
180.0
203.0
183.0
180.0
183.0
180.0
183.0
25.0
18.0
25.0
35.0
25.0
18.0
35.0
18.0
25.0
35.0
25.0
18.0
35.0
25.0
18.0
25.0
18.0
25.0
3000
250
250
3000
250
250
3000
3000
3000
250
3000
3000
250
3000
3000
Pack Materials-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Jul-2023
Device
TLV863MDBZT
Package Type Package Drawing Pins
SOT-23 DBZ
SPQ
Length (mm) Width (mm) Height (mm)
200.0 183.0 25.0
3
250
Pack Materials-Page 4
PACKAGE OUTLINE
DBZ0003A
SOT-23 - 1.12 mm max height
S
C
A
L
E
4
.
0
0
0
SMALL OUTLINE TRANSISTOR
C
2.64
2.10
1.12 MAX
1.4
1.2
B
A
0.1 C
PIN 1
INDEX AREA
1
0.95
(0.125)
3.04
2.80
1.9
3
(0.15)
NOTE 4
2
0.5
0.3
3X
0.10
0.01
(0.95)
TYP
0.2
C A B
0.25
GAGE PLANE
0.20
0.08
TYP
0.6
0.2
TYP
SEATING PLANE
0 -8 TYP
4214838/D 03/2023
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Reference JEDEC registration TO-236, except minimum foot length.
4. Support pin may differ or may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
DBZ0003A
SOT-23 - 1.12 mm max height
SMALL OUTLINE TRANSISTOR
PKG
3X (1.3)
1
3X (0.6)
SYMM
3
2X (0.95)
2
(R0.05) TYP
(2.1)
LAND PATTERN EXAMPLE
SCALE:15X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214838/D 03/2023
NOTES: (continued)
4. Publication IPC-7351 may have alternate designs.
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBZ0003A
SOT-23 - 1.12 mm max height
SMALL OUTLINE TRANSISTOR
PKG
3X (1.3)
1
3X (0.6)
SYMM
3
2X(0.95)
2
(R0.05) TYP
(2.1)
SOLDER PASTE EXAMPLE
BASED ON 0.125 THICK STENCIL
SCALE:15X
4214838/D 03/2023
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.
www.ti.com
重要声明和免责声明
TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，
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保。
这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。
这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。
您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成
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TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改
TI 针对 TI 产品发布的适用的担保或担保免责声明。
TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE
邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2023，德州仪器 (TI) 公司
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