TLV9001_V03 [TI]
TLV900x Low-Power, RRIO, 1-MHz Operational Amplifier for Cost-Sensitive Systems;型号: | TLV9001_V03 |
厂家: | TEXAS INSTRUMENTS |
描述: | TLV900x Low-Power, RRIO, 1-MHz Operational Amplifier for Cost-Sensitive Systems |
文件: | 总94页 (文件大小:6330K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
TLV9001, TLV9002, TLV9004
SBOS833R – OCTOBER 2017 – REVISED NOVEMBER 2021
TLV900x Low-Power, RRIO, 1-MHz Operational Amplifier for Cost-Sensitive Systems
The TLV900x devices include a shutdown mode
(TLV9001S, TLV9002S, and TLV9004S) that allow the
1 Features
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Scalable CMOS amplifier for low-cost applications
Rail-to-rail input and output
Low input offset voltage: ±0.4 mV
Unity-gain bandwidth: 1 MHz
Low broadband noise: 27 nV/√Hz
Low input bias current: 5 pA
Low quiescent current: 60 µA/Ch
Unity-gain stable
amplifiers to switch off into standby mode with typical
current consumption less than 1 µA.
Micro-size packages, such as SOT-553 and WSON,
are offered for all channel variants (single, dual, and
quad), along with industry-standard packages such as
SOIC, MSOP, SOT-23, and TSSOP packages.
Device Information
PART NUMBER(1)
PACKAGE
BODY SIZE (NOM)
1.60 mm × 2.90 mm
1.25 mm × 2.00 mm
1.65 mm × 1.20 mm
0.80 mm × 0.80 mm
1.60 mm × 2.90 mm
1.25 mm × 2.00 mm
3.91 mm × 4.90 mm
2.00 mm × 2.00 mm
3.00 mm × 3.00 mm
1.60 mm × 2.90 mm
3.00 mm × 4.40 mm
3.00 mm × 3.00 mm
1.50 mm × 2.00 mm
1.00 mm × 1.00 mm
8.65 mm × 3.91 mm
4.20 mm × 2.00 mm
4.40 mm × 5.00 mm
3.00 mm × 3.00 mm
2.00 mm × 2.00 mm
3.00 mm × 3.00 mm
Internal RFI and EMI filter
Operational at supply voltages as low as 1.8 V
Easier to stabilize with higher capacitive load due
to resistive open-loop output impedance
Extended temperature range: –40°C to 125°C
SOT-23 (5)
SC70 (5)
TLV9001
SOT-553 (5)(2)
X2SON (5)
SOT-23 (6)
SC70 (6)
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2 Applications
TLV9001S
TLV9002
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Sensor signal conditioning
Power modules
Active filters
Low-side current sensing
Smoke detectors
Motion detectors
Wearable devices
Large and small appliances
EPOS
SOIC (8)
WSON (8)
VSSOP (8)
SOT-23 (8)
TSSOP (8)
VSSOP (10)
X2QFN (10)
DSBGA (9)
SOIC (14)
TLV9002S
Barcode scanners
Personal electronics
HVAC: heating, ventilating, and air conditioning
Motor control: AC induction
SOT-23 (14)
TSSOP (14)
WQFN (16)
X2QFN (14)
WQFN (16)
TLV9004
3 Description
The TLV900x family includes single (TLV9001), dual
(TLV9002), and quad-channel (TLV9004) low-voltage
(1.8 V to 5.5 V) operational amplifiers (op amps)
with rail-to-rail input and output swing capabilities.
These op amps provide a cost-effective solution
for space-constrained applications such as smoke
detectors, wearable electronics, and small appliances
where low-voltage operation and high capacitive-load
drive are required. The capacitive-load drive of the
TLV900x family is 500 pF, and the resistive open-
loop output impedance makes stabilization easier with
much higher capacitive loads. These op amps are
designed specifically for low-voltage operation (1.8 V
to 5.5 V) with performance specifications similar to the
TLV600x devices.
TLV9004S
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
(2) Package is for preview only.
The robust design of the TLV900x family simplifies
circuit design. The op amps feature unity-gain
stability, an integrated RFI and EMI rejection filter, and
no-phase reversal in overdrive conditions.
Single-Pole, Low-Pass Filter
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TLV9001, TLV9002, TLV9004
SBOS833R – OCTOBER 2017 – REVISED NOVEMBER 2021
www.ti.com
Table of Contents
1 Features............................................................................1
2 Applications.....................................................................1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Device Comparison Table...............................................6
6 Pin Configuration and Functions...................................7
7 Specifications................................................................ 14
7.1 Absolute Maximum Ratings...................................... 14
7.2 ESD Ratings............................................................. 14
7.3 Recommended Operating Conditions.......................14
7.4 Thermal Information: TLV9001................................. 15
7.5 Thermal Information: TLV9001S...............................15
7.6 Thermal Information: TLV9002................................. 15
7.7 Thermal Information: TLV9002S...............................16
7.8 Thermal Information: TLV9004................................. 16
7.9 Thermal Information: TLV9004S...............................16
7.10 Electrical Characteristics.........................................17
7.11 Typical Characteristics............................................ 19
8 Detailed Description......................................................25
8.1 Overview...................................................................25
8.2 Functional Block Diagram.........................................25
8.3 Feature Description...................................................26
8.4 Overload Recovery................................................... 27
8.5 Shutdown..................................................................27
8.6 Device Functional Modes..........................................27
9 Application and Implementation..................................28
9.1 Application Information............................................. 28
9.2 Typical Application.................................................... 28
10 Power Supply Recommendations..............................34
10.1 Input and ESD Protection....................................... 34
11 Layout...........................................................................35
11.1 Layout Guidelines................................................... 35
11.2 Layout Example...................................................... 35
12 Device and Documentation Support..........................36
12.1 Documentation Support.......................................... 36
12.2 Receiving Notification of Documentation Updates..36
12.3 Support Resources................................................. 36
12.4 Trademarks.............................................................36
12.5 Electrostatic Discharge Caution..............................36
12.6 Glossary..................................................................36
13 Mechanical, Packaging, and Orderable
Information.................................................................... 37
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision Q (June 2021) to Revision R (November 2021)
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Added SOT-23 (14) package to Device Information table.................................................................................. 1
Added SOT-23 DYY package to Device Comparison Table ..............................................................................6
Added SOT-23 (14) package to Pin Configuration and Functions section ........................................................ 7
Added DYY (SOT-23) package thermal information to the Thermal Information: TLV9004 table.................... 16
Changes from Revision P (April 2021) to Revision Q (June 2021)
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Changed supply voltage (V+) – (V–) MAX from 6 V to 7 V in the Absolute Maximum Ratings table............... 14
Changes from Revision O (April 2020) to Revision P (April 2021)
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Updated the numbering format for tables, figures, and cross-references throughout the document..................1
Added 9-pin DSBGA package to Device Information table................................................................................ 1
Added 9-pin DSBGA package to Device Comparison Table ............................................................................. 6
Added TLV9002S 9-pin DSBGA package to Pin Configuration and Functions section......................................7
Added TLV9002S 9-pin DSBGA package to Thermal Information: TLV9002S ............................................... 16
Deleted the Related Links section from the Device and Documentation Support section................................36
Changes from Revision N (January 2020) to Revision O (April 2020)
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Deleted PREVIEW designation on TLV9001S ...................................................................................................1
Deleted TLV9001SIDCK (6-pin SC70) package preview note ...........................................................................7
Added DCK (SC70) data to the Thermal Information: TLV9001S table ...........................................................15
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SBOS833R – OCTOBER 2017 – REVISED NOVEMBER 2021
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Changes from Revision M (September 2019) to Revision N (January 2020)
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Added 6-pin SC70 package to Device Information table....................................................................................1
Added 6-pin SC70 package to Device Comparison Table .................................................................................6
Added TLV9001SIDCK (6-Pin SC70) package pinout........................................................................................7
Added TLV9001S 6-pin SC70 package to Pin Configuration and Functions section......................................... 7
Added 6-pin SC70 pinout to Pin Functions: TLV9001S .....................................................................................7
Added TLV9001S 6-pin SC70 package to Thermal Information: TLV9001S table........................................... 15
Changes from Revision L (May 2019) to Revision M (September 2019)
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Deleted preview notations for SOT-23-8 (DDF) package................................................................................... 6
Added link to Shutdown section in all SHDN pin function rows..........................................................................7
Added EMI Rejection section to the Feature Description section.....................................................................26
Changed the Shutdown section to add more clarity regarding internal pull-up resistor....................................27
Changes from Revision K (March 2019) to Revision L (May 2019)
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Added SOT-23 (8) information to Device Information table................................................................................1
Added SOT-23 DDF package to Device Comparison Table ..............................................................................6
Added SOT-23 (DDF) to Pin Configuration and Functions section.....................................................................7
Added DDF (SOT-23) Thermal Information: TLV9002 table.............................................................................15
Changes from Revision J (January 2019) to Revision K (March 2019)
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Changed TLV9002S ESD Ratings heading to include all TLV9002S packages...............................................14
Deleted preview notation from TLV9002SIRUG in Thermal Information table................................................. 16
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Changes from Revision I (November 2018) to Revision J (January 2019)
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Deleted preview notation for TLV9002SIRUGR..................................................................................................1
Changed TLV9004 WQFN(14) package designator to X2QFN(14) package designator................................... 1
Added RUG package to Device Comparison Table ...........................................................................................6
Added DGS package to Device Comparison Table ...........................................................................................6
Added shutdown devices to Device Comparison Table .....................................................................................6
Changed TLV9001 DRL package pinout drawing...............................................................................................7
Changed TLV9001 DRL package pin functions..................................................................................................7
Deleted package preview note from TLV9002SIRUGR (X2QFN) pinout drawing.............................................. 7
Added TLV9004IRUC Thermal Information......................................................................................................16
Changed legend of Closed-Loop Gain vs Frequency plot................................................................................19
Changes from Revision H (October 2018) to Revision I (November 2018)
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Added TLV9002SIDGS to ESD Ratings table...................................................................................................14
Changes from Revision G (September 2018) to Revision H (October 2018)
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Changed From: TLV9001 DCK Package To: TLV9001T DCK Package.............................................................7
Changes from Revision F (August 2018) to Revision G (September 2018)
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Added Device Comparison Table ...................................................................................................................... 6
Changed pin names for all devices and all packages.........................................................................................7
Changed pin names and I/O designation on some TLV9001 pins .....................................................................7
Changed the pin number for V+ in the SOIC, TSSOP column of the Pin Functions: TLV9004 table................. 7
Changes from Revision E (July 2018) to Revision F (August 2018)
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Added Scalabe CMOS Amplifier for Low-Cost Applications feature...................................................................1
Deleted PREVIEW designation on TLV9002 and TLV9004 devices with the TSSOP package. ....................... 1
Added TLV9001U DBV (SOT-23) pinout drawing to Pin Configuration and Functions section ......................... 7
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SBOS833R – OCTOBER 2017 – REVISED NOVEMBER 2021
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Added SOT-23 U Pinout to Pin Functions section .............................................................................................7
Changes from Revision D (June 2018) to Revision E (July 2018)
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Corrected typo in Description section ................................................................................................................1
Added TLV9001 5-pin X2SON package to Device Information table ................................................................ 1
Added TLV9001S 6-pin SOT-23 package to Device Information table...............................................................1
Added TLV9004 14-pin and 16-pin WQFN packages to Device Information table ............................................1
Added TLV9001 DPW (X2SON) pinout drawing to Pin Configuration and Functions section............................ 7
Added TLV9001S 6-pin SOT-23 package to Pin Configuration and Functions section......................................7
Added TLV9004 RTE pinout information to Pin Configuration and Functions section .......................................7
Added DPW (X2SON) and DRL (SOT-553) packages to Thermal Information: TLV9001 table.......................15
Added Thermal Information: TLV9001S table to Specifications section...........................................................15
Added RUG (X2QFN) package to Thermal Information: TLV9002 table..........................................................15
Added RTE (WQFN) and RUC (WQFN) packages to Thermal Information: TLV9004 table............................16
Changes from Revision C (May 2018) to Revision D (June 2018)
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Added shutdown text to Description section.......................................................................................................1
Added TLV9002S and TLV9004S devices to Device Information table..............................................................1
Added TLV9002S 10-pin X2QFN package to Device Information table............................................................. 1
Added TLV9002S DGS package pinout information to Pin Configurations and Functions section.................... 7
Added Thermal Information: TLV9001 table to Specifications section............................................................. 15
Added Thermal Information: TLV9004 table to Specifications section............................................................. 16
Added shutdown section to Electrical Characteristics: VS (Total Supply Voltage) = (V+) – (V–) = 1.8 V to 5.5 V
table..................................................................................................................................................................17
Added Shutdown section..................................................................................................................................27
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Changes from Revision B (March 2018) to Revision C (May 2018)
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Added TLV9002 16-pin TSSOP package to Device Information table............................................................... 1
Added TLV9002 10-pin X2QFN package to Device Information table................................................................1
Added TLV9002S DGS package pinout drawing in Pin Configurations and Functions section..........................7
Added TLV9004 pinout diagram and pin configuration table to Pin Configuration and Functions section ........ 7
Added TLV9004S pinout diagram and pin configuration table to Pin Configuration and Functions section ......7
Changed TLV9002 D (SOIC) junction-to-ambient thermal resistance value from 147.4°C/W to 207.9°C/W... 15
Changed TLV9002 D (SOIC) junction-to-case (top) thermal resistance from 94.3°C/W to 92.8°C/W..............15
Changed TLV9002 D (SOIC) junction-to-board thermal resistance from 89.5°C/W to 129.7°C/W...................15
Changed TLV9002 D (SOIC) junction-to-top characterization parameter from 47.3°C/W to 26°C/W.............. 15
Changed TLV9002 D (SOIC) junction-to-board characterization parameter from 89°C/W to 127.9°C/W........ 15
Added DGK (VSSOP) thermal information to Thermal Information: TLV9002 table ........................................15
Added TLV9002 PW (TSSOP) thermal information to Thermal Information: TLV9002 table........................... 15
Added PW (TSSOP) thermal information to Thermal Information: TLV9002 table ..........................................16
Changes from Revision A (December 2017) to Revision B (March 2018)
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Added package preview notes to TLV9001 packages, TLV9004 packages, and TLV9002 8-pin VSSOP
package in Device Information table ..................................................................................................................1
Added package preview notes to TLV9001, TLV9004 and TLV9002 VSSOP package pinout drawings in Pin
Configuration and Functions section ................................................................................................................. 7
Deleted package preview note from TLV9002 DSG (WSON) pinout drawing in Pin Configurations and
Functions section................................................................................................................................................7
Deleted package preview note from TLV9002 RUG (X2QFN) pinout drawing in Pin Configurations and
Functions section................................................................................................................................................7
Added DSG (WSON) package thermal information to the Thermal Information: TLV9002 table..................... 15
Deleted package preview note from DSG (WSON) package in Thermal Information: TLV9002 table.............15
Added D (SOIC) package thermal information to the Thermal Information: TLV9004 table.............................16
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Changes from Revision * (October 2017) to Revision A (December 2017)
Page
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Changed device status from Advance Information to Production Data/Mixed Status........................................ 1
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5 Device Comparison Table
PACKAGE LEADS
NO.
DEVICE
OF
CH.
SC70
DCK
SOIC
D
SOT-23 SOT-23 SOT-553 TSSOP VSSOP SOT-23 WQFN
WSON
DSG
X2QFN
RUC
X2SON
DPW
X2QFN VSSOP DSBGA
DBV
5
DYY
—
DRL
5
PW
—
—
8
DGK
—
DDF
—
—
8
RTE
—
RUG
DGS
YCK
—
—
—
9
TLV9001
TLV9001S
TLV9002
TLV9002S
TLV9004
TLV9004S
5
—
—
8
—
—
8
—
—
—
—
14
—
5
—
—
1
2
4
6
6
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
8
—
—
—
—
14
—
—
—
14
—
—
—
—
—
—
—
—
—
10
—
10
—
14
—
—
16
16
—
—
—
—
—
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6 Pin Configuration and Functions
OUT
Vœ
1
2
3
5
V+
IN+
Vœ
1
2
3
5
V+
IN+
4
INœ
INœ
4
OUT
Not to scale
Not to scale
Figure 6-1. TLV9001 DBV, TLV9001T DCK Package
Figure 6-2. TLV9001 DCK Package, TLV9001 DRL
Package, TLV9001U DBV Package
5-Pin SC70, SOT-553, SOT-23
Top View
5-Pin SOT-23, SC70
Top View
OUT
1
5
V+
3
Vœ
INœ
2
4
IN+
Not to scale
Figure 6-3. TLV9001 DPW Package
5-Pin X2SON
Top View
Table 6-1. Pin Functions: TLV9001
PIN
SC70,
SOT-23(U),
SOT-553
I/O
DESCRIPTION
SOT-23,
SC70(T)
NAME
IN–
X2SON
4
3
1
2
5
3
1
4
2
5
2
4
1
3
5
I
I
Inverting input
Noninverting input
Output
IN+
OUT
V–
O
I or — Negative (low) supply or ground (for single-supply operation)
Positive (high) supply
V+
I
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IN+
Vœ
1
2
3
6
5
4
V+
OUT
Vœ
1
2
3
6
5
4
V+
SHDN
OUT
SHDN
INœ
INœ
IN+
Not to scale
Not to scale
Figure 6-5. TLV9001S DCK Package
6-Pin SC70
Figure 6-4. TLV9001S DBV Package
6-Pin SOT-23
Top View
Top View
Table 6-2. Pin Functions: TLV9001S
PIN
I/O
DESCRIPTION
NAME
IN–
SOT-23
SC70
4
3
1
3
1
4
I
I
Inverting input
Noninverting input
Output
IN+
OUT
O
Shutdown: low = amp disabled, high = amp enabled. See Section 8.5 for more
information.
SHDN
5
5
I
V–
V+
2
6
2
6
I or —
I
Negative (low) supply or ground (for single-supply operation)
Positive (high) supply
OUT1
IN1œ
IN1+
Vœ
1
2
3
4
8
7
6
5
V+
OUT1
IN1œ
IN1+
Vœ
1
2
3
4
8
7
6
5
V+
OUT2
OUT2
IN2œ
IN2+
Thermal
Pad
IN2œ
IN2+
Not to scale
Not to scale
Figure 6-6. TLV9002 D, DGK, PW, DDF Package
8-Pin SOIC, VSSOP, TSSOP, SOT-23
Top View
A. Connect thermal pad to V–.
Figure 6-7. TLV9002 DSG Package
8-Pin WSON With Exposed Thermal Pad
Top View
Table 6-3. Pin Functions: TLV9002
PIN
I/O
DESCRIPTION
NAME
IN1–
NO.
2
I
I
Inverting input, channel 1
Noninverting input, channel 1
Inverting input, channel 2
Noninverting input, channel 2
Output, channel 1
IN1+
IN2–
IN2+
OUT1
OUT2
V–
3
6
I
5
I
1
O
O
7
Output, channel 2
4
I or — Negative (low) supply or ground (for single-supply operation)
V+
8
I
Positive (high) supply
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OUT1
IN1œ
1
2
3
4
5
10
9
V+
OUT2
IN2œ
IN2+
SHDN2
Vœ
SHDN1
SHDN2
IN2+
1
2
3
4
9
8
7
6
IN1œ
OUT1
V+
IN1+
8
Vœ
7
SHDN1
6
Not to scale
Figure 6-8. TLV9002S DGS Package
10-Pin VSSOP
OUT2
Top View
Not to scale
Figure 6-9. TLV9002S RUG Package
10-Pin X2QFN
Top View
1
2
3
C
B
A
OUT1
IN1–
IN1+
V+
OUT2
SHDN
IN2–
V–
IN2+
Not to scale
Figure 6-10. TLV9002S YCK Package
9-Pin DSBGA (WCSP)
Bottom View
Table 6-4. Pin Functions: TLV9002S
PIN
VSSOP
I/O
DESCRIPTION
DSBGA
(WCSP)
NAME
IN1–
X2QFN
2
3
8
7
1
9
9
10
5
B1
A1
B3
A3
C1
C3
I
I
Inverting input, channel 1
Noninverting input, channel 1
Inverting input, channel 2
Noninverting input, channel 2
Output, channel 1
IN1+
IN2–
I
IN2+
OUT1
OUT2
4
I
8
O
O
6
Output, channel 2
Shutdown: low = amp disabled, high = amp enabled, channel 1. See
Section 8.5 for more information.
SHDN1
5
2
—
I
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Table 6-4. Pin Functions: TLV9002S (continued)
PIN
VSSOP
I/O
DESCRIPTION
DSBGA
(WCSP)
NAME
X2QFN
Shutdown: low = amp disabled, high = amp enabled, channel 1. See
Section 8.5 for more information.
SHDN2
6
3
—
I
SHDN
V–
—
4
—
1
B2
A2
C2
Shutdown: low = both amplifiers disabled, high = both amplifiers enabled
Negative (low) supply or ground (for single-supply operation)
Positive (high) supply
I or —
I
V+
10
7
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OUT1
IN1œ
IN1+
V+
1
2
3
4
5
6
7
14
13
12
11
10
9
OUT4
IN4œ
IN4+
Vœ
IN1œ
IN1+
V+
1
2
3
4
5
12
11
10
9
IN4œ
IN4+
Vœ
IN2+
IN2œ
OUT2
IN3+
IN3œ
OUT3
8
IN2+
IN2œ
IN3+
IN3œ
Not to scale
8
Figure 6-11. TLV9004 D, DYY, PW Package
14-Pin SOIC, SOT-23 (14), TSSOP
Top View
Not to scale
Figure 6-12. TLV9004 RUC Package
14-Pin X2QFN
Top View
IN1+
V+
1
2
3
4
12
11
10
9
IN4+
Vœ
Thermal
Pad
IN2+
IN2œ
IN3+
IN3œ
Not to scale
A. Connect thermal pad to V–.
Figure 6-13. TLV9004 RTE Package
16-Pin WQFN With Exposed Thermal Pad
Top View
Table 6-5. Pin Functions: TLV9004
PIN
SOIC,
SOT-23 (14),
TSSOP
I/O
DESCRIPTION
NAME
IN1–
WQFN
X2QFN
2
3
6
5
16
1
1
2
5
4
I
I
I
I
Inverting input, channel 1
Noninverting input, channel 1
Inverting input, channel 2
Noninverting input, channel 2
IN1+
IN2–
IN2+
4
3
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Table 6-5. Pin Functions: TLV9004 (continued)
PIN
SOIC,
SOT-23 (14),
TSSOP
I/O
DESCRIPTION
NAME
IN3–
WQFN
X2QFN
9
10
13
12
—
1
9
10
13
12
6, 7
15
5
8
9
I
I
Inverting input, channel 3
IN3+
IN4–
IN4+
NC
Noninverting input, channel 3
Inverting input, channel 4
Noninverting input, channel 4
No internal connection
Output, channel 1
12
11
—
14
6
I
I
—
O
O
O
O
OUT1
OUT2
OUT3
OUT4
V–
7
Output, channel 2
8
8
7
Output, channel 3
14
11
4
14
11
2
13
10
3
Output, channel 4
I or — Negative (low) supply or ground (for single-supply operation)
Positive (high) supply
V+
I
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IN1+
V+
1
2
3
4
12
11
10
9
IN4+
Vœ
Thermal
Pad
IN2+
IN2œ
IN3+
IN3œ
Not to scale
A. Connect thermal pad to V–.
Figure 6-14. TLV9004S RTE Package
16-Pin WQFN With Exposed Thermal Pad
Top View
Table 6-6. Pin Functions: TLV9004S
PIN
I/O
DESCRIPTION
NAME
IN1+
NO.
1
I
I
I
I
I
I
I
I
Noninverting input
Inverting input
IN1–
IN2+
IN2–
IN3+
IN3–
IN4+
IN4–
16
3
Noninverting input
Inverting input
4
10
9
Noninverting input
Inverting input
12
13
Noninverting input
Inverting input
Shutdown: low = amp disabled, high = amp enabled, channel 1 and 2. See Section 8.5 for
more information.
SHDN12
SHDN34
6
7
I
I
Shutdown: low = amp disabled, high = amp enabled, channel 3 and 4. See Section 8.5 for
more information.
OUT1
OUT2
OUT3
OUT4
V–
15
5
O
Output
O
Output
8
O
Output
14
11
2
O
I or —
I
Output
Negative (low) supply or ground (for single-supply operation)
Positive (high) supply
V+
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7 Specifications
7.1 Absolute Maximum Ratings
over operating temperature range (unless otherwise noted)(1)
MIN
(V–) – 0.5
–10
MAX
UNIT
V
Supply voltage (V+) – (V–)
7
Common-mode
Differential
(V+) + 0.5
V
Voltage(2)
Current(2)
Signal input pins
(V+) – (V–) + 0.2
V
10
mA
Output short-circuit(3)
Operating, TA
Junction, TJ
Continuous
150
–55
°C
°C
°C
150
Storage, Tstg
–65
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) Input pins are diode-clamped to the power-supply rails. Input signals that may swing more than 0.5 V beyond the supply rails must be
current limited to 10 mA or less.
(3) Short-circuit to ground, one amplifier per package.
7.2 ESD Ratings
TLV9002S PACKAGE
VALUE
±1500
±1500
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
ALL OTHER PACKAGES
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±2000
±1000
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating temperature range (unless otherwise noted)
MIN
1.8
MAX
UNIT
V
VS
TA
Supply voltage
5.5
Specified temperature
–40
125
°C
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7.4 Thermal Information: TLV9001
TLV9001
THERMAL METRIC(1)
DBV (SOT-23)
5 PINS
232.9
DCK (SC70)
DPW (X2SON) DRL (SOT-553)(2) UNIT
5 PINS
239.6
148.5
82.3
5 PINS
470.0
211.9
334.8
29.8
5 PINS
TBD
TBD
TBD
TBD
TBD
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top) Junction-to-case (top) thermal resistance
153.8
RθJB
ψJT
Junction-to-board thermal resistance
100.9
Junction-to-top characterization parameter
Junction-to-board characterization parameter
77.2
54.5
ψJB
100.4
81.8
333.2
(1) For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics.
(2) This package option for TLV9001 is preview only.
7.5 Thermal Information: TLV9001S
TLV9001S
THERMAL METRIC(1)
DBV (SOT-23)
6 PINS
232.9
DCK (SC70)
6 PINS
215.6
UNIT
RθJA
RθJC(top)
RθJB
ψJT
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
153.8
146.4
100.9
72.0
Junction-to-top characterization parameter
Junction-to-board characterization parameter
77.2
55.0
ψJB
100.4
71.7
(1) For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics.
7.6 Thermal Information: TLV9002
TLV9002
D
DGK
(VSSOP)
DGS
(VSSOP)
DSG
(WSON)
PW
(TSSOP)
DDF
(SOT-23)
THERMAL METRIC(1)
UNIT
(SOIC)
8 PINS
8 PINS
10 PINS
8 PINS
8 PINS
8 PINS
Junction-to-ambient
thermal resistance
RθJA
207.9
201.2
169.5
103.2
200.7
183.7
°C/W
°C/W
°C/W
°C/W
°C/W
Junction-to-case (top)
thermal resistance
RθJC(top)
RθJB
ψJT
92.8
129.7
26
85.7
122.9
21.2
84.1
113
120.1
68.8
14.7
68.5
95.4
128.6
27.2
112.5
98.2
18.8
97.6
Junction-to-board thermal
resistance
Junction-to-top
characterization parameter
15.8
111.6
Junction-to-board
characterization parameter
ψJB
127.9
121.4
127.2
(1) For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics.
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7.7 Thermal Information: TLV9002S
TLV9002S
RUG (X2QFN)
10 PINS
194.2
THERMAL METRIC(1)
DGS (VSSOP)
10 PINS
169.5
YCK (DSBGA)
9 PINS
101.2
0.9
UNIT
RθJA
RθJC(top)
RθJB
ψJT
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
84.1
90.3
113
122.2
33.8
Junction-to-top characterization parameter
Junction-to-board characterization parameter
15.8
3.5
0.5
ψJB
111.6
118.8
33.8
(1) For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics.
7.8 Thermal Information: TLV9004
TLV9004
THERMAL METRIC(1)
D (SOIC)
14 PINS
DYY (SOT-23)
14 PINS
PW (TSSOP)
14 PINS
RTE (WQFN)
16 PINS
RUC (X2QFN) UNIT
14 PINS
Junction-to-ambient thermal
resistance
RθJA
RθJC(top)
RθJB
ψJT
102.1
56.8
58.5
20.5
58.1
154.3
86.8
67.9
10.1
67.5
148.3
68.1
92.7
16.9
91.8
66.4
69.3
41.7
5.7
205.5
72.5
°C/W
°C/W
°C/W
°C/W
°C/W
Junction-to-case (top) thermal
resistance
Junction-to-board thermal
resistance
150.2
3.0
Junction-to-top characterization
parameter
Junction-to-board
characterization parameter
ψJB
41.5
149.6
(1) For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics.
7.9 Thermal Information: TLV9004S
TLV9004S
THERMAL METRIC(1)
RTE (WQFN)
16 PINS
66.4
UNIT
RθJA
RθJC(top)
RθJB
ψJT
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
69.3
41.7
Junction-to-top characterization parameter
Junction-to-board characterization parameter
5.7
ψJB
41.5
(1) For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics.
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7.10 Electrical Characteristics
For VS = (V+) – (V–) = 1.8 V to 5.5 V (±0.9 V to ±2.75 V), TA = 25°C, RL = 10 kΩ connected to VS / 2, and VCM = VOUT
=
VS / 2 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OFFSET VOLTAGE
VS = 5 V
±0.4
±1.6
±2
VOS
Input offset voltage
mV
VS = 5 V, TA = –40°C to 125°C
TA = –40°C to 125°C
dVOS/dT VOS vs temperature
±0.6
105
µV/°C
dB
PSRR
Power-supply rejection ratio
VS = 1.8 to 5.5 V, VCM = (V–)
80
INPUT VOLTAGE RANGE
VCM
Common-mode voltage range
No phase reversal, rail-to-rail input
(V–) – 0.1
(V+) + 0.1
V
VS = 1.8 V, (V–) – 0.1 V < VCM < (V+) – 1.4 V,
TA = –40°C to 125°C
86
95
77
68
VS = 5.5 V, (V–) – 0.1 V < VCM < (V+) – 1.4 V,
TA = –40°C to 125°C
CMRR
Common-mode rejection ratio
dB
VS = 5.5 V, (V–) – 0.1 V < VCM < (V+) + 0.1 V,
TA = –40°C to 125°C
63
VS = 1.8 V, (V–) – 0.1 V < VCM < (V+) + 0.1 V,
TA = –40°C to 125°C
INPUT BIAS CURRENT
IB
Input bias current
Input offset current
VS = 5 V
±5
±2
pA
pA
IOS
NOISE
Input voltage noise (peak-to-
peak)
En
ƒ = 0.1 Hz to 10 Hz, VS = 5 V
4.7
µVPP
ƒ = 1 kHz, VS = 5 V
ƒ = 10 kHz, VS = 5 V
ƒ = 1 kHz, VS = 5 V
30
27
23
en
in
Input voltage noise density
nV/√ Hz
fA/√ Hz
Input current noise density
INPUT CAPACITANCE
CID
CIC
Differential
1.5
5
pF
pF
Common-mode
OPEN-LOOP GAIN
VS = 5.5 V, (V–) + 0.05 V < VO < (V+) – 0.05 V,
RL = 10 kΩ
104
117
100
115
130
VS = 1.8 V, (V–) + 0.04 V < VO < (V+) – 0.04 V,
RL = 10 kΩ
AOL
Open-loop voltage gain
dB
VS = 1.8 V, (V–) + 0.1 V < VO < (V+) – 0.1 V,
RL = 2 kΩ
VS = 5.5 V, (V–) + 0.15 V < VO < (V+) – 0.15 V,
RL = 2 kΩ
FREQUENCY RESPONSE
GBW
φm
Gain-bandwidth product
VS = 5 V
1
78
MHz
°
Phase margin
Slew rate
VS = 5.5 V, G = 1
SR
VS = 5 V
2
V/µs
To 0.1%, VS = 5 V, 2-V step, G = +1, CL = 100 pF
To 0.01%, VS = 5 V, 2-V step, G = +1, CL = 100 pF
VS = 5 V, VIN × gain > VS
2.5
3
tS
Settling time
µs
µs
tOR
Overload recovery time
0.85
Total harmonic distortion +
noise
VS = 5.5 V, VCM = 2.5 V, VO = 1 VRMS, G = +1,
ƒ = 1 kHz, 80-kHz measurement BW
THD+N
OUTPUT
0.004%
VS = 5.5 V, RL = 10 kΩ
VS = 5.5 V, RL = 2 kΩ
VS = 5.5 V
10
35
20
55
Voltage output swing from
supply rails
VO
mV
ISC
ZO
Short-circuit current
±40
1200
mA
Ω
Open-loop output impedance
VS = 5 V, ƒ = 1 MHz
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7.10 Electrical Characteristics (continued)
For VS = (V+) – (V–) = 1.8 V to 5.5 V (±0.9 V to ±2.75 V), TA = 25°C, RL = 10 kΩ connected to VS / 2, and VCM = VOUT
VS / 2 (unless otherwise noted)
=
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER SUPPLY
VS
Specified voltage range
1.8 (±0.9)
5.5 (±2.75)
75
V
TLV9002, TLV9002S TLV9004,
TLV9004S
IO = 0 mA, VS = 5.5 V
IO = 0 mA, VS = 5.5 V
60
60
IQ
Quiescent current per amplifier
µA
TLV9001, TLV9001S
77
85
IO = 0 mA, VS = 5.5 V, TA = –40°C to 125°C
SHUTDOWN(1)
IQSD
Quiescent current per amplifier VS = 1.8 V to 5.5 V, all amplifiers disabled, SHDN = VS–
0.5
1.5
µA
Output impedance during
VS = 1.8 V to 5.5 V, amplifier disabled
shutdown
ZSHDN
10 || 2
GΩ || pF
High level voltage shutdown
VS = 1.8 V to 5.5 V
(V–) + 0.9
(V–) + 1.1
V
V
threshold (amplifier enabled)
Low level voltage shutdown
VS = 1.8 V to 5.5 V
(V–) + 0.2 V (V–) + 0.7 V
threshold (amplifier disabled)
Amplifier enable time (full
shutdown)
VS = 1.8 V to 5.5 V, full shutdown; G = 1,
VOUT = 0.9 × VS / 2, RL connected to V–
70
50
4
tON
µs
Amplifier enable time (partial
shutdown)
VS = 1.8 V to 5.5 V, partial shutdown; G = 1,
VOUT = 0.9 × VS / 2, RL connected to V–
VS = 1.8 V to 5.5 V, G = 1, VOUT = 0.1 × VS / 2,
RL connected to V–
tOFF
Amplifier disable time
µs
VS = 1.8 V to 5.5 V, V+ ≥ SHDN ≥ (V+) – 0.8 V
VS = 1.8 V to 5.5 V, V– ≤ SHDN ≤ V– + 0.8 V
40
SHDN pin input bias current
(per pin)
nA
150
(1) Specified by design and characterization; not production tested.
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7.11 Typical Characteristics
at TA = 25°C, V+ = 2.75 V, V– = –2.75 V, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise
noted)
40
35
30
25
20
15
10
5
25
20
15
10
5
0
0
0
0.2 0.4 0.6 0.8
1
1.2 1.4 1.6 1.8
2
-
1200 -900 -600 -300
0
300 600 900 1200 1500 1800
D001
D002
Offset Voltage Drift (μV/°C)
Offset Voltage (μV)
VS = 5 V, TA = –40°C to 125°C
VS = 5 V
Figure 7-2. Offset Voltage Drift Distribution Histogram
Figure 7-1. Offset Voltage Distribution Histogram
1000
2000
1500
1000
500
800
600
400
200
0
0
-200
-400
-600
-800
-1000
-500
-1000
-1500
-2000
-40
-20
0
20
40 60
Temperature (°C)
80
100 120 140
-4
-3
-2
-1
0
1
Common-Mode Voltage (V)
2
3
4
D003
D004
Figure 7-3. Input Offset Voltage vs Temperature
Figure 7-4. Offset Voltage vs Common-Mode
1000
6
4
IB-
IB+
IOS
800
600
2
400
0
200
0
-2
-4
-6
-8
-10
-200
-400
-600
-800
-1000
1.5
2
2.5
3
3.5
4
Supply Voltage (V)
4.5
5
5.5
6
-40
-20
0
20
40
60
80
100 120 140
D005
Temperature (èC)
D006
Figure 7-5. Offset Voltage vs Supply Voltage
Figure 7-6. IB and IOS vs Temperature
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7.11 Typical Characteristics (continued)
at TA = 25°C, V+ = 2.75 V, V– = –2.75 V, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise
noted)
3.5
3
160
140
120
100
80
IB-
IB+
IOS
2.5
2
1.5
1
0.5
0
60
-0.5
-1
40
-1.5
-2
20
VS = 5.5 V
VS = 1.8 V
-2.5
0
-3
-2
-1
0
1
Common-Mode Voltage (V)
2
3
-40
-20
0
20
40
60
80
100 120 140
Temperature (èC)
D007
D008
Figure 7-7. IB and IOS vs Common-Mode Voltage
Figure 7-8. Open-Loop Gain vs Temperature
100
80
60
40
20
0
120
100
80
60
40
20
0
160
140
120
100
80
60
40
Gain
Phase
20
-20
1k
0
10k
100k
Frequency (Hz)
1M
-3
-2
-1 0
Output Voltage (V)
1
2
3
D009
D010
CL = 10 pF
Figure 7-9. Open-Loop Gain and Phase vs Frequency
Figure 7-10. Open-Loop Gain vs Output Voltage
80
3
Gain = -1
Gain = 1
Gain = 100
Gain = 1000
Gain = 10
2.5
2
70
60
1.5
1
125°C
50
40
30
20
10
0
85°C
25°C
-40°C
0.5
0
-0.5
-1
85°C
25°C
-40°C
-1.5
-2
125°C
-10
-20
-2.5
-3
100
1k
10k 100k
Frequency (Hz)
1M
0
5
10
15
20
25
30
Output Current (mA)
35
40
45
50
D011
D012
CL = 10 pF
Figure 7-11. Closed-Loop Gain vs Frequency
Figure 7-12. Output Voltage vs Output Current (Claw)
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7.11 Typical Characteristics (continued)
at TA = 25°C, V+ = 2.75 V, V– = –2.75 V, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise
noted)
120
100
80
60
40
20
0
120
100
80
60
40
20
0
PSRR+
PSRR-
-40
-20
0
20
40
60
80
100 120 140
100
1k
10k
Frequency (Hz)
100k
1M
Temperature (èC)
D014
D013
VS = 1.8 V to 5.5 V
Figure 7-14. DC PSRR vs Temperature
Figure 7-13. PSRR vs Frequency
120
100
80
60
40
20
0
160
140
120
100
80
60
40
20
VS = 1.8 V
VS = 5.5 V
0
-40
-20
0
20
40
60
80
100 120 140
100
1k
10k
Frequency (Hz)
100k
1M
Temperature (èC)
D016
D015
VCM = (V–) – 0.1 V to (V+) – 1.4 V
Figure 7-16. DC CMRR vs Temperature
Figure 7-15. CMRR vs Frequency
120
100
80
60
40
20
0
Time (1 s/div)
10
100
1k
Frequency (Hz)
10k
100k
D017
D018
Figure 7-17. 0.1-Hz to 10-Hz Integrated Voltage Noise
Figure 7-18. Input Voltage Noise Spectral Density
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7.11 Typical Characteristics (continued)
at TA = 25°C, V+ = 2.75 V, V– = –2.75 V, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise
noted)
-50
0
G = +1, RL = 2 kW
G = +1, RL = 10 kW
G = -1, RL = 2 kW
G = -1, RL = 10 kW
-60
-20
-70
-40
-80
-60
-90
-80
RL = 2K
RL = 10K
-100
-100
100
1k
Frequency (Hz)
10k
0.001
0.01
0.1
Amplitude (VRMS)
1
2
D019
D020
VS = 5.5 V
BW = 80 kHz
VCM = 2.5 V
G = 1
VS = 5.5 V
G = 1
VCM = 2.5 V
ƒ = 1 kHz
VOUT = 0.5 VRMS
BW = 80 kHz
Figure 7-19. THD + N vs Frequency
Figure 7-20. THD + N vs Amplitude
70
60
50
40
30
20
10
0
70
60
50
40
30
20
10
0
-40
-20
0
20
40
60
80
100 120 140
1.5
2
2.5
3
3.5
4
Voltage Supply (V)
4.5
5
5.5
Temperature (èC)
D022
D021
Figure 7-22. Quiescent Current vs Temperature
Figure 7-21. Quiescent Current vs Supply Voltage
2000
50
1800
1600
1400
1200
1000
800
600
400
200
0
45
40
35
30
25
20
15
10
5
Overshoot (+)
Overshoot (–)
0
1k
10k
100k
Frequency (Hz)
1M
10M
0
200
400 600
Capacitance Load (pF)
800
1000
D023
D024
G = 1
VIN = 100 mVpp
Figure 7-23. Open-Loop Output Impedance vs Frequency
Figure 7-24. Small Signal Overshoot vs Capacitive Load
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7.11 Typical Characteristics (continued)
at TA = 25°C, V+ = 2.75 V, V– = –2.75 V, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise
noted)
50
45
40
35
30
25
20
15
10
5
90
80
70
60
50
40
30
20
10
0
Overshoot (+)
Overshoot (–)
0
0
200
400 600
Capacitance Load (pF)
800
1000
0
200
400 600
Capacitance Load (pF)
800
1000
D025
D026
G = –1
VIN = 100 mVpp
Figure 7-25. Small Signal Overshoot vs Capacitive Load
Figure 7-26. Phase Margin vs Capacitive Load
VOUT
VIN
VOUT
VIN
Time (100 ms/div)
Time (20 ms/div)
D027
D028
G = 1
VIN = 6.5 VPP
G = –10
VIN = 600 mVPP
Figure 7-27. No Phase Reversal
Figure 7-28. Overload Recovery
VOUT
VIN
VOUT
VIN
Time (10 ms/div)
Time (10 ms/div)
D029
D030
G = 1
VIN = 100 mVPP
CL = 10 pF
G = 1
VIN = 4 VPP
CL = 10 pF
Figure 7-29. Small-Signal Step Response
Figure 7-30. Large-Signal Step Response
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7.11 Typical Characteristics (continued)
at TA = 25°C, V+ = 2.75 V, V– = –2.75 V, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise
noted)
Time (1 ms/div)
Time (1 μs/div)
D032
D031
G = 1
CL = 100 pF
2-V step
G = 1
CL = 100 pF
2-V step
Figure 7-32. Large-Signal Settling Time (Positive)
Figure 7-31. Large-Signal Settling Time (Negative)
80
6
VS = 5.5 V
VS = 1.8 V
60
40
20
0
5
4
3
2
1
0
-20
-40
-60
-80
Sinking
Sourcing
1
10
100
1k
10k
Frequency (Hz)
100k
1M
10M 100M
-40
-20
0
20
40
60
80
100
120
Temperature (èC)
D034
D033
Figure 7-34. Maximum Output Voltage vs Frequency
Figure 7-33. Short-Circuit Current vs Temperature
140
0
-20
-40
120
100
80
60
40
20
0
-60
-80
-100
-120
-140
1k
10k
100k
Frequency (Hz)
1M
10M
10M
100M
Frequency (Hz)
1G
10G
D036
D035
Figure 7-36. Channel Separation
Figure 7-35. Electromagnetic Interference Rejection Ratio
Referred to Noninverting Input (EMIRR+) vs Frequency
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8 Detailed Description
8.1 Overview
The TLV900x is a family of low-power, rail-to-rail input and output op amps. These devices operate from 1.8 V
to 5.5 V, are unity-gain stable, and are designed for a wide range of general-purpose applications. The input
common-mode voltage range includes both rails and allows the TLV900x family to be used in virtually any
single-supply application. Rail-to-rail input and output swing significantly increases dynamic range, especially in
low-supply applications, and makes them suitable for driving sampling analog-to-digital converters (ADCs).
8.2 Functional Block Diagram
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8.3 Feature Description
8.3.1 Operating Voltage
The TLV900x family of op amps are for operation from 1.8 V to 5.5 V. In addition, many specifications such
as input offset voltage, quiescent current, offset current, and short circuit current apply from –40°C to 125°C.
Parameters that vary significantly with operating voltages or temperature are shown in Section 7.11.
8.3.2 Rail-to-Rail Input
The input common-mode voltage range of the TLV900x family extends 100 mV beyond the supply rails for the
full supply voltage range of 1.8 V to 5.5 V. This performance is achieved with a complementary input stage:
an N-channel input differential pair in parallel with a P-channel differential pair, as shown in Section 8.2. The
N-channel pair is active for input voltages close to the positive rail, typically (V+) – 1.4 V to 100 mV above
the positive supply, whereas the P-channel pair is active for inputs from 100 mV below the negative supply to
approximately (V+) – 1.4 V. There is a small transition region, typically (V+) – 1.2 V to (V+) – 1 V, in which both
pairs are on. This 100-mV transition region can vary up to 100 mV with process variation. Thus, the transition
region (with both stages on) can range from (V+) – 1.4 V to (V+) – 1.2 V on the low end, and up to (V+) – 1 V to
(V+) – 0.8 V on the high end. Within this transition region, PSRR, CMRR, offset voltage, offset drift, and THD can
degrade compared to device operation outside this region.
8.3.3 Rail-to-Rail Output
Designed as a low-power, low-voltage operational amplifier, the TLV900x family delivers a robust output
drive capability. A class-AB output stage with common-source transistors achieves full rail-to-rail output swing
capability. For resistive loads of 10 kΩ, the output swings to within 20 mV of either supply rail, regardless of the
applied power-supply voltage. Different load conditions change the ability of the amplifier to swing close to the
rails.
8.3.4 EMI Rejection
The TLV900x uses integrated electromagnetic interference (EMI) filtering to reduce the effects of EMI from
sources such as wireless communications and densely-populated boards with a mix of analog signal chain and
digital components. EMI immunity can be improved with circuit design techniques; the TLV900x benefits from
these design improvements. Texas Instruments has developed the ability to accurately measure and quantify the
immunity of an operational amplifier over a broad frequency spectrum extending from 10 MHz to 6 GHz. Figure
8-1 shows the results of this testing on the TLV900x. Table 8-1 shows the EMIRR IN+ values for the TLV900x at
particular frequencies commonly encountered in real-world applications. The EMI Rejection Ratio of Operational
Amplifiers application report contains detailed information on the topic of EMIRR performance as it relates to op
amps and is available for download from www.ti.com.
140
120
100
80
60
40
20
0
10M
100M
Frequency (Hz)
1G
10G
D035
Figure 8-1. EMIRR Testing
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Table 8-1. TLV900x EMIRR IN+ For Frequencies of Interest
FREQUENCY
APPLICATION OR ALLOCATION
EMIRR IN+
Mobile radio, mobile satellite, space operation, weather, radar, ultra-high frequency (UHF)
applications
400 MHz
59.5 dB
Global system for mobile communications (GSM) applications, radio communication, navigation,
GPS (to 1.6 GHz), GSM, aeronautical mobile, UHF applications
900 MHz
1.8 GHz
2.4 GHz
3.6 GHz
68.9 dB
77.8 dB
78.0 dB
88.8 dB
GSM applications, mobile personal communications, broadband, satellite, L-band (1 GHz to 2 GHz)
802.11b, 802.11g, 802.11n, Bluetooth®, mobile personal communications, industrial, scientific and
medical (ISM) radio band, amateur radio and satellite, S-band (2 GHz to 4 GHz)
Radiolocation, aero communication and navigation, satellite, mobile, S-band
8.4 Overload Recovery
Overload recovery is defined as the time required for the operational amplifier output to recover from a saturated
state to a linear state. The output devices of the operational amplifier enter a saturation region when the output
voltage exceeds the rated operating voltage, because of the high input voltage or the high gain. After the device
enters the saturation region, the charge carriers in the output devices require time to return to the linear state.
After the charge carriers return to the linear state, the device begins to slew at the specified slew rate. Therefore,
the propagation delay (in case of an overload condition) is the sum of the overload recovery time and the slew
time. The overload recovery time for the TLV900x family is approximately 850 ns.
8.5 Shutdown
The TLV9001S, TLV9002S, and TLV9004S devices feature SHDN pins that disable the op amp, placing it into
a low-power standby mode. In this mode, the op amp typically consumes less than 1 µA. The SHDN pins are
active low, meaning that shutdown mode is enabled when the input to the SHDN pin is a valid logic low.
The SHDN pins are referenced to the negative supply voltage of the op amp. The threshold of the shutdown
feature lies around 620 mV (typical) and does not change with respect to the supply voltage. Hysteresis has
been included in the switching threshold to ensure smooth switching characteristics. To ensure optimal shutdown
behavior, the SHDN pins should be driven with valid logic signals. A valid logic low is defined as a voltage
between V– and V– + 0.2 V. A valid logic high is defined as a voltage between V– + 1.2 V and V+. The shutdown
pin circuitry includes a pull-up resistor, which will inherently pull the voltage of the pin to the positive supply rail
if not driven. Thus, to enable the amplifier, the SHDN pins should either be left floating or driven to a valid logic
high. To disable the amplifier, the SHDN pins must be driven to a valid logic low. While we highly recommend
that the shutdown pin be connected to a valid high or a low voltage or driven, we have included a pull-up resistor
connected to VCC. The maximum voltage allowed at the SHDN pins is (V+) + 0.5 V. Exceeding this voltage level
will damage the device.
The SHDN pins are high-impedance CMOS inputs. Dual op amp versions are independently controlled and quad
op amp versions are controlled in pairs with logic inputs. For battery-operated applications, this feature may be
used to greatly reduce the average current and extend battery life. The enable time is 70 µs for full shutdown of
all channels; disable time is 4 µs. When disabled, the output assumes a high-impedance state. This architecture
allows the TLV9002S and TLV9004S to operate as a gated amplifier (or to have the device output multiplexed
onto a common analog output bus). Shutdown time (tOFF) depends on loading conditions and increases as load
resistance increases. To ensure shutdown (disable) within a specific shutdown time, the specified 10-kΩ load
to midsupply (VS / 2) is required. If using the TLV9001S, TLV9002S, or TLV9004S without a load, the resulting
turnoff time significantly increases.
8.6 Device Functional Modes
The TLV900x family has a single functional mode. The devices are powered on as long as the power-supply
voltage is between 1.8 V (±0.9 V) and 5.5 V (±2.75 V).
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9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and
TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
9.1 Application Information
The TLV900x family of low-power, rail-to-rail input and output operational amplifiers is specifically designed for
portable applications. The devices operate from 1.8 V to 5.5 V, are unity-gain stable, and are suitable for a wide
range of general-purpose applications. The class AB output stage is capable of driving less than or equal to
10‑kΩ loads connected to any point between V+ and V–. The input common-mode voltage range includes both
rails, and allows the TLV900x devices to be used in any single-supply application.
9.2 Typical Application
9.2.1 TLV900x Low-Side, Current Sensing Application
Figure 9-1 shows the TLV900x configured in a low-side current sensing application.
VBUS
ILOAD
ZLOAD
5 V
+
TLV9002
VOUT
Þ
+
RSHUNT
VSHUNT
RF
0.1 Ω
57.6 kΩ
Þ
RG
1.2 kΩ
Figure 9-1. TLV900x in a Low-Side, Current-Sensing Application
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9.2.1.1 Design Requirements
The design requirements for this design are:
•
•
•
Load current: 0 A to 1 A
Output voltage: 4.9 V
Maximum shunt voltage: 100 mV
9.2.1.2 Detailed Design Procedure
The transfer function of the circuit in Figure 9-1 is given in Equation 1.
VOUT = ILOAD ìRSHUNT ìGain
(1)
The load current (ILOAD) produces a voltage drop across the shunt resistor (RSHUNT). The load current is set
from 0 A to 1 A. To keep the shunt voltage below 100 mV at maximum load current, the largest shunt resistor is
shown using Equation 2.
VSHUNT _MAX
100mV
1A
RSHUNT
=
=
=100mW
ILOAD_MAX
(2)
Using Equation 2, RSHUNT is calculated to be 100 mΩ. The voltage drop produced by ILOAD and RSHUNT is
amplified by the TLV900x to produce an output voltage of approximately 0 V to 4.9 V. The gain needed by the
TLV900x to produce the necessary output voltage is calculated using Equation 3.
V
OUT _MAX - VOUT _MIN
(
)
Gain =
VIN_MAX - V
IN_MIN
(3)
Using Equation 3, the required gain is calculated to be 49 V/V, which is set with resistors RF and RG. Equation 4
sizes the resistors RF and RG, to set the gain of the TLV900x to 49 V/V.
R
(
)
F
Gain = 1+
R
G
(4)
Selecting RF as 57.6 kΩ and RG as 1.2 kΩ provides a combination that equals 49 V/V. Figure 9-2 shows the
measured transfer function of the circuit shown in Figure 9-1. Notice that the gain is only a function of the
feedback and gain resistors. This gain is adjusted by varying the ratio of the resistors and the actual resistors
values are determined by the impedance levels that the designer wants to establish. The impedance level
determines the current drain, the effect that stray capacitance has, and a few other behaviors. There is no
optimal impedance selection that works for every system, you must choose an impedance that is ideal for your
system parameters.
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9.2.1.3 Application Curve
5
4
3
2
1
0
0
0.2
0.4
0.6
0.8
1
ILOAD (A)
C219
Figure 9-2. Low-Side, Current-Sense Transfer Function
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9.2.2 Single-Supply Photodiode Amplifier
Photodiodes are used in many applications to convert light signals to electrical signals. The current through
the photodiode is proportional to the photon energy absorbed, and is commonly in the range of a few hundred
picoamps to a few tens of microamps. An amplifier in a transimpedance configuration is typically used to convert
the low-level photodiode current to a voltage signal for processing in an MCU. The circuit shown in Figure 9-3 is
an example of a single-supply photodiode amplifier circuit using the TLV9002.
+3.3V
R1
11.5 kΩ
10 pF
CF
VREF
R2
357 Ω
RF
309 kΩ
3.3 V
œ
TLV9002
VOUT
+
VREF
CPD
IIN
0-10 µA
RL
10 kꢀ
47 pF
Figure 9-3. Single-Supply Photodiode Amplifier Circuit
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9.2.2.1 Design Requirements
The design requirements for this design are:
•
•
•
•
Supply voltage: 3.3 V
Input: 0 µA to 10 µA
Output: 0.1 V to 3.2 V
Bandwidth: 50 kHz
9.2.2.2 Detailed Design Procedure
The transfer function between the output voltage (VOUT), the input current, (IIN) and the reference voltage (VREF
)
is defined in Equation 5.
VOUT = IIN ìRF + VREF
(5)
(6)
Where:
≈
∆
«
’
÷
R1 ìR2
R1 + R2 ◊
VREF = V ì
+
Set VREF to 100 mV to meet the minimum output voltage level by setting R1 and R2 to meet the required ratio
calculated in Equation 7.
VREF
0.1 V
3.3 V
=
= 0.0303
V+
(7)
The closest resistor ratio to meet this ratio sets R1 to 11.5 kΩ and R2 to 357 Ω.
The required feedback resistance can be calculated based on the input current and desired output voltage.
VOUT - VREF
3.2 V - 0.1 V
10 mA
kV
A
RF =
=
= 310
ö 309 kW
I
IN
(8)
Calculate the value for the feedback capacitor based on RF and the desired –3-dB bandwidth, (f–3dB) using
Equation 9.
1
1
CF =
=
= 10.3 pF ö 10 pF
2ì pìRF ì f-3dB 2ì pì309 kWì50 kHz
(9)
The minimum op amp bandwidth required for this application is based on the value of RF, CF, and the
capacitance on the INx– pin of the TLV9002 which is equal to the sum of the photodiode shunt capacitance,
(CPD) the common-mode input capacitance, (CCM) and the differential input capacitance (CD) as Equation 10
shows.
C
= CPD + CCM + CD = 47 pF+ 5 pF +1pF = 53 pF
IN
(10)
The minimum op amp bandwidth is calculated in Equation 11.
CIN + CF
f=BGW
í
í 324 kHz
2
2ì pìRF ì CF
(11)
The 1-MHz bandwidth of the TLV900x meets the minimum bandwidth requirement and remains stable in this
application configuration.
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9.2.2.3 Application Curves
The measured current-to-voltage transfer function for the photodiode amplifier circuit is shown in Figure 9-4. The
measured performance of the photodiode amplifier circuit is shown in Figure 9-5.
120
100
80
3
2.5
2
1.5
1
60
0.5
0
40
10
100
1k 10k
Frequency (Hz)
100k
1M
0
2E-6
4E-6 6E-6
Input Current (A)
8E-6
1E-5
D001
D002
Figure 9-4. Photodiode Amplifier Circuit AC Gain
Results
Figure 9-5. Photodiode Amplifier Circuit DC
Results
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10 Power Supply Recommendations
The TLV900x family is specified for operation from 1.8 V to 5.5 V (±0.9 V to ±2.75 V); many specifications
apply from –40°C to 125°C. Section 7.11 presents parameters that may exhibit significant variance with regard to
operating voltage or temperature.
CAUTION
Supply voltages larger than 6 V may permanently damage the device; see Section 7.1.
Place 0.1-µF bypass capacitors close to the power-supply pins to reduce coupling errors from noisy or high-
impedance power supplies. For more detailed information on bypass capacitor placement, see Section 11.1.
10.1 Input and ESD Protection
The TLV900x family incorporates internal ESD protection circuits on all pins. For input and output pins, this
protection primarily consists of current-steering diodes connected between the input and power-supply pins.
These ESD protection diodes provide in-circuit, input overdrive protection, as long as the current is limited to
10 mA. Figure 10-1 shows how a series input resistor can be added to the driven input to limit the input current.
The added resistor contributes thermal noise at the amplifier input and the value must be kept to a minimum in
noise-sensitive applications.
V+
IOVERLOAD
10-mA maximum
VOUT
Device
VIN
5 kW
Figure 10-1. Input Current Protection
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11 Layout
11.1 Layout Guidelines
For best operational performance of the device, use good printed circuit board (PCB) layout practices, including:
•
Noise can propagate into analog circuitry through the power connections of the board and propagate to the
power pins of the op amp itself. Bypass capacitors are used to reduce the coupled noise by providing a
low-impedance path to ground.
– Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as
close to the device as possible. A single bypass capacitor from V+ to ground is adequate for single-supply
applications.
•
•
Separate grounding for analog and digital portions of circuitry is one of the simplest and most effective
methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes.
A ground plane helps distribute heat and reduces electromagnetic interference (EMI) noise pickup. Take care
to physically separate digital and analog grounds, paying attention to the flow of the ground current.
To reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible.
If these traces cannot be kept separate, crossing the sensitive trace at a 90 degree angle is much better as
opposed to running the traces in parallel with the noisy trace.
•
•
•
Place the external components as close to the device as possible, as shown in Figure 11-2. Keeping RF and
RG close to the inverting input minimizes parasitic capacitance.
Keep the length of input traces as short as possible. Remember that the input traces are the most sensitive
part of the circuit.
Consider a driven, low-impedance guard ring around the critical traces. A guard ring may significantly reduce
leakage currents from nearby traces that are at different potentials.
•
•
Cleaning the PCB following board assembly is recommended for best performance.
Any precision integrated circuit can experience performance shifts resulting from moisture ingress into the
plastic package. Following any aqueous PCB cleaning process, baking the PCB assembly is recommended
to remove moisture introduced into the device packaging during the cleaning process. A low-temperature,
post-cleaning bake at 85°C for 30 minutes is sufficient for most circumstances.
11.2 Layout Example
VIN 1
VIN 2
+
+
VOUT 1
VOUT 2
RG
RG
RF
RF
Figure 11-1. Schematic Representation
Place components
close to device and to
each other to reduce
parasitic errors.
OUT 1
Use low-ESR,
ceramic bypass
capacitor . Place as
close to the device
as possible .
VS+
GND
OUT1
V+
RF
RG
OUT 2
GND
IN1œ
IN1+
Vœ
OUT2
IN2œ
IN2+
RF
VIN 1
GND
RG
VIN 2
Keep input traces short
and run the input traces
as far away from
the supply lines
Use low-ESR,
GND
ceramic bypass
capacitor . Place as
close to the device
as possible .
VSœ
Ground (GND) plane on another layer
as possible .
Figure 11-2. Layout Example
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
35
Product Folder Links: TLV9001 TLV9002 TLV9004
TLV9001, TLV9002, TLV9004
SBOS833R – OCTOBER 2017 – REVISED NOVEMBER 2021
www.ti.com
12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation, see the following:
•
Texas Instruments, EMI Rejection Ratio of Operational Amplifiers
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
12.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
Bluetooth® is a registered trademark of Bluetooth SIG, Inc.
All trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.6 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
Copyright © 2021 Texas Instruments Incorporated
36
Submit Document Feedback
Product Folder Links: TLV9001 TLV9002 TLV9004
TLV9001, TLV9002, TLV9004
SBOS833R – OCTOBER 2017 – REVISED NOVEMBER 2021
www.ti.com
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most-
current data available for the designated devices. This data is subject to change without notice and without
revision of this document. For browser-based versions of this data sheet, see the left-hand navigation pane.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
37
Product Folder Links: TLV9001 TLV9002 TLV9004
PACKAGE OPTION ADDENDUM
www.ti.com
18-Nov-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TLV9001IDBVR
TLV9001IDCKR
TLV9001IDPWR
TLV9001SIDBVR
TLV9001SIDCKR
TLV9001TIDCKR
TLV9001UIDBVR
TLV9002IDDFR
TLV9002IDGKR
TLV9002IDGKT
TLV9002IDR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOT-23
SC70
DBV
DCK
DPW
DBV
DCK
DCK
DBV
DDF
DGK
DGK
D
5
5
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
2500 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-1-260C-UNLIM
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-1-260C-UNLIM
Level-2-260C-1 YEAR
Level-1-260C-UNLIM
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
1OGF
1BZ
SN
NIPDAUAG
NIPDAU
SN
X2SON
SOT-23
SC70
5
DF
6
1OJF
1F8
6
SC70
5
SN
1D6
SOT-23
5
NIPDAU
NIPDAU
NIPDAUAG
NIPDAUAG
SN
1ODF
T902
1GNX
1GNX
ACTIVE SOT-23-THIN
8
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
VSSOP
VSSOP
SOIC
8
8
250
RoHS & Green
8
2500 RoHS & Green
3000 RoHS & Green
TL9002
1GMH
1GMH
9002
TLV9002IDSGR
TLV9002IDSGT
TLV9002IPWR
TLV9002SIDGSR
TLV9002SIRUGR
TLV9002SIYCKR
TLV9004IDR
WSON
WSON
TSSOP
VSSOP
X2QFN
DSBGA
SOIC
DSG
DSG
PW
8
NIPDAU
NIPDAU
NIPDAU | SN
NIPDAUAG
NIPDAUAG
SNAGCU
NIPDAU
NIPDAU
SN
8
250
RoHS & Green
8
2000 RoHS & Green
2500 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
2500 RoHS & Green
3000 RoHS & Green
2000 RoHS & Green
DGS
RUG
YCK
D
10
10
9
1GDX
ENF
JK
14
14
14
TLV9004
TLV9004I
TLV9004
TLV9004IDYYR
TLV9004IPWR
ACTIVE SOT-23-THIN
ACTIVE TSSOP
DYY
PW
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
18-Nov-2021
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TLV9004IRTER
TLV9004IRUCR
TLV9004SIRTER
ACTIVE
ACTIVE
ACTIVE
WQFN
QFN
RTE
RUC
RTE
16
14
16
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
Level-2-260C-1 YEAR
Level-1-260C-UNLIM
-40 to 125
-40 to 125
-40 to 125
T9004
NIPDAU
NIPDAU
1DC
WQFN
T9004S
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
18-Nov-2021
OTHER QUALIFIED VERSIONS OF TLV9002, TLV9004 :
Automotive : TLV9002-Q1, TLV9004-Q1
•
NOTE: Qualified Version Definitions:
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
•
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
19-Nov-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TLV9001IDBVR
TLV9001IDCKR
TLV9001IDPWR
TLV9001SIDBVR
TLV9001SIDCKR
TLV9001TIDCKR
TLV9001UIDBVR
TLV9002IDDFR
SOT-23
SC70
DBV
DCK
DPW
DBV
DCK
DCK
DBV
DDF
5
5
5
6
6
5
5
8
3000
3000
3000
3000
3000
3000
3000
3000
180.0
178.0
178.0
180.0
178.0
178.0
180.0
180.0
8.4
9.0
8.4
8.4
9.0
9.0
8.4
8.4
3.2
2.4
0.91
3.2
2.4
2.4
3.2
3.2
3.2
2.5
0.91
3.2
2.5
2.5
3.2
3.2
1.4
1.2
0.5
1.4
1.2
1.2
1.4
1.4
4.0
4.0
2.0
4.0
4.0
4.0
4.0
4.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
Q3
Q3
Q2
Q3
Q3
Q3
Q3
Q3
X2SON
SOT-23
SC70
SC70
SOT-23
SOT-
23-THIN
TLV9002IDGKR
TLV9002IDGKT
TLV9002IDR
VSSOP
VSSOP
SOIC
DGK
DGK
D
8
8
2500
250
330.0
330.0
330.0
180.0
180.0
330.0
330.0
330.0
178.0
12.4
12.4
15.4
8.4
5.3
5.3
6.4
2.3
2.3
7.0
7.0
5.3
1.75
3.4
3.4
5.2
2.3
2.3
3.6
3.6
3.4
2.25
1.4
1.4
8.0
8.0
8.0
4.0
4.0
8.0
8.0
8.0
4.0
12.0
12.0
12.0
8.0
Q1
Q1
Q1
Q2
Q2
Q1
Q1
Q1
Q1
8
2500
3000
250
2.1
TLV9002IDSGR
TLV9002IDSGT
TLV9002IPWR
TLV9002IPWR
TLV9002SIDGSR
TLV9002SIRUGR
WSON
WSON
TSSOP
TSSOP
VSSOP
X2QFN
DSG
DSG
PW
8
1.15
1.15
1.6
8
8.4
8.0
8
2000
2000
2500
3000
12.4
12.4
12.4
8.4
12.0
12.0
12.0
8.0
PW
8
1.6
DGS
RUG
10
10
1.4
0.56
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
19-Nov-2021
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TLV9002SIYCKR
TLV9004IDR
DSBGA
SOIC
YCK
D
9
3000
2500
2500
3000
180.0
330.0
330.0
330.0
8.4
1.1
6.4
6.5
4.8
1.1
5.2
9.0
3.6
0.4
2.1
2.1
1.6
2.0
8.0
8.0
8.0
8.0
Q1
Q1
Q1
Q3
14
14
14
15.4
16.4
12.4
12.0
16.0
12.0
TLV9004IDR
SOIC
D
TLV9004IDYYR
SOT-
DYY
23-THIN
TLV9004IPWR
TLV9004IRTER
TLV9004IRUCR
TLV9004SIRTER
TSSOP
WQFN
QFN
PW
RTE
RUC
RTE
14
16
14
16
2000
3000
3000
3000
330.0
330.0
180.0
330.0
12.4
12.4
9.5
6.9
3.3
5.6
3.3
1.6
1.1
0.5
1.1
8.0
8.0
4.0
8.0
12.0
12.0
8.0
Q1
Q2
Q2
Q2
2.16
3.3
2.16
3.3
WQFN
12.4
12.0
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TLV9001IDBVR
TLV9001IDCKR
TLV9001IDPWR
TLV9001SIDBVR
TLV9001SIDCKR
TLV9001TIDCKR
TLV9001UIDBVR
TLV9002IDDFR
SOT-23
SC70
DBV
DCK
DPW
DBV
DCK
DCK
DBV
DDF
5
5
5
6
6
5
5
8
3000
3000
3000
3000
3000
3000
3000
3000
210.0
190.0
205.0
210.0
180.0
190.0
210.0
210.0
185.0
190.0
200.0
185.0
180.0
190.0
185.0
185.0
35.0
30.0
33.0
35.0
18.0
30.0
35.0
35.0
X2SON
SOT-23
SC70
SC70
SOT-23
SOT-23-THIN
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
19-Nov-2021
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TLV9002IDGKR
TLV9002IDGKT
TLV9002IDR
VSSOP
VSSOP
SOIC
DGK
DGK
D
8
8
2500
250
366.0
366.0
336.6
210.0
210.0
366.0
853.0
366.0
205.0
182.0
336.6
853.0
336.6
366.0
367.0
205.0
367.0
364.0
364.0
336.6
185.0
185.0
364.0
449.0
364.0
200.0
182.0
336.6
449.0
336.6
364.0
367.0
200.0
367.0
50.0
50.0
41.3
35.0
35.0
50.0
35.0
50.0
33.0
20.0
41.3
35.0
31.8
50.0
35.0
30.0
35.0
8
2500
3000
250
TLV9002IDSGR
TLV9002IDSGT
TLV9002IPWR
TLV9002IPWR
TLV9002SIDGSR
TLV9002SIRUGR
TLV9002SIYCKR
TLV9004IDR
WSON
WSON
TSSOP
TSSOP
VSSOP
X2QFN
DSBGA
SOIC
DSG
DSG
PW
8
8
8
2000
2000
2500
3000
3000
2500
2500
3000
2000
3000
3000
3000
PW
8
DGS
RUG
YCK
D
10
10
9
14
14
14
14
16
14
16
TLV9004IDR
SOIC
D
TLV9004IDYYR
TLV9004IPWR
TLV9004IRTER
TLV9004IRUCR
TLV9004SIRTER
SOT-23-THIN
TSSOP
WQFN
QFN
DYY
PW
RTE
RUC
RTE
WQFN
Pack Materials-Page 3
PACKAGE OUTLINE
DGS0010A
VSSOP - 1.1 mm max height
S
C
A
L
E
3
.
2
0
0
SMALL OUTLINE PACKAGE
C
SEATING PLANE
0.1 C
5.05
4.75
TYP
PIN 1 ID
AREA
A
8X 0.5
10
1
3.1
2.9
NOTE 3
2X
2
5
6
0.27
0.17
10X
3.1
2.9
1.1 MAX
0.1
C A
B
B
NOTE 4
0.23
0.13
TYP
SEE DETAIL A
0.25
GAGE PLANE
0.15
0.05
0.7
0.4
0 - 8
DETAIL A
TYPICAL
4221984/A 05/2015
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-187, variation BA.
www.ti.com
EXAMPLE BOARD LAYOUT
DGS0010A
VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE
10X (1.45)
(R0.05)
TYP
SYMM
10X (0.3)
1
5
10
SYMM
6
8X (0.5)
(4.4)
LAND PATTERN EXAMPLE
SCALE:10X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
4221984/A 05/2015
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DGS0010A
VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE
10X (1.45)
SYMM
(R0.05) TYP
10X (0.3)
8X (0.5)
1
5
10
SYMM
6
(4.4)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:10X
4221984/A 05/2015
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
DPW0005A
X2SON - 0.4 mm max height
S
C
A
L
E
1
2
.
0
0
0
PLASTIC SMALL OUTLINE - NO LEAD
0.85
0.75
A
B
PIN 1 INDEX AREA
0.85
0.75
0.4 MAX
C
SEATING PLANE
NOTE 3
(0.1)
0.05
0.00
(0.324)
4X (0.05)
0.25 0.1
2
1
4
5
NOTE 3
2X
3
2X (0.26)
0.48
0.245
0.145
4X
0.239
0.139
0.1
C A B
C
0.288
0.188
3X
0.05
4223102/C 06/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The size and shape of this feature may vary.
www.ti.com
EXAMPLE BOARD LAYOUT
DPW0005A
X2SON - 0.4 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(0.78)
(
0.1)
SYMM
4X (0.42)
VIA
0.05 MIN
ALL AROUND
TYP
1
5
4X (0.22)
SYMM
4X (0.26)
(0.48)
3
2
4
(R0.05) TYP
SOLDER MASK
OPENING, TYP
4X (0.06)
(
0.25)
(0.21) TYP
EXPOSED METAL
CLEARANCE
METAL UNDER
SOLDER MASK
TYP
LAND PATTERN EXAMPLE
SOLDER MASK DEFINED
SCALE:60X
4223102/C 06/2021
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, refer to QFN/SON PCB application note
in literature No. SLUA271 (www.ti.com/lit/slua271).
www.ti.com
EXAMPLE STENCIL DESIGN
DPW0005A
X2SON - 0.4 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
4X (0.42)
4X (0.06)
5
1
4X (0.22)
SYMM
(
0.24)
4X (0.26)
(0.21)
(0.48)
TYP
SOLDER MASK
EDGE
3
2
4
(R0.05) TYP
SYMM
(0.78)
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
EXPOSED PAD 3
92% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:100X
4223102/C 06/2021
NOTES: (continued)
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.189-.197
[4.81-5.00]
NOTE 3
.150
[3.81]
4X (0 -15 )
4
5
8X .012-.020
[0.31-0.51]
B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.010 [0.25]
C A B
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 - 8
.016-.050
[0.41-1.27]
DETAIL A
TYPICAL
(.041)
[1.04]
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED
METAL
EXPOSED
METAL
.0028 MAX
[0.07]
.0028 MIN
[0.07]
ALL AROUND
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
YCK0009
DSBGA - 0.33 mm max height
SCALE 12.000
DIE SIZE BALL GRID ARRAY
A
D
B
E
BALL A1
CORNER
0.33 MAX
C
SEATING PLANE
0.05 C
BALL TYP
0.125
0.075
0.7 TYP
SYMM
C
SYMM
0.7 TYP
B
A
D: Max = 0.98 mm, Min = 0.92 mm
E: Max = 0.98 mm, Min = 0.92 mm
0.35 TYP
1
2
3
0.195
0.155
C A B
9X
0.015
0.35 TYP
4225837/A 04/2020
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
YCK0009
DSBGA - 0.33 mm max height
DIE SIZE BALL GRID ARRAY
(0.35) TYP
9X ( 0.18)
1
2
3
A
(0.35) TYP
SYMM
B
C
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 50X
0.0325 MIN
0.0325 MAX
METAL UNDER
SOLDER MASK
(
0.18)
METAL
EXPOSED
METAL
(
0.18)
SOLDER MASK
OPENING
EXPOSED
METAL
SOLDER MASK
OPENING
SOLDER MASK
DEFINED
(PREFERRED)
NON-SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
4225837/A 04/2020
NOTES: (continued)
3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
See Texas Instruments Literature No. SNVA009 (www.ti.com/lit/snva009).
www.ti.com
EXAMPLE STENCIL DESIGN
YCK0009
DSBGA - 0.33 mm max height
DIE SIZE BALL GRID ARRAY
(0.35) TYP
(R0.05) TYP
3
9X ( 0.21)
1
2
A
(0.35) TYP
SYMM
B
C
METAL
TYP
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.075 mm THICK STENCIL
SCALE: 50X
4225837/A 04/2020
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
www.ti.com
PACKAGE OUTLINE
DBV0006A
SOT-23 - 1.45 mm max height
S
C
A
L
E
4
.
0
0
0
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
0.1 C
1.75
1.45
B
1.45 MAX
A
PIN 1
INDEX AREA
1
2
6
5
2X 0.95
1.9
3.05
2.75
4
3
0.50
6X
0.25
C A B
0.15
0.00
0.2
(1.1)
TYP
0.25
GAGE PLANE
0.22
0.08
TYP
8
TYP
0
0.6
0.3
TYP
SEATING PLANE
4214840/C 06/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Body dimensions do not include mold flash or protrusion. Mold flash and protrusion shall not exceed 0.25 per side.
4. Leads 1,2,3 may be wider than leads 4,5,6 for package orientation.
5. Refernce JEDEC MO-178.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0006A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
6X (1.1)
1
6X (0.6)
6
SYMM
5
2
3
2X (0.95)
4
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214840/C 06/2021
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0006A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
6X (1.1)
1
6X (0.6)
6
SYMM
5
2
3
2X(0.95)
4
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214840/C 06/2021
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
GENERIC PACKAGE VIEW
DSG 8
2 x 2, 0.5 mm pitch
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224783/A
www.ti.com
PACKAGE OUTLINE
DSG0008A
WSON - 0.8 mm max height
SCALE 5.500
PLASTIC SMALL OUTLINE - NO LEAD
2.1
1.9
B
A
PIN 1 INDEX AREA
2.1
1.9
0.32
0.18
0.4
0.2
ALTERNATIVE TERMINAL SHAPE
TYPICAL
C
0.8 MAX
SEATING PLANE
0.08 C
0.05
0.00
EXPOSED
THERMAL PAD
(0.2) TYP
0.9 0.1
5
4
6X 0.5
2X
1.5
9
1.6 0.1
8
1
0.32
0.18
8X
0.4
0.2
PIN 1 ID
8X
0.1
C A B
C
0.05
4218900/D 04/2020
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
DSG0008A
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(0.9)
(
0.2) VIA
8X (0.5)
TYP
1
8
8X (0.25)
(0.55)
SYMM
9
(1.6)
6X (0.5)
5
4
SYMM
(1.9)
(R0.05) TYP
LAND PATTERN EXAMPLE
SCALE:20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4218900/D 04/2020
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
DSG0008A
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
8X (0.5)
METAL
8
SYMM
1
8X (0.25)
(0.45)
SYMM
9
(0.7)
6X (0.5)
5
4
(R0.05) TYP
(0.9)
(1.9)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 9:
87% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:25X
4218900/D 04/2020
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
PACKAGE OUTLINE
PW0008A
TSSOP - 1.2 mm max height
S
C
A
L
E
2
.
8
0
0
SMALL OUTLINE PACKAGE
C
6.6
6.2
SEATING PLANE
TYP
PIN 1 ID
AREA
A
0.1 C
6X 0.65
8
5
1
3.1
2.9
NOTE 3
2X
1.95
4
0.30
0.19
8X
4.5
4.3
1.2 MAX
B
0.1
C A
B
NOTE 4
(0.15) TYP
SEE DETAIL A
0.25
GAGE PLANE
0.15
0.05
0.75
0.50
0 - 8
DETAIL A
TYPICAL
4221848/A 02/2015
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
PW0008A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
8X (1.5)
SYMM
8X (0.45)
(R0.05)
1
4
TYP
8
SYMM
6X (0.65)
5
(5.8)
LAND PATTERN EXAMPLE
SCALE:10X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
4221848/A 02/2015
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
PW0008A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
8X (1.5)
SYMM
(R0.05) TYP
8X (0.45)
1
4
8
SYMM
6X (0.65)
5
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:10X
4221848/A 02/2015
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
X2QFN - 0.4 mm max height
PLASTIC QUAD FLAT PACK- NO LEAD
RUC0014A
A
2.1
1.9
B
2.1
1.9
PIN 1 INDEX AREA
0.4 MAX
C
SEATING PLANE
0.08 C
0.05
0.00
(0.15) TYP
2X 0.4
6
7
8X 0.4
5
8
SYMM
1.6
12
1
0.25
0.15
14
13
14X
0.5
PIN 1 ID
SYMM
(45oX0.1)
0.1
C A B
C
14X
0.3
0.05
4220584/A 05/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
X2QFN - 0.4 mm max height
PLASTIC QUAD FLAT PACK- NO LEAD
RUC0014A
SYMM
14X (0.6)
14X (0.2)
8X (0.4)
SYMM
(1.6) (1.8)
(R0.05)
2X (0.4)
(1.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 23X
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
EXPOSED METAL
EXPOSED METAL
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4220584/A 05/2019
NOTES: (continued)
3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).
www.ti.com
EXAMPLE STENCIL DESIGN
X2QFN - 0.4 mm max height
RUC0014A
PLASTIC QUAD FLAT PACK- NO LEAD
SYMM
14X (0.6)
14X (0.2)
8X (0.4)
SYMM
(1.6) (1.8)
(R0.05)
2X (0.4)
(1.8)
SOLDER PASTE EXAMPLE
BASED ON 0.100mm THICK STENCIL
SCALE: 23X
4220584/A 05/2019
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
PACKAGE OUTLINE
DDF0008A
SOT-23 - 1.1 mm max height
S
C
A
L
E
4
.
0
0
0
PLASTIC SMALL OUTLINE
C
2.95
2.65
SEATING PLANE
TYP
PIN 1 ID
AREA
0.1 C
A
6X 0.65
8
1
2.95
2.85
NOTE 3
2X
1.95
4
5
0.4
0.2
8X
0.1
C A
B
1.65
1.55
B
1.1 MAX
0.20
0.08
TYP
SEE DETAIL A
0.25
GAGE PLANE
0.1
0.0
0 - 8
0.6
0.3
DETAIL A
TYPICAL
4222047/B 11/2015
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
www.ti.com
EXAMPLE BOARD LAYOUT
DDF0008A
SOT-23 - 1.1 mm max height
PLASTIC SMALL OUTLINE
8X (1.05)
SYMM
1
8
8X (0.45)
SYMM
6X (0.65)
5
4
(R0.05)
TYP
(2.6)
LAND PATTERN EXAMPLE
SCALE:15X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4222047/B 11/2015
NOTES: (continued)
4. Publication IPC-7351 may have alternate designs.
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DDF0008A
SOT-23 - 1.1 mm max height
PLASTIC SMALL OUTLINE
8X (1.05)
SYMM
(R0.05) TYP
8
1
8X (0.45)
SYMM
6X (0.65)
5
4
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4222047/B 11/2015
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
SOT-23-THIN - 1.1 mm max height
PLASTIC SMALL OUTLINE
DYY0014A
C
3.36
3.16
SEATING PLANE
PIN 1 INDEX
AREA
A
0.1 C
12X 0.5
14
1
4.3
4.1
NOTE 3
2X
3
7
8
0.31
0.11
14X
0.1
C A
B
1.1 MAX
2.1
1.9
B
0.2
0.08
TYP
SEE DETAIL A
0.25
GAUGE PLANE
0°- 8°
0.1
0.0
0.63
0.33
DETAIL A
TYP
4224643/B 07/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed
0.15 per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.50 per side.
5. Reference JEDEC Registration MO-345, Variation AB
www.ti.com
EXAMPLE BOARD LAYOUT
SOT-23-THIN - 1.1 mm max height
PLASTIC SMALL OUTLINE
DYY0014A
SYMM
14X (1.05)
1
14
14X (0.3)
SYMM
12X (0.5)
8
7
(R0.05) TYP
(3)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 20X
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
METAL
NON- SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4224643/B 07/2021
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
SOT-23-THIN - 1.1 mm max height
PLASTIC SMALL OUTLINE
DYY0014A
SYMM
14X (1.05)
1
14
14X (0.3)
SYMM
12X (0.5)
8
7
(R0.05) TYP
(3)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 20X
4224643/B 07/2021
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
DBV0005A
SOT-23 - 1.45 mm max height
S
C
A
L
E
4
.
0
0
0
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
0.1 C
1.75
1.45
1.45
0.90
B
A
PIN 1
INDEX AREA
1
2
5
2X 0.95
1.9
3.05
2.75
1.9
4
3
0.5
5X
0.3
0.15
0.00
(1.1)
TYP
0.2
C A B
0.25
GAGE PLANE
0.22
0.08
TYP
8
0
TYP
0.6
0.3
TYP
SEATING PLANE
4214839/F 06/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.25 mm per side.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X (0.95)
4
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214839/F 06/2021
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X(0.95)
4
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214839/F 06/2021
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license
is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you
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