TLV9042_V03_技术文档

TLV9042, TLV9044

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SBOS836B – MARCH 2020 – REVISED DECEMBER 2020

TLV904x Micro-power, 1.2-V, RRIO, 350-kHz Operational Amplifier for

Cost-Sensitive Applications

TLV904x achieves excellent balance between

1 Features

performance and power consumption. The device

delivers optimum gain bandwidth, low noise, and high

cap load drive while consuming just 10 µA of

quiescent current. This enables customers to achieve

their desired performance targets and helps them

save valuable battery power. Further power savings

can be achieved from low-voltage operation at 1.2 V

compared to a 1.8-V, 3.3-V, or 5-V operation.

•

Operational from supply voltage as low as 1.2 V

Rail-to-rail input and output

Low quiescent current: 10 µA/ch

High gain bandwidth product: 350 kHz

Low integrated noise of 6.5 µV_p-pin 0.1 Hz –10 Hz

Low input offset voltage: ±0.6 mV

Low input bias current: 1 pA

The robust design of the TLV904x family simplifies

circuit design. These op amps feature rail-to-rail input

and output, unity-gain stability, an integrated RFI and

EMI rejection filter, and has no-phase reversal in

overdrive conditions.

Unity-gain stable

Robustly drives 100 pF of load capacitance

Internal RFI and EMI filtered input pins

Wide specified temperature range: –40°C to 125°C

Low power CMOS amplifier for cost-optimized

applications

The TLV904x devices include a shutdown mode

(TLV9041S, TLV9042S, and TLV9044S) that allow the

amplifiers to switch off and enter into a standby mode

with typical current consumption of less than 150 nA.

2 Applications

•

Portable electronics

Motion detector (PIR, uWave, etc.)

Wearables (non-medical)

Pressure transmitter

Process analytics (pH, gas, concentration, force,

and humidity)

Space saving micro-size packages, such as X2QFN

and WSON, are offered for all channel variants

(single, dual, and quad), along with industry-standard

packages such as SOIC, VSSOP, TSSOP, and

SOT-23 packages.

•

Electronic point of sales (EPOS)

Wearable fitness and activity monitor

Headsets/headphones and earbuds

Personal electronics

Building automation

Single-supply, low-side, unidirectional current-

sensing circuit

Device Information

PART NUMBER^{(1) (2)}

PACKAGE

BODY SIZE (NOM)

3.91 mm × 4.90 mm

1.60 mm × 2.90 mm

2.00 mm × 2.00 mm

3.00 mm × 3.00 mm

3.00 mm × 4.40 mm

1.50 mm × 2.00 mm

8.65 mm × 3.91 mm

4.40 mm × 5.00 mm

SOIC (8)

SOT-23 (8)

WSON (8)

VSSOP (8)

TSSOP (8)

X2QFN (10)

SOIC (14)

TLV9042

TLV9042S

TLV9044

3 Description

The low-power TLV904x family includes single

(TLV9041), dual (TLV9042), and quad-channel

(TLV9044) ultra low-voltage (1.2 V to 5.5 V)

operational amplifiers (op amps) with rail-to-rail input

and output swing capabilities. These op amps provide

a cost-effective solution for power and space-

constrained applications such as battery powered IoT

devices, wearable electronics, and personal

electronics where low-voltage operation is usually

desired. TLV904x is one of the few op amp families in

the industry that enables 1.5-V coin cell battery

powered applications.

TSSOP (14)

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

(2) Other single and dual channel package variants will release

shortly.

Single-Pole, Low-Pass Filter

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

Product Folder Links: TLV9042 TLV9044

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TLV9042, TLV9044

SBOS836B – MARCH 2020 – REVISED DECEMBER 2020

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Table of Contents

1 Features............................................................................1

2 Applications.....................................................................1

3 Description.......................................................................1

4 Revision History.............................................................. 2

5 Device Comparison Table...............................................3

6 Pin Configuration and Functions...................................3

7 Specifications.................................................................. 6

7.1 Absolute Maximum Ratings ....................................... 6

7.2 ESD Ratings .............................................................. 6

7.3 Recommended Operating Conditions ........................6

7.4 Thermal Information for Dual Channel .......................6

7.5 Thermal Information for Quad Channel ..................... 7

7.6 Electrical Characteristics ............................................8

7.7 Typical Characteristics.............................................. 11

8 Detailed Description......................................................19

8.1 Overview...................................................................19

8.2 Functional Block Diagram.........................................19

8.3 Feature Description...................................................20

8.4 Device Functional Modes..........................................23

9 Application and Implementation..................................24

9.1 Application Information............................................. 24

9.2 Typical Application.................................................... 24

10 Power Supply Recommendations..............................27

11 Layout...........................................................................28

11.1 Layout Guidelines................................................... 28

11.2 Layout Example...................................................... 28

12 Device and Documentation Support..........................30

12.1 Documentation Support.......................................... 30

12.2 Receiving Notification of Documentation Updates..30

12.3 Support Resources................................................. 30

12.4 Trademarks.............................................................30

12.5 Electrostatic Discharge Caution..............................30

12.6 Glossary..................................................................30

13 Mechanical, Packaging, and Orderable

Information.................................................................... 30

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision A (October 2020) to Revision B (December 2020)

Page

•

Updated the numbering format for tables, figures, and cross-references throughout the document..................1

Updated Device Information table to add TLV9044............................................................................................1

Updated Device Comparison section to add TLV9044.......................................................................................3

Updated Pin Configuration and Functions section to add TLV9044 pin diagrams..............................................3

Added Thermal Information for TLV9044 D and PW packages to the Specifications section............................ 6

Updated the Noise and Power Supply sections of the Electrical Characteristics table ..................................... 6

Deleted the Related Links section.................................................................................................................... 30

Changes from Revision * (March 2020) to Revision A (October 2020)

Page

•

Changed device status from Advance Information to Production Data.............................................................. 1

2

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5 Device Comparison Table

PACKAGE LEADS

NO. OF

DEVICE

SC70

SOIC

D

SOT-23

DBV⁽¹⁾

SOT-23-8 SOT-553 TSSOP VSSOP WQFN WSON

X2QFN X2SON

X2QFN

RUG

CHANNELS

DCK⁽¹⁾

DDF

DRL⁽¹⁾

PW

DGK

RTE⁽¹⁾

DSG

RUC⁽¹⁾

DPW⁽¹⁾

TLV9042

TLV9042S

TLV9044

2

4

—

8

—

8

—

8

—

8

—

10

—

14

—

14

—

16

—

14

—

(1) Package is preview only.

6 Pin Configuration and Functions

OUT1

IN1œ

IN1+

Vœ

1

2

3

4

8

7

6

5

V+

OUT1

IN1œ

IN1+

Vœ

1

2

3

4

8

7

6

5

V+

OUT2

IN2œ

IN2+

OUT2

IN2œ

IN2+

Thermal

Pad

Not to scale

Figure 6-1. TLV9042 D, DDF, DGK, PW Packages

8-Pin SOIC, SOT-23 8, VSSOP, TSSOP

Top View

Connect exposed thermal pad to V–. See Section 8.3.11 for

more information.

Figure 6-2. TLV9042 DSG Package

8-Pin WSON With Exposed Thermal Pad

Top View

Table 6-1. Pin Functions: TLV9042

I/O

DESCRIPTION

NAME

IN1–

NO.

2

I

Inverting input, channel 1

Noninverting input, channel 1

Inverting input, channel 2

Noninverting input, channel 2

Output, channel 1

IN1+

IN2–

IN2+

OUT1

OUT2

V–

3

6

I

5

I

1

O

I

7

Output, channel 2

4

Negative (low) supply or ground (for single-supply operation)

Positive (high) supply

V+

8

I

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Vœ

1

2

3

4

9

8

7

6

IN1œ

OUT1

V+

SHDN1

SHDN2

IN2+

OUT2

Not to scale

Figure 6-3. TLV9042S RUG Package

10-Pin X2QFN

Top View

Table 6-2. Pin Functions: TLV9042S

I/O

DESCRIPTION

NAME

IN1–

NO.

9

I

Inverting input, channel 1

IN1+

IN2–

10

5

Noninverting input, channel 1

I

Inverting input, channel 2

IN2+

OUT1

OUT2

SHDN1

SHDN2

V–

4

I

Noninverting input, channel 2

8

O

I

Output, channel 1

6

Output, channel 2

2

Shutdown – low = disabled, high = enabled, channel 1

Shutdown – low = disabled, high = enabled, channel 2

Negative (low) supply or ground (for single-supply operation)

Positive (high) supply

3

I

1

I

V+

7

I

4

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OUT1

IN1œ

IN1+

V+

1

2

3

4

5

6

7

14

13

12

11

10

9

OUT4

IN4œ

IN4+

Vœ

IN2+

IN2œ

OUT2

IN3+

IN3œ

OUT3

8

Not to scale

Figure 6-4. TLV9044 D, PW Packages

14-Pin SOIC, TSSOP

Top View

Table 6-3. Pin Functions: TLV9044

I/O

DESCRIPTION

NAME

IN1–

IN1+

IN2–

IN2+

IN3–

IN3+

IN4–

IN4+

NC

NO.

2

I

Inverting input, channel 1

Noninverting input, channel 1

Inverting input, channel 2

Noninverting input, channel 2

Inverting input, channel 3

Noninverting input, channel 3

Inverting input, channel 4

Noninverting input, channel 4

No internal connection

3

I

6

I

5

I

9

I

10

13

12

—

1

I

—

O

OUT1

OUT2

OUT3

OUT4

V–

Output, channel 1

7

O

Output, channel 2

8

O

Output, channel 3

14

11

4

O

Output, channel 4

I or —

I

Negative (low) supply or ground (for single-supply operation)

Positive (high) supply

V+

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7 Specifications

7.1 Absolute Maximum Ratings

over operating ambient temperature range (unless otherwise noted) ⁽¹⁾

MIN

0

MAX

6.0

UNIT

V

Supply voltage, V_S= (V+) – (V–)

Common-mode voltage ⁽²⁾

(V–) – 0.5

(V+) + 0.5

V_S+ 0.2

10

V

Signal input pins

Differential voltage ⁽²⁾

Current ⁽²⁾

V

–10

–55

–65

mA

Output short-circuit ⁽³⁾

Continuous

Operating ambient temperature, T_A

Junction temperature, T_J

150

°C

Storage temperature, T_stg

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under

Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device

reliability.

(2) Input pins are diode-clamped to the power-supply rails. Input signals that may swing more than 0.5 V beyond the supply rails must be

current limited to 10 mA or less.

(3) Short-circuit to ground, one amplifier per package.

7.2 ESD Ratings

VALUE

±3000

±1500

UNIT

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 ⁽¹⁾

V_(ESD)

Electrostatic discharge

V

Charged-device model (CDM), per JEDEC specification JESD22-C101 ⁽²⁾

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating ambient temperature range (unless otherwise noted)

MIN

1.2

MAX

UNIT

V

V_S

V_I

Supply voltage, (V+) – (V–)

Input voltage range

5.5

(V+)

125

(V–)

–40

V

T_A

Specified temperature

°C

7.4 Thermal Information for Dual Channel

TLV9042, TLV9042S

D

THERMAL METRIC ⁽¹⁾

(SOIC)

DDF

(SOT-23-8)

DSG

(WSON)

PW

(TSSOP)

RUG

(X2QFN)

UNIT

8 PINS

10 PINS

Junction-to-ambient thermal

resistance

R_θJA

R_θJC(top)

R_θJB

ψ_JT

148.3

89.8

91.6

38.6

90.9

203.8

99.8

203.1

91.9

196.9

°C/W

Junction-to-case (top) thermal

resistance

123.9

121.6

21.7

122.2

66.0

13.8

65.9

87.6

117.8

3.4

Junction-to-board thermal

resistance

133.8

23.7

Junction-to-top characterization

parameter

Junction-to-board

characterization parameter

ψ_JB

199.6

132.1

117.6

6

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7.4 Thermal Information for Dual Channel (continued)

TLV9042, TLV9042S

D

DDF

(SOT-23-8)

DSG

(WSON)

PW

(TSSOP)

RUG

(X2QFN)

THERMAL METRIC ⁽¹⁾

UNIT

(SOIC)

8 PINS

10 PINS

Junction-to-case (bottom)

thermal resistance

R_θJC(bot)

n/a

41.9

n/a

°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report, SPRA953.

7.5 Thermal Information for Quad Channel

TLV9044, TLV9044S

D

PW

(TSSOP)

THERMAL METRIC ⁽¹⁾

UNIT

(SOIC)

14 PINS

116.4

72.5

72.4

30.8

72

14 PINS

135.7

78.8

R_θJA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

°C/W

R_θJC(top)

R_θJB

°C/W

63.9

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

14.2

ψ_JB

78.3

R_θJC(bot)

n/a

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report, SPRA953.

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7.6 Electrical Characteristics

For V_S= (V+) – (V–) = 1.2 V to 5.5 V (±0.6 V to ±2.75 V) at T_A= 25°C, R_L= 100 kΩ connected to V_S/ 2, V_CM= V_S/ 2, and

V_{O UT}= V_S/ 2, unless otherwise noted.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

OFFSET VOLTAGE

±0.6

±2.25

±2.5

V_OS

Input offset voltage

mV

T_A= –40°C to

125°C

Input offset voltage

drift

T_A= –40°C to

125°C

dV_OS/dT

PSRR

±0.8

µV/℃

Input offset voltage

versus power

supply

V_S= ±0.6 V to ±2.75 V , V_CM= V–

±20

±100

µV/V

Channel separation f = 10 kHz

INPUT BIAS CURRENT

±5.6

I_B

Input bias current ⁽¹⁾

±1

±50

±30

pA

Input offset current

I_OS

±0.5

(1)

NOISE

E_N

Input voltage noise f = 0.1 to 10 Hz

f = 100 Hz

6.5

85

66

64

μV_PP

Input voltage noise

density

e_N

f = 1 kHz

nV/√Hz

f = 10 kHz

Input current noise

i_N

f = 1 kHz

20

fA/√Hz

V

(2)

INPUT VOLTAGE RANGE

Common-mode

V_CM

(V–)

(V+)

voltage range

(V–) < V_CM< (V+) – 0.7 V, V_S= 1.2 V

(V–) < V_CM< (V+) – 0.7 V, V_S= 5.5 V

(V–) < V_CM< (V+), V_S= 1.2 V

60

75

77

89

60

72

Common-mode

CMRR

T_A= –40°C to

125°C

dB

rejection ratio

(V–) < V_CM< (V+), V_S= 5.5 V

57

INPUT IMPEDANCE

Z_ID

Differential

80 || 1.4

GΩ || pF

Z_ICM

Common-mode

100 || 0.5

OPEN-LOOP GAIN

V_S= 1.2 V, (V–) + 0.2 V < V_O< (V+) – 0.2 V,

R_L= 10 kΩ to V_S/ 2

98

125

105

130

V_S= 5.5 V, (V–) + 0.2 V < V_O< (V+) – 0.2 V,

R_L= 10 kΩ to V_S/ 2

Open-loop voltage

gain

T_A= –40°C to

125°C

A_OL

dB

V_S= 1.2 V, (V–) + 0.1 V < V_O< (V+) – 0.1 V,

R_L= 100 kΩ to V_S/ 2

V_S= 5.5 V, (V–) + 0.1 V < V_O< (V+) – 0.1 V,

R_L= 100 kΩ to V_S/ 2

107

FREQUENCY RESPONSE

Total harmonic

THD+N

V_S= 5.5 V, V_CM= 2.75 V, V_O= 1 V_RMS, G = +1, f = 1 kHz,

0.013

%

distortion + noise ⁽³⁾R_L= 100 kΩ to V_S/ 2

Gain-bandwidth

product

GBW

SR

R_L= 1 MΩ connected to V_S/2

V_S= 5.5 V, G = +1, C_L= 10 pF

350

0.2

kHz

Slew rate

V/μs

8

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7.6 Electrical Characteristics (continued)

For V_S= (V+) – (V–) = 1.2 V to 5.5 V (±0.6 V to ±2.75 V) at T_A= 25°C, R_L= 100 kΩ connected to V_S/ 2, V_CM= V_S/ 2, and

V_{O UT}= V_S/ 2, unless otherwise noted.

PARAMETER

Settling time

Phase margin

TEST CONDITIONS

MIN

TYP

MAX

UNIT

To 0.1%, V_S= 5.5 V, V_STEP= 4 V, G = +1, C_L= 10 pF

To 0.1%, V_S= 5.5 V, V_STEP= 2 V, G = +1, C_L= 10 pF

To 0.01%, V_S= 5.5 V, V_STEP= 4 V, G = +1, C_L= 10 pF

To 0.01%, V_S= 5.5 V, V_STEP= 2 V, G = +1, C_L= 10 pF

G = +1, R_L= 100 kΩ connected to V_S/2, C_L= 10 pF

25

22

t_S

μs

35

30

65

°

Overload recovery

time

V_IN× gain > V_S

13

70

μs

Electro-magnetic

interference

EMIRR

f = 1 GHz, V_{IN_EMIRR}= 100 mV

dB

rejection ratio

OUTPUT

V_S= 1.2 V,

R_L= 100 kΩ to

V_S/ 2

0.75

10

1

7

21

8

V_S= 5.5 V,

R_L= 10 kΩ to

V_S/ 2

Positive rail headroom

V_S= 5.5 V,

R_L= 100 kΩ to

V_S/ 2

Voltage output

swing from rail

mV

V_S= 1.2 V,

R_L= 100 kΩ to

V_S/ 2

0.75

10

1

5

V_S= 5.5 V,

R_L= 10 kΩ to

V_S/ 2

Negative rail headroom

21

8

V_S= 5.5 V,

R_L= 100 kΩ to

V_S/ 2

Short-circuit current

I_SC

Z_O

V_S= 5.5 V

f = 10 kHz

±40

mA

Ω

(4)

Open-loop output

impedance

7500

POWER SUPPLY

10

13

Quiescent current

per amplifier

I_Q

V_S= 5.5 V, I_O= 0 A

µA

T_A= –40°C to

125°C

13.5

SHUTDOWN

Quiescent current

per amplifier

I_QSD

All amplifiers disabled, SHDN = V–

Amplifier disabled

75

200

nA

Output impedance

during shutdown

Z_SHDN

43 || 11.5

GΩ || pF

Logic high threshold

voltage (amplifier

enabled)

(V–) + 1

V

V_IH

V

Logic low threshold

voltage (amplifier

disabled)

(V–) +

0.2 V

V_IL

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7.6 Electrical Characteristics (continued)

For V_S= (V+) – (V–) = 1.2 V to 5.5 V (±0.6 V to ±2.75 V) at T_A= 25°C, R_L= 100 kΩ connected to V_S/ 2, V_CM= V_S/ 2, and

V_{O UT}= V_S/ 2, unless otherwise noted.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Amplifier enable

time (full shutdown) G = +1, V_CM= V_S/ 2, V_O= 0.9 × V_S/ 2, R_Lconnected to V–

160

(5) (6)

t_ON

µs

Amplifier enable

time (partial

G = +1, V_CM= V_S/ 2, V_O= 0.9 × V_S/ 2, R_Lconnected to V–

G = +1, V_CM= V_S/ 2, V_O= 0.1 × V_S/ 2, R_Lconnected to V–

120

10

shutdown) ^{(5) (6)}

Amplifier disable

time ⁽⁵⁾

t_OFF

µs

(V+) ≥ SHDN ≥ (V–) + 1 V

(V–) ≤ SHDN ≤ (V–) + 0.2 V

100

50

SHDN pin input bias

current (per pin)

pA

(1) Max I_Band I_OSlimits are specified based on characterization results. Input differential voltages greater than 2.5V can cause increased

I_B

(2) Typical input current noise data is specified based on design simulation results

(3) Third-order filter; bandwidth = 80 kHz at –3 dB.

(4) Short circuit current is average of sourcing and sinking short circuit currents

(5) Disable time (t_OFF) and enable time (t_ON) are defined as the time interval between the 50% point of the signal applied to the SHDN pin

and the point at which the output voltage reaches the 10% (disable) or 90% (enable) level.

(6) Full shutdown refers to the dual TLV9042S having both channels 1 and 2 disabled (SHDN1 = SHDN2 = V–) and the quad TLV9044S

having all channels 1 to 4 disabled (SHDN12 = SHDN34 = V–). For partial shutdown, only one SHDN pin is exercised; in this mode,

the internal biasing circuitry remains operational and the enable time is shorter.

10

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7.7 Typical Characteristics

at T_A= 25°C, V+ = 2.75 V, V– = –2.75 V, R_L= 10 kΩ connected to V_S/ 2, V_CM= V_S/ 2, and V_OUT= V_S/ 2 (unless otherwise

noted)

45

40

35

30

25

20

15

10

5

20

18

16

14

12

10

8

6

4

2

0

-2 -1.6 -1.2 -0.8 -0.4

0

0.4 0.8 1.2 1.6

2

0.2 0.4 0.6 0.8

1

1.2 1.4 1.6 1.8

2

2.2

D01_

D04_

Offset Voltage (mV)

Offset Voltage Drift (µV/°C)

V_S= 5.5 V

V_S= 5.5 V, T_A= –40°C to +125°C

Figure 7-1. Offset Voltage Distribution Histogram

Figure 7-2. Offset Voltage Drift Distribution Histogram

1600

2000

1600

1200

800

1200

800

400

0

-400

-800

-1200

-1600

-2000

-400

-800

-1200

-1600

-40

-20

0

20

40 60

Temperature (°C)

80

100 120 140

-40

-20

0

20

40 60

Temperature (°C)

80

100 120 140

D06_

D05_

V_S= 5.5 V, V_CM= V–

Figure 7-3. Input Offset Voltage vs Temperature

V_S= 5.5 V, V_CM= V+

Figure 7-4. Input Offset Voltage vs Temperature

2000

1600

1200

800

1600

1200

800

400

0

-400

-800

-1200

-1600

-2000

-400

-800

-1200

-1600

-2000

-3 -2.5 -2 -1.5 -1 -0.5 0 0.5

V_CM(V)

1

1.5

2

2.5

3

1.25

1.5

1.75

2

2.25

2.5

2.75

3

V_CM(V)

D07_

D09_

V_CM> (V+) – 1.4 V

Figure 7-6. Offset Voltage vs Common-Mode

Figure 7-5. Offset Voltage vs Common-Mode

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7.7 Typical Characteristics (continued)

at T_A= 25°C, V+ = 2.75 V, V– = –2.75 V, R_L= 10 kΩ connected to V_S/ 2, V_CM= V_S/ 2, and V_OUT= V_S/ 2 (unless otherwise

noted)

1200

24

22

20

18

16

14

12

10

8

I_B-

I_B+

I_OS

800

400

0

-400

-800

-1200

6

4

2

0

-40

1

1.5

2

2.5

3

3.5

4

Supply Voltage (V)

4.5

5

5.5

6

-20

0

20

40 60

Temperature (°C)

80

100 120 140

D51_

D14_

V_CM= (V–)

Figure 7-7. Offset Voltage vs Supply Voltage

Figure 7-8. I_Band I_OSvs Temperature

1.8

1.2

0.6

0

150

140

130

120

110

100

90

-0.6

-1.2

-1.8

-2.4

-3

80

V_S= 5.5 V, R_L= 100KW

70

I_B-

I_B+

I_OS

V_S= 1.2 V, R_L= 100KW

V_S= 1.2 V, R_L= 10KW

V_S= 5.5 V, R_L= 10KW

60

-3.6

50

-3 -2.5 -2 -1.5 -1 -0.5

0

Common-Mode Voltage (V)

0.5

1

1.5

2

2.5

3

-40

-20

0

20

40 60

Temperature (°C)

80

100 120 140

D13_

D18_

Figure 7-9. I_Band I_OSvs Common-Mode Voltage

Figure 7-10. Open-Loop Gain vs Temperature

75

60

45

30

15

0

100

80

9000

8000

7000

6000

5000

4000

3000

2000

1000

0

60

40

20

0

-15

-30

-45

-20

-40

-60

Gain

Phase

100

1k

10k

Frequency (Hz)

100k

1M

100

1k

10k 100k

Frequency (Hz)

1M

10M

D16_

D41_

C_L= 10 pF

Figure 7-11. Open-Loop Gain and Phase vs Frequency

Figure 7-12. Open-Loop Output Impedance vs Frequency

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7.7 Typical Characteristics (continued)

at T_A= 25°C, V+ = 2.75 V, V– = –2.75 V, R_L= 10 kΩ connected to V_S/ 2, V_CM= V_S/ 2, and V_OUT= V_S/ 2 (unless otherwise

noted)

160

150

140

130

120

110

100

90

80

70

60

50

30

20

10

0

-10

-20

-30

-40

-50

-60

-70

-40^oC

25^oC

125^oC

40

30

20

10

G = -1

G = 1

G = 10

0

-3 -2.5 -2 -1.5 -1 -0.5

0

Output Voltage (V)

0.5

1

1.5

2

2.5

3

10k

100k

Frequency (Hz)

1M

D19_

D17_

V+ = 2.75 V, V– = –2.75 V

R_L= 10 kΩ

C_L= 10 pF

Figure 7-13. Open-Loop Gain vs Output Voltage

Figure 7-14. Closed-Loop Gain vs Frequency

3

0.75

0.5

2.5

2

1.5

1

0.25

0

-40^oC

25^oC

85^oC

125^oC

-40^oC

25^oC

85^oC

125^oC

0.5

0

-0.5

-1

-0.25

-0.5

-0.75

-1.5

-2

-2.5

-3

0

0.25

0.5

0.75

1

Iout (mA)

1.25

1.5

1.75

2

0

5

10 15 20 25 30 35 40 45 50 55 60

Iout (mA)

D34_

D32_

V+ = 0.6 V, V– = –0.6 V

V+ = 2.75 V, V– = –2.75 V

Figure 7-16. Output Voltage vs Output Current (Claw)

Figure 7-15. Output Voltage vs Output Current (Claw)

80

40

36

32

28

24

20

16

12

8

PSRR+

PSRR-

72

64

56

48

40

32

24

16

8

4

0

100

1k

10k 100k

Frequency (Hz)

1M

-40

-20

0

20

40 60

Temperature (°C)

80

100 120 140

D10_

D11_

V_S= 1.2 V to 5.5 V

Figure 7-18. DC PSRR vs Temperature

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Figure 7-17. PSRR vs Frequency

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7.7 Typical Characteristics (continued)

at T_A= 25°C, V+ = 2.75 V, V– = –2.75 V, R_L= 10 kΩ connected to V_S/ 2, V_CM= V_S/ 2, and V_OUT= V_S/ 2 (unless otherwise

noted)

100

90

80

70

60

50

40

30

20

10

0

95

90

85

80

75

70

65

CMRR

V_S= 5.5 V;V_CM= 0 V to 4.7 V

V_S= 3.3 V;V_CM= 0 V to 2.6 V

V_S= 1.8 V;V_CM= 0 V to 1.1 V

V_S= 1.2 V;V_CM= 0 V to 0.5 V

100

1k

10k 100k

Frequency (Hz)

1M

10M

-40

-20

0

20

40 60

Temperature (°C)

80

100 120 140

D010

D12_

D15_

D30_

Figure 7-19. CMRR vs Frequency

Figure 7-20. DC CMRR vs Temperature

4

3

200

180

160

140

120

100

80

2

1

0

-1

-2

-3

-4

60

40

20

0

10

100

1k

Frequency (Hz)

10k

Time (1s/div)

D011

Figure 7-22. Input Voltage Noise Spectral Density

Figure 7-21. 0.1 Hz to 10 Hz Voltage Noise in Time Domain

0

R_L= 10 kW

R_L= 100 kW

R_L= 10 kW

R_L= 100 kW

-10

-20

-30

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-100

-110

100

1k

Frequency (Hz)

10k

100

1k

Frequency (Hz)

10k

D30_

V_S= 5.5 V

V_CM= 2.5 V

V_OUT= 0.5 V_RMS

G = 1

V_S= 5.5 V

V_CM= 2.5 V

V_OUT= 0.5 V_RMS

G = –1

BW = 80 kHz

Figure 7-23. THD + N vs Frequency

Figure 7-24. THD + N vs Frequency

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7.7 Typical Characteristics (continued)

at T_A= 25°C, V+ = 2.75 V, V– = –2.75 V, R_L= 10 kΩ connected to V_S/ 2, V_CM= V_S/ 2, and V_OUT= V_S/ 2 (unless otherwise

noted)

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

R_L= 10 kW

R_L= 100 kW

R_L= 10 kW

R_L= 100 kW

1m

10m

100m

Amplitude(Vrms)

1

1m

10m

100m

Amplitude(Vrms)

1

D31_

V_S= 5.5 V

G = 1

V_CM= 2.5 V

f = 1 kHz

V_S= 5.5 V

G = –1

V_CM= 2.5 V

f = 1 kHz

BW = 80 kHz

Figure 7-25. THD + N vs Amplitude

Figure 7-26. THD + N vs Amplitude

11

10.5

10

9.5

9

11

10.5

10

9.5

9

V_S= 5.5 V

V_S= 1.2 V

8.5

8

8.5

8

7.5

7

7.5

7

6.5

6

6.5

6

1

1.5

2

2.5

3

3.5

4

Supply Voltage (V)

4.5

5

5.5

6

-40

-20

0

20

40 60

Temperature (°C)

80

100 120 140

D38_

D40_

Figure 7-27. Quiescent Current vs Supply Voltage

70

Figure 7-28. Quiescent Current vs Temperature

70

60

50

40

30

20

10

0

R_ISO= 0W , Overshoot (+)

R_ISO= 0W ,Overshoot (-)

R_ISO= 50W , Overshoot (+)

R_ISO= 50W ,Overshoot (-)

R_ISO= 0W , Overshoot (+)

R_ISO= 0W ,Overshoot (-)

R_ISO= 50W , Overshoot (+)

R_ISO= 50W ,Overshoot (-)

60

50

40

30

20

10

0

80

160

240 320

Capacitive Load (pF)

400

480

560

0

80

160

240 320

Capacitive Load (pF)

400

480

560

D23_

D24_

G = 1

V_IN= 100 mVpp

G = –1

V_IN= 100 mVpp

Figure 7-29. Small Signal Overshoot vs Capacitive Load

Figure 7-30. Small Signal Overshoot vs Capacitive Load

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7.7 Typical Characteristics (continued)

at T_A= 25°C, V+ = 2.75 V, V– = –2.75 V, R_L= 10 kΩ connected to V_S/ 2, V_CM= V_S/ 2, and V_OUT= V_S/ 2 (unless otherwise

noted)

72

68

64

60

56

52

48

44

40

36

3

2.4

1.8

1.2

0.6

0

V_IN

V_OUT

-0.6

-1.2

-1.8

-2.4

-3

10

30

50

70 90

Capacitive Load (pF)

110

130

150

Time (25 µs/div)

D005

D21_

G = 1

V_IN= 6 V_PP

Figure 7-31. Phase Margin vs Capacitive Load

Figure 7-32. No Phase Reversal

3

2

12.5

10

V_IN

V_OUT

7.5

5

1

2.5

0

-2.5

-5

-1

-2

-3

-7.5

-10

-12.5

V_IN

V_OUT

Time (100 µs/div)

Time (10 µs/div)

D22_

D25_

G = –10

V_IN= 600 mV_PP

G = 1

V_IN= 20 mV_PP

C_L= 10 pF

Figure 7-33. Overload Recovery

Figure 7-34. Small-Signal Step Response

2.5

2

V_IN

V_OUT

1.5

1

0.5

0

-0.5

-1

-1.5

-2

-2.5

Time (5 µs/div)

Time (10 µs/div)

D29_

D27_

G = 1

V_IN= 4 V_PP

C_L= 10 pF

G = 1

V_IN= 4 V_PP

C_L= 10 pF

Figure 7-36. Large-Signal Settling Time (Negative)

Figure 7-35. Large-Signal Step Response

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7.7 Typical Characteristics (continued)

at T_A= 25°C, V+ = 2.75 V, V– = –2.75 V, R_L= 10 kΩ connected to V_S/ 2, V_CM= V_S/ 2, and V_OUT= V_S/ 2 (unless otherwise

noted)

2.5

2

1.5

V_IN

V_OUT

1

0.5

0

-0.5

-1

-1.5

-2

-2.5

Time (10 µs/div)

Time (5 µs/div)

D28_

D29_

G = –1

V_IN= 4 V_PP

C_L= 10 pF

G = 1

V_IN= 4 V_PP

C_L= 10 pF

Figure 7-37. Large-Signal Settling Time (Positive)

Figure 7-38. Large-Signal Step Response

6

80

V_s= 5.5 V

V_s= 1.2 V

Sinking

Sourcing

5.4

60

40

4.8

4.2

3.6

3

20

0

2.4

1.8

1.2

0.6

0

-20

-40

-60

-80

1

10

100

1k

10k

Frequency (Hz)

100k

1M

10M 100M

-40

-20

0

20

40 60

Temperature (°C)

80

100 120 140

D36_

D37_

Figure 7-39. Maximum Output Voltage vs Frequency

Figure 7-40. Short-Circuit Current vs Temperature

100

90

80

70

60

50

40

30

20

10

0

140

V_s= 5.5 V

V_s= 1.2 V

120

100

80

60

40

20

0

1

1.5

2

2.5

3

Supply Voltage (V)

3.5

4

4.5

5

5.5

6

-40

-20

0

20

40 60

Temperature (°C)

80

100 120 140

D44_

D45_

Figure 7-41. Shutdown Mode Quiescent Current vs Supply

Voltage

Figure 7-42. Shutdown Mode Quiescent Current vs Temperature

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7.7 Typical Characteristics (continued)

at T_A= 25°C, V+ = 2.75 V, V– = –2.75 V, R_L= 10 kΩ connected to V_S/ 2, V_CM= V_S/ 2, and V_OUT= V_S/ 2 (unless otherwise

noted)

1

0.5

0

1

0.5

0

V_OUT(V)

SHDN (V)

V_OUT(V)

SHDN (V)

-0.5

-1

-0.5

-1

-1.5

-2

-1.5

-2

-2.5

-3

-2.5

-3

Time (20 µs/div)

D49_

D48_

Figure 7-43. Amplifier Enable Response

Figure 7-44. Amplifier Disable Response

100

90

80

70

60

50

40

30

20

10

0

-20

-40

-60

-80

-100

-120

-140

100

1k

10k 100k

Frequency (Hz)

1M

10M

1M

10M

100M

Frequency (Hz)

1G

D50_

D42_

Figure 7-46. Channel Separation

Figure 7-45. Electromagnetic Interference Rejection Ratio

Referred to Noninverting Input (EMIRR+) vs Frequency

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8 Detailed Description

8.1 Overview

The TLV904x is a family of low-power, rail-to-rail input and output operational amplifiers specifically designed for

battery powered applications. This family of amplifiers utilizes unique transistors that enable operation from ultra

low supply voltage of 1.2 V to a standard supply voltage of 5.5 V. These unity-gain stable amplifiers provide 350

kHz of GBW with an I_Qof only 10 µA. TLV904x also has short circuit current capability of 40 mA at 5.5 V. This

combination of low voltage, low IQ, and high output current capability makes this device quite unique and

suitable for suitable for a wide range of general-purpose applications. The input common-mode voltage range

includes both rails, and allows the TLV904x series to be used in many single-supply or dual supply

configurations. Rail-to-rail input and output swing significantly increases dynamic range, especially in low-supply

applications, and makes these devices ideal for driving low speed sampling analog-to-digital converters (ADCs).

Further, the class AB output stage is capable of driving resitive loads greater than 2-kΩ connected to any point

between V+ and ground.

The TLV904x can drive up to 100 pF with a typical phase margin of 45° and features 350-kHz gain bandwidth

product, 0.2-V/μs slew rate with 6.5-μV_p-pintegrated noise (0.1 to 10 Hz) while consuming only 10-μA supply

current per channel, thus providing a good AC performance at a very low power consumption. DC applications

are also well served with a low input bias current of 1 pA (typical), an input offset voltage of 0.6 mV (typical) and

a good PSRR, CMRR, and A_OL

.

8.2 Functional Block Diagram

V+

Reference

Current

V_IN+

V_IN-

V_BIAS1

Class AB

Control

Circuitry

V_O

V_BIAS2

V-

(Ground)

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8.3 Feature Description

8.3.1 Operating Voltage

The TLV904x series of operational amplifiers is fully specified and ensured for operation from 1.2 V to 5.5 V. In

addition, many specifications apply from –40°C to 125°C. Parameters that vary significantly with operating

voltages or temperature are provided in Section 7.7. It is highly recommended to bypass power-supply pins with

at least 0.01-μF ceramic capacitors.

8.3.2 Rail-to-Rail Input

The input common-mode voltage range of the TLV904x series includes the supply rails even from the ultra-low

supply voltage of 1.2 V all the way upto the standard supply voltage of 5.5 V. This performance is achieved with

a complementary input stage: an N-channel input differential pair in parallel with a P-channel differential pair; see

the Section 8.2. The N-channel pair is active for input voltages from the positive rail to typically, (V+) – 0.4 V and

the P-channel pair is active for input voltages from the negative supply to typically, (V+) – 0.4 V. There is a small

transition region, typically (V+) – 0.5 V to (V+) – 0.3 V, in which both pairs are on. This 200-mV transition region

can vary up to 200 mV on either direction with process variation. Thus, the transition region (both stages on) can

range from (V+) – 0.7 V to (V+) – 0.5 V on the low end, up to (V+) – 0.3 V to (V+) – 0.1 V on the high end. Within

this transition region, PSRR, CMRR, offset voltage, offset drift, and THD can be degraded compared to device

operation outside this region.

8.3.3 Rail-to-Rail Output

Designed as a micro-power, low-noise operational amplifier, the TLV904x delivers a robust output drive

capability. A class AB output stage with common-source transistors is used to achieve full rail-to-rail output swing

capability. For resistive loads up to 5 kΩ, the output typically swings to within 20 mV of either supply rail

regardless of the power-supply voltage applied. Different load conditions change the ability of the amplifier to

swing close to the rails.

8.3.4 Common-Mode Rejection Ratio (CMRR)

The CMRR for the TLV904x is specified in several ways so the best match for a given application can be used;

see the Electrical Characteristics table. First, the CMRR of the device in the common-mode range below the

transition region [VCM < (V+) – 0.7 V] is given. This specification is the best indicator of the capability of the

device when the application requires using one of the differential input pairs. Second, the CMRR over the entire

common-mode range is specified at (VCM = 0 V to 5.5 V). This last value includes the variations measured

through the transition region.

8.3.5 Capacitive Load and Stability

The TLV904x is designed to be used in applications where driving a capacitive load is required. As with all

operational amplifiers, there may be specific instances where the TLV904x can become unstable. The particular

operational amplifier circuit configuration, layout, gain, and output loading are some of the factors to consider

when establishing whether or not an amplifier is stable in operation. An operational amplifier in the unity-gain (1

V/V) buffer configuration that drives a capacitive load exhibits a greater tendency to be unstable than an

amplifier operated at a higher noise gain. The capacitive load, in conjunction with the operational amplifier output

resistance, creates a pole within the feedback loop that degrades the phase margin. The degradation of the

phase margin increases when capacitive loading increases. When operating in the unity-gain configuration, the

TLV904x remains stable with a pure capacitive load up to approximately 100 pF with a good phase margin of 45°

typical. The equivalent series resistance (ESR) of some very large capacitors (C_Lgreater than 1 μF) is sufficient

to alter the phase characteristics in the feedback loop such that the amplifier remains stable. Increasing the

amplifier closed-loop gain allows the amplifier to drive increasingly larger capacitance. This increased capability

is evident when measuring the overshoot response of the amplifier at higher voltage gains.

One technique for increasing the capacitive load drive capability of the amplifier operating in a unity-gain

configuration is to insert a small resistor (typically 10 Ω to 20 Ω) in series with the output, as shown in Figure 8-1.

This resistor significantly reduces the overshoot and ringing associated with large capacitive loads. One possible

problem with this technique, however, is that a voltage divider is created with the added series resistor and any

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resistor connected in parallel with the capacitive load. The voltage divider introduces a gain error at the output

that reduces the output swing.

+V_s

V_out

R_iso

+

C_load

+

V_in

-V_s

œ

Figure 8-1. Improving Capacitive Load Drive

8.3.6 Overload Recovery

Overload recovery is defined as the time required for the operational amplifier output to recover from a saturated

state to a linear state. The output devices of the operational amplifier enter a saturation region when the output

voltage exceeds the rated operating voltage, because of the high input voltage or high gain. Once one of the

output devices enters the saturation region, the output stage requires additional time to return to the linear

operating state which is referred to as overload recovery time. After the output stage returns to its linear

operating state, the amplifier begins to slew at the specified slew rate. Therefore, the propagation delay (in case

of an overload condition) is the sum of the overload recovery time and the slew time. The overload recovery time

for the TLV904x family is approximately 13-µs typical.

8.3.7 EMI Rejection

The TLV904x uses integrated electromagnetic interference (EMI) filtering to reduce the effects of EMI from

sources such as wireless communications and densely-populated boards with a mix of analog signal chain and

digital components. EMI immunity can be improved with circuit design techniques; the TLV904x benefits from

these design improvements. Texas Instruments has developed the ability to accurately measure and quantify the

immunity of an operational amplifier over a broad frequency spectrum extending from 10 MHz to 6 GHz. Figure

8-2 shows the results of this testing on the TLV904x. Table 8-1 shows the EMIRR IN+ values for the TLV904x at

particular frequencies commonly encountered in real-world applications. The EMI Rejection Ratio of Operational

Amplifiers application report contains detailed information on the topic of EMIRR performance as it relates to op

amps and is available for download from www.ti.com.

100

90

80

70

60

50

40

30

20

10

0

1M

10M

100M

Frequency (Hz)

1G

D42_

Figure 8-2. EMIRR Testing

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Table 8-1. TLV904x EMIRR IN+ for Frequencies of Interest

FREQUENCY

APPLICATION OR ALLOCATION

EMIRR IN+

Mobile radio, mobile satellite, space operation, weather, radar, ultra-high frequency (UHF)

applications

400 MHz

60 dB

Global system for mobile communications (GSM) applications, radio communication, navigation,

GPS (to 1.6 GHz), GSM, aeronautical mobile, UHF applications

900 MHz

1.8 GHz

2.4 GHz

3.6 GHz

5 GHz

70 dB

75 dB

79.0 dB

82 dB

85 dB

GSM applications, mobile personal communications, broadband, satellite, L-band (1 GHz to 2 GHz)

802.11b, 802.11g, 802.11n, Bluetooth^®, mobile personal communications, industrial, scientific and

medical (ISM) radio band, amateur radio and satellite, S-band (2 GHz to 4 GHz)

Radiolocation, aero communication and navigation, satellite, mobile, S-band

802.11a, 802.11n, aero communication and navigation, mobile communication, space and satellite

operation, C-band (4 GHz to 8 GHz)

8.3.8 Electrical Overstress

Designers often ask questions about the capability of an operational amplifier to withstand electrical overstress.

These questions tend to focus on the device inputs, but can involve the supply voltage pins or even the output

pin. Each of these different pin functions have electrical stress limits determined by the voltage breakdown

characteristics of the particular semiconductor fabrication process and specific circuits connected to the pin.

Additionally, internal electrostatic discharge (ESD) protection is built into these circuits to protect them from

accidental ESD events both before and during product assembly.

Having a good understanding of this basic ESD circuitry and its relevance to an electrical overstress event is

helpful. Figure 8-3 shows the ESD circuits contained in the TLV904x devices. The ESD protection circuitry

involves several current-steering diodes connected from the input and output pins and routed back to the internal

power supply lines, where they meet at an absorption device internal to the operational amplifier. This protection

circuitry is intended to remain inactive during normal circuit operation.

V+

Power Supply

ESD Cell

+IN

+

œ

OUT

œ IN

Vœ

Figure 8-3. Equivalent Internal ESD Circuitry

8.3.9 Input and ESD Protection

The TLV904x family incorporates internal ESD protection circuits on all pins. For input and output pins, this

protection primarily consists of current-steering diodes connected between the input and power-supply pins.

These ESD protection diodes provide in-circuit, input overdrive protection, as long as the current is limited to

10 mA. Figure 8-4 shows how a series input resistor can be added to the driven input to limit the input current.

The added resistor contributes thermal noise at the amplifier input and the value must be kept to a minimum in

noise-sensitive applications.

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V+

I_OVERLOAD

10-mA maximum

V_OUT

Device

V_IN

5 kW

Figure 8-4. Input Current Protection

8.3.10 Shutdown Function

The TLV904xS devices feature SHDN pins that disable the op amp, placing it into a low-power standby mode. In

this mode, the op amp typically consumes less than 150 nA. The SHDN pins are active low, meaning that

shutdown mode is enabled when the input to the SHDN pin is a valid logic low.

The SHDN pins are referenced to the negative supply voltage of the op amp. The threshold of the shutdown

feature lies around 500 mV (typical) and does not change with respect to the supply voltage. Hysteresis has

been included in the switching threshold to ensure smooth switching characteristics. To ensure optimal shutdown

behavior, the SHDN pins should be driven with valid logic signals. A valid logic low is defined as a voltage

between V– and V– + 0.2 V. A valid logic high is defined as a voltage between V– + 1 V and V+. To enable the

amplifier, the SHDN pins must be driven to a valid logic high. To disable the amplifier, the SHDN pins must be

driven to a valid logic low. We highly recommend that the shutdown pin be connected to a valid high or a low

voltage or driven. The maximum voltage allowed at the SHDN pins is (V+) + 0.5 V. Exceeding this voltage level

will damage the device.

The SHDN pins are high-impedance CMOS inputs. Dual op amp versions are independently controlled and quad

op amp versions are controlled in pairs with logic inputs. For battery-operated applications, this feature may be

used to greatly reduce the average current and extend battery life. The enable time is 160 µs for full shutdown of

all channels; disable time is 10 µs. When disabled, the output assumes a high-impedance state. This

architecture allows the TLV904xS to be operated as a gated amplifier (or to have the device output multiplexed

onto a common analog output bus). Shutdown time (t_OFF) depends on loading conditions and increases as load

resistance increases. To ensure shutdown (disable) within a specific shutdown time, the specified 100-kΩ load to

midsupply (V_S/ 2) is required. If using the TLV904xS without a load, the resulting turnoff time is significantly

increased.

8.3.11 Packages With an Exposed Thermal Pad

The TLV904x family is available in packages such as the WQFN-16 (RTE) which feature an exposed thermal

pad. Inside the package, the die is attached to this thermal pad using an electrically conductive compound. For

this reason, when using a package with an exposed thermal pad, the thermal pad must either be connected to

V– or left floating. Attaching the thermal pad to a potential other then V– is not allowed, and the performance of

the device is not assured when doing so.

8.4 Device Functional Modes

The TLV904x devices have a single functional mode. These devices are powered on as long as the power-

supply voltage is between 1.2 V (±0.6 V) and 5.5 V (±2.75 V).

The TLV904xS devices feature a shutdown pin, which can be used to place the op amp into a low-power mode.

See Section 8.3.10 for more information.

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9 Application and Implementation

Note

Information in the following applications sections is not part of the TI component specification, and TI

does not warrant its accuracy or completeness. TI’s customers are responsible for determining

suitability of components for their purposes, as well as validating and testing their design

implementation to confirm system functionality.

9.1 Application Information

The TLV904x family of low-power, rail-to-rail input and output operational amplifiers is specifically designed for

portable applications. The devices operate from 1.2 V to 5.5 V, are unity-gain stable, and are suitable for a wide

range of general-purpose applications. The class AB output stage is capable of driving resitive loads greater

than 2-kΩ connected to any point between V+ and V–. The input common-mode voltage range includes both

rails and allows the TLV904x series to be used in many single-supply or dual supply configurations.

9.2 Typical Application

9.2.1 TLV904x Low-Side, Current Sensing Application

Figure 9-1 shows the TLV904x configured in a low-side current sensing application.

V_BUS

I_LOAD

Z_LOAD

5 V

+

Device

V_OUT

Þ

+

R_SHUNT

V_SHUNT

R_F

0.1 Ω

57.6 kΩ

Þ

R_G

1.2 kΩ

Figure 9-1. TLV904x in a Low-Side, Current-Sensing Application

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9.2.1.1 Design Requirements

The design requirements for this design are:

•

Load current: 0 A to 1 A

Maximum output voltage: 4.9 V

Maximum shunt voltage: 100 mV

9.2.1.2 Detailed Design Procedure

The transfer function of the circuit in Figure 9-1 is given in Equation 1.

V_OUT= I_LOADìR_SHUNTìGain

(1)

The load current (I_LOAD) produces a voltage drop across the shunt resistor (R_SHUNT). The load current is set from

0 A to 1 A. To keep the shunt voltage below 100 mV at maximum load current, the largest shunt resistor is

shown using Equation 2.

V_{SHUNT _MAX}

100mV

1A

R_SHUNT

=

=100mW

I_{LOAD_MAX}

(2)

Using Equation 2, R_SHUNTis calculated to be 100 mΩ. The voltage drop produced by I_LOADand R_SHUNTis

amplified by the TLV904x to produce an output voltage of approximately 0 V to 4.9 V. The gain needed by the

TLV904x to produce the necessary output voltage is calculated using Equation 3.

V

_{OUT _MAX}- V_{OUT _MIN}

(

)

Gain =

V_{IN_MAX}- V

(

)

IN_MIN

(3)

Using Equation 3, the required gain is calculated to be 49 V/V, which is set with resistors R_Fand R_G. Equation 4

sizes the resistors R_Fand R_G, to set the gain of the TLV904x to 49 V/V.

R

(

)

F

Gain = 1+

R

G

(4)

Selecting R_Fas 57.6 kΩ and R_Gas 1.2 kΩ provides a combination that equals 49 V/V. Figure 9-2 shows the

measured transfer function of the circuit shown in Figure 9-1. Notice that the gain is only a function of the

feedback and gain resistors. This gain is adjusted by varying the ratio of the resistors and the actual resistors

values are determined by the impedance levels that the designer wants to establish. The impedance level

determines the current drain, the effect that stray capacitance has, and a few other behaviors. There is no

optimal impedance selection that works for every system; you must choose an impedance that is ideal for your

system parameters.

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9.2.1.3 Application Curve

5

4

3

2

1

0

0.2

0.4

0.6

0.8

1

I_LOAD(A)

C219

Figure 9-2. Low-Side, Current-Sense Transfer Function

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10 Power Supply Recommendations

The TLV904x family is specified for operation from 1.2 V to 5.5 V (±0.6 V to ±2.75 V); many specifications apply

from –40°C to 125°C. Section 7.6 presents parameters that may exhibit significant variance with regard to

operating voltage or temperature.

CAUTION

Supply voltages larger than 6 V may permanently damage the device; see the Absolute Maximum

Ratings table.

Place 0.1-µF bypass capacitors close to the power-supply pins to reduce coupling errors from noisy or high-

impedance power supplies. For more detailed information on bypass capacitor placement, see Section 11.1.

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11 Layout

11.1 Layout Guidelines

For best operational performance of the device, use good printed circuit board (PCB) layout practices, including:

•

Noise can propagate into analog circuitry through the power connections of the board and propagate to the

power pins of the op amp itself. Bypass capacitors are used to reduce the coupled noise by providing a low-

impedance path to ground.

– Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as

close to the device as possible. A single bypass capacitor from V+ to ground is adequate for single-supply

applications.

•

Separate grounding for analog and digital portions of circuitry is one of the simplest and most effective

methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes.

A ground plane helps distribute heat and reduces electromagnetic interference (EMI) noise pickup. Take care

to physically separate digital and analog grounds, paying attention to the flow of the ground current.

To reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible. If

these traces cannot be kept separate, crossing the sensitive trace at a 90 degree angle is much better as

opposed to running the traces in parallel with the noisy trace.

•

Place the external components as close to the device as possible, as shown in Figure 11-2. Keeping R_Fand

R_Gclose to the inverting input minimizes parasitic capacitance.

Keep the length of input traces as short as possible. Remember that the input traces are the most sensitive

part of the circuit.

Consider a driven, low-impedance guard ring around the critical traces. A guard ring may significantly reduce

leakage currents from nearby traces that are at different potentials.

•

Cleaning the PCB following board assembly is recommended for best performance.

Any precision integrated circuit can experience performance shifts resulting from moisture ingress into the

plastic package. Following any aqueous PCB cleaning process, baking the PCB assembly is recommended

to remove moisture introduced into the device packaging during the cleaning process. A low-temperature,

post-cleaning bake at 85°C for 30 minutes is sufficient for most circumstances.

11.2 Layout Example

VIN 1

VIN 2

+

VOUT 1

VOUT 2

R_G

R_F

Figure 11-1. Schematic Representation

Place components

close to device and to

each other to reduce

parasitic errors.

OUT 1

Use low-ESR,

ceramic bypass

capacitor . Place as

close to the device

as possible .

V_S+

GND

OUT1

V+

R_F

R_G

OUT 2

GND

IN1œ

IN1+

Vœ

OUT2

IN2œ

IN2+

R_F

VIN 1

GND

R_G

VIN 2

Keep input traces short

and run the input traces

as far away from

the supply lines

Use low-ESR,

GND

ceramic bypass

capacitor . Place as

close to the device

as possible .

V_Sœ

Ground (GND) plane on another layer

as possible .

Figure 11-2. Layout Example

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GND

V+

INPUT A

OUTPUT B

V-

GND

Figure 11-3. Example Layout for VSSOP-8 (DGK) Package

GND

-

+

OUT B

+

-

+IN A

GND

Figure 11-4. Example Layout for WSON-8 (DSG) Package

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12 Device and Documentation Support

12.1 Documentation Support

12.1.1 Related Documentation

For related documentation see the following:

•

EMI rejection ratio of operational amplifiers

QFN/SON PCB attachment

Quad flatpack no-lead logic packages

12.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on

Subscribe to updates to register and receive a weekly digest of any product information that has changed. For

change details, review the revision history included in any revised document.

12.3 Support Resources

TI E2E^™support forums are an engineer's go-to source for fast, verified answers and design help — straight

from the experts. Search existing answers or ask your own question to get the quick design help you need.

Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do

not necessarily reflect TI's views; see TI's Terms of Use.

12.4 Trademarks

TI E2E^™is a trademark of Texas Instruments.

Bluetooth^®is a registered trademark of Bluetooth SIG, Inc.

All trademarks are the property of their respective owners.

12.5 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric changes could cause the device not to meet its published

specifications.

12.6 Glossary

TI Glossary

This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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PACKAGE MATERIALS INFORMATION

www.ti.com

23-Dec-2020

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

TLV9042IDDFR

SOT-

DDF

8

3000

180.0

8.4

3.2

1.4

4.0

8.0

Q3

23-THIN

TLV9042IDR

TLV9042IDSGR

TLV9042IPWR

TLV9042SIRUGR

TLV9044IDR

SOIC

WSON

TSSOP

X2QFN

SOIC

D

8

2500

3000

2000

3000

2500

2000

330.0

180.0

330.0

178.0

330.0

12.4

8.4

6.4

2.3

7.0

1.75

6.5

6.9

5.2

2.3

3.6

2.25

9.0

5.6

2.1

1.15

1.6

8.0

4.0

8.0

4.0

8.0

12.0

8.0

Q1

Q2

Q1

DSG

PW

RUG

D

8

12.4

8.4

12.0

8.0

10

14

0.56

2.1

16.4

12.4

16.0

12.0

TLV9044IPWR

TSSOP

PW

1.6

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

23-Dec-2020

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

TLV9042IDDFR

TLV9042IDR

SOT-23-THIN

SOIC

DDF

D

8

3000

2500

3000

2000

3000

2500

2000

210.0

853.0

210.0

853.0

205.0

367.0

853.0

185.0

449.0

185.0

449.0

200.0

367.0

449.0

35.0

33.0

38.0

35.0

TLV9042IDSGR

TLV9042IPWR

TLV9042SIRUGR

TLV9044IDR

WSON

DSG

PW

RUG

D

8

TSSOP

X2QFN

SOIC

8

10

14

TLV9044IPWR

TSSOP

PW

Pack Materials-Page 2

PACKAGE OUTLINE

D0008A

SOIC - 1.75 mm max height

SCALE 2.800

SMALL OUTLINE INTEGRATED CIRCUIT

C

SEATING PLANE

.228-.244 TYP

[5.80-6.19]

.004 [0.1] C

A

PIN 1 ID AREA

6X .050

[1.27]

8

1

2X

.189-.197

[4.81-5.00]

NOTE 3

.150

[3.81]

4X (0 -15 )

4

5

8X .012-.020

[0.31-0.51]

B

.150-.157

[3.81-3.98]

NOTE 4

.069 MAX

[1.75]

.010 [0.25]

C A B

.005-.010 TYP

[0.13-0.25]

4X (0 -15 )

SEE DETAIL A

.010

[0.25]

.004-.010

[0.11-0.25]

0 - 8

.016-.050

[0.41-1.27]

DETAIL A

TYPICAL

(.041)

[1.04]

4214825/C 02/2019

NOTES:

1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.

Dimensioning and tolerancing per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed .006 [0.15] per side.

4. This dimension does not include interlead flash.

5. Reference JEDEC registration MS-012, variation AA.

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EXAMPLE BOARD LAYOUT

D0008A

SOIC - 1.75 mm max height

SMALL OUTLINE INTEGRATED CIRCUIT

8X (.061 )

[1.55]

SYMM

SEE

DETAILS

1

8

8X (.024)

[0.6]

SYMM

(R.002 ) TYP

[0.05]

5

4

6X (.050 )

[1.27]

(.213)

[5.4]

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:8X

SOLDER MASK

OPENING

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

METAL

EXPOSED

METAL

EXPOSED

METAL

.0028 MAX

[0.07]

.0028 MIN

[0.07]

ALL AROUND

SOLDER MASK

DEFINED

NON SOLDER MASK

DEFINED

SOLDER MASK DETAILS

4214825/C 02/2019

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

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EXAMPLE STENCIL DESIGN

D0008A

SOIC - 1.75 mm max height

SMALL OUTLINE INTEGRATED CIRCUIT

8X (.061 )

[1.55]

SYMM

1

8

8X (.024)

[0.6]

SYMM

(R.002 ) TYP

[0.05]

5

4

6X (.050 )

[1.27]

(.213)

[5.4]

SOLDER PASTE EXAMPLE

BASED ON .005 INCH [0.125 MM] THICK STENCIL

SCALE:8X

4214825/C 02/2019

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

9. Board assembly site may have different recommendations for stencil design.

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GENERIC PACKAGE VIEW

DSG 8

2 x 2, 0.5 mm pitch

WSON - 0.8 mm max height

PLASTIC SMALL OUTLINE - NO LEAD

This image is a representation of the package family, actual package may vary.

Refer to the product data sheet for package details.

4224783/A

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PACKAGE OUTLINE

DSG0008A

WSON - 0.8 mm max height

SCALE 5.500

PLASTIC SMALL OUTLINE - NO LEAD

2.1

1.9

B

A

PIN 1 INDEX AREA

2.1

1.9

0.32

0.18

0.4

0.2

ALTERNATIVE TERMINAL SHAPE

TYPICAL

C

0.8 MAX

SEATING PLANE

0.08 C

0.05

0.00

EXPOSED

THERMAL PAD

(0.2) TYP

0.9 0.1

5

4

6X 0.5

2X

1.5

9

1.6 0.1

8

1

0.32

0.18

8X

0.4

0.2

PIN 1 ID

8X

0.1

C A B

C

0.05

4218900/D 04/2020

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

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EXAMPLE BOARD LAYOUT

DSG0008A

WSON - 0.8 mm max height

PLASTIC SMALL OUTLINE - NO LEAD

(0.9)

(

0.2) VIA

8X (0.5)

TYP

1

8

8X (0.25)

(0.55)

SYMM

9

(1.6)

6X (0.5)

5

4

SYMM

(1.9)

(R0.05) TYP

LAND PATTERN EXAMPLE

SCALE:20X

0.07 MIN

ALL AROUND

0.07 MAX

ALL AROUND

SOLDER MASK

OPENING

METAL

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

NON SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4218900/D 04/2020

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

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EXAMPLE STENCIL DESIGN

DSG0008A

WSON - 0.8 mm max height

PLASTIC SMALL OUTLINE - NO LEAD

8X (0.5)

METAL

8

SYMM

1

8X (0.25)

(0.45)

SYMM

9

(0.7)

6X (0.5)

5

4

(R0.05) TYP

(0.9)

(1.9)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD 9:

87% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE

SCALE:25X

4218900/D 04/2020

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

PACKAGE OUTLINE

PW0008A

TSSOP - 1.2 mm max height

S

C

A

L

E

2

.

8

0

SMALL OUTLINE PACKAGE

C

6.6

6.2

SEATING PLANE

TYP

PIN 1 ID

AREA

A

0.1 C

6X 0.65

8

5

1

3.1

2.9

NOTE 3

2X

1.95

4

0.30

0.19

8X

4.5

4.3

1.2 MAX

B

0.1

C A

B

NOTE 4

(0.15) TYP

SEE DETAIL A

0.25

GAGE PLANE

0.15

0.05

0.75

0.50

0 - 8

DETAIL A

TYPICAL

4221848/A 02/2015

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed 0.15 mm per side.

4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.

5. Reference JEDEC registration MO-153, variation AA.

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EXAMPLE BOARD LAYOUT

PW0008A

TSSOP - 1.2 mm max height

SMALL OUTLINE PACKAGE

8X (1.5)

SYMM

8X (0.45)

(R0.05)

1

4

TYP

8

SYMM

6X (0.65)

5

(5.8)

LAND PATTERN EXAMPLE

SCALE:10X

SOLDER MASK

OPENING

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

METAL

0.05 MAX

ALL AROUND

0.05 MIN

ALL AROUND

SOLDER MASK

DEFINED

NON SOLDER MASK

DEFINED

SOLDER MASK DETAILS

NOT TO SCALE

4221848/A 02/2015

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com

EXAMPLE STENCIL DESIGN

PW0008A

TSSOP - 1.2 mm max height

SMALL OUTLINE PACKAGE

8X (1.5)

SYMM

(R0.05) TYP

8X (0.45)

1

4

8

SYMM

6X (0.65)

5

(5.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

SCALE:10X

4221848/A 02/2015

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

9. Board assembly site may have different recommendations for stencil design.

www.ti.com

PACKAGE OUTLINE

DDF0008A

SOT-23 - 1.1 mm max height

S

C

A

L

E

4

.

0

PLASTIC SMALL OUTLINE

C

2.95

2.65

SEATING PLANE

TYP

PIN 1 ID

AREA

0.1 C

A

6X 0.65

8

1

2.95

2.85

NOTE 3

2X

1.95

4

5

0.4

0.2

8X

0.1

C A

B

1.65

1.55

B

1.1 MAX

0.20

0.08

TYP

SEE DETAIL A

0.25

GAGE PLANE

0.1

0.0

0 - 8

0.6

0.3

DETAIL A

TYPICAL

4222047/B 11/2015

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed 0.15 mm per side.

www.ti.com

EXAMPLE BOARD LAYOUT

DDF0008A

SOT-23 - 1.1 mm max height

PLASTIC SMALL OUTLINE

8X (1.05)

SYMM

1

8

8X (0.45)

SYMM

6X (0.65)

5

4

(R0.05)

TYP

(2.6)

LAND PATTERN EXAMPLE

SCALE:15X

SOLDER MASK

OPENING

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

METAL

SOLDER MASK

DEFINED

NON SOLDER MASK

DEFINED

SOLDER MASK DETAILS

4222047/B 11/2015

NOTES: (continued)

4. Publication IPC-7351 may have alternate designs.

5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com

EXAMPLE STENCIL DESIGN

DDF0008A

SOT-23 - 1.1 mm max height

PLASTIC SMALL OUTLINE

8X (1.05)

SYMM

(R0.05) TYP

8

1

8X (0.45)

SYMM

6X (0.65)

5

4

(2.6)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

SCALE:15X

4222047/B 11/2015

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

7. Board assembly site may have different recommendations for stencil design.

www.ti.com

IMPORTANT NOTICE AND DISCLAIMER

TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE

DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”

AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY

IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD

PARTY INTELLECTUAL PROPERTY RIGHTS.

These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate

TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable

standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you

permission to use these resources only for development of an application that uses the TI products described in the resource. Other

reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third

party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims,

damages, costs, losses, and liabilities arising out of your use of these resources.

TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on

ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable

warranties or warranty disclaimers for TI products.

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	TLV9042_V03
厂家：	TEXAS INSTRUMENTS
描述：	TLV904x Micro-power, 1.2-V, RRIO, 350-kHz Operational Amplifier for Cost-Sensitive Applications
文件：	总54页 (文件大小：4566K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TLV9042_V03 [TI]

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