TLV9151_V04_技术文档

TLV9151, TLV9152, TLV9154

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TLV915x 4.5-MHz, Rail-to-Rail Input/Output, Low Offset Voltage, Low Noise Op Amp

1 Features

3 Description

•

Low offset voltage: ±125 µV

The TLV915x family (TLV9151, TLV9152, and

TLV9154) is a family of 16-V, general purpose

Low offset voltage drift: ±0.3 µV/°C

Low noise: 10.5 nV/√ Hz at 1 kHz

High common-mode rejection: 120 dB

Low bias current: ±10 pA

Rail-to-rail input and output

Wide bandwidth: 4.5-MHz GBW

High slew rate: 20 V/µs

Low quiescent current: 560 µA per amplifier

Wide supply: ±1.35 V to ±8 V, 2.7 V to 16 V

Robust EMIRR performance: EMI/RFI filters on

input pins

Differential and common-mode input voltage range

to supply rail

operational

amplifiers.

These

devices

offer

exceptional DC precision and AC performance,

including rail-to-rail output, low offset (±125 µV, typ),

low offset drift (±0.3 µV/°C, typ), and 4.5-MHz

bandwidth.

Convenient features such as wide differential input-

voltage range, high output current (±75 mA), high

slew rate (20 V/μs), and low noise (10.5 nV/√ Hz)

make the TLV915x a robust, low-noise operational

amplifier for industrial applications.

The TLV915x family of op amps is available in

standard packages and is specified from –40°C to

125°C.

•

Industry standard packages:

Device Information

– Single in SOT-23-5, SC70-5, and SOT553

– Dual in SOIC-8, SOT-23-8, TSSOP-8,

VSSOP-8, WSON-8, and X2QFN-10

– Quad in SOIC-14, TSSOP-14, WQFN-14, and

WQFN-16

PART NUMBER ⁽¹⁾

PACKAGE

BODY SIZE (NOM)

2.90 mm × 1.60 mm

2.00 mm × 1.25 mm

1.60 mm × 1.20 mm

4.90 mm × 3.90 mm

2.90 mm × 1.60 mm

3.00 mm × 4.40 mm

3.00 mm × 3.00 mm

2.00 mm × 2.00 mm

1.50 mm × 1.50 mm

8.65 mm × 3.90 mm

5.00 mm × 4.40 mm

3.00 mm × 3.00 mm

2.00 mm × 2.00 mm

SOT-23 (5)

SOT-23 (6)

SC70 (5)

TLV9151

SOT-553 (5)⁽²⁾

2 Applications

SOIC (8)

•

Professional microphones & wireless systems

Multiplexed data-acquisition systems

Test and measurement equipment

Factory automation & control

SOT-23 (8)

TSSOP (8)

VSSOP (8)

VSSOP (10)⁽²⁾

WSON (8)

TLV9152

TLV9154

High-side and low-side current sensing

X2QFN (10)

SOIC (14)

TSSOP (14)

WQFN (16)⁽²⁾

X2QFN (14)

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

(2) This package is preview only.

TLV915x in a Single-Pole, Low-Pass Filter

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

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intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTION

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1

DATA.

TLV9151, TLV9152, TLV9154

SBOS986C – OCTOBER 2019 – REVISED DECEMBER 2020

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Table of Contents

1 Features............................................................................1

2 Applications.....................................................................1

3 Description.......................................................................1

4 Revision History.............................................................. 2

5 Pin Configuration and Functions...................................4

6 Specifications................................................................ 11

6.1 Absolute Maximum Ratings ..................................... 11

6.2 ESD Ratings .............................................................11

6.3 Recommended Operating Conditions ......................11

6.4 Thermal Information for Single Channel .................. 11

6.5 Thermal Information for Dual Channel .....................12

6.6 Thermal Information for Quad Channel ................... 12

6.7 Electrical Characteristics ..........................................13

6.8 Typical Characteristics..............................................17

7 Detailed Description......................................................24

7.1 Overview...................................................................24

7.2 Functional Block Diagram.........................................24

7.3 Feature Description...................................................25

7.4 Device Functional Modes..........................................32

8 Application and Implementation..................................33

8.1 Application Information............................................. 33

8.2 Typical Applications.................................................. 33

9 Power Supply Recommendations................................35

10 Layout...........................................................................35

10.1 Layout Guidelines................................................... 35

10.2 Layout Example...................................................... 36

11 Device and Documentation Support..........................37

11.1 Device Support........................................................37

11.2 Documentation Support.......................................... 37

11.3 Related Links.......................................................... 37

11.4 Receiving Notification of Documentation Updates..37

11.5 Support Resources................................................. 37

11.6 Trademarks............................................................. 38

11.7 Electrostatic Discharge Caution..............................38

11.8 Glossary..................................................................38

12 Mechanical, Packaging, and Orderable

Information.................................................................... 39

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision B (May 2020) to Revision C (December 2020)

Page

•

Updated the numbering format for tables, figures and cross-references throughout the document ..................1

Changed SOT-23 (5) package status on Device Information from Preview to Active ....................................... 1

Changed SC70 (5) package status on Device Information from Preview to Active ...........................................1

Changed SOT-23 (6) package status on Device Information from Preview to Active ....................................... 1

Changed SOT-23 (8) package status on Device Information from Preview to Active ....................................... 1

Changed VSSOP (8) package status on Device Information from Preview to Active ....................................... 1

Changed SOIC (14) package status on Device Information from Preview to Active .........................................1

Changed TSSOP (14) package status on Device Information from Preview to Active ......................................1

Changed X2QFN (14) package status on Device Information from Preview to Active ......................................1

Removed preview notation on SOT-23-5 (DBV), SC70-5 (DCK) SOT-23-6 (DBV), and SOT-23-8 (DDF)

packages in Pin Configurations and Functions ..................................................................................................4

Removed preview notation on SOIC-14 (D) package in Pin Configurations and Functions ..............................4

Removed preview notation on TSSOP-14 (PW) package in Pin Configurations and Functions ....................... 4

Removed preview notation on X2QFN-14 (RUC) package in Pin Configurations and Functions ..................... 4

•

Changes from Revision A (March 2020) to Revision B (May 2020)

Page

•

Changed X2QFN (10) package status on Device Information from Preview to Active ......................................1

Removed preview notation on X2QFN (RUG) package in Pin Configurations and Functions .......................... 4

Added V_IHand V_ILin Recommended Operating Conditions section.................................................................11

Added SHUTDOWN in Electrical Characteristics table.....................................................................................11

Changes from Revision * (October 2019) to Revision A (March 2020)

Page

•

Changed document status from Advance Information to Production Data ........................................................1

Changed SOIC (8) package status on Device Information from Preview to Active ...........................................1

Changed TSSOP (8) package status on Device Information from Preview to Active ........................................1

2

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•

Changed WSON (8) package status on Device Information from Preview to Active .........................................1

Removed preview notation on SOIC-8 (D), TSSOP-8 (PW), and WSON-8 (DSG) packages in Pin

Configurations and Functions ............................................................................................................................4

Added Typical Characteristics section in Specifications section.......................................................................17

•

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5 Pin Configuration and Functions

OUT

Vœ

1

2

3

5

V+

IN+

Vœ

1

2

3

5

V+

IN+

4

INœ

4

OUT

Not to scale

A. DRL package is preview only.

Figure 5-2. TLV9151 DCK 5-Pin SC70 and SOT-553

Top View

Figure 5-1. TLV9151 DBV and DRL Package⁽¹⁾5-Pin

SOT-23 Top View

Table 5-1. Pin Functions: TLV9151

I/O

DESCRIPTION

NAME

DBV, DRL

DCK

+IN

–IN

3

4

1

5

2

1

3

4

5

2

I

Noninverting input

I

Inverting input

OUT

V+

O

—

Output

Positive (highest) power supply

Negative (lowest) power supply

V–

4

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OUT

Vœ

1

2

3

6

5

4

V+

NC

œIN

+IN

Not to scale

A. DRL package is preview only.

Figure 5-3. TLV9151S DBV and DRL Package⁽¹⁾6-Pin SOT-23 and SOT-563 Top View

Table 5-2. Pin Functions: TLV9151S

I/O

DESCRIPTION

NAME

DBV, DRL

+IN

3

4

1

5

6

2

I

Noninverting input

Inverting input

Output

–IN

OUT

SHDN

V+

O

I

Shutdown (active low) logic input

Positive (highest) power supply

Negative (lowest) power supply

—

V–

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OUT1

IN1œ

IN1+

Vœ

1

2

3

4

8

7

6

5

V+

OUT1

IN1œ

IN1+

Vœ

1

2

3

4

8

7

6

5

V+

OUT2

IN2œ

IN2+

OUT2

IN2œ

IN2+

Thermal

Pad

Not to scale

A. DGK package is preview only.

A. Connect thermal pad to V–. See Packages with and Exposed

Thermal Pad section for more information.

Figure 5-5. TLV9152 DSG Package⁽¹⁾8-Pin WSON

With Exposed Thermal Pad Top View

Figure 5-4. TLV9152 D, DDF, DGK, and PW

Package⁽¹⁾8-Pin SOIC, SOT-23-8, TSSOP, and

VSSOP Top View

Table 5-3. Pin Functions: TLV9152

SOIC, SOT-23-8,

I/O

DESCRIPTION

NAME

TSSOP, VSSOP,

WSON

+IN A

+IN B

–IN A

–IN B

3

5

2

6

1

7

8

4

I

Noninverting input, channel A

Noninverting input, channel B

Inverting input, channel A

Inverting input, channel B

Output, channel A

I

OUT A

OUT B

V+

O

—

Output, channel B

Positive (highest) power supply

Negative (lowest) power supply

V–

6

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OUT1

IN1œ

1

2

3

4

5

10

9

V+

OUT2

IN2œ

IN2+

SHDN2

Vœ

SHDN1

SHDN2

IN2+

1

2

3

4

9

8

7

6

IN1œ

OUT1

V+

IN1+

8

Vœ

7

SHDN1

6

Not to scale

A. Package is preview only.

Figure 5-6. TLV9152S DGS Package⁽¹⁾10-Pin

VSSOP Top View

OUT2

Not to scale

Figure 5-7. TLV9152S RUG Package 10-Pin X2QFN

Top View

Table 5-4. Pin Functions: TLV9152S

I/O

DESCRIPTION

NAME

+IN A

VSSOP

X2QFN

3

7

2

8

1

9

10

4

I

Noninverting input, channel A

Noninverting input, channel B

Inverting input, channel A

Inverting input, channel B

Output, channel A

+IN B

–IN A

–IN B

OUT A

OUT B

9

I

5

I

8

O

6

Output, channel B

Shutdown, channel 1: low = amplifier enabled, high = amplifier

disabled. See Shutdown section for more information.

SHDN1

SHDN2

5

6

2

3

I

Shutdown, channel 2: low = amplifier enabled, high = amplifier

disabled. See Shutdown section for more information.

V+

V–

10

4

7

1

—

Positive (highest) power supply

Negative (lowest) power supply

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OUT1

IN1œ

IN1+

V+

1

2

3

4

5

6

7

14

13

12

11

10

9

OUT4

IN4œ

IN4+

Vœ

IN1+

V+

1

2

3

4

12

11

10

9

IN4+

Vœ

IN2+

IN2œ

OUT2

IN3+

IN3œ

OUT3

Thermal

Pad

IN2+

IN2œ

IN3+

IN3œ

8

Not to scale

Figure 5-8. TLV9154 D and PW Package 14-Pin

SOIC and TSSOP Top View

Not to scale

A. Connect thermal pad to V–. See Packages with and Exposed

Thermal Pad section for more information.

B. Package is preview only.

Figure 5-9. TLV9154 RTE Package⁽¹⁾⁽²⁾16-Pin

WQFN With Exposed Thermal Pad Top View

IN1œ

IN1+

V+

1

2

3

4

5

12

11

10

9

IN4œ

IN4+

Vœ

IN2+

IN2œ

IN3+

IN3œ

8

Not to scale

Figure 5-10. TLV9154 RUC Package 14-Pin X2QFN With Exposed Thermal Pad Top View

Table 5-5. Pin Functions: TLV9154

I/O

DESCRIPTION

SOIC,

TSSOP

NAME

IN1+

WQFN

X2QFN

3

2

1

16

3

2

1

4

5

9

I

Noninverting input, channel 1

IN1–

IN2+

IN2–

IN3+

Inverting input, channel 1

Noninverting input, channel 2

Inverting input, channel 2

Noninverting input, channel 3

5

6

4

10

8

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NAME

SBOS986C – OCTOBER 2019 – REVISED DECEMBER 2020

Table 5-5. Pin Functions: TLV9154 (continued)

I/O

DESCRIPTION

SOIC,

TSSOP

WQFN

X2QFN

IN3–

IN4+

IN4–

NC

9

12

13

—

1

9

12

13

6, 7

15

5

8

11

12

—

14

6

I

Inverting input, channel 3

I

Noninverting input, channel 4

Inverting input, channel 4

Do not connect

I

—

O

—

OUT1

OUT2

OUT3

OUT4

V+

Output, channel 1

7

Output, channel 2

8

7

Output, channel 3

14

4

14

2

13

3

Output, channel 4

Positive (highest) power supply

Negative (lowest) power supply

V–

11

10

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IN1+

V+

1

2

3

4

12

11

10

9

IN4+

Vœ

Thermal

Pad

IN2+

IN2œ

IN3+

IN3œ

Not to scale

A. Package is preview only.

Figure 5-11. TLV9154S RTE Package⁽¹⁾16-Pin WQFN With Exposed Thermal Pad Top View

Table 5-6. Pin Functions: TLV9154S

I/O

DESCRIPTION

NAME

RTE

1

IN1+

IN1–

IN2+

IN2–

IN3+

IN3–

IN4+

IN4–

OUT1

OUT2

OUT3

OUT4

I

Noninverting input, channel 1

Inverting input, channel 1

Noninverting input, channel 2

Inverting input, channel 2

Noninverting input, channel 3

Inverting input, channel 3

Noninverting input, channel 4

Inverting input, channel 4

Output, channel 1

16

3

I

4

I

10

9

I

12

13

15

5

I

O

I

Output, channel 2

8

Output, channel 3

14

6

Output, channel 4

SHDN12

SHDN34

VCC+

Shutdown (active low), channel 1 & 2, logic input

Shutdown (active low), channel 3 & 4, logic input

Positive (highest) power supply

7

I

2

—

VCC–

11

Negative (lowest) power supply

10

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6 Specifications

6.1 Absolute Maximum Ratings

over operating ambient temperature range (unless otherwise noted) ⁽¹⁾

MIN

0

MAX

20

UNIT

V

Supply voltage, V_S= (V+) – (V–)

Common-mode voltage ⁽³⁾

(V–) – 0.5

(V+) + 0.5

V_S+ 0.2

10

V

Signal input pins

Differential voltage ⁽³⁾

Current ⁽³⁾

V

–10

–55

–65

mA

Output short-circuit ⁽²⁾

Continuous

Operating ambient temperature, T_A

Junction temperature, T_J

150

°C

Storage temperature, T_stg

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under

Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device

reliability.

(2) Short-circuit to ground, one amplifier per package.

(3) Input pins are diode-clamped to the power-supply rails. Input signals that may swing more than 0.5 V beyond the supply rails must be

current limited to 10 mA or less.

6.2 ESD Ratings

VALUE

±2000

±1000

UNIT

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

V_(ESD)

Electrostatic discharge

V

Charged device model (CDM), per JEDEC specification JESD22-C101 ⁽²⁾

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating ambient temperature range (unless otherwise noted)

MIN

2.7

MAX

UNIT

V_S

V_I

Supply voltage, (V+) – (V–)

16

(V+) + 0.1

(V+)

V

Input voltage range

(V–) – 0.1

1.1

V_IH

V_IL

T_A

High level input voltage at shutdown pin (amplifier enabled)

Low level input voltage at shutdown pin (amplifier disabled)

Specified temperature

V

(V–)

0.2

V

–40

125

°C

6.4 Thermal Information for Single Channel

TLV9151, TLV9151S

DBV

(SOT-23)

DCK

(SC70)

DRL ⁽²⁾

(SOT-553)

THERMAL METRIC ⁽¹⁾

UNIT

5 PINS

6 PINS

167.8

107.9

49.7

5 PINS

202.6

101.5

47.8

5 PINS

6 PINS

TBD

R_θJA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

Junction-to-top characterization parameter

185.7

108.2

54.5

TBD

°C/W

R_θJC(top)

R_θJB

TBD

ψ_JT

31.2

33.9

18.8

TBD

Junction-to-board characterization

parameter

ψ_JB

54.2

49.5

47.4

TBD

°C/W

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6.4 Thermal Information for Single Channel (continued)

TLV9151, TLV9151S

DBV

DCK

(SC70)

DRL ⁽²⁾

(SOT-553)

THERMAL METRIC ⁽¹⁾

(SOT-23)

UNIT

5 PINS

6 PINS

5 PINS

TBD

6 PINS

R_θJC(bot)

Junction-to-case (bottom) thermal resistance

N/A

TBD

°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report, SPRA953.

(2) This package option is preview for TLV9151.

6.5 Thermal Information for Dual Channel

TLV9152, TLV9152S

D

DDF

(SOT-23-8)

DGK ⁽²⁾

(VSSOP)

DGS ⁽²⁾

(VSSOP)

DSG

(WSON)

PW

(TSSOP)

RUG

(X2QFN)

THERMAL METRIC ⁽¹⁾

UNIT

(SOIC)

8 PINS

10 PINS

8 PINS

10 PINS

Junction-to-ambient

thermal resistance

R_θJA

R_θ

138.7

143.5

176.5

TBD

77.6

185.1

142.3

°C/W

Junction-to-case (top)

thermal resistance

78.7

82.2

79.9

61.6

68.1

98.2

TBD

93.7

43.9

74.0

53.5

68.5

JC(top)

Junction-to-board

thermal resistance

R_θJB

115.7

Junction-to-top

characterization

parameter

ψ_JT

27.8

81.4

N/A

5.7

61.3

N/A

12.0

96.7

N/A

TBD

4.4

12.3

114.0

N/A

1.0

68.4

N/A

°C/W

Junction-to-board

characterization

parameter

ψ_JB

43.9

19.0

Junction-to-case

(bottom) thermal

resistance

R_θ

JC(bot)

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report, SPRA953.

(2) This package option is preview for TLV9152.

6.6 Thermal Information for Quad Channel

TLV9154, TLV9154S

D

PW

(TSSOP)

RTE ⁽²⁾

(WQFN)

RUC

(WQFN)

THERMAL METRIC ⁽¹⁾

UNIT

(SOIC)

14 PINS

101.4

57.6

14 PINS

131.4

51.8

16 PINS

TBD

14 PINS

125.9

39.8

R_θJA

Junction-to-ambient thermal resistance

°C/W

R_θJC(top)Junction-to-case (top) thermal resistance

TBD

R_θJB

ψ_JT

Junction-to-board thermal resistance

57.3

75.8

TBD

68.0

Junction-to-top characterization parameter

18.5

7.9

TBD

0.8

Junction-to-board characterization

parameter

ψ_JB

56.9

N/A

74.8

N/A

TBD

67.8

N/A

°C/W

Junction-to-case (bottom) thermal

resistance

R_θJC(bot)

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report, SPRA953.

(2) This package option is preview for TLV9154.

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6.7 Electrical Characteristics

For V_S= (V+) – (V–) = 2.7 V to 16 V (±1.35 V to ±8 V) at T_A= 25°C, R_L= 10 kΩ connected to V_S/ 2, V_CM= V_S/ 2, and V_{O UT}

= V_S/ 2, unless otherwise noted.

PARAMETER

TEST CONDITIONS

MIN

TYP

±125

MAX

UNIT

OFFSET VOLTAGE

±750

±780

±830

±880

TLV9151, TLV9152

V_CM= V–

T_A= –40°C to 125°C

V_OS

Input offset voltage

µV

TLV9154

V_CM= V–

T_A= –40°C to 125°C

Input offset voltage

drift

dV_OS/dT

PSRR

±0.3

µV/℃

V_CM= V–, V_S= 4 V to 16 V

V_CM= V–, V_S= 2.7 V to 16 V⁽²⁾

f = 0 Hz

±0.3

±1

5

±1

±5

Input offset voltage

versus power supply

T_A= –40°C to 125°C

μV/V

µV/V

Channel separation

INPUT BIAS CURRENT

I_B

Input bias current

±10

pA

I_OS

Input offset current

NOISE

1.8

0.3

10.8

9.4

2

μV_PP

E_N

Input voltage noise

f = 0.1 Hz to 10 Hz

µV_RMS

f = 1 kHz

f = 10 kHz

f = 1 kHz

Input voltage noise

density

e_N

i_N

nV/√Hz

fA/√Hz

Input current noise

INPUT VOLTAGE RANGE

Common-mode

V_CM

(V–) –

0.1

(V+) +

0.1

V

voltage range

V_S= 16 V, (V–) – 0.1 V < V_CM

(V+) – 2 V (Main input pair)

<

109

84

130

100

95

V_S= 4 V, (V–) – 0.1 V < V_CM

(V+) – 2 V (Main input pair)

<

Common-mode

CMRR

T_A= –40°C to 125°C

<

dB

V_S= 2.7 V, (V–) – 0.1 V < V_CM

(V+) – 2 V (Main input pair)⁽²⁾

rejection ratio

75

V_S= 2.7 V to 16 V, (V+) – 1 V <

V_CM< (V+) + 0.1 V (Aux input

pair)

85

INPUT CAPACITANCE

Z_ID

Differential

100 || 3

6 || 1

MΩ || pF

TΩ || pF

Z_ICM

Common-mode

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6.7 Electrical Characteristics (continued)

For V_S= (V+) – (V–) = 2.7 V to 16 V (±1.35 V to ±8 V) at T_A= 25°C, R_L= 10 kΩ connected to V_S/ 2, V_CM= V_S/ 2, and V_{O UT}

= V_S/ 2, unless otherwise noted.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

OPEN-LOOP GAIN

V_S= 16 V, V_CM= V–

(V–) + 0.1 V < V_O< (V+) – 0.1

V

120

145

142

130

125

120

118

T_A= –40°C to 125°C

V_S= 4 V, V_CM= V–

(V–) + 0.1 V < V_O< (V+) – 0.1

V

104

101

Open-loop voltage

gain

A_OL

dB

V_S= 2.7 V, V_CM= V–

(V–) + 0.1 V < V_O< (V+) – 0.1

V⁽²⁾

FREQUENCY RESPONSE

Gain-bandwidth

product

GBW

4.5

MHz

V/μs

SR

Slew rate

V_S= 16 V, G = +1, C_L= 20 pF

21

2.5

1.5

2

To 0.01%, V_S= 16 V, V_STEP= 10 V , G = +1, CL = 20 pF

To 0.01%, V_S= 16 V, V_STEP= 2 V , G = +1, CL = 20 pF

To 0.1%, V_S= 16 V, V_STEP= 10 V , G = +1, CL = 20 pF

To 0.1%, V_S= 16 V, V_STEP= 2 V , G = +1, CL = 20 pF

G = +1, R_L= 10 kΩ

t_S

Settling time

μs

1

Phase margin

60

°

Overload recovery

time

V_IN× gain > V_S

400

ns

Total harmonic

distortion + noise

0.00021

%

THD+N

V_S= 16 V, V_O= 3 V_RMS, G = 1, f = 1 kHz

OUTPUT

V_S= 16 V, R_L= no

load⁽²⁾

5

10

V_S= 16 V, R_L= 10 kΩ

50

55

V_S= 16 V, R_L= 2 kΩ

200

250

Voltage output swing Positive and negative rail

mV

from rail

headroom

V_S= 2.7 V, R_L= no

load⁽²⁾

1

6

V_S= 2.7 V, R_L= 10 kΩ

V_S= 2.7 V, R_L= 2 kΩ

5

25

12

40

I_SC

Short-circuit current

Capacitive load drive

±75

1000

mA

pF

C_LOAD

Open-loop output

impedance

Z_O

f = 1 MHz, I_O= 0 A

525

Ω

POWER SUPPLY

560

685

750

Quiescent current per

amplifier

I_Q

I_O= 0 A

µA

T_A= –40°C to 125°C

14

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6.7 Electrical Characteristics (continued)

For V_S= (V+) – (V–) = 2.7 V to 16 V (±1.35 V to ±8 V) at T_A= 25°C, R_L= 10 kΩ connected to V_S/ 2, V_CM= V_S/ 2, and V_{O UT}

= V_S/ 2, unless otherwise noted.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

SHUTDOWN

Quiescent current per

amplifier

I_QSD

V_S= 2.7 V to 40 V, all amplifiers disabled, SHDN = V–

V_S= 2.7 V to 40 V, amplifier disabled

30

45

µA

Output impedance

during shutdown

Z_SHDN

10 || 2

GΩ || pF

Logic high threshold

voltage (amplifier

enabled)

(V–) +

1.1

V_IH

V

Logic low threshold

voltage (amplifier

disabled)

(V–) +

0.2

V_IL

Amplifier enable

time

t_ON

G = +1, V_CM= V-, V_O= 0.1 × V_S/2

V_CM= V-, V_O= V_S/2

8

3

µs

(1)

Amplifier disable time

t_OFF

(1)

V_S= 2.7 V to 40 V, (V+) ≥ SHDN ≥ (V–) + 0.9 V

V_S= 2.7 V to 40 V, (V–) ≤ SHDN ≤ (V–) + 0.7 V

500

150

SHDN pin input bias

current (per pin)

nA

(1) Disable time (t_OFF) and enable time (t_ON) are defined as the time interval between the 50% point of the signal applied to the SHDN pin

and the point at which the output voltage reaches the 10% (disable) or 90% (enable) level.

(2) Specified by characterization only.

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Table 6-1. Table of Graphs

DESCRIPTION

FIGURE

Figure 6-1

Offset Voltage Production Distribution

Offset Voltage Drift Distribution

Offset Voltage vs Temperature

Figure 6-2

Figure 6-3, Figure 6-4

Figure 6-5, Figure 6-6, Figure 6-7, Figure 6-8

Figure 6-9

Offset Voltage vs Common-Mode Voltage

Offset Voltage vs Power Supply

Open-Loop Gain and Phase vs Frequency

Closed-Loop Gain and Phase vs Frequency

Input Bias Current vs Common-Mode Voltage

Input Bias Current vs Temperature

Output Voltage Swing vs Output Current

CMRR and PSRR vs Frequency

Figure 6-10

Figure 6-11

Figure 6-12

Figure 6-13

Figure 6-14, Figure 6-15,

Figure 6-16

CMRR vs Temperature

Figure 6-17

PSRR vs Temperature

Figure 6-18

0.1-Hz to 10-Hz Noise

Figure 6-19

Input Voltage Noise Spectral Density vs Frequency

THD+N Ratio vs Frequency

Figure 6-20

Figure 6-21

THD+N vs Output Amplitude

Figure 6-22

Quiescent Current vs Supply Voltage

Quiescent Current vs Temperature

Open Loop Voltage Gain vs Temperature

Open Loop Output Impedance vs Frequency

Small Signal Overshoot vs Capacitive Load (100-mV Output Step)

Phase Margin vs Capacitive Load

No Phase Reversal

Figure 6-23

Figure 6-24

Figure 6-25

Figure 6-26

Figure 6-27, Figure 6-28

Figure 6-29

Figure 6-30

Positive Overload Recovery

Figure 6-31

Negative Overload Recovery

Figure 6-32

Small-Signal Step Response (100 mV)

Large-Signal Step Response

Figure 6-33, Figure 6-34

Figure 6-35, Figure 6-36, Figure 6-37

Figure 6-38

Short-Circuit Current vs Temperature

Maximum Output Voltage vs Frequency

Channel Separation vs Frequency

EMIRR vs Frequency

Figure 6-39

Figure 6-40

Figure 6-41

16

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6.8 Typical Characteristics

at T_A= 25°C, V_S= ±8 V, V_CM= V_S/ 2, R_LOAD= 10 kΩ connected to V_S/ 2, and C_L= 10 pF (unless otherwise noted)

33

30

27

24

21

18

15

12

9

50

40

30

20

10

0

6

3

0

D002

D001

Offset Voltage Drift (µV/C)

Offset Voltage (µV)

Distribution from 60 amplifiers

Distribution from 15462 amplifiers, T_A= 25°C

Figure 6-2. Offset Voltage Drift Distribution

Figure 6-1. Offset Voltage Production Distribution

900

700

400

300

200

100

0

500

300

100

-100

-300

-500

-700

-900

-100

-200

-300

-400

-40

-20

0

20

40

60

80

100 120 140

-40 -20

0

20

40

60

80

100 120 140

Temperature (°C)

D004

D003

V_CM= V+

V_CM= V–

Figure 6-3. Offset Voltage vs Temperature

Figure 6-4. Offset Voltage vs Temperature

800

600

400

200

0

800

600

400

200

0

-200

-400

-600

-800

-200

-400

-600

-800

-8

-6

-4

-2

0

2

4

6

8

4

4.5

5

5.5

6

6.5

7

7.5

8

VCM

D005

T_A= 25°C

Figure 6-5. Offset Voltage vs Common-Mode Voltage

Figure 6-6. Offset Voltage vs Common-Mode Voltage (Transition

Region)

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6.8 Typical Characteristics (continued)

at T_A= 25°C, V_S= ±8 V, V_CM= V_S/ 2, R_LOAD= 10 kΩ connected to V_S/ 2, and C_L= 10 pF (unless otherwise noted)

800

600

400

200

0

800

600

400

200

0

-200

-400

-600

-800

-200

-400

-600

-800

-8

-6

-4

-2

0

2

4

6

8

-8

-6

-4

-2

0

2

4

6

8

VCM

D006

D007

T_A= 125°C

T_A= –40°C

Figure 6-7. Offset Voltage vs Common-Mode Voltage

Figure 6-8. Offset Voltage vs Common-Mode Voltage

100

200

175

150

125

100

75

600

500

400

300

200

100

0

Gain (dB)

Phase (ꢀ)

90

80

70

60

50

40

30

20

10

0

50

25

-100

-200

-300

-400

-500

-600

0

-25

-50

-75

-100

-10

-20

100

1k

10k

100k

1M

10M

Frequency (Hz)

2

4

6

8

10

12

14

16

18

C002

Supply Voltage (V)

D008

C_L= 20 pF

Figure 6-9. Offset Voltage vs Power Supply

Figure 6-10. Open-Loop Gain and Phase vs Frequency

80

70

60

50

40

30

20

10

0

6

4.5

3

G = ꢀ1

G = 1

G = 10

G = 100

G = 1000

1.5

0

-1.5

-3

-4.5

I_Bꢀ

I_B+

I_OS

-6

-10

-20

-7.5

-8 -7 -6 -5 -4 -3 -2 -1

0

1

2

3

4

5

6

7

8

100

1k

10k

100k

1M

10M

Common Mode Voltage (V)

Frequency (Hz)

D010

C001

Figure 6-12. Input Bias Current vs Common-Mode Voltage

Figure 6-11. Closed-Loop Gain vs Frequency

18

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6.8 Typical Characteristics (continued)

at T_A= 25°C, V_S= ±8 V, V_CM= V_S/ 2, R_LOAD= 10 kΩ connected to V_S/ 2, and C_L= 10 pF (unless otherwise noted)

V+

V+ ꢀ 1 V

V+ ꢀ 2 V

V+ ꢀ 3 V

V+ ꢀ 4 V

V+ ꢀ 5 V

V+ ꢀ 6 V

V+ ꢀ 7 V

V+ ꢀ 8 V

V+ ꢀ 9 V

V+ ꢀ 10 V

150

125

100

75

I_Bꢀ

I_B+

I_OS

50

25

0

-25

-50

-75

-100

-40°C

25°C

125°C

0

10

20

30

40

50

60

70

80

90 100

-40

-20

0

20

40

60

80

100 120 140

Output Current (mA)

D012

Temperature (°C)

D011

Figure 6-14. Output Voltage Swing vs Output Current (Sourcing)

Figure 6-13. Input Bias Current vs Temperature

Vꢀ + 8 V

135

-40°C

25°C

125°C

CMRR

PSRR+

PSRRꢀ

120

Vꢀ + 7 V

Vꢀ + 6 V

Vꢀ + 5 V

Vꢀ + 4 V

Vꢀ + 3 V

Vꢀ + 2 V

Vꢀ + 1 V

Vꢀ

105

90

75

60

45

30

15

0

10

20

30

40

50

60

70

80

90 100

Output Current (mA)

100

1k

10k

100k

1M

10M

D012

Frequency (Hz)

C003

Figure 6-15. Output Voltage Swing vs Output Current (Sinking)

Figure 6-16. CMRR and PSRR vs Frequency

135

130

125

120

170

165

160

155

150

145

140

115

PMOS (V_CMꢀ V+ ꢁ 1.5 V)

110

NMOS (V_CM V+ ꢁ 1.5 V)

105

100

95

90

85

-40

-20

0

20

40

60

80

100 120 140

-40 -20

0

20

40

60

80

100 120 140

Temperature (°C)

D015

D016

f = 0 Hz

Figure 6-17. CMRR vs Temperature (dB)

f = 0 Hz

Figure 6-18. PSRR vs Temperature (dB)

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6.8 Typical Characteristics (continued)

at T_A= 25°C, V_S= ±8 V, V_CM= V_S/ 2, R_LOAD= 10 kΩ connected to V_S/ 2, and C_L= 10 pF (unless otherwise noted)

1

0.8

0.6

0.4

0.2

0

200

100

10

-0.2

-0.4

-0.6

-0.8

-1

1

10

100

1k

10k

100k

Time (1s/div)

Frequency (Hz)

C017

C019

Figure 6-20. Input Voltage Noise Spectral Density vs Frequency

Figure 6-19. 0.1-Hz to 10-Hz Noise

-20

-30

-40

-50

-60

-70

-80

-32

-40

R_L= 10 kꢀ

R_L= 2 kꢀ

R_L= 604 ꢀ

R_L= 128 ꢀ

-48

-56

-64

-72

-80

-90

-88

R_L= 10 kꢀ

-100

R_L= 2 kꢀ

-96

R_L= 604 ꢀ

R_L= 128 ꢀ

-110

-104

-112

-120

1m

10m

100m

Amplitude (Vrms)

1

10

100

1k

10k

C023

Frequency (Hz)

C012

BW = 80 kHz, f = 1 kHz

Figure 6-22. THD+N vs Output Amplitude

BW = 80 kHz, V_OUT= 1 V_RMS

Figure 6-21. THD+N Ratio vs Frequency

580

570

560

550

540

530

520

510

500

490

480

700

675

650

625

600

575

550

525

500

475

450

2

4

6

8

10

12

14

16

18

-40

-20

0

20

40

60

80

100 120 140

Supply Voltage (V)

Temperature (°C)

D021

D022

Figure 6-24. Quiescent Current vs Temperature

V_CM= V–

Figure 6-23. Quiescent Current vs Supply Voltage

20

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6.8 Typical Characteristics (continued)

at T_A= 25°C, V_S= ±8 V, V_CM= V_S/ 2, R_LOAD= 10 kΩ connected to V_S/ 2, and C_L= 10 pF (unless otherwise noted)

140

135

130

125

120

115

700

650

600

550

500

450

400

350

300

250

200

150

V_S= 4 V

V_S= 16 V

-40

-20

0

20

40

60

80

100 120 140

100

1k

10k

100k

1M

10M

Temperature (°C)

D023

Frequency (Hz)

C013

Figure 6-25. Open-Loop Voltage Gain vs Temperature (dB)

Figure 6-26. Open-Loop Output Impedance vs Frequency

60

80

70

60

50

40

30

50

40

30

20

R_ISO= 0 ꢀ, Positive Overshoot

R_ISO= 0 ꢀ, Negative Overshoot

R_ISO= 50 ꢀ, Positive Overshoot

R_ISO= 50 ꢀ, Negative Overshoot

R_ISO= 0 ꢀ, Negative Overshoot

10

0

10

0

R_ISO= 50 ꢀ, Positive Overshoot

R_ISO= 50 ꢀ, Negative Overshoot

0

500 1000 1500 2000 2500 3000 3500 4000 4500 5000

0

500 1000 1500 2000 2500 3000 3500 4000 4500 5000

Cap Load (pF)

C007

C008

G = –1, 10-mV output step

G = 1, 10-mV output step

Figure 6-27. Small-Signal Overshoot vs Capacitive Load

Figure 6-28. Small-Signal Overshoot vs Capacitive Load

60

Input

Output

50

40

30

20

10

Time (20us/div)

0

500 1000 1500 2000 2500 3000 3500 4000 4500 5000

Cap Load (pF)

C016

C009

Figure 6-29. Phase Margin vs Capacitive Load

V_IN= ±8 V; V_S= V_OUT= ±17 V

Figure 6-30. No Phase Reversal

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6.8 Typical Characteristics (continued)

at T_A= 25°C, V_S= ±8 V, V_CM= V_S/ 2, R_LOAD= 10 kΩ connected to V_S/ 2, and C_L= 10 pF (unless otherwise noted)

Input

Output

Input

Output

Time (100ns/div)

C018

C010

C005

C018

C011

C005

G = –10

Figure 6-31. Positive Overload Recovery

Figure 6-32. Negative Overload Recovery

Input

Output

Input

Output

Time (300ns/div)

Time (1µs/div)

C_L= 20 pF, G = 1, 20-mV step response

Figure 6-34. Small-Signal Step Response, Falling

Figure 6-33. Small-Signal Step Response, Rising

Input

Output

Input

Output

Time (300ns/div)

C_L= 20 pF, G = 1

Figure 6-35. Large-Signal Step Response (Rising)

Figure 6-36. Large-Signal Step Response (Falling)

22

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6.8 Typical Characteristics (continued)

at T_A= 25°C, V_S= ±8 V, V_CM= V_S/ 2, R_LOAD= 10 kΩ connected to V_S/ 2, and C_L= 10 pF (unless otherwise noted)

100

80

60

Input

Output

40

20

Sourcing

Sinking

0

-20

-40

-60

-80

-100

Time (2µs/div)

-40 -20

0

20

40

60

80

100 120 140

Temperature (°C)

C021

D014

Figure 6-38. Short-Circuit Current vs Temperature

C_L= 20 pF, G = –1

Figure 6-37. Large-Signal Step Response

20

18

16

14

12

10

8

-50

V_S= 15 V

V_S= 2.7 V

-60

-70

-80

-90

-100

-110

-120

-130

6

4

2

0

1k

100

1k

10k

100k

1M

10M

10k

100k

1M

10M

Frequency (Hz)

C014

C020

Figure 6-40. Channel Separation vs Frequency

Figure 6-39. Maximum Output Voltage vs Frequency

110

100

90

80

70

60

50

40

1M

10M

100M

Frequency (Hz)

1G

C004

Figure 6-41. EMIRR (Electromagnetic Interference Rejection Ratio) vs Frequency

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7 Detailed Description

7.1 Overview

The TLV915x family (TLV9151, TLV9152, and TLV9154) is a family of 16-V general purpose operational

amplifiers.

These devices offer excellent DC precision and AC performance, including rail-to-rail input/output, low offset

(±125 µV, typ), low offset drift (±0.3 µV/°C, typ), and 4.5-MHz bandwidth.

Wide differential and common-mode input-voltage range, high output current (±80 mA), high slew rate (21 V/µs),

low power operation (560 µA, typ) and shutdown functionality make the TLV915x a robust, high-speed, high-

performance operational amplifier for industrial applications.

7.2 Functional Block Diagram

24

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7.3 Feature Description

7.3.1 EMI Rejection

The TLV915x uses integrated electromagnetic interference (EMI) filtering to reduce the effects of EMI from

sources such as wireless communications and densely-populated boards with a mix of analog signal chain and

digital components. EMI immunity can be improved with circuit design techniques; the TLV915x benefits from

these design improvements. Texas Instruments has developed the ability to accurately measure and quantify the

immunity of an operational amplifier over a broad frequency spectrum extending from 10 MHz to 6 GHz. Figure

7-1 shows the results of this testing on the TLV915x. Table 7-1 shows the EMIRR IN+ values for the TLV915x at

particular frequencies commonly encountered in real-world applications. The EMI Rejection Ratio of Operational

Amplifiers application report contains detailed information on the topic of EMIRR performance as it relates to op

amps and is available for download from www.ti.com.

100

90

80

70

60

50

40

30

1M

10M

100M

Frequency (Hz)

1G

C004

Figure 7-1. EMIRR Testing

Table 7-1. TLV9151 EMIRR IN+ for Frequencies of Interest

FREQUENCY

APPLICATION OR ALLOCATION

EMIRR IN+

Mobile radio, mobile satellite, space operation, weather, radar, ultra-high frequency (UHF)

applications

400 MHz

59.5 dB

Global system for mobile communications (GSM) applications, radio communication, navigation,

GPS (to 1.6 GHz), GSM, aeronautical mobile, UHF applications

900 MHz

1.8 GHz

2.4 GHz

3.6 GHz

5 GHz

68.9 dB

77.8 dB

78.0 dB

88.8 dB

87.6 dB

GSM applications, mobile personal communications, broadband, satellite, L-band (1 GHz to 2 GHz)

802.11b, 802.11g, 802.11n, Bluetooth^®, mobile personal communications, industrial, scientific and

medical (ISM) radio band, amateur radio and satellite, S-band (2 GHz to 4 GHz)

Radiolocation, aero communication and navigation, satellite, mobile, S-band

802.11a, 802.11n, aero communication and navigation, mobile communication, space and satellite

operation, C-band (4 GHz to 8 GHz)

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7.3.2 Thermal Protection

The internal power dissipation of any amplifier causes its internal (junction) temperature to rise. This

phenomenon is called self heating. The absolute maximum junction temperature of the TLV915x is 150°C.

Exceeding this temperature causes damage to the device. The TLV915x has a thermal protection feature that

reduces damage from self heating. The protection works by monitoring the temperature of the device and turning

off the op amp output drive for temperatures above 170°C. Figure 7-2 shows an application example for the

TLV9151 that has significant self heating because of its power dissipation (0.81 W). Thermal calculations

indicate that for an ambient temperature of 65°C, the device junction temperature must reach 177°C. The actual

device, however, turns off the output drive to recover towards a safe junction temperature. Figure 7-2 shows how

the circuit behaves during thermal protection. During normal operation, the device acts as a buffer so the output

is 3 V. When self heating causes the device junction temperature to increase above the internal limit, the thermal

protection forces the output to a high-impedance state and the output is pulled to ground through resistor R_L. If

the condition that caused excessive power dissipation is not removed, the amplifier will oscillate between a

shutdown and enabled state until the output fault is corrected.

Normal

Operation

3 V

T_A= 100°C

16 V

P_D= 0.39W

_JA= 138.7°C/W

T_J= 138.7°C/W × 0.39W + 100°C

T_J= 154.1°C (expected)

Output

High-Z

0 V

ꢀ

150°C

140ºC

TLV9151

ꢁ

I_OUT= 30 mA

+

3 V

–

RL

100

+

–

V_IN

3 V

Figure 7-2. Thermal Protection

7.3.3 Capacitive Load and Stability

The TLV915x features a resistive output stage capable of driving moderate capacitive loads, and by leveraging

an isolation resistor, the device can easily be configured to drive large capacitive loads. Increasing the gain

enhances the ability of the amplifier to drive greater capacitive loads; see Figure 7-3 and Figure 7-4. The

particular op amp circuit configuration, layout, gain, and output loading are some of the factors to consider when

establishing whether an amplifier will be stable in operation.

55

50

45

40

35

30

25

20

15

10

5

33

30

27

24

21

18

15

12

9

R_ISO= 0 W, Positive Overshoot

R_ISO= 0 W, Negative Overshoot

R_ISO= 50 W, Positive Overshoot

R_ISO= 50 W, Negative Overshoot

R_ISO= 0 W, Positive Overshoot

R_ISO= 0 W, Negative Overshoot

R_ISO= 50 W, Positive Overshoot

R_ISO= 50 W, Negative Overshoot

6

3

0

40

80

120 160 200 240 280 320 360

Cap Load (pF)

0

40

80

120 160 200 240 280 320 360

Cap Load (pF)

C008

C007

Figure 7-3. Small-Signal Overshoot vs Capacitive

Load (10-mV Output Step, G = 1)

Figure 7-4. Small-Signal Overshoot vs Capacitive

Load (10-mV Output Step, G = –1)

For additional drive capability in unity-gain configurations, improve capacitive load drive by inserting a small

resistor, R_ISO, in series with the output, as shown in Figure 7-5. This resistor significantly reduces ringing and

maintains DC performance for purely capacitive loads. However, if a resistive load is in parallel with the

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capacitive load, then a voltage divider is created, thus introducing a gain error at the output and slightly reducing

the output swing. The error introduced is proportional to the ratio R_ISO/ R_L, and is generally negligible at low

output levels. A high capacitive load drive makes the TLV915x well suited for applications such as reference

buffers, MOSFET gate drives, and cable-shield drives. The circuit shown in Figure 7-5 uses an isolation resistor,

R_ISO, to stabilize the output of an op amp. R_ISOmodifies the open-loop gain of the system for increased phase

margin.

+V_s

V_out

R_iso

+

C_load

+

V_in

-V_s

œ

Figure 7-5. Extending Capacitive Load Drive With the TLV9151

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7.3.4 Common-Mode Voltage Range

The TLV915x is a 16-V, rail-to-rail input operational amplifier with an input common-mode range that extends 200

mV beyond either supply rail. This wide range is achieved with paralleled complementary N-channel and P-

channel differential input pairs, as shown in Figure 7-6. The N-channel pair is active for input voltages close to

the positive rail, typically (V+) – 1 V to 100 mV above the positive supply. The P-channel pair is active for inputs

from 100 mV below the negative supply to approximately (V+) – 2 V. There is a small transition region, typically

(V+) – 2 V to (V+) – 1 V in which both input pairs are on. This transition region can vary modestly with process

variation, and within this region PSRR, CMRR, offset voltage, offset drift, noise, and THD performance may be

degraded compared to operation outside this region.

Figure 6-5 shows this transition region for a typical device in terms of input voltage offset in more detail.

For more information on common-mode voltage range and PMOS/NMOS pair interaction, see Op Amps With

Complementary-Pair Input Stages application note.

V+

IN-

PMOS

NMOS

IN+

NMOS

V-

Figure 7-6. Rail-to-Rail Input Stage

7.3.5 Phase Reversal Protection

The TLV915x family has internal phase-reversal protection. Many op amps exhibit a phase reversal when the

input is driven beyond its linear common-mode range. This condition is most often encountered in non-inverting

circuits when the input is driven beyond the specified common-mode voltage range, causing the output to

reverse into the opposite rail. The TLV915x is a rail-to-rail input op amp; therefore, the common-mode range can

extend up to the rails. Input signals beyond the rails do not cause phase reversal; instead, the output limits into

the appropriate rail. This performance is shown in Figure 7-7. For more information on phase reversal, see Op

Amps With Complementary-Pair Input Stages application note.

Input

Output

Time (20us/div)

C016

Figure 7-7. No Phase Reversal

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7.3.6 Electrical Overstress

Designers often ask questions about the capability of an operational amplifier to withstand electrical overstress

(EOS). These questions tend to focus on the device inputs, but may involve the supply voltage pins or even the

output pin. Each of these different pin functions have electrical stress limits determined by the voltage

breakdown characteristics of the particular semiconductor fabrication process and specific circuits connected to

the pin. Additionally, internal electrostatic discharge (ESD) protection is built into these circuits to protect them

from accidental ESD events both before and during product assembly.

Having a good understanding of this basic ESD circuitry and its relevance to an electrical overstress event is

helpful. Figure 7-8 shows an illustration of the ESD circuits contained in the TLV915x (indicated by the dashed

line area). The ESD protection circuitry involves several current-steering diodes connected from the input and

output pins and routed back to the internal power-supply lines, where the diodes meet at an absorption device or

the power-supply ESD cell, internal to the operational amplifier. This protection circuitry is intended to remain

inactive during normal circuit operation.

TVS

R_F

+V_S

V_DD

TLV915x

100

R₁

R_S

IN–

IN+

–

+

Power Supply

ESD Cell

R_L

I_D

+

–

V_IN

V_SS

–V_S

TVS

Figure 7-8. Equivalent Internal ESD Circuitry Relative to a Typical Circuit Application

An ESD event is very short in duration and very high voltage (for example; 1 kV, 100 ns), whereas an EOS event

is long duration and lower voltage (for example; 50 V, 100 ms). The ESD diodes are designed for out-of-circuit

ESD protection (that is, during assembly, test, and storage of the device before being soldered to the PCB).

During an ESD event, the ESD signal is passed through the ESD steering diodes to an absorption circuit

(labeled ESD power-supply circuit). The ESD absorption circuit clamps the supplies to a safe level.

Although this behavior is necessary for out-of-circuit protection, excessive current and damage is caused if

activated in-circuit. A transient voltage suppressors (TVS) can be used to prevent against damage caused by

turning on the ESD absorption circuit during an in-circuit ESD event. Using the appropriate current limiting

resistors and TVS diodes allows for the use of device ESD diodes to protect against EOS events.

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7.3.7 Overload Recovery

Overload recovery is defined as the time required for the op amp output to recover from a saturated state to a

linear state. The output devices of the op amp enter a saturation region when the output voltage exceeds the

rated operating voltage, either due to the high input voltage or the high gain. After the device enters the

saturation region, the charge carriers in the output devices require time to return back to the linear state. After

the charge carriers return back to the linear state, the device begins to slew at the specified slew rate. Thus, the

propagation delay in case of an overload condition is the sum of the overload recovery time and the slew time.

The overload recovery time for the TLV915x is approximately 500 ns.

7.3.8 Typical Specifications and Distributions

Designers often have questions about a typical specification of an amplifier in order to design a more robust

circuit. Due to natural variation in process technology and manufacturing procedures, every specification of an

amplifier will exhibit some amount of deviation from the ideal value, like an amplifier's input offset voltage. These

deviations often follow Gaussian ("bell curve"), or normal distributions, and circuit designers can leverage this

information to guardband their system, even when there is not a minimum or maximum specification in the

Electrical Characteristics table.

0.00312% 0.13185%

0.13185% 0.00312%

0.00002%

2.145% 13.59% 34.13% 34.13% 13.59% 2.145%

1

1 1 1 1 1 1 1 1

1

ꢀ-61 ꢀ-51 ꢀ-41 ꢀ-31 ꢀ-21 ꢀ-1

ꢀ+1 ꢀ+21 ꢀ+31 ꢀ+41 ꢀ+51 ꢀ+61

ꢀ

Figure 7-9. Ideal Gaussian Distribution

Figure 7-9 shows an example distribution, where µ, or mu, is the mean of the distribution, and where σ, or

sigma, is the standard deviation of a system. For a specification that exhibits this kind of distribution,

approximately two-thirds (68.26%) of all units can be expected to have a value within one standard deviation, or

one sigma, of the mean (from µ – σ to µ + σ).

Depending on the specification, values listed in the typical column of the Electrical Characteristics table are

represented in different ways. As a general rule of thumb, if a specification naturally has a nonzero mean (for

example, like gain bandwidth), then the typical value is equal to the mean (µ). However, if a specification

naturally has a mean near zero (like input offset voltage), then the typical value is equal to the mean plus one

standard deviation (µ + σ) in order to most accurately represent the typical value.

You can use this chart to calculate approximate probability of a specification in a unit; for example, for TLV915x,

the typical input voltage offset is 125 µV, so 68.2% of all TLV915x devices are expected to have an offset from –

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125 µV to 125 µV. At 4 σ (±500 µV), 99.9937% of the distribution has an offset voltage less than ±500 µV, which

means 0.0063% of the population is outside of these limits, which corresponds to about 1 in 15,873 units.

Specifications with a value in the minimum or maximum column are assured by TI, and units outside these limits

will be removed from production material. For example, the TLV915x family has a maximum offset voltage of 675

µV at 25°C, and even though this corresponds to about 5 σ (≈1 in 1.7 million units), which is extremely unlikely,

TI assures that any unit with larger offset than 675 µV will be removed from production material.

For specifications with no value in the minimum or maximum column, consider selecting a sigma value of

sufficient guardband for your application, and design worst-case conditions using this value. For example, the 6-

σ value corresponds to about 1 in 500 million units, which is an extremely unlikely chance, and could be an

option as a wide guardband to design a system around. In this case, the TLV915x family does not have a

maximum or minimum for offset voltage drift, but based on Figure 6-2 and the typical value of 0.3 µV/°C in the

Electrical Characteristics table, it can be calculated that the 6 σ value for offset voltage drift is about 1.8 µV/°C.

When designing for worst-case system conditions, this value can be used to estimate the worst possible offset

across temperature without having an actual minimum or maximum value.

However, process variation and adjustments over time can shift typical means and standard deviations, and

unless there is a value in the minimum or maximum specification column, TI cannot assure the performance of a

device. This information should be used only to estimate the performance of a device.

7.3.9 Packages With an Exposed Thermal Pad

The TLV915x family is available in packages such as the WSON-8 (DSG) and WQFN-16 (RTE) which feature an

exposed thermal pad. Inside the package, the die is attached to this thermal pad using an electrically conductive

compound. For this reason, when using a package with an exposed thermal pad, the thermal pad must either be

connected to V– or left floating. Attaching the thermal pad to a potential other than V– is not allowed, and

performance of the device is not assured when doing so.

7.3.10 Shutdown

The TLV915xS devices feature one or more shutdown pins (SHDN) that disable the op amp, placing it into a low-

power standby mode. In this mode, the op amp typically consumes about 20 µA. The SHDN pins are active high,

meaning that shutdown mode is enabled when the input to the SHDN pin is a valid logic high.

The SHDN pins are referenced to the negative supply rail of the op amp. The threshold of the shutdown feature

lies around 800 mV (typical) and does not change with respect to the supply voltage. Hysteresis has been

included in the switching threshold to ensure smooth switching characteristics. To ensure optimal shutdown

behavior, the SHDN pins should be driven with valid logic signals. A valid logic low is defined as a voltage

between V– and V– + 0.4 V. A valid logic high is defined as a voltage between V– + 1.2 V and V– + 20 V. The

shutdown pin circuitry includes a pull-down resistor, which will inherently pull the voltage of the pin to the

negative supply rail if not driven. Thus, to enable the amplifier, the SHDN pins should either be left floating or

driven to a valid logic low. To disable the amplifier, the SHDN pins must be driven to a valid logic high. The

maximum voltage allowed at the SHDN pins is V– + 20 V. Exceeding this voltage level will damage the device.

The SHDN pins are high-impedance CMOS inputs. Channels of single and dual op amp packages are

independently controlled, and channels of quad op amp packages are controlled in pairs. For battery-operated

applications, this feature may be used to greatly reduce the average current and extend battery life. The typical

enable time out of shutdown is 30 µs; disable time is 3 µs. When disabled, the output assumes a high-

impedance state. This architecture allows the TLV915xS family to operate as a gated amplifier, multiplexer, or

programmable-gain amplifier. Shutdown time (t_OFF) depends on loading conditions and increases as load

resistance increases. To ensure shutdown (disable) within a specific shutdown time, the specified 10-kΩ load to

midsupply (V_S/ 2) is required. If using the TLV915xS without a load, the resulting turnoff time significantly

increases.

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7.4 Device Functional Modes

The TLV915x has a single functional mode and is operational when the power-supply voltage is greater than 2.7

V (±1.35 V). The maximum power supply voltage for the TLV915x is 16 V (±8 V).

The TLV915xS devices feature a shutdown pin, which can be used to place the op amp into a low-power mode.

See Shutdown section for more information.

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8 Application and Implementation

Note

Information in the following applications sections is not part of the TI component specification, and TI

does not warrant its accuracy or completeness. TI’s customers are responsible for determining

suitability of components for their purposes, as well as validating and testing their design

implementation to confirm system functionality.

8.1 Application Information

The TLV915x family offers excellent DC precision and DC performance. These devices operate up to 16-V

supply rails and offer true rail-to-rail input/output, low offset voltage and offset voltage drift, as well as 4.5-MHz

bandwidth and high output drive. These features make the TLV915x a robust, high-performance operational

amplifier for high-voltage industrial applications.

8.2 Typical Applications

8.2.1 Low-Side Current Measurement

Figure 8-1 shows the TLV9151 configured in a low-side current sensing application. For a full analysis of the

circuit shown in Figure 8-1 including theory, calculations, simulations, and measured data, see TI Precision

Design TIPD129, 0-A to 1-A Single-Supply Low-Side Current-Sensing Solution.

V_CC

12 V

LOAD

TLV9151

+

V_OUT

–

R_SHUNT

I_LOAD

100 m

LM7705

R_F

360 k

R_G

7.5 k

Figure 8-1. TLV9151 in a Low-Side, Current-Sensing Application

8.2.1.1 Design Requirements

The design requirements for this design are:

•

Load current: 0 A to 1 A

Output voltage: 4.9 V

Maximum shunt voltage: 100 mV

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8.2.1.2 Detailed Design Procedure

The transfer function of the circuit in Figure 8-1 is given in Equation 1.

V_OUT= I_LOADìR_SHUNTìGain

(1)

The load current (I_LOAD) produces a voltage drop across the shunt resistor (R_SHUNT). The load current is set from

0 A to 1 A. To keep the shunt voltage below 100 mV at maximum load current, the largest shunt resistor is

defined using Equation 2.

V_{SHUNT _MAX}

100mV

1A

R_SHUNT

=

=100mW

I_{LOAD_MAX}

(2)

Using Equation 2, R_SHUNTis calculated to be 100 mΩ. The voltage drop produced by I_LOADand R_SHUNTis

amplified by the TLV9151 to produce an output voltage of 0 V to 4.9 V. The gain needed by the TLV9151 to

produce the necessary output voltage is calculated using Equation 3.

V

_{OUT _MAX}- V_{OUT _MIN}

(

)

Gain =

V_{IN_MAX}- V

(

)

IN_MIN

(3)

Using Equation 3, the required gain is calculated to be 49 V/V, which is set with resistors R_Fand R_G. Equation 4

is used to size the resistors, R_Fand R_G, to set the gain of the TLV9151 to 49 V/V.

R

(

)

F

Gain = 1+

R

G

(4)

Choosing R_Fas 360 kΩ, R_Gis calculated to be 7.5 kΩ. R_Fand R_Gwere chosen as 360 kΩ and 7.5 kΩ because

they are standard value resistors that create a 49:1 ratio. Other resistors that create a 49:1 ratio can also be

used. Figure 8-2 shows the measured transfer function of the circuit shown in Figure 8-1.

8.2.1.3 Application Curves

5

4

3

2

1

0

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

I_LOAD(A)

1

Figure 8-2. Low-Side, Current-Sense, Transfer Function

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9 Power Supply Recommendations

The TLV915x is specified for operation from 2.7 V to 16 V (±1.35 V to ±8 V); many specifications apply from –

40°C to 125°C. Parameters that can exhibit significant variance with regard to operating voltage or temperature

are presented in the Typical Characteristics.

CAUTION

Supply voltages larger than 16 V can permanently damage the device; see the Absolute Maximum

Ratings.

Place 0.1-µF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or high-

impedance power supplies. For more detailed information on bypass capacitor placement, refer to the Layout

section.

10 Layout

10.1 Layout Guidelines

For best operational performance of the device, use good PCB layout practices, including:

•

Noise can propagate into analog circuitry through the power pins of the circuit as a whole and op amp itself.

Bypass capacitors are used to reduce the coupled noise by providing low-impedance power sources local to

the analog circuitry.

– Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as

close to the device as possible. A single bypass capacitor from V+ to ground is applicable for single-

supply applications.

•

Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective

methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes.

A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically separate digital

and analog grounds paying attention to the flow of the ground current.

In order to reduce parasitic coupling, run the input traces as far away from the supply or output traces as

possible. If these traces cannot be kept separate, crossing the sensitive trace perpendicular is much better as

opposed to in parallel with the noisy trace.

•

Place the external components as close to the device as possible. As illustrated in Figure 10-2, keeping RF

and RG close to the inverting input minimizes parasitic capacitance.

Keep the length of input traces as short as possible. Always remember that the input traces are the most

sensitive part of the circuit.

Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce

leakage currents from nearby traces that are at different potentials.

•

Cleaning the PCB following board assembly is recommended for best performance.

Any precision integrated circuit may experience performance shifts due to moisture ingress into the plastic

package. Following any aqueous PCB cleaning process, baking the PCB assembly is recommended to

remove moisture introduced into the device packaging during the cleaning process. A low temperature, post

cleaning bake at 85°C for 30 minutes is sufficient for most circumstances.

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10.2 Layout Example

VIN

+

VOUT

RG

RF

Figure 10-1. Schematic Representation

Place components close

to device and to each

other to reduce parasitic

errors

Run the input traces

as far away from

the supply lines

as possible

VS+

RF

NC

Use a low-ESR,

ceramic bypass

capacitor

RG

GND

œIN

+IN

Vœ

V+

OUTPUT

NC

VIN

GND

VSœ

VOUT

Ground (GND) plane on another layer

Use low-ESR,

ceramic bypass

capacitor

Figure 10-2. Operational Amplifier Board Layout for Noninverting Configuration

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11 Device and Documentation Support

11.1 Device Support

11.1.1 Development Support

11.1.1.1 TINA-TI^™(Free Software Download)

TINA^™is a simple, powerful, and easy-to-use circuit simulation program based on a SPICE engine. TINA-TI is a

free, fully-functional version of the TINA software, preloaded with a library of macro models in addition to a range

of both passive and active models. TINA-TI provides all the conventional dc, transient, and frequency domain

analysis of SPICE, as well as additional design capabilities.

Available as a free download from the Analog eLab Design Center, TINA-TI offers extensive post-processing

capability that allows users to format results in a variety of ways. Virtual instruments offer the ability to select

input waveforms and probe circuit nodes, voltages, and waveforms, creating a dynamic quick-start tool.

Note

These files require that either the TINA software (from DesignSoft^™) or TINA-TI software be installed.

Download the free TINA-TI software from the TINA-TI folder.

11.1.1.2 TI Precision Designs

The TLV915x is featured in several TI Precision Designs, available online at http://www.ti.com/ww/en/analog/

precision-designs/. TI Precision Designs are analog solutions created by TI’s precision analog applications

experts and offer the theory of operation, component selection, simulation, complete PCB schematic and layout,

bill of materials, and measured performance of many useful circuits.

11.2 Documentation Support

11.2.1 Related Documentation

Texas Instruments, Analog Engineer's Circuit Cookbook: Amplifiers.

Texas Instruments, AN31 amplifier circuit collection.

11.3 Related Links

The table below lists quick access links. Categories include technical documents, support and community

resources, tools and software, and quick access to order now.

Table 11-1. Related Links

TECHNICAL

DOCUMENTS

TOOLS &

SOFTWARE

SUPPORT &

COMMUNITY

PARTS

PRODUCT FOLDER

ORDER NOW

TLV9152

Click here

11.4 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on

Subscribe to updates to register and receive a weekly digest of any product information that has changed. For

change details, review the revision history included in any revised document.

11.5 Support Resources

TI E2E^™support forums are an engineer's go-to source for fast, verified answers and design help — straight

from the experts. Search existing answers or ask your own question to get the quick design help you need.

Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do

not necessarily reflect TI's views; see TI's Terms of Use.

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11.6 Trademarks

TINA-TI^™are trademarks of Texas Instruments, Inc and DesignSoft, Inc.

TINA^™and DesignSoft^™are trademarks of DesignSoft, Inc.

TI E2E^™is a trademark of Texas Instruments.

Bluetooth^®is a registered trademark of Bluetooth SIG, Inc.

All trademarks are the property of their respective owners.

11.7 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric changes could cause the device not to meet its published

specifications.

11.8 Glossary

TI Glossary

This glossary lists and explains terms, acronyms, and definitions.

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Product Folder Links: TLV9151 TLV9152 TLV9154

TLV9151, TLV9152, TLV9154

SBOS986C – OCTOBER 2019 – REVISED DECEMBER 2020

www.ti.com

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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39

Product Folder Links: TLV9151 TLV9152 TLV9154

PACKAGE MATERIALS INFORMATION

www.ti.com

27-Jan-2021

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

TLV9151IDBVR

TLV9151SIDBVR

TLV9152IDDFR

SOT-23

DBV

DDF

5

6

8

3000

180.0

8.4

3.2

1.4

4.0

8.0

Q3

SOT-

23-THIN

TLV9152IDR

TLV9152IDSGR

TLV9152IPWR

TLV9152SIRUGR

TLV9154IDR

SOIC

WSON

TSSOP

X2QFN

SOIC

D

8

2500

3000

2000

3000

2500

2000

3000

330.0

180.0

330.0

178.0

330.0

180.0

12.4

8.4

6.4

2.3

5.2

2.3

2.1

1.15

1.6

8.0

4.0

8.0

4.0

8.0

4.0

12.0

8.0

Q1

Q2

Q1

Q2

DSG

PW

RUG

D

8

12.4

8.4

7.0

3.6

12.0

8.0

10

14

1.75

6.5

2.25

9.0

0.56

2.1

16.4

12.4

9.5

16.0

12.0

8.0

TLV9154IPWR

TLV9154IRUCR

TSSOP

QFN

PW

RUC

6.9

5.6

1.6

2.16

0.5

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

27-Jan-2021

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

TLV9151IDBVR

TLV9151SIDBVR

TLV9152IDDFR

TLV9152IDR

SOT-23

SOT-23-THIN

SOIC

DBV

DDF

D

5

6

3000

2500

3000

2000

3000

2500

2000

3000

210.0

853.0

210.0

853.0

205.0

853.0

366.0

205.0

185.0

449.0

185.0

449.0

200.0

449.0

364.0

200.0

35.0

33.0

35.0

50.0

30.0

8

TLV9152IDSGR

TLV9152IPWR

TLV9152SIRUGR

TLV9154IDR

WSON

DSG

PW

RUG

D

8

TSSOP

X2QFN

SOIC

8

10

14

TLV9154IPWR

TLV9154IRUCR

TSSOP

QFN

PW

RUC

Pack Materials-Page 2

PACKAGE OUTLINE

DDF0008A

SOT-23 - 1.1 mm max height

S

C

A

L

E

4

.

0

PLASTIC SMALL OUTLINE

C

2.95

2.65

SEATING PLANE

TYP

PIN 1 ID

AREA

0.1 C

A

6X 0.65

8

1

2.95

2.85

NOTE 3

2X

1.95

4

5

0.4

0.2

8X

0.1

C A

B

1.65

1.55

B

1.1 MAX

0.20

0.08

TYP

SEE DETAIL A

0.25

GAGE PLANE

0.1

0.0

0 - 8

0.6

0.3

DETAIL A

TYPICAL

4222047/B 11/2015

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed 0.15 mm per side.

www.ti.com

EXAMPLE BOARD LAYOUT

DDF0008A

SOT-23 - 1.1 mm max height

PLASTIC SMALL OUTLINE

8X (1.05)

SYMM

1

8

8X (0.45)

SYMM

6X (0.65)

5

4

(R0.05)

TYP

(2.6)

LAND PATTERN EXAMPLE

SCALE:15X

SOLDER MASK

OPENING

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

METAL

SOLDER MASK

DEFINED

NON SOLDER MASK

DEFINED

SOLDER MASK DETAILS

4222047/B 11/2015

NOTES: (continued)

4. Publication IPC-7351 may have alternate designs.

5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com

EXAMPLE STENCIL DESIGN

DDF0008A

SOT-23 - 1.1 mm max height

PLASTIC SMALL OUTLINE

8X (1.05)

SYMM

(R0.05) TYP

8

1

8X (0.45)

SYMM

6X (0.65)

5

4

(2.6)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

SCALE:15X

4222047/B 11/2015

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

7. Board assembly site may have different recommendations for stencil design.

www.ti.com

PACKAGE OUTLINE

DBV0006A

SOT-23 - 1.45 mm max height

S

C

A

L

E

4

.

0

SMALL OUTLINE TRANSISTOR

C

3.0

2.6

0.1 C

1.75

1.45

B

1.45 MAX

A

PIN 1

INDEX AREA

1

2

6

5

2X 0.95

1.9

3.05

2.75

4

3

0.50

6X

0.25

C A B

0.15

0.00

0.2

(1.1)

TYP

0.25

GAGE PLANE

0.22

0.08

TYP

8

TYP

0

0.6

0.3

TYP

SEATING PLANE

4214840/B 03/2018

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. Body dimensions do not include mold flash or protrusion. Mold flash and protrusion shall not exceed 0.15 per side.

4. Leads 1,2,3 may be wider than leads 4,5,6 for package orientation.

5. Refernce JEDEC MO-178.

www.ti.com

EXAMPLE BOARD LAYOUT

DBV0006A

SOT-23 - 1.45 mm max height

SMALL OUTLINE TRANSISTOR

PKG

6X (1.1)

1

6X (0.6)

6

SYMM

5

2

3

2X (0.95)

4

(R0.05) TYP

(2.6)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:15X

SOLDER MASK

OPENING

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

METAL

EXPOSED METAL

0.07 MIN

ARROUND

0.07 MAX

ARROUND

NON SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4214840/B 03/2018

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com

EXAMPLE STENCIL DESIGN

DBV0006A

SOT-23 - 1.45 mm max height

SMALL OUTLINE TRANSISTOR

PKG

6X (1.1)

1

6X (0.6)

6

SYMM

5

2

3

2X(0.95)

4

(R0.05) TYP

(2.6)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

SCALE:15X

4214840/B 03/2018

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

9. Board assembly site may have different recommendations for stencil design.

www.ti.com

PACKAGE OUTLINE

DBV0005A

SOT-23 - 1.45 mm max height

S

C

A

L

E

4

.

0

SMALL OUTLINE TRANSISTOR

C

3.0

2.6

0.1 C

1.75

1.45

0.90

B

A

PIN 1

INDEX AREA

1

2

5

2X 0.95

1.9

3.05

2.75

1.9

4

3

0.5

5X

0.3

0.15

0.00

(1.1)

TYP

0.2

C A B

0.25

GAGE PLANE

0.22

0.08

TYP

8

0

TYP

0.6

0.3

TYP

SEATING PLANE

4214839/E 09/2019

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. Refernce JEDEC MO-178.

4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed 0.15 mm per side.

www.ti.com

EXAMPLE BOARD LAYOUT

DBV0005A

SOT-23 - 1.45 mm max height

SMALL OUTLINE TRANSISTOR

PKG

5X (1.1)

1

5

5X (0.6)

SYMM

(1.9)

2

3

2X (0.95)

4

(R0.05) TYP

(2.6)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:15X

SOLDER MASK

OPENING

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

METAL

EXPOSED METAL

0.07 MIN

ARROUND

0.07 MAX

ARROUND

NON SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4214839/E 09/2019

NOTES: (continued)

5. Publication IPC-7351 may have alternate designs.

6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com

EXAMPLE STENCIL DESIGN

DBV0005A

SOT-23 - 1.45 mm max height

SMALL OUTLINE TRANSISTOR

PKG

5X (1.1)

1

5

5X (0.6)

SYMM

(1.9)

2

3

2X(0.95)

4

(R0.05) TYP

(2.6)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

SCALE:15X

4214839/E 09/2019

NOTES: (continued)

7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

8. Board assembly site may have different recommendations for stencil design.

www.ti.com

PACKAGE OUTLINE

D0008A

SOIC - 1.75 mm max height

SCALE 2.800

SMALL OUTLINE INTEGRATED CIRCUIT

C

SEATING PLANE

.228-.244 TYP

[5.80-6.19]

.004 [0.1] C

A

PIN 1 ID AREA

6X .050

[1.27]

8

1

2X

.189-.197

[4.81-5.00]

NOTE 3

.150

[3.81]

4X (0 -15 )

4

5

8X .012-.020

[0.31-0.51]

B

.150-.157

[3.81-3.98]

NOTE 4

.069 MAX

[1.75]

.010 [0.25]

C A B

.005-.010 TYP

[0.13-0.25]

4X (0 -15 )

SEE DETAIL A

.010

[0.25]

.004-.010

[0.11-0.25]

0 - 8

.016-.050

[0.41-1.27]

DETAIL A

TYPICAL

(.041)

[1.04]

4214825/C 02/2019

NOTES:

1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.

Dimensioning and tolerancing per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed .006 [0.15] per side.

4. This dimension does not include interlead flash.

5. Reference JEDEC registration MS-012, variation AA.

www.ti.com

EXAMPLE BOARD LAYOUT

D0008A

SOIC - 1.75 mm max height

SMALL OUTLINE INTEGRATED CIRCUIT

8X (.061 )

[1.55]

SYMM

SEE

DETAILS

1

8

8X (.024)

[0.6]

SYMM

(R.002 ) TYP

[0.05]

5

4

6X (.050 )

[1.27]

(.213)

[5.4]

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:8X

SOLDER MASK

OPENING

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

METAL

EXPOSED

METAL

EXPOSED

METAL

.0028 MAX

[0.07]

.0028 MIN

[0.07]

ALL AROUND

SOLDER MASK

DEFINED

NON SOLDER MASK

DEFINED

SOLDER MASK DETAILS

4214825/C 02/2019

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com

EXAMPLE STENCIL DESIGN

D0008A

SOIC - 1.75 mm max height

SMALL OUTLINE INTEGRATED CIRCUIT

8X (.061 )

[1.55]

SYMM

1

8

8X (.024)

[0.6]

SYMM

(R.002 ) TYP

[0.05]

5

4

6X (.050 )

[1.27]

(.213)

[5.4]

SOLDER PASTE EXAMPLE

BASED ON .005 INCH [0.125 MM] THICK STENCIL

SCALE:8X

4214825/C 02/2019

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

9. Board assembly site may have different recommendations for stencil design.

www.ti.com

GENERIC PACKAGE VIEW

DSG 8

2 x 2, 0.5 mm pitch

WSON - 0.8 mm max height

PLASTIC SMALL OUTLINE - NO LEAD

This image is a representation of the package family, actual package may vary.

Refer to the product data sheet for package details.

4224783/A

www.ti.com

PACKAGE OUTLINE

DSG0008A

WSON - 0.8 mm max height

SCALE 5.500

PLASTIC SMALL OUTLINE - NO LEAD

2.1

1.9

B

A

PIN 1 INDEX AREA

2.1

1.9

0.32

0.18

0.4

0.2

ALTERNATIVE TERMINAL SHAPE

TYPICAL

C

0.8 MAX

SEATING PLANE

0.08 C

0.05

0.00

EXPOSED

THERMAL PAD

(0.2) TYP

0.9 0.1

5

4

6X 0.5

2X

1.5

9

1.6 0.1

8

1

0.32

0.18

8X

0.4

0.2

PIN 1 ID

8X

0.1

C A B

C

0.05

4218900/D 04/2020

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

www.ti.com

EXAMPLE BOARD LAYOUT

DSG0008A

WSON - 0.8 mm max height

PLASTIC SMALL OUTLINE - NO LEAD

(0.9)

(

0.2) VIA

8X (0.5)

TYP

1

8

8X (0.25)

(0.55)

SYMM

9

(1.6)

6X (0.5)

5

4

SYMM

(1.9)

(R0.05) TYP

LAND PATTERN EXAMPLE

SCALE:20X

0.07 MIN

ALL AROUND

0.07 MAX

ALL AROUND

SOLDER MASK

OPENING

METAL

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

NON SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4218900/D 04/2020

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

www.ti.com

EXAMPLE STENCIL DESIGN

DSG0008A

WSON - 0.8 mm max height

PLASTIC SMALL OUTLINE - NO LEAD

8X (0.5)

METAL

8

SYMM

1

8X (0.25)

(0.45)

SYMM

9

(0.7)

6X (0.5)

5

4

(R0.05) TYP

(0.9)

(1.9)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD 9:

87% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE

SCALE:25X

4218900/D 04/2020

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

PACKAGE OUTLINE

PW0008A

TSSOP - 1.2 mm max height

S

C

A

L

E

2

.

8

0

SMALL OUTLINE PACKAGE

C

6.6

6.2

SEATING PLANE

TYP

PIN 1 ID

AREA

A

0.1 C

6X 0.65

8

5

1

3.1

2.9

NOTE 3

2X

1.95

4

0.30

0.19

8X

4.5

4.3

1.2 MAX

B

0.1

C A

B

NOTE 4

(0.15) TYP

SEE DETAIL A

0.25

GAGE PLANE

0.15

0.05

0.75

0.50

0 - 8

DETAIL A

TYPICAL

4221848/A 02/2015

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed 0.15 mm per side.

4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.

5. Reference JEDEC registration MO-153, variation AA.

www.ti.com

EXAMPLE BOARD LAYOUT

PW0008A

TSSOP - 1.2 mm max height

SMALL OUTLINE PACKAGE

8X (1.5)

SYMM

8X (0.45)

(R0.05)

1

4

TYP

8

SYMM

6X (0.65)

5

(5.8)

LAND PATTERN EXAMPLE

SCALE:10X

SOLDER MASK

OPENING

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

METAL

0.05 MAX

ALL AROUND

0.05 MIN

ALL AROUND

SOLDER MASK

DEFINED

NON SOLDER MASK

DEFINED

SOLDER MASK DETAILS

NOT TO SCALE

4221848/A 02/2015

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com

EXAMPLE STENCIL DESIGN

PW0008A

TSSOP - 1.2 mm max height

SMALL OUTLINE PACKAGE

8X (1.5)

SYMM

(R0.05) TYP

8X (0.45)

1

4

8

SYMM

6X (0.65)

5

(5.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

SCALE:10X

4221848/A 02/2015

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

9. Board assembly site may have different recommendations for stencil design.

www.ti.com

PACKAGE OUTLINE

X2QFN - 0.4 mm max height

PLASTIC QUAD FLAT PACK- NO LEAD

RUC0014A

A

2.1

1.9

B

2.1

1.9

PIN 1 INDEX AREA

0.4 MAX

C

SEATING PLANE

0.08 C

0.05

0.00

(0.15) TYP

2X 0.4

6

7

8X 0.4

5

8

SYMM

1.6

12

1

0.25

0.15

14

13

14X

0.5

PIN 1 ID

SYMM

(45^oX0.1)

0.1

C A B

C

14X

0.3

0.05

4220584/A 05/2019

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

www.ti.com

EXAMPLE BOARD LAYOUT

X2QFN - 0.4 mm max height

PLASTIC QUAD FLAT PACK- NO LEAD

RUC0014A

SYMM

14X (0.6)

14X (0.2)

8X (0.4)

SYMM

(1.6) (1.8)

(R0.05)

2X (0.4)

(1.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE: 23X

0.05 MAX

ALL AROUND

0.05 MIN

ALL AROUND

SOLDER MASK

OPENING

METAL

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

EXPOSED METAL

NON-SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4220584/A 05/2019

NOTES: (continued)

3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).

www.ti.com

EXAMPLE STENCIL DESIGN

X2QFN - 0.4 mm max height

RUC0014A

PLASTIC QUAD FLAT PACK- NO LEAD

SYMM

14X (0.6)

14X (0.2)

8X (0.4)

SYMM

(1.6) (1.8)

(R0.05)

2X (0.4)

(1.8)

SOLDER PASTE EXAMPLE

BASED ON 0.100mm THICK STENCIL

SCALE: 23X

4220584/A 05/2019

NOTES: (continued)

4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

IMPORTANT NOTICE AND DISCLAIMER

TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE

DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”

AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY

IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD

PARTY INTELLECTUAL PROPERTY RIGHTS.

These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate

TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable

standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you

permission to use these resources only for development of an application that uses the TI products described in the resource. Other

reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party

intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages,

costs, losses, and liabilities arising out of your use of these resources.

TI’s products are provided subject to TI’s Terms of Sale (https:www.ti.com/legal/termsofsale.html) or other applicable terms available either

on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s

applicable warranties or warranty disclaimers for TI products.IMPORTANT NOTICE

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	TLV9151_V04
厂家：	TEXAS INSTRUMENTS
描述：	TLV915x 4.5-MHz, Rail-to-Rail Input/Output, Low Offset Voltage, Low Noise Op Amp
文件：	总72页 (文件大小：5580K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TLV9151_V04 [TI]

相关型号：

TLV9151_V05

TLV9152

TLV9152-Q1

TLV9152-Q1_V01

TLV9152-Q1_V02

TLV9152IDDFR

TLV9152IDGKR

TLV9152IDR

TLV9152IDSGR

TLV9152IPWR

TLV9152QDGKRQ1

TLV9152QDRQ1