TLV9164_技术文档

TLV9161, TLV9162, TLV9164

SBOSA68A – NOVEMBER 2021 – REVISED DECEMBER 2021

TLV916x 16-V, 11-MHz, Rail-to-Rail Input/Output, Low Offset Voltage,

Low Noise Op Amp

1 Features

3 Description

•

Low offset voltage: ±210 µV

The TLV916x family (TLV9161, TLV9162, and

TLV9164) is a family of 16-V, general-purpose

Low offset voltage drift: ±0.25 µV/°C

Low noise: 6.8 nV/√Hz at 1 kHz, 4.2 nV/√Hz

broadband

High common-mode rejection: 110 dB

Low bias current: ±10 pA

operational

amplifiers.

These

devices

offer

exceptional DC precision and AC performance,

including rail-to-rail input/output, low offset (±210 µV,

typical), low-offset drift (±0.25 µV/°C, typ), and low

noise (6.8 nV/√Hz at 1 kHz, 4.2 nV/√Hz at 10 kHz).

•

Rail-to-rail input and output

MUX-friendly/comparator inputs

– Amplifier operates with differential inputs up to

supply rails

– Amplifier can be used in open-loop or as

comparator

Wide bandwidth: 11-MHz GBW, unity-gain stable

High slew rate: 33 V/µs

Low quiescent current: 2.4 mA per amplifier

Wide supply: ±1.35 V to ±8 V, 2.7 V to 16 V

Robust EMIRR performance

Features such as differential and common-mode input

voltage ranges to the supply rails, high short-circuit

current (±73 mA), and high slew rate (33 V/µs) make

the TLV916x a flexible, robust, and high-performance

op amp for industrial applications.

•

The TLV916x family of op amps is available in micro-

size packages (such as WSON), as well as standard

packages (such as SOT-23, SOIC, and TSSOP), and

is specified from –40°C to 125°C.

Device Information

2 Applications

PART NUMBER⁽¹⁾

PACKAGE

BODY SIZE (NOM)

2.90 mm × 1.60 mm

2.00 mm × 1.25 mm

4.90 mm × 3.90 mm

2.90 mm × 1.60 mm

3.00 mm × 4.40 mm

3.00 mm × 3.00 mm

2.00 mm × 2.00 mm

8.65 mm × 3.90 mm

5.00 mm × 4.40 mm

•

Professional microphones and wireless systems

Multiplexed data-acquisition systems

Test and measurement equipment

Factory automation and control

High-side and low-side current sensing

SOT-23 (5)

TLV9161

SOT-23 (6)

SC70 (5)

SOIC (8)

SOT-23 (8)

TSSOP (8)

VSSOP (8)

WSON (8)

SOIC (14)

TSSOP (14)

TLV9162

TLV9164

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

TLV916x

+

V_shuntR_shunt

+

System

Load

-

MCU

V_o

-

I_load

GND

+

–

+

V_bus

–

I_load

GND

System

Load

TLV916x

+

MCU

+

V_shunt

+

R_shunt

-

V_o

-

GND

Low-Side Current Sense

High-Side Current Sense

TLV916x in Current-Sensing Applications

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

TLV9161, TLV9162, TLV9164

SBOSA68A – NOVEMBER 2021 – REVISED DECEMBER 2021

www.ti.com

Table of Contents

1 Features............................................................................1

2 Applications.....................................................................1

3 Description.......................................................................1

4 Revision History.............................................................. 2

5 Pin Configuration and Functions...................................3

6 Specifications.................................................................. 6

6.1 Absolute Maximum Ratings........................................ 6

6.2 ESD Ratings............................................................... 6

6.3 Recommended Operating Conditions.........................6

6.4 Thermal Information for Single Channel..................... 6

6.5 Thermal Information for Dual Channel........................7

6.6 Thermal Information for Quad Channel...................... 7

6.7 Electrical Characteristics.............................................8

6.8 Typical Characteristics.............................................. 11

7 Detailed Description......................................................18

7.1 Overview...................................................................18

7.2 Functional Block Diagram.........................................18

7.3 Feature Description...................................................19

7.4 Device Functional Modes..........................................27

8 Application and Implementation..................................28

8.1 Application Information............................................. 28

8.2 Typical Applications.................................................. 28

9 Power Supply Recommendations................................31

10 Layout...........................................................................31

10.1 Layout Guidelines................................................... 31

10.2 Layout Example...................................................... 32

11 Device and Documentation Support..........................33

11.1 Device Support........................................................33

11.2 Documentation Support.......................................... 33

11.3 Receiving Notification of Documentation Updates..33

11.4 Support Resources................................................. 33

11.5 Trademarks............................................................. 34

11.6 Electrostatic Discharge Caution..............................34

11.7 Glossary..................................................................34

12 Mechanical, Packaging, and Orderable

Information.................................................................... 35

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision * (November 2021) to Revision A (December 2021)

Page

•

Removed preview notation from TLV9164 SOIC (14) package from Device Information table..........................1

Removed preview notation from TLV9164 TSSOP (14) package from Device Information table...................... 1

Removed preview notation from TLV9164 D package (SOIC) in the Pin Configuration and Functions section...

3

•

Removed preview notation from TLV9164 PW package (TSSOP) in the Pin Configuration and Functions

section................................................................................................................................................................ 3

Removed preview notation from TLV9164 D package (SOIC) in the Thermal Information for Quad Channel

section................................................................................................................................................................ 7

Removed preview notation from TLV9164 PW package (TSSOP) in the Thermal Information for Quad

Channel section..................................................................................................................................................7

Added PSRR specification for TLV9164 release in Electrical Characteristics section........................................8

Added clarification to V_S= 2.7 V to 16 V PSRR specification noting that specification is for all channel

variants............................................................................................................................................................... 8

•

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5 Pin Configuration and Functions

OUT

Vœ

1

2

3

5

V+

IN+

Vœ

1

2

3

5

V+

IN+

4

INœ

4

OUT

Not to scale

Figure 5-1. TLV9161 DBV Package

5-Pin SOT-23

Figure 5-2. TLV9161 DCK Package

5-Pin SC70

(Top View)

Table 5-1. Pin Functions: TLV9161

I/O

DESCRIPTION

NAME

SOT-23

SC70

IN+

IN–

3

4

1

5

2

1

3

4

5

2

I

Noninverting input

I

Inverting input

OUT

V+

O

—

Output

Positive (highest) power supply

Negative (lowest) power supply

V–

OUT

V–

1

6

5

4

V+

2

3

SHDN

–IN

+IN

Not to scale

Figure 5-3. TLV9161S DBV Package

6-Pin SOT-23

(Top View)

Table 5-2. Pin Functions: TLV9161S

I/O

DESCRIPTION

NAME

NO.

+IN

3

4

1

5

6

2

I

Noninverting input

–IN

Inverting input

OUT

SHDN

V+

O

I

Output

Shutdown: low = amplifier enabled, high = amplifier disabled

Positive (highest) power supply

Negative (lowest) power supply

—

V–

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OUT1

IN1œ

IN1+

Vœ

1

2

3

4

8

7

6

5

V+

OUT1

IN1œ

IN1+

Vœ

1

2

3

4

8

7

6

5

V+

OUT2

IN2œ

IN2+

OUT2

IN2œ

IN2+

Thermal

Pad

Not to scale

Figure 5-4. TLV9162 D, DDF, PW, and DGK Package

8-Pin SOIC, SOT-23, TSSOP, and VSSOP

(Top View)

A. Connect thermal pad to V–. See Section 7.3.10 for more

information.

Figure 5-5. TLV9162 DSG Package^(A)

8-Pin WSON With Exposed Thermal Pad

(Top View)

Table 5-3. Pin Functions: TLV9162

I/O

DESCRIPTION

NAME

NO.

3

IN1+

IN1–

IN2+

IN2–

OUT1

OUT2

V+

I

Noninverting input, channel 1

2

Inverting input, channel 1

Noninverting input, channel 2

Inverting input, channel 2

Output, channel 1

5

I

6

I

1

O

—

7

Output, channel 2

8

Positive (highest) power supply

Negative (lowest) power supply

V–

4

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OUT1

IN1œ

IN1+

V+

1

2

3

4

5

6

7

14

13

12

11

10

9

OUT4

IN4œ

IN4+

Vœ

IN2+

IN2œ

OUT2

IN3+

IN3œ

OUT3

8

Not to scale

Figure 5-6. TLV9164 D and PW Package

14-Pin SOIC and TSSOP

(Top View)

Table 5-4. Pin Functions: TLV9164

I/O

DESCRIPTION

NAME

IN1+

IN1–

IN2+

IN2–

IN3+

IN3–

IN4+

IN4–

OUT1

OUT2

OUT3

OUT4

V+

NO.

3

I

Noninverting input, channel 1

Inverting input, channel 1

Noninverting input, channel 2

Inverting input, channel 2

Noninverting input, channel 3

Inverting input, channel 3

Noninverting input, channel 4

Inverting input, channel 4

Output, channel 1

2

5

I

6

I

10

9

I

12

13

1

I

O

—

7

Output, channel 2

8

Output, channel 3

14

4

Output, channel 4

Positive (highest) power supply

Negative (lowest) power supply

V–

11

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6 Specifications

6.1 Absolute Maximum Ratings

over operating ambient temperature range (unless otherwise noted)⁽¹⁾

MIN

0

MAX

20

UNIT

V

Supply voltage, V_S= (V+) – (V–)

Common-mode voltage⁽³⁾

(V–) – 0.5

(V+) + 0.5

V_S+ 0.2

10

V

Signal input pins

Differential voltage⁽³⁾

Current⁽³⁾

V

–10

V–

mA

Shutdown pin voltage

V+

Output short-circuit⁽²⁾

Continuous

Operating ambient temperature, T_A

Junction temperature, T_J

Storage temperature, T_stg

–55

–65

150

°C

(1) Operating the device beyond the ratings listed under Absolute Maximum Ratings will cause permanent damage to the device.

These are stress ratings only, based on process and design limitations, and this device has not been designed to function outside

the conditions indicated under Recommended Operating Conditions. Exposure to any condition outside Recommended Operating

Conditions for extended periods, including absolute-maximum-rated conditions, may affect device reliability and performance.

(2) Short-circuit to ground, one amplifier per package. Extended short-circuit current, especially with higher supply voltage, can cause

excessive heating and eventual destruction.

(3) Input pins are diode-clamped to the power-supply rails. Input signals that may swing more than 0.5 V beyond the supply rails must be

current limited to 10 mA or less.

6.2 ESD Ratings

VALUE

±2500

±1500

UNIT

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

Charged-device model (CDM), per ANSI/ESDA/JEDEC JS-002⁽²⁾

V_(ESD)

Electrostatic discharge

V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating ambient temperature range (unless otherwise noted)

MIN

2.7

MAX

UNIT

V_S

V_I

Supply voltage, (V+) – (V–)

16

V+

V

Common mode voltage range

V–

V_IH

V_IL

T_A

High level input voltage at shutdown pin (amplifier disabled)

Low level input voltage at shutdown pin (amplifier enabled)

Specified temperature

(V–) + 1.1

V–

V+

V

(V–) + 0.2

125

V

–40

°C

6.4 Thermal Information for Single Channel

TLV9161, TLV9161S

DBV

(SOT-23)

DCK

(SC70)

THERMAL METRIC⁽¹⁾

Unit

5 PINS

185.4

83.9

6 PINS

166.9

83.9

5 PINS

198.1

94.1

R_θJA

R_θJC(top)

R_θJB

ψ_JT

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

°C/W

52.5

47.1

45.3

Junction-to-top characterization parameter

Junction-to-board characterization parameter

25.4

25.9

16.9

ψ_JB

52.1

47.0

45.0

6

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6.4 Thermal Information for Single Channel (continued)

TLV9161, TLV9161S

DBV

(SOT-23)

DCK

(SC70)

THERMAL METRIC⁽¹⁾

Unit

5 PINS

N/A

6 PINS

5 PINS

R_θJC(bot)

Junction-to-case (bottom) thermal resistance

N/A

°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report, SPRA953.

6.5 Thermal Information for Dual Channel

TLV9162

D

DDF

(SOT-23)

DGK

(VSSOP)

DSG

(WSON)

PW

(TSSOP)

THERMAL METRIC⁽¹⁾

Unit

(SOIC)

8 PINS

Junction-to-ambient thermal

resistance

R_θJA

131.0

149.6

174.2

74.8

183.4

°C/W

Junction-to-case (top) thermal

resistance

R_θJC(top)

R_θJB

73.0

74.5

25.0

73.8

N/A

85.3

68.6

7.9

65.9

95.9

11.0

94.4

N/A

93.6

42.1

3.8

72.4

114.0

12.1

112.3

N/A

°C/W

Junction-to-board thermal

resistance

Junction-to-top characterization

parameter

ψ_JT

Junction-to-board characterization

parameter

ψ_JB

68.4

N/A

41.9

17.0

Junction-to-case (bottom) thermal

resistance

R_θJC(bot)

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report, SPRA953.

6.6 Thermal Information for Quad Channel

TLV9164

D

PW

(TSSOP)

THERMAL METRIC⁽¹⁾

UNIT

(SOIC)

14 PINS

99.0

14 PINS

118.8

47.0

R_θJA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

°C/W

R_θJC(top)

R_θJB

55.1

°C/W

54.8

61.9

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

16.7

5.5

ψ_JB

54.4

61.3

R_θJC(bot)

N/A

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report, SPRA953.

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6.7 Electrical Characteristics

For V_S= (V+) – (V–) = 2.7 V to 16 V (±1.35 V to ±8 V) at T_A= 25°C, R_L= 10 kΩ connected to V_S/ 2, V_CM= V_S/ 2, and

V_OUT= V_S/ 2, unless otherwise noted.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

OFFSET VOLTAGE

±0.21

±1

V_OS

Input offset voltage

V_CM= V–

mV

T_A= –40°C to 125°C

±1.2

dV_OS/dT

Input offset voltage drift

T_A= –40°C to 125°C

±0.25

±0.45

µV/℃

±2

±3

TLV9161, TLV9162, V_CM

V–, V_S= 5 V to 16 V

=

±2.2

±3.8

TLV9164, V_CM= V–, V_S= 5 V

to 16 V

Input offset voltage versus

power supply

PSRR

μV/V

TLV9161, TLV9162,

TLV9164, V_CM= V–, V_S= 2.7 T_A= –40°C to 125°C

±2

±12

V to 16 V⁽¹⁾

DC channel separation

0.4

µV/V

INPUT BIAS CURRENT

I_B

Input bias current

±10

pA

I_OS

Input offset current

NOISE

2.7

0.49

6.8

μV_PP

E_N

Input voltage noise

f = 0.1 Hz to 10 Hz

µV_RMS

f = 1 kHz

e_N

i_N

Input voltage noise density

nV/√Hz

fA/√Hz

f = 10 kHz

4.2

Input current noise density f = 1 kHz

55

INPUT VOLTAGE RANGE

Common-mode voltage

range

V_CM

(V–)

85

(V+)

V

V_S= 16 V, V– < V_CM< (V+) –

2 V (PMOS pair)

110

98

V_S= 5 V, V– < V_CM< (V+) – 2

V (PMOS pair)⁽¹⁾

75

Common-mode rejection

ratio

CMRR

V_S= 2.7 V, V– < V_CM< (V+) – T_A= –40°C to 125°C

2 V (PMOS pair)

dB

90

V_S= 2.7 – 16 V, (V+) – 1 V <

V_CM< V+ (NMOS pair)

78

(V+) – 2 V < V_CM< (V+) – 1 V

See Figure 6-6

INPUT IMPEDANCE

Z_ID

Differential

Common-mode

100 || 9

6 || 1

MΩ || pF

TΩ || pF

Z_ICM

OPEN-LOOP GAIN

V_S= 16 V, V_CM= V_S/ 2,

(V–) + 0.1 V < V_O< (V+) –

120

104

90

136

125

105

T_A= –40°C to 125°C

0.1 V

V_S= 5 V, V_CM= V_S/ 2,

A_OL

Open-loop voltage gain

(V–) + 0.1 V < V_O< (V+) –

dB

0.1 V⁽¹⁾

T_A= –40°C to 125°C

V_S= 2.7 V, V_CM= V_S/ 2,

(V–) + 0.1 V < V_O< (V+) –

0.1 V⁽¹⁾

FREQUENCY RESPONSE

GBW

SR

Gain-bandwidth product

11

33

MHz

V/μs

Slew rate

V_S= 16 V, G = +1, V_STEP= 10 V, C_L= 20 pF⁽³⁾

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6.7 Electrical Characteristics (continued)

For V_S= (V+) – (V–) = 2.7 V to 16 V (±1.35 V to ±8 V) at T_A= 25°C, R_L= 10 kΩ connected to V_S/ 2, V_CM= V_S/ 2, and

V_OUT= V_S/ 2, unless otherwise noted.

PARAMETER

TEST CONDITIONS

To 0.1%, V_S= 16 V, V_STEP= 10 V, G = +1, C_L= 20 pF

To 0.1%, V_S= 16 V, V_STEP= 2 V, G = +1, C_L= 20 pF

To 0.01%, V_S= 16 V, V_STEP= 10 V, G = +1, C_L= 20 pF

To 0.01%, V_S= 16 V, V_STEP= 2 V, G = +1, C_L= 20 pF

G = +1, R_L= 10 kΩ, C_L= 20 pF

MIN

TYP

MAX

UNIT

0.70

0.22

t_S

Settling time

μs

0.89

0.42

Phase margin

64

°

Overload recovery time

V_IN× gain > V_S

120

ns

0.00005%

126

V_S= 16 V, V_O= 3 V_RMS, G = 1, f = 1 kHz

dB

0.0032%

90

Total harmonic distortion +

noise

THD+N

V_S= 10 V, V_O= 3 V_RMS, G = 1, f = 1 kHz, R_L= 128 Ω

V_S= 10 V, V_O= 0.4 V_RMS, G = 1, f = 1 kHz, R_L= 32 Ω

0.00032%

110

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6.7 Electrical Characteristics (continued)

For V_S= (V+) – (V–) = 2.7 V to 16 V (±1.35 V to ±8 V) at T_A= 25°C, R_L= 10 kΩ connected to V_S/ 2, V_CM= V_S/ 2, and

V_OUT= V_S/ 2, unless otherwise noted.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

OUTPUT

V_S= 16 V, R_L= no load

6

V_S= 16 V, R_L= 10 kΩ

V_S= 16 V, R_L= 2 kΩ

V_S= 2.7 V, R_L= no load

V_S= 2.7 V, R_L= 10 kΩ

V_S= 2.7 V, R_L= 2 kΩ

25

60

85

300

Voltage output swing from Positive and negative

mV

rail

rail headroom

0.5

5

20

50

20

±73

I_SC

Short-circuit current

Capacitive load drive

mA

pF

C_LOAD

See Figure 6-33

Open-loop output

impedance

Z_O

I_O= 0 A

See Figure 6-30

Ω

POWER SUPPLY

2.4

2.8

2.84

2.92

2.98

TLV9162, TLV9164, I_O= 0 A

TLV9161, I_O= 0 A

T_A= –40°C to 125°C

Quiescent current per

amplifier

I_Q

mA

2.48

SHUTDOWN

Quiescent current per

amplifier

I_QSD

V_S= 2.7 V to 16 V, all amplifiers disabled, SHDN = V– + 2 V

36

45

µA

Output impedance during

shutdown

Z_SHDN

V_IH

V_S= 2.7 V to 16 V, amplifier disabled

10 || 2

GΩ || pF

Logic high threshold

For valid input high, the SHDN pin voltage should be greater

(V–) + 1.1 V

V

voltage (amplifier disabled) than the maximum threshold but less than or equal to V+

Logic low threshold For valid input low, the SHDN pin voltage should be less than (V–) + 0.2

voltage (amplifier enabled) the minimum threshold but greater than or equal to V–

V_IL

V

Amplifier enable time (from

t_ON

V_S= ±8 V, G = +1, V_CM= V_S/2, R_L= 10 kΩ connected to V-

shutdown) ⁽²⁾

5

µs

t_OFF

Amplifier disable time ⁽²⁾

V_S= ±8 V, G = +1, V_CM= V_S/2, R_L= 10 kΩ connected to V-

V_S= 2.7 V to 16 V, V+ ≥ SHDN ≥ (V–) + 0.9 V

3

500

400

SHDN pin input bias

current (per pin)

nA

V_S= 2.7 V to 16 V, (V–) ≤ SHDN ≤ (V–) + 0.7 V

(1) Specified by characterization only.

(2) Disable time (t_OFF) and enable time (t_ON) are defined as the time interval between the 50% point of the signal applied to the SHDN pin

and the point at which the output voltage reaches 10% (disable) or 90% (enable) of its final value.

(3) See Figure 6-15 for more information.

10

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6.8 Typical Characteristics

at T_A= 25°C, V_S= ±8 V, V_CM= V_S/ 2, R_LOAD= 10 kΩ (unless otherwise noted)

45

40

35

30

25

20

15

10

5

30

25

20

15

10

5

0

-675 -525 -375 -225 -75

0

75

Offset Voltage (µV)

225 375 525 675

0.1

0.2

0.3

0.4

0.5

0.6

Offset Voltage Drift (µV/°C)

0.7

0.8

0.9

D001

D002

Distribution from 74 amplifiers, T_A= 25°C

Distribution from 74 amplifiers

Figure 6-2. Offset Voltage Drift Distribution

Figure 6-1. Offset Voltage Production Distribution

500

2000

1600

1200

800

400

300

200

100

0

400

0

-400

-800

-1200

-1600

-2000

-100

-200

-300

-400

-500

-40

-20

0

20

40 60

Temperature (°C)

80

100 120 140

-40

-20

0

20

40 60

Temperature (°C)

80

100 120 140

D014

D013

V_CM= V+

V_CM= V–

Data from 74 amplifiers

Figure 6-4. Offset Voltage vs Temperature

Data from 74 amplifiers

Figure 6-3. Offset Voltage vs Temperature

2000

1600

1200

800

2000

1600

1200

800

400

0

-400

-800

-1200

-1600

-2000

-400

-800

-1200

-1600

-2000

-8 -7 -6 -5 -4 -3 -2 -1

0

1

Common-Mode Voltage (V)

2

3

4

5

6

7

8

4

4.5

5

5.5

Common-Mode Voltage (V)

6

6.5

7

7.5

8

D015

D060

T_A= 25°C

Data from 74 amplifiers

Figure 6-5. Offset Voltage vs Common-Mode Voltage

Figure 6-6. Offset Voltage vs Common-Mode Voltage (Transition

Region)

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6.8 Typical Characteristics (continued)

at T_A= 25°C, V_S= ±8 V, V_CM= V_S/ 2, R_LOAD= 10 kΩ (unless otherwise noted)

2000

1600

1200

800

2000

1600

1200

800

400

0

-400

-800

-1200

-1600

-2000

-400

-800

-1200

-1600

-2000

-8 -7 -6 -5 -4 -3 -2 -1

0

1

2

3

4

5

6

7

8

4

4.5

5

5.5

6

6.5

7

7.5

8

Common-Mode Voltage (V)

T_A= 125°C

Data from 74 amplifiers

Figure 6-7. Offset Voltage vs Common-Mode Voltage

Figure 6-8. Offset Voltage vs Common-Mode Voltage (Transition

Region)

2000

1600

1200

800

2000

1600

1200

800

400

0

-400

-800

-1200

-1600

-2000

-400

-800

-1200

-1600

-2000

-8 -7 -6 -5 -4 -3 -2 -1

0

1

2

3

4

5

6

7

8

4

4.5

5

5.5

6

6.5

7

7.5

8

Common-Mode Voltage (V)

T_A= –40°C

Data from 74 amplifiers

Figure 6-9. Offset Voltage vs Common-Mode Voltage

Figure 6-10. Offset Voltage vs Common-Mode Voltage

(Transition Region)

500

400

300

200

100

0

75

G=-1

G=1

G=11

G=101

G=1001

60

45

30

15

0

-100

-200

-300

-400

-500

-15

-30

-45

0

1

2

3

4

5

6

7

8

9 10 11 12 13 14 15 16

100

1k

10k 100k

Frequency (Hz)

1M

10M

Supply Voltage (V)

D005

V_CM= V–

Data from 74 amplifiers

Figure 6-12. Closed-Loop Gain vs Frequency

Figure 6-11. Offset Voltage vs Power Supply

12

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6.8 Typical Characteristics (continued)

at T_A= 25°C, V_S= ±8 V, V_CM= V_S/ 2, R_LOAD= 10 kΩ (unless otherwise noted)

20

15

10

5

600

550

500

450

400

350

300

250

200

150

100

50

I_B-

I_B+

I_OS

I_B-

I_B+

I_OS

0

-5

-10

-15

-20

0

-50

-100

-40

-20

0

20

40 60

Temperature (°C)

80

100 120 140

-8

-6

-4

-2

0

2

Common-Mode Voltage (V)

4

6

8

D020

D019

No Load

Figure 6-14. Input Bias Current and Offset Current vs

Temperature

Figure 6-13. Input Bias Current and Offset Current vs Common-

Mode Voltage

V+

V+ - 1V

V+ - 2V

V+ - 3V

V+ - 4V

V+ - 5V

V+ - 6V

V+ - 7V

50

SR+

SR-

45

40

35

30

25

20

15

10

5

V+ - 8V

-40°C

25°C

V+ - 9V

125°C

V+ - 10V

0

10

20

30

40

50

60

Output Current (mA)

70

80

90 100

0

0.5

1

1.5

2

2.5

3

Input Step (V)

3.5

4

4.5

5

D021

D035

V_S= 16 V

Figure 6-15. Slew Rate vs Input Step Voltage

Figure 6-16. Output Voltage Swing vs Output Current (Sourcing)

V- + 10V

V- + 9V

V- + 8V

V- + 7V

V- + 6V

V- + 5V

V- + 4V

V- + 3V

V- + 2V

V- + 1V

V-

V+

-40°C

25°C

125°C

V+ - 1V

V+ - 2V

V+ - 3V

V+ - 4V

-40°C

25°C

125°C

V+ - 5V

0

10

20

30

40

Output Current (mA)

50

60

70

80

90 100

0

10

20

30

40

Output Current (mA)

50

60

70

80

90 100

D022

D049

V_S= 16 V

V_S= 5 V

Figure 6-17. Output Voltage Swing vs Output Current (Sinking) Figure 6-18. Output Voltage Swing vs Output Current (Sourcing)

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6.8 Typical Characteristics (continued)

at T_A= 25°C, V_S= ±8 V, V_CM= V_S/ 2, R_LOAD= 10 kΩ (unless otherwise noted)

V- + 5V

V- + 4V

V- + 3V

V- + 2V

V- + 1V

V-

120

105

90

75

60

45

30

15

0

-40°C

25°C

125°C

CMRR

PSRR+

PSRR-

0

10

20

30

40

50

60

Output Current (mA)

70

80

90 100

1k

10k

100k

Frequency (Hz)

1M

10M

D050

D006

V_S= 5 V

Figure 6-20. CMRR and PSRR vs Frequency

Figure 6-19. Output Voltage Swing vs Output Current (Sinking)

1000

100

10

60

80

100

80

100

10

100

120

140

120

1

140

100 120 140

0.1

-40

0.1

-40

-20

0

20

40 60

Temperature (°C)

80

-20

0

20

40 60

Temperature (°C)

80

100 120 140

D023

D051

V_S= 16 V, V_CM= V–

Figure 6-21. CMRR vs Temperature

V_S= 5 V, V_CM= V–

Figure 6-22. CMRR vs Temperature

1000

60

80

100

10

80

100

10

1

100

120

140

160

100

1

0.1

120

0.01

0.1

140

-40

-20

0

20

40

60

80

100 120 140

-40

-20

0

20

40 60

Temperature (°C)

80

100 120 140

Temperature (°C)

D052

Figure 6-24. PSRR vs Temperature

V_S= 2.7 V, V_CM= V–

Figure 6-23. CMRR vs Temperature

14

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6.8 Typical Characteristics (continued)

at T_A= 25°C, V_S= ±8 V, V_CM= V_S/ 2, R_LOAD= 10 kΩ (unless otherwise noted)

2

1.5

1

100

10

1

0.5

0

-0.5

-1

-1.5

-2

Time (1s/div)

10

100

1k

Frequency (Hz)

10k

D025

D007

Figure 6-25. 0.1-Hz to 10-Hz Noise

Figure 6-26. Input Voltage Noise Spectral Density vs Frequency

2.6

2.55

2.5

2.45

2.4

2.8

2.4

2

2.35

2.3

2.25

2.2

2.15

2.1

2.05

2

1.95

1.9

1.6

1.2

0.8

0.4

0

Vs=2.7V

Vs=5V

Vs=16V

1.85

1.8

-40

-20

0

20

40 60

Temperature (°C)

80

100 120 140

0

1

2

3

4

5

6

7

8

9 10 11 12 13 14 15 16

Supply Voltage (V)

D027

V_CM= V–

Figure 6-28. Quiescent Current vs Temperature

Figure 6-27. Quiescent Current vs Supply Voltage

145

1000

V_S= 2.7V

V_S= 5V

V_S= 16V

140

135

130

125

120

115

110

105

100

10

1

0.1

-40

-20

0

20

40 60

Temperature (°C)

80

100 120 140

100

1k

10k 100k

Frequency (Hz)

1M

10M

D028

D099

Figure 6-29. Open-Loop Voltage Gain vs Temperature (dB)

Figure 6-30. Open-Loop Output Impedance vs Frequency

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6.8 Typical Characteristics (continued)

at T_A= 25°C, V_S= ±8 V, V_CM= V_S/ 2, R_LOAD= 10 kΩ (unless otherwise noted)

70

60

50

40

30

20

10

0

70

60

50

40

30

20

10

0

R_ISO= 0W, Overshoot (+)

R_ISO= 0W, Overshoot (-)

R_ISO= 50W, Overshoot (+)

R_ISO= 50W, Overshoot (-)

R_ISO= 0W, Overshoot (+)

R_ISO= 0W, Overshoot (-)

R_ISO= 50W, Overshoot (+)

R_ISO= 50W, Overshoot (-)

0

80

160

240 320

Capacitive Load (pF)

400

480

560

0

80

160

240 320

Capacitive Load (pF)

400

480

560

D029

D030

20-mV_ppoutput step, G = –1

20-mV_ppoutput step, G = +1

Figure 6-31. Small-Signal Overshoot vs Capacitive Load

Figure 6-32. Small-Signal Overshoot vs Capacitive Load

70

65

60

55

50

45

40

35

30

25

20

Input

Output

10

0

-10

-20

Time (2 µs/div)

0

20 40 60 80 100 120 140 160 180 200 220

Capacitive Load (pF)

D033

D004

C_L= 20 pF, G = 1, 20-mV_ppstep response

G = +1

Figure 6-34. Small-Signal Step Response

Figure 6-33. Phase Margin vs Capacitive Load

20

4

3

Input

Output

Input

Output

10

0

2

1

0

-1

-2

-3

-4

-10

-20

Time (2 µs/div)

D054

D034

C_L= 20 pF, G = –1, 20-mV_ppstep response

C_L= 20 pF, G = 1, 5-V_ppstep response

Figure 6-35. Small-Signal Step Response

Figure 6-36. Large-Signal Step Response

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6.8 Typical Characteristics (continued)

at T_A= 25°C, V_S= ±8 V, V_CM= V_S/ 2, R_LOAD= 10 kΩ (unless otherwise noted)

4

3

20

16

12

8

Vs=16V

Vs=2.7V

Input

Output

2

1

0

-1

-2

-3

-4

4

0

Time (2 µs/div)

100

1k

10k

100k

Frequency (Hz)

1M

10M

100M

D055

Figure 6-38. Maximum Output Voltage vs Frequency

C_L= 20 pF, G = –1, 5-V_ppstep response

Figure 6-37. Large-Signal Step Response

-60

120

110

100

90

-70

-80

-90

-100

-110

-120

-130

-140

-150

-160

80

70

60

50

40

30

20

100

1k

10k 100k

Frequency (Hz)

1M

10M

100M

Frequency (Hz)

1G

D011

D012

Figure 6-39. Channel Separation vs Frequency

Figure 6-40. EMIRR (Electromagnetic Interference Rejection

Ratio) vs Frequency

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7 Detailed Description

7.1 Overview

The TLV916x family (TLV9161, TLV9162, and TLV9164) is a family of 16-V, general-purpose, operational

amplifiers.

These devices offer excellent DC precision and AC performance, including rail-to-rail input/output, low offset

(±210 µV, typ), low offset drift (±0.25 µV/°C, typ), and 11-MHz bandwidth.

Features such as differential and common-mode input voltage range to the supply rail, high short-circuit current

(±73 mA), high slew rate (33 V/μs), and shutdown make the TLV916x a flexible, robust, and high-performance

operational amplifier for 16-V industrial applications.

7.2 Functional Block Diagram

+

NCH Input

Stage

–

IN+

IN-

+

–

16-V

OUT

Gain

Stage

Output

Stage

Differential

MUX-Friendly

Front End

Slew

Boost

Shutdown

Circuitry

+

PCH Input

Stage

–

18

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7.3 Feature Description

7.3.1 Input Protection Circuitry

The TLV916x uses a special input architecture to eliminate the requirement for input protection diodes but still

provides robust input protection under transient conditions. Figure 7-1 shows conventional input diode protection

schemes that are activated by fast transient step responses and introduce signal distortion and settling time

delays because of alternate current paths, as shown in Figure 7-2. For low-gain circuits, these fast-ramping input

signals forward-bias back-to-back diodes, causing an increase in input current and resulting in extended settling

time.

V+

V_IN+

V_OUT

TLV916x

~0.7 V

16 V

V_INꢀ

Vꢀ

TLV916x Provides Full 16-V

Differential Input Range

Conventional Input Protection

Limits Differential Input Range

Figure 7-1. TLV916x Input Protection Does Not Limit Differential Input Capability

1

R_{on_mux}

V_n= 8 V

R_FILT

8 V

S_n

D

1

2

~–7.3 V

8 V

C_FILT

C_S

C_D

VIN–

2

R_{on_mux}

S_n+1

V

_n+1= –8 V R_FILT

–8 V

~0.7 V

VOUT

C_FILT

C_S

I_{diode_transient}

VIN+

–8 V

Input Low-Pass Filter

Simplified Mux Model

Buffer Amplifier

Figure 7-2. Back-to-Back Diodes Create Settling Issues

The TLV916x family of operational amplifiers provides a true high-impedance differential input capability using

a patented input protection architecture that does not introduce additional signal distortion or delayed settling

time, making the device an optimal op amp for multichannel, high-switched, input applications. The TLV916x

tolerates a maximum differential swing (voltage between inverting and non-inverting pins of the op amp) of up

to 16 V, making the device suitable for use as a comparator or in applications with fast-ramping input signals

such as data-acquisition systems; see the TI TechNote MUX-Friendly Precision Operational Amplifiers for more

information.

7.3.2 EMI Rejection

The TLV916x uses integrated electromagnetic interference (EMI) filtering to reduce the effects of EMI from

sources such as wireless communications and densely-populated boards with a mix of analog signal chain and

digital components. EMI immunity can be improved with circuit design techniques; the TLV916x benefits from

these design improvements. Texas Instruments has developed the ability to accurately measure and quantify the

immunity of an operational amplifier over a broad frequency spectrum extending from 10 MHz to 6 GHz. Figure

7-3 shows the results of this testing on the TLV916x. Table 7-1 shows the EMIRR IN+ values for the TLV916x at

particular frequencies commonly encountered in real-world applications. The EMI Rejection Ratio of Operational

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Amplifiers application report contains detailed information on the topic of EMIRR performance as it relates to op

amps and is available for download from www.ti.com.

120

110

100

90

80

70

60

50

40

30

20

10M

100M

Frequency (Hz)

1G

D012

Figure 7-3. EMIRR Testing

Table 7-1. TLV9161 EMIRR IN+ for Frequencies of Interest

FREQUENCY

APPLICATION OR ALLOCATION

EMIRR IN+

Mobile radio, mobile satellite, space operation, weather, radar, ultra-high frequency (UHF)

applications

400 MHz

50.0 dB

Global system for mobile communications (GSM) applications, radio communication, navigation,

GPS (to 1.6 GHz), GSM, aeronautical mobile, UHF applications

900 MHz

1.8 GHz

2.4 GHz

3.6 GHz

5 GHz

56.3 dB

65.6 dB

70.0 dB

78.9 dB

91.0 dB

GSM applications, mobile personal communications, broadband, satellite, L-band (1 GHz to 2 GHz)

802.11b, 802.11g, 802.11n, Bluetooth^®, mobile personal communications, industrial, scientific and

medical (ISM) radio band, amateur radio and satellite, S-band (2 GHz to 4 GHz)

Radiolocation, aero communication and navigation, satellite, mobile, S-band

802.11a, 802.11n, aero communication and navigation, mobile communication, space and satellite

operation, C-band (4 GHz to 8 GHz)

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7.3.3 Thermal Protection

The internal power dissipation of any amplifier causes its internal (junction) temperature to rise. This

phenomenon is called self heating. The absolute maximum junction temperature of the TLV916x is 150°C.

Exceeding this temperature causes damage to the device. The TLV916x has a thermal protection feature that

reduces damage from self heating. The protection works by monitoring the temperature of the device and

turning off the op amp output drive for temperatures above 170°C. Figure 7-4 shows an application example

for the TLV9162 that has significant self heating because of its power dissipation (0.627 W). In this example,

both channels have a quiescent power dissipation while one of the channels has a significant load. Thermal

calculations indicate that for an ambient temperature of 60°C, the device junction temperature reaches 175°C.

The actual device, however, turns off the output drive to recover towards a safe junction temperature. Figure 7-4

shows how the circuit behaves during thermal protection. During normal operation, the device acts as a buffer so

the output is 5 V. When self heating causes the device junction temperature to increase above the internal limit,

the thermal protection forces the output to a high-impedance state and the output is pulled to ground through

resistor R_L. If the condition that caused excessive power dissipation is not removed, the amplifier will oscillate

between a shutdown and enabled state until the output fault is corrected. Please note that thermal performance

can vary greatly depending on the package selected and the PCB layout design. This example uses the thermal

performance of the TSSOP (8) package.

One channel has load

Consider I_Qof two channels

T_A= 60°C

5 V

16 V

P_D= 0.627W

_JA= 183.4°C/W

0 V

T_J= 183.4°C/W × 0.627W + 60°C

T_J= 175°C (expected)

ꢀ

TLV9162

170ºC

ꢁ

I_OUT= 50 mA

+

5 V

–

RL

100

+

–

V_IN

5 V

Figure 7-4. Thermal Protection

7.3.4 Capacitive Load and Stability

The TLV916x features an output stage capable of driving moderate capacitive loads, and by leveraging an

isolation resistor, the device can easily be configured to drive larger capacitive loads. Increasing the gain

enhances the ability of the amplifier to drive greater capacitive loads; see Figure 7-5 and Figure 7-6. The

particular op amp circuit configuration, layout, gain, and output loading are some of the factors to consider when

establishing whether an amplifier will be stable in operation.

70

60

50

40

30

20

10

0

70

60

50

40

30

20

10

0

R_ISO= 0W, Overshoot (+)

R_ISO= 0W, Overshoot (-)

R_ISO= 50W, Overshoot (+)

R_ISO= 50W, Overshoot (-)

R_ISO= 0W, Overshoot (+)

R_ISO= 0W, Overshoot (-)

R_ISO= 50W, Overshoot (+)

R_ISO= 50W, Overshoot (-)

0

80

160

240 320

Capacitive Load (pF)

400

480

560

0

80

160

240 320

Capacitive Load (pF)

400

480

560

D030

D029

Figure 7-5. Small-Signal Overshoot vs Capacitive

Load (20-mV_ppOutput Step, G = +1)

Figure 7-6. Small-Signal Overshoot vs Capacitive

Load (20-mV_ppOutput Step, G = -1)

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For additional drive capability in unity-gain configurations, improve capacitive load drive by inserting a small

resistor, R_ISO, in series with the output, as shown in Figure 7-7. This resistor significantly reduces ringing

and maintains DC performance for purely capacitive loads. However, if a resistive load is in parallel with the

capacitive load, then a voltage divider is created, thus introducing a gain error at the output and slightly reducing

the output swing. The error introduced is proportional to the ratio R_ISO/ R_L, and is generally negligible at low

output levels. A high capacitive load drive makes the TLV916x well suited for applications such as reference

buffers, MOSFET gate drives, and cable-shield drives. The circuit shown in Figure 7-7 uses an isolation resistor,

R_ISO, to stabilize the output of an op amp. R_ISOmodifies the open-loop gain of the system for increased phase

margin.

+V_s

V_out

R_iso

+

C_load

+

V_in

-V_s

œ

Figure 7-7. Extending Capacitive Load Drive With the TLV9161

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7.3.5 Common-Mode Voltage Range

The TLV916x is a 16-V, rail-to-rail input operational amplifier with an input common-mode range that extends

to both supply rails. This wide range is achieved with paralleled complementary N-channel and P-channel

differential input pairs, as shown in Figure 7-8. The N-channel pair is active for input voltages close to the

positive rail, typically from (V+) – 1 V to the positive supply. The P-channel pair is active for inputs from the

negative supply to approximately (V+) – 2 V. There is a small transition region, typically (V+) – 2 V to (V+) – 1

V in which both input pairs are on. This transition region can vary modestly with process variation. Within this

region PSRR, CMRR, offset voltage, offset drift, noise, and THD performance may be degraded compared to

operation outside this region.

Figure 6-5 shows this transition region for a typical device in terms of input voltage offset in more detail.

For more information on common-mode voltage range and PMOS/NMOS pair interaction, see Op Amps With

Complementary-Pair Input Stages application note.

V+

IN-

PMOS

NMOS

IN+

NMOS

V-

Figure 7-8. Rail-to-Rail Input Stage

7.3.6 Phase Reversal Protection

The TLV916x family has internal phase-reversal protection. Many op amps exhibit a phase reversal when the

input is driven beyond its linear common-mode range. This condition is most often encountered in non-inverting

circuits when the input is driven beyond the specified common-mode voltage range, causing the output to

reverse into the opposite rail. The TLV916x is a rail-to-rail input op amp; therefore, the common-mode range

can extend up to the rails. Input signals beyond the rails do not cause phase reversal; instead, the output limits

into the appropriate rail. For more information on phase reversal, see Op Amps With Complementary-Pair Input

Stages application note.

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7.3.7 Electrical Overstress

Designers often ask questions about the capability of an operational amplifier to withstand electrical overstress

(EOS). These questions tend to focus on the device inputs, but may involve the supply voltage pins or even

the output pin. Each of these different pin functions have electrical stress limits determined by the voltage

breakdown characteristics of the particular semiconductor fabrication process and specific circuits connected to

the pin. Additionally, internal electrostatic discharge (ESD) protection is built into these circuits to protect them

from accidental ESD events both before and during product assembly.

Having a good understanding of this basic ESD circuitry and its relevance to an electrical overstress event is

helpful. Figure 7-9 shows an illustration of the ESD circuits contained in the TLV916x (indicated by the dashed

line area). The ESD protection circuitry involves several current-steering diodes connected from the input and

output pins and routed back to the internal power-supply lines, where the diodes meet at an absorption device

or the power-supply ESD cell, internal to the operational amplifier. This protection circuitry is intended to remain

inactive during normal circuit operation.

TVS

R_F

+V_S

V_DD

50

R₁

R_S

IN–

IN+

–

+

Power-Supply

ESD Cell

R_L

I_D

+

–

V_IN

V_SS

–V_S

TVS

Figure 7-9. Equivalent Internal ESD Circuitry Relative to a Typical Circuit Application

An ESD event is very short in duration and very high voltage (for example; 1 kV, 100 ns), whereas an EOS event

is long duration and lower voltage (for example; 50 V, 100 ms). The ESD diodes are designed for out-of-circuit

ESD protection (that is, during assembly, test, and storage of the device before being soldered to the PCB).

During an ESD event, the ESD signal is passed through the ESD steering diodes to an absorption circuit

(labeled ESD power-supply circuit). The ESD absorption circuit clamps the supplies to a safe level.

Although this behavior is necessary for out-of-circuit protection, excessive current and damage is caused if

activated in-circuit. A transient voltage suppressors (TVS) can be used to prevent against damage caused by

turning on the ESD absorption circuit during an in-circuit ESD event. Using the appropriate current limiting

resistors and TVS diodes allows for the use of device ESD diodes to protect against EOS events.

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7.3.8 Overload Recovery

Overload recovery is defined as the time required for the op amp output to recover from a saturated state to

a linear state. The output devices of the op amp enter a saturation region when the output voltage exceeds

the rated operating voltage, either due to the high input voltage or the high gain. After the device enters the

saturation region, the charge carriers in the output devices require time to return back to the linear state. After

the charge carriers return back to the linear state, the device begins to slew at the specified slew rate. Thus, the

propagation delay in case of an overload condition is the sum of the overload recovery time and the slew time.

The overload recovery time for the TLV916x is approximately 120 ns.

7.3.9 Typical Specifications and Distributions

Designers often have questions about a typical specification of an amplifier in order to design a more robust

circuit. Due to natural variation in process technology and manufacturing procedures, every specification of an

amplifier will exhibit some amount of deviation from the ideal value, like an amplifier's input offset voltage. These

deviations often follow Gaussian ("bell curve"), or normal distributions, and circuit designers can leverage this

information to guardband their system, even when there is not a minimum or maximum specification in the

Electrical Characteristics table.

0.00312% 0.13185%

0.13185% 0.00312%

0.00002%

2.145% 13.59% 34.13% 34.13% 13.59% 2.145%

1

1 1 1 1 1 1 1 1

1

ꢀ-61 ꢀ-51 ꢀ-41 ꢀ-31 ꢀ-21 ꢀ-1

ꢀ+1 ꢀ+21 ꢀ+31 ꢀ+41 ꢀ+51 ꢀ+61

ꢀ

Figure 7-10. Ideal Gaussian Distribution

Figure 7-10 shows an example distribution, where µ, or mu, is the mean of the distribution, and where σ,

or sigma, is the standard deviation of a system. For a specification that exhibits this kind of distribution,

approximately two-thirds (68.26%) of all units can be expected to have a value within one standard deviation, or

one sigma, of the mean (from µ – σ to µ + σ).

Depending on the specification, values listed in the typical column of the Electrical Characteristics table are

represented in different ways. As a general rule of thumb, if a specification naturally has a nonzero mean

(for example, like gain bandwidth), then the typical value is equal to the mean (µ). However, if a specification

naturally has a mean near zero (like input offset voltage), then the typical value is equal to the mean plus one

standard deviation (µ + σ) in order to most accurately represent the typical value.

You can use this chart to calculate approximate probability of a specification in a unit; for example, for TLV916x,

the typical input voltage offset is 210 µV, so 68.2% of all TLV916x devices are expected to have an offset from

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–210 µV to 210 µV. At 4 σ (±840 µV), 99.9937% of the distribution has an offset voltage less than ±840 µV,

which means 0.0063% of the population is outside of these limits, which corresponds to about 1 in 15,873 units.

Specifications with a value in the minimum or maximum column are assured by TI, and units outside these limits

will be removed from production material. For example, the TLV916x family has a maximum offset voltage of 1

mV at 25°C, and even though this corresponds to about 5-σ (≈1 in 1.7 million units), which is extremely unlikely,

TI assures that any unit with larger offset than 1 mV will be removed from production material.

For specifications with no value in the minimum or maximum column, consider selecting a sigma value of

sufficient guardband for your application, and design worst-case conditions using this value. For example, the

6-σ value corresponds to about 1 in 500 million units, which is an extremely unlikely chance, and could be

an option as a wide guardband to design a system around. In this case, the TLV916x family does not have

a maximum or minimum for offset voltage drift, but based on the typical value of 0.25 µV/°C in the Electrical

Characteristics table, it can be calculated that the 6-σ value for offset voltage drift is about 1.5 µV/°C. When

designing for worst-case system conditions, this value can be used to estimate the worst possible offset across

temperature without having an actual minimum or maximum value.

However, process variation and adjustments over time can shift typical means and standard deviations, and

unless there is a value in the minimum or maximum specification column, TI cannot assure the performance of a

device. This information should be used only to estimate the performance of a device.

7.3.10 Packages With an Exposed Thermal Pad

The TLV916x family is available in the WSON-8 (DSG) package which features an exposed thermal pad. Inside

the package, the die is attached to this thermal pad using an electrically conductive compound. For this reason,

when using a package with an exposed thermal pad, the thermal pad must either be connected to V– or left

floating. Attaching the thermal pad to a potential other than V– is not allowed, and performance of the device is

not assured when doing so.

7.3.11 Shutdown

The TLV916xS devices feature one or more shutdown pins (SHDN) that disable the op amp, placing it into a

low-power standby mode. In this mode, the op amp typically consumes about 36 µA. The SHDN pins are active

high, meaning that shutdown mode is enabled when the input to the SHDN pin is a valid logic high. The amplifier

is enabled when the input to the SHDN pin is a valid logic low.

The SHDN pins are referenced to the negative supply rail of the op amp. The threshold of the shutdown feature

lies around 800 mV (typical) and does not change with respect to the supply voltage. Hysteresis has been

included in the switching threshold to ensure smooth switching characteristics. To ensure optimal shutdown

behavior, the SHDN pins should be driven with valid logic signals. A valid logic low is defined as a voltage

between V– and V– + 0.2 V. A valid logic high is defined as a voltage between V– + 1.1 V and V+. The shutdown

pin circuitry includes a pull-down resistor, which will inherently pull the voltage of the pin to the negative supply

rail if not driven. Thus, to enable the amplifier, the SHDN pins should either be left floating or driven to a valid

logic low. To disable the amplifier, the SHDN pins must be driven to a valid logic high. The maximum voltage

allowed at the SHDN pins is V+. Exceeding V+ will damage the device.

The SHDN pins are high-impedance CMOS inputs. Channels of single and dual op amp packages are

independently controlled, and channels of quad op amp packages are controlled in pairs. For battery-operated

applications, this feature may be used to greatly reduce the average current and extend battery life. The

typical enable time out of shutdown is 5 µs; disable time is 3 µs. When disabled, the output assumes a

high-impedance state. This architecture allows the TLV916xS family to operate as a gated amplifier, multiplexer,

or programmable-gain amplifier. Shutdown time (t_OFF) depends on loading conditions and increases as load

resistance increases. To ensure shutdown (disable) within a specific shutdown time, the specified 10-kΩ load to

V– is required. If using the TLV916xS without a load, the resulting turnoff time significantly increases.

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7.4 Device Functional Modes

The TLV916x has a single functional mode and is operational when the power-supply voltage is greater than 2.7

V (±1.35 V). The maximum power supply voltage for the TLV916x is 16 V (±8 V).

The TLV916xS devices feature a shutdown pin, which can be used to place the op amp into a low-power mode.

See Shutdown section for more information.

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8 Application and Implementation

Note

Information in the following applications sections is not part of the TI component specification,

and TI does not warrant its accuracy or completeness. TI’s customers are responsible for

determining suitability of components for their purposes, as well as validating and testing their design

implementation to confirm system functionality.

8.1 Application Information

The TLV916x family offers excellent DC precision and AC performance. These devices operate up to 16-V

supply rails and offer true rail-to-rail input/output, low offset voltage and offset voltage drift, as well as 11-MHz

bandwidth and high output drive. These features make the TLV916x a robust, high-performance operational

amplifier for 16-V industrial applications.

8.2 Typical Applications

8.2.1 Low-Side Current Measurement

Figure 8-1 shows the TLV9161 configured in a low-side current sensing application. For a full analysis of the

circuit shown in Figure 8-1 including theory, calculations, simulations, and measured data, see TI Precision

Design TIPD129, 0-A to 1-A Single-Supply Low-Side Current-Sensing Solution.

V_CC

5 V

LOAD

TLV9161

+

V_OUT

–

R_SHUNT

I_LOAD

100 m

LM7705

R_F

5.76 k

R_G

120

Figure 8-1. TLV9161 in a Low-Side, Current-Sensing Application

8.2.1.1 Design Requirements

The design requirements for this design are:

•

Load current: 0 A to 1 A

Output voltage: 4.9 V

Maximum shunt voltage: 100 mV

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8.2.1.2 Detailed Design Procedure

The transfer function of the circuit in Figure 8-1 is given in Equation 1.

V_OUT= I_LOADìR_SHUNTìGain

(1)

The load current (I_LOAD) produces a voltage drop across the shunt resistor (R_SHUNT). The load current is set

from 0 A to 1 A. To keep the shunt voltage below 100 mV at maximum load current, the largest shunt resistor is

defined using Equation 2.

V_{SHUNT _MAX}

100mV

1A

R_SHUNT

=

=100mW

I_{LOAD_MAX}

(2)

Using Equation 2, R_SHUNTis calculated to be 100 mΩ. The voltage drop produced by I_LOADand R_SHUNTis

amplified by the TLV9161 to produce an output voltage of 0 V to 4.9 V. The gain needed by the TLV9161 to

produce the necessary output voltage is calculated using Equation 3.

V

_{OUT _MAX}- V_{OUT _MIN}

(

)

Gain =

V_{IN_MAX}- V

(

)

IN_MIN

(3)

Using Equation 3, the required gain is calculated to be 49 V/V, which is set with resistors R_Fand R_G. Equation 4

is used to size the resistors, R_Fand R_G, to set the gain of the TLV9161 to 49 V/V.

R

(

)

F

Gain = 1+

R

G

(4)

Choosing R_Fas 5.76 kΩ, R_Gis calculated to be 120 Ω. R_Fand R_Gwere chosen as 5.76 kΩ and 120 Ω because

they are standard value resistors that create a 49:1 ratio. Other resistors that create a 49:1 ratio can also be

used. However, excessively large resistors will generate thermal noise that exceeds the intrinsic noise of the op

amp Figure 8-2 shows the measured transfer function of the circuit shown in Figure 8-1.

8.2.1.3 Application Curve

5

4

3

2

1

0

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

I_LOAD(A)

1

Figure 8-2. Low-Side, Current-Sense, Transfer Function

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8.2.2 Buffered Multiplexer

The TLV916xS shutdown devices can be configured to create a buffered multiplexer. Outputs can be connected

together on a common bus and the shutdown pins can be used to select the desired channel to pass through.

Since the amplifier circuitry has been designed such that disable transitions occur faster than enable transitions,

the amplifier naturally exhibits a "break before make" switch topology. Amplifier outputs enter a high impedance

state when placed in shutdown, so there is no risk of bus contention when connecting multiple channel outputs

together. Additionally, because outputs are isolated from inputs, there is no concern about the impedance at

the input of each channel interacting undesirably with the impedance at the output, like an amplifier gain stage

or ADC driver circuit. Also, because this topology uses amplifiers instead of MOSFET switches, other common

issues with multiplexers such as charge injection or signal error due to R_ONeffects are eliminated.

Figure 8-3 shows an example topology for a basic 2:1 multiplexer. When SEL is low, channel 1 is selected and

active; when SEL is high, channel 2 is selected and active. For more information on how to use the TLV916xS

shutdown function, see the shutdown section in Section 7.3.11

–

Channel 1

+

Input

SEL

Output

Channel 2

Input

+

Channel 2

–

Figure 8-3. Precision Reference Buffer

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9 Power Supply Recommendations

The TLV916x is specified for operation from 2.7 V to 16 V (±1.35 V to ±8 V); many specifications apply from

–40°C to 125°C or with specific supply voltage and test conditions.

CAUTION

Supply voltages larger than 20 V can permanently damage the device; see the Absolute Maximum

Ratings section.

Place 0.1-µF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or

high-impedance power supplies. For more detailed information on bypass capacitor placement, refer to the

Layout section.

10 Layout

10.1 Layout Guidelines

For best operational performance of the device, use good PCB layout practices, including:

•

Noise can propagate into analog circuitry through the power pins of the circuit as a whole and op amp itself.

Bypass capacitors are used to reduce the coupled noise by providing low-impedance power sources local to

the analog circuitry.

– Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as

close to the device as possible. A single bypass capacitor from V+ to ground is applicable for single-

supply applications.

•

Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective

methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes.

A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically separate digital

and analog grounds paying attention to the flow of the ground current.

In order to reduce parasitic coupling, run the input traces as far away from the supply or output traces as

possible. If these traces cannot be kept separate, crossing the sensitive trace perpendicular is much better as

opposed to in parallel with the noisy trace.

•

Place the external components as close to the device as possible. As illustrated in Figure 10-2, keeping RF

and RG close to the inverting input minimizes parasitic capacitance.

Keep the length of input traces as short as possible. Always remember that the input traces are the most

sensitive part of the circuit.

Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce

leakage currents from nearby traces that are at different potentials.

•

Cleaning the PCB following board assembly is recommended for best performance.

Any precision integrated circuit may experience performance shifts due to moisture ingress into the plastic

package. Following any aqueous PCB cleaning process, baking the PCB assembly is recommended to

remove moisture introduced into the device packaging during the cleaning process. A low temperature, post

cleaning bake at 85°C for 30 minutes is sufficient for most circumstances.

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10.2 Layout Example

V-

C3

INPUT

OUTPUT

U1

TLV9161

2

1

3

R3

+

–

4

C4

C2

V+

R1

C1

R2

Figure 10-1. Schematic for Noninverting Configuration Layout Example

GND

OUT

V-

GND

Figure 10-2. Operational Amplifier Board Layout for Noninverting Configuration - SC70 (DCK) Package

32

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11 Device and Documentation Support

11.1 Device Support

11.1.1 Development Support

11.1.1.1 TINA-TI^™(Free Software Download)

TINA^™is a simple, powerful, and easy-to-use circuit simulation program based on a SPICE engine. TINA-TI is a

free, fully-functional version of the TINA software, preloaded with a library of macro models in addition to a range

of both passive and active models. TINA-TI provides all the conventional dc, transient, and frequency domain

analysis of SPICE, as well as additional design capabilities.

Available as a free download from the Analog eLab Design Center, TINA-TI offers extensive post-processing

capability that allows users to format results in a variety of ways. Virtual instruments offer the ability to select

input waveforms and probe circuit nodes, voltages, and waveforms, creating a dynamic quick-start tool.

Note

These files require that either the TINA software (from DesignSoft^™) or TINA-TI software be installed.

Download the free TINA-TI software from the TINA-TI folder.

11.2 Documentation Support

11.2.1 Related Documentation

Texas Instruments, Analog Engineer's Circuit Cookbook: Amplifiers

Texas Instruments, AN31 amplifier circuit collection application note

Texas Instruments, MUX-Friendly, Precision Operational Amplifiers application brief

Texas Instruments, EMI Rejection Ratio of Operational Amplifiers application note

Texas Instruments, Op Amps With Complementary-Pair Input Stages application note

11.3 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on

Subscribe to updates to register and receive a weekly digest of any product information that has changed. For

change details, review the revision history included in any revised document.

11.4 Support Resources

TI E2E^™support forums are an engineer's go-to source for fast, verified answers and design help — straight

from the experts. Search existing answers or ask your own question to get the quick design help you need.

Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do

not necessarily reflect TI's views; see TI's Terms of Use.

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11.5 Trademarks

TINA-TI^™are trademarks of Texas Instruments, Inc and DesignSoft, Inc.

TINA^™and DesignSoft^™are trademarks of DesignSoft, Inc.

TI E2E^™is a trademark of Texas Instruments.

Bluetooth^®is a registered trademark of Bluetooth SIG, Inc.

All trademarks are the property of their respective owners.

11.6 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric changes could cause the device not to meet its published

specifications.

11.7 Glossary

TI Glossary

This glossary lists and explains terms, acronyms, and definitions.

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12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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PACKAGE MATERIALS INFORMATION

www.ti.com

19-Dec-2021

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

TLV9161IDBVR

TLV9161IDCKR

TLV9161SIDBVR

TLV9162IDDFR

SOT-23

SC70

DBV

DCK

DBV

DDF

5

6

8

3000

180.0

178.0

180.0

8.4

9.0

8.4

3.2

2.4

3.2

2.5

3.2

1.4

1.2

1.4

4.0

8.0

Q3

SOT-23

SOT-

23-THIN

TLV9162IDSGR

TLV9162IPWR

TLV9164IDR

WSON

TSSOP

SOIC

DSG

PW

D

8

3000

180.0

330.0

8.4

2.3

7.0

6.5

6.9

2.3

3.6

9.0

5.6

1.15

1.6

2.1

1.6

4.0

8.0

Q2

Q1

12.4

16.4

12.4

12.0

16.0

12.0

14

TLV9164IPWR

TSSOP

PW

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

19-Dec-2021

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

TLV9161IDBVR

TLV9161IDCKR

TLV9161SIDBVR

TLV9162IDDFR

TLV9162IDSGR

TLV9162IPWR

TLV9164IDR

SOT-23

SC70

DBV

DCK

DBV

DDF

DSG

PW

5

3000

210.0

180.0

210.0

853.0

185.0

180.0

185.0

449.0

35.0

18.0

35.0

SOT-23

SOT-23-THIN

WSON

6

8

TSSOP

SOIC

8

D

14

TLV9164IPWR

TSSOP

PW

Pack Materials-Page 2

PACKAGE OUTLINE

D0008A

SOIC - 1.75 mm max height

SCALE 2.800

SMALL OUTLINE INTEGRATED CIRCUIT

C

SEATING PLANE

.228-.244 TYP

[5.80-6.19]

.004 [0.1] C

A

PIN 1 ID AREA

6X .050

[1.27]

8

1

2X

.189-.197

[4.81-5.00]

NOTE 3

.150

[3.81]

4X (0 -15 )

4

5

8X .012-.020

[0.31-0.51]

B

.150-.157

[3.81-3.98]

NOTE 4

.069 MAX

[1.75]

.010 [0.25]

C A B

.005-.010 TYP

[0.13-0.25]

4X (0 -15 )

SEE DETAIL A

.010

[0.25]

.004-.010

[0.11-0.25]

0 - 8

.016-.050

[0.41-1.27]

DETAIL A

TYPICAL

(.041)

[1.04]

4214825/C 02/2019

NOTES:

1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.

Dimensioning and tolerancing per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed .006 [0.15] per side.

4. This dimension does not include interlead flash.

5. Reference JEDEC registration MS-012, variation AA.

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EXAMPLE BOARD LAYOUT

D0008A

SOIC - 1.75 mm max height

SMALL OUTLINE INTEGRATED CIRCUIT

8X (.061 )

[1.55]

SYMM

SEE

DETAILS

1

8

8X (.024)

[0.6]

SYMM

(R.002 ) TYP

[0.05]

5

4

6X (.050 )

[1.27]

(.213)

[5.4]

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:8X

SOLDER MASK

OPENING

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

METAL

EXPOSED

METAL

EXPOSED

METAL

.0028 MAX

[0.07]

.0028 MIN

[0.07]

ALL AROUND

SOLDER MASK

DEFINED

NON SOLDER MASK

DEFINED

SOLDER MASK DETAILS

4214825/C 02/2019

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com

EXAMPLE STENCIL DESIGN

D0008A

SOIC - 1.75 mm max height

SMALL OUTLINE INTEGRATED CIRCUIT

8X (.061 )

[1.55]

SYMM

1

8

8X (.024)

[0.6]

SYMM

(R.002 ) TYP

[0.05]

5

4

6X (.050 )

[1.27]

(.213)

[5.4]

SOLDER PASTE EXAMPLE

BASED ON .005 INCH [0.125 MM] THICK STENCIL

SCALE:8X

4214825/C 02/2019

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

9. Board assembly site may have different recommendations for stencil design.

www.ti.com

PACKAGE OUTLINE

DDF0008A

SOT-23 - 1.1 mm max height

S

C

A

L

E

4

.

0

PLASTIC SMALL OUTLINE

C

2.95

2.65

SEATING PLANE

TYP

PIN 1 ID

AREA

0.1 C

A

6X 0.65

8

1

2.95

2.85

NOTE 3

2X

1.95

4

5

0.4

0.2

8X

0.1

C A

B

1.65

1.55

B

1.1 MAX

0.20

0.08

TYP

SEE DETAIL A

0.25

GAGE PLANE

0.1

0.0

0 - 8

0.6

0.3

DETAIL A

TYPICAL

4222047/B 11/2015

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed 0.15 mm per side.

www.ti.com

EXAMPLE BOARD LAYOUT

DDF0008A

SOT-23 - 1.1 mm max height

PLASTIC SMALL OUTLINE

8X (1.05)

SYMM

1

8

8X (0.45)

SYMM

6X (0.65)

5

4

(R0.05)

TYP

(2.6)

LAND PATTERN EXAMPLE

SCALE:15X

SOLDER MASK

OPENING

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

METAL

SOLDER MASK

DEFINED

NON SOLDER MASK

DEFINED

SOLDER MASK DETAILS

4222047/B 11/2015

NOTES: (continued)

4. Publication IPC-7351 may have alternate designs.

5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com

EXAMPLE STENCIL DESIGN

DDF0008A

SOT-23 - 1.1 mm max height

PLASTIC SMALL OUTLINE

8X (1.05)

SYMM

(R0.05) TYP

8

1

8X (0.45)

SYMM

6X (0.65)

5

4

(2.6)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

SCALE:15X

4222047/B 11/2015

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

7. Board assembly site may have different recommendations for stencil design.

www.ti.com

PACKAGE OUTLINE

DBV0005A

SOT-23 - 1.45 mm max height

S

C

A

L

E

4

.

0

SMALL OUTLINE TRANSISTOR

C

3.0

2.6

0.1 C

1.75

1.45

0.90

B

A

PIN 1

INDEX AREA

1

2

5

2X 0.95

1.9

3.05

2.75

1.9

4

3

0.5

5X

0.3

0.15

0.00

(1.1)

TYP

0.2

C A B

0.25

GAGE PLANE

0.22

0.08

TYP

8

0

TYP

0.6

0.3

TYP

SEATING PLANE

4214839/F 06/2021

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. Refernce JEDEC MO-178.

4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed 0.25 mm per side.

www.ti.com

EXAMPLE BOARD LAYOUT

DBV0005A

SOT-23 - 1.45 mm max height

SMALL OUTLINE TRANSISTOR

PKG

5X (1.1)

1

5

5X (0.6)

SYMM

(1.9)

2

3

2X (0.95)

4

(R0.05) TYP

(2.6)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:15X

SOLDER MASK

OPENING

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

METAL

EXPOSED METAL

0.07 MIN

ARROUND

0.07 MAX

ARROUND

NON SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4214839/F 06/2021

NOTES: (continued)

5. Publication IPC-7351 may have alternate designs.

6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com

EXAMPLE STENCIL DESIGN

DBV0005A

SOT-23 - 1.45 mm max height

SMALL OUTLINE TRANSISTOR

PKG

5X (1.1)

1

5

5X (0.6)

SYMM

(1.9)

2

3

2X(0.95)

4

(R0.05) TYP

(2.6)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

SCALE:15X

4214839/F 06/2021

NOTES: (continued)

7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

8. Board assembly site may have different recommendations for stencil design.

www.ti.com

PACKAGE OUTLINE

DBV0006A

SOT-23 - 1.45 mm max height

S

C

A

L

E

4

.

0

SMALL OUTLINE TRANSISTOR

C

3.0

2.6

0.1 C

1.75

1.45

B

1.45 MAX

A

PIN 1

INDEX AREA

1

2

6

5

2X 0.95

1.9

3.05

2.75

4

3

0.50

6X

0.25

C A B

0.15

0.00

0.2

(1.1)

TYP

0.25

GAGE PLANE

0.22

0.08

TYP

8

TYP

0

0.6

0.3

TYP

SEATING PLANE

4214840/C 06/2021

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. Body dimensions do not include mold flash or protrusion. Mold flash and protrusion shall not exceed 0.25 per side.

4. Leads 1,2,3 may be wider than leads 4,5,6 for package orientation.

5. Refernce JEDEC MO-178.

www.ti.com

EXAMPLE BOARD LAYOUT

DBV0006A

SOT-23 - 1.45 mm max height

SMALL OUTLINE TRANSISTOR

PKG

6X (1.1)

1

6X (0.6)

6

SYMM

5

2

3

2X (0.95)

4

(R0.05) TYP

(2.6)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:15X

SOLDER MASK

OPENING

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

METAL

EXPOSED METAL

0.07 MIN

ARROUND

0.07 MAX

ARROUND

NON SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4214840/C 06/2021

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com

EXAMPLE STENCIL DESIGN

DBV0006A

SOT-23 - 1.45 mm max height

SMALL OUTLINE TRANSISTOR

PKG

6X (1.1)

1

6X (0.6)

6

SYMM

5

2

3

2X(0.95)

4

(R0.05) TYP

(2.6)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

SCALE:15X

4214840/C 06/2021

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

9. Board assembly site may have different recommendations for stencil design.

www.ti.com

GENERIC PACKAGE VIEW

DSG 8

2 x 2, 0.5 mm pitch

WSON - 0.8 mm max height

PLASTIC SMALL OUTLINE - NO LEAD

This image is a representation of the package family, actual package may vary.

Refer to the product data sheet for package details.

4224783/A

www.ti.com

PACKAGE OUTLINE

DSG0008A

WSON - 0.8 mm max height

SCALE 5.500

PLASTIC SMALL OUTLINE - NO LEAD

2.1

1.9

B

A

PIN 1 INDEX AREA

2.1

1.9

0.32

0.18

0.4

0.2

ALTERNATIVE TERMINAL SHAPE

TYPICAL

C

0.8 MAX

SEATING PLANE

0.08 C

0.05

0.00

EXPOSED

THERMAL PAD

(0.2) TYP

0.9 0.1

5

4

6X 0.5

2X

1.5

9

1.6 0.1

8

1

0.32

0.18

8X

0.4

0.2

PIN 1 ID

8X

0.1

C A B

C

0.05

4218900/D 04/2020

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

www.ti.com

EXAMPLE BOARD LAYOUT

DSG0008A

WSON - 0.8 mm max height

PLASTIC SMALL OUTLINE - NO LEAD

(0.9)

(

0.2) VIA

8X (0.5)

TYP

1

8

8X (0.25)

(0.55)

SYMM

9

(1.6)

6X (0.5)

5

4

SYMM

(1.9)

(R0.05) TYP

LAND PATTERN EXAMPLE

SCALE:20X

0.07 MIN

ALL AROUND

0.07 MAX

ALL AROUND

SOLDER MASK

OPENING

METAL

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

NON SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4218900/D 04/2020

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

www.ti.com

EXAMPLE STENCIL DESIGN

DSG0008A

WSON - 0.8 mm max height

PLASTIC SMALL OUTLINE - NO LEAD

8X (0.5)

METAL

8

SYMM

1

8X (0.25)

(0.45)

SYMM

9

(0.7)

6X (0.5)

5

4

(R0.05) TYP

(0.9)

(1.9)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD 9:

87% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE

SCALE:25X

4218900/D 04/2020

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

PACKAGE OUTLINE

PW0008A

TSSOP - 1.2 mm max height

S

C

A

L

E

2

.

8

0

SMALL OUTLINE PACKAGE

C

6.6

6.2

SEATING PLANE

TYP

PIN 1 ID

AREA

A

0.1 C

6X 0.65

8

5

1

3.1

2.9

NOTE 3

2X

1.95

4

0.30

0.19

8X

4.5

4.3

1.2 MAX

B

0.1

C A

B

NOTE 4

(0.15) TYP

SEE DETAIL A

0.25

GAGE PLANE

0.15

0.05

0.75

0.50

0 - 8

DETAIL A

TYPICAL

4221848/A 02/2015

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed 0.15 mm per side.

4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.

5. Reference JEDEC registration MO-153, variation AA.

www.ti.com

EXAMPLE BOARD LAYOUT

PW0008A

TSSOP - 1.2 mm max height

SMALL OUTLINE PACKAGE

8X (1.5)

SYMM

8X (0.45)

(R0.05)

1

4

TYP

8

SYMM

6X (0.65)

5

(5.8)

LAND PATTERN EXAMPLE

SCALE:10X

SOLDER MASK

OPENING

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

METAL

0.05 MAX

ALL AROUND

0.05 MIN

ALL AROUND

SOLDER MASK

DEFINED

NON SOLDER MASK

DEFINED

SOLDER MASK DETAILS

NOT TO SCALE

4221848/A 02/2015

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com

EXAMPLE STENCIL DESIGN

PW0008A

TSSOP - 1.2 mm max height

SMALL OUTLINE PACKAGE

8X (1.5)

SYMM

(R0.05) TYP

8X (0.45)

1

4

8

SYMM

6X (0.65)

5

(5.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

SCALE:10X

4221848/A 02/2015

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

9. Board assembly site may have different recommendations for stencil design.

www.ti.com

IMPORTANT NOTICE AND DISCLAIMER

TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE

DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”

AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY

IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD

PARTY INTELLECTUAL PROPERTY RIGHTS.

These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate

TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable

standards, and any other safety, security, regulatory or other requirements.

These resources are subject to change without notice. TI grants you permission to use these resources only for development of an

application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license

is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you

will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these

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TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with

such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for

TI products.

TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	TLV9164
厂家：	TEXAS INSTRUMENTS
描述：	TLV916x 16-V, 11-MHz, Rail-to-Rail Input/Output, Low Offset Voltage, Low Noise Op Amp
文件：	总67页 (文件大小：5121K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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