TLVM13640RDLR [TI]
采用 5mm x 5.5mm 增强型 HotRod™ QFN 封装的 36V 输入、1V 至 6V 输出、4A 降压电源模块 | RDL | 20 | -40 to 125;型号: | TLVM13640RDLR |
厂家: | TEXAS INSTRUMENTS |
描述: | 采用 5mm x 5.5mm 增强型 HotRod™ QFN 封装的 36V 输入、1V 至 6V 输出、4A 降压电源模块 | RDL | 20 | -40 to 125 电源电路 |
文件: | 总40页 (文件大小:2536K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
TLVM13640
SLVSGJ7 – APRIL 2022
TLVM13640 High-Density, 3-V to 36-V Input, 1-V to 6-V Output, 4-A Synchronous Buck
DC/DC Power Module With Enhanced HotRod™ QFN Package
1 Features
3 Description
•
Versatile synchronous buck DC/DC power module
– Integrated MOSFETs, inductor, and controller
– Wide input voltage range of 3 V to 36 V
– Adjustable output voltage from 1 V to 6 V with
1% setpoint accuracy over temperature
– 5.0-mm × 5.5-mm × 4-mm overmolded package
– –40°C to 125°C junction temperature range
– Frequency adjustable from 200 kHz to 2.2 MHz
– Negative output voltage capability
Deriving from a family of synchronous buck modules,
the TLVM13640 is a highly integrated 36-V, 4-A
DC/DC solution that combines power MOSFETs, a
shielded inductor, and passives in an Enhanced
HotRod™ QFN package. The module has VIN and
VOUT pins located at the corners of the package
for optimized input and output capacitor placement.
Four larger thermal pads beneath the module enable
a simple layout and easy handling in manufacturing.
•
•
Ultra-high efficiency across the full load range
– 95%+ peak efficiency
With an output voltage range from 1 V to 6 V,
the TLVM13640 is designed to quickly and easily
implement a low-EMI design in a small PCB footprint.
The total solution requires as few as four external
components and eliminates the magnetics and
compensation part selection from the design process.
– External bias option for improved efficiency
– Shutdown quiescent current of 0.6 µA (typical)
– 0.5-V typical dropout voltage at 4-A load
Ultra-low conducted and radiated EMI signatures
– Low-noise package with dual input paths and
integrated capacitors reduces switch ringing
– Resistor-adjustable switch-node slew rate
– Constant-frequency FPWM mode of operation
– Meets CISPR 11 and 32 class B emissions
Suitable for scalable power supplies
– Pin compatible with the TLVM13660 (36 V, 6 A)
Inherent protection features for robust design
– Precision enable input and open-drain PGOOD
indicator for sequencing, control, and VIN UVLO
– Overcurrent and thermal shutdown protections
Create a custom design using the TLVM13640 with
the WEBENCH® Power Designer
Although designed for small size and simplicity
in space-constrained applications, the TLVM13640
module offers many features for robust performance:
precision enable with hysteresis for adjustable
input-voltage UVLO, resistor-programmable switch
node slew rate for improved EMI, integrated VCC,
bootstrap, and input capacitors for increased reliability
and higher density, constant switching frequency over
the full load current range, negative output voltage
capability, and a PGOOD indicator for sequencing,
fault protection, and output voltage monitoring.
•
•
•
Device Information
PART NUMBER
PACKAGE(1)
BODY SIZE (NOM)
2 Applications
TLVM13640
B3QFN (20)
5.0 mm × 5.5 mm
•
•
•
Test and measurement, aerospace and defense
Factory automation and control
Buck and inverting buck-boost power supplies
VIN = 3 V...36 V
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
100
95
VIN1
CBOOT
VIN2
CIN
RBOOT
PGND
90
TLVM13640
VOUT = 5 V
VLDOIN
EN
IOUT(max) = 4 A
85
VCC
VOUT1
VOUT2
RPG
80
RFBT
COUT
PG
RT
FB
VIN = 12 V
VIN = 24 V
VIN = 36 V
75
70
RFBB
RRT
AGND
0
1
2
3
4
* VOUT enters dropout
if VIN < 5.8 V
Output Current (A)
Typical Efficiency, VOUT = 5 V, FSW = 1 MHz
Typical Schematic
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TLVM13640
SLVSGJ7 – APRIL 2022
www.ti.com
Table of Contents
1 Features............................................................................1
2 Applications.....................................................................1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Device Comparison Table...............................................3
6 Pin Configuration and Functions...................................3
7 Specifications.................................................................. 5
7.1 Absolute Maximum Ratings........................................ 5
7.2 ESD Ratings............................................................... 5
7.3 Recommended Operating Conditions.........................6
7.4 Thermal Information....................................................6
7.5 Electrical Characteristics.............................................7
7.6 System Characteristics............................................... 8
7.7 Typical Characteristics................................................9
7.8 Typical Characteristics (VIN = 12 V).......................... 11
7.9 Typical Characteristics (VIN = 24 V)..........................12
8 Detailed Description......................................................13
8.1 Overview...................................................................13
8.2 Functional Block Diagram.........................................13
8.3 Feature Description...................................................14
8.4 Device Functional Modes..........................................19
9 Applications and Implementation................................20
9.1 Application Information............................................. 20
9.2 Typical Applications.................................................. 20
10 Power Supply Recommendations..............................28
11 Layout...........................................................................29
11.1 Layout Guidelines................................................... 29
11.2 Layout Example...................................................... 30
12 Device and Documentation Support..........................32
12.1 Device Support....................................................... 32
12.2 Documentation Support.......................................... 33
12.3 Receiving Notification of Documentation Updates..33
12.4 Support Resources................................................. 33
12.5 Trademarks.............................................................33
12.6 Electrostatic Discharge Caution..............................33
12.7 Glossary..................................................................33
13 Mechanical, Packaging, and Orderable
Information.................................................................... 33
4 Revision History
DATE
REVISION
NOTES
April 2022
*
Initial release
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5 Device Comparison Table
Device
Orderable Part Number
Rated Output Current
Junction Temperature Range
–40°C to 125°C
External Sync(1)
TLVM13620
TLVM13630
TLVM13640
TLVM13660
TLVM13620RDHR
TLVM13630RDHR
TLVM13640RDLR
TLVM13660RDLR
2 A
3 A
4 A
6 A
No
No
No
No
–40°C to 125°C
–40°C to 125°C
–40°C to 125°C
(1) See the TPSM63602, TPSM63603, TPSM63604, and TPSM63606 for applications that require clock synchronization, an output
voltage above 6 V, spread-spectrum modulation for EMI mitigation or both.
6 Pin Configuration and Functions
1
16
VIN1
VIN2
17
PGND
SW
CBOOT
RBOOT
VLDOIN
AGND
2
3
4
5
6
7
15
14
13
12
11
10
NC
EN
18
PGND
PG
RT
19
AGND
FB
PGND
VCC
20
PGND
8
9
VOUT1
VOUT2
Figure 6-1. 20-Pin QFN RDL Package (Top View)
Table 6-1. Pin Functions
Pin
Type(1)
Description
Name
NO.
Input supply voltage. Connect the input supply to these pins. Connect input capacitors between these
pins and PGND in close proximity to the device.
VIN1, VIN2
SW
1, 16
P
Switch node. Do not place any external component on this pin or connect to any signal. The amount of
copper placed on this pin must be kept to a minimum to prevent issues with noise and EMI.
2
3
O
Bootstrap pin for the internal high-side gate driver. A 100-nF bootstrap capacitor is internally connected
from this pin to SW within the module to provide the bootstrap voltage. CBOOT is brought out to use in
conjunction with RBOOT to effectively lower the value of the internal series bootstrap resistance to adjust
the switch-node slew rate, if necessary.
CBOOT
RBOOT
VLDOIN
I/O
I/O
P
External bootstrap resistor connection. Internal to the device, a 100-Ω bootstrap resistor is connected
between RBOOT and CBOOT. RBOOT is brought out to use in conjunction with CBOOT to effectively
lower the value of the internal series bootstrap resistance to adjust the switch-node slew rate, if
necessary.
4
5
Input bias voltage. Input to the internal LDO that supplies the internal control circuits. Connect to an
output voltage point to improve efficiency. Connect an optional high-quality 0.1-μF to 1-μF capacitor from
this pin to ground for improved noise immunity. If the output voltage is above 12 V, connect this pin to
ground.
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Table 6-1. Pin Functions (continued)
Pin
Type(1)
Description
Name
NO.
Analog ground. Zero-voltage reference for internal references and logic. All electrical parameters are
measured with respect to this pin. These pins must be connected to PGND. See Section 11.2 for a
recommended layout.
AGND
6, 11
G
Internal LDO output. Used as a supply to the internal control circuits. Do not connect to any external
loads. A 1-μF capacitor internally connects from VCC to AGND.
VCC
7
O
P
VOUT1,
VOUT2
Output voltage. These pins are connected to the internal buck inductor. Connect these pins to the output
load and connect external output capacitors between these pins and PGND.
8, 9
Feedback input. Connect the midpoint of the feedback resistor divider to this pin. Connect the upper
resistor (RFBT) of the feedback divider to VOUT at the desired point of regulation. Connect the lower
resistor (RFBB) of the feedback divider to AGND. Do not leave open or connect to ground.
FB
RT
PG
10
12
13
I
I
Frequency setting pin used to set the switching frequency between 200 kHz and 2.2 MHz by placing an
external resistor from RT to AGND. Do not leave open or connect to ground.
Open-drain power-good monitor output that asserts low if the FB voltage is not within the specified
window thresholds. A 10-kΩ to 100-kΩ pullup resistor to a suitable voltage is required. If not used, PG
can be left open or connected to GND.
O
Precision enable input pin. High = on, Low = off. Can be connected to VIN. Precision enable allows
the pin to be used as an adjustable input voltage UVLO. The module can be turned off by using an
open-drain/collector device to connect this pin to AGND. Connect an external resistor divider between
this pin, VIN and AGND to create an external UVLO.
EN
14
15
I
NC
—
G
No connection. Tie to GND or leave open.
Power ground. This is the return current path for the power stage of the device. Connect these pads to
the input supply return, the load return, and the capacitors associated with the VIN and VOUT pins. See
Section 11.2 for a recommended layout.
17, 18,
19, 20
PGND
(1) P = Power, G = Ground, I = Input, O = Output
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7 Specifications
7.1 Absolute Maximum Ratings
Limits apply over TJ = –40°C to 150°C (unless otherwise noted). (1)
MIN
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
0
MAX
UNIT
V
VIN1, VIN2 to AGND, PGND
RBOOT to SW
42
5.5
V
CBOOT to SW
5.5
V
VLDOIN to AGND, PGND
min (VVIN + 0.3, 16)
V
Input voltage
EN to AGND, PGND
RT to AGND, PGND
FB to AGND, PGND
PG to AGND, PGND
PGND to AGND
42
5.5
16
V
V
V
20
V
–1
2
V
VCC to AGND, PGND
SW to AGND, PGND(2)
VOUT1, VOUT2 to AGND, PGND
PG
–0.3
–0.3
–0.3
5.5
42
V
Output voltage
V
6
V
Input current
10
mA
°C
°C
°C
°C
TJ
Junction temperature
Ambient temperature
Storage temperature
–40
–40
–55
150
125
150
250
3
TA
Tstg
Peak reflow case temperature
Maximum number of reflows allowed
Mechanical vibration
Mechanical shock
MIL-STD-883D, Method 2007.2, 20 Hz to 2 kHz
MIL-STD-883D, Method 2002.3, 1 ms, 1/2 sine, mounted
20
G
G
500
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions.
If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
(2) A voltage of 2 V below PGND and 2 V above VIN can appear on this pin for ≤ 200 ns with a duty cycle of ≤ 0.01%.
7.2 ESD Ratings
VALUE
±1500
±500
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged-device model (CDM), per ANSI/ESDA/JEDEC JS-002(2)
V(ESD)
Electrostatic discharge
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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7.3 Recommended Operating Conditions
Limits apply over TJ = –40°C to 125°C (unless otherwise noted).
MIN
NOM
MAX
UNIT
V
Input voltage
Input voltage
Output voltage
Output current
Frequency
Input current
Output voltage
TJ
VIN (input voltage range after start-up)
3
36
VLDOIN
min (VVIN, 12)
V
VOUT(1)
1
0
6
4
V
IOUT(2)
A
FSW set by RT
200
2200
2
kHz
mA
V
PG
PG
16
Operating junction temperature
Operating ambient temperature
–40
–40
125
105
°C
°C
TA
(1) Under no conditions should the output voltage be allowed to fall below zero volts.
(2) Maximum continuous DC current can be derated when operating with high switching frequency, high ambient temperature, or both.
Refer to the Typical Characteristics section for details.
7.4 Thermal Information
RDL (QFN)
THERMAL METRIC(1)
UNIT
20 PINS
22.6
33.1
1
RθJA
RθJA
ψJT
Junction-to-ambient thermal resistance (TLVM13660 EVM)
Junction-to-ambient thermal resistance (2)
°C/W
°C/W
°C/W
°C/W
Junction-to-top characterization parameter (3)
Junction-to-board characterization parameter (4)
ψJB
12.3
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
(2) The junction-to-ambient thermal resistance, RθJA, applies to devices soldered directly to a 75-mm × 75-mm four-layer PCB with 2 oz.
copper and natural convection cooling. Additional airflow and PCB copper area reduces RθJA
.
(3) The junction-to-top board characterization parameter, ψJT, estimates the junction temperature, TJ, of a device in a real system, using a
procedure described in JESD51-2A (section 6 and 7). TJ = ψJT × PDIS + TT; where PDIS is the power dissipated in the device and TT is
the temperature of the top of the device.
(4) The junction-to-board characterization parameter, ψJB, estimates the junction temperature, TJ, of a device in a real system, using a
procedure described in JESD51-2A (sections 6 and 7). TJ = ψJB × PDIS + TB; where PDIS is the power dissipated in the device and TB is
the temperature of the board 1mm from the device.
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7.5 Electrical Characteristics
Limits apply over TJ = –40°C to 125°C, VIN = 24 V, VOUT = 3.3 V, VLDOIN = 5 V, FSW = 800 kHz (unless otherwise noted).
Minimum and maximum limits are specified through production test or by design. Typical values represent the most likely
parametric norm and are provided for reference only.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY VOLTAGE
Needed to start up (over the IOUT range)
Once operating (over the IOUT range)
3.95
3
36
36
V
V
VIN
Input operating voltage range
VIN_HYS
IQ_VIN
Hysteresis(1)
1
7
1
V
Input operating quiescent current (non-switching)
VIN shutdown quiescent current
TA = 25°C, VEN = 3.3 V, VFB = 1.5 V
VEN = 0 V, TA = 25°C
µA
µA
ISDN_VIN
ENABLE
VEN_RISE
VEN_FALL
VEN_HYS
VEN_WAKE
IEN
EN voltage rising threshold
EN voltage falling threshold
EN voltage hysteresis
1.161
1.263
0.91
1.365
0.404
V
V
0.303
0.4
0.353
V
EN wake-up threshold
V
Input current into EN (non-switching)
EN high to start of switching delay(1)
VEN = 3.3 V, VFB = 1.5 V
10
nA
ms
tEN
0.7
VCC INTERNAL LDO
3.4 V ≤ VVLDOIN ≤ 12.5 V
VVLDOIN = 3.1 V, non-switching
VVLDOIN < 3.1 V(1)
3.3
3.1
3.6
3.6
1.1
25
V
V
VCC
Internal LDO VCC voltage
V
VCC_UVLO
VCC UVLO rising threshold
VIN < 3.6 V(2)
V
VCC_UVLO_HYS VCC UVLO hysteresis(2)
Hysteresis below VCC_UVLO
VEN = 3.3 V, VFB = 1.5 V
V
IVLDOIN
FEEDBACK
VOUT
Input current into VLDOIN pin (non-switching)(3)
31
6
µA
Adjustable output voltage range
Feedback voltage
Over the IOUT range
TA = 25°C, IOUT = 0 A
1
V
V
VFB
1.0
Over the VIN range, VOUT = 1 V, IOUT = 0
A, FSW = 200 kHz
VFB_ACC
Feedback voltage accuracy
–1%
+1%
VFB
Load regulation
Line regulation
TA = 25°C, 0 A ≤ IOUT ≤ 6 A
TA = 25°C, IOUT = 0 A, 4 V ≤ VIN ≤ 36 V
VFB = 1 V
0.1%
0.1%
10
VFB
IFB
Input current into FB
nA
CURRENT
IOUT
Output current
TA = 25°C
0
4
A
A
A
A
A
IOCL
Output overcurrent (DC) limit threshold
High-side switch current limit
Low-side switch current limit
Negative current limit
5.9
7.0
4.8
–3
IL_HS
IL_LS
IL_NEG
Duty cycle approaches 0%
6.0
4.0
8.1
5.4
Ratio of FB voltage to in-regulation FB voltage to
enter hiccup
VHICCUP
tW
Not during soft start
40%
80
Short circuit wait time ("hiccup" time before soft start)
ms
(1)
SOFT START
tSS
Time from first SW pulse to VFB at 90%
VIN ≥ 4.2 V
VIN ≥ 4.2 V
3.5
9.5
5
7
ms
ms
Time from first SW pulse to release of FPWM lockout
if output not in regulation(1)
tSS2
13
17
POWER GOOD
PGOV
PG upper threshold – rising
% of VOUT setting
105%
92%
107%
94%
110%
PGUV
PG lower threshold – falling
% of VOUT setting
96.5%
PGHYS
PG threshold hysteresis (rising and falling)
Input voltage for valid PG output
PG low-level output voltage
% of VOUT setting
1.3%
VIN_PG_VALID
VPG_LOW
46-μA pullup, VEN = 0 V
2-mA pullup to PG pin, VEN = 3.3 V
1.0
V
V
0.4
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Limits apply over TJ = –40°C to 125°C, VIN = 24 V, VOUT = 3.3 V, VLDOIN = 5 V, FSW = 800 kHz (unless otherwise noted).
Minimum and maximum limits are specified through production test or by design. Typical values represent the most likely
parametric norm and are provided for reference only.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Input current into PG pin when open drain output is
high
IPG
IOV
VPG = 3.3 V
10
nA
Pulldown current at the SW node during an
overvoltage condition
0.5
mA
tPG_FLT_RISE
tPG_FLT_FALL
Delay time to PG high signal
1.5
2.0
2.5
ms
µs
Glitch filter time constant for PG function
120
SWITCHING FREQUENCY
fSW_RANGE Switching frequency range by RT or SYNC
fSW_RT1
200
180
2200
220
kHz
kHz
kHz
Default switching frequency by RRT
Default switching frequency by RRT
RRT = 66.5 kΩ
RRT = 5.76 kΩ
200
fSW_RT2
1980
2200
2420
SYNCHRONIZATION
tB
Blanking of EN after rising or falling edges(1)
4
28
70
µs
V
POWER STAGE
Voltage on CBOOT pin relative to SW that turns off
the high-side switch
VBOOT_UVLO
2.1
VOUT = 1 V, IOUT = 1 A, RBOOT shorted to
CBOOT
tON(min)
tON(max)
tOFF(min)
Minimum ON pulse width(1)
Maximum ON pulse width(1)
Minimum OFF pulse width
55
9
ns
µs
ns
VIN = 4 V, IOUT = 1 A, RBOOT shorted to
CBOOT
65
85
THERMAL SHUTDOWN
TSHD
Thermal shutdown threshold (1)
Thermal shutdown hysteresis (1)
Temperature rising
158
168
10
180
°C
°C
TSHD-HYS
(1) Parameter specified by design, statistical analysis and production testing of correlated parameters. Not production tested.
(2) Production tested with VIN = 3 V.
(3) This is the current used by the device while not switching, open loop, with FB pulled to +5% of nominal. It does not represent the total
input current to the system while regulating.
7.6 System Characteristics
The following specifications apply only to the typical applications circuit, with nominal component values. Specifications in the
typical (TYP) column apply to TJ = 25°C only. These specifications are not ensured by production testing.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
SUPPLY
Input supply current when in
regulation
IIN
VIN = VEN = 24 V, VOUT = VVLDOIN = 3.3 V, FSW = 750 kHz, IOUT = 0 A
15
mA
OUTPUT VOLTAGE
ΔVOUT1
ΔVOUT2
ΔVOUT3
Load regulation
VIN = 24 V, VOUT = 3.3 V, IOUT = 0.1 A to 4 A
1
1
mV
mV
mV
Line regulation
Load transient
VOUT = 3.3 V, VIN = 4 V to 36 V, IOUT = 4 A
VIN = 24 V, VOUT = 3.3 V, IOUT = 1 A to 4 A at 1 A/μs, COUT(derated) = 50 μF
100
EFFICIENCY
η
η
η
η
η
Efficiency
VIN = 12 V, VOUT = VVLDOIN = 3.3 V, IOUT = 4 A, FSW = 750 kHz
VIN = 24 V, VOUT = VVLDOIN = 3.3 V, IOUT = 4 A, FSW = 750 kHz
VIN = 12 V, VOUT = VVLDOIN = 5 V, IOUT = 4 A, FSW = 1 MHz
VIN = 24 V, VOUT = VVLDOIN = 5 V, IOUT = 4 A, FSW = 1 MHz
VIN = 24 V, VOUT = VVLDOIN = 12 V, IOUT = 4 A, FSW = 2 MHz
92.1%
91%
Efficiency
Efficiency
Efficiency
Efficiency
94.3%
93%
95.6%
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7.7 Typical Characteristics
VIN = 24 V, unless otherwise specified
4
14
12
10
8
TJ = -40C
TJ = 25C
TJ = 125C
3
2
1
0
6
-50
-25
0
25
50
75
100
125
0
6
12
18
24
30
36
Junction Temperature (C)
Input Voltage (V)
VLDOIN = 5 V
VEN/SYNC = 0 V
Figure 7-2. Nonswitching Input Supply Current
Figure 7-1. Shutdown Supply Current
1.01
1.005
1
9
Peak
Valley
8
7
6
5
4
3
0.995
0.99
-50
-25
0
25
50
75
100
125
Junction Temperature (°C)
-50
-25
0
25
50
75
100
125
Junction Temperature (C)
Figure 7-3. Feedback Voltage
Figure 7-4. High-Side (Peak) and Low-Side (Valley)
Current Limits
70
60
50
40
30
20
10
1.4
1.2
1
0.8
0.6
0.4
VEN Rising
VEN Falling
VEN_WAKE
0.2
High-side MOSFET
Low-side MOSFET
0
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
Junction Temperature (°C)
Junction Temperature (°C)
Figure 7-6. Enable Thresholds
Figure 7-5. High-Side and Low-Side MOSFET
RDS(on)
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115
110
105
100
95
70
60
50
40
30
20
10
0
90
OV Tripping
OV Recovery
UV Recovery
UV Tripping
85
80
-50
-25
0
25
50
75
100
125
200 400 600 800 1000 1200 1400 1600 1800 2000 2200
Junction Temperature (°C)
Frequency (kHz)
Figure 7-8. Switching Frequency Set by RT
Resistor
Figure 7-7. Power Good (PG) Thresholds
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7.8 Typical Characteristics (VIN = 12 V)
Unless otherwise indicated, TA = 25°C, VLDOIN is tied to VOUT (except for VOUT = 2.5 V), and the module
is soldered to a 76-mm × 63-mm, 4-layer PCB. The SOA curves are taken with TJ(max) = 125°C and TA(max)
105°C. Refer to Section 9.2 for circuit designs.
=
100
95
90
85
80
75
1.5
1
7.5 V, 1.5 MHz
5.0 V, 1 MHz
3.3 V, 750 kHz
2.5 V, 500 kHz
0.5
0
7.5 V, 1.5 MHz
5.0 V, 1 MHz
3.3 V, 750 kHz
2.5 V, 500 kHz
0
1
2
3
4
0
1
2
3
4
Output Current (A)
Output Current (A)
Figure 7-9. Efficiency
Figure 7-10. Power Dissipation
120
100
80
120
100
80
60
60
0 LFM
0 LFM
40
40
100 LFM
200 LFM
400 LFM
100 LFM
200 LFM
400 LFM
20
20
0
1
2
3
4
0
1
2
3
4
Output Current (A)
Output Current (A)
Figure 7-11. Safe Operating Area
(VOUT = 2.5 V, FSW = 500 kHz)
Figure 7-12. Safe Operating Area
(VOUT = 3.3 V, FSW = 750 kHz)
120
100
80
60
0 LFM
40
100 LFM
200 LFM
400 LFM
20
0
1
2
3
4
Output Current (A)
Figure 7-13. Safe Operating Area
(VOUT = 5 V, FSW = 1 MHz)
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7.9 Typical Characteristics (VIN = 24 V)
Unless otherwise indicated, TA = 25°C, VLDOIN is tied to VOUT (except for VOUT = 2.5 V), and the module
is soldered to a 76-mm × 63-mm, 4-layer PCB. The SOA curves are taken with TJ(max) = 125°C and TA(max)
105°C. Refer to Section 9.2 for circuit designs.
=
100
95
90
85
80
75
2.5
12 V, 2 MHz
7.5 V, 1.5 MHz
5 V, 1 MHz
2
3.3 V, 750 kHz
1.5
1
12 V, 2 MHz
0.5
0
7.5 V, 1.5 MHz
5.0 V, 1 MHz
3.3 V, 750 kHz
0
1
2
3
4
0
1
2
3
4
Output Current (A)
Output Current (A)
Figure 7-14. Efficiency
Figure 7-15. Power Dissipation
120
100
80
60
0 LFM
40
100 LFM
200 LFM
400 LFM
20
0
1
2
3
4
Output Current (A)
Figure 7-16. Safe Operating Area
(VOUT = 2.5 V, FSW = 500 kHz)
Figure 7-17. Safe Operating Area
(VOUT = 3.3 V, FSW = 750 kHz)
120
100
80
120
100
80
60
60
0 LFM
0 LFM
40
40
100 LFM
200 LFM
400 LFM
100 LFM
200 LFM
400 LFM
20
20
0
1
2
3
4
0
1
2
3
4
Output Current (A)
Output Current (A)
Figure 7-18. Safe Operating Area
(VOUT = 5 V, FSW = 1 MHz)
Figure 7-19. Safe Operating Area
(VOUT = 12 V, FSW = 2 MHz)
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8 Detailed Description
8.1 Overview
The TLVM13640 is an easy-to-use, synchronous buck DC/DC power module designed for a wide variety of
applications where reliability, small solution size, and low EMI signature are of paramount importance. With
integrated power MOSFETs, a buck inductor, and PWM controller, the TLVM13640 operates over an input
voltage range of 3 V to 36 V with transients as high as 42 V. The module delivers up to 6-A DC load current with
high conversion efficiency and ultra-low input quiescent current in a very small solution footprint. Control loop
compensation is not required, reducing design time and external component count.
With a programmable switching frequency from 200 kHz to 2.2 MHz using its RT pin, the TLVM13640
incorporates specific features to improve EMI performance in noise-sensitive applications:
•
•
An optimized package and pinout design enables a shielded switch-node layout that mitigates radiated EMI.
Parallel input and output paths with symmetrical capacitor layouts minimize parasitic inductance, switch-
voltage ringing, and radiated field coupling
•
•
•
Resistor-programmable switch-node slew rate
Clock synchronization and FPWM mode enable constant switching frequency across the load current range.
Integrated power MOSFETs with enhanced gate drive control enable low-noise PWM switching.
Together, these features significantly reduce EMI filtering requirements, while helping to meet CISPR 11 and
CISPR 32 Class B EMI limits for conducted and radiated emissions.
The TLVM13640 module also includes inherent protection features for robust system requirements:
•
•
An open-drain PGOOD indicator for power-rail sequencing and fault reporting
Precision enable input with hysteresis, providing:
– Programmable line undervoltage lockout (UVLO)
– Remote ON/OFF capability
•
•
•
Internally fixed output-voltage soft start with monotonic start-up into prebiased loads
Hiccup-mode overcurrent protection with cycle-by-cycle peak and valley current limits
Thermal shutdown with automatic recovery.
Leveraging a pin arrangement designed for simple layout that requires only a few external components, the
TLVM13640 is specified to maximum ambient and junction temperatures of 105°C and 125°C, respectively.
8.2 Functional Block Diagram
VLDOIN
VCC
Optional
external bias
(from VOUT)
RT
LDO bias
subregulator
VIN
Oscillator
RRT
UVLO
VIN = 3 V to 36 V
OTP
VIN1, VIN2
RENT
Shutdown
logic
Precision
enable for
VIN UVLO
EN
PG
Enable
logic
RBOOT
CBOOT
100 Ω
RENB
OCP
PGOOD
indicator
PGOOD
logic
CIN
SW
Power
stage
and
control
logic
2.2 µH
VOUT = 1 V to 6 V
IOUT(max) = 4 A
COUT
RFBT
VOUT1, VOUT2
FB
To VOUT
sense point
UVLO
OTP
OCP
EN
Soft start
+
RFBB
Comp
VREF
PGND
AGND
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8.3 Feature Description
8.3.1 Input Voltage Range (VIN1, VIN2)
With a steady-state input voltage range from 3 V to 36 V, the TLVM13640 module is intended for step-down
conversions from typical 12-V, 24-V, and 28-V input supply rails. The schematic circuit in Figure 8-1 shows all the
necessary components to implement a TLVM13640-based buck regulator using a single input supply.
VIN = 3 V to 36 V
VIN1
VIN2
CIN1
CIN2
PGND
PGND
RENT
TLVM13640
Precision enable
for VIN UVLO
Optional
external bias
VOUT = 1 V to 6 V
IOUT(max) = 4 A
EN
VLDOIN
VOUT
VOUT1
VOUT2
RENB
VCC
RPG
COUT
CBOOT
RBOOT
PG
RT
RFBT
PGOOD
indicator
FB
AGND
RRT
RFBB
Figure 8-1. TLVM13640 Schematic Diagram with Input Voltage Operating Range of 3 V to 36 V
The minimum input voltage required for start-up is 3.95 V. Take extra care to make sure that the voltage at the
VIN pins of the module (VIN1 and VIN2) does not exceed the absolute maximum voltage rating of 42 V during
line or load transient events. Voltage ringing at the VIN pins that exceeds the absolute maximum ratings can
damage the IC.
8.3.2 Adjustable Output Voltage (FB)
The TLVM13640 has an adjustable output voltage range from 1 V up to a maximum of 6 V or slightly less than
VIN, whichever is lower. Setting the output voltage requires two feedback resistors, designated as RFBT and RFBB
in Figure 8-1. The reference voltage at the FB pin is set at 1 V with a feedback system accuracy over the full
junction temperature range of ±1%. The junction temperature range for the device is –40°C to 125°C.
Calculate the value for RFBT using Equation 1 based on a recommended value for RFBB of 10 kΩ.
(1)
Table 8-1 lists the standard resistor values for several output voltages and the recommended switching
frequency range to maintain reasonable peak-to-peak inductor ripple current. This table also includes the
minimum required output capacitance for each output voltage setting to maintain stability. The capacitances
as listed represent effective values for ceramic capacitors derated for DC bias voltage and temperature.
Furthermore, place a feedforward capacitor, CFF, in parallel with RFBT to increase the phase margin when the
output capacitance is close to the minimum recommended value.
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Table 8-1. Standard RFBT Values, Recommended FSW Range and Minimum COUT
VOUT RFBT (kΩ) Suggested FSW
COUT(min) (µF)
(Effective)
VOUT RFBT (kΩ) Suggested FSW
COUT(min) (µF)
(Effective)
CFF (pF)
CFF (pF)
(1)
(1)
(V)
Range (kHz)
300 to 500
400 to 600
500 to 700
(V)
2.5
3.3
5
Range (MHz)
650 to 900
700 to 950
0.8 to 1.2
1
Short
2
300
200
120
–
–
15
65
40
25
68
47
22
1.2
1.8
23.2
40.2
8.06
100
(1) RFBB = 10 kΩ
Note that higher feedback resistances consume less DC current. However, an upper RFBT resistor value higher
than 1 MΩ renders the feedback path more susceptible to noise. Higher feedback resistances generally require
more careful layout of the feedback path. It is important to locate the feedback resistors close to the FB and
AGND pins, keeping the feedback trace as short as possible (and away from noisy areas of the PCB). See
Section 11.2 guidelines for more detail.
8.3.3 Input Capacitors
Input capacitors are necessary to limit the input ripple voltage to the module due to switching frequency AC
currents. TI recommends using ceramic capacitors to provide low impedance and high RMS current rating over
a wide temperature range. Equation 2 gives the input capacitor RMS current. The highest input capacitor RMS
current occurs at D = 0.5, at which point, the RMS current rating of the capacitors should be greater than half the
output current.
DIL2
12
≈
’
D∂ IOUT2 ∂ 1-D +
∆
÷
÷
◊
ICIN,rms
=
(
)
∆
«
(2)
where
D = VOUT / VIN is the module duty cycle.
•
Ideally, the DC and AC components of input current to the buck stage are provided by the input voltage source
and the input capacitors, respectively. Neglecting inductor ripple current, the input capacitors source current of
amplitude (IOUT – IIN) during the D interval and sink IIN during the 1 – D interval. Thus, the input capacitors
conduct a square-wave current of peak-to-peak amplitude equal to the output current. The resultant capacitive
component of AC ripple voltage is a triangular waveform. Together with the ESR-related ripple component,
Equation 3 gives the peak-to-peak ripple voltage amplitude:
IOUT ∂D ∂ 1- D
(
)
+ IOUT ∂RESR
DV
=
IN
FSW ∂CIN
(3)
(4)
Equation 4 gives the input capacitance required for a particular load current:
D∂ 1-D ∂I
(
)
OUT
CIN
í
FSW ∂ DVIN -RESR ∂IOUT
where
ΔVIN is the input voltage ripple specification.
•
The TLVM13640 requires a minimum of two 10-µF ceramic input capacitors, preferably with X7R or X7S
dielectric and in 1206 or 1210 footprint. Additional capacitance can be required for applications to meet
conducted EMI specifications, such as CISPR 11 or CISPR 32.
Table 8-2 includes a preferred list of capacitors by vendor. To minimize the parasitic inductance in the switching
loops, position the ceramic input capacitors in a symmetrical layout close to the VIN1 and VIN2 pins and connect
the capacitor return terminals to the PGND pins using a copper ground plane under the module.
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Table 8-2. Recommended Ceramic Input Capacitors
Vendor(1)
TDK
Dielectric
X7R
Part Number
Case Size
Capacitance (µF)(2)
Rated Voltage (V)
C3216X7R1H106K160AC
GCM32EC71H106KA03K
12105C106MAT2A
1206
10
10
10
10
50
50
50
50
Murata
AVX
X7S
1210
X7R
1210
Murata
X7R
GRM32ER71H106KA12L
1210
(1) Consult capacitor suppliers regarding availability, material composition, RoHS and lead-free status, and manufacturing process
requirements for any capacitors identified in this table. See the Third-Party Products Disclaimer.
(2) Nameplate capacitance values (the effective values are lower based on the applied DC voltage and temperature).
As discussed in Section 10, an electrolytic bulk capacitance (68 µF to 100 µF) provides low-frequency filtering
and parallel damping to mitigate the effects of input parasitic inductance resonating with the low-ESR, high-Q
ceramic input capacitors.
8.3.4 Output Capacitors
Table 8-1 lists the TLVM13640 minimum amount of required output capacitance. The effects of DC bias and
temperature variation must be considered when using ceramic capacitance. For ceramic capacitors in particular,
the package size, voltage rating, and dielectric material contribute to differences between the standard rated
value and the actual effective value of the capacitance.
When including additional capacitance above COUT(min), the capacitance can be ceramic type, low-ESR polymer
type, or a combination of the two. See Table 8-3 for a preferred list of output capacitors by vendor.
Table 8-3. Recommended Ceramic Output Capacitors
Vendor(1)
Murata
TDK
Dielectric
X7R
X7R
X7R
X6S
Part Number
Case Size
1206
1210
1210
1206
1210
1210
1210
1210
1210
1206
1206
1210
Capacitance (µF)(2)
Voltage (V)
GRM31CZ71C226ME15L
C3225X7R1C226M250AC
GRM32ER71C226KEA8K
C3216X6S1E226M160AC
12103C226KAT4A
22
22
16
16
16
25
25
25
10
10
16
4
Murata
TDK
22
22
AVX
X7R
X7R
X7R
X7R
X6S
22
Murata
AVX
GRM32ER71E226ME15L
1210ZC476MAT2A
22
47
Murata
Murata
TDK
GRM32ER71A476ME15L
GRM32EC81C476ME15L
C3216X6S0G107M160AC
GRM31CD80J107MEA8L
GRM32EC70J107ME15L
47
47
X6S
100
100
100
Murata
Murata
X6T
6.3
6.3
X7S
(1) Consult capacitor suppliers regarding availability, material composition, RoHS and lead-free status, and manufacturing process
requirements for any capacitors identified in the table. See the Third-Party Products Disclaimer.
(2) Nameplate capacitance values (the effective values are lower based on the applied DC voltage and temperature)
8.3.5 Switching Frequency (RT)
Connect a resistor, designated as RRT in Figure 8-1, between RT and AGND to set the swiching frequency within
the range of 200 kHz to 2.2 MHz. Use Equation 5 or refer to Figure 7-8 to calculate RRT for a desired frequency.
(5)
Refer to Table 8-1 or use the simplified expression in Equation 6 to find a switching frequency that sets an
inductor ripple current of 30% to 50% of the 4-A module current rating at nominal input voltage:
(6)
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where
•
VIN(nom) and VOUT are the nominal input voltage (typically 12 V or 24 V) and output voltage of the application,
respectively.
Note that a resistor value outside of the recommended range can cause the module to shut down. This prevents
unintended operation if the RT pin is shorted to ground or left open.
8.3.6 Precision Enable and Input Voltage UVLO (EN)
The EN pin provides precision ON and OFF control for the TLVM13640. Once the EN pin voltage exceeds the
rising threshold and VIN is above its minimum turn-on threshold, the device starts operation. The simplest way
to enable the TLVM13640 is to connect EN directly to VIN. This allows the TLVM13640 to start up when VIN is
within its valid operating range. However, many applications benefit from the use of an enable divider network
as shown in Figure 8-1, which establishes a precision input undervoltage lockout (UVLO). This can be used for
sequencing, to prevent re-triggering the device when used with long input cables, or to reduce the occurrence of
deep discharge of a battery power source. An external logic signal can also be used to drive the enable input to
toggle the output on and off and for system sequencing or protection.
Calculate RENB using Equation 7:
(7)
where
•
•
•
A typical value for RENT is 100 kΩ.
VEN_RISE is enable rising threshold voltage of 1.263 V (typical).
VIN(on) is the desired start-up input voltage.
8.3.7 Power Good Monitor (PG)
The TLVM13640 provides a power-good status signal to indicate when the output voltage is within a regulation
window of 94% to 107%. The PG voltage goes low when the feedback (FB) voltage is outside of the specified
PGOOD thresholds (see Figure 7-7). This can occur during current limit and thermal shutdown, as well as when
disabled and during start-up.
PG is an open-drain output, requiring an external pullup resistor to a DC supply, such as VCC or VOUT. To
limit current supplied by VCC, the recommended range of pullup resistance is 20 kΩ to 100 kΩ. A 120-µs
deglitch filter prevents false flag operation for short excursions of the output voltage, such as during line and load
transients. When EN is pulled low, PG is forced low and remains remains valid as long as the input voltage is
above 1 V (typical). Use the PG signal for start-up sequencing of downstream regulators, as shown in Figure
8-2, or for fault protection and output monitoring.
VIN(on) = 13.9 V
VIN(off) = 10 V
VOUT2 = 3.3 V
VOUT1 = 5 V
RUV1
1 M
RFB3
PG 13
PG 13
RPG
RFB1
23.2 k
1 V
RFB4
100 k
14
EN
14
EN
40.2 k
RUV2
FB
10
FB
10
1 V
100 k
RFB2
10 k
10 k
Regulator #1
Regulator #2
Start-up based on
input voltage UVLO
Sequential start-up
based on PG
Figure 8-2. TLVM13640 Sequencing Implementation Using PG and EN
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8.3.8 Adjustable Switch-Node Slew Rate (RBOOT, CBOOT)
Adjust the switch-node slew rate of the TLVM13640 to slow the switch-node voltage rise time and improve EMI
performance at high frequencies. However, slowing the rise time decreases efficiency. Care must be taken to
balance the improved EMI versus the decreased efficiency.
Internal to the module, a 100-Ω bootstrap resistor connects between the RBOOT and CBOOT pins as shown in
Figure 8-3. Leaving these pins open incorporates the 100-Ω resistor in the bootstrap circuit, slowing the switch
voltage slew rate and optimizing EMI. However, if improved EMI is not required, connect RBOOT to CBOOT to
short the internal resistor, thus resulting in the highest efficiency. Place a resistor across RBOOT and CBOOT to
allow adjustment of the internal resistance to balance EMI and efficiency performance.
VCC
7
CVCC
4
3
2
RBOOT
CBOOT
1 µF
RBOOT
100
Power
MOSFET
gate drivers
CBOOT
100 nF
SW
Figure 8-3. Internal BOOT Resistor
8.3.9 Bias Supply Regulator (VCC, VLDOIN)
VCC is the output of the internal LDO subregulator used to supply the control circuits of the TLVM13640. The
nominal VCC voltage is 3.3 V. The VLDOIN pin is the input to the internal LDO. Connect this input to VOUT to
provide the lowest possible input supply current. If the VLDOIN voltage is less than 3.1 V, VIN1 and VIN2 directly
power the internal LDO.
To prevent unsafe operation, VCC has UVLO protection that prevents switching if the internal voltage is too low.
See VCC_UVLO and VCC_UVLO_HYS in the Electrical Characteristics.
VCC must not be used to power external circuitry. Do not load VCC or short it to ground. VLDOIN is an optional
input to the internal LDO. Connect an optional high quality 0.1-µF to 1-µF capacitor from VLDOIN to AGND for
improved noise immunity.
The LDO provides the VCC voltage from one of two inputs: VIN or VLDOIN. When VLDOIN is tied to ground
or below 3.1 V, the LDO derives power from VIN. The LDO input becomes VLDOIN when VLDOIN is tied to a
voltage above 3.1 V. The VLDOIN voltage must not exceed both VIN and 12 V.
Equation 8 specifies the LDO power loss reduction as:
PLDO-LOSS = ILDO × (VIN-LDO – VVCC
)
(8)
The VLDOIN input provides an option to supply the LDO with a lower voltage than VIN, thus minimizing the LDO
input voltage relative to VCC and reducing power loss. For example, if the LDO current is 10 mA at 1 MHz with
VIN = 24 V and VOUT = 5 V, the LDO power loss with VLDOIN tied to ground is 10 mA × (24 V – 3.3 V) = 207
mW, while the loss with VLDOIN tied to VOUT is equal to 10 mA × (5 V – 3.3 V) = 17 mW – a reduction of 190
mW.
Figure 8-4 and Figure 8-5 show typical efficiency plots with and without VLDOIN connected to VOUT.
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100
100
95
90
85
80
75
70
95
90
85
80
75
VVLDOIN = VOUT
VVLDOIN = GND
VVLDOIN = VOUT
VVLDOIN = GND
70
0
1
2
3
4
0
1
2
3
4
Output Current (A)
Output Current (A)
VIN = 24 V
VOUT = 5 V
FSW = 1 MHz
VIN = 36 V
VOUT = 5 V
FSW = 1 MHz
Figure 8-4. Efficiency Increase With External Bias Figure 8-5. Efficiency Increase With External Bias
8.3.10 Overcurrent Protection (OCP)
The TLVM13640 is protected from overcurrent conditions using cycle-by-cycle current limiting of the peak
inductor current. The current is compared every switching cycle to the current limit threshold. During an
overcurrent condition, the output voltage decreases.
The TLVM13640 employs hiccup overcurrent protection if there is an extreme overload. In hiccup mode, the
TLVM13640 module is shut down and kept off for 80 ms (typical) before a restart is attempted. If an overcurrent
or short-circuit fault condition still exists, hiccup repeats until the fault condition is removed. Hiccup mode
reduces power dissipation under severe overcurrent conditions, thus preventing overheating and potential
damage to the device. Once the fault is removed, the module automatically recovers and returns to normal
operation.
8.3.11 Thermal Shutdown
Thermal shutdown is an integrated self-protection used to limit junction temperature and prevent damage related
to overheating. Thermal shutdown turns off the device when the junction temperature exceeds 168°C (typical) to
prevent further power dissipation and temperature rise. Junction temperature decreases after shutdown, and the
TLVM13640 attempts to restart when the junction temperature falls to 158°C (typical).
8.4 Device Functional Modes
8.4.1 Shutdown Mode
The EN pin provides ON and OFF control for the TLVM13640. When VEN is below approximately 0.4 V, the
device is in shutdown mode. Both the internal LDO and the switching regulator are off. The quiescent current in
shutdown mode drops to 0.6 µA (typical). The TLVM13640 also employs internal undervoltage protection. If the
input voltage is below its UV threshold, the regulator remains off.
8.4.2 Standby Mode
The internal LDO for the VCC bias supply has a lower enable threshold than the regulator itself. When VEN is
above 1.1 V (maximum) and below the precision enable threshold of 1.263 V (typical), the internal LDO is on and
regulating. The precision enable circuitry is turned on once the internal VCC is above its UVLO threshold. The
switching action and voltage regulation are not enabled until VEN rises above the precision enable threshold.
8.4.3 Active Mode
The TLVM13640 is in active mode when VVCC and VEN are above their relevant thresholds and no fault
conditions are present. The simplest way to enable operation is to connect EN to VIN, which allows self start-up
when the applied input voltage exceeds the minimum start-up voltage.
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9 Applications and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information
The TLVM13640 synchronous buck module requires only a few external components to convert from a wide
range of supply voltages to a fixed output voltage at an output current up to 4 A. To expedite and streamline
the process of designing of a TLVM13640-based regulator, a comprehensive TLVM13640 quickstart calculator is
available by download to assist the system designer with component selection for a given application.
9.2 Typical Applications
For the circuit schematic, bill of materials, PCB layout files, and test results of a TLVM13640-powered
implementation, see the TLVM13660 EVM.
9.2.1 Design 1 – High-Efficiency 4-A Synchronous Buck Regulator for Industrial Applications
Figure 9-1 shows the schematic diagram of a 5-V, 6-A buck regulator with a switching frequency of 1 MHz. In
this example, the target half-load and full-load efficiencies are 93.2% and 93%, respectively, based on a nominal
input voltage of 24 V that ranges from 9 V to 36 V. A resistor RRT of 13 kΩ sets the free-running switching
frequency at 1 MHz. An optional SYNC input signal allows adjustment of the switching frequency from 700 kHz
to 1.4 MHz for this specific application.
VIN = 9 V to 36 V
VIN(on) = 6 V
VIN(off) = 4.3 V
VIN1
VIN2
CIN1
10
CIN2
10
F
F
PGND
PGND
RENT
374 k
TLVM13640
Precision
enable for
VIN UVLO
VOUT = 5 V
IOUT(max) = 4 A
Optional
external bias
EN
VLDOIN
VOUT1
VOUT2
VCC
RENB
RPG
100 k
100 k
COUT
CFF
22 pF
CBOOT
RBOOT
RFBT
2 ꢀ 47
F
PG
RT
40.2 k
PGOOD
indicator
FB
RRT
RFBB
10 k
AGND
13 k
Figure 9-1. Circuit Schematic
9.2.1.1 Design Requirements
Table 9-1 shows the intended input, output, and performance parameters for this application example. Note
that if the input voltage decreases below approximately 5.5 V, the regulator operates in dropout with the output
voltage below its 5-V setpoint.
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Table 9-1. Design Parameters
Design Parameter
Value
Input voltage range
Input voltage UVLO turn on, off
Output voltage
9 V to 36 V
6 V, 4.3 V
5 V
Maximum output current
Switching frequency
4 A
1 MHz
±1%
Output voltage regulation
Module shutdown current
< 1 µA
Table 9-2 gives the selected buck module power-stage components with availability from multiple vendors. This
design uses an all-ceramic output capacitor implementation.
Table 9-2. List of Materials for Application Circuit 1
Reference
Designator
Qty
Specification
Manufacturer(1)
Part Number
Taiyo Yuden
TDK
UMJ325KB7106KMHT
CNA6P1X7R1H106K
GCM32EC71H106KA03
CGA6P3X7S1H106M
GRM32ER70J476ME20K
12106C476MAT2A
10 µF, 50 V, X7R, 1210, ceramic
CIN1, CIN2
2
Murata
10 µF, 50 V, X7S, 1210, ceramic
47 µF, 6.3 V, X7R, 1210, ceramic
47 µF, 10 V, X7R, 1210, ceramic
TDK
Murata
AVX
COUT1, COUT2
2
1
Murata
GRM32ER71A476ME15L
1210ZC476MAT2A
AVX
100 µF, 6.3 V, X7S, 1210, ceramic
Murata
GRM32EC70J107ME15L
TLVM13640RDLR
U1
TLVM13640 36-V, 4-A synchronous buck module
Texas Instruments
(1) See the Third-Party Products Disclaimer.
More generally, the TLVM13640 module is designed to operate with a wide range of external components
and system parameters. However, the integrated loop compensation is optimized for a certain range of output
capacitance.
9.2.1.2 Detailed Design Procedure
9.2.1.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the TLVM13640 module with WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
•
•
•
•
Run electrical simulations to see important waveforms and circuit performance.
Run thermal simulations to understand board thermal performance.
Export customized schematic and layout into popular CAD formats.
Print PDF reports for the design, and share the design with colleagues.
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
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9.2.1.2.2 Output Voltage Setpoint
The output voltage of a TLVM13640 module is externally adjustable using a resistor divider. A recommended
value for RFBB of 10 kΩ establishes a divider current of 0.1 mA. Select the value for RFBT from Table 8-1 or
calculate using Equation 9:
(9)
Choose the closest standard value of 40.2 kΩ for RFBT
.
9.2.1.2.3 Switching Frequency Selection
Connect a 13-kΩ resistor from RT to AGND to set a switching frequency of 1 MHz, which is ideal for an output of
5 V as it establishes an inductor peak-to-peak ripple current in the range of 20% to 40% of the 4-A rated output
current at a nominal input voltage of 24 V.
9.2.1.2.4 Input Capacitor Selection
The TLVM13640 requires a minimum input capacitance of 2 × 10-µF ceramic, preferably with X7R dielectric.
The voltage rating of input capacitors must be greater than the maximum input voltage. For this design, select
two 10-µF, X7R, 50-V, 1210 case size, ceramic capacitors connected from VIN1 and VIN2 to PGND as close as
possible to the module. See Figure 11-2 for recommneded layout placement.
9.2.1.2.5 Output Capacitor Selection
From Table 8-1, the TLVM13640 requires a minimum of 25 µF of effective output capacitance for proper
operation at an output voltage of 5 V. Use high-quality ceramic type capacitors with sufficient voltage and
temperature rating. If needed, connect additional output capacitance to reduce ripple voltage or for applications
with specific load transient requirements.
For this design example, use two 47-µF, 6.3-V or 10-V, X7R, 1210, ceramic capacitors connected close to the
module from the VOUT1 and VOUT2 pins to PGND. The total effective capacitance at 5 V is approximately
52 µF and 38 µF at 25°C and –40°C, respectively.
9.2.1.2.6 Other Connections
Connect VLDOIN to the 5-V output for best efficiency. To increase phase margin when using an output
capacitance close to the minimum recommended in Table 8-1, use a feedforward capacitor, designated as
CFF in Figure 9-1, across the upper feedback resistor. Based on the feedback resistor values in this application,
a capacitor of 22 pF sets a zero-pole pair at 180 kHz and 900 kHz, respectively.
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9.2.1.3 Application Curves
Unless otherwise indicated, VIN = 24 V, VOUT = 5 V, IOUT = 4 A (1.25-Ω resistive load), and FSW = 1 MHz.
100
95
90
85
80
75
70
5.05
5.025
5
4.975
4.95
VIN = 12 V
VIN = 24 V
VIN = 36 V
VIN = 12 V
VIN = 24 V
VIN = 36 V
0
1
2
3
4
0
1
2
3
4
Output Current (A)
Output Current (A)
Figure 9-3. Load Regulation
Figure 9-2. Efficiency
IOUT 2 A/DIV
VIN 5 V/DIV
VOUT 5 V/DIV
VOUT 0.1 V/DIV
PG 5 V/DIV
4 ms/DIV
80 ꢀs/DIV
Figure 9-5. Load Transient, 0 A to 3 A, 1 A/µs
Figure 9-4. Start-Up, VIN Stepped to 12 V
QP detector
QP detector
AVG detector
AVG detector
Figure 9-7. CISPR 32 Class B Conducted
Emissions: VIN = 24 V
Figure 9-6. CISPR 32 Class B Conducted
Emissions: VIN = 12 V
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QPK detector
QPK detector
Figure 9-8. CISPR 32 Class B Radiated Emissions:
Horizontal Polarization
Figure 9-9. CISPR 32 Class B Radiated Emissions:
Vertical Polarization
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9.2.2 Design 2 – Inverting Buck-Boost Regulator with Negative Output Voltage
Figure 9-10 shows the schematic diagram of an inverting buck-boost (IBB) regulator with an output of –5 V at –3
A and a switching frequency of 1.2 MHz. In this example, the target half-load and full-load efficiencies are 90%
and 90.5%, respectively, based on a nominal input voltage of 24 V that ranges from 10 V to 31 V.
VIN+
U1
CIN3
10
VIN1
VIN2
VIN = 10 V to 31 V
VIN–
VIN(on) = 8.9 V
F
CIN1
10
CIN2
10
F
F
PGND
PGND
RENT
604 k
–VOUT
–VOUT
Optional
TLVM13640
Precision
EN
VLDOIN
external bias
enable for
VIN UVLO
VOUT+
VOUT1
VOUT2
CBOOT
VCC
RENB
100 k
VOUT = –5 V
IOUT(max) = –3 A
COUT
PG
RT
RFBT
3 ꢀ 47
F
RBOOT
FB
102 k
–VOUT
VOUT–
–VOUT
RRT
10.7 k
RFBB
AGND
25.5 k
–VOUT
Figure 9-10. Circuit Schematic
9.2.2.1 Design Requirements
Table 9-3 shows the intended input, output, and performance parameters for this application example. With an
IBB topology, the module sees a total current of IIN + |–IOUT|, which is highest at minimum input voltage.
Table 9-3. Design Parameters
Design Parameter
Input voltage range
Input voltage UVLO turn on
Output voltage
Value
10 V to 31 V
8.9 V
–5 V
Full-load current
–3 A
Switching frequency
Output voltage regulation
1.2 MHz
±1%
Table 9-4 gives the selected buck module power-stage components with availability from multiple vendors. This
design uses an all-ceramic output capacitor implementation.
Table 9-4. List of Materials for Application Circuit 2
Ref Des
Qty
Specification
Manufacturer(1)
Part Number
Kemet
C1210C106K5RACTU
CNA6P1X7R1H106K
GRM32ER71A476ME15L
GRT32EC70J107ME13L
TLVM13640RDLR
CIN1, CIN2, CIN3
3
10 µF, 50 V, X7R, 1210, ceramic
TDK
47 µF, 10 V, X7R, 1210, ceramic
Murata
COUT1, COUT2
U1
2
1
100 µF, 6.3 V, X7S, 1210, ceramic
Murata
TLVM13640 36-V, 4-A synchronous buck module
Texas Instruments
(1) See the Third-Party Products Disclaimer.
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9.2.2.2 Detailed Design Procedure
9.2.2.2.1 Output Voltage Setpoint
For an output voltage of –5 V, choose upper and lower feedback resistance of 102 kΩ and 25.5 kΩ, respectively,
using Equation 1.
9.2.2.2.2 IBB Maximum Output Current
The achievable output current with an IBB topology using the TLVM13640 is IOUT(max) = ILDC(max) × (1 – D),
where ILDC(max) = 4 A is the rated current of the module and D = |VOUT| / (VIN + |VOUT|) is the IBB duty cycle.
Figure 9-11 provides the maximum output current capability as a function of input voltage for output voltage
setpoints of –3.3 V and –5 V.
9.2.2.2.3 Switching Frequency Selection
Connect a 10.7-kΩ resistor from RT to AGND to set a switching frequency of 1.2 MHz, which is ideal for an
output of –5 V as it establishes an inductor peak-to-peak ripple current of approximately 40% of the 4-A rated
module current at the nominal input voltage of 12 V.
9.2.2.2.4 Input Capacitor Selection
Use two 10-µF, 50-V, X7R-dielectric ceramic capacitors in 1210 case size connected symmetrically from the
VIN1 and VIN2 pins to PGND as close as possible to the module. More specifically, these capacitors appear
from the drain of the internal high-side MOSFET to the source of the low-side MOSFET, effectively connecting
from the positive input voltage to the negative output voltage terminals.
The sum of the input and output voltages, VIN + |–VOUT|, is the effective applied voltage across the capacitors.
The total effective capacitance at 25°C and input voltages of 12 V and 24 V (corresponding to applied voltages
of 17 V and 29 V) is approximately 15 µF and 10 µF, respectively. Check the capacitance versus voltage
derating curve in the capacitor data sheet.
Use an additional 10-µF, 50-V capacitor directly across the input. This capacitor is designated as CIN3 and
connects across the VIN+ and VIN– terminals as shown in Figure 9-10.
9.2.2.2.5 Output Capacitor Selection
For this IBB design example, use two 47-µF, 10-V, X7R-dielectric ceramic capacitors in 1210 case size
connected symmetrically close to the module from the VOUT1 and VOUT2 pins to PGND. The total effective
capacitance is approximately 52 µF with DC bias of 5 V.
9.2.2.2.6 Other Considerations
Short RBOOT to CBOOT and connect VLDOIN to the power stage GND terminal (corresponding to VOUT1,
VOUT2 of the module) for best efficiency.
The right-half-plane zero of an IBB topology is at its lowest freqeuncy at minimum input voltage and highest load
current. Using the TLVM13640 quickstart calculator, select the output capacitance to set that the loop crossover
freqeuncy at less than one third of the lowest right-half-plane zero frequency for a given application.
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9.2.2.3 Application Curves
Unless otherwise indicated, VIN = 24 V, VOUT = –5 V, IOUT = –3 A (1.66-Ω resistive load), and FSW = 1.2 MHz.
100
95
90
85
80
75
70
VIN = 12 V
VIN = 24 V
65
0
0.5
1
1.5
2
2.5
3
3.5
Output Current (A)
Figure 9-12. Efficiency
Figure 9-11. IBB Maximum Output Current
-5.05
-5.025
-5
-4.975
-4.95
VIN = 12 V
VIN = 24 V
0
0.5
1
1.5
2
2.5
3
3.5
Output Current (A)
Figure 9-13. Load Regulation
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10 Power Supply Recommendations
The TLVM13640 buck module is designed to operate over a wide input voltage range of 3 V to 36 V. The
characteristics of the input supply must be compatible with the Absolute Maximum Ratings and Recommended
Operating Conditions in this data sheet. In addition, the input supply must be capable of delivering the required
input current to the loaded regulator circuit. Estimate the average input current with Equation 10.
VOUT ∂IOUT
IIN
=
V ∂ h
IN
(10)
where
•
η is the efficiency.
If the module is connected to an input supply through long wires or PCB traces with a large impedance, take
special care to achieve stable performance. The parasitic inductance and resistance of the input cables can
have an adverse affect on module operation. More specifically, the parasitic inductance in combination with the
low-ESR ceramic input capacitors form an underdamped resonant circuit, possibly resulting in instability, voltage
transients, or both, each time the input supply is cycled ON and OFF. The parasitic resistance causes the input
voltage to dip during a load transient. If the module is operating close to the minimum input voltage, this dip can
cause false UVLO triggering and a system reset.
The best way to solve such issues is to reduce the distance from the input supply to the module and use an
electrolytic input capacitor in parallel with the ceramics. The moderate ESR of the electrolytic capacitor helps
damp the input resonant circuit and reduce any overshoot or undershoot at the input. A capacitance in the range
of 47 μF to 100 μF is usually sufficient to provide input parallel damping and helps hold the input voltage steady
during large load transients. A typical ESR of 0.1 Ω to 0.4 Ω provides enough damping for most input circuit
configurations.
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11 Layout
Proper PCB design and layout is important in high-current, fast-switching module circuits (with high internal
voltage and current slew rates) to achieve reliable device operation and design robustness. Furthermore, the
EMI performance of the module depends to a large extent on PCB layout.
11.1 Layout Guidelines
The following list summarizes the essential guidelines for PCB layout and component placement to optimze
DC/DC module performance, including thermals and EMI signature. Figure 11-1 and Figure 11-2 show a
recommended PCB layout for the TLVM13640 with optimized placement and routing of the power-stage and
small-signal components.
•
Place input capacitors as close as possible to the VIN pins. Note the dual and symmetrical arrangement
of the input capacitors based on the VIN1 and VIN2 pins located on each side of the module package.
The high-frequency currents are split in two and effectively flow in opposing directions such that the related
magnetic fields contributions cancel each other, leading to improved EMI performance.
– Use low-ESR 1206 or 1210 ceramic capacitors with X7R or X7S dielectric. The module has integrated
dual 0402 input capacitors for high-frequency bypass.
– Ground return paths for the input capacitors should consist of localized top-side planes that connect to the
PGND pads under the module.
– Even though the VIN pins are connected internally, use a wide polygon plane on a lower PCB layer to
connect these pins together and to the input supply.
•
•
Place output capacitors as close as possible to the VOUT pins. A similar dual and symmetrical arrangement
of the output capacitors enables magnetic field cancellation and EMI mitigation.
– Ground return paths for the output capacitors should consist of localized top-side planes that connect to
the PGND pads under the module.
– Even though the VOUT pins are connected internally, use a wide polygon plane on a lower PCB layer to
connect these pins together and to the load, thus reducing conduction loss and thermal stress.
Keep the FB trace as short as possible by placing the feedback resistors close to the FB pin. Reduce noise
sensitivity of the output voltage feedback path by placing the resistor divider close to the FB pin, rather than
close to the load. FB is the input to the voltage-loop error anplifier and represents a high-impedance node
sensitive to noise. Route a trace from the upper feedback resistor to the required point of output voltage
regulation.
•
•
Use a solid ground plane on the PCB layer directly below the top layer with the module. This plane acts as
a noise shield by minimizing the magnetic fields associated with the currents in the switching loops. Connect
AGND pins 6 and 11 directly to PGND pin 19 under the module.
Provide enough PCB area for proper heatsinking. Use sufficient copper area to acheive a low thermal
impedance commensurate with the maximum load current and ambient temperature conditions. Provide
adequate heatsinking for the TLVM13640 to keep the junction temperature below 150°C. For operation at
full rated load, the top-side ground plane is an important heat-dissipating area. Use an array of heat-sinking
vias to connect the exposed pads (PGND) of the package to the PCB ground plane. If the PCB has multiple
copper layers, connect these thermal vias to inner-layer ground planes. Make the top and bottom PCB layers
preferably with two-ounce copper thickness (and no less than one ounce).
11.1.1 Thermal Design and Layout
For a DC/DC module to be useful over a particular temperature range, the package must allow for the efficient
removal of the heat produced while keeping the junction temperature within rated limits. The TLVM13640 module
is available in a small 5.5-mm × 5-mm 20-pin QFN (RDL) package to cover a range of application requirements.
The Thermal Information table summarizes the thermal metrics of this package with related detail provided by
the Semiconductor and IC Package Thermal Metrics Application Report.
The 20-pin QFN package offers a means of removing heat through the exposed thermal pads at the base of
the package. This allows a significant improvement in heatsinking, and it becomes imperative that the PCB
is designed with thermal lands, thermal vias, and one or more ground planes to complete the heat removal
subsystem. The exposed pads of the TLVM13640 are soldered to the ground-connected copper lands on the
PCB directly underneath the device package, reducing the thermal resistance to a very low value.
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Preferably, use a four-layer board with 2-oz copper thickness for all layers to provide low impedance, proper
shielding and lower thermal resistance. Numerous vias with a 0.3-mm diameter connected from the thermal
lands to the internal and solder-side ground planes are vital to promote heat transfer. In a multi-layer PCB
stack-up, a solid ground plane is typically placed on the PCB layer below the power-stage components. Not only
does this provide a plane for the power-stage currents to flow, but it also represents a thermally conductive path
away from the heat-generating device.
11.2 Layout Example
Figure 11-1. Typical Layout
Place the feedback
components close to the FB pin
Legend
Top layer copper
EN
Layer-2 GND plane
RT
VIN
VIN
VOUT
Input
capacitor
Top solder
Output
capacitor
FB
Position the input
capacitors very close
to the VIN pins
Place an array of
PGND vias close to the
IC for heat spreading
PGND
Input
capacitor
Output
capacitor
VOUT
Place thermal vias at the
VOUT pins for heat spreading
Figure 11-2. Typical Top Layer Design
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11.2.1 Package Specifications
Table 11-1. Package Specifications Table
TLVM13640
VALUE
UNIT
Weight
748
mg
Flammability
Meets UL 94 V-0
MTBF calculated reliability
Per Bellcore TR-332, 50% stress, TA = 40°C, ground benign
2580
MHrs
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12 Device and Documentation Support
12.1 Device Support
12.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
12.1.2 Development Support
With an input operating voltage from 3 V to 36 V and rated output current from 2 A to 6 A, the
TLVM13620/30/40/60 family of synchronous buck power modules specified in Table 12-1 provides flexibility,
scalability and optimized solution size for a range of applications. These modules enable DC/DC solutions with
high density, low EMI and increased flexibility. Available EMI mitigation features include RBOOT-configured
switch-node slew rate control, fixed switching frequency, and integrated input bypass capacitors. All modules are
rated for an ambient temperature up to 105°C.
Table 12-1. Synchronous Buck DC/DC Power Module Family
DC/DC Module
TLVM13620
TLVM13630
TLVM13640
TLVM13660
Rated IOUT
Package
Dimensions
Features
EMI Mitigation
2 A
B0QFN (30)
6.0 × 4.0 × 1.8 mm
3 A
RT adjustable FSW
precision enable
,
Integrated input, VCC, and
BOOT capacitors
4 A
B3QFN (20)
5.5 × 5.0 × 4.0 mm
6 A
For development support see the following:
•
•
•
•
•
•
•
•
•
TLVM13640 Quickstart Calculator
TLVM13640 Simulation Models
TLVM13660 EVM user's guide
TLVM13660 EVM Layout Files (Altium)
For TI's reference design library, visit the TI Reference Design library.
For TI's WEBENCH Design Environment, visit the WEBENCH® Design Center.
To design a low-EMI power supply, review TI's comprehensive EMI Training Series.
To design an inverting buck-boost (IBB) regulator, visit DC/DC inverting buck-boost modules.
TI Reference Designs:
– Multiple Output Power Solution For Kintex 7 Application
– Arria V Power Reference Design
– Altera Cyclone V SoC Power Supply Reference Design
– Space-optimized DC/DC Inverting Power Module Reference Design With Minimal BOM Count
– 3- To 11.5-VIN, –5-VOUT, 1.5-A Inverting Power Module Reference Design For Small, Low-noise Systems
Technical Articles:
– Powering Medical Imaging Applications With DC/DC Buck Converters
– How To Create A Programmable Output Inverting Buck-boost Regulator
To view a related device of this product, see the LM61460 36-V, 6-A synchronous buck converter.
•
•
12.1.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the TLVM13640 module with WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
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•
•
•
•
Run electrical simulations to see important waveforms and circuit performance.
Run thermal simulations to understand board thermal performance.
Export customized schematic and layout into popular CAD formats.
Print PDF reports for the design, and share the design with colleagues.
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
12.2 Documentation Support
12.2.1 Related Documentation
For related documentation, see the following:
•
•
Texas Instruments, Innovative DC/DC Power Modules selection guide
Texas Instruments, Enabling Small, Cool and Quiet Power Modules with Enhanced HotRod™ QFN Package
Technology white paper
•
•
•
•
•
•
•
•
•
Texas Instruments, Benefits and Trade-offs of Various Power-Module Package Options white paper
Texas Instruments, Simplify Low EMI Design with Power Modules white paper
Texas Instruments, Power Modules for Lab Instrumentation white paper
Texas Instruments, An Engineer's Guide To EMI In DC/DC Regulators e-book
Texas Instruments, Soldering Considerations for Power Modules application report
Texas Instruments, Practical Thermal Design With DC/DC Power Modules application report
Texas Instruments, Using New Thermal Metrics application report
Texas Instruments, AN-2020 Thermal Design By Insight, Not Hindsight application report
Texas Instruments, Using the TPSM53602/3/4 for Negative Output Inverting Buck-Boost Applications
application report
12.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
12.4 Support Resources
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from the experts. Search existing answers or ask your own question to get the quick design help you need.
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12.5 Trademarks
HotRod™ and TI E2E™ are trademarks of Texas Instruments.
WEBENCH® is a registered trademark of Texas Instruments.
All trademarks are the property of their respective owners.
12.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.7 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this datasheet, refer to the left-hand navigation.
Copyright © 2022 Texas Instruments Incorporated
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33
Product Folder Links: TLVM13640
PACKAGE OPTION ADDENDUM
www.ti.com
12-May-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TLVM13640RDLR
ACTIVE
B3QFN
RDL
20
1000
RoHS Exempt
& Green
NIPDAU
Level-3-250C-168 HR
-40 to 125
TLVM13640
B1
Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
25-Apr-2022
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TLVM13640RDLR
B3QFN
RDL
20
1000
330.0
16.4
5.28
5.78
4.28
8.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
25-Apr-2022
*All dimensions are nominal
Device
Package Type Package Drawing Pins
B3QFN RDL 20
SPQ
Length (mm) Width (mm) Height (mm)
336.0 336.0 48.0
TLVM13640RDLR
1000
Pack Materials-Page 2
PACKAGE OUTLINE
B3QFN - 4.1 mm max height
PLASTIC QUAD FLAT PACK- NO LEAD
RDL0020A
5.1
4.9
A
B
5.6
5.4
PIN 1 INDEX AREA
4.1
3.9
C
SEATING PLANE
0.08
C
1.63
1.53
4X
1.3
1.1
4X
(0.20) TYP
PKG
(0.2) TYP
8
9
0.92
0.82
0.875
20
4X
0.35
0.15
0.1
12X
1.275
PKG
19
18
C
A B
0.05
C
2X (0.537)
2X (1.612)
10X 0.5
17
16
1
0.925
0.6
4X
0.4
0.1
0.8
0.6
C
A B
12X
0.05
C
PIN 1 ID
(OPTIONAL)
4226416/B 04/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
B3QFN - 4.1 mm max height
PLASTIC QUAD FLAT PACK- NO LEAD
RDL0020A
PKG
4X (1.4)
(Ø0.2) VIA
TYP
4X (0.5)
(0.5) TYP
16
1
2X (0.925)
17
10X (0.25)
(1.075) TYP
18
PKG
2X (0.538)
10X (0.50)
19
4X (0.875)
20
10X (0.9)
2X (0.875)
8
9
(R0.05) TYP
4X (1.58)
(4)
(4.5)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 15X
0.05 MAX
ALL AROUND
0.05 MAX
ALL AROUND
EXPOSED
METAL
EXPOSED
METAL
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL EDGE
SOLDER MASK
DEFINED
NON- SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4226416/B 04/2021
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
B3QFN - 4.1 mm max height
PLASTIC QUAD FLAT PACK- NO LEAD
RDL0020A
PKG
4X (1.35)
4X (0.45)
16
1
2X (0.925)
17
10X (0.2)
(1.075) TYP
18
PKG
2X (0.538)
10X (0.5)
19
4X (0.825)
10X (0.85)
20
2X (0.875)
9
8
4X (1.53)
(4)
(R0.05) TYP
(4.5)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 17,18, 19 & 20 :
91% PRINTED SOLDER COVERAGE BY AREA
SCALE: 15X
4226416/B 04/2021
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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相关型号:
TLVM13660RDLR
采用 5mm x 5.5mm 增强型 HotRod™ QFN 封装的 36V 输入、1V 至 6V 输出、6A 降压电源模块 | RDL | 20 | -40 to 125
TI
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