TM16TT64JPN-8A [TI]
16MX64 SYNCHRONOUS DRAM MODULE, 6ns, DMA168, DIMM-168;
| 型号： | TM16TT64JPN-8A |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 16MX64 SYNCHRONOUS DRAM MODULE, 6ns, DMA168, DIMM-168 动态存储器 内存集成电路 |
| 文件： | 总23页 (文件大小：370K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TM8TT64JPN, TM16TT64JPN
TM8TT72JPN, TM16TT72JPN
SYNCHRONOUS DYNAMIC RAM MODULES
SMMS700A – APRIL 1998 – REVISED AUGUST 1998
Organization:
Single 3.3-V Power Supply
– TM8TT64JPN . . . 8388608 × 64 Bits
– TM16TT64JPN . . . 16777216 × 64 Bits
– TM8TT72JPN . . . 8388608 × 72 Bits
– TM16TT72JPN . . . 16777216 × 72 Bits
(±10% Tolerance)
Byte-Read/Write Capability
High-Speed, Low-Noise Low-Voltage TTL
(LVTTL) Interface
Designed for 100-MHz 4-Clock Systems
Read Latencies 2 and 3 Supported
JEDEC 168-Pin Dual-In-Line Memory
Module (DIMM) Without Buffer for Use With
Socket
Supports Burst-Interleave and
Burst-Interrupt Operations
Burst Length Programmable to 1, 2, 4,
and 8
TM8TT64JPN — Uses Eight 64M-Bit
Synchronous Dynamic RAMs (SDRAMs)
(8M × 8-Bit) in Plastic Thin Small-Outline
Packages (TSOPs)
Four Banks for On-Chip Interleaving
(Gapless Access)
Ambient Temperature Range
0°C to 70°C
TM16TT64JPN — Uses Sixteen 64M-Bit
SDRAMs (8M × 8-Bit) in Plastic TSOPs
Gold-Plated Contacts
Pipeline Architecture
TM8TT72JPN — Uses Nine 64M-Bit
SDRAMs (8M × 8-Bit) in Plastic TSOPs
TM16TT72JPN — Uses Eighteen 64M-Bit
SDRAMs (8M × 8-Bit) in Plastic TSOPs
Serial Presence-Detect (SPD) Using
EEPROM
Performance Ranges:
SYNCHRONOUS
CLOCK CYCLE
TIME
ACCESS TIME
CLOCK TO
OUTPUT
REFRESH
INTERVAL
t
t
t
t
t
REF
CK3
CK2
AC3
AC2
’xTTxxJPN-8
8 ns
8 ns
10 ns
10 ns
6 ns
6 ns
6 ns
64 ms
64 ms
’xTTxxJPN-8A
7.5 ns
description
The TM8TT64JPN is a 64M-byte, 168-pin dual-in-line memory module (DIMM). The DIMM is composed of eight
TMS664814ADGE, 8388608 x 8-bit SDRAMs, each in a 400-mil, 54-pin plastic thin small-outline package
(TSOP) mounted on a substrate with decoupling capacitors. See the TMS664814 data sheet (literature number
SMOS695).
The TM16TT64JPN is a 128M-byte, 168-pin DIMM. The DIMM is composed of sixteen TMS664814ADGE,
8388608 x 8-bit SDRAMs, each in a 400-mil, 54-pin plastic TSOP mounted on a substrate with decoupling
capacitors. See the TMS664814 data sheet (literature number SMOS695).
The TM8TT72JPN is a 64M-byte, 168-pin DIMM. The DIMM is composed of nine TMS664814ADGE,
8388608 x 8-bit SDRAMs, each in a 400-mil, 54-pin plastic thin small-outline package (TSOP) mounted on a
substrate with decoupling capacitors. See the TMS664814 data sheet (literature number SMOS695).
The TM16TT72JPN is a 128M-byte, 168-pin DIMM. The DIMM is composed of eighteen TMS664814ADGE,
2097152 x 8-bit SDRAMs, each in a 400-mil, 54-pin plastic TSOP mounted on a substrate with decoupling
capacitors. See the TMS664814 data sheet (literature number SMOS695).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 1998, Texas Instruments Incorporated
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
1
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TM8TT64JPN, TM16TT64JPN
TM8TT72JPN, TM16TT72JPN
SYNCHRONOUS DYNAMIC RAM MODULES
SMMS700A – APRIL 1998 – REVISED AUGUST 1998
operation
The TM8TT64JPN operates as eight TMS664814DGE devices that are connected as shown in the
TM8TT64JPN functional block diagram. The TM16TT64JPN operates as 16 TMS664814ADGE devices
connected as shown in the TM16TT64JPN functional block diagram. The TM8TT72JPN operates as nine
TMS664814ADGE devices that are connected as shown in the TM8TT72JPN functional block diagram. The
TM16TT72JPN operates as 18 TMS664814ADGE devices connected as shown in the TM16TT72JPN
functional block diagram.
2
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TM8TT64JPN, TM16TT64JPN
TM8TT72JPN, TM16TT72JPN
SYNCHRONOUS DYNAMIC RAM MODULES
SMMS700A – APRIL 1998 – REVISED AUGUST 1998
DUAL-IN-LINE MEMORY MODULE
(TOP VIEW)
TM8TT64JPN TM16TT64JPN
(SIDE VIEW) (SIDE VIEW)
PIN NOMENCLATURE
A[0:11]
A[0:8]
Row Address Inputs
Column Address Inputs
Bank-Select Zero
Bank-Select One
Column-Address Strobe
Check Bit In/Check Bit Out
Clock Enable
A13/BA0
A12/BA1
CAS
CB[0:7]
CKE[0:1]
CK[0:3]
DQ[0:63]
DQMB[0:7]
1
System Clock
10
11
Data-In/Data-Out
Data-In/Data-Out
Mask Enable
NC
No Connect
RAS
S[0:3]
SA[0:2]
Row-Address Strobe
Chip-Select
Serial Presence-Detect (SPD)
Device Address Input
SPD Clock
SPD Address/Data
3.3-V Supply
Ground
SCL
SDA
V
DD
V
SS
WE
WP
Write Enable
Write Protect
40
41
84
3
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TM8TT64JPN, TM16TT64JPN
TM8TT72JPN, TM16TT72JPN
SYNCHRONOUS DYNAMIC RAM MODULES
SMMS700A – APRIL 1998 – REVISED AUGUST 1998
Pin Assignments
PIN
PIN
NAME
PIN
NAME
PIN
NAME
NO.
1
NAME
NO.
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
NO.
85
NO.
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
V
SS
V
SS
V
SS
V
SS
2
DQ0
DQ1
DQ2
DQ3
NC
S2
86
DQ32
DQ33
DQ34
DQ35
CKE0
S3
3
87
4
DQMB2
DQMB3
NC
88
DQMB6
DQMB7
NC
5
89
6
V
DD
90
V
DD
7
DQ4
DQ5
DQ6
DQ7
DQ8
V
DD
91
DQ36
DQ37
DQ38
DQ39
DQ40
V
DD
8
NC
NC
92
NC
NC
9
93
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
CB2
CB3
94
CB6
CB7
95
V
SS
V
SS
96
V
SS
V
SS
DQ9
DQ10
DQ11
DQ12
DQ13
DQ16
DQ17
DQ18
DQ19
97
DQ41
DQ42
DQ43
DQ44
DQ45
DQ48
DQ49
DQ50
DQ51
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
V
DD
V
DD
V
DD
DQ20
NC
V
DD
DQ52
NC
DQ14
DQ15
CB0
DQ46
DQ47
CB4
NC
NC
CKE1
NC
CB1
V
SS
CB5
V
SS
V
SS
DQ21
DQ22
DQ23
V
SS
DQ53
DQ54
DQ55
NC
NC
NC
NC
V
DD
V
SS
V
DD
V
SS
WE
DQ24
DQ25
DQ26
DQ27
CAS
DQ56
DQ57
DQ58
DQ59
DQMB0
DQMB1
S0
DQMB4
DQMB5
S1
NC
V
DD
RAS
V
DD
V
SS
DQ28
DQ29
DQ30
DQ31
V
SS
DQ60
DQ61
DQ62
DQ63
A0
A2
A1
A3
A4
A5
A6
V
SS
A7
V
SS
A8
CK2
NC
A9
CK3
NC
A10
A12/BA1
A13/BA0
A11
WP
SA0
SA1
SA2
V
V
SDA
SCL
V
DD
DD
CK1
NC
DD
CK0
V
DD
V
DD
4
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TM8TT64JPN, TM16TT64JPN
TM8TT72JPN, TM16TT72JPN
SYNCHRONOUS DYNAMIC RAM MODULES
SMMS700A – APRIL 1998 – REVISED AUGUST 1998
dual-in-line memory module and components
The dual-in-line memory module and components include:
PC substrate: 1,27 ± 0,1 mm (0.05 inch) nominal thickness; 0.005 inch/inch maximum warpage
Bypass capacitors: Multilayer ceramic
Contact area: Nickel plate and gold plate over copper
functional block diagram for the TM8TT64JPN
S0
R
R
C
C
CK: U0, U4
CK: U1, U5
CS
CS
†
†
CK0
R
R
C
C
U0
U4
DQMB0
DQ[0:7]
DQM
DQMB4
DQM
CK: U2, U6
CK: U3, U7
R
R
CK2
8
8
DQ[0:7]
DQ[32:39]
DQ[0:7]
R
R
C
C
CK1
CK3
C
C
CS
CS
U1
U5
DQMB1
DQM
DQMB5
DQM
R
R
8
8
DQ[8:15]
DQ[0:7]
DQ[40:47]
DQ[0:7]
R = 10 Ω
R
= 10 Ω
C
C = 10 pF
S2
CS
CS
V
DD
U[0:7]
U2
U6
DQMB2
DQM
DQMB6
DQM
Two 0.1 µF
per SDRAM
R
R
8
8
DQ[16:23]
DQ[0:7]
DQ[48:55]
V
SS
U[0:7]
DQ[0:7]
CS
CS
SPD EEPROM
U3
U7
SCL
WP
DQMB3
DQM
DQMB7
DQM
SDA
R
R
8
8
DQ[24:31]
DQ[0:7]
DQ[56:63]
DQ[0:7]
A0
A1
A2
SA0 SA1 SA2
47 kΩ
RAS
CAS
WE
RAS: SDRAM U[0:7]
CAS: SDRAM U[0:7]
WE: SDRAM U[0:7]
CKE: SDRAM U[0:7]
A[0:13]: SDRAM U[0:7]
CKE0
A[0:13]
LEGEND:
CS
SPD
=
=
Chip select
Serial Presence Detect
†
Additional 3.3 pF capacity is used to balance loads among clocks.
5
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TM8TT64JPN, TM16TT64JPN
TM8TT72JPN, TM16TT72JPN
SYNCHRONOUS DYNAMIC RAM MODULES
SMMS700A – APRIL 1998 – REVISED AUGUST 1998
functional block diagram for the TM16TT64JPN
S1
S0
V
U[0:7], UB[0:7]
Two 0.1 µF
per SDRAM
U[0:7], UB[0:7]
DD
CS
CS
CS
CS
V
SS
U0
UB0
U4
UB4
R = 10 Ω
Rc = 10 Ω
DQMB0
DQ[0:7]
DQM
DQM
DQMB4
DQM
DQM
R
R
8
8
DQ[0:7]
DQ[0:7]
DQ[32:39]
DQ[0:7]
DQ[0:7]
V
DD
CS
CS
CS
CS
10 kΩ
CKE1
CKE0
CKE: UB[0:7]
CKE: U[0:7]
U1
UB1
U5
UB5
DQMB1
DQM
DQM
DQMB5
DQM
DQM
R
R
8
8
RAS
CAS
RAS: U[0:7], UB[0:7]
CAS: U[0:7], UB[0:7]
DQ[8:15]
DQ[0:7]
DQ[0:7]
DQ[40:47]
DQ[0:7]
DQ[0:7]
WE
WE: U[0:7], UB[0:7]
A[0:13]
A[0:13]: U[0:7], UB[0:7]
R
C
S3
S2
CK: U0, U4
CK: U1, U5
†
R
R
R
CK0
C
C
C
CS
CS
CS
CS
CK: UB0, UB4
CK: UB1, UB5
†
CK1
U2
UB2
U6
UB6
R
R
C
CK: U2, U6
CK: U3, U7
DQMB2
DQM
DQM
DQMB6
DQM
DQM
†
CK2
R
R
C
8
8
DQ[16:23]
DQ[0:7]
DQ[0:7]
DQ[48:55]
DQ[0:7]
DQ[0:7]
R
R
C
CK: UB2, UB6
CK: UB3, UB7
†
CK3
C
CS
CS
CS
CS
U3
U7
UB3
UB7
SPD EEPROM
DQMB3
DQM
DQMB7
DQM
DQM
DQM
SDA
SCL
WP
R
R
8
8
DQ[24:31]
DQ[0:7]
DQ[56:63]
DQ[0:7]
DQ[0:7]
DQ[0:7]
A0
A1
A2
SA0 SA1 SA2
47 kΩ
†
Additional 3.3 pF capacity is used to balance loads among clocks.
6
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TM8TT64JPN, TM16TT64JPN
TM8TT72JPN, TM16TT72JPN
SYNCHRONOUS DYNAMIC RAM MODULES
SMMS700A – APRIL 1998 – REVISED AUGUST 1998
functional block diagram for the TM8TT72JPN
R
R
B
B
S0
CS
U0
U0, U4
CK0
†
CS
U1, U5, U8
U4
U5
R
R
DQMB0
DQ[0:7]
DQM
DQMB4
DQM
C
C
R
R
R
U2, U6
U3, U7
8
8
8
DQ[0:7]
DQ[32:39]
DQ[0:7]
CK2
R
R
C
C
CS
CS
CK1
C
C
U1
U8
DQMB1
DQM
DQMB5
DQM
R
R
DQ[8:15]
8
8
DQ[0:7]
DQ[40:47]
DQ[0:7]
CK3
R = 10 Ω
CS
R
R
= 5 Ω
= 10Ω
B
C
DQMB1
CB[0:7]
DQM
C = 10 pF
DQ[0:7]
S2
V
DD
U[0:8]
Two 0.1 µF
per SDRAM
CS
CS
U2
U3
U6
U7
DQMB2
DQM
DQMB6
DQM
V
SS
U[0:8]
R
R
R
R
8
8
8
8
DQ[16:23]
DQ[0:7]
DQ[48:55]
DQ[0:7]
CS
CS
DQMB3
DQM
DQMB7
DQM
DQ[24:31]
DQ[0:7]
DQ[56:63]
DQ[0:7]
RAS
CAS
RAS: SDRAM U[0:8]
CAS: SDRAM U[0:8]
WE: SDRAM U[0:8]
CKE: SDRAM U[0:8]
A[0:13]: SDRAM U[0:8]
SPD EEPROM
SCL
WP
SDA
A0
A1
A2
WE
SA0 SA1 SA2
CKE0
A[0:13]
47 kΩ
†
Additional 3.3 pF capacity is used to balance loads among clocks.
7
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TM8TT64JPN, TM16TT64JPN
TM8TT72JPN, TM16TT72JPN
SYNCHRONOUS DYNAMIC RAM MODULES
SMMS700A – APRIL 1998 – REVISED AUGUST 1998
functional block diagram for the TM16TT72JPN
S1
S0
V
U[0:8], UB[0:8]
Two 0.1 µF
per SDRAM
U[0:8], UB[0:8]
DD
CS
CS
CS
CS
V
SS
U0
UB0
U4
UB4
R = 10 Ω
DQMB0
DQ[0:7]
DQM
DQM
DQMB4
DQM
DQM
R
R
= 10Ω
= 5Ω
C
B
R
R
R
R
8
8
8
8
DQ[0:7]
DQ[0:7]
DQ[32:39]
DQ[0:7]
DQ[0:7]
R
R
B
CK: U0, U4
CS
CS
CS
CS
CK0
CK1
B
CK: U1, U5, U8
R
R
B
U1
UB1
U5
UB5
CK: UB0, UB4
DQMB1
DQM
DQM
DQMB5
DQM
DQM
B
R
CK: UB1, UB5, UB8
8
DQ[8:15]
DQ[0:7]
DQ[0:7]
DQ[40:47]
DQ[0:7]
DQ[0:7]
R
R
C
CK: U2, U6
CK: U3, U7
†
CS
CS
CK2
C
R
R
C
U8
UB8
CK: UB2, UB6
CK: UB3, UB7
†
CK3
C
DQMB1
CB[0:7]
DQM
DQM
DQ[0:7]
DQ[0:7]
V
DD
S3
S2
10 kΩ
CKE: UB[0:8]
CKE1
CKE0
RAS
CKE: U[0:8]
CS
CS
CS
CS
RAS: U[0:8], UB[0:8]
CAS: U[0:8], UB[0:8]
WE: U[0:8], UB[0:8]
A[0:13]: U[0:8], UB[0:8]
U2
UB2
U6
UB6
CAS
DQMB2
DQM
DQM
DQMB6
DQM
DQM
WE
R
R
8
8
DQ[16:23]
DQ[0:7]
DQ[0:7]
DQ[48:55]
DQ[0:7]
DQ[0:7]
A[0:13]
CS
CS
CS
CS
SPD EEPROM
SDA
SCL
WP
U3
U7
UB3
UB7
A0
A1
A2
DQMB3
DQM
DQMB7
DQM
DQM
DQM
SA0 SA1 SA2
R
R
8
8
47 kΩ
DQ[24:31]
DQ[0:7]
DQ[56:63]
DQ[0:7]
DQ[0:7]
DQ[0:7]
†
Additional 3.3 pF capacity is used to balance loads among clocks.
8
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TM8TT64JPN, TM16TT64JPN
TM8TT72JPN, TM16TT72JPN
SYNCHRONOUS DYNAMIC RAM MODULES
SMMS700A – APRIL 1998 – REVISED AUGUST 1998
†
absolute maximum ratings over ambient temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
DD
Voltage range on any pin (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 4.6 V
Short-circuit output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Power dissipation: TM8TT64JPN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 W
TM16TT64JPN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 W
TM8TT72JPN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 W
TM16TT72JPN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 W
Ambient temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
A
stg
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 150°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to V
.
SS
recommended operating conditions
MIN NOM
MAX
UNIT
V
V
V
V
V
V
Supply voltage
3
3.3
0
3.6
DD
Supply voltage
V
SS
High-level input voltage
High-level input voltage for SPD device
Low-level input voltage
Ambient temperature
2
2
V
DD
+ 0.3
V
IH
5.5
0.8
70
V
IH-SPD
IL
–0.3
0
V
T
A
°C
capacitance over recommended ranges of supply voltage and ambient temperature,
‡
f = 1 MHz (see Note 2)
’xTTxxJPN
PARAMETER
UNIT
MIN
2.5
MAX
C
C
C
C
C
C
C
C
)
)
Input capacitance, CK input
4
5
pF
pF
pF
pF
pF
pF
pF
pF
i(CK
Input capacitance, address and control inputs: A0–A13, RAS, CAS, WE
Input capacitance, CKE input
2.5
i(AC
)
5
i(CKE
Output capacitance
4
2.5
2.5
6.5
5
o
)
Input capacitance, DQMBx input
i(DQMBx
)
Input capacitance, Sx input
5
i(Sx
)
SDA Input/output capacitance
9
i/o(SDA
)
Input capacitance, SA0, SA1, SA2, SCL inputs
7
i(SPD
‡
Specifications in this table represent a single SDRAM device.
NOTE 2: = 3.3 V ± 0.3 V. Bias on pins under test is 0 V.
V
DD
9
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TM8TT64JPN, TM16TT64JPN
TM8TT72JPN, TM16TT72JPN
SYNCHRONOUS DYNAMIC RAM MODULES
SMMS700A – APRIL 1998 – REVISED AUGUST 1998
electrical characteristics over recommended ranges of supply voltage and ambient temperature
†
(unless otherwise noted) (see Note 3)
TMxTTxxJPN
’xTTxxJPN-8
’xTTxxJPN-8A
PARAMETER
TEST CONDITIONS
= – 2 mA
UNIT
MIN
MAX
MIN
MAX
V
V
High-level output voltage
Low-level output voltage
I
I
2.4
2.4
V
V
OH
OH
= 2 mA
0.4
10
0.4
10
10
95
OL
OL
0 V ≤ V ≤ V
All other pins = 0 V to V
+ 0.3 V,
I
DD
I
I
Input current (leakage)
Output current (leakage)
µA
µA
I
DD
0 V ≤ V ≤ V
+0.3 V, Output disabled
10
O
O
DD
Burst length = 1,
115
mA
CAS latency = 2
t
I
≥ t MIN,
I
Operating current
CC1
/I = 0 mA
OH OL
125
1
95
1
mA
mA
mA
CAS latency = 3
(See Notes 4, 5, and 6)
I
I
CKE ≤ V MAX, t
= 15 ns (see Note 7)
CK
CC2P
IL
Precharge standby current in
power-down mode
CKE and CK ≤ V , MAX, t
(see Note 8)
= ∞
CK
IL
1
1
CC2PS
I
I
CKE ≥ V MIN, t
IH
= 15 ns (see Note 7)
= 15 ns
CK
40
5
40
5
mA
mA
CC2N
Active standby current in
non-power-down mode
CK
= ∞ (see Note 8)
CK
t
CC2NS
CKE ≤ V MAX, t
IL
(see Notes 4 and 7)
I
I
I
8
8
8
8
mA
mA
mA
CC3P
CC3PS
CC3N
Active standby current in
power-down mode
CKE and CK ≤ V MAX, t
= ∞
CK
IL
(see Notes 4 and 8)
CKE ≥ V MIN,
IH
50
50
t
= 15 ns (see Notes 4 and 7)
CK
Precharge standby current in
non-power-down mode
CKE ≥ V MIN,
IH
CK ≤ V MAX, t = ∞
CK
I
I
15
15
mA
CC3NS
IL
(see Notes 4 and 8)
Page burst,
CAS latency = 2
CAS latency = 3
165
225
120
165
mA
mA
I /I = 0 mA
OH OL
All banks activated,
= one cycle
Burst current
CC4
n
CCD
(see Notes 9 and 10)
CAS latency = 2
CAS latency = 3
150
150
1
150
150
1
mA
mA
mA
t
≤ t
MIN
RC RC
I
I
Auto-refresh current
Self-refresh current
CC5
(see Notes 5 and 8)
CKE ≤ V MAX
IL
CC6
†
Specifications in this table represent a single SDRAM device.
NOTES: 3. All specifications apply to the device after power-up initialization. All control and address inputs must be stable and valid.
4. Only one bank is activated.
5.
t ≥ t MIN
RC RC
6. Control and address inputs change state twice during t
.
RC
7. Control and address inputs change state once every 30 ns.
8. Control and address inputs do not change state (stable).
9. Control and address inputs change once every cycle.
10. Continuous burst access, n
CCD
= 1 cycle
10
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TM8TT64JPN, TM16TT64JPN
TM8TT72JPN, TM16TT72JPN
SYNCHRONOUS DYNAMIC RAM MODULES
SMMS700A – APRIL 1998 – REVISED AUGUST 1998
†‡
ac timing requirements
’xTTxxJPN-8
’xxTTxxJPN-8A
UNIT
MIN
10
8
MAX
MIN
15
8
MAX
t
t
t
t
Cycle time, CK
CAS latency = 2
CAS latency = 3
ns
ns
ns
ns
CK2
CK3
CH
Cycle time, CK
Pulse duration, CK high
Pulse duraction, CK low
3
3
3
3
CL
Access time, CK high to data out
(see Note 11)
t
CAS latency = 2
CAS latency = 3
6
6
7.5
6
ns
AC2
Access time, CK high to data out
(see Note 11)
t
t
t
ns
ns
ns
AC3
OH
LZ
Hold time, CK high to data out with 50-pF load
3
1
3
1
Delay time, CK high to DQ in low-impedance state
(see Note 12)
Delay time, CK high to DQ in high-impedance state
(see Note 13)
t
8
8
ns
HZ
t
t
t
t
t
Setup time, address, control, and data input
Hold time, address, control, and data input
Power down/self–refresh exit time
2
1
8
2
1
ns
ns
ns
ns
ns
IS
IH
8
CESP
RAS
RC
Delay time, ACTV command to DEAC or DCAB command
48 100000
68
48
68
Delay time, ACTV,MRS,REFR,or SLFR to ACTV,MRS,REFR,or SLFR command
Delay time ACTV command to READ,READ–P,WRT,or WRT–P command (see
Note 14)
t
20
20
ns
RCD
t
t
t
t
t
t
Delay time, DEAC or DCAB command to ACTV,MRS,REFR, or SLFR command
Delay time,ACTV command in one bank to ACTV command in the other bank
Delay time,MRS command to ACTV,MRS,REFR,or SLFR command
Final data out of READ–P operation to ACTV,MRS,SLFR,or REFR command
Final data in of WRT–P operation to ACTV,MRS,SLFR,or REFR command
Transition time
20
16
16
20
16
16
ns
ns
ns
ns
ns
ms
RP
RRD
RSA
APR
APW
T
t
–(CL–1)*t
t –(CL–1) t
CK RP * CK
RP
t
+ 1 t
t
+ 1 t
1
RP
CK
RP
CK
1
5
5
t
Refresh interval
64
64
ms
REF
n
n
n
n
n
n
Delay time, READ or WRT command to an interrupting command
Delay time, CS low or high to input enabled or inhibited
1
0
1
1
0
2
1
0
1
1
0
2
cycles
cycles
cycles
cycles
cycles
cycles
CCD
CDD
CLE
CWL
DID
0
1
0
1
Delay time, CKE high or low to CLK enabled or disabled
Delay time, final data in of WRT operation to READ, READ-P, WRT, or WRT-P
Delay time, ENBL or MASK command to enabled or masked data in
Delay time, ENBL or MASK command to enabled or masked data out
0
2
0
2
DOD
Delay time, DEAC or DCAB, command to DQ in
CAS latency = 2
n
2
2
cycles
HZP2
high-impedance state
†
‡
All references are made to the rising transition of CK unless otherwise noted.
Specifications in this table represent a single SDRAM device.
NOTES: 11. t
is referenced from the rising transition of CK that precedes the data-out cycle. For example, the first data out t is referenced
AC
AC
from the rising transition of CK that is read latency (one cycle after the READ command). Access time is measured at output
reference level 1.4 V.
12.
13.
t
is measured from the rising transition of CK that is read latency (one cycle after the READ command).
(max) defines the time at which the outputs are no longer driven and is not referenced to output voltage levels.
LZ
t
HZ
14. For read or write operations with automatic deactivate, t
must be set to satisfy minimum t .
RCD
RAS
11
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TM8TT64JPN, TM16TT64JPN
TM8TT72JPN, TM16TT72JPN
SYNCHRONOUS DYNAMIC RAM MODULES
SMMS700A – APRIL 1998 – REVISED AUGUST 1998
†‡
ac timing requirements (continued)
’xTTxxJPN-8
’xTTxxJPN-8A
UNIT
MIN
MAX
MIN
MAX
Delay time, DEAC or DCAB, command to DQ in
high-impedance state
n
CAS latency = 3
3
0
3
0
cycles
HZP3
n
n
Delay time, WRT command to first data in
0
1
0
1
cycles
cycles
WCD
Delay time, final data in of WRT operation to DEAC or DCAB command
WR
†
‡
All references are made to the rising transition of CK unless otherwise noted.
Specifications in this table represent a single SDRAM device.
12
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TM8TT64JPN, TM16TT64JPN
TM8TT72JPN, TM16TT72JPN
SYNCHRONOUS DYNAMIC RAM MODULES
SMMS700A – APRIL 1998 – REVISED AUGUST 1998
serial presence detect
The serial presence detect (SPD) is contained in a 256-byte serial EEPROM located on the module. The SPD
nonvolatile EEPROM contains various data such as module configuration, SDRAM organization, and timing
parameters (see tables below). Only the first 128 bytes are programmed by Texas Instruments, while the
remaining 128 bytes are available for customer use. Programming is done through an IIC bus using the clock
(SCL) and data (SDA) signals. All Texas Instruments modules comply with the current JEDEC SPD Standard.
See the Texas Instruments Serial Presence Detect Technical Reference (literature number SMMU001) for
further details.
Tables in this section list the SPD contents as follows:
Table 1–TM8TT64JPN
Table 3–TM8TT72JPN
Table 2–TM16TT64JPN
Table 4–TM16TT72JPN
Table 1. Serial-Presence-Detect Data for the TM8TT64JPN
TM8TT64JPN-8
TM8TT64JPN-8A
BYTE
NO.
DESCRIPTION OF FUNCTION
ITEM
DATA
ITEM
DATA
Defines number of bytes written into serial memory during module
manufacturing
0
128 bytes
80h
128 bytes
80h
1
2
Total number of bytes of SPD memory device
Fundamental memory type (FPM, EDO, SDRAM, . . .)
Number of row addresses on this assembly
Number of column addresses on this assembly
Number of module rows on this assembly
256 bytes
SDRAM
12
08h
04h
0Ch
09h
01h
40h
00h
01h
80h
60h
00h
256 bytes
SDRAM
12
08h
04h
0Ch
09h
01h
40h
00h
01h
80h
60h
00h
3
4
9
9
5
1 bank
64 bits
1 bank
64 bits
6
Data width of this assembly
7
Data width continuation
8
Voltage interface standard of this assembly
SDRAM cycle time at maximum supported CAS latency (CL), CL = X
SDRAM access from clock at CL = X
LVTTL
LVTTL
9
t
t
= 8 ns
= 6 ns
t
t
= 8 ns
= 6 ns
CK
CK
10
11
AC
AC
DIMM configuration type (non-parity, parity, error correcting code [ECC])
Non-Parity
Non-Parity
15.6 µs/
self-refresh
15.6 µs/
self-refresh
12
Refresh rate/type
80h
80h
13
14
15
16
17
18
19
20
SDRAM width, primary DRAM
Error-checking SDRAM data width
Minimum clock delay, back-to-back random column addresses
Burst lengths supported
x8
N/A
08h
00h
01h
0Fh
04h
06h
01h
01h
x8
N/A
08h
00h
01h
0Fh
04h
06h
01h
01h
1 CK cycle
1, 2, 4, 8
4 banks
2, 3
1 CK cycle
1, 2, 4, 8
4 banks
2, 3
Number of banks on each SDRAM device
CAS latencies supported
CS latency
0
0
Write latency
0
0
Non-buffered/
Non-registered
Non-buffered/
Non-registered
21
22
23
SDRAM module attributes
00h
0Eh
A0h
00h
0Eh
F0h
V
DD
tolerance =
(+10%),
Burst
V
DD
tolerance =
(+10%),
Burst
SDRAM device attributes: general
read/write,
precharge all,
auto precharge
read/write,
precharge all,
auto precharge
Minimum clock cycle time at
CL = X – 1
t
= 10 ns
t
= 15 ns
CK
CK
13
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TM8TT64JPN, TM16TT64JPN
TM8TT72JPN, TM16TT72JPN
SYNCHRONOUS DYNAMIC RAM MODULES
SMMS700A – APRIL 1998 – REVISED AUGUST 1998
serial presence detect (continued)
Table 1. Serial-Presence-Detect Data for the TM8TT64JPN (Continued)
TM8TT64JPN-8
ITEM DATA
= 6 ns
TM8TT64JPN-8A
ITEM DATA
BYTE
NO.
DESCRIPTION OF FUNCTION
24
25
Maximum data-access time from clock at CL = X – 1
t
60h
00h
t
= 7.5 ns
75h
AC
AC
Minimum clock cycle time at
CL = X – 2
N/A
N/A
00h
26
27
Maximum data-access time from clock at CL = X – 2
Minimum row precharge time
N/A
00h
14h
10h
10h
30h
10h
20h
10h
20h
10h
N/A
00h
14h
10h
14h
30h
10h
20h
10h
20h
10h
t
= 20 ns
t
= 20 ns
RP
RP
28
Minimum row-active to row-active delay
Minimum RAS-to-CAS delay
t
t
= 16 ns
= 16 ns
= 48 ns
t
= 16 ns
= 20 ns
= 48 ns
RRD
RCD
RRD
29
t
RCD
30
Minimum RAS pulse width
t
t
RAS
RAS
31
Density of each bank on module
Command and address signal input setup time
Command and address signal input hold time
Data signal input setup time
64M Bytes
tIS = 2 ns
tIH = 1 ns
tIS = 2 ns
tIH = 1 ns
64M Bytes
tIS = 2 ns
tIH = 1 ns
tIS = 2 ns
tIH = 1 ns
32
33
34
35
Data signal input hold time
36–61
62
Superset features (may be used in the future)
SPD revision
Rev. 1.2
95
12h
5Fh
Rev. 1.2
196
12h
C4h
63
Checksum for byte 0–62
9700...
00h
9700...
00h
64–71
Manufacturer’s JEDEC ID code per JEP–106E
97h
97h
†
72
73–90
91
Manufacturing location
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
†
Manufacturer’s part number
†
Die revision code
†
PCB revision code
92
†
93–94
95–98
Manufacturing date
†
Assembly serial number
†
99–125 Manufacturer-specific data
†
126–127 Vendor-specific data
‡
128–166 System-integrator-specific data
167–255 Open
†
‡
TBD indicates values are determined at manufacturing time and are module-dependent.
These TBD values are determined and programmed by the customer (optional).
14
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TM8TT64JPN, TM16TT64JPN
TM8TT72JPN, TM16TT72JPN
SYNCHRONOUS DYNAMIC RAM MODULES
SMMS700A – APRIL 1998 – REVISED AUGUST 1998
serial presence detect (continued)
Table 2. Serial-Presence-Detect Data for the TM16TT64JPN
TM16TT64JPN-8
TM16TT64JPN-8A
BYTE
NO.
DESCRIPTION OF FUNCTION
ITEM
DATA
ITEM
DATA
Defines number of bytes written into serial memory during module
manufacturing
0
128 bytes
80h
128 bytes
80h
1
2
Total number of bytes of SPD memory device
Fundamental memory type (FPM, EDO, SDRAM, . . .)
Number of row addresses on this assembly
Number of column addresses on this assembly
Number of module rows on this assembly
256 bytes
SDRAM
12
08h
04h
0Ch
09h
02h
40h
00h
01h
80h
60h
00h
256 bytes
SDRAM
12
08h
04h
0Ch
09h
02h
40h
00h
01h
80h
60h
00h
3
4
9
9
5
2 banks
64 bits
2 banks
64 bits
6
Data width of this assembly
7
Data width continuation
8
Voltage interface standard of this assembly
SDRAM cycle time at maximum supported CAS latency (CL), CL = X
SDRAM access from clock at CL = X
LVTTL
LVTTL
9
t
t
= 8 ns
= 6 ns
t
t
= 8 ns
= 6 ns
CK
CK
10
11
AC
AC
DIMM configuration type (non-parity, parity, error correcting code [ECC])
Non-Parity
Non-Parity
15.6 µs/
self-refresh
15.6 µs/
self-refresh
12
Refresh rate/type
80h
80h
13
14
15
16
17
18
19
20
SDRAM width, primary DRAM
Error-checking SDRAM data width
Minimum clock delay, back-to-back random column addresses
Burst lengths supported
x8
N/A
08h
00h
01h
0Fh
04h
06h
01h
01h
x8
N/A
08h
00h
01h
0Fh
04h
06h
01h
01h
1 CK cycle
1, 2, 4, 8
4 banks
2, 3
1 CK cycle
1, 2, 4, 8
4 banks
2, 3
Number of banks on each SDRAM device
CAS latencies supported
CS latency
0
0
Write latency
0
0
Non-buffered/
Non-registered
Non-buffered/
Non-registered
21
SDRAM module attributes
00h
00h
V tolerance =
DD
(+10%).
V tolerance =
DD
(+10%).
Burst read/write,
precharge all,
Burst read/write,
precharge all,
22
SDRAM device attributes: general
0Eh
0Eh
auto precharge
auto precharge
23
24
25
26
Minimum clock cycle time at CL = X – 1
t
= 10 ns
= 6 ns
A0h
60h
00h
00h
t
= 15 ns
= 7.5 ns
N/A
F0h
75h
00h
00h
CK
CK
Maximum data-access time from clock at
CL = X – 1
t
t
AC
AC
Minimum clock cycle time at CL = X – 2
N/A
Maximum data-access time from clock at
CL = X – 2
N/A
N/A
27
28
29
30
Minimum row precharge time
Minimum row-active to row-active delay
Minimum RAS-to-CAS delay
Minimum RAS pulse width
t
= 20 ns
14h
10h
14h
30h
t
= 20 ns
1Eh
14h
1Eh
32h
RP
RP
t
t
= 16 ns
= 20 ns
= 48 ns
t
= 16 ns
= 20 ns
= 48 ns
RRD
RCD
RRD
t
RCD
t
t
RAS
RAS
15
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TM8TT64JPN, TM16TT64JPN
TM8TT72JPN, TM16TT72JPN
SYNCHRONOUS DYNAMIC RAM MODULES
SMMS700A – APRIL 1998 – REVISED AUGUST 1998
serial presence detect (continued)
Table 2. Serial-Presence-Detect Data for the TM16TT64JPN (Continued)
TM16TT64JPN-8
TM16TT64JPN-8A
BYTE
NO.
DESCRIPTION OF FUNCTION
Density of each bank on module
ITEM
DATA
ITEM
DATA
31
32
64M Bytes
tIS = 2 ns
tIH = 1 ns
tIS = 2 ns
tIH = 1 ns
10h
20h
10h
20h
10h
64M Bytes
tIS = 2 ns
tIH = 1 ns
tIS = 2 ns
tIH = 1 ns
10h
20h
10h
20h
10h
Command and address signal input setup time
Command and address signal input hold time
Data signal input setup time
33
34
35
Data signal input hold time
36–61
62
Superset features (may be used in the future)
SPD revision
Rev. 1.2
96
12h
60h
Rev. 1.2
197
12h
C5h
63
Checksum for byte 0–62
9700...
00h
9700...
00h
64–71
Manufacturer’s JEDEC ID code per JEP–106E
97h
97h
†
72
73–90
91
Manufacturing location
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
†
Manufacturer’s part number
†
Die revision code
†
PCB revision code
92
†
93–94
95–98
Manufacturing date
†
Assembly serial number
†
99–125 Manufacturer-specific data
†
126–127 Vendor-specific data
‡
128–166 System-integrator-specific data
167–255 Open
†
‡
TBD indicates values are determined at manufacturing time and are module-dependent.
These TBD values are determined and programmed by the customer (optional).
16
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TM8TT64JPN, TM16TT64JPN
TM8TT72JPN, TM16TT72JPN
SYNCHRONOUS DYNAMIC RAM MODULES
SMMS700A – APRIL 1998 – REVISED AUGUST 1998
serial presence detect (continued)
Table 3. Serial-Presence-Detect Data for the TM8TT72JPN
TM8TT72JPN-8
TM8TT72JPN-8A
BYTE
NO.
DESCRIPTION OF FUNCTION
ITEM
DATA
ITEM
DATA
Defines number of bytes written into serial memory during module
manufacturing
0
128 bytes
80h
128 bytes
80h
1
2
Total number of bytes of SPD memory device
Fundamental memory type (FPM, EDO, SDRAM, . . .)
Number of row addresses on this assembly
Number of column addresses on this assembly
Number of module rows on this assembly
256 bytes
SDRAM
12
08h
04h
0Ch
09h
01h
48h
00h
01h
80h
60h
02h
256 bytes
SDRAM
12
08h
04h
0Ch
09h
01h
48h
00h
01h
80h
60h
02h
3
4
9
9
5
1 bank
72 bits
1 bank
72 bits
6
Data width of this assembly
7
Data width continuation
8
Voltage interface standard of this assembly
SDRAM cycle time at maximum supported CAS latency (CL), CL = X
SDRAM access from clock at CL = X
LVTTL
LVTTL
9
t
t
= 8 ns
= 6 ns
t
t
= 8 ns
= 6 ns
CK
CK
10
11
AC
AC
DIMM configuration type (non-parity, parity, error correcting code [ECC])
ECC
15.6 µs/
ECC
15.6 µs/
12
Refresh rate/type
80h
80h
self-refresh
self-refresh
13
14
15
16
17
18
19
20
SDRAM width, primary DRAM
Error-checking SDRAM data width
Minimum clock delay, back-to-back random column addresses
Burst lengths supported
x8
x8
08h
08h
01h
0Fh
04h
06h
01h
01h
x8
x8
08h
08h
01h
0Fh
04h
06h
01h
01h
1 CK cycle
1, 2, 4, 8
4 banks
2, 3
1 CK cycle
1, 2, 4, 8
4 banks
2, 3
Number of banks on each SDRAM device
CAS latencies supported
CS latency
0
0
Write latency
0
0
Non-buffered/
Non-registered
Non-buffered/
Non-registered
21
SDRAM module attributes
00h
00h
V tolerance =
DD
(+10%),
V tolerance =
DD
(+10%),
Burst read/write,
precharge all,
Burst read/write,
precharge all,
22
SDRAM device attributes: general
0Eh
0Eh
auto precharge
auto precharge
23
24
25
26
Minimum clock cycle time at CL = X – 1
t
= 10 ns
= 6 ns
A0h
60h
00h
00h
t
= 15 ns
= 7.5 ns
N/A
F0h
75h
00h
00h
CK
CK
Maximum data-access time from clock at
CL = X – 1
t
t
AC
AC
Minimum clock cycle time at CL = X – 2
N/A
Maximum data-access time from clock at
CL = X – 2
N/A
N/A
27
28
29
30
31
32
Minimum row precharge time
t
= 20 ns
14h
10h
14h
30h
10h
20h
t
= 20 ns
14h
10h
14h
30h
10h
20h
RP
RP
Minimum row-active to row-active delay
Minimum RAS-to-CAS delay
t
t
= 16 ns
= 20 ns
= 48 ns
t
= 16 ns
= 20 ns
= 48 ns
RRD
RCD
RRD
t
RCD
Minimum RAS pulse width
t
t
RAS
RAS
Density of each bank on module
Command and address signal input setup time
64M Bytes
tIS = 2 ns
64M Bytes
tIS = 2 ns
17
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TM8TT64JPN, TM16TT64JPN
TM8TT72JPN, TM16TT72JPN
SYNCHRONOUS DYNAMIC RAM MODULES
SMMS700A – APRIL 1998 – REVISED AUGUST 1998
serial presence detect (continued)
Table 3. Serial-Presence-Detect Data for the TM8TT72JPN (Continued)
TM8TT72JPN-8
TM8TT72JPN-8A
BYTE
NO.
DESCRIPTION OF FUNCTION
Command and address signal input hold time
ITEM
DATA
ITEM
DATA
33
34
tIH = 1 ns
tIS = 2 ns
tIH = 1 ns
10h
20h
10h
tIH = 1 ns
tIS = 2 ns
tIH = 1 ns
10h
20h
10h
Data signal input setup time
Data signal input hold time
Superset features (may be used in the future)
SPD revision
35
36–61
62
Rev. 1.2
113
12h
71h
Rev. 1.2
214
12h
D6h
63
Checksum for byte 0–62
9700...
00h
9700...
00h
64–71
Manufacturer’s JEDEC ID code per JEP–106E
97h
97h
†
72
73–90
91
Manufacturing location
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
†
Manufacturer’s part number
†
Die revision code
†
PCB revision code
92
†
93–94
95–98
Manufacturing date
†
Assembly serial number
†
99–125 Manufacturer-specific data
†
126–127 Vendor-specific data
‡
128–166 System-integrator-specific data
167–255 Open
†
‡
TBD indicates values are determined at manufacturing time and are module-dependent.
These TBD values are determined and programmed by the customer (optional).
18
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TM8TT64JPN, TM16TT64JPN
TM8TT72JPN, TM16TT72JPN
SYNCHRONOUS DYNAMIC RAM MODULES
SMMS700A – APRIL 1998 – REVISED AUGUST 1998
serial presence detect (continued)
Table 4. Serial Presence-Detect Data for the TM16TT72JPN
TM16TT72JPN-8
TM16TT72JPN-8A
BYTE
NO.
DESCRIPTION OF FUNCTION
ITEM
DATA
ITEM
DATA
Defines number of bytes written into serial memory during module
manufacturing
0
128 bytes
80h
128 bytes
80h
1
2
Total number of bytes of SPD memory device
Fundamental memory type (FPM, EDO, SDRAM, . . .)
Number of row addresses on this assembly
Number of column addresses on this assembly
Number of module rows on this assembly
256 bytes
SDRAM
12
08h
04h
0Ch
09h
02h
48h
00h
01h
80h
60h
02h
256 bytes
SDRAM
12
08h
04h
0Ch
09h
02h
48h
00h
01h
80h
60h
02h
3
4
9
9
5
2 banks
72 bits
2 banks
72 bits
6
Data width of this assembly
7
Data width continuation
8
Voltage interface standard of this assembly
SDRAM cycle time at maximum supported CAS latency (CL), CL = X
SDRAM access from clock at CL = X
LVTTL
LVTTL
9
t
t
= 8 ns
= 6 ns
t
t
= 8 ns
= 6 ns
CK
CK
10
11
AC
AC
DIMM configuration type (non-parity, parity, error correcting code [ECC])
ECC
15.6 µs/
ECC
15.6 µs/
12
Refresh rate/type
80h
80h
self-refresh
self-refresh
13
14
15
16
17
18
19
20
SDRAM width, primary DRAM
Error-checking SDRAM data width
Minimum clock delay, back-to-back random column addresses
Burst lengths supported
x8
x8
08h
08h
01h
0Fh
04h
06h
01h
01h
x8
x8
08h
08h
01h
0Fh
04h
06h
01h
01h
1 CK cycle
1, 2, 4, 8
4 banks
2, 3
1 CK cycle
1, 2, 4, 8
4 banks
2, 3
Number of banks on each SDRAM device
CAS latencies supported
CS latency
0
0
Write latency
0
0
Non-buffered/
Non-registered
Non-buffered/
Non-registered
21
SDRAM module attributes
00h
00h
V tolerance =
DD
(+10%).
V tolerance =
DD
(+10%).
Burst read/write,
precharge all,
Burst read/write,
precharge all,
22
SDRAM device attributes: general
0Eh
0Eh
auto precharge
auto precharge
Minimum clock cycle time at
CL = X – 1
23
24
25
t
= 10 ns
= 6 ns
A0h
60h
00h
t
= 15 ns
= 7.5 ns
N/A
F0h
75h
00h
CK
CK
Maximum data-access time from clock at CL = X – 1
t
t
AC
AC
Minimum clock cycle time at
CL = X – 2
N/A
26
27
28
29
30
31
Maximum data-access time from clock at CL = X – 2
Minimum row precharge time
N/A
00h
14h
10h
14h
30h
10h
N/A
00h
14h
10h
14h
30h
10h
t
= 20 ns
t
= 20 ns
RP
RP
Minimum row-active to row-active delay
Minimum RAS-to-CAS delay
t
t
= 16 ns
= 20 ns
= 48 ns
t
= 16 ns
= 20 ns
= 48 ns
RRD
RCD
RRD
t
RCD
Minimum RAS pulse width
t
t
RAS
RAS
Density of each bank on module
64M Bytes
64M Bytes
19
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TM8TT64JPN, TM16TT64JPN
TM8TT72JPN, TM16TT72JPN
SYNCHRONOUS DYNAMIC RAM MODULES
SMMS700A – APRIL 1998 – REVISED AUGUST 1998
serial presence detect (continued)
Table 4. Serial-Presence-Detect Data for the TM16TT72JPN (Continued)
TM16TT72JPN-8
TM16TT72JPN-8A
BYTE
NO.
DESCRIPTION OF FUNCTION
ITEM
DATA
ITEM
DATA
32
33
Command and address signal input setup time
Command and address signal input hold time
Data signal input setup time
tIS = 2 ns
tIH = 1 ns
tIS = 2 ns
tIH = 1 ns
20h
10h
20h
10h
tIS = 2 ns
tIH = 1 ns
tIS = 2 ns
tIH = 1 ns
20h
10h
20h
10h
34
35
Data signal input hold time
36–61
62
Superset features (may be used in the future)
SPD revision
Rev. 1.2
114
12h
72h
Rev. 1.2
215
12h
D7h
63
Checksum for byte 0–62
9700...
00h
9700...
00h
64–71
Manufacturer’s JEDEC ID code per JEP–106E
97h
97h
†
72
73–90
91
Manufacturing location
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
†
Manufacturer’s part number
†
Die revision code
†
PCB revision code
92
†
93–94
95–98
Manufacturing date
Assembly serial number
†
†
99–125 Manufacturer-specific data
†
126–127 Vendor-specific data
‡
128–166 System-integrator-specific data
167–255 Open
†
‡
TBD indicates values are determined at manufacturing time and are module-dependent.
These TBD values are determined and programmed by the customer (optional).
20
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TM8TT64JPN, TM16TT64JPN
TM8TT72JPN, TM16TT72JPN
SYNCHRONOUS DYNAMIC RAM MODULES
SMMS700A – APRIL 1998 – REVISED AUGUST 1998
device symbolization (TM8TT64JPN)
TM8TT64JPN
Unbuffered Key Position
3.3-V Voltage Key Position
YY = Year Code
MM = Month Code
T = Assembly Site Code
-SS = Speed Code
NOTE A: Location of symbolization may vary.
21
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TM8TT64JPN, TM16TT64JPN
TM8TT72JPN, TM16TT72JPN
SYNCHRONOUS DYNAMIC RAM MODULES
SMMS700A – APRIL 1998 – REVISED AUGUST 1998
BUV (R-PDIM-N168)
DUAL-IN-LINE MEMORY MODULE
5.255 (133,48)
(Note D)
5.245 (133,22)
Notch 0.250 (6,35) x 0.089 (2,26) Deep
2 Places
0.054 (1,37)
Notch 0.157 (4,00) x 0.122 (3,10) Deep
2 Places
Notch 0.079 (2,00) x 0.122 (3,10) Deep
2 Places
0.046 (1,17)
2 Places
0.050 (1,27)
0.039 (1,00) TYP
0.125 (3,18)
0.014 (0,35) MAX
0.125 (3,18)
0.118 (3,00) TYP
0.700 (17,78) TYP
0.118 (3,00) DIA (2 Places)
1.255 (31,88)
0.875 (22,23) 2 Places
1.245 (31,62)
0.106 (2,70) MAX
0.157 (4,00) MAX
(For Double Sided DIMM Only)
4088192/A 01/98
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MO-161
D. Dimension includes depanelization variations; applies between notch and tab edge.
E. Outline may vary above notches to allow router/panelization irregularities.
22
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
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