TM248CBK32U-70L [TI]
2MX32 FAST PAGE DRAM MODULE, 70ns, SMA72, SIMM-72;
| 型号： | TM248CBK32U-70L |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 2MX32 FAST PAGE DRAM MODULE, 70ns, SMA72, SIMM-72 动态存储器 内存集成电路 |
| 文件： | 总11页 (文件大小：149K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TM124BBK32, TM124BBK32S 1048576 BY 32-BIT
TM248CBK32, TM248CBK32S 2097152 BY 32-BIT
DYNAMIC RAM MODULE
SMMS132D – JANUARY 1991 – REVISED JUNE 1995
Organization
Performance Ranges:
TM124BBK32 . . . 1 048 576 × 32
TM248CBK32 . . . 2 097 152 × 32
ACCESS
TIME
ACCESS
TIME
READ
OR
t
t
WRITE
CYCLE
(MIN)
RAC
CAC
Single 5-V Power Supply (±10 % Tolerance)
72-pin Single In-Line Memory Module
(SIMM) for Use With Sockets
(MAX)
60 ns
70 ns
80 ns
60 ns
70 ns
80 ns
(MAX)
15 ns
18 ns
20 ns
15 ns
18 ns
20 ns
TM124BBK32-60
TM124BBK32-70
TM124BBK32-80
TM248CBK32-60
TM248CBK32-70
TM248CBK32-80
110 ns
130 ns
150 ns
110 ns
130 ns
150 ns
TM124BBK32-Utilizes Eight 4-Megabit
DRAMs in Plastic Small-Outline J-Lead
(SOJ) Packages
TM248CBK32-Utilizes Sixteen 4-Megabit
DRAMs in Plastic Small-Outline J-Lead
(SOJ) Packages
Low Power Dissipation
Distributed Refresh Period
16 ms (1024 Cycles)
Operating Free-Air-Temperature Range
0°C to 70°C
All Inputs, Outputs, Clocks Fully TTL
Compatible
†
Gold-Tabbed Versions Available:
– TM124BBK32
– TM248CBK32
3-State Output
Tin-Lead (Solder) Tabbed Versions
Available:
Common CAS Control for Eight Common
Data-In and Data-Out Lines, In Four Blocks
– TM124BBK32S
– TM248CBK32S
Presence Detect
description
TM124BBK32
The TM124BBK32 is a dynamic random-access memory (DRAM) organized as four times 1048576 × 8 in a
72-pin leadless single in-line memory module (SIMM). The SIMM is composed of eight TMS44400, 1048576
× 4-bit DRAMs, each in 20/26-lead plastic SOJ packages, mounted on a substrate together with decoupling
capacitors. Each TMS44400 is described in the TMS44400 data sheet.
The TM124BBK32 is available in the single-sided BK leadless module for use with sockets.
The TM124BBK32 features RAS access times of 60 ns, 70 ns and 80 ns. This device is rated for operation from
0°C to 70°C
TM248CBK32
The TM248CBK32 is a dynamic random-access memory organized as four times 2097152 × 8 in a 72-pin
leadless SIMM. The SIMM is composed of sixteen TMS44400, 1048576 × 4-bit dynamic RAMs, each in
20/26-lead plastic SOJ packages SOJs, mounted on a substrate together with decoupling capacitors. Each
TMS44400 is described in the TMS44400 data sheet.
The TM248CBK32 is available in the double-sided BK leadless module for use with sockets.
The TM248CBK32 features RAS access times of 60 ns, 70 ns and 80 ns. This device is rated for operation from
0°C to 70°C
operation
TM124BBK32
The TM124BBK32 operates as eight TMS44400DJs connected as shown in the functional block diagram. Refer
to the TMS44400 data sheet for details of operation. The common I/O feature of the TM124BBK32 dictates the
use of early write cycles to prevent contention on D and Q.
†
Part numbers in this data sheet are for the gold-tabbed version; the information applies to both gold-tabbed and solder-tabbed versions.
Copyright 1995, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TM124BBK32, TM124BBK32S 1048576 BY 32-BIT
TM248CBK32, TM248CBK32S 2097152 BY 32-BIT
DYNAMIC RAM MODULE
SMMS132D – JANUARY 1991 – REVISED JUNE 1995
TM248CBK32
The TM248CBK32 operates as sixteen TMS44400DJs connected as shown in the functional block diagram.
Refer to the TMS44400 data sheet for details of operation. The common I/O feature of the TM248CBK32
dictates the use of early write cycles to prevent contention on D and Q.
refresh
Refresh period is extended to 16 ms and, during this period, each of the 1024 rows must be strobed with RAS
inordertoretaindata. A0-A9addresslinesmustberefreshedevery16msasrequiredbytheTMS44400DRAM.
CAS can remain high during the refresh sequence to conserve power.
single in-line memory module and components
PC substrate: 1,27 ± 0,1 mm (0.05 inch) nominal thickness; 0.005 inch/inch maximum warpage
Bypass capacitors: Multilayer ceramic
Contact area for TM124BBK32 AND TM248CBK32: Nickel plate and gold plate over copper.
Contact area for TM124BBK32S AND TM248CBK32S: Nickel plate and tin-lead over copper.
2
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TM124BBK32, TM124BBK32S 1048576 BY 32-BIT
TM248CBK32, TM248CBK32S 2097152 BY 32-BIT
DYNAMIC RAM MODULE
SMMS132D – JANUARY 1991 – REVISED JUNE 1995
†
†
TM124BBK32
TM248CBK32
BK SINGLE IN-LINE MEMORY MODULE
(TOP VIEW)
(SIDE VIEW)
(SIDE VIEW)
V
1
2
3
4
5
6
7
8
SS
DQ0
DQ16
DQ1
DQ17
DQ2
DQ18
DQ3
DQ19
9
V
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
CC
NC
A0
A1
A2
A3
A4
A5
A6
NC
DQ4
DQ20
DQ5
DQ21
DQ6
DQ22
DQ7
DQ23
A7
NC
V
CC
A8
A9
RAS3
RAS2
NC
NC
NC
NC
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
V
PIN NOMENCLATURE
Address Inputs
SS
CAS0
CAS2
CAS3
CAS1
RAS0
RAS1
NC
W
NC
DQ8
DQ24
DQ9
DQ25
DQ10
DQ26
DQ11
DQ27
DQ12
DQ28
A0–A9
CAS0–CAS3
DQ0–DQ31
NC
Column-Address Strobe
Data In/Data Out
No Connection
Presence Detects
Row-Address Strobe
5-V Supply
PD1– PD4
RAS0–RAS3
V
V
CC
Ground
SS
W
Write Enable
V
CC
PRESENCE DETECT
DQ29
DQ13
DQ30
DQ14
DQ31
DQ15
NC
SIGNAL
(PIN)
PD1
(67)
PD2
(68)
PD3
(69)
PD4
(70)
80 ns
70 ns
60 ns
80 ns
70 ns
60 ns
V
V
V
V
V
V
NC
V
SS
SS
SS
SS
SS
SS
SS
TM124BBK32
V
SS
NC
NC
PD1
PD2
PD3
PD4
NC
NC
NC
NC
NC
NC
NC
NC
V
SS
NC
NC
V
SS
TM248CBK32
V
SS
NC
NC
†
The packages shown here are not drawn to scale.
3
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
functional block diagram (for TM124BBK32 and TM248CBK32, Side 1)
10
A0–A9
RAS0
W
RAS2
CAS2
CAS3
CAS0
CAS1
1M × 4
A0–A9
RAS
W
CAS
OE
1M × 4
A0–A9
RAS
W
CAS
OE
1M × 4
A0–A9
RAS
W
CAS
OE
1M × 4
A0–A9
RAS
W
CAS
OE
10
10
10
10
DQ1–
DQ4
DQ1–
DQ4
DQ1–
DQ4
DQ1–
DQ4
DQ0–
DQ3
DQ8–
DQ11
DQ16–
DQ19
DQ24–
DQ27
1M × 4
A0–A9
RAS
W
CAS
OE
1M × 4
A0–A9
RAS
W
CAS
OE
10
10
10
10
1M × 4
A0–A9
RAS
W
CAS
OE
1M × 4
A0–A9
RAS
W
CAS
OE
DQ1–
DQ4
DQ1–
DQ4
DQ1–
DQ4
DQ1–
DQ4
DQ4–
DQ7
DQ12–
DQ15
DQ20–
DQ23
DQ28–
DQ31
functional block diagram (for TM248CBK32, Side 2)
10
A0–A9
RAS1
W
RAS3
CAS2
CAS3
CAS0
CAS1
1M × 4
A0–A9
RAS
W
CAS
OE
1M × 4
A0–A9
RAS
W
CAS
OE
1M × 4
A0–A9
RAS
W
CAS
OE
1M × 4
A0–A9
RAS
W
CAS
OE
10
10
10
10
DQ1–
DQ4
DQ1–
DQ4
DQ1–
DQ4
DQ1–
DQ4
DQ0–
DQ3
DQ8–
DQ11
DQ16–
DQ19
DQ24–
DQ27
1M × 4
A0–A9
RAS
W
CAS
OE
1M × 4
A0–A9
RAS
W
CAS
OE
10
10
10
10
1M × 4
A0–A9
RAS
W
CAS
OE
1M × 4
A0–A9
RAS
W
CAS
OE
DQ1–
DQ4
DQ1–
DQ4
DQ1–
DQ4
DQ1–
DQ4
DQ4–
DQ7
DQ12–
DQ15
DQ20–
DQ23
DQ28–
DQ31
TM124BBK32, TM124BBK32S 1048576 BY 32-BIT
TM248CBK32, TM248CBK32S 2097152 BY 32-BIT
DYNAMIC RAM MODULE
SMMS132D – JANUARY 1991 – REVISED JUNE 1995
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Voltage range on any pin (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 1 V to 7 V
Voltage range on V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 1 V to 7 V
CC
Short-circuit output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 W
Operating free-air temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
A
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 125°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to V
.
SS
recommended operating conditions
MIN NOM
MAX
5.5
6.5
0.8
70
UNIT
V
V
V
V
Supply voltage
4.5
2.4
– 1
0
5
CC
IH
IL
High-level input voltage
V
Low-level input voltage (see Note 2)
Operating free-air temperature
V
T
A
°C
NOTE 2: The algebraic convention, where the more negative (less positive) limit is designated as minimum, is used for logic-voltage levels only.
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
’124BBK32-60 ’124BBK32-70 ’124BBK32-80
PARAMETER
TEST CONDITIONS
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
V
V
High-level output voltage
Low-level output voltage
I
I
= – 5 mA
2.4
2.4
2.4
V
V
OH
OH
= 4.2 mA
= 5 V,
0.4
0.4
0.4
OL
OL
V
V = 0 V to 6.5 V,
I
CC
All other pins = 0 V to V
I
I
I
Input current (leakage)
Output current (leakage)
±10
±10
±10
µA
µA
I
CC
V
= 5.5 V,
V
= 0 V to V ,
CC
CC
CAS high
O
±10
±10
±10
O
Read- or write-cycle current
(see Note 3)
V
= 5.5 V,
Minimum cycle
840
720
640
mA
CC1
CC
After 1 memory cycle,
RAS and CAS high,
16
8
16
8
16
8
V
IH
=2.4 V (TTL)
I
Standby current
mA
CC2
After 1 memory cycle,
RAS and CAS high,
V
IH
= V
– 0.2 V (CMOS)
CC
V
= 5.5 V,
Minimum cycle,
CC
Average refresh current
(RAS only or CBR)
(see Note 3)
RAS cycling,
CAS high (RAS only),
RAS low after CAS low (CBR)
I
I
840
720
720
640
640
560
mA
mA
CC3
Average page current
(see Note 4)
V
= 5.5 V,
t
= minimum,
CC
RAS low,
PC
CAS cycling
CC4
NOTES: 3. Measured with a maximum of one address change while RAS = V
IL
4. Measured with a maximum of one address change while CAS = V
IH
6
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TM124BBK32, TM124BBK32S 1048576 BY 32-BIT
TM248CBK32, TM248CBK32S 2097152 BY 32-BIT
DYNAMIC RAM MODULE
SMMS132D – JANUARY 1991 – REVISED JUNE 1995
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
’248CBK32-60 ’248CBK32-70 ’248CBK32-80
PARAMETER
TEST CONDITIONS
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
V
V
High-level output voltage
Low-level output voltage
I
I
= – 5 mA
2.4
2.4
2.4
V
V
OH
OH
= 4.2 mA
= 5 V,
0.4
0.4
0.4
OL
OL
V
V = 0 V to 6.5 V,
I
CC
All other pins = 0 V to V
I
I
I
Input current (leakage)
Output current (leakage)
±20
±20
±20
µA
µA
I
CC
= 0 V to V
V
= 5.5 V,
V
,
CC
CC
CAS high
O
±20
±20
±20
O
Read- or write-cycle current
(see Note 3)
V
= 5.5 V,
Minimum cycle
856
736
656
mA
CC1
CC
After 1 memory cycle,
RAS and CAS high,
32
16
32
16
32
16
V
IH
=2.4 V (TTL)
I
Standby current
mA
CC2
After 1 memory cycle,
RAS and CAS high,
V
= V
– 0.2 V (CMOS)
IH
CC
= 5.5 V,
V
CC
Minimum cycle,
Average refresh current
(RAS only or CBR)
(see Note 3)
RAS cycling,
I
I
1680
736
1440
656
1280
576
mA
mA
CC3
CAS high (RAS only),
RAS low after CAS low (CBR)
V
= 5.5 V,
t
= minimum,
Average page current
(see Note 4)
CC
RAS low,
PC
CAS cycling
CC4
NOTES: 3. Measured with a maximum of one address change while RAS = V
4. Measured with a maximum of one address change while CAS = V
IL
IH
capacitance over recommended ranges of supply voltage and operating free-air temperature
f = 1 MHz (see Note 5)
’124BBK32
MIN MAX
’248CBK32
MIN MAX
UNIT
C
C
C
C
C
Input capacitance, address inputs
Input capacitance, RAS
40
28
14
56
7
80
28
pF
pF
pF
pF
pF
i(A)
i(R)
Input capacitance, CAS
28
i(C)
Input capacitance, W
112
14
i(W)
o(DQ)
Output capacitance on DQ pins
NOTE 5:
V
CC
= 5 V ± 0.5 V and the bias on pins under test is 0 V.
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature
’124BBK32-60 ’124BBK32-70 ’124BBK32-80
’248CBK32-60 ’248CBK32-70 ’248CBK32-80
PARAMETER
UNIT
MIN
MAX
30
MIN
MAX
35
MIN
MAX
40
t
t
t
t
t
t
Access time from column-address
Access time from CAS low
ns
ns
ns
ns
ns
ns
AA
15
18
20
CAC
CPA
RAC
CLZ
OFF
Access time from column precharge
Access time from RAS low
35
40
45
60
70
80
CAS to output in low Z
0
0
0
0
0
0
Output disable time after CAS high (see Note 6)
15
18
20
NOTE 6:
t
is specified when the output is no longer driven.
OFF
7
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TM124BBK32, TM124BBK32S 1048576 BY 32-BIT
TM248CBK32, TM248CBK32S 2097152 BY 32-BIT
DYNAMIC RAM MODULE
SMMS132D – JANUARY 1991 – REVISED JUNE 1995
timing requirements over recommended range of supply voltage and operating free-air
temperature
’124BBK32-60
’248CBK32-60
’124BBK32-70
’248CBK32-70
’124BBK32-80
’248CBK32-80
UNIT
MIN
110
40
MAX
MIN
130
45
MAX
MIN
150
50
MAX
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Cycle time, random read or write (see Note 7)
Cycle time, page-mode read or write (see Note 8)
Pulse duration, CAS high
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
RC
PC
10
10
10
CP
Pulse duration, CAS low
15
10 000
18
10 000
20
10 000
CAS
RP
Pulse duration, RAS high (precharge)
Pulse duration, page mode, RAS low
Pulse duration, nonpage mode, RAS low
Pulse duration, write
40
50
60
60 100 000
70 100 000
80 100 000
RASP
RAS
WP
60
15
0
10 000
70
15
0
10 000
80
15
0
10 000
Setup time, column address before CAS low
Setup time, row address before RAS low
Setup time, data
ASC
ASR
DS
0
0
0
0
0
0
Setup time, read before CAS low
0
0
0
RCS
WCS
WSR
CWL
RWL
WTS
CAH
RAH
AR
Setup time, W low before CAS low
Setup time, W high (CBR refresh only)
Setup time, W low before CAS high
Setup time, W low before RAS high
Setup time, W low (test mode only)
Hold time, column address after CAS low
Hold time, row address after RAS low
Hold time, column address after RAS low (see Note 9)
Hold time, data after RAS low (see Note 9)
Hold time, data
0
0
0
10
15
15
10
10
10
50
50
10
0
10
18
18
10
15
10
55
55
15
0
10
20
20
10
15
10
60
60
15
0
DHR
DH
Hold time, read after CAS high (see Note 10)
Hold time, read after RAS high (see Note 10)
Hold time, write after CAS low
RCH
RRH
WCH
WHR
WCR
WTH
CSH
CRP
RCD
CHR
CSR
RAD
RAL
0
0
0
15
10
50
10
60
0
15
10
55
10
70
0
15
10
60
10
80
0
Hold time, W high (CBR refresh only)
Hold time, write after RAS low
Hold time, W low (test mode only)
Delay time, RAS low to CAS high
Delay time, CAS high to RAS low
Delay time, RAS low to CAS low (see Note 11)
Delay time, RAS low to CAS high (CBR refresh only)
Delay time, CAS low to RAS low (CBR refresh only)
Delay time, RAS low to column address (see Note 11)
Delay time, column address to RAS high
20
15
10
15
30
45
30
20
15
10
15
35
52
35
20
20
10
15
40
60
40
NOTES: 7. All cycle times assume t = 5 ns.
T
8. To assure t min, t
PL
should be ≥ 5 ns.
ASC
9. The minimum value is measured when t
is set to t
RCD
min as a reference.
RCD
must be satisfied for a read cycle.
10. Either t
or t
RRH
RCH
11. Maximum value specified only to assure access time.
8
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TM124BBK32, TM124BBK32S 1048576 BY 32-BIT
TM248CBK32, TM248CBK32S 2097152 BY 32-BIT
DYNAMIC RAM MODULE
SMMS132D – JANUARY 1991 – REVISED JUNE 1995
timing requirements over recommended range of supply voltage and operating free-air
temperature (concluded)
’124BBK32-60 ’124BBK32-70 ’124BBK32-80
’248CBK32-60 ’248CBK32-70 ’248CBK32-80
UNIT
MIN
30
0
MAX
MIN
35
0
MAX
MIN
40
0
MAX
t
t
t
t
t
t
t
t
Delay time, column address to CAS high
Delay time, RAS high to CAS low (CBR refresh only)
Delay time, CAS low to RAS high
Access time from address (test mode)
Access time from RAS (test mode)
Access time from column precharge (test mode)
Refresh time interval
ns
ns
ns
ns
ns
ns
ms
ns
CAL
RPC
RSH
TAA
TRAC
TCPA
REF
T
15
35
65
40
18
40
75
45
20
45
85
50
16
50
16
50
16
50
Transition time
2
2
2
device symbolization (TM124BBK32 illustrated)
TM124BBK36B
–SS
YYMMT
YY = Year Code
MM = Month Code
T = Assembly Site Code
–SS = Speed Code
NOTE: Location of symbolization may vary.
9
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TM124BBK32, TM124BBK32S 1048576 BY 32-BIT
TM248CBK32, TM248CBK32S 2097152 BY 32-BIT
DYNAMIC RAM MODULE
SMMS132D – JANUARY 1991 – REVISED JUNE 1995
10
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