TM248NBK36T-80 [TI]
2MX36 FAST PAGE DRAM MODULE, 80ns, SMA72, SIMM-72;
| 型号： | TM248NBK36T-80 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 2MX36 FAST PAGE DRAM MODULE, 80ns, SMA72, SIMM-72 动态存储器 |
| 文件： | 总12页 (文件大小：168K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TM124MBK36E, TM124MBK36T 1048576 BY 36-BIT DYNAMIC RAM MODULE
TM248NBK36E, TM248NBK36T 2097152 BY 36-BIT DYNAMIC RAM MODULE
SMMS139 – MARCH 1994
•
Organization
TM124MBK36E . . . 1 048 576 × 36
TM248NBK36E . . . 2 097 152 × 36
•
Enhanced Page-Mode Operation With
CAS-Before-RAS, RAS-Only, and Hidden
Refresh
•
•
Single 5-V Power Supply (±10% Tolerance)
•
•
Presence Detect
72-Pin Leadless Single-In-Line Memory
Module (SIMM)
Performance Ranges:
ACCESS ACCESS ACCESS READ
TIME
TIME
TIME
OR
•
TM124MBK36E – Utilizes Eight 4-Megabit
Dynamic RAMs in Plastic Small-Outline
J-Lead (SOJ) Packages and Two 2-Megabit
Dual-CAS Dynamic RAMs in Plastic
t
t
t
WRITE
CYCLE
(MIN)
RAC
AA
CAC
(MAX)
’124MBK36E-60 60 ns
’124MBK36E-70 70 ns
’124MBK36E-80 80 ns
’248NBK36E-60 60 ns
’248NBK36E-70 70 ns
’248NBK36E-80 80 ns
(MAX)
30 ns
35 ns
40 ns
30 ns
35 ns
40 ns
(MAX)
15 ns
18 ns
20 ns
15 ns
18 ns
20 ns
110 ns
130 ns
150 ns
110 ns
130 ns
150 ns
Small-Outline J-Lead (SOJ) Packages
•
TM248NBK36E – Utilizes Sixteen 4-Megabit
Dynamic RAMs in Plastic Small-Outline
J-Lead (SOJ) Packages and Four 2-Megabit
Dual-CAS Dynamic RAMs in Plastic
•
•
Low Power Dissipation
Small-Outline J-Lead (SOJ) Packages
Operating Free-Air Temperature Range:
•
•
Long Refresh Period . . . 16 ms
(1024 Cycles)
0°C to 70°C
†
•
•
Gold-Tabbed Versions Available:
– TM124MBK36E
– TM248NBK36E
All Inputs, Outputs, Clocks Fully TTL
Compatible
•
•
3-State Output
Tin-Lead (Solder) Tabbed Versions
Available:
– TM124MBK36T
Common CAS Control for Nine Common
Data-In and Data-Out Lines in Four Blocks
– TM248NBK36T
description
The TM124MBK36E is a dynamic random-access memory (RAM) organized as four times 1048576 × 9
(bit 9 is generally used for parity) in a 72-pin leadless single-in-line memory module (SIMM). The SIMM is
composed of eight TMS44400DJ, 1 048 576 × 4-bit dynamic RAMs, each in a 20/26-lead plastic small-outline
J-lead (SOJ) package, and two TMS42260DJ, 1 048 576 × 2-bit dual-CAS dynamic RAMs, each in a 24/26-lead
plastic small-outline J-lead (SOJ) package, mounted on a substrate with decoupling capacitors. Each
TMS44400DJ or TMS42260DJ is described in the TMS44400 or TMS42260 data sheet, respectively.
The TM124MBK36E is available in the single-sided BK leadless module for use with sockets. It features RAS
access times of 60 ns, 70 ns, and 80 ns. This device is characterized for operation from 0°C to 70°C.
The TM248NBK36E is a dynamic random-access memory (RAM) organized as four times 2 097 152 × 9 (bit 9
is generally used for parity) in a 72-pin leadless single-in-line memory module (SIMM). The SIMM is composed
of sixteen TMS44400DJ, 1 048 576 × 4-bit dynamic RAMs, each in a 20/26-lead plastic small-outline J-lead
(SOJ)package, andfourTMS42260DJ, 1 048 576× 2-bitdual-CASdynamicRAMs, eachina24/26-leadplastic
small-outline J-lead (SOJ) package, mounted on a substrate with decoupling capacitors. Each TMS44400DJ
or TMS42260DJ is described in the TMS44400 or TMS42260 data sheet, respectively.
The TM248NBK36E is available in the double-sided BK leadless module for use with sockets. It features RAS
access times of 60 ns, 70 ns, and 80 ns. This device is rated for operation from 0°C to 70°C.
†
Part numbers in this data sheet are for the gold-tabbed version; the information applies to both gold-tabbed and solder-tabbed versions.
Copyright 1994, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TM124MBK36E, TM124MBK36T 1048576 BY 36-BIT DYNAMIC RAM MODULE
TM248NBK36E, TM248NBK36T 2097152 BY 36-BIT DYNAMIC RAM MODULE
SMMS139 – MARCH 1994
operation
The TM124MBK36E operates as eight TMS44400DJs and two TMS42260DJs connected as shown in the
functional block diagram and Table 1. The common I/O feature dictates the use of early write cycles to prevent
contention on D and Q.
The TM248NBK36E operates as sixteen TMS44400DJs and four TMS42260DJs connected as shown in the
functional block diagram and Table 1. The common I/O feature dictates the use of early write cycles to prevent
contention on D and Q.
2
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TM124MBK36E, TM124MBK36T 1048576 BY 36-BIT DYNAMIC RAM MODULE
TM248NBK36E, TM248NBK36T 2097152 BY 36-BIT DYNAMIC RAM MODULE
SMMS139 – MARCH 1994
BK SINGLE-IN-LINE MEMORY MODULE
(TOP VIEW)
TM124MBK36E
(SIDE VIEW)
TM248NBK36E
(SIDE VIEW)
V
1
2
3
4
SS
DQ0
DQ18
DQ1
DQ19
DQ2
5
6
DQ20
DQ3
7
8
DQ21
9
V
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
CC
NC
A0
A1
A2
A3
A4
A5
A6
NC
DQ4
DQ22
DQ5
DQ23
DQ6
DQ24
DQ7
DQ25
A7
NC
V
CC
A8
A9
RAS3
RAS2
DQ26
DQ8
DQ17
DQ35
SS
CAS0
CAS2
CAS3
CAS1
RAS0
RAS1
NC
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
V
PIN NOMENCLATURE
A0–A9
Address Inputs
CAS0–CAS3
Column-Address Strobe
DQ0–DQ35
NC
Data In/Data Out
No Connection
Presence Detects
Row-Address Strobe
5-V Supply
W
NC
DQ9
PD1– PD4
RAS0–RAS3
DQ27
DQ10
DQ28
DQ11
DQ29
DQ12
DQ30
DQ13
DQ31
V
V
CC
Ground
SS
W
Write Enable
PRESENCE DETECT
PD1 PD2
V
CC
SIGNAL
(PIN)
PD3
(69)
PD4
(70)
DQ32
DQ14
DQ33
DQ15
DQ34
DQ16
NC
(67) (68)
80 ns
70 ns
60 ns
80 ns
70 ns
60 ns
V
V
V
V
V
V
NC
V
SS
SS
SS
SS
SS
SS
SS
TM124MBK36E
TM248NBK36E
V
SS
NC
NC
NC
NC
PD1
PD2
PD3
PD4
NC
NC
NC
NC
NC
NC
V
SS
NC
V
SS
NC
NC
NC
V
SS
3
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TM124MBK36E, TM124MBK36T 1048576 BY 36-BIT DYNAMIC RAM MODULE
TM248NBK36E, TM248NBK36T 2097152 BY 36-BIT DYNAMIC RAM MODULE
SMMS139 – MARCH 1994
Table 1. Connection Table
RASx
DATA BLOCK
CASx
†
SIDE 1
SIDE 2
DQ0–DQ7
DQ8
RAS0
RAS0
RAS1
RAS1
CAS0
CAS0
DQ9–DQ16
DQ17
RAS0
RAS0
RAS1
RAS1
CAS1
CAS1
DQ18–DQ25
DQ26
RAS2
RAS2
RAS3
RAS3
CAS2
CAS2
DQ27–DQ34
DQ35
RAS2
RAS2
RAS3
RAS3
CAS3
CAS3
†
Side 2 applies to the TM248NBK36E only.
single in-line memory module and components
PC substrate: 1,27 ± 0,1 mm (0.05 inch) nominal thickness; 0.005 inch/inch maximum warpage
Bypass capacitors: Multilayer ceramic
Contact area for TM124MBK36E and TM248NBK36E: Nickel plate and gold plate over copper
Contact area for TM124MBK36T and TM248NBK36T: Nickel plate and tin/lead over copper
4
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
functional block diagram (TM124MBK36E and TM248NBK36E, side 1)
10
A0–A9
RAS0
W
RAS2
CAS2
CAS3
CAS0
CAS1
1M × 4
A0–A9
RAS
W
CAS
OE
1M × 4
A0–A9
RAS
W
CAS
OE
10 1M × 4
A0–A9
RAS
10
10
10
1M × 4
A0–A9
RAS
W
CAS
OE
10
10
W
CAS
OE
DQ1–
DQ4
4
4
4
4
DQ1–
DQ4
DQ18–
DQ21
DQ1–
DQ4
DQ27–
DQ30
DQ0–
DQ3
DQ9–
DQ12
DQ1–
DQ4
10
10 1M × 4
A0–A9
RAS
10 1M × 4
A0–A9
RAS
1M × 4
1M × 4
A0–A9
RAS
W
CAS
OE
A0–A9
RAS
W
CAS
OE
W
CAS
OE
DQ1–
DQ4
W
CAS
OE
DQ1–
DQ4
4
4
4
4
DQ22–
DQ25
DQ31–
DQ34
DQ4–
DQ7
DQ13–
DQ16
DQ1–
DQ4
DQ1–
DQ4
1M × 2
A0–A9
RAS
W
1M × 2
A0–A9
RAS
10
W
CAS2
CAS1
OE
CAS2
CAS1
OE
DQ1
DQ2
DQ1
DQ2
DQ26
DQ35
DQ8
DQ17
functional block diagram (TM248NBK36E, side 2)
10
A0–A9
RAS1
W
RAS3
CAS2
CAS3
CAS0
CAS1
1M × 4
A0–A9
RAS
W
CAS
OE
1M × 4
A0–A9
RAS
W
CAS
OE
10 1M × 4
A0–A9
RAS
10
10
10
1M × 4
A0–A9
RAS
W
CAS
OE
10
10
W
CAS
OE
DQ1–
DQ4
4
4
4
4
DQ1–
DQ4
DQ18–
DQ21
DQ1–
DQ4
DQ27–
DQ30
DQ0–
DQ3
DQ9–
DQ12
DQ1–
DQ4
10
10 1M × 4
A0–A9
RAS
10 1M × 4
A0–A9
RAS
1M × 4
1M × 4
A0–A9
RAS
W
CAS
OE
A0–A9
RAS
W
CAS
OE
W
CAS
OE
DQ1–
DQ4
W
CAS
OE
DQ1–
DQ4
4
4
4
4
DQ22–
DQ25
DQ31–
DQ34
DQ4–
DQ7
DQ13–
DQ16
DQ1–
DQ4
DQ1–
DQ4
1M × 2
A0–A9
RAS
W
1M × 2
A0–A9
RAS
10
W
CAS2
CAS1
OE
CAS2
CAS1
OE
DQ1
DQ2
DQ1
DQ2
DQ26
DQ35
DQ8
DQ17
TM124MBK36E, TM124MBK36T 1048576 BY 36-BIT DYNAMIC RAM MODULE
TM248NBK36E, TM248NBK36T 2097152 BY 36-BIT DYNAMIC RAM MODULE
SMMS139 – MARCH 1994
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 1 V to 7 V
CC
Input voltage range (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 1 V to 7 V
Short-circuit output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 W
Operating free-air temperature range, T
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 125°C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
A
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to V
.
SS
recommended operating conditions
MIN NOM
MAX
5.5
6.5
0.8
70
UNIT
V
V
V
V
Supply voltage
4.5
2.4
– 1
0
5
CC
IH
IL
High-level input voltage
V
Low-level input voltage (see Note 2)
Operating free-air temperature
V
T
A
°C
NOTE 2: The algebraic convention, where the more negative (less positive) limit is designated as minimum, is used in this data sheet for logic
voltage levels only.
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
’124MBK36E-60 ’124MBK36E-70 ’124MBK36E-80
PARAMETER
TEST CONDITIONS
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
V
V
High-level output voltage
Low-level output voltage
I
I
= – 5 mA
= 4.2 mA
2.4
2.4
2.4
V
V
OH
OH
0.4
0.4
0.4
OL
OL
V
= 5.5 V, V = 0 V to 6.5 V,
I
CC
All other pins = 0 V to V
I
I
I
Input current (leakage)
± 10
± 10
± 10
µA
I
CC
V
V
= 5.5 V,
CC
= 0 V to V ,
CC
Output current (leakage)
± 10
1050
20
± 10
900
20
± 10
800
20
µA
O
O
CAS high
Read- or write-cycle
current (see Note 3)
V
V
= 5.5 V, Minimum cycle
mA
mA
CC1
CC
= 2.4 V (TTL),
IH
After 1 memory cycle,
RAS and CAS high
I
Standby current
CC2
V
IH
= V
– 0.2 V (CMOS),
CC
After 1 memory cycle,
RAS and CAS high
10
10
10
mA
V
= 5.5 V, Minimum cycle,
CC
Average refresh current
(RAS-only or CBR)
(see Note 3)
RAS cycling,
CAS high (RAS-only);
RAS low after CAS low (CBR)
I
I
1050
900
900
800
800
700
mA
mA
CC3
Average page current
(see Note 4)
V
= 5.5 V,
t
= MIN,
CC
RAS low,
PC
CAS cycling
CC4
NOTES: 3. Measured with a maximum of one address change while RAS = V
.
IL
4. Measured with a maximum of one address change while CAS = V
.
IH
7
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TM124MBK36E, TM124MBK36T 1048576 BY 36-BIT DYNAMIC RAM MODULE
TM248NBK36E, TM248NBK36T 2097152 BY 36-BIT DYNAMIC RAM MODULE
SMMS139 – MARCH 1994
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
’248NBK36E-60 ’248NBK36E-70 ’248NBK36E-80
PARAMETER
TEST CONDITIONS
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
High-level output
voltage
V
V
I
I
= – 5 mA
2.4
2.4
2.4
V
V
OH
OH
Low-level output
voltage
= 4.2 mA
0.4
± 20
± 20
1070
0.4
± 20
± 20
920
0.4
± 20
± 20
820
OL
OL
V
= 5.5 V,
V = 0 V to 6.5 V,
I
CC
All other pins = 0 V to V
I
I
I
Input current (leakage)
µA
µA
mA
I
CC
Output current
(leakage)
V
V
= 5.5 V,
CC
= 0 V to V , CAS high
O
O
CC
Read- or write-cycle
current (see Note 3)
V
= 5.5 V,
Minimum cycle
CC1
CC
V
IH
= 2.4 V (TTL),
After 1 memory cycle,
RAS and CAS high
40
20
40
20
40
20
mA
mA
I
Standby current
CC2
V
IH
= V
– 0.2 V (CMOS),
CC
After 1 memory cycle,
RAS and CAS high
V
= 5.5 V,
Minimum cycle,
CC
RAS cycling,
Average refresh
current (RAS-only or
CBR) (see Note 3)
I
I
2100
920
1800
820
1600
720
mA
mA
CC3
CAS high (RAS-only);
RAS low after CAS low (CBR)
Average page current
(see Note 4)
V
= 5.5 V,
t
= MIN,
CC
RAS low,
PC
CAS cycling
CC4
NOTES: 3. Measured with a maximum of one address change while RAS = V
4. Measured with a maximum of one address change while CAS = V
IL
IH
capacitance over recommended ranges of supply voltage and operating free-air temperature,
f = 1 MHz (see Note 5)
’124MBK36E
’248NBK36E
PARAMETER
UNIT
MIN
MAX
50
35
21
70
7
MIN
MAX
100
35
C
C
C
C
C
Input capacitance, address inputs
pF
pF
pF
pF
pF
i(A)
Input capacitance, RAS inputs
Input capacitance, CAS inputs
Input capacitance, write-enable input
Output capacitance on DQ pins
i(R)
42
i(C)
140
14
i(W)
o(DQ)
NOTE 5:
V
CC
= 5 V ± 0.5 V, and the bias on pins under test is 0 V.
8
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TM124MBK36E, TM124MBK36T 1048576 BY 36-BIT DYNAMIC RAM MODULE
TM248NBK36E, TM248NBK36T 2097152 BY 36-BIT DYNAMIC RAM MODULE
SMMS139 – MARCH 1994
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature
’124MBK36E-60 ’124MBK36E-70 ’124MBK36E-80
’248NBK36E-60 ’248NBK36E-70 ’248NBK36E-80
PARAMETER
UNIT
MIN
MAX
15
MIN
MAX
18
MIN
MAX
20
t
t
t
t
t
t
Access time from CAS low
ns
ns
ns
ns
ns
ns
CAC
Access time from column address
Access time from RAS low
30
35
40
AA
60
70
80
RAC
CPA
CLZ
OFF
Access time from column precharge
CAS to output in low-impedance state
Output disable time after CAS high (see Note 6)
35
40
45
0
0
0
0
0
0
15
18
20
NOTE 6:
t
is specified when the output is no longer driven.
OFF
timing requirements over recommended ranges of supply voltage and operating free-air
temperature
’124MBK36E-60 ’124MBK36E-70 ’124MBK36E-80
’248NBK36E-60 ’248NBK36E-70 ’248NBK36E-80
UNIT
MIN
110
155
40
MAX
MIN
130
181
45
MAX
MIN
150
205
50
MAX
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Cycle time, random read or write (see Note 7)
Cycle time, read-write
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
RC
RWC
PC
Cycle time, page-mode read or write (see Note 8)
Pulse duration, page mode, RAS low
Pulse duration, nonpage mode, RAS low
Pulse duration, CAS low
60 100 000
70 100 000
80 100 000
RASP
RAS
CAS
CP
60
15
10
40
15
0
10 000
10 000
70
18
10
50
15
0
10 000
10 000
80
20
10
60
15
0
10 000
10 000
Pulse duration, CAS high
Pulse duration, RAS high (precharge)
Pulse duration, write
RP
WP
Setup time, column address before CAS low
Setup time, row address before RAS low
Setup time, data
ASC
ASR
DS
0
0
0
0
0
0
Setup time, read before CAS low
Setup time, W low before CAS high
Setup time, W low before RAS high
Setup time, W low before CAS low
Setup time, W high (see Note 9)
0
0
0
RCS
CWL
RWL
WCS
WSR
15
15
0
18
18
0
20
20
0
10
10
10
NOTES: 7. All cycles assume t = 5 ns.
T
8. To assure t
min, t
should be greater than or equal to 5 ns.
ASC
PC
9. CAS-before-RAS refresh only
9
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TM124MBK36E, TM124MBK36T 1048576 BY 36-BIT DYNAMIC RAM MODULE
TM248NBK36E, TM248NBK36T 2097152 BY 36-BIT DYNAMIC RAM MODULE
SMMS139 – MARCH 1994
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (continued)
’124MBK36E-60 ’124MBK36E-70 ’124MBK36E-80
’248NBK36E-60 ’248NBK36E-70 ’248NBK36E-80
UNIT
MIN
10
50
10
50
5
MAX
MIN
15
55
15
55
5
MAX
MIN
15
60
15
60
5
MAX
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Hold time, column address after CAS low
Hold time, data after RAS low (see Note 10)
Hold time, data
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
CAH
DHR
DH
Hold time, column address after RAS low (see Note 10)
Hold time, CAS low to CAS high
AR
CLCH
RAH
RCH
RRH
WCH
WCR
WHR
CHR
CRP
CSH
CSR
RAD
RAL
CAL
RCD
RPC
RSH
REF
T
Hold time, row address after RAS low
Hold time, read after CAS high (see Note 11)
Hold time, read after RAS high (see Note 11)
Hold time, write after CAS low
10
0
10
0
10
0
0
0
0
15
50
10
15
0
15
55
10
15
0
15
60
10
20
0
Hold time, write after RAS low (see Note 10)
Hold time, W high (see Note 9)
Delay time, RAS low to CAS high (see Note 9)
Delay time, CAS high to RAS low
Delay time, RAS low to CAS high
60
10
15
30
30
20
0
70
10
15
35
35
20
0
80
10
15
40
40
20
0
Delay time, CAS low to RAS low (see Note 9)
Delay time, RAS low to column address (see Note 12)
Delay time, column address to RAS high
Delay time, column address to CAS high
Delay time, RAS low to CAS low (see Note 12)
Delay time, RAS high to CAS low (see Note 9)
Delay time, CAS low to RAS high
30
45
35
52
40
60
15
18
20
Refresh time interval
16
50
16
50
16
50
Transition time
2
2
2
NOTES: 9. CAS-before-RAS refresh only
10. The minimum value is measured when t
is set to t
RCD
min as a reference.
RCD
11. Either t
or t
must be satisfied for a read cycle.
RRH
12. The maximum value is specified only to assure access time.
RCH
10
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TM124MBK36E, TM124MBK36T 1048576 BY 36-BIT DYNAMIC RAM MODULE
TM248NBK36E, TM248NBK36T 2097152 BY 36-BIT DYNAMIC RAM MODULE
SMMS139 – MARCH 1994
MECHANICAL DATA
BK–72 LEAD SINGLE IN-LINE MEMORY MODULE
BK/R–PSIP–N72
0.054 (1,37)
0.047 (1,19)
4.255 (108,08)
4.245 (107,82)
0.125 (3,18) TYP
0.010 (0, 254) MAX
0.400 (10,16) TYP
0.128 (3,25)
1.005 (25,53)
0.995 (25,27)
0.120 (3,05)
0.050 (1,27) TYP
0.040 (1,02) TYP
0.208 (5,28) MAX
0.360 (9,14) MAX
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
device symbolization (TM124MBK36E illustrated)
TM124MBK36E
-SS
YYMMT
YY = Year Code
MM = Month Code
T = Assembly Site Code
-SS = Speed Code
NOTE: Location of symbolization may vary.
11
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
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