TM2EP72DPN_技术文档

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SMMS684A − AUGUST 1997 − REVISED FEBRUARY 1998

D

Organization

D

JEDEC 168-Pin Dual-In-Line Memory

Module (DIMM) Without Buffer for Use With

Socket

− TM2EP64DxN . . . 2097152 × 64 Bits

− TM2EP72DxN . . . 2097152 × 72 Bits

− TM4EP64DxN . . . 4194304 × 64 Bits

− TM4EP72DxN . . . 4194304 × 72 Bits

Single 3.3-V Power Supply

( 10% Tolerance)

D

High-Speed, Low-Noise LVTTL Interface

Long Refresh Period: 32 ms (2 048 Cycles)

3-State Output

D

Extended-Data-Out (EDO) Operation With

CAS-Before-RAS (CBR), RAS-Only, and

Hidden Refresh

TM2EP64DxN — Uses Eight 16M-Bit

(2M×8-Bit) Dynamic Random Access

Memories (DRAMs) in Thin Small-Outline

Package (TSOP), or Small-Outline J-Lead

Package (SOJ)

D

Serial Presence Detect (SPD) Using

EEPROM

Ambient Air Temperature Range

0°C to 70°C

Gold-Plated Contacts

D

TM2EP72DxN — Uses Nine 16M-Bit

(2M×8-Bit) DRAMs in TSOP, or SOJ

TM4EP64DxN — Uses 16 16M-Bit

(2M×8-Bit) DRAMs in TSOP, or SOJ

TM4EP72DxN — Uses 18 16M-Bit

(2M×8-Bit) DRAMs in TSOP, or SOJ

Performance ranges

ACCESS ACCESS ACCESS

TIME TIME TIME

EDO

CYCLE

t

RAC

CAC

AA

HPC

MAX

50 ns

60 ns

70 ns

MAX

13 ns

15 ns

18 ns

MAX

25 ns

30 ns

35 ns

MIN

’xEPxxDxN-50

’xEPxxDxN-60

’xEPxxDxN-70

20 ns

25 ns

30 ns

description

The TM2EP64DPN is a 16M-byte, 168-pin, dual-in-line memory module (DIMM). The DIMM is composed of

eight TMS427809A, 2097152 byte × 8-bit 2K-refresh EDO DRAMs, each in a 400-mil, 28-pin plastic TSOP

(DGC suffix) mounted on a substrate with decoupling capacitors. See the TMS427809A data sheet (literature

number SMKS887). The TM2EP64DJN is available with an SOJ package (DZ suffix).

The TM2EP72DPN is a 16M-byte, 168-pin DIMM. The DIMM is composed of nine TMS427809A,

2097152 byte × 8-bit 2K-refresh EDO DRAMs, mounted on a substrate with decoupling capacitors. See the

TMS427809A data sheet (literature number SMKS887). The TM2EP72DJN is available with an SOJ package

(DZ suffix).

The TM4EP64DPN is a 32M-byte, 168-pin, dual-in-line memory module (DIMM). The DIMM is composed of

sixteen TMS427809A, 2097152 × 8-bit 2K-refresh EDO DRAMs, mounted on a substrate with decoupling

capacitors. The TM4EP64DJN is available with an SOJ package (DZ suffix).

The TM4EP72DPN is a 32M-byte, 168-pin DIMM. The DIMM is composed of 18 TMS427809A, 2097152 × 8-bit

2K-refresh EDO DRAMs, mounted on a substrate with decoupling capacitors. See the TMS427809A data sheet

(literature number SMKS887). The TM4EP72DJN is available with an SOJ package (DZ suffix).

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

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Copyright  1998, Texas Instruments Incorporated

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ꢞ ꢢ ꢟ ꢞꢗ ꢘꢬ ꢚꢙ ꢝ ꢥꢥ ꢣꢝ ꢛ ꢝ ꢜ ꢢ ꢞ ꢢ ꢛ ꢟ ꢧ

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1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

^{POST OFFICE BOX 1443}• HOUSTON, TEXAS 77251−1443

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SMMS684A − AUGUST 1997 − REVISED FEBRUARY 1998

operation

The TMxEPxxDxN DIMMs operate as displayed in Table 1.

Table 1. TMxEPxxDxN DIMM Device Table

DIMM

DEVICE AND QUANTITY ( )

TM2EP64DxN

TM2EP72DxN

TM4EP64DxN

TM4EP72DxN

TMS427809A (8)

Connected as shown in the functional

block diagram.

TMS427809A (9)

TMS427809A (16)

TMS427809A (18)

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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SMMS684A − AUGUST 1997 − REVISED FEBRUARY 1998

DUAL-IN-LINE MEMORY MODULE

(TOP VIEW)

TM2EP64DPN TM4EP72DPN

(SIDE VIEW) (SIDE VIEW)

PIN NOMENCLATURE

A[0:10]

A[0:9]

DQ[0:63]

CB[0:7]

CAS[0:7]

RAS[0:3]

WE0 and WE2

OE0 and OE2

SA[0:2]

Row Address Inputs

Column Address Inputs

Data In/Data Out

Check-Bit In/Check-Bit Out

Column-Address Strobe

Row-Address Strobe

Write Enable

1

Output Enable

10

11

Serial Presence Detect (SPD)

Device Add Input

SPD Address/Data

SPD Clock

SDA

SCL

NC

No-Connect Pin

V

DD

V

SS

3.3-V Supply

Ground

40

41

84

3

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SMMS684A − AUGUST 1997 − REVISED FEBRUARY 1998

Pin Assignments

NAME

NO.

1

NAME

NO.

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

NAME

NO.

85

NAME

NO.

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

145

146

147

148

149

150

151

152

153

154

155

156

157

158

159

160

161

162

163

164

165

166

167

168

V

SS

V

SS

V

SS

V

SS

2

DQ0

DQ1

DQ2

DQ3

OE2

RAS2

CAS2

CAS3

WE2

86

DQ32

DQ33

DQ34

DQ35

NC

3

87

RAS3

CAS6

CAS7

NC

4

88

5

89

6

V

DD

90

V

DD

7

DQ4

DQ5

DQ6

DQ7

DQ8

V

DD

91

DQ36

DQ37

DQ38

DQ39

DQ40

V

DD

8

NC

92

NC

9

93

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

CB2

CB3

94

CB6

CB7

95

V

SS

V

SS

96

V

SS

V

SS

DQ9

DQ10

DQ11

DQ12

DQ13

DQ16

DQ17

DQ18

DQ19

97

DQ41

DQ42

DQ43

DQ44

DQ45

DQ48

DQ49

DQ50

DQ51

98

99

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

V

DD

V

DD

V

DD

DQ20

NC

V

DD

DQ52

NC

DQ14

DQ15

CB0

DQ46

DQ47

CB4

NC

CB1

V

SS

CB5

V

SS

V

SS

DQ21

DQ22

DQ23

V

SS

DQ53

DQ54

DQ55

NC

V

DD

V

SS

V

DD

NC

V

SS

WE0

DQ24

DQ25

DQ26

DQ27

DQ56

DQ57

DQ58

DQ59

CAS0

CAS1

RAS0

OE0

CAS4

CAS5

RAS1

NC

V

DD

V

DD

V

SS

DQ28

DQ29

DQ30

DQ31

V

SS

DQ60

DQ61

DQ62

DQ63

A0

A2

A1

A3

A5

A7

A9

NC

A4

A6

V

SS

V

SS

A8

NC

A10

NC

SA0

SA1

SA2

V

DD

SDA

SCL

V

DD

NC

V

DD

NC

V

DD

NC

V

DD

4

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SMMS684A − AUGUST 1997 − REVISED FEBRUARY 1998

dual-in-line memory module and components

The dual-in-line memory module and components include:

D

PC substrate: 1,27 " 0,1 mm (0.05 inch) nominal thickness; 0.005 inch/inch maximum warpage

Bypass capacitors: Multilayer ceramic

Contact area: Nickel plate and gold plate over copper

5

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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SMMS684A − AUGUST 1997 − REVISED FEBRUARY 1998

functional block diagram

The following table shows the four DIMM modules and locations (Ux/UBx) that are used.

COMPONENT TABLE

MODULE

LOCATIONS USED

U[0:7]

TM2EP64DxN

TM2EP72DxN

TM4EP64DxN

TM4EP72DxN

U[0:8]

U[0:7], UB[0:7]

U[0:8], UB[0:8]

RAS0

WE0

OE0

RAS1

WE0

OE0

RAS2

RAS3

WE2

OE2

WE2

OE2

CAS0

CAS OE W RAS

CAS4

CAS OE W RAS

DQ[0:7]

U0

DQ[0:7]

UB0

DQ[32:39]

DQ[0:7]

U4

DQ[0:7]

UB4

CAS1

CAS OE W RAS

CAS5

CAS OE W RAS

DQ[8:15]

DQ[0:7]

U1

DQ[0:7]

UB1

DQ[40:47]

DQ[0:7]

U5

DQ[0:7]

UB5

CAS1

CAS OE W RAS

CAS6

CAS OE W RAS

CB[0:7]

DQ[0:7]

U8

DQ[0:7]

UB8

DQ[48:55]

DQ[0:7]

U6

DQ[0:7]

UB6

CAS2

CAS OE W RAS

CAS7

CAS OE W RAS

DQ[16:23]

DQ[0:7]

U2

DQ[0:7]

UB2

DQ[56:63]

DQ[0:7]

U7

DQ[0:7]

UB7

A[0:10]

A[0:10] : U[0:8], UB[0:8]

SPD EEPROM

CAS3

CAS OE W RAS

DQ[24:31]

DQ[0:7]

U3

DQ[0:7]

UB3

SCL

SDA

Legend: SPD = Serial Presence Detect

A0

A1

A2

SA0 SA1 SA2

U[0:8], UB[0:8]

V

DD

Two 0.1 µF

(minimum) per

DRAM

V

SS

U[0:8], UB[0:8]

6

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SMMS684A − AUGUST 1997 − REVISED FEBRUARY 1998

†

absolute maximum ratings over ambient temperature range (unless otherwise noted)

Supply voltage range, V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V

DD

Voltage range on any pin (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 0.5 V to 4.6 V

Short-circuit output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA

Power dissipation: TM2EP64DxN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 W

TM2EP72DxN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 W

TM4EP64DxN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 W

TM4EP72DxN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 W

Ambient temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C

A

stg

Storage temperature range, T

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 55°C to 125°C

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 1: All voltage values are with respect to V

.

SS

recommended operating conditions

MIN NOM

MAX

UNIT

V

Supply voltage

3

3.3

0

3.6

DD

Supply voltage

V

SS

High-level input voltage

High-level input voltage for the SPD device

Low-level input voltage

Ambient temperature

2

V

DD

+ 0.3

V

IH

5.5

0.8

70

V

IH−SPD

IL

−0.3

0

V

T

A

°C

capacitance over recommended ranges of supply voltage and ambient temperature, f = 1 MHz

(see Note 2)

’2EP64DxN

’2EP72DxN

’4EP64DxN

’4EP72DxN

PARAMETER

UNIT

MIN MAX

C

Input capacitance, A0−A10

Input capacitance, OEx

42

30

9

47

37

16

37

9

82

58

16

30

38

16

9

92

72

30

37

16

9

pF

i(A)

i(OE)

i(CAS)

i(RAS)

i(W)

Input capacitance, CASx

Input capacitance, RASx

30

9

Input capacitance, WEx

Output capacitance

o

Input/output capacitance, SDA input

Input capacitance, SA0,SA1,SA2,SCL inputs

9

i/o(SDA)

i(SPD)

7

NOTE 2:

V

DD

= NOM supply voltage 10%, and the bias on pins under test is 0 V.

7

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

^{POST OFFICE BOX 1443}• HOUSTON, TEXAS 77251−1443

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SMMS684A − AUGUST 1997 − REVISED FEBRUARY 1998

electrical characteristics over recommended ranges of supply voltage and ambient temperature

(unless otherwise noted)

TM2EP64DxN

’2EP64DxN-50

’2EP64DxN-60

’2EP64DxN-70

†

PARAMETER

UNIT

TEST CONDITIONS

MIN

MAX

MIN

MAX

MIN

MAX

High-level

output

voltage

I

= − 2 mA

LVTTL

2.4

OH

OL

V

OH

= − 100 µA

= 2 mA

LVCMOS

LVTTL

V

−0.2

V

−0.2

V

−0.2

DD

Low-level

output

voltage

0.4

0.2

0.4

0.2

0.4

0.2

V

OL

= 100 µA

LVCMOS

Input current

(leakage)

V

= 3.6 V,

V = 0 V to 3.9 V,

DD

All others = 0 V to V

I

10

µA

I

DD

Output

current

(leakage)

V

= 3.6 V,

V

O

= 0 V to V ,

DD

CASx high

I

O

Read- or

write-cycle

current

‡§

I

V

= 3.6 V,

Minimum cycle

960

16

800

16

720

16

mA

CC1

DD

= 2 V (LVTTL),

IH

After one memory cycle,

RASx and CASx high

Standby

current

I

V

= V − 0.2 V

DD

CC2

IH

(LVCMOS),

8

mA

After one memory cycle,

RASx and CASx high

Average

refresh

current

V

= 3.6 V,

Minimum cycle,

DD

RASx cycling,

‡§

‡¶

I

960

880

800

720

640

mA

CC3

(RAS-only

refresh

or CBR)

CASx high (RAS-only refresh),

RASx low after CASx low (CBR)

Average

EDO current

V

= 3.6 V,

t

= MIN,

DD

RASx low,

HPC

CASx cycling

CC4

†

For conditions shown as MIN/MAX, use the appropriate value specified in the timing requirements.

Measured with outputs open

‡

§

¶

Measured with a maximum of one address change while RASx = V

Measured with a maximum of one address change during each EDO cycle, t

IL

HPC

8

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

^{POST OFFICE BOX 1443}• HOUSTON, TEXAS 77251−1443

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SMMS684A − AUGUST 1997 − REVISED FEBRUARY 1998

electrical characteristics over recommended ranges of supply voltage and ambient temperature

(unless otherwise noted) (continued)

TM2EP72DxN

’2EP72DxN-50

’2EP72DxN-60

’2EP72DxN-70

†

PARAMETER

UNIT

TEST CONDITIONS

MIN

MAX

MIN

MAX

MIN

MAX

High-level

output

voltage

I

= − 2 mA

LVTTL

2.4

OH

OL

V

OH

= − 100 µA

= 2 mA

LVCMOS

LVTTL

V

−0.2

V

−0.2

V

−0.2

DD

Low-level

output

voltage

0.4

0.2

0.4

0.2

0.4

0.2

V

OL

= 100 µA

LVCMOS

Input current

(leakage)

V

= 3.6 V,

V = 0 V to 3.9 V,

DD

All others = 0 V to V

I

10

µA

I

DD

Output

current

(leakage)

V

= 3.6 V,

V

O

= 0 V to V ,

DD

CASx high

I

O

Read- or

write-cycle

current

‡§

I

V

= 3.6 V,

Minimum cycle

976

18

816

18

736

18

mA

CC1

DD

= 2 V (LVTTL),

IH

After one memory cycle,

RASx and CASx high

Standby

current

I

V

= V − 0.2 V

DD

CC2

IH

(LVCMOS),

9

mA

After one memory cycle,

RASx and CASx high

Average

refresh

current

V

= 3.6 V,

Minimum cycle,

DD

RASx cycling,

‡§

‡¶

I

976

990

816

810

736

720

mA

CC3

(RASx-only

refresh

or CBR)

CASx high (RAS-only refresh),

RASx low after CASx low (CBR)

Average

EDO current

V

= 3.6 V,

t

= MIN,

DD

RASx low,

HPC

CASx cycling

CC4

†

For conditions shown as MIN/MAX, use the appropriate value specified in the timing requirements.

Measured with outputs open

‡

§

¶

Measured with a maximum of one address change while RASx = V

Measured with a maximum of one address change during each EDO cycle, t

IL

HPC

9

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

^{POST OFFICE BOX 1443}• HOUSTON, TEXAS 77251−1443

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ꢐ

SMMS684A − AUGUST 1997 − REVISED FEBRUARY 1998

electrical characteristics over recommended ranges of supply voltage and ambient temperature

(unless otherwise noted) (continued)

TM4EP64DxN

’4EP64DxN-50

’4EP64DxN-60

’4EP64DxN-70

†

PARAMETER

UNIT

TEST CONDITIONS

MIN

MAX

MIN

MAX

MIN

MAX

High-level

output

voltage

I

= − 2 mA

LVTTL

2.4

OH

OL

V

OH

= − 100 µA

= 2 mA

LVCMOS

LVTTL

V

−0.2

V

−0.2

V

−0.2

DD

Low-level

output

voltage

0.4

0.2

0.4

0.2

0.4

0.2

V

OL

= 100 µA

LVCMOS

Input current

(leakage)

V

= 3.6 V,

V = 0 V to 3.9 V,

DD

All others = 0 V to V

I

20

µA

I

DD

Output

current

(leakage)

V

= 3.6 V,

V

O

= 0 V to V ,

DD

CASx high

I

O

Read- or

write-cycle

current

‡§

I

V

= 3.6 V,

Minimum cycle

976

32

816

32

736

32

mA

CC1

DD

= 2 V (LVTTL),

IH

After one memory cycle,

RASx and CASx high

Standby

current

I

V

= V − 0.2 V

DD

CC2

IH

(LVCMOS),

16

mA

After one memory cycle,

RASx and CASx high

Average

refresh

current

V

= 3.6 V,

Minimum cycle,

DD

RASx cycling,

‡§

‡¶

I

976

896

816

736

656

mA

CC3

(RASx-only

refresh

or CBR)

CASx high (RAS-only refresh),

RASx low after CASx low (CBR)

Average

EDO current

V

= 3.6 V,

t

= MIN,

DD

RASx low,

HPC

CASx cycling

CC4

†

For conditions shown as MIN/MAX, use the appropriate value specified in the timing requirements.

Measured with outputs open

‡

§

¶

Measured with a maximum of one address change while RASx = V

Measured with a maximum of one address change during each EDO cycle, t

IL

HPC

10

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

^{POST OFFICE BOX 1443}• HOUSTON, TEXAS 77251−1443

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ꢃꢖ

SMMS684A − AUGUST 1997 − REVISED FEBRUARY 1998

electrical characteristics over recommended ranges of supply voltage and ambient temperature

(unless otherwise noted) (continued)

TM4EP72DxN

’4EP72DxN-50

’4EP72DxN-60

’4EP72DxN-70

†

PARAMETER

UNIT

TEST CONDITIONS

MIN

MAX

MIN

MAX

MIN

MAX

High-level

output

voltage

I

= − 2 mA

LVTTL

2.4

OH

OL

V

OH

= − 100 µA

= 2 mA

LVCMOS

LVTTL

V

−0.2

V

−0.2

V

−0.2

DD

Low-level

output

voltage

0.4

0.2

0.4

0.2

0.4

0.2

V

OL

= 100 µA

LVCMOS

Input current

(leakage)

V

= 3.6 V,

V = 0 V to 3.9 V,

DD

All others = 0 V to V

I

20

µA

I

DD

Output

current

(leakage)

V

= 3.6 V,

V

O

= 0 V to V ,

DD

CASx high

I

O

Read- or

write-cycle

current

‡§

I

V

= 3.6 V,

Minimum cycle

1098

36

918

36

828

36

mA

CC1

DD

= 2 V (LVTTL),

IH

After one memory cycle,

RASx and CASx high

Standby

current

I

V

= V − 0.2 V

DD

CC2

IH

(LVCMOS),

18

mA

After one memory cycle,

RASx and CASx high

Average

refresh

current

V

= 3.6 V,

Minimum cycle,

DD

RASx cycling,

‡§

‡¶

I

1098

1008

918

828

738

mA

CC3

(RASx-only

refresh

or CBR)

CASx high (RAS-only refresh),

RASx low after CASx low (CBR)

Average

EDO current

V

= 3.6 V,

t

= MIN,

DD

RASx low,

HPC

CASx cycling

CC4

†

For conditions shown as MIN/MAX, use the appropriate value specified in the timing requirements.

Measured with outputs open

‡

§

¶

Measured with a maximum of one address change while RASx = V

Measured with a maximum of one address change during each EDO cycle, t

IL

HPC

11

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

^{POST OFFICE BOX 1443}• HOUSTON, TEXAS 77251−1443

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SMMS684A − AUGUST 1997 − REVISED FEBRUARY 1998

switching characteristics over recommended ranges of supply voltage and ambient temperature

(see Note 3)

’xEP64DxN-50 ’xEP64DxN-60 ’xEP64DxN-70

’xEP72DxN-50 ’xEP72DxN-60 ’xEP72DxN-70

PARAMETER

UNIT

MIN

MAX

25

MIN

MAX

30

MIN

MAX

35

t

Access time from column address (see Note 4)

Access time from CASx (see Note 4)

ns

AA

13

15

18

CAC

CPA

RAC

OEA

CLZ

REZ

CEZ

OEZ

WEZ

Access time from CASx precharge (see Note 4)

Access time from RASx (see Note 4)

28

35

40

50

60

70

Access time from OEx (see Note 4)

13

15

18

Delay time, CASx to output in low impedance

Output buffer turn off delay from RASx (see Note 5)

Output buffer turn off delay from CASx (see Note 5)

Output buffer turn off delay from OEx (see Note 5)

Output buffer turn off delay from WEx (see Note 5)

0

3

0

3

0

3

13

15

18

NOTES: 3. With ac parameters, it is assumed that t = 2 ns.

T

4. Access times are measured with output reference levels of V

=2 V and V =0.8 V.

OL

OH

5. The maximum values of t

, t

, and t are specified when the outputs are no longer driven. Data-in should not be driven

REZ CEZ OEZ

WEZ

until one of the applicable maximum values is satisfied.

EDO timing requirements (see Note 3)

’xEP64DxN-50 ’xEP64DxN-60 ’xEP64DxN-70

’xEP72DxN-50 ’xEP72DxN-60 ’xEP72DxN-70

UNIT

MIN

20

57

40

7

MAX

MIN

25

68

48

10

5

MAX

MIN

30

78

58

10

5

MAX

t

Cycle time, EDO page mode, read-write

Cycle time, EDO read-write

ns

HPC

PRWC

CSH

CHO

DOH

OEP

Delay time, RASx active to CASx precharge

Hold time, OEx from CASx

Hold time, output from CASx

Precharge time, OEx

5

t

Pulse duration, CASx active

8

7

8

5

10000

10 10000

12 10000

ns

CAS

WPE

CP

Pulse duration, WEx active (output disable only)

Pulse duration, CASx precharge

Setup time, OEx before CASx

Precharge time, OEx

7

10

5

7

10

5

OCH

OEP

NOTE 3: With ac parameters, it is assumed that t = 2 ns.

T

12

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

^{POST OFFICE BOX 1443}• HOUSTON, TEXAS 77251−1443

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ꢆ

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ꢈ

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ꢄ

ꢈ

ꢉ

ꢀ

ꢁ

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ꢃ

ꢄ

ꢋ

ꢂ

ꢇ

ꢊ

ꢈ

ꢉ

ꢀ

ꢁꢆ

ꢃ

ꢄ

ꢋ

ꢂ

ꢇ

ꢄ

ꢈ

ꢉ

ꢀ

ꢁ

ꢆ

ꢃ

ꢄꢋ

ꢂ

ꢇ

ꢊ

ꢈ

ꢃ

ꢌ

ꢀ

ꢃ

ꢈ

ꢇ

ꢃ

ꢇ

ꢍ

ꢇ

ꢎ

ꢀ

ꢎ

ꢍ

ꢏ

ꢐ

ꢀ

ꢇ

ꢑ

ꢈ

ꢎ

ꢁ

ꢒ

ꢓ

ꢔ

ꢎ

ꢁ

ꢏ

ꢇ

ꢐ

ꢕ

ꢃꢖ

SMMS684A − AUGUST 1997 − REVISED FEBRUARY 1998

ac timing requirements

’xEP64DxN-50

’xEP72DxN-50

’xEP64DxN-60

’xEP72DxN-60

’xEP64DxN-70

’xEP72DxN-70

UNIT

MIN

84

MAX

MIN

104

135

MAX

MIN

124

160

70

50

10

100

130

0

MAX

t

Cycle time, random read or write

Cycle time, read-write

ns

ms

ns

RC

111

RWC

RASP

RAS

RP

Pulse duration, RASx active, fast page mode (see Note 6)

50 100 000

60 100 000

100 000

10 000

Pulse duration, RASx active, non-page mode (see Note 6)

Pulse duration, RASx precharge

50

30

8

10 000

60

40

10

100

110

0

10 000

Pulse duration, write command

WP

Pulse duration, RASx active, self refresh (see Note 7)

Pulse duration, RASx precharge after self refresh

Setup time, column address

100

90

0

RASS

RPS

ASC

ASR

DS

Setup time, row address

0

Setup time, data in (see Note 8)

0

Setup time, read command

0

RCS

CWL

RWL

Setup time, write command before CASx precharge

Setup time, write command before RASx precharge

8

10

12

8

Setup time, write command before CASx active

(early-write only)

t

0

ns

WCS

t

Setup time, WEx high before RASx low (CBR refresh only)

Setup time, CASx referenced to RASx (CBR refresh only)

Hold time, column address

10

5

10

5

10

5

ns

WRP

CSR

CAH

DH

8

10

0

12

10

0

Hold time, data in (see Note 8)

8

Hold time, row address

8

RAH

RCH

RRH

Hold time, read command referenced to CASx (see Note 9)

Hold time, read command referenced to RASx (see Note 9)

0

Hold time, write command during CASx active

(early-write only)

t

8

10

12

ns

WCH

t

Hold time, RASx referenced to OEx

8

10

ns

ROH

WRH

CHR

OEH

RHCP

CHS

Hold time, WEx high after RASx low (CBR refresh only)

Hold time, CASx referenced to RASx (CBR refresh only)

Hold time, OEx command

10

13

15

18

Hold time, RASx active from CASx precharge

Hold time, CASx referenced to RASx (self refresh only)

28

35

40

− 50

Delay time, column address to write command

(read-write only)

t

42

49

57

ns

AWD

t

Delay time, CASx precharge to RASx

5

ns

CRP

NOTES: 6. In a read-write cycle, t

RWD

and t

must be observed.

≤100 µs, the device is in a transition state from normal-operation mode to self-refresh mode.

RWL

7. During the period of 10 µs ≤ t

RASS

8. Referenced to the later of CASx or WEx in write operations

9. Either t or t must be satisfied for a read cycle.

RRH RCH

13

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

^{POST OFFICE BOX 1443}• HOUSTON, TEXAS 77251−1443

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ꢈ

ꢉ

ꢎ

ꢉ

ꢀ

ꢁ

ꢂ

ꢍ

ꢂ

ꢃ

ꢏ

ꢃ

ꢄ

ꢐ

ꢄ

ꢋ

ꢀ

ꢅ

ꢂ

ꢆ

ꢇ

ꢊ

ꢑ

ꢊ

ꢈ

ꢉ

ꢎ

ꢉ

ꢀ

ꢁ

ꢆ

ꢃ

ꢔ

ꢃ

ꢄ

ꢎ

ꢄ

ꢋ

ꢅ

ꢂ

ꢁ

ꢆ

ꢇ

ꢄ

ꢁ

ꢄ

ꢈ

ꢏ

ꢈ

ꢉ

ꢇ

ꢉ

ꢀ

ꢕ

ꢁ

ꢃ

ꢆ

ꢖ

ꢃ

ꢄ

ꢅ

ꢋ

ꢆ

ꢂ

ꢇ

ꢊ

ꢈ

ꢀ

ꢁ

ꢋ

ꢂ

ꢀ

ꢁ

ꢀꢁ

ꢃ

ꢌꢀ

ꢇ

ꢍ

ꢇ

ꢀ

ꢎ

ꢁ

ꢒ

ꢓ

ꢐ

SMMS684A − AUGUST 1997 − REVISED FEBRUARY 1998

ac timing requirements (continued)

’xEP64DxN-50

’xEP72DxN-50

’xEP64DxN-60

’xEP72DxN-60

’xEP64DxN-70

’xEP72DxN-70

UNIT

MIN

30

13

10

25

18

12

5

MAX

MIN

34

15

12

30

20

14

5

MAX

MIN

40

18

12

35

25

14

5

MAX

t

Delay time, CASx to write command (read-write only)

Delay time, OEx to data in

ns

CWD

OED

RAD

RAL

Delay time, RASx to column address (see Note 10)

Delay time, column address to RASx precharge

Delay time, column address to CASx precharge

Delay time, RASx to CASx (see Note 10)

Delay time, RASx precharge to CASx

25

30

35

CAL

37

45

52

RCD

RPC

RSH

RWD

Delay time, CASx active to RASx precharge

Delay time, RASx to write command (read-write only)

8

10

79

12

92

67

Delay time, CASx precharge to write command

(read-write only)

t

45

2

54

62

ns

CPW

t

Refresh time interval

Transition time

32

30

32

30

32

30

ms

ns

REF

2

T

NOTE 10: The maximum value is specified only to ensure access time.

14

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

^{POST OFFICE BOX 1443}• HOUSTON, TEXAS 77251−1443

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ꢈ

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ꢇ

ꢊ

ꢈ

ꢉ

ꢀ

ꢁꢆ

ꢃ

ꢄ

ꢋ

ꢂ

ꢇ

ꢄ

ꢈ

ꢉ

ꢀ

ꢁꢆ

ꢃ

ꢄꢋ

ꢂ

ꢇ

ꢊ

ꢈ

ꢃ

ꢌ

ꢀꢃ

ꢈ

ꢇ

ꢃ

ꢇ

ꢍ

ꢇ

ꢎ

ꢀ

ꢎ

ꢍ

ꢏ

ꢐ

ꢀ

ꢇ

ꢑ

ꢈ

ꢎ

ꢁ

ꢒ

ꢓ

ꢔ

ꢎ

ꢁ

ꢏ

ꢇ

ꢐ

ꢕ

ꢃꢖ

SMMS684A − AUGUST 1997 − REVISED FEBRUARY 1998

serial presence detect

The serial presence detect (SPD) is contained in a 2K-bit serial EEPROM located on the module. The SPD

nonvolatile EEPROM contains various data such as module configuration, DRAM organization, and timing

parameters (see tables below). Only the first 128 bytes are programmed by Texas Instruments, while the

remaining 128 bytes are available for customer use. Programming is done through an IIC bus using the clock

(SCL) and data (SDA) signals. All Texas Instruments module comply with the current JEDEC SPD Standard.

Please see the Texas Instruments Serial Presence Detect Technical Reference (literature number SMMU001)

for further details.

Tables in this section list the SPD contents as follows:

Table 2−TM2EP64DxN

Table 4−TM4EP64DxN

Table 3−TM2EP72DxN

Table 5−TM4EP72DxN

Table 2. Serial Presence Detect Data for the TM2EP64DxN

’2EP64DxN-50

’2EP64DxN-60

’2EP64DxN-70

BYTE

NO.

FUNCTION DESCRIBED

ITEM

DATA

ITEM

DATA

ITEM

DATA

Defines number of bytes written

into serial memory during module

manufacturing

0

128 bytes

80h

128 bytes

80h

128 bytes

80h

Total number of bytes of SPD

memory device

1

2

3

4

5

256 bytes

EDO

11

08h

02h

0Bh

0Ah

01h

256 bytes

EDO

11

08h

02h

0Bh

0Ah

01h

256 bytes

EDO

11

08h

02h

0Bh

0Ah

01h

Fundamental memory type (FPM,

EDO, SDRAM)

Number of row addresses on this

assembly

Number of column addresses on

this assembly

10

Number of module banks on this

assembly

1 bank

64 bits

1 bank

64 bits

1 bank

64 bits

6

7

Data width of this assembly

Data width continuation

40h

00h

40h

00h

40h

00h

Voltage interface standard of this

assembly

8

LVTTL

01h

LVTTL

01h

LVTTL

01h

9

RASx access time of module

CASx access time of module

t

= 50 ns

= 13 ns

32h

0Dh

t

= 60 ns

= 15 ns

3Ch

0Fh

t

= 70 ns

= 18 ns

46h

12h

RAC

10

CAC

DIMM configuration type

(non-parity, parity, ECC)

11

Non-Parity

00h

Non-Parity

00h

Non-Parity

00h

12

13

14

62

63

Refresh rate/type

15.6 µs

x8

00h

08h

00h

01h

29h

15.6 µs

x8

00h

08h

00h

01h

35h

15.6 µs

x8

00h

08h

00h

01h

42h

DRAM width, primary DRAM

Error-checking SDRAM data width

SPD revision

N/A

Rev. 1

41

N/A

Rev. 1

53

N/A

Rev. 1

66

Checksum for bytes 0−62

Manufacturer’s JEDEC ID code per

JEP-106E

64−71

97h

9700...00h

97h

9700...00h

97h

9700...00h

15

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

^{POST OFFICE BOX 1443}• HOUSTON, TEXAS 77251−1443

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ꢎ

ꢉ

ꢀ

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ꢂ

ꢍ

ꢂ

ꢃ

ꢏ

ꢃ

ꢄ

ꢐ

ꢄ

ꢋ

ꢀ

ꢅ

ꢂ

ꢆ

ꢇ

ꢊ

ꢑ

ꢊ

ꢈ

ꢉ

ꢎ

ꢉ

ꢀ

ꢁ

ꢆ

ꢃ

ꢔ

ꢃ

ꢄ

ꢎ

ꢄ

ꢋ

ꢅ

ꢂ

ꢁ

ꢆ

ꢇ

ꢄ

ꢁ

ꢄ

ꢈ

ꢏ

ꢈ

ꢉ

ꢇ

ꢉ

ꢀ

ꢕ

ꢁ

ꢃ

ꢆ

ꢖ

ꢃ

ꢄ

ꢅ

ꢋ

ꢆ

ꢂ

ꢇ

ꢊ

ꢈ

ꢀ

ꢁ

ꢋ

ꢂ

ꢀ

ꢁ

ꢀꢁ

ꢃ

ꢌꢀ

ꢇ

ꢍ

ꢇ

ꢀꢎ

ꢁ

ꢒ

ꢓ

ꢐ

SMMS684A − AUGUST 1997 − REVISED FEBRUARY 1998

serial presence detect (continued)

Table 2. Serial Presence Detect Data for the TM2EP64DxN (Continued)

’2EP64DxN-50

ITEM DATA

’2EP64DxN-60

ITEM DATA

’2EP64DxN-70

ITEM DATA

BYTE

NO.

FUNCTION DESCRIBED

†

72

73−90

91

Manufacturing location

TBD

†

Manufacturer’s part number

†

Die revision code

†

PCB revision code

92

†

93−94

95−98

Manufacturing date

Assembly serial number

†

99−125 Manufacturer specific data

†

126−127 Vendor specific data

‡

128−166 System integrator’s specific data

167−255 Open

†

‡

TBD indicates values are determined at manufacturing time and are module dependent.

These TBD values are determined and programmed by the customer (optional).

16

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

^{POST OFFICE BOX 1443}• HOUSTON, TEXAS 77251−1443

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ꢆ

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ꢅ

ꢆ

ꢇ

ꢄ

ꢈ

ꢉ

ꢀ

ꢁꢆ

ꢃ

ꢄ

ꢅ

ꢆ

ꢇ

ꢊ

ꢈ

ꢀ

ꢁ

ꢂ

ꢃ

ꢄ

ꢋ

ꢂ

ꢇ

ꢄ

ꢈ

ꢉ

ꢀ

ꢁꢂ

ꢃ

ꢄ

ꢋ

ꢂ

ꢇ

ꢊ

ꢈ

ꢉ

ꢀ

ꢁꢆ

ꢃ

ꢄ

ꢋ

ꢂ

ꢇ

ꢄ

ꢈ

ꢉ

ꢀ

ꢁ

ꢆ

ꢃ

ꢄꢋ

ꢂ

ꢇ

ꢊ

ꢈ

ꢃ

ꢌ

ꢀ

ꢃ

ꢈ

ꢇ

ꢃ

ꢇ

ꢍ

ꢇ

ꢎ

ꢀ

ꢎ

ꢍ

ꢏ

ꢐ

ꢀ

ꢇ

ꢑ

ꢈ

ꢎ

ꢁ

ꢒ

ꢓ

ꢔ

ꢎ

ꢁ

ꢏ

ꢇ

ꢐ

ꢕ

ꢃ

ꢖ

SMMS684A − AUGUST 1997 − REVISED FEBRUARY 1998

serial presence detect (continued)

Table 3. Serial Presence Detect Data for the TM2EP72DxN

’2EP72DxN-50

’2EP72DxN-60

’2EP72DxN-70

BYTE

NO.

FUNCTION DESCRIBED

ITEM

DATA

ITEM

DATA

ITEM

DATA

Defines number of bytes written

into serial memory during module

manufacturing

0

128 bytes

80h

128 bytes

80h

128 bytes

80h

Total number of bytes of SPD

memory device

1

2

3

4

5

256 bytes

EDO

11

08h

02h

0Bh

0Ah

01h

256 bytes

EDO

11

08h

02h

0Bh

0Ah

01h

256 bytes

EDO

11

08h

02h

0Bh

0Ah

01h

Fundamental memory type (FPM,

EDO, SDRAM)

Number of row addresses on this

assembly

Number of column addresses on

this assembly

10

Number of module banks on this

assembly

1 bank

72 bits

1 bank

72 bits

1 bank

72 bits

6

7

Data width of this assembly

Data width continuation

48h

00h

48h

00h

48h

00h

Voltage interface standard of this

assembly

8

LVTTL

01h

LVTTL

01h

LVTTL

01h

9

RASx access time of module

CASx access time of module

t

= 50 ns

= 13 ns

32h

0Dh

t

= 60 ns

= 15 ns

3Ch

0Fh

t

= 70 ns

= 18 ns

46h

12h

RAC

10

CAC

DIMM configuration type

(non-parity, parity, ECC)

11

ECC

02h

ECC

02h

ECC

02h

12

13

14

62

63

Refresh rate/type

15.6 µs

x8

00h

08h

01h

3Bh

15.6 µs

x8

00h

08h

01h

47h

15.6 µs

x8

00h

08h

01h

54h

DRAM width, primary DRAM

Error-checking SDRAM data width

SPD revision

x8

Rev. 1

59

Rev. 1

71

Rev. 1

84

Checksum for bytes 0−62

Manufacturer’s JEDEC ID code per

JEP-106E

64−71

97h

9700...00h

97h

9700...00h

97h

9700...00h

†

72

73−90

91

Manufacturing location

TBD

†

Manufacturer’s part number

†

Die revision code

†

PCB revision code

92

†

93−94

95−98

Manufacturing date

†

Assembly serial number

†

99−125 Manufacturer specific data

†

126−127 Vendor specific data

‡

128−166 System integrator’s specific data

167−255 Open

†

‡

TBD indicates values are determined at manufacturing time and are module dependent.

These TBD values are determined and programmed by the customer (optional).

17

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

^{POST OFFICE BOX 1443}• HOUSTON, TEXAS 77251−1443

ꢀ

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ꢈ

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ꢄ

ꢈ

ꢉ

ꢎ

ꢉ

ꢀ

ꢁ

ꢂ

ꢍ

ꢂ

ꢃ

ꢏ

ꢃ

ꢄ

ꢐ

ꢄ

ꢋ

ꢀ

ꢅ

ꢂ

ꢆ

ꢇ

ꢊ

ꢑ

ꢊ

ꢈ

ꢉ

ꢎ

ꢉ

ꢀ

ꢁ

ꢆ

ꢃ

ꢔ

ꢃ

ꢄ

ꢎ

ꢄ

ꢋ

ꢅ

ꢂ

ꢁ

ꢆ

ꢇ

ꢄ

ꢁ

ꢄ

ꢈ

ꢏ

ꢈ

ꢉ

ꢇ

ꢉ

ꢀ

ꢕ

ꢁ

ꢃ

ꢆ

ꢖ

ꢃ

ꢄ

ꢅ

ꢋ

ꢆ

ꢂ

ꢇ

ꢊ

ꢈ

ꢀ

ꢁ

ꢋ

ꢂ

ꢀ

ꢁ

ꢀ

ꢁ

ꢃ

ꢌꢀ

ꢇ

ꢍ

ꢇ

ꢀ

ꢎ

ꢁ

ꢒ

ꢓ

ꢐ

SMMS684A − AUGUST 1997 − REVISED FEBRUARY 1998

serial presence detect (continued)

Table 4. Serial Presence Detect Data for the TM4EP64DxN

’4EP64DxN-50

’4EP64DxN-60

’4EP64DxN-70

BYTE

NO.

FUNCTION DESCRIBED

ITEM

DATA

ITEM

DATA

ITEM

DATA

Defines number of bytes written

into serial memory during module

manufacturing

0

128 bytes

80h

128 bytes

80h

128 bytes

80h

Total number of bytes of SPD

memory device

1

2

3

4

5

256 bytes

EDO

11

08h

02h

0Bh

0Ah

02h

256 bytes

EDO

11

08h

02h

0Bh

0Ah

02h

256 bytes

EDO

11

08h

02h

0Bh

0Ah

02h

Fundamental memory type (FPM,

EDO, SDRAM)

Number of row addresses on this

assembly

Number of column addresses on

this assembly

10

Number of module banks on this

assembly

2 banks

64 bits

2 banks

64 bits

2 banks

64 bits

6

7

Data width of this assembly

Data width continuation

40h

00h

40h

00h

40h

00h

Voltage interface standard of this

assembly

8

LVTTL

01h

LVTTL

01h

LVTTL

01h

9

RASx access time of module

CASx access time of module

t

= 50 ns

= 13 ns

32h

0Dh

t

= 60 ns

= 15 ns

3Ch

0Fh

t

= 70 ns

= 18 ns

46h

12h

RAC

10

CAC

DIMM configuration type

(non-parity, parity, ECC)

11

Non-Parity

00h

Non-Parity

00h

Non-Parity

00h

12

13

14

62

63

Refresh rate/type

15.6 µs

x8

00h

08h

00h

01h

2Ah

15.6 µs

x8

00h

08h

00h

01h

36h

15.6 µs

x8

00h

08h

00h

01h

43h

DRAM width, primary DRAM

Error-checking SDRAM data width

SPD revision

N/A

Rev. 1

42

N/A

Rev. 1

54

N/A

Rev. 1

67

Checksum for bytes 0−62

Manufacturer’s JEDEC ID code per

JEP-106E

64−71

97h

9700...00h

97h

9700...00h

97h

9700...00h

†

72

73−90

91

Manufacturing location

TBD

†

Manufacturer’s part number

†

Die revision code

†

PCB revision code

92

†

93−94

95−98

Manufacturing date

†

Assembly serial number

†

99−125 Manufacturer specific data

†

126−127 Vendor specific data

‡

128−166 System integrator’s specific data

167−255 Open

†

‡

TBD indicates values are determined at manufacturing time and are module dependent.

These TBD values are determined and programmed by the customer (optional).

18

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

^{POST OFFICE BOX 1443}• HOUSTON, TEXAS 77251−1443

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SMMS684A − AUGUST 1997 − REVISED FEBRUARY 1998

serial presence detect (continued)

Table 5. Serial Presence Detect for the TM4EP72DxN

’4EP72DxN-50

’4EP72DxN-60

’4EP72DxN-70

BYTE

NO.

FUNCTION DESCRIBED

ITEM

DATA

ITEM

DATA

ITEM

DATA

Defines number of bytes written

into serial memory during module

manufacturing

0

128 bytes

80h

128 bytes

80h

128 bytes

80h

Total number of bytes of SPD

memory device

1

2

3

4

5

256 bytes

EDO

11

08h

02h

0Bh

0Ah

02h

256 bytes

EDO

11

08h

02h

0Bh

0Ah

02h

256 bytes

EDO

11

08h

02h

0Bh

0Ah

02h

Fundamental memory type (FPM,

EDO, SDRAM)

Number of row addresses on this

assembly

Number of column addresses on

this assembly

10

Number of module banks on this

assembly

2 banks

72 bits

2 banks

72 bits

2 banks

72 bits

6

7

Data width of this assembly

Data width continuation

48h

00h

48h

00h

48h

00h

Voltage interface standard of this

assembly

8

LVTTL

01h

LVTTL

01h

LVTTL

01h

9

RASx access time of module

CASx access time of module

t

= 50 ns

= 13 ns

32h

0Dh

t

= 60 ns

= 15 ns

3Ch

0Fh

t

= 70 ns

= 18 ns

46h

12h

RAC

10

CAC

DIMM configuration type

(non-parity, parity, ECC)

11

ECC

02h

ECC

02h

ECC

02h

12

13

14

62

63

Refresh rate/type

15.6 µs

x8

00h

08h

01h

3Ch

15.6 µs

x8

00h

08h

01h

48h

15.6 µs

x8

00h

08h

01h

55h

DRAM width, primary DRAM

Error-checking SDRAM data width

SPD revision

x8

Rev. 1

60

Rev. 1

72

Rev. 1

85

Checksum for bytes 0−62

Manufacturer’s JEDEC ID code per

JEP-106E

64−71

97h

9700...00h

97h

9700...00h

97h

9700...00h

†

72

73−90

91

Manufacturing location

TBD

†

Manufacturer’s part number

†

Die revision code

†

PCB revision code

92

†

93−94

95−98

Manufacturing date

†

Assembly serial number

†

99−125 Manufacturer specific data

†

126−127 Vendor specific data

‡

128−166 System integrator’s specific data

167−255 Open

†

‡

TBD indicates values are determined at manufacturing time and are module dependent.

These TBD values are determined and programmed by the customer (optional).

19

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

^{POST OFFICE BOX 1443}• HOUSTON, TEXAS 77251−1443

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SMMS684A − AUGUST 1997 − REVISED FEBRUARY 1998

device symbolization (TM4EP64DPN illustrated)

TM4EP64DPN

-SS

YYMMT

Unbuffered Key Position

3.3-V Voltage Key Position

YY = Year Code

MM = Month Code

T = Assembly Site Code

-SS = Speed Code

NOTE A: Location of symbolization may vary.

20

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

^{POST OFFICE BOX 1443}• HOUSTON, TEXAS 77251−1443

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SMMS684A − AUGUST 1997 − REVISED FEBRUARY 1998

MECHANICAL DATA

BR (R-PDIM-N168)

DUAL IN-LINE MEMORY MODULE

5.255 (133,48)

5.245 (133,22)

(Note D)

0.054 (1,37)

Notch 0.157 (4,00) x 0.122 (3,10) Deep

2 Places

Notch 0.079 (2,00) x 0.122 (3,10) Deep

2 Places

0.046 (1,17)

0.050 (1,27)

0.125 (3,18)

0.039 (1,00) TYP

0.125 (3,18)

0.014 (0,35) MAX

0.118 (3,00) TYP

0.700 (17,78) TYP

1.005 (25,53)

0.118 (3,00) DIA

2 Places

0.995 (25,27)

0.106 (2,70) MAX

0.157 (4,00) MAX

(For Double Sided DIMM Only)

4088180/A 07/97

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C. Falls within JEDEC MO-161

D. Dimension includes de-panelization variations; applies between notch and tab edge.

E. Outline may vary above notches to allow router/panelization irregularities.