TM4100EAD9-80 [TI]
4MX9 FAST PAGE DRAM MODULE, 80ns, SMA30, SIMM-30;
| 型号： | TM4100EAD9-80 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 4MX9 FAST PAGE DRAM MODULE, 80ns, SMA30, SIMM-30 动态存储器 内存集成电路 |
| 文件： | 总9页 (文件大小：108K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TM4100EAD9
4194304 BY 9-BIT
DYNAMIC RAM MODULE
SMMS419C – NOVEMBER 1991 – REVISED JUNE 1995
Organization . . . 4194304 × 9
SINGLE IN-LINE MODULE
(TOP VIEW)
Single 5-V Power Supply (±10% Tolerance)
30-Pin Single In-Line Memory Module
(SIMM) for Use With Sockets
Utilizes Nine 4-Megabit Dynamic RAMs in
Plastic Small-Outline J-Lead Packages
(SOJs)
V
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
CC
CAS
DQ1
A0
Long Refresh Period
16 ms (1024 Cycles)
A1
DQ2
A2
All Inputs, Outputs, and Clocks Fully TTL
Compatible
A3
SS
V
DQ3
A4
3-State Outputs
Performance Ranges:
A5
DQ4
A6
ACCESS ACCESS ACCESS READ
TIME
(t
TIME
TIME
(t
OR
A7
)
(t
CAC)
)
WRITE
CYCLE
(MIN)
RAC
AA
DQ5
A8
A9
(MAX)
’4100EAD9-60 60 ns
’4100EAD9-70 70 ns
’4100EAD9-80 80 ns
(MAX)
15 ns
18 ns
20 ns
(MAX)
30 ns
35 ns
40 ns
A10
DQ6
W
V
DQ7
NC
110 ns
130 ns
150 ns
SS
Common CAS Control for Eight Common
Data-In and Data-Out Lines
DQ8
Q9
Separate CAS Control for One Separate
Pair of Data-In and Data-Out Lines
RAS
CAS9
D9
Low Power Dissipation
V
CC
Operating Free-Air Temperature Range
0°C to 70°C
description
The TM4100EAD9 is a dynamic random-access
memory module organized as 4194304 × 9 [bit
nine (D9, Q9) is generally used for parity and is
controlled by CAS9] in a 30-pin leadless single
in-line memory module (SIMM).
PIN NOMENCLATURE
A0–A10
Address Inputs
CAS, CAS9
DQ1–DQ8
D9
Column-Address Strobe
Data In/Data Out
Data In
This module is composed of nine TMS44100DJ,
4194304 × 1-bit dynamic RAMs (DRAMs) each in
a 20/26-lead plastic small-outline J-lead package
(SOJ) mounted on a substrate with decoupling
capacitors.
NC
No Internal Connection
Data Out
Q9
RAS
Row-Address Strobe
5-V Supply
V
V
CC
Ground
SS
W
Write Enable
The TM4100EAD9 is characterized for operation
from 0°C to 70°C and is available in the AD
single-sided, leadless module for use with
sockets.
Copyright 1995, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TM4100EAD9
4194304 BY 9-BIT
DYNAMIC RAM MODULE
SMMS419C – NOVEMBER 1991 – REVISED JUNE 1995
functional block diagram
A0–A10
RAS
CAS
W
4096K × 1
4096K × 1
A0–A10
RAS
CAS
W
11
11
11
11
11
11
11
11
11
A0–A10
RAS
CAS
W
Q
Q
Q
Q
Q
Q
Q
Q
Q
D
D
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
V
CC
V
SS
V
CC
V
SS
4096K × 1
A0–A10
RAS
CAS
W
4096K × 1
A0–A10
RAS
CAS
W
D
V
D
V
SS
V
CC
V
SS
CC
4096K × 1
A0–A10
RAS
CAS
W
4096K × 1
A0–A10
RAS
CAS
W
D
V
D
V
V
SS
V
SS
CC
CC
4096K × 1
A0–A10
RAS
CAS
W
4096K × 1
A0–A10
RAS
CAS
W
D
V
D
V
SS
V
V
SS
CC
CC
4096K × 1
A0–A10
RAS
CAS
W
CAS9
D9
D
V
V
SS
CC
Q9
V
V
CC
C . . . .C
SS
2
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TM4100EAD9
4194304 BY 9-BIT
DYNAMIC RAM MODULE
SMMS419C – NOVEMBER 1991 – REVISED JUNE 1995
operation
The TM4100EAD9 operates as nine TMS44100DJs connected as shown in the functional block diagram. Refer
to the TMS44100 data sheet for details of its operation. The common I/O feature of the TM4100EAD9 dictates
the use of early-write cycles to prevent contention on D and Q.
single in-line memory module and components
PC substrate: 1,27 mm (0.05 inch) nominal thickness; 0.005 inch/inch maximum warpage
Bypass capacitors: Multilayer ceramic
Contact area for socketable devices: Nickel plate and solder plate over copper
3
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TM4100EAD9
4194304 BY 9-BIT
DYNAMIC RAM MODULE
SMMS419C – NOVEMBER 1991 – REVISED JUNE 1995
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Voltage range on any pin (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 1 V to 7 V
Voltage range on V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 1 V to 7 V
CC
Short-circuit output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 W
Operating free-air temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
A
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 125°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to V
.
SS
recommended operating conditions
MIN NOM
MAX
5.5
6.5
0.8
70
UNIT
V
V
V
V
Supply voltage
4.5
2.4
– 1
0
5
CC
IH
IL
High-level input voltage
V
Low-level input voltage (see Note 2)
Operating free-air temperature
V
T
A
°C
NOTE 2: The algebraic convention, where the more negative (less positive) limit is designated as minimum, is used for logic-voltage levels only.
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
’4100EAD9-60 ’4100EAD9-70 ’4100EAD9-80
PARAMETER
TEST CONDITIONS
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
V
V
High-level output voltage
Low-level output voltage
I
I
= – 5 mA
= 4.2 mA
2.4
2.4
2.4
V
V
OH
OH
0.4
0.4
0.4
OL
OL
V
= 5.5 V,
V = 0 V to 6.5 V,
I
CC
CC
All others = 0 V to V
I
I
I
Input current (leakage)
Output current (leakage)
±10
±10
±10
µA
µA
I
V
= 5.5 V,
V
= 0 V to V ,
CC
CC
CAS high
O
±10
±10
±10
O
Read- or write-cycle current
(see Note 3)
V
CC
= 5.5 V,
Minimum cycle
945
810
720
mA
CC1
After 1 memory cycle,
RAS and CAS high,
18
9
18
9
18
9
mA
mA
V
IH
= 2.4 V (TTL)
I
Standby current
CC2
After 1 memory cycle,
RAS and CAS high,
V
= V
– 0.2 V (CMOS)
IH
CC
= 5.5 V,
V
CC
Minimum cycle,
Average refresh current
(RAS only or CBR)
(see Note 3)
RAS cycling,
I
I
945
810
810
720
720
630
mA
mA
CC3
CAS high (RAS only),
RAS low after CAS low (CBR)
V
= 5.5 V,
t
= minimum,
Average page current
(see Note 4)
CC
RAS low,
PC
CAS cycling
CC4
NOTES: 3. Measured with a maximum of one address change while RAS = V
IL
4. Measured with a maximum of one address change while CAS = V
IH
4
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TM4100EAD9
4194304 BY 9-BIT
DYNAMIC RAM MODULE
SMMS419C – NOVEMBER 1991 – REVISED JUNE 1995
capacitance over recommended ranges of supply voltage and operating free-air temperature,
f = 1 MHz (see Note 5)
PARAMETER
MIN
MAX
45
5
UNIT
pF
C
C
C
C
C
C
Input capacitance, A0–A10
Input capacitance, data input (pin D9)
Input capacitance, CAS and RAS
Input capacitance, W
i(A)
pF
i(D)
63
63
12
7
pF
i(RC)
i(W)
o(DQ)
O
pF
Output capacitance, DQ1–Q8
Output capacitance, Q9
pF
pF
NOTE 5:
V
CC
= 5 V ± 0.5 V and the bias on pins under test is 0 V.
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature
’4100EAD9-60 ’4100EAD9-70 ’4100EAD9-80
PARAMETER
UNIT
MIN
MAX
30
MIN
MAX
35
MIN
MAX
40
t
t
t
t
t
t
Access time from column address
ns
ns
ns
ns
ns
ns
AA
Access time from CAS low
15
18
20
CAC
CPA
RAC
CLZ
OFF
Access time from column precharge
Access time from RAS low
35
40
45
60
70
80
CAS to output in low-impedance
Output disable time after CAS high (see Note 6)
0
0
0
0
0
0
15
18
20
NOTE 6:
t
is specified when the output is no longer driven.
OFF
5
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TM4100EAD9
4194304 BY 9-BIT
DYNAMIC RAM MODULE
SMMS419C – NOVEMBER 1991 – REVISED JUNE 1995
timing requirements over recommended ranges of supply voltage and operating free-air
temperature
’4100EAD9-60
’4100EAD9-70
’4100EAD9-80
UNIT
MIN
110
40
MAX
MIN
130
45
MAX
MIN
150
50
MAX
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Cycle time, random read or write (see Note 7)
Cycle time, page-mode read or write (see Note 8)
Pulse duration, page mode RAS low (see Note 9)
Pulse duration, nonpage mode, RAS low (see Note 9)
Pulse duration, CAS low (see Note 10)
Pulse duration, CAS high
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
RC
PC
60 100 000
70 100 000
80 100 000
RASP
RAS
CAS
CP
60
15
10
40
15
0
10 000
10 000
70
18
10
50
15
0
10 000
10 000
80
20
10
60
15
0
10 000
10 000
Pulse duration, RAS high (precharge)
Pulse duration, write
RP
WP
Setup time, column address before CAS low
Setup time, row address before RAS low
Setup time, data (see Note 11)
ASC
ASR
DS
0
0
0
0
0
0
Setup time, read before CAS low
0
0
0
RCS
CWL
RWL
WCS
WSR
WTS
CAH
DHR
DH
Setup time, W low before CAS high
15
15
0
18
18
0
20
20
0
Setup time, W low before RAS high
Setup time, W low before CAS low (early-write operation only)
Setup time, W high (CBR refresh only)
Setup time, W low (test mode only)
10
10
10
50
10
50
10
0
10
10
15
55
15
55
10
0
10
10
15
60
15
60
10
0
Hold time, column address after CAS low
Hold time, data after RAS low (see Note 12)
Hold time, data (see Note 10)
Hold time, column address after RAS low (see Note 12)
Hold time, row address after RAS low
Hold time, read after CAS high (see Note 13)
Hold time, read after RAS high (see Note 13)
Hold time, write after CAS low (early-write operation only)
Hold time, write after RAS low (see Note 12)
Hold time, W high (CBR refresh only)
AR
RAH
RCH
RRH
WCH
WCR
WHR
WTH
0
0
0
15
50
10
10
15
55
10
10
15
60
10
10
Hold time, W low (test mode only)
t
t
t
t
Delay time, RAS low to CAS high (CBR refresh only)
Delay time, CAS high to RAS low
15
0
15
0
20
0
ns
ns
ns
ns
CHR
CRP
CSH
CSR
Delay time, RAS low to CAS high
60
10
70
10
80
10
Delay time, CAS low to RAS low (CBR refresh only)
NOTES: 7. All cycle times assume t = 5 ns.
T
ASC
RWD
CWD
8. To assure t
9. In a read-write cycle, t
10. In a read-write cycle, t
min, t
should be ≥ 5 ns.
PC
and t
and t
must be observed.
must be observed.
RWL
CWL
11. Referenced to the later of CAS or W in write operations
12. The minimum value is measured when t
is set to t min as a reference.
RCD
RCD
must be satisfied for a read cycle.
13. Either t
RRH
or t
RCH
6
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TM4100EAD9
4194304 BY 9-BIT
DYNAMIC RAM MODULE
SMMS419C – NOVEMBER 1991 – REVISED JUNE 1995
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (continued)
’4100EAD9-60
’4100EAD9-70
’4100EAD9-80
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
t
Delay time, RAS low to column address (see Note 14)
15
30
15
35
15
40
ns
RAD
t
t
t
t
t
t
t
t
t
t
Delay time, column address to RAS high
Delay time, column address to CAS high
Delay time, RAS low to CAS low (see Note 14)
Delay time, RAS high to CAS low
Delay time, CAS low to RAS high
Access time from address (test mode)
Access time from column precharge (test mode)
Access time from RAS (test mode)
Refresh time interval
30
30
20
0
35
35
20
0
40
40
20
0
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
RAL
CAL
RCD
RPC
RSH
TAA
TCPA
TRAC
REF
T
45
52
60
15
35
40
65
18
40
45
75
20
45
50
85
16
50
16
50
16
50
Transition time
2
2
2
NOTE 14: The maximum value is specified only to assure access time.
device symbolization
TM4100EAD9
– SS
YYMMT
YY = Year Code
MM = Month Code
T
= Assembly Site Code
–SS = Speed
NOTE: The location of symbolization may vary.
7
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TM4100EAD9
4194304 BY 9-BIT
DYNAMIC RAM MODULE
SMMS419C – NOVEMBER 1991 – REVISED JUNE 1995
8
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
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accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
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Copyright 1998, Texas Instruments Incorporated
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