TM893GBK32-70 [TI]
8MX32 EDO DRAM MODULE, 70ns, SMA72, SIMM-72;
| 型号： | TM893GBK32-70 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 8MX32 EDO DRAM MODULE, 70ns, SMA72, SIMM-72 动态存储器 内存集成电路 |
| 文件： | 总12页 (文件大小：168K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TM497FBK32, TM497FBK32S 4194304 BY 32-BIT
TM893GBK32, TM893GBK32S 8388608 BY 32-BIT
EXTENDED DATA OUT DYNAMIC RAM MODULES
SMMS668 – NOVEMBER 1996
Organization
Presence Detect
– TM497FBK32/S: 4 194 304 x 32
– TM893GBK32/S: 8 388 608 x 32
Performance Ranges:
ACCESS ACCESS ACCESS EDO
TIME
TIME
TIME
CYCLE
Single 5-V Power Supply (±10% Tolerance)
t
t
t
t
RAC
AA
CAC
HPC
72-Pin Single-In-Line Memory Module
(SIMM) for Use With Sockets
(MAX)
’497FBK32/S-60 60 ns
’497FBK32/S-70 70 ns
’497FBK32/S-80 80 ns
(MAX)
30 ns
35 ns
40 ns
(MAX)
15 ns
18 ns
20 ns
(MIN)
25 ns
30 ns
35 ns
TM497FBK32/S – Uses Eight 16M-Bit
Dynamic Random-Access Memories
(DRAMs) in Plastic Small-Outline J-Lead
(SOJ) Packages
’893GBK32/S-60 60 ns
’893GBK32/S-70 70 ns
’893GBK32/S-80 80 ns
30 ns
35 ns
40 ns
15 ns
18 ns
20 ns
25 ns
30 ns
35 ns
TM893GBK32/S – Uses Sixteen 16M-Bit
DRAMs in Plastic SOJ Packages
Low Power Dissipation
Long Refresh Period
32 ms (2 048 Cycles)
Operating Free-Air Temperature Range
0°C to 70°C
All Inputs, Outputs, Clocks Fully
TTL-Compatible
†
Gold-Tabbed Version Available:
TM497FBK32, TM893GBK32
3-State Output
Tin-Lead (Solder-) Tabbed Version
Available: TM497FBK32S, TM893GBK32S
Common CAS Control for Eight Common
Data-In and Data-Out Lines in Four Blocks
Extended Data Out (EDO) Operation With
CAS-Before-RAS (CBR), RAS-Only, and
Hidden Refresh
description
The TM497FBK32 is a 16M-byte dynamic random-access memory (DRAM) organized as four times
4194304 × 8 bits in a 72-pin leadless single-in-line memory module (SIMM). The SIMM is composed of eight
TMS417409DJ, 4194304 × 4-bit DRAMs, each in 24/26-lead plastic small-outline J-lead (SOJ) packages
mounted on a substrate with decoupling capacitors. The TMS417409DJ is described in the TMS416409,
TMS417409 data sheet (literature number SMKS884).
The TM497FBK32 SIMM is available in the single-sided BK leadless module for use with sockets. The
TM497FBK32 features RAS access times of 60 ns, 70 ns, and 80 ns. This device is characterized for operation
from 0°C to 70°C.
The TM893GBK32/S is a 32M-byte DRAM organized as four times 8388608 × 8 bits in a 72-pin leadless SIMM.
The SIMM is composed of sixteen TMS417409DJ 4194304 × 4-bit DRAMs.
The TM893GBK32/S SIMM is available in the double-sided BK leadless module for use with sockets. The
TM893GBK32/S features RAS access times of 60 ns, 70 ns, and 80 ns. This device is characterized for
operation from 0°C to 70°C.
operation
The TM497FBK32/S operates as eight TMS417409DJs connected as shown in Figure 1 and in Table 1. The
common I/O feature dictates the use of early write cycles to prevent contention on D and Q.
The TM893GBK32/S operates as sixteen TMS417409DJs connected as shown in Figure 2 and in Table 2. The
common I/O feature dictates the use of early write cycles to prevent contention on D and Q.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
†
Part numbers in this data sheet are for the gold-tabbed version; the information applies to both gold-tabbed and solder-tabbed versions.
Copyright 1996, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TM497FBK32, TM497FBK32S 4194304 BY 32-BIT
TM893GBK32, TM893GBK32S 8388608 BY 32-BIT
EXTENDED DATA OUT DYNAMIC RAM MODULES
SMMS668 – NOVEMBER 1996
refresh
The refresh period is extended to 32 ms and, during this period, each of the 2 048 rows must be strobed with
RAS in order to retain data. CAS can remain high during the refresh sequence to conserve power.
power up
To achieve proper operation, an initial pause of 200 µs followed by a minimum of eight initialization cycles is
required after full V
(RAS-only or CBR) cycle.
level is achieved. These eight initialization cycles need to include at least one refresh
CC
2
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TM497FBK32, TM497FBK32S 4194304 BY 32-BIT
TM893GBK32, TM893GBK32S 8388608 BY 32-BIT
EXTENDED DATA OUT DYNAMIC RAM MODULES
SMMS668 – NOVEMBER 1996
BK SINGLE-IN-LINE PACKAGE
(TOP VIEW)
TM497FBK32/S
(SIDE VIEW)
TM893GBK32/S
(SIDE VIEW)
V
1
2
3
4
SS
DQ0
DQ16
DQ1
DQ17
DQ2
5
6
DQ18
DQ3
7
8
DQ19
9
V
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
CC
NC
A0
A1
A2
A3
A4
A5
A6
A10
DQ4
DQ20
DQ5
DQ21
DQ6
DQ22
DQ7
DQ23
A7
NC
V
CC
A8
A9
NC
RAS2
NC
NC
NC
NC
SS
CAS0
CAS2
CAS3
CAS1
RAS0
NC
NC
W
NC
DQ8
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
V
PIN NOMENCLATURE
A0–A10
Address Inputs
Column-Address Strobe
Data In/Data Out
No Connection
Presence Detects
Row-Address Strobe
5-V Supply
CAS0–CAS3
DQ0–DQ31
NC
PD1–PD4
RAS0–RAS3
DQ24
DQ9
V
V
W
CC
SS
DQ25
DQ10
DQ26
DQ11
DQ27
DQ12
DQ28
Ground
Write Enable
PRESENCE DETECT
V
CC
DQ29
DQ13
DQ30
DQ14
DQ31
DQ15
NC
SIGNAL
(PIN)
PD1
(67)
PD2
(68)
PD3
(69)
PD4
(70)
80 ns
70 ns
60 ns
80 ns
70 ns
60 ns
V
V
V
NC
NC
NC
NC
V
SS
SS
SS
SS
TM497FBK32/S
TM893GBK32/S
V
SS
NC
NC
NC
NC
PD1
PD2
PD3
PD4
NC
NC
NC
V
SS
V
SS
V
SS
V
SS
NC
V
SS
NC
NC
V
NC
SS
3
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TM497FBK32, TM497FBK32S 4194304 BY 32-BIT
TM893GBK32, TM893GBK32S 8388608 BY 32-BIT
EXTENDED DATA OUT DYNAMIC RAM MODULES
SMMS668 – NOVEMBER 1996
Table 1. TM497FBK32/S Connection Table
DATA BLOCK
DQ0–DQ7
RASx
RAS0
RAS0
RAS2
RAS2
CASx
CAS0
CAS1
CAS2
CAS3
DQ8–DQ15
DQ16–DQ23
DQ24–DQ31
Table 2. TM893GBK32/S Connection Table
RASx
DATA BLOCK
CASx
Side 1
RAS0
RAS0
RAS2
RAS2
Side 2
RAS1
RAS1
RAS3
RAS3
DQ0–DQ7
CAS0
CAS1
CAS2
CAS3
DQ8–DQ15
DQ16–DQ23
DQ24–DQ31
single-in-line memory module and components
PC substrate: 1,27 ± 0,1 mm (0.05 inch) nominal thickness; 0.005 inch/inch maximum warpage
Bypass capacitors: Multilayer ceramic
Contact area for TM497FBK32 and TM893GBK32: Nickel plate and gold plate over copper
Contact area for TM497FBK32S and TM893GBK32S: Nickel plate and tin-lead over copper
4
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
11
A0 – A10
RAS0
W
RAS2
CAS2
CAS3
CAS0
CAS1
4 M × 4
A0 – A10
RAS
4 M × 4
A0–A10
RAS
4 M × 4
A0–A10
RAS
4 M × 4
A0–A10
RAS
11
11
11
11
W
W
W
W
CAS
CAS
CAS
CAS
OE
OE
DQ1–
DQ4
OE
DQ1–
DQ4
OE
DQ1–
DQ4
DQ16–
DQ19
DQ24–
DQ27
DQ0 –
DQ3
DQ8–
DQ11
DQ1 –
DQ4
4 M × 4
A0 – A10
RAS
4 M × 4
A0–A10
RAS
4 M × 4
A0–A10
RAS
4 M × 4
A0–A10
RAS
11
11
11
11
W
W
W
W
CAS
CAS
CAS
CAS
OE
OE
DQ1–
DQ4
OE
DQ1–
DQ4
OE
DQ1–
DQ4
DQ20–
DQ23
DQ28–
DQ31
DQ4–
DQ7
DQ12–
DQ15
DQ1 –
DQ4
Figure 1. Functional Block Diagram of TM497FBK32
side 1
11
A0–A10
RAS0
W
CAS0
RAS2
CAS2
CAS3
CAS1
4 M × 4
A0–A10
RAS
W
CAS
4 M × 4
A0–A10
RAS
W
CAS
4 M × 4
A0–A10
RAS
W
CAS
4 M × 4
A0–A10
RAS
W
CAS
11
11
11
11
11
11
OE
OE
OE
OE
DQ1–
DQ4
DQ1–
DQ4
DQ1–
DQ4
DQ1–
DQ4
DQ0–
DQ3
DQ8–
DQ11
DQ16–
DQ19
DQ24–
DQ27
4 M × 4
A0–A10
RAS
W
CAS
4 M × 4
A0–A10
RAS
W
CAS
11 4 M × 4
A0–A10
RAS
11 4 M × 4
A0–A10
RAS
W
CAS
OE
W
CAS
OE
OE
OE
DQ1–
DQ4
DQ1–
DQ4
DQ1–
DQ4
DQ1–
DQ4
DQ4–
DQ7
DQ12–
DQ15
DQ20–
DQ23
DQ28–
DQ31
side 2
11
A0–A10
RAS1
W
RAS3
CAS2
CAS3
CAS0
CAS1
4 M × 4
A0–A10
RAS
W
CAS
4 M × 4
A0–A10
RAS
W
CAS
4 M × 4
A0–A10
RAS
W
CAS
4 M × 4
A0–A10
RAS
W
CAS
11
11
11
11
11
11
OE
OE
OE
OE
DQ1–
DQ4
DQ1–
DQ4
DQ1–
DQ4
DQ1–
DQ4
DQ0–
DQ3
DQ8–
DQ11
DQ16–
DQ19
DQ24–
DQ27
4 M × 4
A0–A10
RAS
W
CAS
4 M × 4
A0–A10
RAS
W
CAS
11 4 M × 4
A0–A10
RAS
11 4 M × 4
A0–A10
RAS
W
CAS
OE
W
CAS
OE
OE
OE
DQ1–
DQ4
DQ1–
DQ4
DQ1–
DQ4
DQ1–
DQ4
DQ4–
DQ7
DQ12–
DQ15
DQ20–
DQ23
DQ28–
DQ31
Figure 2. Functional Block Diagram of TM893GBK32/S
TM497FBK32, TM497FBK32S 4 194 304 BY 32-BIT
TM893GBK32, TM893GBK32S 8 388 608 BY 32-BIT
EXTENDED DATA OUT DYNAMIC RAM MODULES
SMMS668 – NOVEMBER 1996
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 1 V to 7 V
CC
Voltage range on any pin (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 1 V to 7 V
Short-circuit output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 W
Operating free-air temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
A
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 125°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to V
.
SS
recommended operating conditions
MIN NOM
MAX UNIT
V
V
V
Supply voltage
4.5
2.4
– 1
0
5
5.5
6.5
0.8
70
V
V
CC
IH
IL
High-level input voltage
Low-level input voltage (see Note 2)
Operating free-air temperature
V
T
A
°C
NOTE 2: The algebraic convention, where the more negative (less positive) limit is designated as minimum, is used for logic-voltage levels only.
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
’497FBK32-60 ’497FBK32-70 ’497FBK32-80
‡
PARAMETER
UNIT
TEST CONDITIONS
MIN
MAX
MIN
MAX
MIN
MAX
V
V
High-level output voltage
Low-level output voltage
I
I
= – 5 mA
2.4
2.4
2.4
V
V
OH
OH
= 4.2 mA
= 5.5 V,
0.4
0.4
0.4
OL
OL
V
V = 0 V to 6.5 V,
I
CC
All others = 0 V to V
I
I
I
Input current (leakage)
Output current (leakage)
± 10
± 10
± 10
µA
µA
I
CC
V
= 5.5 V,
V
= 0 V to V ,
CC
CC
CAS high
O
± 10
± 10
± 10
O
Read- or write-cycle current
(see Note 3)
V
V
= 5.5 V,
Minimum cycle
880
800
720
mA
CC1
CC
= 2.4 V (TTL),
IH
After one memory cycle,
RAS and CAS high
16
8
16
8
16
8
mA
mA
I
Standby current
CC2
V
= V
– 0.2 V (CMOS),
CC
IH
After one memory cycle,
RAS and CAS high
V
= 5.5 V,
Minimum cycle,
CAS high
RAS low after
CC
Average refresh current
(RAS only or CBR)
(see Note 3)
RAS cycling,
(RAS only);
CAS low (CBR)
I
I
880
560
800
480
720
400
mA
mA
CC3
Average page current
(see Note 4)
V
= 5.5 V,
t
= MIN,
CC
RAS low,
PC
CAS cycling
CC4
‡
For test conditions shown as MIN/MAX, use the appropriate value specified under recommended operating conditions.
NOTES: 3. Measured with a maximum of one address change while RAS = V
IL
4. Measured with a maximum of one address change while CAS = V
IH
7
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TM497FBK32, TM497FBK32S 4 194 304 BY 32-BIT
TM893GBK32, TM893GBK32S 8 388 608 BY 32-BIT
EXTENDED DATA OUT DYNAMIC RAM MODULES
SMMS668 – NOVEMBER 1996
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
’893GBK32-60 ’893GBK32-70 ’893GBK32-80
†
PARAMETER
UNIT
TEST CONDITIONS
MIN
MAX
MIN
MAX
MIN
MAX
V
V
High-level output voltage
Low-level output voltage
I
I
= – 5 mA
2.4
2.4
2.4
V
V
OH
OH
= 4.2 mA
= 5.5 V,
0.4
0.4
0.4
OL
OL
V
V = 0 V to 6.5 V,
I
CC
All others = 0 V to V
I
I
I
Input current (leakage)
Output current (leakage)
± 20
± 20
± 20
µA
µA
I
CC
V
= 5.5 V,
V
= 0 V to V ,
CC
CC
CASx high
O
± 20
± 20
± 20
O
Read- or write-cycle current
(see Note 3)
V
V
= 5.5 V,
Minimum cycle
896
816
736
mA
CC1
CC
= 2.4 V (TTL),
IH
After one memory cycle,
RASx and CASx high
32
16
32
16
32
16
mA
mA
I
Standby current
CC2
V
= V
– 0.2 V (CMOS),
CC
IH
After one memory cycle,
RASx and CASx high
V
= 5.5 V,
RASx cycling,
Minimum cycle
CC
(RASx only);
Average refresh current
(RAS only or CBR)
(see Note 3)
I
I
1760
576
1600
496
1440
416
mA
mA
CC3
CASx low (CBR) CASx high
RASx low after
Average page current
(see Note 4)
V
= 5.5 V,
t
= MIN,
CC
RASx low,
PC
CASx cycling
CC4
†
For test conditions shown as MIN/MAX, use the appropriate value specified under recommended operating conditions.
NOTES: 3. Measured with a maximum of one address change while RAS = V
4. Measured with a maximum of one address change while CAS = V
IL
IH
capacitance over recommended ranges of supply voltage and operating free-air temperature,
f = 1 MHz (see Note 5)
TM497FBK32 TM893GBK32
PARAMETER
UNIT
MIN
MAX
50
33
17
66
9
MIN
MAX
80
C
C
C
C
C
Input capacitance, address inputs
pF
pF
pF
pF
pF
i(A)
Input capacitance, RAS inputs
Input capacitance, CAS inputs
Input capacitance, write-enable input
Output capacitance on DQ pins
28
i(R)
28
i(C)
112
14
i(W)
o(DQ)
NOTE 5:
V
CC
= 5 V ± 0.5 V, and the bias on pins under test is 0 V.
8
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TM497FBK32, TM497FBK32S 4 194 304 BY 32-BIT
TM893GBK32, TM893GBK32S 8 388 608 BY 32-BIT
EXTENDED DATA OUT DYNAMIC RAM MODULES
SMMS668 – NOVEMBER 1996
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature
’497FBK32-60
’893GBK32-60
’497FBK32-70
’893GBK32-70
’497FBK32-80
’893GBK32-80
PARAMETER
UNIT
MIN
MAX
30
MIN
MAX
35
MIN
MAX
40
t
t
t
t
t
t
t
Access time from column address
Access time from CAS low
ns
ns
ns
ns
ns
ns
ns
AA
15
18
20
CAC
CPA
RAC
CLZ
OH
Access time from column precharge
Access time from RAS low
35
40
45
60
70
80
CAS to output in low-impedance state
Output disable time from start of CAS high
Output disable time after CAS high (see Note 6)
0
3
0
0
3
0
0
3
0
15
18
20
OFF
NOTE 6:
t
is specified when the output is no longer driven.
OFF
EDO timing requirements over recommended ranges of supply voltage and operating free-air
temperature
’497FBK32-60
’893GBK32-60
’497FBK32-70
’893GBK32-70
’497FBK32-80
’893GBK32-80
UNIT
MIN
25
80
50
3
MAX
MIN
30
90
55
3
MAX
MIN
35
100
60
3
MAX
t
t
t
t
t
t
t
Cycle time, EDO page mode read or write
Cycle time, EDO read-write
Hold time, CAS after RAS
ns
ns
ns
ns
ns
ns
ns
HPC
PRWC
CSH
DOH
CAS
WPE
CP
Hold time, output after RAS
Pulse duration, CAS
10
5
10 000
12
5
10 000
15
5
10 000
Pulse duration, W (output disable only)
Precharge time, CAS
5
5
5
9
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TM497FBK32, TM497FBK32S 4 194 304 BY 32-BIT
TM893GBK32, TM893GBK32S 8 388 608 BY 32-BIT
EXTENDED DATA OUT DYNAMIC RAM MODULES
SMMS668 – NOVEMBER 1996
timing requirements over recommended ranges of supply voltage and operating free-air
temperature
’497FBK32-60
’893GBK32-60
’497FBK32-70
’893GBK32-70
’497FBK32-80
’893GBK32-80
UNIT
MIN
110
40
MAX
MIN
130
45
MAX
MIN
150
50
MAX
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Cycle time, random read or write (see Note 7)
Cycle time, page-mode read or write (see Notes 7 and 8)
Pulse duration, page-mode, RAS low
Pulse duration, non-page-mode, RAS low
Pulse duration, CAS low
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
RC
PC
60 100 000
70 100 000
80 100 000
RASP
RAS
CAS
CP
60
15
10
40
10
0
10 000
10 000
70
18
10
50
10
0
10 000
10 000
80
20
10
60
10
0
10 000
10 000
Pulse duration, CAS high
Pulse duration, RAS high (precharge)
Pulse duration, W low
RP
WP
Setup time, column address before CAS low
Setup time, row address before RAS low
Setup time, data before CAS low
ASC
ASR
DS
0
0
0
0
0
0
Setup time, W high before CAS low
Setup time, W-low before CAS high
Setup time, W-low before RAS high
Setup time, W-low before CAS low
0
0
0
RCS
CWL
RWL
WCS
WRP
CAH
RHCP
DH
10
10
0
12
12
0
15
15
0
Setup time, W-high before RAS low (CBR refresh only)
Hold time, column address after CAS low
Hold time, RAS high after CAS precharge
Hold time, data after CAS low
10
10
35
10
10
0
10
12
40
12
10
0
10
15
45
15
10
0
Hold time, row address after RAS low
Hold time, W high after CAS high (see Note 9)
Hold time, W high after RAS high (see Note 9)
Hold time, W low after CAS low
RAH
RCH
RRH
WCH
WRH
CHR
CRP
CSH
CSR
RAD
RAL
CAL
RCD
RPC
RSH
REF
T
0
0
0
10
10
10
5
12
10
10
5
15
10
10
5
Hold time, W high after RAS low (CBR refresh only)
Delay time, RAS low to CAS high (CBR refresh only)
Delay time, CAS high to RAS low
Delay time, RAS low to CAS high
50
5
55
5
60
5
Delay time, CAS low to RAS low (CBR refresh only)
Delay time, RAS low to column address (see Note 10)
Delay time, column address to RAS high
Delay time, column address to CAS high
Delay time, RAS low to CAS low (see Note 10)
Delay time, RAS high to CAS low (CBR only)
Delay time, CAS low to RAS high
15
30
30
20
0
30
45
15
35
35
20
0
35
52
15
40
40
20
0
40
60
10
12
15
Refresh time interval
32
30
32
30
32
30
Transition time
3
3
3
NOTES: 7. All cycles assume t = 5 ns.
T
8. To assure t
9. Either t
min, t
should be greater than or equal to t .
CP
PC
or t
ASC
must be satisfied for a read cycle.
RCH
RRH
10. The maximum value is specified only to assure access time.
10
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TM497FBK32, TM497FBK32S 4 194 304 BY 32-BIT
TM893GBK32, TM893GBK32S 8 388 608 BY 32-BIT
EXTENDED DATA OUT DYNAMIC RAM MODULES
SMMS668 – NOVEMBER 1996
MECHANICAL DATA
BK (R-PSIM-N72)
SINGLE-IN-LINE MEMORY MODULE
0.054 (1,37)
0.047 (1,19)
4.255 (108,08)
4.245 (107,82)
0.125 (3,18) TYP
1.005 (25,53)
0.995 (25,27)
0.128 (3,25)
0.120 (3,05)
0.050 (1,27)
0.040 (1,02) TYP
0.010 (0,25) MAX
0.400 (10,16) TYP
0.208 (5,28) MAX
0.360 (9,14) MAX
(For Double-Sided SIMM)
4040197/B 02/96
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
device symbolization
TM497FBK32
-SS
YYMMT
YY
= Year Code
MM
T
= Month Code
= Assembly Site Code
= Speed Code
-SS
NOTE: The location of the part number may vary.
11
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
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