TM893GBK32R-60 [TI]
8MX32 EDO DRAM MODULE, 60ns, SMA72, SIMM-72;
| 型号： | TM893GBK32R-60 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 8MX32 EDO DRAM MODULE, 60ns, SMA72, SIMM-72 动态存储器 内存集成电路 |
| 文件： | 总12页 (文件大小：169K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TM497FBK32R, TM497FBK32G 4194304 BY 32-BIT
TM893GBK32R, TM893GBK32G 8388608 BY 32-BIT
EXTENDED DATA OUT DYNAMIC RAM MODULES
SMMS672 – FEBRUARY 1997
Organization
Presence Detect
– TM497FBK32R/G: 4 194 304 x 32
– TM893GBK32R/G: 8 388 608 x 32
Performance Ranges:
ACCESS ACCESS ACCESS EDO
TIME
TIME
TIME
CYCLE
Single 5-V Power Supply (±10% Tolerance)
t
t
t
t
RAC
AA
CAC
HPC
72-Pin Single-In-Line Memory Module
(SIMM) for Use With Sockets
(MAX)
’497FBK32R/G-50 50 ns
’497FBK32R/G-60 60 ns
’497FBK32R/G-70 70 ns
(MAX)
40 ns
30 ns
35 ns
(MAX)
20 ns
15 ns
18 ns
(MIN)
35 ns
25 ns
30 ns
TM497FBK32R/G – Uses Eight 16M-Bit
Dynamic Random-Access Memories
(DRAMs) in Plastic Small-Outline J-Lead
(SOJ) Packages
’893GBK32R/G-50 50 ns
’893GBK32R/G-60 60 ns
’893GBK32R/G-70 70 ns
40 ns
30 ns
35 ns
20 ns
15 ns
18 ns
35 ns
25 ns
30 ns
TM893GBK32R/G – Uses Sixteen 16M-Bit
DRAMs in Plastic SOJ Packages
Low Power Dissipation
Long Refresh Period
32 ms (2 048 Cycles)
Operating Free-Air Temperature Range
0°C to 70°C
All Inputs, Outputs, Clocks Fully
TTL-Compatible
†
Gold-Tabbed Version Available:
TM497FBK32G, TM893GBK32G
3-State Output
Tin-Lead (Solder-) Tabbed Version
Available: TM497FBK32R, TM893GBK32R
Common CAS Control for Eight Common
Data-In and Data-Out Lines in Four Blocks
Extended Data Out (EDO) Operation With
CAS-Before-RAS (CBR), RAS-Only, and
Hidden Refresh
description
The TM497FBK32R/G, designed as 4 × 4 194304 × 8-bits, is a 16M-byte, 72-pin, leadless, single-in-line
memory module (SIMM). The SIMM is composed of eight (8) TMS417409DJs, 4194304 × 4-bit DRAMs, each
in 24/26-lead, plastic, small-outline J-lead (SOJ) packages mounted on a substrate with decoupling capacitors.
See the TMS417409A data sheet (literature number SMKS893) for timing diagrams.
The TM497FBK32R/G SIMM is available in the single-sided BK leadless module for use with sockets. The
TM497FBK32R/G features RAS access times of 50, 60, and 70 ns. This device is designed for operation from
0°C to 70°C.
The TM893GBK32R/G, designed as 4 × 8 388608 × 8-bits, is a 32M-byte, 72-pin, leadless SIMM. The SIMM
is composed of sixteen TMS417409DJs, 4194304 × 4-bit DRAMs, each in 24/26-lead, plastic, small-outline
J-lead (SOJ) packages mounted on a substrate with decoupling capacitors. See the TMS417409A data sheet
(literature number SMKS893) for timing diagrams.
The TM893GBK32R/G SIMM is available in the double-sided BK leadless module for use with sockets. The
TM893GBK32R/G features RAS access times of 50, 60, and 70 ns. This device is characterized for operation
from 0°C to 70°C.
operation
The TM497FBK32R/G operates as eight TMS417409DJs connected as shown in the functional block diagram
of TM497RBK32R/G and in Table 1. The common I/O feature dictates the use of early write cycles to prevent
contention on D and Q.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
†
Part numbers in this data sheet are for the gold-tabbed version; the information applies to both gold-tabbed and solder-tabbed versions.
Copyright 1997, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TM497FBK32R, TM497FBK32G 4194304 BY 32-BIT
TM893GBK32R, TM893GBK32G 8388608 BY 32-BIT
EXTENDED DATA OUT DYNAMIC RAM MODULES
SMMS672 – FEBRUARY 1997
operation (continued)
The TM893GBK32R/G operates as sixteen TMS417409DJs connected as shown in the functional block
diagram of TM893GBK32R/G and in Table 2. The common I/O feature dictates the use of early write cycles to
prevent contention on D and Q.
refresh
The refresh period is extended to 32 ms and, during this period, each of the 2 048 rows must be strobed with
RAS to retain data. CAS can remain high during the refresh sequence to conserve power.
power up
To achieve proper operation, an initial pause of 200 µs followed by a minimum of eight initialization cycles is
required after full V
(RAS-only or CBR) cycle.
level is achieved. These eight initialization cycles need to include at least one refresh
DD
2
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TM497FBK32R, TM497FBK32G 4194304 BY 32-BIT
TM893GBK32R, TM893GBK32G 8388608 BY 32-BIT
EXTENDED DATA OUT DYNAMIC RAM MODULES
SMMS672 – FEBRUARY 1997
BK SINGLE-IN-LINE PACKAGE
(TOP VIEW)
TM497FBK32R/G
(SIDE VIEW)
TM893GBK32R/G
(SIDE VIEW)
V
1
2
3
4
SS
DQ0
DQ16
DQ1
DQ17
DQ2
5
6
DQ18
DQ3
7
8
DQ19
9
V
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
DD
NC
A0
A1
A2
A3
A4
A5
A6
A10
DQ4
DQ20
DQ5
DQ21
DQ6
DQ22
DQ7
DQ23
A7
NC
V
DD
A8
A9
NC
RAS2
NC
NC
NC
NC
SS
CAS0
CAS2
CAS3
CAS1
RAS0
NC
NC
W
NC
DQ8
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
V
PIN NOMENCLATURE
A0–A10
Address Inputs
Column-Address Strobe
Data In/Data Out
No Connection
Presence Detects
Row-Address Strobe
5-V Supply
CAS0–CAS3
DQ0–DQ31
NC
PD1–PD4
RAS0–RAS3
DQ24
DQ9
V
V
W
DD
SS
DQ25
DQ10
DQ26
DQ11
DQ27
DQ12
DQ28
Ground
Write Enable
PRESENCE DETECT
V
DD
DQ29
DQ13
DQ30
DQ14
DQ31
DQ15
NC
SIGNAL
(PIN)
PD1
(67)
PD2
(68)
PD3
(69)
PD4
(70)
70 ns
60 ns
50 ns
70 ns
60 ns
50 ns
V
V
V
NC
NC
NC
V
NC
NC
SS
SS
SS
SS
TM497FBK32R/G
TM893GBK32R/G
NC
NC
V
SS
PD1
PD2
PD3
PD4
NC
NC
NC
V
SS
V
SS
V
SS
V
SS
NC
NC
NC
NC
V
NC
V
SS
SS
3
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TM497FBK32R, TM497FBK32G 4194304 BY 32-BIT
TM893GBK32R, TM893GBK32G 8388608 BY 32-BIT
EXTENDED DATA OUT DYNAMIC RAM MODULES
SMMS672 – FEBRUARY 1997
Table 1. TM497FBK32R/G Connection Table
DATA BLOCK
DQ0–DQ7
RASx
RAS0
RAS0
RAS2
RAS2
CASx
CAS0
CAS1
CAS2
CAS3
DQ8–DQ15
DQ16–DQ23
DQ24–DQ31
Table 2. TM893GBK32R/G Connection Table
RASx
DATA BLOCK
CASx
Side 1
RAS0
RAS0
RAS2
RAS2
Side 2
RAS1
RAS1
RAS3
RAS3
DQ0–DQ7
CAS0
CAS1
CAS2
CAS3
DQ8–DQ15
DQ16–DQ23
DQ24–DQ31
single-in-line memory module and components
PC substrate: 1,27 ± 0,1 mm (0.05 inch) nominal thickness; 0.005 inch/inch maximum warpage
Bypass capacitors: Multilayer ceramic
Contact area for TM497FBK32G and TM893GBK32G: Nickel plate and gold plate over copper
Contact area for TM497FBK32R and TM893GBK32R: Nickel plate and tin-lead over copper
4
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TM497FBK32R, TM497FBK32G 4 194 304 BY 32-BIT
TM893GBK32R, TM893GBK32G 8 388 608 BY 32-BIT
EXTENDED DATA OUT DYNAMIC RAM MODULES
SMMS672 – FEBRUARY 1997
•
5
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443
Template Release Date: 7–11–94
TM497FBK32R, TM497FBK32G 4 194 304 BY 32-BIT
TM893GBK32R, TM893GBK32G 8 388 608 BY 32-BIT
EXTENDED DATA OUT DYNAMIC RAM MODULES
SMMS672 – FEBRUARY 1997
6
•
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443
TM497FBK32R, TM497FBK32G 4 194 304 BY 32-BIT
TM893GBK32R, TM893GBK32G 8 388 608 BY 32-BIT
EXTENDED DATA OUT DYNAMIC RAM MODULES
SMMS672 – FEBRUARY 1997
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 1 V to 7 V
DD
Voltage range on any pin (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 1 V to 7 V
Short-circuit output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 W
Operating free-air temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
A
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 125°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to V
.
SS
recommended operating conditions
MIN NOM
MAX UNIT
V
V
V
Supply voltage
4.5
2.4
– 1
0
5
5.5
6.5
0.8
70
V
V
DD
IH
IL
High-level input voltage
Low-level input voltage (see Note 2)
Operating free-air temperature
V
T
A
°C
NOTE 2: The algebraic convention, where the more negative (less positive) limit is designated as minimum, is used for logic-voltage levels only.
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
’497FBK32-50 ’497FBK32-60 ’497FBK32-70
‡
PARAMETER
UNIT
TEST CONDITIONS
MIN
MAX
MIN
MAX
MIN
MAX
V
V
High-level output voltage
Low-level output voltage
I
I
= – 5 mA
2.4
2.4
2.4
V
V
OH
OH
= 4.2 mA
= 5.5 V,
0.4
0.4
0.4
OL
OL
V
V = 0 V to 6.5 V,
I
DD
All others = 0 V to V
I
I
I
Input current (leakage)
Output current (leakage)
± 10
± 10
± 10
µA
µA
I
DD
V
= 5.5 V,
V
= 0 V to V ,
DD
DD
CAS high
O
± 10
± 10
± 10
O
Average read- or write-cycle
current (see Note 3)
V
V
= 5.5 V,
Minimum cycle
960
880
800
mA
CC1
DD
= 2.4 V (TTL),
IH
After one memory cycle,
RAS and CAS high
16
8
16
8
16
8
mA
mA
I
Average standby current
CC2
V
= V
– 0.2 V (CMOS),
DD
IH
After one memory cycle,
RAS and CAS high
V
= 5.5 V,
Minimum cycle,
CAS high
RAS low after
DD
Average refresh current
(RAS only or CBR)
(see Note 3)
RAS cycling,
(RAS only);
CAS low (CBR)
I
I
960
800
880
720
800
640
mA
mA
CC3
Average EDO
(see Note 4)
V
= 5.5 V,
t
= MIN,
DD
RAS low,
PC
CAS cycling
CC4
‡
For test conditions shown as MIN/MAX, use the appropriate value specified under recommended operating conditions.
NOTES: 3. Measured with a maximum of one address change while RAS = V
IL
4. Measured with a maximum of one address change while CAS = V
IH
7
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TM497FBK32R, TM497FBK32G 4 194 304 BY 32-BIT
TM893GBK32R, TM893GBK32G 8 388 608 BY 32-BIT
EXTENDED DATA OUT DYNAMIC RAM MODULES
SMMS672 – FEBRUARY 1997
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
’893GBK32-50 ’893GBK32-60 ’893GBK32-70
†
PARAMETER
UNIT
TEST CONDITIONS
MIN
MAX
MIN
MAX
MIN
MAX
V
V
High-level output voltage
Low-level output voltage
I
I
= – 5 mA
2.4
2.4
2.4
V
V
OH
OH
= 4.2 mA
= 5.5 V,
0.4
0.4
0.4
OL
OL
V
V = 0 V to 6.5 V,
I
DD
All others = 0 V to V
I
I
I
Input current (leakage)
Output current (leakage)
± 20
± 20
± 20
µA
µA
I
DD
V
= 5.5 V,
V
= 0 V to V ,
DD
DD
CASx high
O
± 20
± 20
± 20
O
Average read- or write-cycle
current (see Note 3)
V
V
= 5.5 V,
Minimum cycle
976
896
816
mA
CC1
DD
= 2.4 V (TTL),
IH
After one memory cycle,
RASx and CASx high
32
16
32
16
32
16
mA
mA
I
Average standby current
CC2
V
= V
– 0.2 V (CMOS),
DD
IH
After one memory cycle,
RASx and CASx high
V
= 5.5 V,
RASx cycling,
Minimum cycle
DD
(RASx only);
Average refresh current
(RAS only or CBR)
(see Note 3)
I
I
1920
1600
1760
1440
1600
1280
mA
mA
CC3
CASx low (CBR) CASx high
RASx low after
Average EDO
(see Note 4)
V
= 5.5 V,
t
= MIN,
DD
RASx low,
PC
CASx cycling
CC4
†
For test conditions shown as MIN/MAX, use the appropriate value specified under recommended operating conditions.
NOTES: 3. Measured with a maximum of one address change while RAS = V
4. Measured with a maximum of one address change while CAS = V
IL
IH
capacitance over recommended ranges of supply voltage and operating free-air temperature,
f = 1 MHz (see Note 5)
TM497FBK32R/G TM893GBK32R/G
PARAMETER
UNIT
MIN
MAX
50
28
17
66
9
MIN
MAX
80
C
C
C
C
C
Input capacitance, address inputs
pF
pF
pF
pF
pF
i(A)
Input capacitance, RAS inputs
Input capacitance, CAS inputs
Input capacitance, write-enable input
Output capacitance on DQ pins
33
i(R)
28
i(C)
112
14
i(W)
o(DQ)
NOTE 5:
V
DD
= 5 V ± 0.5 V, and the bias on pins under test is 0 V.
8
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TM497FBK32R, TM497FBK32G 4 194 304 BY 32-BIT
TM893GBK32R, TM893GBK32G 8 388 608 BY 32-BIT
EXTENDED DATA OUT DYNAMIC RAM MODULES
SMMS672 – FEBRUARY 1997
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (see Note 6)
’497FBK32-60
’893GBK32-50 ’893GBK32-60 ’893GBK32-70
’497FBK32-50
’497FBK32-70
PARAMETER
UNIT
MIN
MAX
25
MIN
MAX
30
MIN
MAX
35
t
t
t
t
t
t
t
Access time from column address
Access time from CAS low
ns
ns
ns
ns
ns
ns
ns
AA
13
15
18
CAC
CPA
RAC
CLZ
OH
Access time from column precharge
Access time from RAS low
28
35
40
50
60
70
CAS to output in low-impedance state
Output disable time from start of CAS high
Output disable time after CAS high (see Note 6)
0
3
0
0
3
0
0
3
0
13
15
18
OFF
NOTES: 6. With ac parameters, it is assumed that t = 2 ns.
T
7.
t
is specified when the output is no longer driven.
OFF
EDO timing requirements over recommended ranges of supply voltage and operating free-air
temperature
’497FBK32-50
’893GBK32-50
’497FBK32-60
’893GBK32-60
’497FBK32-70
’893GBK32-70
UNIT
MIN
20
57
40
5
MAX
MIN
25
68
48
5
MAX
MIN
30
78
58
5
MAX
t
t
t
t
t
t
t
Cycle time, EDO page mode read or write
Cycle time, EDO read-write
Hold time, CAS after RAS
ns
ns
ns
ns
ns
ns
ns
HPC
PRWC
CSH
DOH
CAS
WPE
CP
Hold time, output after RAS
Pulse duration, CAS
8
10 000
10
7
10 000
12
7
10 000
Pulse duration, W (output disable only)
Precharge time, CAS
7
8
10
10
NOTE 6: With ac parameters, it is assumed that t = 2 ns.
T
9
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TM497FBK32R, TM497FBK32G 4 194 304 BY 32-BIT
TM893GBK32R, TM893GBK32G 8 388 608 BY 32-BIT
EXTENDED DATA OUT DYNAMIC RAM MODULES
SMMS672 – FEBRUARY 1997
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (see Note 6)
’497FBK32-50
’893GBK32-50
’497FBK32-60
’893GBK32-60
’497FBK32-70
’893GBK32-70
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Cycle time, random read or write (see Note 8)
Pulse duration, page-mode, RAS low (see Note 8)
Pulse duration, non-page-mode, RAS low (see Note 8)
Pulse duration, CAS low
84
104
124
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
RC
50 100 000
60 100 000
70 100 000
RASP
RAS
CAS
CP
50
20
8
10 000
10 000
60
15
10
40
10
0
10 000
10 000
70
18
10
50
10
0
10 000
10 000
Pulse duration, CAS high
Pulse duration, RAS high (precharge)
Pulse duration, W low
30
8
RP
WP
Setup time, column address before CAS low
Setup time, row address before RAS low
Setup time, data before CAS low (see Note 9)
Setup time, W high before CAS low
0
ASC
ASR
DS
0
0
0
0
0
0
0
0
0
RCS
CWL
RWL
WCS
WRP
CAH
RHCP
DH
Setup time, W-low before CAS high
8
10
10
0
12
12
0
Setup time, W-low before RAS high
8
Setup time, W-low before CAS low
0
Setup time, W-high before RAS low (CBR refresh only)
Hold time, column address after CAS low
Hold time, RAS high after CAS precharge
Hold time, data after CAS low (see Note 9)
Hold time, row address after RAS low
Hold time, W high after CAS high (see Note 10)
Hold time, W high after RAS high (see Note 10)
Hold time, W low after CAS low (early-write only)
Hold time, W high after RAS low (CBR refresh only)
Delay time, RAS low to CAS high (CBR refresh only)
Delay time, CAS high to RAS low
10
8
10
10
35
10
10
0
10
12
40
12
10
0
28
8
8
RAH
RCH
RRH
WCH
WRH
CHR
CRP
CSH
CSR
RAD
RAL
CAL
RCD
RPC
RSH
REF
T
0
0
0
0
10
10
8
10
10
10
5
12
10
10
5
5
Delay time, RAS low to CAS high
40
5
48
5
58
5
Delay time, CAS low to RAS low (CBR refresh only)
Delay time, RAS low to column address (see Note 11)
Delay time, column address to RAS high
Delay time, column address to CAS high
Delay time, RAS low to CAS low (see Note 11)
Delay time, RAS high to CAS low (CBR only)
Delay time, CAS low to RAS high
10
25
18
20
5
25
37
12
30
20
20
5
30
45
12
35
25
20
5
35
52
8
10
12
Refresh time interval
32
30
32
30
32
30
Transition time
2
2
2
NOTES: 6. With ac parameters, it is assumed that t = 2 ns.
T
8. In a read-write cycle, t
and t must be observed.
RWD
RWL
9. Referenced to the later of CAS or W in write operations.
10. Either t or t must be satisfied for a read cycle.
RRH
RCH
11. The maximum value is specified only to assure access time.
10
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TM497FBK32R, TM497FBK32G 4 194 304 BY 32-BIT
TM893GBK32R, TM893GBK32G 8 388 608 BY 32-BIT
EXTENDED DATA OUT DYNAMIC RAM MODULES
SMMS672 – FEBRUARY 1997
MECHANICAL DATA
BK (R-PSIM-N72)
SINGLE-IN-LINE MEMORY MODULE
0.054 (1,37)
0.047 (1,19)
4.255 (108,08)
4.245 (107,82)
0.125 (3,18) TYP
1.005 (25,53)
0.995 (25,27)
0.128 (3,25)
0.120 (3,05)
0.050 (1,27)
0.040 (1,02) TYP
0.010 (0,25) MAX
0.400 (10,16) TYP
0.208 (5,28) MAX
0.360 (9,14) MAX
(For Double-Sided SIMM)
4040197/B 02/96
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
device symbolization
TM497FBK32R
-SS
YYMMT
YY
= Year Code
MM
T
= Month Code
= Assembly Site Code
= Speed Code
-SS
NOTE: The location of the part number may vary.
11
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