TM893NBM36A-80 [TI]
8MX36 FAST PAGE DRAM MODULE, 80ns, SMA72, SIMM-72;
| 型号： | TM893NBM36A-80 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 8MX36 FAST PAGE DRAM MODULE, 80ns, SMA72, SIMM-72 动态存储器 内存集成电路 |
| 文件： | 总11页 (文件大小：166K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TM497MBM36A, TM497MBM36Q 4194304 BY 36-BIT
TM893NBM36A, TM893NBM36Q 8388608 BY 36-BIT
DYNAMIC RANDOM-ACCESS MEMORY MODULES
SMMS653B – MAY 1995 – REVISED JULY 1995
Organization
Present Detect
TM497MBM36A . . . 4194304 × 36
TM893NBM36A . . . 8388608 × 36
Operating Free-Air Temperature Range
0°C to 70°C
Single 5-V Power Supply (±10% Tolerance)
Performance Ranges:
ACCESS ACCESS ACCESS READ
72-Pin Leadless Single In-Line Memory
Module (SIMM) for Use With Sockets
TIME
TIME
TIME
OR
t
t
t
WRITE
CYCLE
RAC
AA
CAC
TM497MBM36A – Utilizes Eight 16-Megabit
and Four 4-Megabit DRAMs in Plastic
Small-Outline J-Lead (SOJ) Packages
(MAX)
’497MBM36A-60 60 ns
’497MBM36A-70 70 ns
’497MBM36A-80 80 ns
(MAX)
30 ns
35 ns
40 ns
(MAX)
15 ns
18 ns
20 ns
(MIN)
110 ns
130 ns
150 ns
TM893NBM36A – Utilizes Sixteen
16-Megabit and Eight 4-Megabit DRAMs in
Plastic Small-Outline J-Lead (SOJ)
Packages
’893NBM36A-60 60 ns
’893NBM36A-70 70 ns
’893NBM36A-80 80 ns
30 ns
35 ns
40 ns
15 ns
18 ns
20 ns
110 ns
130 ns
150 ns
†
Gold-Tabbed Versions Available:
TM497MBM36A
Long Refresh Period
32 ms (2048 Cycles)
TM893NBM36A
All Inputs, Outputs, Clocks Fully
TTL-Compatible
Tin-Lead (Solder)-Tabbed Versions
Available:
3-State Output
TM497MBM36Q
Common CAS Control for Nine Common
Data-In and Data-Out Lines in Four Blocks
TM893NBM36Q
Enhanced Page-Mode Operation With
CAS-Before-RAS (CBR), RAS-Only, and
Hidden Refresh
description
TM497MBM36A
The TM497MBM36A is a 16-megabyte dynamic random-access memory (DRAM) organized as four times
4194304 × 9 (bit 9 is generally used for parity) in a 72-pin leadless single in-line memory module (SIMM). The
SIMM is composed of eight TMS417400DJ 4194304 × 4-bit DRAMs, each in a 24/26-lead plastic small-outline
J-lead (SOJ) package, and four TMS44100DJ 4194304 × 1-bit DRAMs, each in a 20/26-lead plastic SOJ
package mounted on a substrate with decoupling capacitors. The TMS417400DJ and TMS44100DJ are
described in the TMS417400 and TMS44100 data sheets, respectively. The TM497MBM36A SIMM is available
in the single-sided, BM leadless module for use with sockets.
TM893NBM36A
The TM893NBM36A is a 32-megabyte DRAM organized as four times 8388608 × 9 (bit 9 is generally used for
parity) in a 72-pin leadless SIMM. The SIMM is composed of sixteen TMS417400DJ 4194304 × 4-bit DRAMs,
each in a 24/26-lead plastic SOJ package, and eight TMS44100DJ 4194304 × 1-bit DRAMs, each in a
20/26-lead plastic SOJ package, mounted on a substrate with decoupling capacitors. The TMS417400DJ and
TMS44100DJ are described in the TMS417400 and TMS44100 data sheets, respectively. The TM893NBM36A
SIMM is available in the double-sided, BM leadless module for use with sockets.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
†
Part numbers in this data sheet refer only to the gold-tabbed version; the information applies to both gold-tabbed and solder-tabbed versions.
Copyright 1995, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TM497MBM36A, TM497MBM36Q 4194304 BY 36-BIT
TM893NBM36A, TM893NBM36Q 8388608 BY 36-BIT
DYNAMIC RANDOM-ACCESS MEMORY MODULES
SMMS653B – MAY 1995 – REVISED JULY 1995
operation
TM497MBM36A
The TM497MBM36A operates as eight TMS417400DJs and four TMS44100DJs connected as shown in the
functionalblockdiagramandinTable1. ThecommonI/Ofeaturedictatestheuseofearly-writecyclestoprevent
contention on D and Q.
TM893NBM36A
The TM893NBM36A operates as sixteen TMS417400DJs and eight TMS44100DJs connected as shown in the
functionalblockdiagramandinTable1. ThecommonI/Ofeaturedictatestheuseofearly-writecyclestoprevent
contention on D and Q.
refresh
The refresh period is extended to 32 ms, and, during this period, each of the 2048 rows must be strobed with
RAS in order to retain data. Address line A10 must be used as the most significant refresh address line (lowest
frequency) to ensure correct refresh for both TMS417400 and TMS44100. Address lines A0–A9 must be
refreshed every 16 ms as required by the TMS44100 DRAM. To conserve power, CAS can remain high during
the refresh sequence.
power up
To achieve proper operation, an initial pause of 200 µs followed by a minimum of eight initialization cycles is
required after full V
(RAS-only or CBR-refresh) cycle.
level is achieved. These eight initialization cycles must include at least one refresh
CC
Table 1. Connection Table
RASx
DATA BLOCK
CASx
CAS0
CAS1
CAS2
CAS3
†
SIDE 1
SIDE 2
DQ0–DQ7
DQ8
RAS0
RAS1
DQ9–DQ16
DQ17
RAS0
RAS2
RAS1
RAS3
RAS3
DQ18–DQ25
DQ26
DQ27–DQ34
DQ35
RAS2
†
Side 2 applies to the TM893NBM36A.
single in-line memory module and components
PC substrate: 1, 27 ± 0,1 mm (0.05 inch) nominal thickness; inch/inch maximum warpage
Bypass capacitors: Multilayer ceramic
Contact area for TM497MBM36A and TM893NBM36A: Nickel plate and gold plate over copper
Contact area for TM497MBM36Q and TM893NBM36Q: Nickel plate and tin/lead over copper
2
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TM497MBM36A, TM497MBM36Q 4194304 BY 36-BIT
TM893NBM36A, TM893NBM36Q 8388608 BY 36-BIT
DYNAMIC RANDOM-ACCESS MEMORY MODULES
SMMS653B – MAY 1995 – REVISED JULY 1995
TM497MBM36A
(SIDE VIEW)
TM893NBM36A
(SIDE VIEW)
BM SINGLE IN-LINE PACKAGE
(TOP VIEW)
fRnrce
V
1
2
3
4
SS
DQ0
DQ18
DQ1
DQ19
DQ2
5
6
DQ20
DQ3
7
8
DQ21
9
V
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
CC
NC
A0
A1
A2
A3
A4
A5
A6
A10
DQ4
DQ22
DQ5
DQ23
DQ6
DQ24
DQ7
DQ25
A7
NC
V
CC
A8
A9
RAS3
RAS2
DQ26
DQ8
DQ17
DQ35
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
V
SS
PIN NOMENCLATURE
CAS0
CAS2
CAS3
CAS1
RAS0
RAS1
NC
W
NC
DQ9
DQ27
DQ10
DQ28
DQ11
DQ29
DQ12
DQ30
DQ13
DQ31
A0–A10
Address Inputs
CAS0–CAS3
DQ0–DQ35
NC
PD1–PD4
RAS0–RAS3
Column-Address Strobe
Data In/Data Out
No Connection
Presence Detects
Row-Address Strobe
5-V Supply
V
V
W
CC
SS
Ground
Write Enable
V
CC
PRESENCE DETECT
DQ32
DQ14
DQ33
DQ15
DQ34
DQ16
NC
SIGNAL
(PIN)
PD1
(67)
PD2
(68)
PD3
(69)
PD4
(70)
80 ns
70 ns
60 ns
80 ns
70 ns
60 ns
V
V
V
NC
NC
NC
NC
V
SS
SS
SS
SS
TM497MBM36A
TM893NBM36A
V
SS
NC
NC
PD1
PD2
PD3
PD4
NC
NC
NC
NC
NC
V
SS
V
SS
NC
NC
V
V
SS
NC
SS
SS
V
SS
V
NC
3
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
functional block diagram (TM497MBM36A and TM893NBM36A, side 1)
11
A0–A10
RAS0
W
RAS2
CAS2
CAS3
CAS0
CAS1
4M × 4
A0–A10
RAS
4M × 4
A0–A10
RAS
4M × 4
A0–A10
RAS
4M × 4
A0–A10
RAS
11
11
11
11
W
W
W
W
CAS
CAS
CAS
CAS
OE
DQ1–
DQ4
OE
DQ1–
DQ4
OE
DQ1–
DQ4
OE
DQ1–
DQ4
DQ18–
DQ21
DQ27–
DQ30
DQ0–
DQ3
DQ9–
DQ12
4M × 4
A0–A10
RAS
4M × 4
A0–A10
RAS
4M × 4
A0–A10
RAS
4M × 4
A0–A10
RAS
11
11
11
11
W
W
W
W
CAS
CAS
CAS
CAS
OE
DQ1–
DQ4
OE
DQ1–
DQ4
OE
DQ1–
DQ4
OE
DQ1–
DQ4
DQ22–
DQ25
DQ31–
DQ34
DQ4–
DQ7
DQ13–
DQ16
4M × 1
A0–A10
RAS
W
CAS
4M × 1
A0–A10
RAS
W
CAS
4M × 1
A0–A10
RAS
W
CAS
4M × 1
A0–A10
RAS
W
CAS
11
11
11
11
D
Q
DQ26
D
Q
DQ35
DQ8
DQ17
D
Q
D
Q
functional block diagram (TM893NBM36A, side 2)
11
A0–A10
RAS1
W
RAS3
CAS2
CAS3
CAS0
CAS1
4M × 4
A0–A10
RAS
4M × 4
A0–A10
RAS
4M × 4
A0–A10
RAS
4M × 4
A0–A10
RAS
11
11
11
11
W
W
W
W
CAS
CAS
CAS
CAS
OE
DQ1–
DQ4
OE
DQ1–
DQ4
OE
DQ1–
DQ4
OE
DQ1–
DQ4
DQ18–
DQ21
DQ27–
DQ30
DQ0–
DQ3
DQ9–
DQ12
4M × 4
A0–A10
RAS
4M × 4
A0–A10
RAS
4M × 4
A0–A10
RAS
4M × 4
A0–A10
RAS
11
11
11
11
W
W
W
W
CAS
CAS
CAS
CAS
OE
DQ1–
DQ4
OE
DQ1–
DQ4
OE
DQ1–
DQ4
OE
DQ1–
DQ4
DQ22–
DQ25
DQ31–
DQ34
DQ4–
DQ7
DQ13–
DQ16
4M × 1
A0–A10
RAS
W
CAS
4M × 1
A0–A10
RAS
W
CAS
4M × 1
A0–A10
RAS
W
CAS
4M × 1
A0–A10
RAS
W
CAS
11
11
11
11
D
Q
DQ26
D
Q
DQ35
DQ8
DQ17
D
Q
D
Q
TM497MBM36A, TM497MBM36Q 4194304 BY 36-BIT
TM893NBM36A, TM893NBM36Q 8388608 BY 36-BIT
DYNAMIC RANDOM-ACCESS MEMORY MODULES
SMMS653B – MAY 1995 – REVISED JULY 1995
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 1 V to 7 V
CC
Voltage range on any pin (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 1 V to 7 V
Short-circuit output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Power dissipation: TM497MBM36A, TM497MBM36Q . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 W
TM893NBM36A, TM893NBM36Q . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 W
Operating free-air temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
A
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 125°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to V
.
SS
recommended operating conditions
MIN NOM
MAX UNIT
V
V
V
Supply voltage
4.5
2.4
– 1
0
5
5.5
6.5
0.8
70
V
V
CC
IH
IL
High-level input voltage
Low-level input voltage (see Note 2)
Operating free-air temperature
V
T
A
°C
NOTE 2: The algebraic convention, where the more negative (less positive) limit is designated as minimum, is used for logic-voltage levels only.
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
’497MBM36A-60 ’497MBM36A-70 ’497MBM36A-80
‡
PARAMETER
UNIT
TEST CONDITIONS
= – 5 mA
MIN
MAX
MIN
MAX
MIN
MAX
High-level output
voltage
V
V
I
I
2.4
2.4
2.4
V
V
OH
OH
Low-level output
voltage
= 4.2 mA
= 5.5 V,
0.4
± 10
± 10
1300
0.4
± 10
± 10
1160
0.4
± 10
± 10
1040
OL
OL
V
V = 0 V to 6.5 V,
I
Input current
(leakage)
CC
I
I
I
µA
µA
mA
I
All other pins = 0 V to V
CC
= 0 V to V
V
= 5.5 V,
CC
CAS high
V
,
CC
Output current
(leakage)
O
O
Read- or write-cycle
current
V
V
= 5.5 V,
Minimum cycle
CC1
CC
= 2.4 V (TTL),
After 1 memory cycle,
RAS and CAS high
IH
24
12
24
12
24
12
mA
mA
I
Standby current
CC2
V
= V
– 0.2 V (CMOS),
CC
IH
After 1 memory cycle,
RAS and CAS high
V
= 5.5 V,
Minimum cycle,
Average refresh
current
CC
RAS cycling,
I
I
1300
920
1160
800
1040
680
mA
mA
CC3
(RAS-only refresh
or CBR)
CAS high (RAS-only refresh);
RAS low after CAS low (CBR)
V
= 5.5 V,
t
= MIN,
Average page
current
CC
RAS low,
PC
CAS cycling
CC4
‡
For test conditions shown as MIN/MAX, use the appropriate value specified in the timing requirements.
6
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TM497MBM36A, TM497MBM36Q 4194304 BY 36-BIT
TM893NBM36A, TM893NBM36Q 8388608 BY 36-BIT
DYNAMIC RANDOM-ACCESS MEMORY MODULES
SMMS653B – MAY 1995 – REVISED JULY 1995
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
’893NBM36A-60 ’893NBM36A-70 ’893NBM36A-80
†
PARAMETER
UNIT
TEST CONDITIONS
= – 5 mA
MIN
MAX
MIN
MAX
MIN
MAX
High-level output
voltage
V
V
I
I
2.4
2.4
2.4
V
V
OH
OH
Low-level output
voltage
= 4.2 mA
= 5.5 V,
0.4
± 20
± 20
0.4
± 20
± 20
0.4
± 20
± 20
OL
OL
V
V = 0 V to 6.5 V,
I
Input current
(leakage)
CC
I
I
µA
µA
All other pins = 0 V to V
CC
= 0 V to V
V
= 5.5 V,
CC
CAS high
V
,
CC
Output current
(leakage)
O
I
O
Read- or write-cycle
current (one RAS
active, see Note 3)
I
V
V
= 5.5 V,
Minimum cycle
1324
48
1184
48
1064
48
mA
mA
mA
CC1
CC
= 2.4 V (TTL),
IH
After 1 memory cycle,
RAS and CAS high
I
Standby current
CC2
V
IH
= V
– 0.2 V (CMOS),
CC
After 1 memory cycle,
RAS and CAS high
24
24
24
V
= 5.5 V,
Minimum cycle,
Average refresh
current
CC
RAS cycling,
I
I
1324
944
1184
824
1064
704
mA
mA
CC3
(RAS only or CBR,
see Note 3)
CAS high (RAS-only refresh);
RAS low after CAS low (CBR)
Average page
current
(one RAS active,
see Note 4)
V
= 5.5 V,
t
= MIN,
CC
RAS low,
PC
CAS cycling
CC4
†
For test conditions shown as MIN/MAX, use the appropriate value specified in the timing requirements.
NOTES: 3. Measured with a maximum of one address change while RAS = V
IL
4. Measured with a maximum of one address change while CAS = V
IH
capacitance over recommended supply voltage range and operating free-air temperature range,
f = 1 MHz (see Note 5)
’497MBM36A ’893NMB36A
PARAMETER
UNIT
MIN
MAX
60
42
21
84
7
MIN
MAX
120
42
C
C
C
C
Input capacitance, A0–A10
Input capacitance, RAS inputs
Input capacitance, CAS inputs
pF
pF
pF
pF
pF
pF
i(A)
i(R)
i(C)
i(W)
42
Input capacitance, write-enable input
168
14
DQ pins
C
Output capacitance
o(DQ)
Parity pins
12
24
NOTE 5:
V
CC
= 5 V ± 0.5 V, and the bias on pins under test is 0 V.
7
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TM497MBM36A, TM497MBM36Q 4194304 BY 36-BIT
TM893NBM36A, TM893NBM36Q 8388608 BY 36-BIT
DYNAMIC RANDOM-ACCESS MEMORY MODULES
SMMS653B – MAY 1995 – REVISED JULY 1995
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature
’497MBM36A-60 ’497MBM36A-70 ’497MBM36A-80
’893NBM36A-60 ’893NBM36A-70 ’893NBM36A-80
PARAMETER
UNIT
MIN
MAX
30
MIN
MAX
35
MIN
MAX
40
t
t
t
t
t
t
t
Access time from column address
Access time from CAS low
ns
ns
ns
ns
ns
ns
ns
AA
15
18
20
CAC
RAC
CPA
CLZ
OFF
OH
Access time from RAS low
60
70
80
Access time from column precharge
CAS low to output in the low-impedance state
Output disable time after CAS high (see Note 6)
Output disable time, start of CAS high
35
40
45
0
0
3
0
0
3
0
0
3
15
18
20
NOTE 6:
t
is specified when the output is no longer driven.
OFF
timing requirements over recommended ranges of supply voltage and operating free-air
temperature
’497MBM36A-60 ’497MBM36A-70 ’497MBM36A-80
’893NBM36A-60 ’893NBM36A-70 ’893NBM36A-80
UNIT
MIN
110
40
MAX
MIN
130
45
MAX
MIN
150
50
MAX
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Cycle time, random read or write (see Note 7)
Cycle time, page-mode read or write (see Notes 7 and 8)
Pulse duration, page mode, RAS low
Pulse duration, nonpage mode, RAS low
Pulse duration, CAS low
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
RC
PC
60 100 000
70 100 000
80 100 000
RASP
RAS
CAS
CP
60
15
10
40
10
0
10 000
10 000
70
18
10
50
10
0
10 000
10 000
80
20
10
60
10
0
10 000
10 000
Pulse duration, CAS high
Pulse duration, RAS high (precharge)
Pulse duration, W low
RP
WP
Setup time, column address before CAS low
Setup time, row address before RAS low
Setup time, data before CAS low
ASC
ASR
DS
0
0
0
0
0
0
Setup time, W high before CAS low
Setup time, W low before CAS high
Setup time, W low before RAS high
Setup time, W low before CAS low
0
0
0
RCS
CWL
RWL
WCS
WRP
CAH
RHCP
DH
15
15
0
18
18
0
20
20
0
Setup time, W high before RAS low (CBR refresh only)
Hold time, column address after CAS low
Hold time, RAS high from CAS precharge
Hold time, data after CAS low
10
10
35
10
10
0
10
15
40
15
10
0
10
15
45
15
10
0
Hold time, row address after RAS low
Hold time, W high after CAS high (see Note 9)
Hold time, W high after RAS high (see Note 9)
Hold time, W low after CAS low
RAH
RCH
RRH
WCH
WRH
0
0
0
10
10
15
10
15
10
Hold time, W high after RAS low (CBR refresh only)
NOTES: 7. All cycle times assume t = 5 ns.
T
8. To assure t
min, t
should be ≥ t .
CP
PC
or t
ASC
must be satisfied for a read cycle.
RCH
9. Either t
RRH
8
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TM497MBM36A, TM497MBM36Q 4194304 BY 36-BIT
TM893NBM36A, TM893NBM36Q 8388608 BY 36-BIT
DYNAMIC RANDOM-ACCESS MEMORY MODULES
SMMS653B – MAY 1995 – REVISED JULY 1995
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (continued)
’497MBM36A-60 ’497MBM36A-70 ’497MBM36A-80
’893NBM36A-60 ’893NBM36A-70 ’893NBM36A-80
UNIT
MIN
10
5
MAX
MIN
10
5
MAX
MIN
10
5
MAX
t
t
t
t
t
t
t
t
t
t
t
t
Delay time, RAS low to CAS high (CBR refresh only)
Delay time, CAS high to RAS low
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
CHR
CRP
CSH
CSR
RAD
RAL
CAL
RCD
RPC
RSH
REF
T
Delay time, RAS low to CAS high
60
5
70
5
80
5
Delay time, CAS low to RAS low (CBR refresh only)
Delay time, RAS low to column address (see Note 10)
Delay time, column address to RAS high
Delay time, column address to CAS high
Delay time, RAS low to CAS low (see Note 10)
Delay time, RAS high to CAS low (CBR refresh only)
Delay time, CAS low to RAS high
15
30
30
20
0
30
45
15
35
35
20
0
35
52
15
40
40
20
0
40
60
15
18
20
Refresh time interval
32
30
32
30
32
30
Transition time
3
3
3
NOTE 10: The maximum value is specified only to assure access time.
9
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TM497MBM36A, TM497MBM36Q 4194304 BY 36-BIT
TM893NBM36A, TM893NBM36Q 8388608 BY 36-BIT
DYNAMIC RANDOM-ACCESS MEMORY MODULES
SMMS653B – MAY 1995 – REVISED JULY 1995
MECHANICAL DATA
BM (R-PSIM-N72)
SINGLE/DOUBLE-SIDED IN-LINE MEMORY MODULE
4.255 (108,08)
4.245 (107,82)
0.054 (1,37)
0.047 (1,19)
0.125 (3,18) TYP
1.305 (33,15)
1.295 (32,89)
0.128 (3,25)
0.120 (3,05)
0.050 (1,27)
0.040 (1,02) TYP
0.010 (0,25) MAX
0.400 (10,16) TYP
0.208 (5,28) MAX
0.360 (9,14) MAX
4088175/A 4/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
device symbolization (TM497MBM36A illustrated)
TM497MBM36A
–SS
YYMMT
YY = Year Code
MM = Month Code
T = Assembly Site Code
-SS = Speed Code
NOTE: Location of symbolization may vary.
10
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
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