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TMDS171, TMDS171I

ZHCSEG5E –OCTOBER 2015–REVISED SEPTEMBER 2017

TMDS171/I 3.4Gbps TMDS 重定时器

1 特性

3 说明

1

•

高清多媒体接口 (HDMI) 输入端口与输出端口间具

TMDS171 是一款数字视频接口 (DVI) 或高清多媒体接

有时钟和数据恢复 (CDR) 电路，支持高达

3.4Gbps 的数据传输速率

口 (HDMI) 重定时器。TMDS171 支持四条 TMDS 通

道，音频返回通道 (SPDIF_IN/ARC_OUT)、热插拔检

测 (HPD) 和数字显示控制 (DDC) 接口。TMDS171 支

持高达 3.4Gbps 的信号传输速率，可实现最高分辨率

达 4k2k30p 24 位/像素和高达 WUXGA 12 位色深或

1080p，并且具有较高的刷新率。TMDS171 在低于

1Gbps 的数据速率下会自动配置为重驱动器，而在高

于该速率时会自动配置为重定时器。

•

兼容 HDMI1.4b 电气参数。

支持 4k2k30p 和高达 WUXGA 12 位色深或

1080p，具有更高的刷新率™

•

对输入流重新定时以补偿随机抖动

自适应接收器均衡器或可编程固定均衡器

I²C 和引脚设置可编程

5+ 位对内偏移补偿

TMDS171 支持双电源轨（VDD 为 1.2V，VCC 为

3.3V），有助于降低功耗。该器件采用多种电源管理

方法来降低整体功耗。TMDS171x 通过 I²C 或引脚设

置支持固定的 EQ 增益或自适应 EQ 控制，以补偿不

同长度的输入电缆或电路板走线。

包括眼图的链路调试工具，位于 RX 均衡器之后

支持单端模式 ARC

48 引脚 7mm x 7mm 0.5mm 间距超薄型四方扁平

无引线 (VQFN) 封装

•

扩展商业温度范围为 0°C 至 85°C (TMDS171)

工业温度范围为 -40℃ 至 85°C (TMDS171I)

器件信息⁽¹⁾

器件型号

TMDS171

TMDS171I

封装

封装尺寸（标称值）

2 应用

(VQFN) 48 引脚

7.00mm x 7.00mm

•

数字电视

数字投影仪

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

音频/视频设备

蓝光 (Blu-Ray) DVD

监视器

台式机/一体化计算机

有源线缆

简化电路原理图

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weceiver

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1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

English Data Sheet: SLLSEN7

TMDS171, TMDS171I

ZHCSEG5E –OCTOBER 2015–REVISED SEPTEMBER 2017

www.ti.com.cn

8.4 Device Functional Modes........................................ 28

8.5 Register Maps ........................................................ 30

Application and Implementation ........................ 43

9.1 Application Information............................................ 43

9.2 Source Side Application.......................................... 45

9.3 System Examples ................................................... 49

1

2

3

4

5

6

特性.......................................................................... 1

应用.......................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

Pin Configuration and Functions......................... 4

Specifications......................................................... 6

6.1 Absolute Maximum Ratings ...................................... 6

6.2 ESD Ratings.............................................................. 6

6.3 Recommended Operating Conditions....................... 7

6.4 Thermal Information.................................................. 7

6.5 Electrical Characteristics........................................... 8

6.6 Switching Characteristics........................................ 10

6.7 Typical Characteristics............................................ 12

Parameter Measurement Information ................ 12

Detailed Description ............................................ 20

8.1 Overview ................................................................. 20

8.2 Functional Block Diagram ....................................... 21

8.3 Feature Description................................................. 21

9

10 Power Supply Recommendations ..................... 50

11 Layout................................................................... 52

11.1 Layout Guidelines ................................................. 52

11.2 Layout Example .................................................... 53

12 器件和文档支持 ..................................................... 54

12.1 相关文档ꢀ ........................................................... 54

12.2 接收文档更新通知 ................................................. 54

12.3 社区资源................................................................ 54

12.4 商标....................................................................... 54

12.5 静电放电警告......................................................... 54

12.6 Glossary................................................................ 54

13 机械、封装和可订购信息....................................... 54

7

8

4 修订历史记录

Changes from Revision D (August 2016) to Revision E

Page

•

Added Note 3 to the Electrical Characteristics table .............................................................................................................. 8

Deleted text "which is needed for certain HDMI CTS test." from the second paragraph in the Overview section .............. 20

Changed section: Input Signal Detect Block ........................................................................................................................ 25

Changed H to X in the first row of the HPD_SNK column in Table 36 ................................................................................ 51

Changed the IN_Dx column in Table 36 .............................................................................................................................. 51

Changes from Revision C (April 2016) to Revision D

Page

•

Recommended Operating Conditions, Changed the CONTROL PINS section ..................................................................... 7

Electrical Characteristics Changed the DDC and I2C section................................................................................................ 9

Changes from Revision B (February 2016) to Revision C

Page

•

Changed pin 36 Description From: TX_TERM_CTL = L: 150 - 300 Ω To: TX_TERM_CTL = L: Reserved in the Pin

Functions table ...................................................................................................................................................................... 6

Added OE to V_IL"Low-level input voltage" in the Recommended Operating Conditions table ............................................. 7

Added OE to V_IH"High-level input voltage" in the Recommended Operating Conditions table ............................................ 7

Changed Figure 23 .............................................................................................................................................................. 22

Deleted the VDD_ramp and VCC_ramp MIN values in Table 1 ......................................................................................... 23

Changed TX_TERM_CTL = L to Reserved in Table 3 ........................................................................................................ 25

•

Changed text "address 22h through the I²C interface" To: "address 0Bh through the I²C interface" DDC Functional

Description............................................................................................................................................................................ 29

•

Added Note to 11–400-kbps in Table 8................................................................................................................................ 32

Added Note to 11–400-kbps in Table 10.............................................................................................................................. 34

2

TMDS171, TMDS171I

www.ti.com.cn

ZHCSEG5E –OCTOBER 2015–REVISED SEPTEMBER 2017

Changes from Revision A (December 2015) to Revision B

Page

•

Changed Pin 44 From: AUX_SRCn To: ARC_OUT Pin 45 From: AUX_SRCn To: SPDIF_IN in the Pin Configuration

and Functions image ............................................................................................................................................................. 4

Changes from Original (October 2015) to Revision A

Page

•

已将器件状态从“产品预览”更改为“量产数据” .......................................................................................................................... 1

3

TMDS171, TMDS171I

ZHCSEG5E –OCTOBER 2015–REVISED SEPTEMBER 2017

www.ti.com.cn

5 Pin Configuration and Functions

RGZ (QFN) Package

48 Pins

Top View

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

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{í!tꢂth[

1

hÜÇ_ꢀ2p

hÜÇ_ꢀ2n

Itꢀ_{bY

hÜÇ_ꢀ1p

hÜÇ_ꢀ1n

Dbꢀ

2

3

Lb_ꢀ2p

Lb_ꢀ2n

4

Itꢀ_{w/

Lb_ꢀ1p

5

Lb_ꢀ1n

Dbꢀ

31

30

6

7

29

28

27

26

25

Lb_ꢀ0p

hÜÇ_ꢀ0p

hÜÇ_ꢀ0n

!1

8

9

Lb_ꢀ0n

L2/_ꢁbꢂtLb

Lb_/[Yp

10

11

12

Dbꢀ

hÜÇ_/[Yp

hÜÇ_/[Yn

Lb_/[Yn

21

24

13

14

15

16

17

18

19

20

23

22

4

TMDS171, TMDS171I

www.ti.com.cn

ZHCSEG5E –OCTOBER 2015–REVISED SEPTEMBER 2017

Pin Functions

I/O⁽¹⁾

DESCRIPTION

NAME

VCC

NO.

13, 43

P

3.3 V Power Supply

1.2 V Power Supply

Ground

VDD

14, 23, 24, 37, 48

7, 19, 41, 30

GND

G

Thermal Pad

Ground

MAIN LINK INPUT PINS (FAIL SAFE)

IN_D2p/n

IN_D1p/n

IN_D0p/n

IN_CLKp/n

2, 3

5, 6

I

Channel 2 Differential Input

Channel 1 Differential Input

Channel 0 Differential Input

Clock Differential Input

8, 9

11, 12

MAIN LINK OUTPUT PINS (FAIL SAFE)

OUT_D2n/p

34, 35

31, 32

28, 29

25, 26

O

TMDS Data 2 Differential Output

TMDS Data 1 Differential Output

TMDS Data 0 Differential Output

TMDS Clock Differential Output

OUT_D1n/p

OUT_D0n/p

OUT_CLKn/p

HOT PLUG DETECT PINS

HPD_SRC

4

O

I

Hot Plug Detect Output to source side

Hot Plug Detect Input from sink side

HPD_SNK

33

AUDIO RETURN CHANNEL and DDC PINS

SPDIF_IN

45

44

47

46

39

38

I

SPDIF signal input

ARC_OUT

SDA_SRC

O

Audio return channel output

I/O

Source Side TMDS Port Bidirectional DDC Data line

Source Side TMDS Port Bidirectional DDC Clock line

Sink Side TMDS Port Bidirectional DDC Data Line

Sink Side TMDS Port Bidirectional DDC Clock Line

SCL_SRC

SDA_SNK,

SCL_SNK

CONTROL PINS⁽²⁾

Operation Enable/Reset Pin

OE = L: Power Down Mode

OE = H: Normal Operation

Internal weak pull up: Resets device when transitions from H to L

OE

42

17

I

Signal detector circuit enable

SIG_EN = L: Signal Detect Circuit Disabled: Term resistors always connected (Default)

SIG_EN = H: Signal Detect Circuit Enabled: When no valid clock device enters Standby

SIG_EN

Mode.

Internal weak pull down

De-emphasis Control when I2C_EN/PIN = Low.

PRE_SEL = L: -2 dB

PRE_SEL = No Connect: 0 dB

PRE_SEL = H: Reserved

When I2C_EN/PIN = High; De-emphasis is controlled through I²C

I

PRE_SEL

20

21

3-Level

Input Receive Equalization pin strap when I2C_EN/PIN = Low

EQ_SEL = L: Fixed EQ at 7.5 dB

EQ_SEL = No Connect: Adaptive EQ

EQ_SEL = H: Fixed at 14 dB

EQ_SEL/A0

I

When I2C_EN/PIN = High Address Bit 1

Note: 3 level for pin strap programming but 2 level when I²C address

I2C_EN/PIN = High; Puts Device into I2C Control Mode

I2C_EN/PIN = Low; Puts Device into Pin Strap Mode

I2C_EN/PIN

SCL_CTL

10

15

I

I²C Clock Signal when I²C_EN/PIN = High.

Note: When I2C_EN = Low; Pin strapping takes priority and those functions cannot be

changed by I²C

I/O

I²C Data Signal when I²C_EN/PIN = High

SDA_CTL

VSadj

16

22

I/O

I

Note: When I2C_EN = Low; Pin strapping takes priority and those functions cannot be

changed by I²C

TMDS Output Voltage Swing Control; Nominal 7.06 kΩ Resistor to GND

(1) (1) G = Ground, I = Input, O = Output, P = Power

(2) (H) Logic High (Pin strapped to VCC through 65 kΩ resistor); (L) Logic Low (Pin strapped to GND through 65 kΩ resistor); (Mid-Level =

No connect)

5

TMDS171, TMDS171I

ZHCSEG5E –OCTOBER 2015–REVISED SEPTEMBER 2017

www.ti.com.cn

Pin Functions (continued)

I/O⁽¹⁾

DESCRIPTION

NAME

NO.

High address bit 2 for I²C programming

Weak internal pull down.

A1

27

I

Note: When I2C_EN/PIN = Low for Pin Strapping Mode leave this pin as No connect

Transmit Termination Control

TX_TERM_CTL = H: No transmit Termination

TX_TERM_CTL = L: Reserved

I

TX_TERM_CTL

36

TX_TERM_CTL = No Connect: Automatically selects the termination impedance

2 Gbps > DR ≤ 3.4 Gbps – 150 - 300 Ω differential near end termination

DR < 2 Gbps – no termination

3-Level

Note: If left floating; the device will be in Automatic Select Mode. DR stands for Data Rate

Receive Polarity Swap and Receive Lane Swap control pin

SWAP/POL = H: Receive Lanes Polarity Swap (Retimer Mode Only)

SWAP/POL = L: Receive Lanes (Retimer and Redriver Mode)

Swap SWAP/POL = No Connect, Normal Operation

I

SWAP/POL

NC

1

3-Level

18, 40

–

No connect

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)

(1)(2)(3)

MIN

–0.3

MAX

4

UNIT

VCC

Supply Voltage Range

VDD

1.4

Main Link Input Differential Voltage (IN_Dx,

IN_CLKx); I_IN= 15mA

V_CC- 0.75 V

–0.3

V_CC+ 0.3 V

4

TMDS Outpus ( OUT_Dx)

V

HPD_SRC, Vsadj, SDA_CTL, SCL_CTL, OE, A1,

Voltage Range

PRE_SEL, EQ_SEL/A0, I2C_EN/PIN, SIG_EN,

TX_TERM_CTL,

–0.3

4

HDP_SNK, SDA_SNK, SCL_SNK, SDA_SRC,

SCL_SRC

6

Main Link Input Differential Voltage (IN_Dx,

Input Current I_IN

IN_CLKx);

15

mA

°C

Continuous power dissipation

Storage temperature, T_stg

See Thermal Information

–65 150

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltage values, except differential voltages, are with respect to network ground terminal.

(3) Tested in accordance with JEDEC Standard 22, Test Method A114-B

6.2 ESD Ratings

VALUE

UNIT

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

±2000

V_(ESD)

Electrostatic discharge

V

Charged-device model (CDM), per JEDEC specification JESD22-

C101⁽²⁾

±500

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6

TMDS171, TMDS171I

www.ti.com.cn

ZHCSEG5E –OCTOBER 2015–REVISED SEPTEMBER 2017

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

3.135

1.1

NOM

3.3

MAX

3.465

1.27

150

92.7

85

UNIT

V

V_CC

Supply Voltage Nominal Value 3.3 V

Supply Voltage Nominial Value 1.2 V

Storage temperature

V_DD

1.2

V

T_STG

T_CASE

–65

°C

Case temperature

Operating free-air temperature (TMDS171)

Operating free-air temperature (TMDS171I)

0

T_A

–40

85

MAIN LINK DIFFERENTIAL PINS

V_ID(PP)

Peak-to-peak input differential voltage

75

VCC – 0.4

0.25

1560

VCC + 0.1

3.4

mVpp

V

V_IC

Input Common Mode Voltage

Data rate

d_R

Gbps

KΩ

R_(VSADJ)

TMDS compliant swing voltage bias resistor 1%

7.06

CONTROL PINS

V_I(DC)

DC Input Voltage

–0.3

3.6

0.8

V

Low-level input voltage OE

(1)

V_IL

Low-level input voltage at PRE_SEL, EQ_SEL/A0, TX_TERM_CTL,

SWAP/POL pins only⁽¹⁾

0.3

1.4

V

Mid-Level input voltage at PRE_SEL, EQ_SEL/A0, TX_TERM_CTL,

SWAP/POL pins only⁽¹⁾

(1)

V_IM

1

1.2

High-level input voltage at PRE_SEL, EQ_SEL/A0, TX_TERM_CTL,

SWAP/POL, OE⁽²⁾pins only⁽¹⁾

(1)

V_IH

2.6

V_OL

V_OH

I_IH

Low-level output voltage

High-level output voltage

High level input current

0.4

V

2.4

30

V

30

25

µA

mA

µA

KΩ

I_IL

Low level input current

–25

–50

I_OS

Short circuit output current

High impedance output current

Pull up resistance on OE pin

50

I_OZ

10

R_(OEPU)

150

250

(1) These values are based upon a microcontroller driving the control pins. The pull up/down/floating resistor configuration will set control

pins properly which will have a different value than shown due to internal biasing.

(2) This value is based upon a microcontroller driving the OE pin. A passive reset circuit using an external capacitor and the internal pullup

resistor will set OE pin properly, but may have a different value than shown due to internal biasing.

6.4 Thermal Information

RGZ (QFN)

THERMAL METRIC⁽¹⁾

UNIT

48 PINS

31.1

18.2

8.1

R_θJA

Junction-to-ambient thermal resistance

R_θJC(top)

R_θJB

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

°C/W

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

0.4

ψ_JB

8.1

R_θJC(bot)

3.2

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

7

TMDS171, TMDS171I

ZHCSEG5E –OCTOBER 2015–REVISED SEPTEMBER 2017

www.ti.com.cn

6.5 Electrical Characteristics

The Maximum rating is simulated at 3.465 V V_CCand 1.27 V V_DDand at 85°C temperature. The Typical rating is simulated at

3.3 V_CCand 1.2 V V_DDand at 27°C temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Power Supply

Device power Dissipation

(Retimer Operation)

(1)(2)

OE = H, V_CC= 3.3 V / 3.465 V, V_DD= 1.2 V / 1.27 V

IN_Dx: VID_PP = 1200 mV, I2C_EN/PIN = L, PRE_SEL= H,

EQ_CTL= H, SDA_CTL/CLK_CTL = 0 V

P_(D1)

675

400

875

600

mW

Device power Dissipation

(Redriver Operation)

(1)(2)

P_(D2)

3.4 Gbps TMDS pattern, V_I= 3.3 V; VSADJ = 7.06 kΩ

OE = H, V_CC= 3.3 V / 3.465 V

V_DD= 1.2 V / 1.27 V , HPD = H,

No Valid input Signal

(1)(2)(3)

P_(SD1)

Device power in Standby

50

100

mW

OE = L, V_CC= 3.3 V / 3.465 V

V_DD= 1.2 V / 1.27 V

(1)(2)(3)

P_(SD2)

Device power in PowerDown

10

80

30

mW

mA

V_CCSupply current (TMDS 3.4 OE = H, V_CC= 3.3 V / 3.465 V

(1)(2)

I_CC1

140

Gpbs Retimer Mode)

V_DD= 1.2 V / 1.27 V

IN_Dx: VID_PP = 1200 mV,

3.4 Gbps TMDS pattern I2C_EN/PIN = L, PRE_SEL = H,

EQ_CTL = H, SDA_CTL/CLK_CTL = 0 V, SLEW_CTL = H

V_DDSupply current (TMDS 3.4

Gpbs Retimer Mode)

(1)(2)

I_DD1

286

51

325

mA

V_CCSupply current (TMDS 3.4 OE = H, V_CC= 3.3 V / 3.465 V

(1)(2)

I_CC2

Gpbs Redriver Mode)

V_DD= 1.2 V / 1.27 V

IN_Dx: VID_PP = 1200 mV,

3.4 Gbps TMDS pattern I2C_EN/PIN = L, PRE_SEL = H,

EQ_CTL = H, SDA_CTL/CLK_CTL = 0V, SLEW_CTL = H

V_DDSupply current (TMDS 3.4

Gpbs Redriver Mode)

(1)(2)

I_DD2

188

6

OE = H, V_CC= 3.3 V / 3.465 V

V_DD= 1.2 V / 1.27 V

HPD = H: No valid signal on

IN_CLK

3.3V Rail⁽¹⁾

15

50

(3)

I_(SD1)

Standby current

mA

1.2V Rail

40

3.3V Rail⁽¹⁾

1.2V Rail

2

5

OE = L, V_CC= 3.3 V / 3.465 V

V_DD= 1.2 V / 1.27 V

(3)

I_(SD2)

PowerDown current

3.5

15

TMDS Differential Input

D_{(R_RX_DATA)}

D_{(R_RX_CLK)}

t_{RX_DUTY}

TMDS data lanes data rate

0.25

25

3.4

340

60%

0.3

Gbps

MHz

TMDS clock lanes clock rate

Input clock duty circle

40%

50%

t_{CLK_JIT}

Input clock jitter tolerance

Input data jitter tolerance

Tbit

ps

t_{DATA_JIT}

Test the TTP2 See Figure 11

150

t_{RX_INTRA}

t_{RX_INTER}

Input intra-pair skew tolerance Test at TTP2 when DR = 1.6 Gbps See Figure 11

Input inter-pair skew tolerance

112

ps

1.8

ns

Fixed EQ gain for data lane

EQ_SEL/A0=H; Fixed EQ gain, test at 3.4 Gbps

IN_D(0,1,2)n/p

E_QH(D)

E_QL(D)

E_QZ(D)

E_Q(C)

14

Fixed EQ gain for data lane

EQ_SEL/A0=L; Fixed EQ gain, test at 3.4 Gbps

IN_D(0,1,2)n/p

7.5

dB

Adaptive EQ gain for data lane

EQ_SEL/A0=NC; adaptive EQ

IN_D(0,1,2)n/p

2

14

EQ gain for clock lane

EQ_SEL/A0=H,LNC

IN_CLKn/p

0

Input differential termination

impedance

R_(INT)

90

100

115

Ω

TMDS Differential Output

PRE_SEL = NC; TX_TERM_CTL = H; OE = H; DR = 750

V_CC

-

V_CC

+

Mbps; VSadj = 7.06 kΩ

10mV

Single-ended high level output

voltage

V_OH

PRE_SEL = NC; TX_TERM_CTL = H; OE = NC; DR = 2.97

V_CC

-

V_CC

+

Gbps; VSadj = 7.06 kΩ

200mV

10mV

V

PRE_SEL = NC; TX_TERM_CTL = H; OE = H; DR = 750

V_CC

-

V_CC

-

Single-ended low level output

voltage No Pre-emphasis,

Load is 50 Ω pull ups to 3.135

V and 3.465 V

Mbps; VSadj = 7.06 kΩ

600mV

400mV

V_OL

PRE_SEL = NC; TX_TERM_CTL = H; OE = NC; DR = 2.97

Gbps; VSadj = 7.06 kΩ

V_CC

-

V_CC

-

700mV

400mV

(1) I_CCis a direct result of the source design as the TMDS171 integrated receive termination resistor accounts for 85 mA to 100 mA.

(2) I_DDis impacted by ARC usage. Connecting a 500 KΩ resistor to GND at SPDIF reduces the value by more than 20 mA.

(3) The measurements were made with no active source connected.

8

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Electrical Characteristics (continued)

The Maximum rating is simulated at 3.465 V V_CCand 1.27 V V_DDand at 85°C temperature. The Typical rating is simulated at

3.3 V_CCand 1.2 V V_DDand at 27°C temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Single-ended output voltage

swing on data lane

PRE_SEL = NC; TX_TERM_CTL = H/NC; OE = NC;

DR = ≤ 3.4 Gbps; VSadj = 7.06 kΩ

V_{(SWING_DA)}

V_{(SWING_CLK)}

400

500

600

Single-ended output voltage

swing on clock lane

PRE_SEL = NC; TX_TERM_CTL = H/NC; OE = NC;

DR = ≤ 3.4 Gbps; VSadj = 7.06 kΩ

400

–5

500

20

600

Change in single-end output

voltage swing per 100Ω

ΔVSadj

ΔV_(SWING)

Change in steady state output

common mode voltage

between logic levels

mV

ΔV_OCM(SS)

5

Initial output differential

voltage before steady state

when pre-emphasis or de-

emphasis is implemented

V_OD(PP)

VSadj = 7.06 kΩ; PRE_SEL = NC, See Figure 8

800

600

1200

Steady state output differential

voltage

V_OD(SS)

I_OS

VSadj = 7.06 kΩ; PRE_SEL = L, See Figure 9

1075

50

Short circuit current limit

Main link output shorted to GND

mA

µA

Ω

Failsafe condition leakage

current

V_CC= 0 V; V_DD= 0 V; TMDS Outputs pulled to 3.3V through

50 Ω resistor

I_LEAK

45

R_(TERM)

Source Termination resistance

150

300

DDC and I2C

SCL/SDA_SNK,

SCL/SDA_SRC DC input

voltage

–0.3

5.5

3.6

V

V_I-DC

SCL/SDA_CTL, DC input

voltage

SCL/SDA_SNK,

SCL/SDA_SRC Low level

input voltage

0.3 x V_CC

V_IL

SCL/SDA_CTL Low level input

voltage

SCL/SDA_SNK,

SCL/SDA_SRC high level

input voltage

3

V_IH

SCL/SDA_CTL high level input

voltage

0.7 x V_CC

SCL/SDA_CTL,

SCL/SDA_SRC low level

output voltage

I_O= 3 mA and V_CC> 2 V

I_O= 3 mA and V_CC< 2 V

0.4

V

V_OL

f_SCL

C_bus

0.2 x V_CC

SCL clock frequency fast I2C

mode for local I2C control

400

kHz

pF

Total capacitive load for each

bus line (DDC and local I2C

pins)

HPD

V_IH

High-level input voltage

Low-level input voltage

High-level output voltage

Low-level output voltage

HPD_SNK

2.1

V_IL

HPD_SNK

0.8

3.6

0.1

V_OH

V_OL

I_OH= -500 µA; HPD_SRC

I_OL= -500 µA; HPD_SRC

2.4

0

V

Failsafe condition leakage

current

I_LEAK

V_CC= 0 V; V_DD= 0 V; HPD_SNK = 5 V

40

Device powered; V_IH= 5 V; I_H(HPD)includes R_pd(HPD)resistor

current

I_H(HPD)

High level input current

µA

Device powered; V_IL= 0.8 V; I_H(HPD)includes R_pd(HPD)

resistor current

30

R_pd(HPD)

HPD input termination to GND; V_CC< 0 V

150

0

190

220

kΩ

SPDIF and ARC

Operating DC voltage for

V_(EL)

Test at ARC_OUT, see Figure 19

5

V

single mode ARC output

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Electrical Characteristics (continued)

The Maximum rating is simulated at 3.465 V V_CCand 1.27 V V_DDand at 85°C temperature. The Typical rating is simulated at

3.3 V_CCand 1.2 V V_DDand at 27°C temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Operating DC voltage for

SPDIF input

V_IN(DC)

0.05

V

Signal amplitude of SPDIF

input

V_{(SP_SW)}

V_(ElSWING)

CLK_(ARC)

0.2

0.4

0.5

0.6

V

Signal amplitude on the ARC

output

Test at ARC_OUT, 75 Ω external termination resistor, see

Figure 19

5.645±0.

1%

Signal frequency on ARC

Test at ARC_OUT, see Figure 19

3.687

13.517

MHz

Duty Cycle

Data Rate

Output Clock Duty cycle

SPDIF Input DR

45%

50%

55%

7.373

11.29

27.034

Mbps

UI

The rise/fall time for ARC

output

t_EDGE

From 10% to 90% voltage level, see Figure 19

0.1 MHz to 128 times the maximum frame rate

0.4

The Input Termination

resistance for SPDIF

R_{(IN_SPDIF)}

R_(EST)

75

55

Ω

Single mode Output

Termination resistance

36

75

6.6 Switching Characteristics

The Maximum rating is simulated at 3.465 V V_CCand 1.27 V V_DDand at 85°C temperature. The Typical rating is simulated at

3.3 V V_CCand 1.2 V V_DDand at 27°C temperature (unless otherwise noted)

PARAMETER

TMDS Redriver Mode

TEST CONDITIONS

MIN

TYP

MAX

UNIT

D_R

Data rate (Redriver mode)

250

3400

600

Mbps

t_PLH

t_PHL

Propagation delay time (low to high)

Propagation delay time (high to low)

800

Transition time (rise and fall time);

measured at 20% and 80% levels

for Data Lanes.

TX_TERM_CTL=L; PRE_SEL=NC;

Data Rate 3.4 Gbps; Clock 340 MHz

t_T1

75

ps

TX_TERM_CTL=NC;

PRE_SEL=NC;

t_SK1(T)

t_SK2(T)

Intra-pair output skew

Inter-pair output skew

40

TX_TERM_CTL=NC;

PRE_SEL=NC;

100

t_JITD1

t_JITC1

Total output data jitter

Total output clock jitter

DR = 750 Mbps, PRE_SEL = NC,

EQ_SEL/A0 = NC. See Figure 5 at

TTP3

0.2

Tbit

0.25

TMDS Retimer Mode

D_R

Data rate (retimer mod )

1.2

3.4

Gbps

Automatic redriver to Retimer Cross- Measured with input signal applied

Over

d_(XVR)

0.75

1.00

1.25

from 0 to 200 mV_PP

f_(CROSSOVE

R)

Crossover frequency hysteresis

Data Retimer PLL bandwidth

250

0.4

MHz

µs

PLL_(BW)

Default loop bandwidth setting

Tested when data rate > 1.0 Gbps

1

Input Clock Frequency Detection

and Retimer Acquisition Time

t_ACQ

I_JT1

180

Input Clock Jitter Tolerance

0.3

Tbit

Transition time (rise and fall time);

measured at 20% and 80% levels

for Data Lanes. TMDS

t_T1

75

ps

t_DCD

OUT_CLK ± duty cycle

40%

50%

60%

0.2

Default setting for internal inter-pair

skew adjust, PRE_SEL = NC;

TX_TERM_CTL = NC, DR ≤ 3.4

Gbps; See Figure 6

t_{SK_INTER}

Inter-pair output skew

Tch

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Switching Characteristics (continued)

The Maximum rating is simulated at 3.465 V V_CCand 1.27 V V_DDand at 85°C temperature. The Typical rating is simulated at

3.3 V V_CCand 1.2 V V_DDand at 27°C temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Default setting for internal intra-pair

skew adjust, PRE_SEL = NC;

TX_TERM_CTL = NC, DR ≤ 3.4

Gbps; See Figure 6

t_{SK_INTRA}

Intra-pair output skew

0.15

Tbit

t_JITC2

t_JITD2

HPD

Total output clock jitter

Total output data jitter

CLK Rate ≤ 340 MHz

0.25

0.2

Tbit

DR ≤ 3.4 Gbps; See Figure 11

Propagation delay from HPD_SNK

to HPD_SRC; rising edge and falling

edge⁽¹⁾

see Figure 13; not valid during

switching time

t_PD(HPD)

40

2

120

ns

t_T(HPD)

HPD logical disconnected timeout

see Figure 14

ms

DDC and I2C

Rise time of both SDA and SCL

signals

t_r

t_f

V_CC= 3.3 V

300

ns

Fall time of both SDA and SCL

signals

t_HIGH

Pulse duration, SCL high

0.6

1.3

100

0.6

µs

ns

t_LOW

Pulse duration, SCL low

t_SU1

Setup time, SDA to SCL

t_ST,STA

t_HD,STA

t_ST,STO

Setup time, SCL to start condition

Hold time, start condition to SCL

Setup time, SCL to stop condition

µs

Bus free time between stop and start

condition

t_(BUF)

t_PLH1

t_PHL1

t_PLH2

t_PHL2

1.3

Propagation delay time, low-to-high-

level output

360

230

250

200

Source to Sink:100 kbps pattern;

C_b(Sink)= 400 pF⁽²⁾; see Figure 17

Propagation delay time, high-to-low-

level output

ns

Propagation delay time, low-to-high-

level output

Sink to Source: 100 kbps pattern;

C_b(Source)= 100 pF⁽²⁾; see Figure 18

Propagation delay time, high-to-low-

level output

(1) The Maximum rating is simulated at 3.465 V V_CCand 1.27 V V_DD

(2) Cb = total capacitance of one bus line in pF.

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6.7 Typical Characteristics

200

180

160

140

120

100

80

300

270

240

210

180

150

120

90

1.2V

3.3V

1.2V

3.3V

60

40

60

0

0.5

1

1.5

2

2.5

3

3.5

0

0.5

1

1.5

2

2.5

3

3.5

Data Rate (Gbps)

D001

D002

Figure 1. Current vs Data Rate Redriver Mode

Figure 2. Current vs Data Rate Retimer Mode

1600

V_ODNo Term

V_OD150 to 300 W

1400

1200

1000

800

600

400

200

0

4

4.5

5

5.5

6

6.5

7

7.5

8

V_sadj(kW)

D003

Figure 3. V_ODvs VSadj

7 Parameter Measurement Information

V_CC

3.3V

50Ω

0.5 pF

D+

Y

Z

Receiver

Driver

V_ID

V_D+

V_Y

D-

V_ID= V_D+- V_D-

V_D-

V_OD= V_Y- V_Z

V_Z

V_ICM= (V_D++ V_D-

2

)

V_OC= (V_Y+ V_Z)

2

Figure 4. TMDS Main Link Test Circuit

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Parameter Measurement Information (continued)

2.2V

V_TERM

V_ID

1.8V

V_ID+

V_ID(pp)

0V

V_ID-

t_PHL

80%

t_PLH

80%

V_OD(pp)

V_OD

0V

20%

t_f

20%

t_r

Figure 5. Input/Output Timing Measurements

t_{SK_INTRA}

TMDS_OUTxp

TMDS_OUTxn

50%

t_{SK_INTER}

TMDS_OUTyp

TMDS_OUTyn

Figure 6. TMDS Output Skew Measurements

Figure 7. HDMI/DVI TMDS Output Common Mode Measurement

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Parameter Measurement Information (continued)

ëh5(tt)

tw9_{9[=ù

wsadj = 7.06YQ

Figure 8. Output Differential Waveform

tw9_{9[ = ù

ësadj = 7.06 lQ

tw9_{9[ = [

ësadj = 7.06 lQ

1^sꢀbiꢀ

2^ndꢀo ꢁ biꢀ

ëh5({{)

ëh5(tt)

Figure 9. Output De-emphasis Waveform

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ZHCSEG5E –OCTOBER 2015–REVISED SEPTEMBER 2017

Parameter Measurement Information (continued)

Avcc⁽⁴⁾

R_T

(5)

R_T

SMA

w9C

/able

9v

Data +

Coax

RX

+EQ

OUT

Data -

Parallel⁽⁶⁾

BERT

Jitter Test

Instrument^(2,3)

FR4 PCB trace⁽¹⁾

Device

FR4 PCB trace

AVcc

R_T

[No Pre-

emphasis]

R_T

w9C

SMA

Coax

Clk+

Clk-

/able

9v

RX

+EQ

OUT

Jitter Test

Instrument^(2,3)

TTP4_EQ

TTP4

TTP1

TTP2

TTP3

(1) The FR4 trace between TTP1 and TTP2 is designed to emulate 1-8” of FR4, connector and another 1-8” of FR4.

Trace width – 4 mils. 100 Ω differential impedance.

(2) All Jitter is measured at a BER of 10^-9

(3) Residual jitter reflects the total jitter measured at TTP4 minus the jitter measured at TTP1

(4) AVCC = 3.3 V

(5) R_T= 50 Ω

(6) The input signal from parallel Bert does not have any pre-emphasis. Refer to Recommended Operating Conditions.

Figure 10. Jitter Measurement Circuit

690

90

0

-90

-690

!bsolute Çime

75ps

ꢀormalized Çime: t_bit

Figure 11. HDMI Output Jitter Measurement

15

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Parameter Measurement Information (continued)

It5_{bY

It5_{w/

190Kꢀ

100Kꢀ

Figure 12. HPD Test Circuit

HPD_SNK

V_CC

50%

0 V

t_PD(HPD)

HPD_SRC

V_CC

50%

0 V

Figure 13. HPD Timing Diagram No. 1

Itꢀ_{bY

ë_//

50%

0ë

Itꢀ [ogical disconnecꢁ

Çimeouꢁ

ꢁ_Ç(Itꢀ)

Itꢀ_{w/

ë_//

0ë

[ogically

ꢀisconnecꢁed

ꢀevice [ogically

/onnecꢁed

Figure 14. HPD Logic Disconnect Timeout

16

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Parameter Measurement Information (continued)

tI5,{Ç!

tf

tr

{/[

t{Ç,{Çh

{5!

t(.ÜC)

{Ç!wÇ

{Çht

Figure 15. Start and Stop Condition Timing

tILDI

t[hí

{/[

t{Ç,{Ç!

{5!

t

{Ü1

Figure 16. SCL and SDA Timing

17

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Parameter Measurement Information (continued)

{5!_{w/ꢀ{/[_{w/

LbtÜÇ

½ ëcc

tꢀ[I1

tꢀI[1

80%

20%

{5!_{bYꢀ{/[_{bY

hÜÇtÜÇ

½ ëcc

tf

Figure 17. DDC Propagation Delay – Source to Sink

tr

{5!_{bY/{ꢀ[_{bY

LbtÜÇ

½ ëcc

tꢀI[2

tꢀ[I2

80%

20%

{5!_{wꢀ/{ꢀ[_{wꢀ

hÜÇtÜÇ

½ ëcc

tf

Figure 18. DDC Propagation Delay – Sink to Source

tr

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ZHCSEG5E –OCTOBER 2015–REVISED SEPTEMBER 2017

Parameter Measurement Information (continued)

1uC

weceiver

!w/_hÜÇ

{t5LC_Lb

wesꢀ

ë9[

ë9[ {íLbD

Figure 19. ARC Output

ÜL

0.4ÜL

Figure 20. Rise/Fall Time of ARC

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8 Detailed Description

8.1 Overview

The TMDS171 is a digital video interface (DVI) or high-definition multimedia interface (HDMI) retimer. The

TMDS171 supports four TMDS channels, Audio Return Channel (SPDIF_IN/ARC_OUT), Hot Plug Detect, and a

Digital Display Control (DDC) interfaces. The TMDS171 supports signaling rates up to 3.4 Gbps to allow for the

highest resolutions of 4k2k30p 24 bits per pixel and up to WUXGA 12-bit color depth or 1080p with higher

refresh rates. The TMDS171 can automatically configure itself as a re-driver at low data rate (< 1 Gbps) or as a

re-timer above this data rate. For passing compliance and reducing system level design issues several features

have been included such as TMDS output amplitude adjust using an external resistor on the VSADJ pin and

source termination selection control. Device operation and configuration can be programmed by pin strapping or

I²C. Four TMDS171s can be used on one I²C bus when I2C_EN enable and device address set by A0/A1.

To reduce active power the TMDS171 supports dual power supply rails of 1.2 V on V_DDand 3.3 V on V_CC. The

TMDS171 supports several methods of power management. It can enter power down mode using three

methods; (1) HPD is low; (2) Writing an 1 to register 09h[3]; or (3) de-asserting OE. If using OE, the device must

be reprogrammed via I²C if it was originally programmed this way. The SIG_EN pin enables the signal detect

circuit that provides an automatic power-management feature during normal operation. When no valid signal is

present on the inputs the device enters Stand by mode. By disabling the detect circuit the receiver block is

always on. DDC bridge supports 100 Kbps data rate default and 400 kbps adjustable by software.

TMDS171 supports both fixed EQ gain control or adaptive equalization to compensate for different lengths of

input cables or board traces. The EQ gain can be software adjusted by I²C control or selection between two fixed

values or adaptive equalization by pin strapping EQ_SEL pin. Implementers can use the TX_TERM_CTL pin to

change the transmitter termination impedance for better output performance when working in HDMI1.4b or leave

it floating. When floating the TMDS171 in conjunction with the rate detect will automatically change its output

termination to be compatible with HDMI1.4b requirements.

The TMDS171 supports single ended mode audio return channel. To assist in ease of implementation the

TMDS171 supports receive lane swapping and receive polarity swap. When swapping the input lanes IN_CLK

and IN_D2 swap and IN_D1 and IN_D0 swap with each other. Swap works in both retimer and redriver mode.

Polarity swap will swap the receive pins n and p channel polarity in each lane and is only available during retimer

mode. Both lane swap and polarity swap can be implemented at the same time in retimer mode using I²C

control.

Two versions of the device are offered to support extended commercial temperature range 0ºC to 85ºC

(TMDS171) or industrial operational temperature range from -40ºC to 85ºC (TMDS171I).

20

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8.2 Functional Block Diagram

Iꢃ5_{w/

Iꢃ5_{bY

130YQ

{LD_9b

ë.L!{

{LDb![ 59Ç9/Ç

ë{!5W

{LD_59Ç_hÜÇ

ꢁ0Q

hÜÇ_/[Yp

Lb_/[Yp

Lb_/[Yn

Çꢄ5{

9v

hÜÇ_/[Yn

5ata wegisters

{í!ꢃ

ꢃ[[

ë.L!{

ꢃ[[ /ontrol

{9w59{

ꢁ0Q

Lb_5ꢀ2:0]p

Lb_5ꢀ2:0]n

hÜÇ_5ꢀ2:0]p

9v

Çꢄ5{

hÜÇ_5ꢀ2:0]n

Ç9wꢄ_{9[

/ontrol .lock, L2/ wegisters

L2/_9bꢂꢃLb

9v_/Ç[

ꢃw9_{9[

9naꢅle

9v_{9[

{LD_9b

{LD_59Ç_hÜÇ

9v_{9[ꢂ!0

Ç9{Çꢂ!1

Ç9{Ç

!0

{LD_9b

ꢃw9_{9[

h9

!1

[ocal L2/

/ontrol

Çó_Ç9wꢄ_/Ç[

{5!_/Ç[

{/[_/Ç[

{í!ꢃꢂꢃh[

{5!_{w/

{/[_{w/

{5!_{bY

{/[_{bY

!/ÇLë9 55/ .[h/Y

{ꢃ5LC_Lb

!w/_hÜÇ

!w/ Cunction

Db5

1ꢆ0ꢁë

3ꢆ3ë

ë55

ë//

ëw9D

8.3 Feature Description

8.3.1 Reset Implementation

When OE is de-asserted, control signal inputs are ignored; the HDMI inputs and outputs are high impedance. It

is critical to transition the OE from a low level to high after the V_CCsupply has reached the minimum

recommended operating voltage. This is achieved by a control signal to the OE input, or by an external capacitor

connected between OE and GND. To insure the TMDS171 is properly reset, the OE pin must be de-asserted for

at least 100 μs before being asserted. When OE is re-asserted the TMDS171 will have to be reprogrammed if it

21

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Feature Description (continued)

was programmed by I²C and not pin strapping. When implementing the external capacitor, the size of the

external capacitor depends on the power up ramp of the V_CCsupply, where a slower ramp-up results in a larger

value external capacitor. Refer to the latest reference schematic for TMDS171; consider approximately 200 nF

capacitor as a reasonable first estimate for the size of the external capacitor. Both OE implementations are

shown in Figure 21 and Figure 22.

h9

ww{Ç = 200 YΩ

/

Figure 21. External Capacitor Controlled OE

Dth

h9

/

Figure 22. OE Input from Active controller

8.3.2 Operation Timing

TMDS171 starts to operate after the OE signal is properly set after power up timing complete. See Figure 23,

Figure 24, Table 1. If OE is held low until V_DDand V_CCbecome stable there is no rail sequence requirement.

t

d2

h9

t

d1

ë_//ꢀ ë₅₅

ë₅₅ꢀ ë_//

Figure 23. Power up Timing for TMDS171

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Feature Description (continued)

t_d3

/5w !ctive

t_d4

wetimer mode

h9 5e-assert or

Iꢀ5_{bY 5e-assert or

wedriver mode

Figure 24. CDR Timing for TMDS171

Table 1. Power Up and Operation Timing Requirements

DESCRIPTION

MIN

0

TYP

MAX

UNIT

µs

t_d1

V_DDStable before V_CC

200

t_d2

V_DDand V_CCstable before OE de-assertion

CDR active operation after retimer mode initiated

CDR turn off time after retimer mode de-assert

V_DDsupply ramp up requirements

100

µs

t_d3

15

ms

ns

td4

120

100

V_DD(ramp)

V_CC(ramp)

ms

V_CCsupply ramp up requirements

8.3.3 Swap and Polarity Working (Retimer Mode Only)

TMDS171 incorporates swap function which can set the input lanes in swap mode. The IN_D2 will route to the

OUT_CLK position by swapping with IN_CLK. The IN_D1 swaps with IN_D0. The Swap function only changes

the input pins. The EQ setup follows the new mapping, see Figure 25. This function can be used with the

SWAP/POL pin 1 and control the register 0x09h bit 7 for SWAP enable. The Swap function works in both redriver

and retimer mode. The TMDS171 can also swap the input polarity signals. When SWAP/POL is high the n and p

pins on each lane will swap. Polarity swap only works when in retimer mode. When this function is enabled and

the device is in automatic cross over mode between redriver and retimer modes, care must be taken to avoid

losing polarity swap. When the data rate drops to the redriver level, the polarity swap is lost.

Table 2. SWAP Pin Mapping

Normal Op

SWAP = L or CSR 0x09h bit 7 is 1'b1

IN_D2 → OUT_CLK

IN_D2 → OUT_D2

IN_D1 → OUT_D1

IN_D0 → OUT_D0

IN_CLK → OUT_CLK

IN_D1 → OUT_D0

IN_D0 → OUT_D1

IN_CLK → OUT_D2

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ZHCSEG5E –OCTOBER 2015–REVISED SEPTEMBER 2017

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36

35

34

33

32

Çꢁwa_/Ç[

hÜÇ_ꢀ2p

hÜÇ_ꢀ2n

{í!tꢂth[

1

2

{í!tꢂth[

36

35

34

33

32

Çꢁwa_/Ç[

1

2

Lb_ꢀ2p

Lb_ꢀ2n

hÜÇ_ꢀ2p

hÜÇ_ꢀ2n

Lb_ꢀ2p

Lb_ꢀ2n

ꢀ!Ç! [!bꢁ2

/[h/Y [!bꢁ

3

Itꢀ_{bY

hÜÇ_ꢀ1p

4

Itꢀ_{bY

hÜÇ_ꢀ1p

Itꢀ_{w/

Lb_ꢀ1p

Itꢀ_{w/

Lb_ꢀ1p

4

5

ꢀ!Ç! [!bꢁ1

ꢀ!Ç! [!bꢁ0

hÜÇ_ꢀ1n

Lb_ꢀ1n

Dbꢀ

31

30

6

Lb_ꢀ1n

Dbꢀ

31

30

6

Dbꢀ

7

Dbꢀ

7

29

28

27

26

25

Lb_ꢀ0p

hÜÇ_ꢀ0p

hÜÇ_ꢀ0n

!1

8

Lb_ꢀ0p

hÜÇ_ꢀ0p

hÜÇ_ꢀ0n

29

28

27

26

25

8

ꢀ!Ç! [!bꢁ0

ꢀ!Ç! [!bꢁ1

Lb_ꢀ0n

L2/_ꢁbꢂtLb

Lb_/[Yp

9

Lb_ꢀ0n

L2/_ꢁbꢂtLb

Lb_/[Yp

9

10

11

12

10

11

12

!1

hÜÇ_/[Yp

hÜÇ_/[Yn

/[h/Y [!bꢁ

hÜÇ_/[Yp

hÜÇ_/[Yn

ꢀ!Ç! [!bꢁ2

Lb_/[Yn

{í!t = ù

Ln bormal íorking

{í!t = [

Ln {wap íorking

Figure 25. TMDS171 Swap Function

8.3.4 TMDS Inputs

Standard TMDS terminations are integrated on all TMDS inputs. External terminations are not required. Each

input data channel contains an adaptive or fixed equalizer to compensate for Inter-Symbol Interference (ISI) due

to cable, connector, and/or board trace losses. The voltage at the TMDS input pins must be limited under the

absolute maximum ratings. TMDS input pins have incorporated failsafe circuits. An unused input channel can be

externally biased to prevent output oscillation by connecting the N input pin to be grounded through a 1-kΩ

resistor and the other pin left open. The input pins can be polarity changed through local I²C register when in

retimer mode.

8.3.5 TMDS Inputs Debug Tools

There are two methods for debugging a system to make sure the inputs to the TMDS171 are valid. A TMDS

error checker is implemented to provide a rough Bit Error Rate per data lane. This allows the system

implementer to determine how the link between the source and TMDS171 is performing on all three data lanes.

See CSR BIT FIELD DEFINITIONS – RX PATTERN VERIFIER CONTROL/STATUS register.

If a high error count is evident the TMDS171 has a way to view the general receiver eye quality. A tool is

available that uses the I²C link to down load the data that can be plotted for an eye diagram. This is available per

data lane. This tool also provides a method to turn on an internal PRBS generator that will transmit a data signal

on the data pins. A clock at the proper frequency is required on the IN_CLK pins to generated the expected

output data rate.

8.3.6 Receiver Equalizer

The equalizer used to clean up inter-symbol interference (ISI) jitter/loss from the bandwidth-limited board traces

or cables. TMDS171 supports fixed receiver equalizer and adaptive equalizer by setting the EQ_SEL/A0 pin or

through I²C. When EQ_SEL/A0 is high, the EQ gain is fixed to 10 dB and when set low the EQ gain is set to 7.5

dB. TMDS171 operates in adaptive equalizer mode when EQ_SEL/A0 pin is left floating. The EQ gain will be

automatically adjusted based on the data rate to compensate for trace or cable loss. Implementers can enable

the various EQ settings through local I²C control.

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Figure 26. Adaptive EQ Gain Curve

8.3.7 Input Signal Detect Block

When SIG_EN is enabled, the TMDS looks for a valid TMDS clock signal input. The terminations on the TMDS

data lines are connected and the device is fully functional when a valid signal is detected. If no valid TMDS clock

signal is detected, the device enters standby mode waiting for a valid signal at the clock input. The internal CDR

is shut down and all of the TMDS outputs are in high-Z status. TMDS signal detect circuit can be set as enable

by SIG_EN pin or through local I²C control but is default disabled. Designers are recommended to activate this

function in normal operation for power saving.

8.3.8 Audio Return Channel

The Audio Return Channel in TMDS171 enables a TV, via a single HDMI cable, to send audio data “upstream” to

an A/V receiver or surround audio controller, increasing user flexibility and eliminating the need for any separate

S/PDIF audio connection. The TMDS171 supports single mode audio return channel. Implementers can send the

S/PDIF signal to SPDIF_IN. The signal from ARC_OUT is sent to HDMI connectors and is passed through the

general HDMI cable to audio receiver. By I²C control, customer can disable ARC_OUT by register. Enabled by

default after initialization.

8.3.9 Transmitter Impedance Control

Source termination is disabled at data rates < 2 Gbps. When the data rate is between 2 Gbps and 3.4 Gbps, the

output signal may be better if the termination value around 150 Ω to 300 Ω depending upon system

implementation. TMDS171 supports two different source termination impedances for ease of implementation. Pin

36, TX_TERM_CTL, offers a selection option to choose the output termination impedance value.

Table 3. TX Termination Control

Control Pin 36

TX_TERM_CTL = H

TX_TERM_CTL = L

DESCRIPTION

The transmit Termination is disabled

Reserved

Automatic select the impedance

TX_TERM_CTL = Z

•

2 Gbps > DR < 3.4 Gbps – 150 - 300 Ω differential near end termination

DR < 2 Gbps – no termination

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1600

1400

1200

1000

800

600

400

200

0

V_ODNo Term

V_OD150 to 300 W

V_ODNo Term

V_OD150 to 300 W

1400

1200

1000

800

600

400

200

0

4

4.5

5

5.5

6

6.5

7

7.5

8

4

4.5

5

5.5

6

6.5

7

7.5

8

V_sadj(kW)

D003

8.3.10 TMDS Outputs

A 1% precision resistor, 7.06 kΩ, connected from VSADJ to ground is recommended to allow the differential

output swing to comply with TMDS signal levels. The differential output driver provides a typical 10 mA current

sink capability, which provides a typical 500 mV voltage drop across a 50 Ω termination resistor.

!ë//

ëcc

Ça5{171

ùo=wÇ

Ça5{ 5wLë9w

Ça5{ w9/9Lë9w

Figure 27. TMDS Driver and Termination Circuit

In Figure 27, if V_CC(TMDS171 supply) and AVCC (sink termination supply) are both powered, the TMDS output

signals are high impedance when OE = high. Both supplies being active are the normal operating condition.

Again refer to Figure 27, if V_CCis on and AVCC is off, the TMDS outputs source a typical 5 mA current through

each termination resistor to ground. A total of 33 mW of power is consumed by the terminations independent of

the OEB logical selection. When AVCC is powered on, normal operation (OE controls output impedance) is

resumed. When the power source of the device is off and the power source to termination is on, the IO(off),

output leakage current, specification ensures the leakage current is limited to 45 μA or less. The PRE_SEL pin

provides – 2 dB de-emphasis gain, allowing output signal pre-conditioning to offset interconnect losses from the

TMDS171 outputs to a TMDS receiver. De-emphasis is recommended to be set at 0 dB while connecting to a

receiver through short PCB route. The V_ODof the data lanes and clock lane can be adjusted through I²C. See

Table 11 for detail. Figure 1 shows the different output voltages based on the different VSADJ settings.

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8.3.11 Pre-Emphasis/De-Emphasis

The TMDS171 provides de-emphasis as a way to compensate for ISI loss between the TMDS171 outputs and a

TMDS receiver. There are two methods to implement this function. When in pin strapping mode the PRE_SEL

pin controls this function. The PRE_SEL pin provides - 2 dB or 0 dB de-emphasis, which allows the output signal

pre-conditioning. De-emphasis is recommended to be set at 0-dB while connecting to a receiver through short

PCB traces. When pulled to ground through a 65 kΩ resistor - 2 dB can be realized, see Figure 9. When using

I²C, reg0Ch[1:0] is used to make these adjustments.

As there are times that true pre-emphasis may be the best solution there are two methods to accomplish this. If

pin strapping is being used the best method is to reduce the VSADJ resistor value thus increasing the V_ODswing

and then pulling the PRE_SEL pin to ground using a 65 kΩ resistor, see Figure 28. If using I²C there are two

methods to accomplish this. The first is similar to pin strapping but reducing VSADJ resistor value and then

implementing - 2 db de-emphasis through I²C, reg0Ch[1:0] = 01. The second method is to increase the VOD

swing by setting reg0Ch[7:5] = 011 and reg0Ch[1:0] = 01 which will accomplish the same pre-emphasis value,

see Figure 29. Note: De-emphasis is only implement able during retimer mode. In redriver mode this function is

not available.

tw9_{9[ = ù

ësadj = 7.06YQ

tw9_{9[ = [

ësadj = 4.5YQ

1^sꢁbiꢁ

2^ndꢁo ꢂ biꢁ

ëh5(tt) = 1400mëpp

ëh5({{) = 11ꢀ0mëpp

Figure 28. Pre-emphasis Using Pin Strapping

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ZHCSEG5E –OCTOBER 2015–REVISED SEPTEMBER 2017

www.ti.com.cn

tw9_{9[ = ù

ësadj = 7.06YQ

L2/ weg0/hꢀ7:5] = 011

weg0/ꢀ1:0] = 01

1^sꢀbiꢀ

2^ndꢀo ꢁ biꢀ

ëh5(tt) = 1200mëpp

ëh5({{) = 1020mëpp

Figure 29. Pre-emphasis Using I²C

8.4 Device Functional Modes

8.4.1 Retimer Mode

Clock and Data Recovery Circuits (CDR) are used to track, sample and retime the equalized data bit streams.

The CDRs are designed with loop bandwidth to minimize the amount of jitter transfer from the video source to

the TMDS outputs. Input jitter within the CDR’s PLL bandwidth, < 1 MHz, is transferred to the TMDS outputs.

Higher frequency jitter above the CDR loop bandwidth is attenuated, providing a jitter cleaning function to reduce

the amount of high frequency jitter from the video source. The retimer is automatically activated at pixel clock

above approximately 100 MHz when jitter cleaning is needed for robust operation. The retimer operates at about

100 Mhz – 340 MHz pixel clock (1 – 3.4 Gbps). At pixel clock below about 100 MHz, the TMDS171 automatically

bypasses the internal retimer, and operates as a redriver. When the video source changes resolution, the internal

retimer starts the acquisition process to determine the input clock frequency and acquire lock to the new data bit

streams. During the clock frequency detection period and the retimer acquisition period that last approximately 7

ms, the TMDS drivers can be kept active (default) or programmed to be disabled to avoid sending invalid clock or

data to the downstream receiver. The TMDS171 can support retimer mode across the full data rate range of 250

Mbps - 3.4 Gbps by setting DEV_FUNC_MODE bits at reg0Ah[1:0], See Table 9. For compliance testing such as

JTOL for 480 Mbps the PLL must be forced to lock.

8.4.2 Redriver Mode

The TMDS171 can function as a redriver which compensates for ISI channel loss. In this mode, power is

reduced as the CDR and PLL are turned off. When in automatic mode, the TMDS171 is in redriver mode for data

rates < 1.0 Gbps. By using I²C the device can be put in Redriver mode for the complete data range of 250 Mbps

to 3.4 Gbps. This is done by writing a 00 to register 0Ah[1:0]. If the link has excessive random jitter then retimer

mode is the best operating mode. If the link has excessive random jitter, the retimer mode is the best operating

mode. When in redriver mode, the device compensates for ISI loss only. When in redriver mode compliance is

not ensured as skew compensation and retiming functions are disabled. If a significant amount of random jitter is

present, the system may not pass compliance at the connector.

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Device Functional Modes (continued)

8.4.3 DDC Functional Description

The TMDS171 solves sink/source level issues by implementing a master/salve control mode for the DDC bus.

When the TMDS171 detects the start condition on the DDC bus from the SDA_SRC/SCL_SRC, it transfers the

data or clock signal to the SDA_SNK/SCL_SNK with little propagation delay. When SDA_SNK detects the

feedback from the downstream device, the TMDS171 pulls up or pulls down the SDA_SRC bus and delivers the

signal to the source.

The DDC link defaults to 100 kbps but can be set to various values including 400 kbps by setting the correct

value to address 0Bh through the I²C interface. The DDC lines are 5 V tolerant when the device is powered off.

The HPD goes to high impedance when VCC is under low power conditions < 1.5 V.

NOTE

The TMDS171 utilizes clock stretching for DDC transactions. As there are sources and

sinks that do not perform this function correctly as system may not work correctly as DDC

transactions are incorrectly transmitted/recieved. To overcome this a snoop configuration

can be implemented where the SDA/SCL from the source is connected directly to the

SDA/SCL sink. The TMDS171 will need its SDA_SNK and SCL_SNK pins connected to

this link.

8.4.4 Mode Selection Functional Description

Mode Selection Definition: reg0Ah[7] is the mode select register, see Table 9. This bit lets the receiver know

where the device is located in a system for the purpose of centering the AEQ point. The TMDS171 is targeting

sink or dock applications so the default value is 1 which centers the EQ at 12 dB to 13 dB, see Table 12. If the

TMDS171 is in a source application the value should be changed to a 0 which centers the EQ at 6.5 dB to 7.5

dB.

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8.5 Register Maps

8.5.1 Local I²C Overview

The TMDS171 local I²C interface is enabled when I2C_EN/PIN is high. The SCL_CTL and SDA_CTL terminals

are used for I²C clock and I²C data respectively. The TMDS171 I²C interface conforms to the two-wire serial

interface defined by the I²C Bus Specification, Version 2.1 (January 2000), and supports the fast mode transfer

up to 400 kbps.

The device address byte is the first byte received following the START condition from the master device. The 7

bit device address for TMDS171 decides by the combination of EQ_SEL/A0 and A1. Table 4 clarifies the

TMDS171 target address.

Table 4. TMDS171 I2C Device Address Description

TMDS171 I2C Device Address

A1/A0

00

Bit 7 (MSB)

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0 (W/R)

HEX

BC/BD

BA/BB

B8/B9

B6/B7

1

0

1

0

1

0

1

0

1

0

1

0/1

01

10

11

The typical source application of the TMDS171 is as a retimer in a TV connecting the HDMI input connector and

an internal HDMI receiver through flat cables. The register setup can adjust by source side. When TMDS171

used in sink side application, it received data from input connector and transmit to receiver. The local I²C is not 5

V tolerant and only support 3.3 V. Local I2C buses run at 400 kHz supporting fast-mode I²C operation.

The following procedure is followed to write to the TMDS171 I²C registers:

1. The master initiates a write operation by generating a start condition (S), followed by the TMDS171 7-bit

address and a zero-value “W/R” bit to indicate a write cycle

2. The TMDS171 acknowledges the address cycle

3. The master presents the sub-address (I²C register within TMDS171) to be written, consisting of one byte of

data, MSB-first

4. The TMDS171 acknowledges the sub-address cycle

5. The master presents the first byte of data to be written to the I²C register

6. The TMDS171 acknowledges the sub-address cycle

7. TMDS171 acknowledges the byte transfer

8. The master may continue presenting additional bytes of data to be written, with each byte transfer completing

with an acknowledge from the TMDS171

9. The master terminates the write operation by generating a stop condition (P)

The following procedure is followed to read the TMDS171 I²C registers:

1. The master initiates a read operation by generating a start condition (S), followed by the TMDS171 7-bit

address and a one-value “W/R” bit to indicate a read cycle

2. The TMDS171 acknowledges the address cycle

3. The TMDS171 transmit the contents of the memory registers MSB-first starting at register 00h.

4. The TMDS171 will wait for either an acknowledge (ACK) or a not-acknowledge (NACK) from the master after

each byte transfer; the I²C master acknowledges reception of each data byte transfer

5. If an ACK is received, the TMDS171 transmits the next byte of data

6. The master terminates the read operation by generating a stop condition (P)

NOTE

Nno sub-addressing is included for the read procedure, and reads start at register offset

00h and continue byte by byte through the registers until the I²C master terminates the

read operation.

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Refer to Table 4 for TMDS171 local I²C register descriptions. Reads from reserved fields not described return

zeros, and writes are ignored.

8.5.1.1 BIT Access Tag Conventions

A table of bit descriptions is typically included for each register description that indicates the bit field name, field

description, and the field access tags. The field access tags are described in Table 5.

Table 5. Access Tags

ACCESS TAG

NAME

Read

DESCRIPTION

The field shall be read by software

R

W

S

Write

The field shall be written by software

Set

The field shall be set by a write of one. Writes of Zero to the field have no effect

The field shall be cleared by a write of one. Writes of Zero to the field have no effect

Hardware may autonomously update this field

C

Clear

u

Update

No Access

NA

Not accessible or not applicable

8.5.2 CSR Bit Field Definitions, DEVICE_ID (offset: 00000000 ≈ 00000111) (reset:00h ≈ 07h)

Figure 30. CSR Bit Field Definitions, DEVICE_ID (00h ≈ 07h)

7

0

6

0

5

0

4

0

3

0

2

0

1

0

R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset, S= Set, U = autonomously update

Table 6. CSR Bit Field Definitions, DEVICE_ID (00h ≈ 07h)

Bit

Field

Type

Reset

Description

7:0

DEVICE_ID

R

00h ≈ 07h

These fields return a string of ASCII characters “TMDS171”

preceded by one space characters.

TMDS171:

0x00 – 0x07 = {- 0x54”T”, 0x4D”M”, 0x44”D”, 0x53”S”, 0x31”1”,

0x37”7”, 0x31”1”, 0x20},

8.5.3 CSR Bit Field Definitions, REV _ID (offset: 00001000) (reset: 01h)

Figure 31. CSR Bit Field Definitions, REV _ID (08h)

7

0

6

0

5

0

4

0

3

0

2

0

1

0

1

R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset, S= Set, U = autonomously update

Table 7. CSR Bit Field Definitions, REV _ID (08h)

Bit

Field

Type

Reset

Description

7:0

REV _ID

R

01h

This field identifies the device revision.

0000001– TMDS171 Revision 1

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8.5.4 CSR BIT Field Definitions – Misc Control (offset: 00001001) (reset: 02h)

Figure 32. CSR Bit Field Definitions – Misc Control (09h)

7

0

6

0

5

0

4

0

3

0

2

0

1

0

R/W/U

R

R/W/U

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset, S= Set, U = autonomously update

Table 8. CSR Bit Field Definitions – Misc Control (09h)

Bit

Field

Type

Reset

Description

7

Lane_SWAP

R/W/U

1’b0

This field Swaps the input lanes as per Figure 25.

0 --- Disable (default) No Lane Swap

1 --- enable: Swaps input lanes (Redriver and Retimer Mode)

Note: field is loaded from SWAP/POL pin; Writes are ignored

when I2C_EN/PIN = 0

6

LANE_POLARITY

R/W/U

1’b0

Swaps the input Data and Clock lanes polarity.

0 – Disabled: No polarity swap

1 – Swaps the input Data and Clock lane polarity (Retimer Mode

Only)

Note: field is loaded from SWAP/POL pin; Writes are ignored

when I2C_EN/PIN = 0

5

4

Reserved

SIG_EN

R

1’b0

Reserved

R/W/U

This field enable the clock lane activity detect circuitry.

0 – Disable(Default) Clock detector circuit closed and receiver

always works in normal operation.

1 – Enable , Clock detector circuit will make receiver automatic

enter the standby state when no valid data detect.

Note: field is loaded from SIG_EN pin; Writes are ignored when

I2C_EN/PIN = 0

3

2

PD_EN

R/W

1’b0

0 – Normal working (default)

1 – Forced Power down by I²C, Lowest Power state

HPD_AUTO_PWRDWN_DISABLE

0 – Automatically enters power down mode based on HPD_SNK

(default)

1 – Will not automatically enter power down mode

1:0

I2C_DR_CTL

R/W

2’b10

I²C data rate supported for configuring device.

00 – 5 Kbps

01 – 10 Kbps

10 – 100 Kbps(default)

11 – 400 Kbps (Note: HPD_AUTO_PWRDWN_DISABLE must

be set before enabling 400 Kbps mode)

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8.5.5 CSR BIT Field Definitions – Misc Control (offset: 00001010) (reset: B1h)

Figure 33. CSR Bit Field Definitions – Misc Control (0Ah)

7

1

6

0

5

1

4

1

3

0

2

0

1

0

1

R/W

R

W

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset, S= Set, U = autonomously update

Table 9. CSR Bit Field Definitions – Misc Control (0Ah)

Bit

Field

Type

Reset

Description

7

Application Mode Selection

R/W

1’b1

See Mode Selection

TMDS171

0 – Source

1 – Sink (Default)

6

HPDSNK_GATE_EN

R/W

1’b0

Swaps the input Data and Clock lanes polarity. The field set the

HPD_SNK signal pass through to HPD_SRC or not and

HPD_SRC whether held in the de-asserted state.

0 – HPD_SNK passed through to the HPD_SRC ( default )

1 – HPD_SNK will not pass through to the HPD_SRC.

5

4

EQ_ADA_EN

EQ_EN

R/W

1’b1

This field enable the equalizer functioning state; Writes are

ignored when I2C_EN/PIN = 0

0 – Fixed EQ

1 – Adaptive EQ (default)

This field enable the Equalizer; Writes are ignored when

I2C_EN/PIN = 0

0 -- EQ disable

1 – EQ enable (default)

3

2

Reserved

R

1’b0

Reserved

APPLY_RXTX_CHANGES

W

Self-clearing write-only bit.

Writing a 1 to this bit will apply new TX_TERM, HDMI_TWPST1,

EQ_EN, EQ_ADA_EN, VSWING, Fixed EQ value settings to the

clock and data lanes. Writes to the respective registers do not

take immediate effect.

This bit does not need to be written if I²C configuration occurs

while OE or HPD_SNK are low, I2C PD_EN=1 or there is no

HDMI clock applied and SIG_EN is high.

1:0

DEV_FUNC_MODE.

R/W

2’b01

This field selects the Device Working Function Mode.

00 – Redriver Mode across full range 250 Mbps – 3.4 Gbps

01 - Automatic Redriver to Retimer Cross Over at 1.0 Gbps

(default)

10 - Reserved

11 - Retimer Mode across full range 250 Mbps – 3.4 Gbps

When changing crossover point, need to toggle PD_EN or

toggle external HPD_SNK.

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8.5.6 CSR BIT Field Definitions – Misc Control (offset: 00001011) (reset: 00h)

Figure 34. CSR Bit Field Definitions – Misc Control (0Bh)

7

0

6

0

5

0

4

0

3

0

2

0

1

0

R

R/W/U

R/W

R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset, S= Set, U = autonomously update

Table 10. CSR Bit Field Definitions – Misc Control (0Bh)

Bit

7:5

4:3

Field

Type

R

Reset

2’b000

2’b00

Description

Reserved

TX_TERM_CTL

Reserved

RWU

Controls termination for HDMI TX; Writes are ignored when

I2C_EN/PIN = 0

00 – No termination

01 – 150 to 300 Ω

10 – Reserved.

11 – Reserved

2

DDC_DR_SEL

Reserved

R/W

R

1’b0

Defines the DDC output speed for both DDC bridge and AUX-

DDC Bridge.

0 = 100 kbps (default)

1 = 400 kbps (Note: HPD_AUTO_PWRDWN_DISABLE must be

set before enabling 400 Kbps mode)

1:0

2’b00

Reserved

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8.5.7 CSR BIT Field Definitions – Misc Control (offset: 00001100) (reset: 00h)

Figure 35. CSR Bit Field Definitions – Misc Control (0Ch)

7

0

6

0

5

0

4

0

3

0

2

0

1

0

R/W

R/W/U

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset, S= Set, U = autonomously update

Table 11. CSR Bit Field Definitions – Misc Control (0Ch)

Bit

Field

Type

Reset

Description

7:5

VSWING_DATA

R/W

3’b000

Data Output Swing Control (Need Design input on what is

available)

000 – Vsadj set (default)

001 – Increase by 7%

010 – Increase by 13%

011 – Increase by 18%

100 – Decrease by 30%

101 – Decrease by 22%

110 – Decrease by 15%

111 – Decrease by 7%

4:2

VSWING_CLK

R/W

13’b000

Clock Output Swing Control: Default is set by DR which means

standard based swing values but this allows for the swing to be

overridden by selecting one of the following values.

000 – Set by Data Rate

001 – Increase by 7%

010 – Increase by 13%

011 – Increase by 18%

100 – Decrease by 30%

101 – Decrease by 22%

110 – Decrease by 15%

111 – Decrease by 7%

1:0

HDMI_TWPST1[1:0]

R/W/U

2’b00

HDMI pre-emphasis FIR post-cursor-1 signed tap weight.

00 – No pre-emphasis

01 – 2 dB pre-emphasis.

10 – Reserved

11 – Reserved

Note: Reflects value of PRE_SEL pin; Writes are ignored when

I2C_EN/PIN = 0

35

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8.5.8 CSR BIT Field Definitions – Equalization Control Register (offset: 00001101) (reset: 01h)

Figure 36. CSR BIT Field Definitions – Equalization Control Register (0Dh)

7

0

6

0

5

0

4

0

3

0

2

0

1

0

1

R

R/W

R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset, S= Set, U = autonomously update

Table 12. CSR BIT Field Definitions – Equalization Control Register (0Dh)

Bit

7:6

5:3

Field

Type

R

Reset

2’b00

Description

Reserved

Data Lane EQ

Reserved

R/W

1’b000

Sets Fixed EQ Values

000 – 0 dB

001 – 4.5 dB

010 – 6.5 dB

011 – 8.5 dB

100 – 10.5 dB

101 – 12 dB

110 – 14 dB

111 – 16.5 dB

2:1

0

Clock Lane EQ

Reserved

R/W

R

13’b000

1’b1

- Sets Fixed EQ Values.

00 – 0 dB

01 – 1.5 dB

10 – 3 dB

011 – RSVD

Reserved

8.5.9 CSR BIT Field Definitions – RX Pattern Verifier Control/Status (offset: 00001110) (reset: 00h)

Figure 37. CSR BIT Field Definitions – RX Pattern Verifier Control/Status (0Eh)

7

0

6

0

5

0

4

0

3

0

2

0

1

0

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset, S= Set, U = autonomously update

Table 13. CSR BIT Field Definitions – RX Pattern Verifier Control/Status (0Eh)

Bit

Field

Type

Reset

Description

7:4

PV_SYNC[3:0]

R/W

4’b0000

Pattern timing pulse. This field is updated for 8UI once every

cycle of the PRBS generator. 1 bit per lane.

3:0

PV_LD[3:0]

R/W

4’b0000

Load pattern-verifier controls into RX lanes. When asserted high,

the PV_TO, PV_SEL, PV_LEN, PV_CP20, and PV_CP values

are enabled into the corresponding RX lane. These values are

then latched and held when PV_LD[n] is subsequently de-

asserted low. 1 bit per lane.

8.5.10 CSR BIT Field Definitions – RX Pattern Verifier Control/Status (offset: 00001111) (reset: 00h)

Figure 38. CSR BIT Field Definitions – RX Pattern Verifier Control/Status (0Fh)

7

0

6

0

5

0

4

0

3

0

2

0

1

0

R/U

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset, S= Set, U = autonomously update

Table 14. CSR BIT Field Definitions – RX Pattern Verifier Control/Status (0Fh)

Bit

7:4

3:0

Field

Type

R/U

Reset

Description

PV_SYNC[3:0]

PV_LD[3:0]

4’b0000

Pattern verification mismatch detected. 1 bit per lane.

Pattern search/training in progress. 1 bit per lane.

R/U

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8.5.11 CSR BIT Field Definitions – RX Pattern Verifier Control/Status (offset: 00010000) (reset: 00h)

Figure 39. CSR BIT Field Definitions – RX Pattern Verifier Control/Status (10h)

7

0

6

0

5

0

4

0

3

0

2

0

1

0

R/W

R

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset, S= Set, U = autonomously update

Table 15. CSR BIT Field Definitions – RX Pattern Verifier Control/Status (10h)

Bit

Field

Type

Reset

Description

7

PV_CP20

R/W

1’b0

Customer pattern length 20/16 bits.

0 – 16 bits

1 – 20 bits

6

Reserved

R

1’b0

Reserved

5:3

PV_LEN[2:0]

R,W

3’b000

]PRBS pattern length

000 – PRBS7

001 – PRBS11

010 – PRBS23

011 – PRBS31

100 – PRBS15

101 – PRBS15

110 – PRBS20

111 – PRBS20

2:0

PV_SEL[24:0]

R/W

3’b000

Pattern select control

000 – Disabled

001 – PRBS

010 - Clock

011 - Custom

1xx – Timing only mode with sync pulse spacing defined by

PV_LEN

8.5.12 CSR BIT Field Definitions – RX Pattern Verifier Control/Status (offset: 00010001) (reset: 00h)

Figure 40. CSR BIT Field Definitions – RX Pattern Verifier Control/Status (11h)

7

0

6

0

5

0

4

0

3

0

2

0

1

0

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset, S= Set, U = autonomously update

Table 16. CSR BIT Field Definitions – RX Pattern Verifier Control/Status (11h)

Bit

Field

Type

Reset

Description

7

PV_CP[7:0]

R/W

‘h00

Custom pattern data.

8.5.13 CSR BIT Field Definitions – RX Pattern Verifier Control/Status (offset: 00010010) (reset: 00h)

Figure 41. CSR BIT Field Definitions – RX Pattern Verifier Control/Status (12h)

7

0

6

0

5

0

4

0

3

0

2

0

1

0

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset, S= Set, U = autonomously update

Table 17. CSR BIT Field Definitions – RX Pattern Verifier Control/Status (12h)

Bit

Field

Type

Reset

Description

7

PV_CP[15:8]

R/W

‘h00

Custom pattern data.

37

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8.5.14 CSR BIT Field Definitions – RX Pattern Verifier Control/Status (offset: 00010011) (reset: 00h)

Figure 42. CSR BIT Field Definitions – RX Pattern Verifier Control/Status (13h)

7

0

6

0

5

0

4

0

3

0

2

0

1

0

R

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset, S= Set, U = autonomously update

Table 18. CSR BIT Field Definitions – RX Pattern Verifier Control/Status (13h)

Bit

7:4

3:0

Field

Type

R

Reset

Description

Reserved

PV_CP[19:16]

4’b0000

Reserved

R/W

Custom pattern data. Used when PV_CP20 = 1’b1.

8.5.15 CSR BIT Field Definitions – RX Pattern Verifier Control/Status (offset: 00010100) (reset: 00h)

Figure 43. CSR BIT Field Definitions – RX Pattern Verifier Control/Status (14h)

7

0

6

0

5

0

4

0

3

0

2

0

1

0

R

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset, S= Set, U = autonomously update

Table 19. CSR BIT Field Definitions – RX Pattern Verifier Control/Status (14h)

Bit

7:3

2:0

Field

Type

R

Reset

Description

Reserved

PV_THR[2:0]

5’b00000

3’b000

Reserved

R/W

Pattern-verifier retain threshold.

8.5.16 CSR BIT Field Definitions – RX Pattern Verifier Control/Status (offset: 00010101) (reset: 00h)

Figure 44. CSR BIT Field Definitions – RX Pattern Verifier Control/Status (15h)

7

0

6

0

5

0

4

0

3

0

2

0

1

0

R

R/S/U

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset, S= Set, U = autonomously update

Table 20. CSR BIT Field Definitions – RX Pattern Verifier Control/Status (15h)

Bit

7

Field

Type

R

Reset

1’b0

Description

DESKEW_CMPLT

Reserved

Indicates that TMDS lane deskew has completed when high.

Reserved

6:5

4

R

2’b00

1’b0

BERT_CLR

TST_INTQ_CLR

TST_SEL[2:0]

R/S/U

R/W

Clear BERT counter (on rising edge).

Clear latched interrupt flag.

3

1’b0

2:0

3’b000

Test interrupt source select.

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8.5.17 CSR BIT Field Definitions – RX Pattern Verifier Control/Status (offset: 00010110) (reset: 00h)

Figure 45. CSR BIT Field Definitions – RX Pattern Verifier Control/Status (16h)

7

0

6

0

5

0

4

0

3

0

2

0

1

0

R/W

R

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset, S= Set, U = autonomously update

Table 21. CSR BIT Field Definitions – RX Pattern Verifier Control/Status (16h)

Bit

7:4

3

Field

Type

R/W

R

Reset

4’b0000

1’b0

Description

PV_DP_EN[3:0]

Reserved

Enable datapath verified based on DP_TST_SEL, 1 bit per lane

Reserved

2:0

DP_TST_SEL[2:0]

R/W

3’b000

Selects pattern reported by BERT_CNT[11:0],

TST_INT[0] and TST_INTQ[0] and PV_DP_EN is non-zero.

000 – TMDS disparity or data errors

001 – FIFO errors

010 – FIFO overflow errors

011 – FIFO underflow errors

100 – TMDS deskew status

101,110,111 – Reserved.

8.5.18 CSR BIT Field Definitions – RX Pattern Verifier Control/Status (offset: 00010111) (reset: 00h)

Figure 46. CSR BIT Field Definitions – RX Pattern Verifier Control/Status (17h)

7

0

6

0

5

0

4

0

3

0

2

0

1

0

R/U

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset, S= Set, U = autonomously update

Table 22. CSR BIT Field Definitions – RX Pattern Verifier Control/Status (17h)

Bit

7:4

3:0

Field

Type

R/U

Reset

Description

TST_INTQ[3:0]

RTST_INT[3:0]

4’b0000

Latched interrupt flag. 1 bit per lane

Test interrupt flag. 1 bit per lane.

R/U

8.5.19 CSR BIT Field Definitions – RX Pattern Verifier Control/Status (offset: 00011000) (reset: 00h)

Figure 47. CSR BIT Field Definitions – RX Pattern Verifier Control/Status (18h)

7

0

6

0

5

0

4

0

3

0

2

0

1

0

R/U

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset, S= Set, U = autonomously update

Table 23. CSR BIT Field Definitions – RX Pattern Verifier Control/Status (18h)

Bit

Field

Type

Reset

Description

7:0

BERT_CNT[7:0]

R/U

‘h00

BERT error count. Lane 0

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8.5.20 CSR BIT Field Definitions – RX Pattern Verifier Control/Status (offset: 00011001) (reset: 00h)

Figure 48. CSR BIT Field Definitions – RX Pattern Verifier Control/Status (19h)

7

0

6

0

5

0

4

0

3

0

2

0

1

0

R

R/U

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset, S= Set, U = autonomously update

Table 24. CSR BIT Field Definitions – RX Pattern Verifier Control/Status (19h)

Bit

7:4

3:0

Field

Type

R

Reset

Description

Reserved

4’b0000

Reserved

BERT_CNT[11:8]

R/U

BERT error count. Lane 0

8.5.21 CSR BIT Field Definitions – RX Pattern Verifier Control/Status (offset: 00011010) (reset: 00h)

Figure 49. CSR BIT Field Definitions – RX Pattern Verifier Control/Status (1Ah)

7

0

6

0

5

0

4

0

3

0

2

0

1

0

R/U

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset, S= Set, U = autonomously update

Table 25. CSR BIT Field Definitions – RX Pattern Verifier Control/Status (1Ah)

Bit

Field

Type

Reset

Description

7:0

BERT_CNT[19:12].

R/U

‘h00

BERT error count. Lane 1

8.5.22 CSR BIT Field Definitions – RX Pattern Verifier Control/Status (offset: 00011011) (reset: 00h)

Figure 50. CSR BIT Field Definitions – RX Pattern Verifier Control/Status (1Bh)

7

0

6

0

5

0

4

0

3

0

2

0

1

0

R

R/U

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset, S= Set, U = autonomously update

Table 26. CSR BIT Field Definitions – RX Pattern Verifier Control/Status (1Bh)

Bit

7:4

3:0

Field

Type

R

Reset

Description

Reserved

4’b0000

Reserved

BERT_CNT[23:20]

R/U

BERT error count. Lane 1

8.5.23 CSR BIT Field Definitions – RX Pattern Verifier Control/Status (offset: 00011100) (reset: 00h)

Figure 51. CSR BIT Field Definitions – RX Pattern Verifier Control/Status (1Ch)

7

0

6

0

5

0

4

0

3

0

2

0

1

0

R/U

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset, S= Set, U = autonomously update

Table 27. CSR BIT Field Definitions – RX Pattern Verifier Control/Status (1Ch)

Bit

Field

Type

Reset

Description

7:0

BERT_CNT[31:24]

R/U

‘h00

BERT error count. Lane 2

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8.5.24 CSR BIT Field Definitions – RX Pattern Verifier Control/Status (offset: 00011101) (reset: 00h)

Figure 52. CSR BIT Field Definitions – RX Pattern Verifier Control/Status (1Dh)

7

0

6

0

5

0

4

0

3

0

2

0

1

0

R

R/U

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset, S= Set, U = autonomously update

Table 28. CSR BIT Field Definitions – RX Pattern Verifier Control/Status (1Dh)

Bit

7:4

3:0

Field

Type

R

Reset

Description

Reserved

4’b0000

Reserved

BERT_CNT[35:32]

R/U

BERT error count. Lane 2

8.5.25 CSR BIT Field Definitions – RX Pattern Verifier Control/Status (offset: 00011110) (reset: 00h)

Figure 53. CSR BIT Field Definitions – RX Pattern Verifier Control/Status (1Eh)

7

0

6

0

5

0

4

0

3

0

2

0

1

0

R/U

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset, S= Set, U = autonomously update

Table 29. CSR BIT Field Definitions – RX Pattern Verifier Control/Status (1Eh)

Bit

Field

Type

Reset

Description

7:0

BERT_CNT[19:12]

R/U

’h00

BERT error count. Lane 3

8.5.26 CSR BIT Field Definitions – RX Pattern Verifier Control/Status (offset: 00011111) (reset: 00h)

Figure 54. CSR BIT Field Definitions – RX Pattern Verifier Control/Status (1Fh)

7

0

6

0

5

0

4

0

3

0

2

0

1

0

R

R/U

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset, S= Set, U = autonomously update

Table 30. CSR BIT Field Definitions – RX Pattern Verifier Control/Status (1Fh)

Bit

7:4

3:0

Field

Type

R

Reset

Description

Reserved

4’b0000

Reserved

BERT_CNT[23:20]

R/U

BERT error count. Lane 3

8.5.27 CSR BIT Field Definitions – RX Pattern Verifier Control/Status (offset: 00100000) (reset: 00h)

Figure 55. CSR BIT Field Definitions – RX Pattern Verifier Control/Status (20h)

7

0

6

0

5

0

4

0

3

0

2

0

1

0

R

R/W

R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset, S= Set, U = autonomously update

Table 31. CSR BIT Field Definitions – RX Pattern Verifier Control/Status (20h)

Bit

Field

Type

Reset

Description

7

PWR_DWN_STATUS

R

1’b0

Power Down Status Bit.

0 = Normal Operation (default)

1 = Device in Power Down Mode

41

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Table 31. CSR BIT Field Definitions – RX Pattern Verifier Control/Status (20h) (continued)

Bit

Field

Type

Reset

Description

6

STB_STATUS

R

1’b0

Standby Status Bit

0 = Normal Operation (default)

1 = Device in Standby Mode

5:0

Reserved

R

6’b000000 Reserved

42

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ZHCSEG5E –OCTOBER 2015–REVISED SEPTEMBER 2017

9 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

9.1 Application Information

The TMDS171 was defined to work in many applications. This includes source applications like a Blu-Ray DVD

player or AVR. The adaptive receive equalizer makes it ideal for sink applications like HDTV, monitors and

projectors where cable length can be widely varied. The TMDS171 is also capable of working as an active cable

to extend the cable length even further.

9.1.1 Application Chain Showing DDC Connections

The DDC circuitry inside the TMDS171 allows multiple stage operation as shown in Figure 56. The retimer

devices can be connected to any of the bus segments. The number of devices that can be connected in series is

limited by repeater delay/time of flight considerations for the maximum bus speed requirements.

{hÜw/9

!cꢂive /ꢃble

{LꢄY

ꢁë

3ꢀ3ë

ꢁë

3ꢀ3ë

wÜtsouce

wÜtsource

wup wup

wÜtsink

{[Y_{w/

w{[Y

Ç{/[

{[Y_{w/ {[Y_{LꢄY

{5!_{w/ {5!_{LꢄY

{[Y_{LꢄY

{[Y_{w/

{[Y_{LꢄY

{5!_{w/ {5!_{LꢄY

w{5!

Ç{5!

/2

/1

/3

/2

/3

/2

.Ü{

{[!ë9

.Ü{

a!{Ç9w

Ça5{171

Figure 56. Typical Series Application

9.1.2 DDC Pull Up Resistors

This section is for information only and subject to change depending upon system implementation. The pull-up

resistor value is determined by two requirements.

1. The maximum sink current of the I²C buffer: The maximum sink current is 3 mA or slightly higher for an I²C

driver supporting standard-mode I²C operation.

V

CC

Rup(min) =

I

sink

(1)

2. The maximum transition time on the bus:

The maximum transition time, T, of an I²C bus is set by an RC time constant, where R is the pull-up resistor

value, and C is the total load capacitance. The parameter, k, can be calculated from Equation 2 by solving

for t, the times at which certain voltage thresholds are reached. Different input threshold combinations

introduce different values of t. Table 32 summarizes the possible values of k under different threshold

combinations.

43

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Application Information (continued)

T = k x RC

(2)

(3)

-t

æ

ç

è

ö

÷

ø

RC

V t = VDD x 1-e

( )

Table 32. Value k upon Different Input Threshold Voltages

Vth-\Vth+

0.7 V_CC

1.0986

1.0415

0.9808

0.9163

0.8473

0.65 V_CC

0.9445

0.8873

0.8267

0.7621

0.6931

0.6 V_CC

0.8109

0.7538

0.6931

0.6286

0.5596

0.55 V_CC

0.6931

0.6360

0.5754

0.5108

0.4418

0.5 V_CC

0.5878

0.5306

0.4700

0.4055

0.3365

0.45 V_CC

0.4925

0.4353

0.3747

0.3102

0.2412

0.4 V_CC

0.4055

0.3483

0.2877

0.2231

0.1542

0.35 V_CC

0.3254

0.2683

0.2076

0.1431

0.0741

0.3 V_CC

0.2513

0.1942

0.1335

0.0690

0.1 V_CC

0.15 V_CC

0.2 V_CC

0.25 V_CC

0.3 V_CC

From Equation 1, R_up(min)= 5.5 V / 3 mA = 1.83 kΩ to operate the bus under a 5-V pull-up voltage and provide

less than 3 mA when the I²C device is driving the bus to a low state. If a higher sink current, for example 4 mA,

is allowed, R_up(min)can be as low as 1.375 kΩ.

If DDC working at standard mode of 100 Kbps, the maximum transition time T is fixed, 1 μs, and using the k

values from Table 32, the recommended maximum total resistance of the pull-up resistors on an I²C bus can be

calculated for different system setups. If DDC working at fast mode of 400 Kbps, the transition time should be set

at 300 ns according to I²C specification.

To support the maximum load capacitance specified in the HDMI spec, C_cable(max)= 700 pF/C_(source)= 50 pF/Ci =

50 pF, R(max) can be calculated as shown in Table 33.

Table 33. Pull-Up Resistor Upon Different Threshold Voltages and 800-pF Loads

Vth-\Vth+

0.1 V_CC

0.7 V_CC

1.14

1.2

0.65 V_CC

1.32

0.6 V_CC

1.54

1.65

1.8

0.55 V_CC

1.8

0.5 V_CC

2.13

0.45 V_CC

2.54

0.4 V_CC

3.08

3.59

4.35

5.6

0.35 V_CC

3.84

0.3 V_CC

4.97

6.44

9.36

18.12

—

UNIT

KΩ

0.15 V_CC

0.2 V_CC

1.41

1.97

2.36

2.87

4.66

KΩ

1.27

1.36

1.48

1.51

2.17

2.66

3.34

6.02

KΩ

0.25 V_CC

0.3 V_CC

1.64

1.99

2.23

2.45

3.08

4.03

8.74

KΩ

1.8

2.83

3.72

5.18

8.11

16.87

KΩ

44

TMDS171, TMDS171I

www.ti.com.cn

ZHCSEG5E –OCTOBER 2015–REVISED SEPTEMBER 2017

To accommodate the 3 mA drive current specification, a narrower threshold voltage range is required to support

a maximum 800 pF load capacitance for a standard-mode I²C bus.

9.2 Source Side Application

I5aL/5ëL

weceptacle

Ça5{_52p

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1

3

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34

32

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hÜÇ_ꢀ[Yp

hÜÇ_ꢀ[Yn

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Ça5{_51p

Db52

Db53

Db54

Db5ꢁ

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Lb_52n

Lb_51p

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8

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11

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4

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13

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20

21

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17

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10uC

0.1uC 0.1uC 0.1uC 0.1uC 0.01uC 0.01uC

10uC

0.1uC 0.1uC

ë55_1.1ë

ëꢀꢀ_3.3ë

Figure 57. TMDS171 in Source Side Application

45

TMDS171, TMDS171I

ZHCSEG5E –OCTOBER 2015–REVISED SEPTEMBER 2017

www.ti.com.cn

Source Side Application (continued)

9.2.1 Design Requirements

The TMDS171 can be designed into many different applications. In all the applications there are certain

requirements for the system to work properly. Two voltage rails are required in order to support lowest power

consumption possible. OE pin must have a 200 nF capacitor to ground. This pin can be driven by a processor

but the pin needs to change states after voltage rails have stabilized. The best way to configure the device is by

using I²C but pin strapping is also provided as I²C is not available in all cases. As sources may have many

different naming conventions it is necessary to confirm that the link between the source and the TMDS171 are

correctly mapped. A Swap function is provide for the input pins incase signaling if reversed between source and

device. Table 34 provides information on expected values in order to perform properly.

Table 34. Design Parameters

PARAMETER

V_CC

VALUE

3.3 V

V_DD

1.2 V

Main Link Input Voltage

Control Pin Max Voltage for Low

Control Pin Voltage Range Mid

Control Pin Min Voltage for High

R_(VSADJ)Resistor

V_ID= 75 mV_PPto 1.4 V_PP

65 kΩ pulldown

Left Not Connected/Floating

65 kΩ pullup

7.06 kΩ 1%

9.2.2 Detailed Design Procedure

The TMDS171 is a signal conditioning device that provides several forms of signal conditioning in order to

support compliance for HDMI or DVI at a source connector. These forms of signal conditioning are accomplished

using receive equalization, retiming, and output driver configurability. The transmitter will drive 2-3” of board trace

and connector when compliance is required at the connector.

To design in the TMDS171 the following need to be understood for a source side application:

•

Determine the loss profile between the GPU/chipset and the HDMI/DVI connector.

Based upon this loss profile and signal swing determine optimal location for the TMDS171, in order to pass

source electrical compliance. Usually within 2”-3” of the connector

•

Use the typical application Figure 57 for information on control pin resistors.

The TMDS171 has a receiver adaptive equalizer but can also be configured using EQ_SEL control pin.

Set the VOD, Pre-emphasis, termination, and edge rate levels appropriately to support compliance by using

the appropriate VSADJ resistor value and setting PRE_SEL, and TX_TERM_CTL control pins.

•

The thermal pad must be connected to ground.

See Figure 57 for recommended decouple capacitors from V_CCand V_DDpins to Ground

9.2.3 Application Curves

Figure 59. 4k2k30 Compliance Eye

Figure 58. 1080p Compliance Eye

46

TMDS171, TMDS171I

www.ti.com.cn

ZHCSEG5E –OCTOBER 2015–REVISED SEPTEMBER 2017

9.2.4 Sink Side Application

For a sink side application HPD needs consideration. The TMDS171 drives the HPD signal to 3.3V which

meetings requirements but if 5 V HPD signaling is required the two circuits shown in Figure 60 are required. As

sources are not consistent in implementing all aspects of the DDC link it is recommended to configure the

TMDS171 as per Figure 60. Another consideration in relationship to how HPD is implemented is the architecture

and behavior of the HDMI RX/Scalar.

IꢀꢂL/ꢀëL

/onnector

IꢀꢂL ꢃó/{calar

35

34

32

31

2ꢆ

28

26

25

2

3

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Çꢂꢀ{_ꢀ1p

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Çꢂꢀ{_ꢅ[Yn

h9

Dꢄꢀ1

Dꢄꢀ2

ꢀ2p

ꢀ2n

Lꢄ_ꢀ2p

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Lꢄ_ꢀ1n

Lꢄ_ꢀ0p

Lꢄ_ꢀ0n

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Lꢄ_ꢅ[Yn

hÜÇ_ꢀ2p

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hÜÇ_ꢅ[Yn

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below

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14

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13 43

ëꢅꢅ

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5ë

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5ë

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1lQ

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100Q

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100lQ

Figure 60. TMDS171 in Sink Side Application, 5 V HPD Implementation

47

TMDS171, TMDS171I

ZHCSEG5E –OCTOBER 2015–REVISED SEPTEMBER 2017

www.ti.com.cn

9.2.4.1 Design Requirements

See Table 35 for the Sink Side design example parameters.

Table 35. Design Parameters

PARAMETER

V_CC

VALUE

3.3 V

V_DD

1.2 V

Main Link Input Voltage

Control Pin Max Voltage for Low

Control Pin Voltage Range Mid

Control Pin Min Voltage for High

R_(VSADJ)Resistor

V_ID= 75 mV_PPto 1.4 V_PP

65 kΩ pulldown

Left Not Connected/Floating

65 kΩ pullup

7.06 kΩ 1%

9.2.4.2 Detailed Design Procedure

To design in the TMDS171 the following need to be understood for a source side application.

•

Determine the loss profile between the RX/chipset and the HDMI/DVI connector.

Based upon this loss profile and signal swing determine optimal location for the TMDS171, in order to pass

sink electrical compliance.

•

Use the typical application Figure 56 for information on control pin resistors.

The TMDS171 has a receiver adaptive equalizer but can also be configured using EQ_SEL control pin.

Set the VOD, Pre-emphasis, termination, and edge rate levels appropriately to support link between

TMDS171 and HDMI RX/Chipset by using the appropriate VSADJ resistor value and setting PRE_SEL and

TX_TERM_CTL control pins.

•

The thermal pad must be connected to ground.

See Figure 60 for recommended decouple caps from V_CCand V_DDpins to Ground.

48

TMDS171, TMDS171I

www.ti.com.cn

ZHCSEG5E –OCTOBER 2015–REVISED SEPTEMBER 2017

9.3 System Examples

Another way to configure sink application is to configure the sink as per Figure 61. This is done as not all

sources are supporting clock stretching as per standard.

I5aL/5ëL

/onnector

{ink {ide

I5aL wó/{cꢀlꢀr

3ꢂ

34

32

31

2ꢃ

28

26

2ꢂ

2

3

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Ça5{_ꢁ[Yn

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52p

52n

Lb_52p

Lb_52n

Lb_51p

Lb_51n

Lb_50p

Lb_50n

Lb_ꢁ[Yp

Lb_ꢁ[Yn

hÜÇ_52p

Db52

Db53

Db54

Db5ꢂ

Db56

hÜÇ_52n

hÜÇ_51p

hÜÇ_51n

hÜÇ_50p

hÜÇ_50n

hÜÇ_ꢁ[Yp

hÜÇ_ꢁ[Yn

ꢂ

51p

6

51n

8

50p

ꢃ

50n

11

12

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Ça5{_ꢁ[Yn

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ëꢁꢁ_3.3ë

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44

!wꢁ_hÜÇ

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55Q

65lQ

1

65lQ

41

Lmplementation specific.

ꢀay not be needed if {ource

ꢁas implemented

{í!t/th[

L2ꢁ_9b/tLb

{LD_9b

7

10

17

20

21

27

36

Db5

ëꢁꢁ_3.3ë

1ꢃ

30

Db5

tw9_{9[

9v_{9[/!0

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16

Çó_Ç9wa_ꢁÇ[

hptional

42

h9

65lQ

h9

65lQ

0.1uC

ëꢁꢁ_3.3ë

ë55_1.1ë

22

10uC

ë{!5W

0.1uC 0.1uC

7YQ

1%

10uC

0.1uC 0.1uC 0.1uC 0.01uC 0.01uC

0.1uC

14

24

23

37 48

13 43

ë55_1.1ë

ëꢁꢁ_3.3ë

Figure 61. TMDS171 in Sink Side Application

49

TMDS171, TMDS171I

ZHCSEG5E –OCTOBER 2015–REVISED SEPTEMBER 2017

www.ti.com.cn

10 Power Supply Recommendations

To minimize the power consumption of customer application, TMDS171 used the dual power supply. V_CCis 3.3 V

with 5% range to support the I/O voltage. The V_DDis 1.2 V with 1.1 V to 1.27 V range to supply the internal digital

control circuit. TMDS171 operates in 3 different working states.

•

o Power down Mode:

–

OE = Low puts the device into its lowest power state by shutting down all function blocks.

–

When OE is re-asserted the transitions from L→H will create a reset and if the device is programmed

through I²C it must to be reprogrammed.

–

Writing a 1 to register 09h[3].

OE = High, HPD_SNK = Low

•

Standby Mode: HPD_SNK = High but no valid clock signal detect on clock lane.

Normal operation: Working in Redriver or Retimer

When HPD assert, the device CDR and output will enable based on the signal detector circuit result.

HPD_SRC = HPD_SNK in all conditions.

50

TMDS171, TMDS171I

ZHCSEG5E –OCTOBER 2015–REVISED SEPTEMBER 2017

www.ti.com.cn

11 Layout

11.1 Layout Guidelines

On a high-K board – It is always recommended to solder the PowerPAD™ onto the thermal land. A thermal land

is the area of solder-tinned-copper underneath the PowerPAD™ package. On a high-K board the TMDS171 can

operate over the full temperature range by soldering the PowerPAD onto the thermal land without vias.

On a low-K board – In order for the device to operate across the temperature range on a low-K board, a 1-oz Cu

trace connecting the GND pins to the thermal land must be used. A simulation shows R_θJA= 100.84°C/W

allowing 545 mW power dissipation at 70°C ambient temperature.

A general PCB design guide for PowerPAD packages is provided in the document SLMA002 - PowerPAD

Thermally Enhanced Package.

TI recommends six layers as the TMDS171 is a two voltage rail device.

•

Routing the high-speed TMDS traces on the top layer avoids the use of vias. (and the introduction of their

inductances) and allows for clean interconnects from the HDMI connectors to the retimer inputs and outputs.

It is important to match the electrical length of these high speed traces to minimize both inter-pair and intra-

pair skew.

•

Placing a solid ground plane next to the high-speed signal layer establishes controlled impedance for

transmission link interconnects and provides an excellent low –inductance path for the return current flow.

•

Placing a power plane next to the ground plane creates an additional high-frequency bypass capacitance.

Routing slower seed control signals on the bottom layer allows for greater flexibility as these signal links

usually have margin to tolerate discontinuities such as vias.

•

If an additional supply voltage plane or signal layer is needed, add a second power/ground plane system to

the stack to keep symmetry. This makes the stack mechanically stable and prevents it from warping. Also the

power and ground plane of each power system can be place closer together, thus increasing the high

frequency bypass capacitance significantly.

[ayer 1: Çꢀꢁ{ signal layer

5 to 10 mils

20 to 40 mils

5 to 10 mils

[ayer 2: Dround ꢂlane

[ayer 3: ë_//ꢂower ꢂlane

[ayer 4: ë_ꢁꢁꢂower ꢂlane

[ayer 5: Dround ꢂlane

[ayer 3: ꢂower ꢂlane

[ayer 4: /ontrol signal layer

[ayer 6: /ontrol signal layer

Figure 62. Recommended 4 or 6 Layer PCB Stack

52

TMDS171, TMDS171I

www.ti.com.cn

ZHCSEG5E –OCTOBER 2015–REVISED SEPTEMBER 2017

11.2 Layout Example

1µC

!ꢄ/_ꢆÜÇ

ꢀꢀQ

Db5

1µC

{ꢁ5LC_Lb

{5!_{bY

{/[_{ꢄ/

2kQ

ë_//

2kQ

ꢀë

2kQ

ë_//

ꢀë

{5!_{ꢄ/

{/[_{bY

aꢂtch Iigh {peed trꢂces

length ꢂs close ꢂs possiꢃle to

minimize {kew

6ꢀkQ

ë_//

{í!ꢁꢅꢁꢆ[

6ꢀkQ

Db5

6ꢀkQ

ë_//

Çó_Ç9ꢄa_/Ç[

1

6ꢀkQ

Db5

Lb_52pꢅn

ꢆÜÇ_52pꢅn

Iꢁ5_{bY

Iꢁ5_{ꢄ/

Lb_51pꢅn

ꢆÜÇ_51pꢅn

Db5

Lb_50pꢅn

ꢆÜÇ_50pꢅn

6ꢀkQ

ë_//

6ꢀkQ

ë_//

!1

L2/_9bꢅꢁLb

6ꢀkQ

Db5

6ꢀkQ

Db5

ꢆÜÇ_/[Ypꢅn

Lb_/[Ypꢅn

{/[_/Ç[

ꢁlꢂce ë_//ꢂnd ë₅₅decoupling

cꢂps ꢂs close to ë_//ꢂnd ë₅₅

pins ꢂs possiꢃle

ë_//

2kQ

ë{!5W

{5!_/Ç[

aꢂtch Iigh {peed trꢂces

length ꢂs close ꢂs possiꢃle to

minimize {kew

(1) If ARC is not used a 500KΩ resistor should be tied to GND at the SPDIF_IN pin

(2) The 55-Ω resistor to GND on the ARC_OUT pin is implementation specific and my not be needed if it is already

implemented elsewhere.

Figure 63. Layout

53

TMDS171, TMDS171I

ZHCSEG5E –OCTOBER 2015–REVISED SEPTEMBER 2017

www.ti.com.cn

12 器件和文档支持

12.1 相关文档ꢀ

[HDMI] 高清多媒体接口规范版本 1.4b，2011 年 10 月

[HDMI] 高清多媒体接口 CTS 版本 1.4b，2011 年 10 月

[I2C] I2C 总线规范版本 2.1，2000 年 1 月

12.2 接收文档更新通知

要接收文档更新通知，请导航至 TI.com 上的器件产品文件夹。单击右上角的通知我进行注册，即可每周接收产品

信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

12.3 社区资源

下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，

并且不一定反映 TI 的观点；请参阅 TI 的《使用条款》。

TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在

e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。

设计支持

TI 参考设计支持可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。

12.4 商标

PowerPAD, E2E are trademarks of Texas Instruments.

is a trademark of ~HDMI.

12.5 静电放电警告

这些装置包含有限的内置 ESD 保护。存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损

伤。

12.6 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

13 机械、封装和可订购信息

以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。这些数据如有变更，恕不另行通知

和修订此文档。如欲获取此数据表的浏览器版本，请参阅左侧的导航。

54

GENERIC PACKAGE VIEW

RGZ 48

7 x 7, 0.5 mm pitch

VQFN - 1 mm max height

PLASTIC QUADFLAT PACK- NO LEAD

Images above are just a representation of the package family, actual package may vary.

Refer to the product data sheet for package details.

4224671/A

www.ti.com

PACKAGE OUTLINE

RGZ0048B

VQFN - 1 mm max height

S

C

A

L

E

2

.

0

PLASTIC QUAD FLATPACK - NO LEAD

7.15

6.85

A

B

PIN 1 INDEX AREA

7.15

6.85

1 MAX

C

SEATING PLANE

0.05

0.00

0.08 C

2X 5.5

4.1 0.1

(0.2) TYP

EXPOSED

THERMAL PAD

13

24

44X 0.5

12

25

49

SYMM

2X

5.5

0.30

0.18

36

48X

1

0.1

0.05

C B A

48

37

SYMM

PIN 1 ID

(OPTIONAL)

0.5

0.3

48X

4218795/B 02/2017

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

www.ti.com

EXAMPLE BOARD LAYOUT

RGZ0048B

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(

4.1)

(1.115) TYP

(0.685)

TYP

37

48

48X (0.6)

1

36

48X (0.24)

(1.115)

TYP

44X (0.5)

(0.685)

TYP

SYMM

49

(

0.2) TYP

VIA

(6.8)

(R0.05)

TYP

12

25

13

24

SYMM

(6.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:12X

0.07 MIN

ALL AROUND

0.07 MAX

ALL AROUND

SOLDER MASK

OPENING

METAL

EXPOSED METAL

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

NON SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4218795/B 02/2017

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

www.ti.com

EXAMPLE STENCIL DESIGN

RGZ0048B

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(1.37)

TYP

37

48

48X (0.6)

1

36

48X (0.24)

44X (0.5)

(1.37)

TYP

SYMM

49

(R0.05) TYP

(6.8)

9X

METAL

TYP

(

1.17)

12

25

13

24

SYMM

(6.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD 49

73% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE

SCALE:12X

4218795/B 02/2017

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

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型号：	TMDS171IRGZT
厂家：	TEXAS INSTRUMENTS
描述：	3.4Gbps HDMI 1.4b TMDS 重定时器 \| RGZ \| 48 \| -40 to 85 商用集成电路
文件：	总63页 (文件大小：3303K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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