TMP105YZCT [TI]

具有 I2C/SMBus 接口和警报功能的 ±2°C、2.6V 至 3.3V 数字温度传感器 | YZC | 6 | -40 to 125;


型号：	TMP105YZCT
厂家：	TEXAS INSTRUMENTS
描述：	具有 I2C/SMBus 接口和警报功能的 ±2°C、2.6V 至 3.3V 数字温度传感器 \| YZC \| 6 \| -40 to 125 温度传感输出元件传感器换能器温度传感器
文件：	总22页 (文件大小：477K)
中文：	中文翻译
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Chip-Scale

Package

TMP105

www.ti.com

SLLS648D –FEBRUARY 2005–REVISED SEPTEMBER 2011

Digital Temperature Sensor

with Two-Wire Interface

Check for Samples: TMP105

FEATURES

DESCRIPTION

The TMP105 is a two-wire, serial output temperature

sensor available in a WCSP package. Requiring no

external components, the TMP105 is capable of

reading temperatures with a resolution of 0.0625°C.

•

SUPPORTS 1.8V I²C™ BUS

•

TWO ADDRESSES

•

DIGITAL OUTPUT: Two-Wire Serial Interface

RESOLUTION: 9- to 12-Bits, User-Selectable

ACCURACY:

The TMP105 features a Two-Wire interface that is

SMBus-compatible, with the TMP105 allowing up to

two devices on one bus. The TMP105 features an

SMBus Alert function.

–

±2.0°C (max) from –25°C to +85°C

±3.0°C (max) from –40°C to +125°C

•

LOW QUIESCENT CURRENT:

50μA, 1.5μA Standby

NO POWER-UP SEQUENCE REQUIRED, I²C

PULLUPS CAN BE ENABLED PRIOR TO V+

The TMP105 is ideal for extended temperature

measurement in

computer, consumer, environmental, industrial, and

instrumentation applications.

variety of communication,

The TMP105 is specified for operation over a

temperature range of –40°C to +125°C.

APPLICATIONS

•

CELL PHONES

COMPUTER PERIPHERAL THERMAL

PROTECTION

•

NOTEBOOK COMPUTERS

BATTERY MANAGEMENT

THERMOSTAT CONTROLS

ENVIRONMENTAL MONITORING AND HVAC

Temperature

YZC LEAD- FREE

2 X 3 ARRAY

(TOP VIEW)

Diode

Control

Logic

Temp.

SDA

GND

Sensor

SDA

SCL

V+

GND

ALERT

1,65 mm

1,50 mm

A/D

SCL

ALERT

Serial

Interface

Converter

Config.

and Temp.

V+

1,15 mm

1,00 mm

OSC

(Bump Side Down)

TMP105

Note: Pin A1 is marked with a 0 for Pb-free (YZC)

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

I²C is a trademark of NXP Semiconductors.

All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

TMP105

SLLS648D –FEBRUARY 2005–REVISED SEPTEMBER 2011

www.ti.com

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

ORDERING INFORMATION⁽¹⁾

PACKAGE

PART NUMBER

SYMBOL

Wafer chip-scale package (YZC)

TMP105YZC

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the

product folder at www.ti.com.

ABSOLUTE MAXIMUM RATINGS⁽¹⁾

Power Supply, V+

7.0V

Input Voltage⁽²⁾

–0.5V to 7.0V

10mA

Input Current

Operating Temperature Range

Storage Temperature Range

Junction Temperature (T_Jmax)

–55°C to +127°C

–60°C to +130°C

+150°C

ESD Rating:

Human Body Model (HBM)⁽³⁾

2000V

Charged-Device Model (CDM)⁽⁴⁾

Machine Model (MM)⁽⁵⁾

500V

200V

(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may

degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond

those specified is not implied.

(2) Input voltage rating applies to all TMP105 input voltages.

(3) HBM testing has been tested to TI specifications JEDEC JESD22-A114C.01.

(4) CDM testing has been tested to TI specifications JEDEC EIA/JESD22-A115A.

(5) MM testing has been tested to TI specifications JEDEC JESD22-C101C.

PIN ASSIGNMENTS

WCSP-6 PACKAGE

(TOP VIEW)

SDA

SCL

V+

GND

ALERT

(Bump Side Down)

Note: Pin 1 is determined by orienting the package marking as indicated in the diagram.

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ELECTRICAL CHARACTERISTICS

At T_A= –40°C to +125°C, and V+ = 2.6V to 3.3V, unless otherwise noted.

TMP105

UNIT

PARAMETER

CONDITION

MIN

TYP

MAX

TEMPERATURE INPUT

Range

–40

+125

±2.0

±3.0

±0.5

°C

Accuracy (Temperature Error)

–25°C to +85°C

–40°C to +125°C

±0.5

±1.0

°C

vs Supply

Resolution⁽¹⁾

0.2

°C/V

°C

Selectable

0.0625

DIGITAL INPUT/OUTPUT

(SCL, SDA, ALERT)

Input Capacitance

Input Logic Levels:

V_IH

1.2

6.0

0.6

V_IL

–0.5

Leakage Input Current, I_IN

Input Voltage Hysteresis

Output Logic Levels:

V_OLSDA

0V ≤ V_IN≤ 6V

μA

SCL and SDA Pins

100

I_OL= 3mA

I_OL= 4mA

Selectable

9-Bit

0.15

9 to 12

27.5

0.4

V_OLALERT

Resolution

Bits

Conversion Time

37.5

10-Bit

11-Bit

110

150

300

12-Bit

220

Timeout Time

DIGITAL INPUT (A0)

Input Capacitance

Input Logic Levels:

V_IH

0.7 x (V+)

(V+) + 0.5

0.3 x (V+)

V_IL

–0.5

Leakage Input Current, I_IN

POWER SUPPLY

Operating Range

Quiescent Current

0V ≤ V_IN≤ V+

μA

2.6

3.3

I_Q

Serial Bus Inactive

Serial Bus Active, SCL Freq = 400kHz

Serial Bus Inactive

100

1.5

μA

Shutdown Current

I_SD

Serial Bus Active, SCL Freq = 400kHz

TEMPERATURE RANGE

Specified Range

–40

–55

+125

+127

°C

Operating Range

Thermal Resistance

θ_JA

240

°C/W

(1) Specified for 12-bit resolution.

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TYPICAL CHARACTERISTICS

At T_A= +25°C and V+ = 2.8V, unless otherwise noted.

QUIESCENT CURRENT

SHUTDOWN CURRENT

TEMPERATURE

100

3.0

2.5

2.0

1.5

1.0

0.5

V+ = 2.6V

V+ = 3.3V

V+ = 2.6V

-50

-25

100

125

-50

-25

100

125

Temperature (°C)

CONVERSION TIME

TEMPERATURE ACCURACY

TEMPERATURE

2.0

1.5

225

220

215

210

205

200

1.0

V+ = 2.6V

V+ = 3.3V

0.5

V+ = 3.0V

V+ = 2.7V

-0.5

-1.0

-1.5

-2.0

12-Bit Resolution

75 100

3 typical units 12-bit resolution

-50

-25

125

-55

Temperature (°C)

-35 -15

105 125

Temperature (°C)

QUIESCENT CURRENT WITH BUS ACTIVITY

TEMPERATURE

500

450

400

350

300

250

200

150

100

+125°C

+25°C

-55°C

10k

100k

10M

Frequency (Hz)

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APPLICATIONS INFORMATION

The TMP105 is a digital temperature sensor that is optimal for thermal management and thermal protection

applications. The TMP105 is Two-Wire and SMBus interface-compatible, and is specified over a temperature

range of –40°C to +125°C.

The TMP105 requires no external components for operation except for pull-up resistors on SCL, SDA, and

ALERT, although a 0.1μF bypass capacitor is recommended, as shown in Figure 1. SCL, SDA and ALERT can

be tied to a 1.8V supply or V+ through pull-up resistors. A0 should be tied to V+ or GND.

V+

0.1mF

SCL B1

SDA A1

Two-Wire

Controller

TMP105

ALERT

(Output)

GND

Note: SCL, SDA, and ALERT pins require pull-up resistors.

Figure 1. Typical Connections of the TMP105

The sensing device of the TMP105 is the chip itself. Thermal paths run through the package leads. The lower

thermal resistance of metal causes the leads to provide the primary thermal path.

To maintain accuracy in applications requiring air or surface temperature measurement, care should be taken to

isolate the package and leads from ambient air temperature.

POINTER REGISTER

Figure 2 shows the internal register structure of the TMP105. The 8-bit Pointer Register of the devices is used to

address a given data register. The Pointer Register uses the two LSBs to identify which of the data registers

should respond to a read or write command. Table 1 identifies the bits of the Pointer Register byte. Table 2

describes the pointer address of the registers available in the TMP105. Power-up reset value of P1/P0 is 00.

Pointer

Temperature

SCL

Configuration

I/O

Control

Interface

T_LOW

SDA

T_HIGH

Figure 2. Internal Register Structure of the TMP105

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Table 1. Pointer Register Byte

Table 2. Pointer Addresses of the TMP105

Temperature Register (Read Only)

Configuration Register (Read/Write)

T_LOWRegister (Read/Write)

T_HIGHRegister (Read/Write)

TEMPERATURE REGISTER

The Temperature Register of the TMP105 is a 12-bit, read-only register that stores the output of the most recent

conversion. Two bytes must be read to obtain data, and are described in Table 3 and Table 4. Note that byte 1 is

the most significant byte; byte 2 is the least significant byte (sent in this order). The first 12 bits are used to

indicate temperature, with all remaining bits equal to zero. The least significant byte does not have to be read if

that information is not needed. Data format for temperature is summarized in Table 5. Following power-up or

reset, the Temperature Register will read 0°C until the first conversion is complete.

Table 3. Byte 1 of Temperature Register

T11

T10

Table 4. Byte 2 of Temperature Register

Table 5. Temperature Data Format

TEMPERATURE (°C)

DIGITAL OUTPUT (BINARY)

0111 1111 1111

0110 0100 0000

0101 0000 0000

0100 1011 0000

0011 0010 0000

0001 1001 0000

0000 0000 0100

0000 0000 0000

1111 1111 1100

1110 0111 0000

1100 1001 0000

HEX

7FF

640

500

4B0

320

190

004

000

FFC

E70

C90

128

127.9375

100

0.25

–0.25

–25

–55

The user can obtain 9, 10, 11, or 12 bits of resolution by addressing the Configuration Register and setting the

resolution bits accordingly. For 9-, 10-, or 11-bit resolution, the most significant bits in the Temperature Register

are used with the unused LSBs set to zero.

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CONFIGURATION REGISTER

The Configuration Register is an 8-bit read/write register used to store bits that control the operational modes of

the temperature sensor. Read/write operations are performed MSB first. The format of the Configuration register

for the TMP105 is shown in Table 6, followed by a breakdown of the register bits. The power-up/reset value of

the Configuration Register is all bits equal to 0.

Table 6. Configuration Register Format

BYTE

POL

SHUTDOWN MODE (SD)

The Shutdown Mode of the TMP105 allows the user to save maximum power by shutting down all device

circuitry other than the serial interface, which reduces current consumption to typically 1.5μA. Shutdown Mode is

enabled when the SD bit is 1; the device will shut down once the current conversion is completed. When SD is

equal to 0, the device will maintain a continuous conversion state.

THERMOSTAT MODE (TM)

The Thermostat Mode bit of the TMP105 indicates to the device whether to operate in Comparator Mode (TM =

0) or Interrupt Mode (TM = 1). For more information on comparator and interrupt modes, see the High and Low

Limit Registers section.

POLARITY (POL)

The Polarity Bit of the TMP105 allows the user to adjust the polarity of the ALERT pin output. If POL = 0, the

ALERT pin will be active LOW, as shown in Figure 3. For POL = 1, the ALERT pin will be active HIGH, and the

state of the ALERT pin is inverted.

T_HIGH

Measured

Temperature

T_LOW

TMP105 ALERT PIN

(Comparator Mode)

POL = 0

TMP105 ALERT PIN

(Interrupt Mode)

POL = 0

TMP105 ALERT PIN

(Comparator Mode)

POL = 1

TMP105 ALERT PIN

(Interrupt Mode)

POL = 1

Read

Time

Read

Figure 3. Output Transfer Function Diagrams

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FAULT QUEUE (F1/F0)

A fault condition is defined as when the measured temperature exceeds the user-defined limits set in the T_HIGH

and T_LOWRegisters. Additionally, the number of fault conditions required to generate an alert may be

programmed using the fault queue. The fault queue is provided to prevent a false alert as a result of

environmental noise. The fault queue requires consecutive fault measurements in order to trigger the alert

function. Table 7 defines the number of measured faults that may be programmed to trigger an alert condition in

the device. For T_HIGHand T_LOWregister format and byte order, see the High and Low Limit Registers section.

Table 7. Fault Settings of the TMP105

CONSECUTIVE FAULTS

CONVERTER RESOLUTION (R1/R0)

The Converter Resolution bits control the resolution of the internal analog-to-digital (A/D) converter. This control

allows the user to maximize efficiency by programming for higher resolution or faster conversion time. Table 8

identifies the resolution bits and the relationship between resolution and conversion time.

Table 8. Resolution of the TMP105

CONVERSION TIME

RESOLUTION

(typical)

27.5ms

55ms

9 Bits (0.5°C)

10 Bits (0.25°C)

11 Bits (0.125°C)

12 Bits (0.0625°C)

110ms

220ms

ONE-SHOT (OS)

The TMP105 features a One-Shot Temperature Measurement Mode. When the device is in Shutdown Mode,

writing a ‘1’ to the OS bit starts a single temperature conversion. The device will return to the shutdown state at

the completion of the single conversion. This option is useful to reduce power consumption in the TMP105 when

continuous temperature monitoring is not required. When the Configuration Register is read, the OS always

reads zero.

HIGH AND LOW LIMIT REGISTERS

In Comparator Mode (TM = 0), the ALERT pin of the TMP105 becomes active when the temperature equals or

exceeds the value in T_HIGHand generates a consecutive number of faults according to fault bits F1 and F0. The

ALERT pin remains active until the temperature falls below the indicated T_LOWvalue for the same number of

faults.

In Interrupt Mode (TM = 1), the ALERT pin becomes active when the temperature equals or exceeds T_HIGHfor a

consecutive number of fault conditions. The ALERT pin remains active until a read operation of any register

occurs, or until the device successfully responds to the SMBus Alert Response address. The ALERT pin clears if

the device is placed in Shutdown Mode. Once the ALERT pin is cleared, it will only become active again by the

temperature falling below T_LOW. When the temperature falls below T_LOW, the ALERT pin becomes active and

remains active until cleared by a read operation of any register or a successful response to the SMBus Alert

Response address. When the ALERT pin clears, the above cycle will repeat, with the ALERT pin becoming

active when the temperature equals or exceeds T_HIGH. The ALERT pin can also be cleared by resetting the

device with the General Call Reset command. This reset also clears the state of the internal registers in the

device returning the device to Comparator Mode (TM = 0).

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Both operational modes are represented in Figure 3. Table 9 and Table 10 describe the format for the T_HIGHand

T_LOWRegisters. Note that the most significant byte is sent first, followed by the least significant byte. Power-up

reset values for T_HIGHand T_LOWare:

T_HIGH= 80°C and T_LOW= 75°C

The format of the data for T_HIGHand T_LOWis the same as for the Temperature Register.

Table 9. Bytes 1 and 2 of T_HIGHRegister

BYTE

H11

H10

BYTE

Table 10. Bytes 1 and 2 of T_LOWRegister

BYTE

L11

L10

BYTE

All 12 bits for the Temperature, T_HIGH, and T_LOWRegisters are used in the comparisons for the ALERT function

for all converter resolutions. The three LSBs in T_HIGHand T_LOWcan affect the ALERT output even if the converter

is configured for 9-bit resolution.

SERIAL INTERFACE

The TMP105 operates only as a slave device on the Two-Wire bus and SMBus. Connections to the bus are

made via the open-drain I/O lines SDA and SCL. The SDA and SCL pins feature integrated spike suppression

filters and Schmitt triggers to minimize the effects of input spikes and bus noise. The TMP105 supports the

transmission protocol for fast (1kHz to 400kHz) mode. All data bytes are transmitted MSB first.

SERIAL BUS ADDRESS

To communicate with the TMP105, the master must first address slave devices via a slave address byte. The

slave address byte consists of seven address bits, and a direction bit indicating the intent of executing a read or

write operation.

The TMP105 features one address pin allowing up to two devices to be connected per bus. Pin logic levels are

described in Table 11. The address pin of the TMP105 is read after reset, at start of communication, or in

response to a Two-Wire address acquire request. Following reading of the state of the pin, the address is latched

to minimize power dissipation associated with detection.

Table 11. Address Pin and Slave Addresses for the

TMP105

SLAVE ADDRESS

1001000

1001001

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BUS OVERVIEW

The device that initiates the transfer is called a master, and the devices controlled by the master are slaves. The

bus must be controlled by a master device that generates the serial clock (SCL), controls the bus access, and

generates the START and STOP conditions.

To address a specific device, a START condition is initiated, indicated by pulling the data-line (SDA) from a

HIGH to LOW logic level while SCL is HIGH. All slaves on the bus shift in the slave address byte, with the last bit

indicating whether a read or write operation is intended. During the ninth clock pulse, the slave being addressed

responds to the master by generating an Acknowledge and pulling SDA LOW.

Data transfer is then initiated and sent over eight clock pulses followed by an Acknowledge Bit. During data

transfer SDA must remain stable while SCL is HIGH, as any change in SDA while SCL is HIGH will be

interpreted as a control signal.

Once all data has been transferred, the master generates a STOP condition, indicated by pulling SDA from LOW

to HIGH while SCL is HIGH.

WRITING/READING TO THE TMP105

Accessing a particular register on the TMP105 is accomplished by writing the appropriate value to the Pointer

bit LOW. Every write operation to the TMP105 requires a value for the Pointer Register. (Refer to Figure 5.)

When reading from the TMP105, the last value stored in the Pointer Register by a write operation is used to

determine which register is read by a read operation. To change the register pointer for a read operation, a new

value must be written to the Pointer Register. This is accomplished by issuing a slave address byte with the R/W

bit LOW, followed by the Pointer Register byte. No additional data are required. The master can then generate a

START condition and send the slave address byte with the R/W bit HIGH to initiate the read command. See

Figure 6 for details of this sequence. If repeated reads from the same register are desired, it is not necessary to

continually send the Pointer Register byte, as the TMP105 remembers the Pointer Register value until it is

changed by the next write operation.

Note that register bytes are sent most significant byte first, followed by the least significant byte.

SLAVE MODE OPERATIONS

The TMP105 can operate as a slave receiver or slave transmitter.

Slave Receiver Mode:

The first byte transmitted by the master is the slave address, with the R/W bit LOW. The TMP105 then

acknowledges reception of a valid address. The next byte transmitted by the master is the Pointer Register. The

TMP105 then acknowledges reception of the Pointer Register byte. The next byte or bytes are written to the

may terminate data transfer by generating a START or STOP condition.

Slave Transmitter Mode:

The first byte is transmitted by the master and is the slave address, with the R/W bit HIGH. The slave

acknowledges reception of a valid slave address. The next byte is transmitted by the slave and is the most

significant byte of the register indicated by the Pointer Register. The master acknowledges reception of the data

byte. The next byte transmitted by the slave is the least significant byte. The master acknowledges reception of

the data byte. The master may terminate data transfer by generating a Not-Acknowledge on reception of any

data byte, or generating a START or STOP condition.

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SMBus ALERT FUNCTION

The TMP105 supports the SMBus Alert function. When the TMP105 is operating in Interrupt Mode (TM = 1), the

ALERT pin of the TMP105 may be connected as an SMBus Alert signal. When a master senses that an ALERT

condition is present on the ALERT line, the master sends an SMBus Alert command (00011001) on the bus. If

the ALERT pin of the TMP105 is active, the devices will acknowledge the SMBus Alert command and respond by

returning its slave address on the SDA line. The eighth bit (LSB) of the slave address byte will indicate if the

temperature exceeding T_HIGHor falling below T_LOWcaused the ALERT condition. This bit will be HIGH if the

temperature is greater than or equal to T_HIGH. This bit will be LOW if the temperature is less than T_LOW. Refer to

Figure 7 for details of this sequence.

If multiple devices on the bus respond to the SMBus Alert command, arbitration during the slave address portion

of the SMBus Alert command will determine which device will clear its ALERT status. If the TMP105 wins the

arbitration, its ALERT pin will become inactive at the completion of the SMBus Alert command. If the TMP105

loses the arbitration, its ALERT pin will remain active.

GENERAL CALL

The TMP105 responds to a Two-Wire General Call address (0000000) if the eighth bit is 0. The device will

acknowledge the General Call address and respond to commands in the second byte. If the second byte is

00000100, the TMP105 will latch the status of the address pin, but will not reset. If the second byte is 00000110,

the TMP105 will latch the status of the address pin and reset the internal registers to their power-up values.

TIMEOUT FUNCTION

The TMP105 will reset the serial interface if either SCL or SDA are held LOW for 54ms (typ) between a START

and STOP condition. The TMP105 will release the bus if it is pulled LOW and will wait for a START condition. To

avoid activating the timeout function, it is necessary to maintain a communication speed of at least 1kHz for SCL

operating frequency.

TIMING DIAGRAMS

The TMP105 is Two-Wire and SMBus-compatible. Figure 4 to Figure 7 describe the various operations on the

TMP105. Bus definitions are given below. Parameters for Figure 4 are defined in Table 12.

Bus Idle:

Both SDA and SCL lines remain HIGH.

Start Data Transfer:

A change in the state of the SDA line, from HIGH to LOW, while the SCL line is HIGH, defines a START

condition. Each data transfer is initiated with a START condition.

Stop Data Transfer:

A change in the state of the SDA line from LOW to HIGH while the SCL line is HIGH defines a STOP condition.

Each data transfer is terminated with a repeated START or STOP condition.

Data Transfer:

The number of data bytes transferred between a START and a STOP condition is not limited and is determined

by the master device. The receiver acknowledges the transfer of data.

Acknowledge:

Each receiving device, when addressed, is obliged to generate an Acknowledge bit. A device that acknowledges

must pull down the SDA line during the Acknowledge clock pulse in such a way that the SDA line is stable LOW

during the HIGH period of the Acknowledge clock pulse. Setup and hold times must be taken into account. On a

master receive, the termination of the data transfer can be signaled by the master generating a Not-Acknowledge

on the last byte that has been transmitted by the slave.

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UNITS

Table 12. Timing Diagram Definitions for the TMP105

FAST MODE

PARAMETER

MIN

MAX

SCL Operating Frequency

f_(SCL)

t_(BUF)

400

kHz

Bus Free Time Between STOP and START Condition

600

Hold time after repeated START condition.

After this period, the first clock is generated.

t_(HDSTA)

100

Repeated START Condition Setup Time

STOP Condition Setup Time

Data Hold Time

t_(SUSTA)

t_(SUSTO)

t_(HDDAT)

t_(SUDAT)

100

Data Setup Time

100

SCL Clock LOW Period

SCL Clock HIGH Period

Clock/Data Fall Time

t_(LOW)1300

t_(HIGH)600

t_F

300

Clock/Data Rise Time

for SCLK ≤ 100kHz

300

1000

t_R

TWO-WIRE TIMING DIAGRAMS

t_(LOW)

t_F

t_R

t_(HDSTA)

SCL

SDA

t_(SUSTO)

t_(HDSTA)

t_(HIGH)t_(SUSTA)

t_(HDDAT)

t_(SUDAT)

t_(BUF)

Figure 4. Two-Wire Timing Diagram

SCL

SDA

A0 R/W

Start By

Master

ACK By

TMP105

Frame 2 Pointer Register Byte

Frame 1 Two-Wire Slave Address Byte

SCL

(Continued)

SDA

D7 D6

D4 D3

D2 D1

(Continued)

ACK By

Stop By

Master

TMP105

Frame 3 Data Byte 1

Frame 4 Data Byte 2

Figure 5. Two-Wire Timing Diagram for TMP105 Write Word Format

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TMP105

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SLLS648D –FEBRUARY 2005–REVISED SEPTEMBER 2011

SCL

SDA

R/W

Start By

Master

ACK By

TMP105

Frame 1 Two-Wire Slave Address Byte

Frame 2 Pointer Register Byte

SCL

(Continued)

SDA

R/W

D4 D3

(Continued)

Start By

Master

ACK By

From

TMP105

ACK By

Master

TMP105

Frame 3 Two-Wire Slave Address Byte

Frame 4 Data Byte 1 Read Register

SCL

(Continued)

SDA

D7 D6

(Continued)

From

ACK By

Master

Stop By

Master

TMP105

Frame 5 Data Byte 2 Read Register

Figure 6. Two-Wire Timing Diagram for Read Word Format

ALERT

SCL

Status

SDA

R/W

Start By

Master

ACK By

From

TMP105

NACK By Stop By

Master Master

TMP105

Frame 1 SMBus ALERT Response Address Byte

Frame 2 Slave Address Byte

Figure 7. Timing Diagram for SMBus ALERT

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TMP105

SLLS648D –FEBRUARY 2005–REVISED SEPTEMBER 2011

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REVISION HISTORY

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision C (April, 2008) to Revision D

Page

•

Updated document format to current standards ................................................................................................................... 1

Added Absolute Maximum Ratings table .............................................................................................................................. 2

In the Electrical Specifications table, changed from: DIGITAL INPUT/OUTPUT to: DIGITAL INPUT/OUTPUT (SCL,

SDA, ALERT) ........................................................................................................................................................................ 3

•

In the Electrical Specifications table, added the DIGITAL INPUT (A0) section .................................................................... 3

Changed max spec for V_IHlogic level ................................................................................................................................... 3

Changed test conditions for leakage input current ............................................................................................................... 3

Updated Temperature Accuracy vs Temperature typical characteristic graph ..................................................................... 4

Added text to the Application Information section, first paragraph ....................................................................................... 5

Corrected typos in Figure 1 .................................................................................................................................................. 5

Changes from Revision B (January, 2006) to Revision C

Page

•

Added labels to Temperature Accuracy vs Temperature typical characteristic graph ......................................................... 4

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PACKAGE OPTION ADDENDUM

www.ti.com

10-Dec-2020

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

TMP105YZCR

TMP105YZCT

ACTIVE

DSBGA

YZC

3000 RoHS & Green

250 RoHS & Green

SNAGCU

Level-1-260C-UNLIM

-40 to 125

SNAGCU

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

10-Dec-2020

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

7-Jul-2023

TAPE AND REEL INFORMATION

REEL DIMENSIONS

TAPE DIMENSIONS

Reel

Diameter

Cavity

A0 Dimension designed to accommodate the component width

B0 Dimension designed to accommodate the component length

K0 Dimension designed to accommodate the component thickness

Overall width of the carrier tape

P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2

Q3 Q4

Q1 Q2

Q3 Q4

User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

TMP105YZCR

DSBGA

YZC

3000

178.0

8.4

1.24

1.7

0.76

4.0

8.0

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

7-Jul-2023

TAPE AND REEL BOX DIMENSIONS

Width (mm)

*All dimensions are nominal

Device

Package Type Package Drawing Pins

DSBGA YZC

SPQ

Length (mm) Width (mm) Height (mm)

220.0 220.0 35.0

TMP105YZCR

3000

Pack Materials-Page 2

PACKAGE OUTLINE

YZC0006

DSBGA - 0.625 mm max height

SCALE 9.000

DIE SIZE BALL GRID ARRAY

BALL A1

CORNER

0.625 MAX

SEATING PLANE

0.08 C

0.35

0.15

BALL TYP

0.5 TYP

0.25 TYP

SYMM

D: Max = 1.61 mm, Min = 1.55 mm

TYP

E: Max = 1.11 mm, Min = 1.05 mm

0.5

TYP

0.35

0.25

0.015

SYMM

C A

4219522/A 02/2015

NanoFree Is a trademark of Texas Instruments.

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. NanoFree^TMpackage configuration.

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EXAMPLE BOARD LAYOUT

YZC0006

DSBGA - 0.625 mm max height

DIE SIZE BALL GRID ARRAY

(0.5) TYP

6X ( 0.265)

(0.5) TYP

SYMM

LAND PATTERN EXAMPLE

SCALE:30X

0.05 MAX

0.05 MIN

(

0.265)

METAL

UNDER

SOLDER MASK

(

0.265)

SOLDER MASK

OPENING

SOLDER MASK

OPENING

NON-SOLDER MASK

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

NOT TO SCALE

4219522/A 02/2015

NOTES: (continued)

4. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.

For more information, see Texas Instruments literature number SNVA009 (www.ti.com/lit/snva009).

www.ti.com

EXAMPLE STENCIL DESIGN

YZC0006

DSBGA - 0.625 mm max height

DIE SIZE BALL GRID ARRAY

(0.5) TYP

6X ( 0.25)

(R0.05) TYP

(0.5)

TYP

SYMM

METAL

TYP

SYMM

SOLDER PASTE EXAMPLE

BASED ON 0.1 mm THICK STENCIL

SCALE:40X

4219522/A 02/2015

NOTES: (continued)

5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.

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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD

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These resources are subject to change without notice. TI grants you permission to use these resources only for development of an

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TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE

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