TMP106YZCR [TI]
具有 I2C/SMBus 接口和警报功能的 ±2°C、2.7V 至 5.5V 数字温度传感器 | YZC | 6 | -40 to 125;
| 型号： | TMP106YZCR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有 I2C/SMBus 接口和警报功能的 ±2°C、2.7V 至 5.5V 数字温度传感器 | YZC | 6 | -40 to 125 温度传感 传感器 温度传感器 |
| 文件： | 总21页 (文件大小：461K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TMP106
Chip-Scale
Package
SLLS672A − OCTOBER 2005 − REVISED JANUARY 2006
Digital Temperature Sensor
with Two-Wire Interface
FD EATURES
DESCRIPTION
TWO ADDRESSES
The TMP106 is a two-wire, serial output temperature
D
D
D
DIGITAL OUTPUT: Two-Wire Serial Interface
RESOLUTION: 9- to 12-Bits, User-Selectable
sensor available in a WCSP package. Requiring no
external components, the TMP106 is capable of reading
temperatures with a resolution of 0.0625°C.
ACCURACY:
2.0°C (max) from −25°C to +85°C
3.0°C (max) from −40°C to +125°C
The TMP106 features a Two-Wire interface that is
SMBus-compatible, with the TMP106 allowing up to two
devices on one bus. The TMP106 also features an SMBus
Alert function.
D
D
LOW QUIESCENT CURRENT:
50µA, 0.1µA Standby
NO POWER-UP SEQUENCE REQUIRED, I C
PULLUPS CAN BE ENABLED PRIOR TO V+
2
The TMP106 is ideal for extended temperature
measurement in a variety of communication, computer,
consumer, environmental, industrial, and instrumentation
applications.
AD PPLICATIONS
NOTEBOOK COMPUTERS
D
COMPUTER PERIPHERAL THERMAL
PROTECTION
The TMP106 is specified for operation over a temperature
range of −40°C to +125°C.
D
D
D
D
CELL PHONES
BATTERY MANAGEMENT
THERMOSTAT CONTROLS
ENVIRONMENTAL MONITORING AND HVAC
Temperature
Diode
YZC LEAD−FREE
2 X 3 ARRAY
(TOP VIEW)
A1
Control
Logic
A2
B2
Temp.
SDA
GND
Sensor
A1
B1
A2
B2
SDA
SCL
V+
GND
ALERT
A0
1,65 mm
1,50 mm
B1
∆Σ
A/D
Converter
SCL
ALERT
Serial
Interface
C2
C1
C1
C2
Config.
and Temp.
Register
V+
A0
OSC
1,15 mm
1,00 mm
(Bump Side Down)
TMP106
Note: Pin A1 is marked with a ‘0’for Pb−free (YZC)
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
ꢀꢁ ꢂ ꢃꢄ ꢅ ꢆꢇ ꢂꢈ ꢃ ꢉꢆꢉ ꢊꢋ ꢌꢍ ꢎ ꢏꢐ ꢑꢊꢍꢋ ꢊꢒ ꢓꢔ ꢎ ꢎ ꢕꢋꢑ ꢐꢒ ꢍꢌ ꢖꢔꢗ ꢘꢊꢓ ꢐꢑꢊ ꢍꢋ ꢙꢐ ꢑꢕꢚ ꢀꢎ ꢍꢙꢔ ꢓꢑꢒ
ꢓ ꢍꢋ ꢌꢍꢎ ꢏ ꢑꢍ ꢒ ꢖꢕ ꢓ ꢊ ꢌꢊ ꢓ ꢐ ꢑꢊ ꢍꢋꢒ ꢖ ꢕꢎ ꢑꢛꢕ ꢑꢕ ꢎ ꢏꢒ ꢍꢌ ꢆꢕꢜ ꢐꢒ ꢇꢋꢒ ꢑꢎ ꢔꢏ ꢕꢋꢑ ꢒ ꢒꢑ ꢐꢋꢙ ꢐꢎ ꢙ ꢝ ꢐꢎ ꢎ ꢐ ꢋꢑꢞꢚ
ꢀꢎ ꢍ ꢙꢔꢓ ꢑ ꢊꢍ ꢋ ꢖꢎ ꢍ ꢓ ꢕ ꢒ ꢒ ꢊꢋ ꢟ ꢙꢍ ꢕ ꢒ ꢋꢍꢑ ꢋꢕ ꢓꢕ ꢒꢒ ꢐꢎ ꢊꢘ ꢞ ꢊꢋꢓ ꢘꢔꢙ ꢕ ꢑꢕ ꢒꢑꢊ ꢋꢟ ꢍꢌ ꢐꢘ ꢘ ꢖꢐ ꢎ ꢐꢏ ꢕꢑꢕ ꢎ ꢒꢚ
Copyright 2005−2006, Texas Instruments Incorporated
www.ti.com
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SLLS672A − OCTOBER 2005 − REVISED JANUARY 2006
This integrated circuit can be damaged by ESD. Texas
Instruments recommends that all integrated circuits be
(1)
ABSOLUTE MAXIMUM RATINGS
Power Supply, V+ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0V
handledwith appropriate precautions. Failure to observe
(2)
proper handling and installation procedures can cause damage.
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5V to 7.0V
Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10mA
Operating Temperature Range . . . . . . . . . . . . . . . −55°C to +127°C
Storage Temperature Range . . . . . . . . . . . . . . . . . −60°C to +130°C
ESD damage can range from subtle performance degradation to
complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could
cause the device not to meet its published specifications.
Junction Temperature (T max) . . . . . . . . . . . . . . . . . . . . . . +150°C
J
(3)
:
ESD Rating
Human Body Model (HBM) . . . . . . . . . . . . . . . . . . . . . . . 2000V
Charged-Device Model (CDM) . . . . . . . . . . . . . . . . . . . . . . 500V
Machine Model (MM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200V
(1)
Stresses above these ratings may cause permanent damage.
Exposure to absolute maximum conditions for extended periods
may degrade device reliability. These are stress ratings only, and
functional operation of the device at these or any other conditions
beyond those specified is not supported.
(2)
(3)
Input voltage rating applies to all TMP106 input voltages.
ESD testing has been tested to TI specifications JEDEC
J−Std 020.
(1)
ORDERING INFORMATION
PACKAGE
PART NUMBER
SYMBOL
Wafer chip-scale package (YZC)
TMP106YZC
F7
(1)
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website
at www.ti.com.
PIN ASSIGNMENTS
WCSP−6 PACKAGE
(TOP VIEW)
A1
B1
A2
B2
SDA
SCL
V+
GND
ALERT
A0
C2
C1
(Bump Side Down)
Note: Pin 1 is determined by orienting the package marking as indicated in the diagram.
2
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SLLS672A − OCTOBER 2005 − REVISED JANUARY 2006
ELECTRICAL CHARACTERISTICS
At T = −40°C to +125°C, and V+ = 2.7V to 5.5V, unless otherwise noted.
A
TMP106
UNITS
PARAMETER
CONDITION
MIN
TYP
MAX
TEMPERATURE INPUT
Range
−40
+125
2.0
°C
°C
Accuracy (Temperature Error)
−25°C to +85°C
−40°C to +125°C
0.5
1.0
3.0
°C
vs Supply
0.2
0.5
°C/V
°C
(1)
Resolution
Selectable
0.0625
DIGITAL INPUT/OUTPUT
Input Capacitance
3
pF
Input Logic Levels:
V
V
2.1
6.0
0.8
1
V
V
IH
IL
−0.5
Leakage Input Current, I
Input Voltage Hysteresis
Output Logic Levels:
0V ≤ V ≤ 6V
µA
mV
IN
IN
SCL and SDA Pins
250
V
V
SDA
I
I
= 3mA
= 4mA
0
0
0.15
0.15
9 to 12
27.5
55
0.4
0.4
V
OL
OL
ALERT
V
OL
OL
Resolution
Selectable
9-Bit
Bits
ms
ms
ms
ms
ms
Conversion Time
37.5
75
10-Bit
11-Bit
110
150
300
74
12-Bit
220
Timeout Time
25
54
POWER SUPPLY
Operating Range
Quiescent Current
2.7
5.5
85
V
I
Serial Bus Inactive
50
100
410
0.1
60
µA
µA
µA
µA
µA
µA
Q
Serial Bus Active, SCL Freq = 400kHz
Serial Bus Active, SCL Freq = 3.4MHz
Serial Bus Inactive
Shutdown Current
I
3
SD
Serial Bus Active, SCL Freq = 400kHz
Serial Bus Active, SCL Freq = 3.4MHz
380
TEMPERATURE RANGE
Specified Range
−40
−55
+125
+127
°C
°C
Operating Range
Thermal Resistance
q
JA
240
°C/W
(1)
Specified for 12-bit resolution.
3
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SLLS672A − OCTOBER 2005 − REVISED JANUARY 2006
TYPICAL CHARACTERISTICS
At T = +25°C and V+ = 5.0V, unless otherwise noted.
A
QUIESCENT CURRENT vs TEMPERATURE
60
SHUTDOWN CURRENT vs TEMPERATURE
V+ = 2.8V
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
V+ = 5V
50
40
V+ = 2.7V
30
20
10
Serial Bus Inactive
0
−
0.1
−
−
25
50
0
25
50
75
100
125
−
−
−
15
55
35
5
25
45
65
85
105 125
_
_
Temperature ( C)
Temperature ( C)
TEMPERATURE ACCURACY vs TEMPERATURE
CONVERSION TIME vs TEMPERATURE
300
2.0
1.5
1.0
0.5
0.0
250
200
150
100
V+ = 5V
V+ = 2.7V
−
−
−
−
0.5
1.0
1.5
2.0
3 typical units 12−bit resolution.
12−bit resolution.
75 100 125
−
−
−
15
55
35
5
25
45
65
85
105 125
−
−
25
50
0
25
50
_
_
Temperature ( C)
Temperature ( C)
QUIESCENT CURRENT WITH
BUS ACTIVITY vs TEMPERATURE
500
450
400
350
300
250
200
150
100
50
Hs MODE
FAST MODE
_
125 C
_
25 C
−
_
55 C
0
1k
10k
100k
Frequency (Hz)
1M
10M
4
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SLLS672A − OCTOBER 2005 − REVISED JANUARY 2006
APPLICATIONS INFORMATION
The TMP106 is a digital temperature sensor that is optimal
for thermal management and thermal protection
applications. The TMP106 is Two-Wire and SMBus
interface-compatible, and is specified over a temperature
range of −40°C to +125°C.
Pointer
Register
Temperature
Register
The TMP106 requires no external components for
operation except for pull-up resistors on SCL, SDA, and
ALERT, although
recommended, as shown in Figure 1.
a
0.1µF bypass capacitor is
SCL
SDA
Configuration
Register
I/O
Control
Interface
V+
TLOW
Register
µ
0.1 F
C1
THIGH
Register
SCL B1
SDA A1
C2
B2
To
Two−Wire
Controller
A0
TMP106
ALERT
(Output)
Figure 2. Internal Register Structure of the
TMP106
A2
P1
0
P0
0
REGISTER
NOTE: SCL, SDA, and ALERT
pins require pull−up resistors.
GND
TemperatureRegister (Read Only)
Configuration Register (Read/Write)
0
1
1
0
T
T
Register (Read/Write)
Register (Read/Write)
LOW
Figure 1. Typical Connections of the TMP106
1
1
HIGH
Table 2. Pointer Addresses of the TMP106
The sensing device of the TMP106 is the chip itself.
Thermal paths run through the package leads. The lower
thermal resistance of metal causes the leads to provide the
primary thermal path.
TEMPERATURE REGISTER
The Temperature Register of the TMP106 is a 12-bit,
read-only register that stores the output of the most recent
conversion. Two bytes must be read to obtain data, and are
described in Table 3 and Table 4. Note that byte 1 is the
most significant byte; byte 2 is the least significant byte.
The first 12 bits are used to indicate temperature, with all
remaining bits equal to zero. The least significant byte
does not have to be read if that information is not needed.
Data format for temperature is summarized in Table 5.
Following power-up or reset, the Temperature Register will
read 0°C until the first conversion is complete.
To maintain accuracy in applications requiring air or
surface temperature measurement, care should be taken
to isolate the package and leads from ambient air
temperature.
POINTER REGISTER
Figure 2 shows the internal register structure of the
TMP106. The 8-bit Pointer Register of the device is used
to address a given data register. The Pointer Register uses
the two LSBs to identify which of the data registers should
respond to a read or write command. Table 1 identifies the
bits of the Pointer Register byte. Table 2 describes the
pointer address of the registers available in the TMP106.
Power-up reset value of P1/P0 is 00.
D7
D6
D5
D4
D3
D2
D1
D0
T11
T10
T9
T8
T7
T6
T5
T4
Table 3. Byte 1 of Temperature Register
D7
D6
D5
D4
D3
D2
D1
D0
P7
P6
P5
P4
P3
P2
P1
P0
T3
T2
T1
T0
0
0
0
0
0
0
0
0
0
0
Register Bits
Table 1. Pointer Register Byte
Table 4. Byte 2 of Temperature Register
5
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SLLS672A − OCTOBER 2005 − REVISED JANUARY 2006
POLARITY (POL)
TEMPERATURE
DIGITAL OUTPUT
(BINARY)
(°C)
HEX
7FF
7FF
640
500
4B0
320
190
004
000
FFC
E70
C90
The Polarity Bit of the TMP106 allows the user to adjust the
polarity of the ALERT pin output. If POL = 0, the ALERT pin
will be active LOW, as shown in Figure 3. For POL = 1, the
ALERT pin will be active HIGH, and the state of the ALERT
pin is inverted.
128
127.9375
100
80
0111 1111 1111
0111 1111 1111
0110 0100 0000
0101 0000 0000
0100 1011 0000
0011 0010 0000
0001 1001 0000
0000 0000 0100
0000 0000 0000
1111 1111 1100
1110 0111 0000
1100 1001 0000
75
50
25
THIGH
0.25
0
Measured
Temperature
−0.25
−25
−55
TLOW
TMP106 ALERT PIN
(Comparator Mode)
POL = 0
Table 5. Temperature Data Format
The user can obtain 9, 10, 11, or 12 bits of resolution by
addressing the Configuration Register and setting the
resolution bits accordingly. For 9-, 10-, or 11-bit resolution,
the most significant bits in the Temperature Register are
used with the unused LSBs set to zero.
TMP106 ALERT PIN
(Interrupt Mode)
POL = 0
TMP106 ALERT PIN
(Comparator Mode)
POL = 1
TMP106 ALERT PIN
(Interrupt Mode)
POL = 1
CONFIGURATION REGISTER
The Configuration Register is an 8-bit read/write register
used to store bits that control the operational modes of the
temperature sensor. Read/write operations are performed
MSB first. The format of the Configuration Register for the
TMP106 is shown in Table 6, followed by a breakdown of
the register bits. The power-up/reset value of the
Configuration Register is all bits equal to 0.
Read
Read
Time
Read
Figure 3. Output Transfer Function Diagrams
FAULT QUEUE (F1/F0)
BYTE D7
OS
D6
D5
D4
D3
D2
D1
D0
A fault condition is defined as when the measured
temperature exceeds the user-defined limits set in the
THIGH and TLOW Registers. Additionally, the number of
fault conditions required to generate an alert may be
programmed using the fault queue. The fault queue is
provided to prevent a false alert as a result of
environmental noise. The fault queue requires
consecutive fault measurements in order to trigger the
alert function. Table 7 defines the number of measured
faults that may be programmed to trigger an alert condition
in the device. For THIGH and TLOW register format and byte
order, see the High and Low Limit Registers section.
1
R1
R0
F1
F0
POL
TM
SD
Table 6. Configuration Register Format
SHUTDOWN MODE (SD)
The Shutdown Mode of the TMP106 allows the user to
save maximum power by shutting down all device circuitry
other than the serial interface, which reduces current
consumption to typically less than 0.1µA. Shutdown Mode
is enabled when the SD bit is 1; the device will shut down
once the current conversion is completed. When SD is
equal to 0, the device will maintain a continuous
conversion state.
F1
0
F0
0
CONSECUTIVE FAULTS
THERMOSTAT MODE (TM)
1
2
4
6
The Thermostat Mode bit of the TMP106 indicates to the
device whether to operate in Comparator Mode (TM = 0)
or Interrupt Mode (TM = 1). For more information on
comparator and interrupt modes, see the High and Low
Limit Registers section.
0
1
1
0
1
1
Table 7. Fault Settings of the TMP106
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Response address. When the ALERT pin clears, the
above cycle will repeat, with the ALERT pin becoming
CONVERTER RESOLUTION (R1/R0)
The Converter Resolution bits control the resolution of the
internal analog-to-digital (A/D) converter. This control
allows the user to maximize efficiency by programming for
higher resolution or faster conversion time. Table 8
identifies the resolution bits and the relationship between
resolution and conversion time.
active when the temperature equals or exceeds THIGH
.
The ALERT pin can also be cleared by resetting the device
with the General Call Reset command. This reset also
clears the state of the internal registers in the device,
returning the device to Comparator Mode (TM = 0).
Both operational modes are represented in Figure 3.
Table 9 and Table 10 describe the format for the THIGH and
CONVERSION TIME
(typical)
27.5ms
55ms
R1
0
R0
0
RESOLUTION
9 Bits (0.5°C)
TLOW Registers. Note that the most significant byte is sent
first, followed by the least significant byte. Power-up reset
values for THIGH and TLOW are:
0
1
10 Bits (0.25°C)
11 Bits (0.125°C)
12 Bits (0.0625°C)
THIGH = 80°C and TLOW = 75°C
1
0
110ms
220ms
1
1
The format of the data for THIGH and TLOW is the same as
for the Temperature Register.
Table 8. Resolution of the TMP106
ONE-SHOT (OS)
BYTE D7
D6
D5
D4
D3
D2
D1
D0
The TMP106 features
a
One-Shot Temperature
1
H11 H10
H9
H8
H7
H6
H5
H4
Measurement Mode. When the device is in Shutdown
Mode, writing a ‘1’ to the OS bit starts a single temperature
conversion. The device will return to the shutdown state at
the completion of the single conversion. This option is
useful to reduce power consumption in the TMP106 when
continuous temperature monitoring is not required. When
the Configuration Register is read, the OS always reads
zero.
BYTE D7
H3
D6
D5
D4
D3
D2
D1
D0
2
H2
H1
H0
0
0
0
0
Table 9. Bytes 1 and 2 of T
Register
HIGH
BYTE D7
L11
D6
D5
D4
D3
D2
D1
D0
1
L10
L9
L8
L7
L6
L5
L4
BYTE D7
L3
D6
D5
D4
D3
D2
D1
D0
2
L2
L1
L0
0
0
0
0
HIGH AND LOW LIMIT REGISTERS
In Comparator Mode (TM = 0), the ALERT pin of the
TMP106 becomes active when the temperature equals or
exceeds the value in THIGH and generates a consecutive
number of faults according to fault bits F1 and F0. The
ALERT pin remains active until the temperature falls below
the indicated TLOW value for the same number of faults.
Table 10. Bytes 1 and 2 of T
Register
LOW
All 12 bits for the Temperature, THIGH, and TLOW Registers
are used in the comparisons for the ALERT function for all
converter resolutions. The three LSBs in THIGH and TLOW
can affect the ALERT output even if the converter is
configured for 9-bit resolution.
In Interrupt Mode (TM = 1), the ALERT pin becomes active
when the temperature equals or exceeds THIGH for a
consecutive number of fault conditions. The ALERT pin
remains active until a read operation of any register
occurs, or until the device successfully responds to the
SMBus Alert Response address. The ALERT pin clears if
the device is placed in Shutdown Mode. Once the ALERT
pin is cleared, it will only become active again by the
temperature falling below TLOW. When the temperature
falls below TLOW, the ALERT pin becomes active and
remains active until cleared by a read operation of any
register or a successful response to the SMBus Alert
SERIAL INTERFACE
The TMP106 operates only as a slave device on the
Two-Wire bus and SMBus. Connections to the bus are
made via the open-drain I/O lines SDA and SCL. The SDA
and SCL pins feature integrated spike suppression filters
and Schmitt triggers to minimize the effects of input spikes
and bus noise. The TMP106 supports the transmission
protocol for fast (1kHz to 400kHz) and high-speed (1kHz
to 3.4MHz) modes. All data bytes are transmitted MSB
first.
7
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SLLS672A − OCTOBER 2005 − REVISED JANUARY 2006
Data transfer is then initiated and sent over eight clock
pulses followed by an Acknowledge Bit. During data
transfer SDA must remain stable while SCL is HIGH, as
any change in SDA while SCL is HIGH will be interpreted
as a control signal.
SERIAL BUS ADDRESS
To communicate with the TMP106, the master must first
address slave devices via a slave address byte. The slave
address byte consists of seven address bits, and a
direction bit indicating the intent of executing a read or
write operation.
Once all data has been transferred, the master generates
a STOP condition, indicated by pulling SDA from LOW to
HIGH while SCL is HIGH.
The TMP106 features one address pin allowing up to two
devices to be connected per bus. Pin logic levels are
described in Table 11. The address pin of the TMP106 is
read after reset, at start of communication, or in response
to a Two-Wire address acquire request. Following the
reading of the pin state, the address is latched to minimize
power dissipation associated with detection.
WRITING/READING TO THE TMP106
Accessing a particular register on the TMP106 is
accomplished by writing the appropriate value to the
Pointer Register. The value for the Pointer Register is the
first byte transferred after the slave address byte with the
R/W bit LOW. Every write operation to the TMP106
requires a value for the Pointer Register. (Refer to
Figure 5.)
A0
0
SLAVE ADDRESS
1001000
1
1001001
Table 11. Address Pin and Slave Addresses for
the TMP106
When reading from the TMP106, the last value stored in
the Pointer Register by a write operation is used to
determine which register is read by a read operation. To
change the register pointer for a read operation, a new
value must be written to the Pointer Register. This is
accomplished by issuing a slave address byte with the
R/W bit LOW, followed by the Pointer Register byte. No
additional data are required. The master can then
generate a START condition and send the slave address
byte with the R/W bit HIGH to initiate the read command.
See Figure 6 for details of this sequence. If repeated reads
from the same register are desired, it is not necessary to
continually send the Pointer Register byte, as the TMP106
remembers the Pointer Register value until it is changed
by the next write operation.
BUS OVERVIEW
The device that initiates the transfer is called a master, and
the devices controlled by the master are slaves. The bus
must be controlled by a master device that generates the
serial clock (SCL), controls the bus access, and generates
the START and STOP conditions.
To address a specific device, a START condition is
initiated, indicated by pulling the data-line (SDA) from a
HIGH to LOW logic level while SCL is HIGH. All slaves on
the bus shift in the slave address byte, with the last bit
indicating whether a read or write operation is intended.
During the ninth clock pulse, the slave being addressed
responds to the master by generating an Acknowledge
and pulling SDA LOW.
Note that register bytes are sent most-significant byte first,
followed by the least-significant byte.
8
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SLLS672A − OCTOBER 2005 − REVISED JANUARY 2006
If multiple devices on the bus respond to the SMBus Alert
command, arbitration during the slave address portion of
the SMBus Alert command will determine which device
will clear its ALERT status. If the TMP106 wins the
arbitration, its ALERT pin will become inactive at the
completion of the SMBus Alert command. If the TMP106
loses the arbitration, its ALERT pin will remain active.
SLAVE MODE OPERATIONS
The TMP106 can operate as a slave receiver or slave
transmitter.
Slave Receiver Mode:
The first byte transmitted by the master is the slave
address, with the R/W bit LOW. The TMP106 then
acknowledges reception of a valid address. The next byte
transmitted by the master is the Pointer Register. The
TMP106 then acknowledges reception of the Pointer
Register byte. The next byte or bytes are written to the
register addressed by the Pointer Register. The TMP106
acknowledges reception of each data byte. The master
may terminate data transfer by generating a START or
STOP condition.
GENERAL CALL
The TMP106 responds to a Two-Wire General Call
address (0000000) if the eighth bit is 0. The device will
acknowledge the General Call address and respond to
commands in the second byte. If the second byte is
00000100, the TMP106 will latch the status of the address
pin, but will not reset. If the second byte is 00000110, the
TMP106 will latch the status of the address pin and reset
the internal registers to their power-up values.
Slave Transmitter Mode:
The first byte is transmitted by the master and is the slave
address, with the R/W bit HIGH. The slave acknowledges
reception of a valid slave address. The next byte is
transmitted by the slave and is the most significant byte of
the register indicated by the Pointer Register. The master
acknowledges reception of the data byte. The next byte
transmitted by the slave is the least significant byte. The
master acknowledges reception of the data byte. The
master may terminate data transfer by generating a
Not-Acknowledge on reception of any data byte, or
generating a START or STOP condition.
HIGH-SPEED MODE
In order for the Two-Wire bus to operate at frequencies
above 400kHz, the master device must issue an Hs-mode
master code (00001XXX) as the first byte after a START
condition to switch the bus to high-speed operation. The
TMP106 will not acknowledge this byte, but will switch its
input filters on SDA and SCL and its output filters on SDA
to operate in Hs-mode, allowing transfers at up to 3.4MHz.
After the Hs-mode master code has been issued, the
master will transmit a Two-Wire slave address to initiate a
data transfer operation. The bus will continue to operate in
Hs-mode until a STOP condition occurs on the bus. Upon
receiving the STOP condition, the TMP106 will switch the
input and output filters back to fast-mode operation.
SMBus ALERT FUNCTION
The TMP106 supports the SMBus Alert function. When
the TMP106 is operating in Interrupt Mode (TM = 1), the
ALERT pin of the TMP106 may be connected as an
SMBus Alert signal. When a master senses that an ALERT
condition is present on the ALERT line, the master sends
an SMBus Alert command (00011001) on the bus. If the
ALERT pin of the TMP106 is active, the devices will
acknowledge the SMBus Alert command and respond by
returning its slave address on the SDA line. The eighth bit
(LSB) of the slave address byte will indicate if the
temperature exceeding THIGH or falling below TLOW
caused the ALERT condition. This bit will be HIGH if the
temperature is greater than or equal to THIGH. This bit will
be LOW if the temperature is less than TLOW. Refer to
Figure 7 for details of this sequence.
TIMEOUT FUNCTION
The TMP106 will reset the serial interface if either SCL or
SDA are held LOW for 54ms (typ) between a START and
STOP condition. The TMP106 will release the bus if it is
pulled LOW and will wait for a START condition. To avoid
activating the timeout function, it is necessary to maintain
a communication speed of at least 1kHz for SCL operating
frequency.
9
ꢆ ꢠ ꢀꢡ ꢢ ꢣ
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SLLS672A − OCTOBER 2005 − REVISED JANUARY 2006
Data Transfer: The number of data bytes transferred
between a START and a STOP condition is not limited and
is determined by the master device. The receiver
acknowledges the transfer of data.
TIMING DIAGRAMS
The TMP106 is Two-Wire- and SMBus-compatible.
Figure 4 to Figure 7 describe the various operations on the
TMP106. Bus definitions are given below. Parameters for
Figure 4 are defined in Table 12.
Acknowledge: Each receiving device, when addressed,
is obliged to generate an Acknowledge bit. A device that
acknowledges must pull down the SDA line during the
Acknowledge clock pulse in such a way that the SDA line
is stable LOW during the HIGH period of the Acknowledge
clock pulse. Setup and hold times must be taken into
account. On a master receive, the termination of the data
transfer can be signaled by the master generating a
Not-Acknowledge on the last byte that has been
transmitted by the slave.
Bus Idle: Both SDA and SCL lines remain HIGH.
Start Data Transfer: A change in the state of the SDA line,
from HIGH to LOW, while the SCL line is HIGH, defines a
START condition. Each data transfer is initiated with a
START condition.
Stop Data Transfer: A change in the state of the SDA line
from LOW to HIGH while the SCL line is HIGH defines a
STOP condition. Each data transfer is terminated with a
repeated START or STOP condition.
FAST MODE
HIGH-SPEED MODE
PARAMETER
UNITS
MIN
MAX
MIN
0.001
160
MAX
SCL Operating Frequency
f
0.001
600
0.4
3.4
MHz
ns
(SCL)
t
(BUF)
Bus Free Time Between STOP and START Condition
Hold time after repeated START condition.
After this period, the first clock is generated.
t
100
100
ns
(HDSTA)
Repeated START Condition Setup Time
STOP Condition Setup Time
Data Hold Time
t
100
100
0
100
100
0
ns
ns
ns
ns
ns
ns
ns
(SUSTA)
t
(SUSTO)
t
(HDDAT)
Data Setup Time
t
100
1300
600
10
(SUDAT)
SCL Clock LOW Period
SCL Clock HIGH Period
Clock/Data Fall Time
t
160
60
(LOW)
t
(HIGH)
t
F
300
160
160
Clock/Data Rise Time
300
1000
ns
ns
t
R
for SCLK ≤ 100kHz
Table 12. Timing Diagram Definitions for the TMP106
TWO-WIRE TIMING DIAGRAMS
t(LOW)
tF
tR
t(HDSTA)
SCL
SDA
t(SUSTO)
t(HDSTA)
t(HIGH) t(SUSTA)
t(HDDAT)
t(SUDAT)
t(BUF)
P
S
S
P
Figure 4. Two-Wire Timing Diagram
10
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SLLS672A − OCTOBER 2005 − REVISED JANUARY 2006
1
9
1
0
9
SCL
SDA
…
1
1
0
0
1
0
0
A0 R/W
0
0
0
0
0
P1
P0
ACK By
…
Start By
Master
ACK By
TMP106
TMP106
Frame 2 Pointer Register Byte
Frame 1 Two−Wire Slave Address Byte
9
1
9
SCL
(Continued)
SDA
(Continued)
D7 D6 D5 D4 D3 D2 D1 D0
D7
D6 D5
D4 D3 D2 D1 D0
ACK By
TMP106
ACK By
TMP106
Stop By
Master
Frame 3 Data Byte 1
Frame 4 Data Byte 2
Figure 5. Two-Wire Timing Diagram for TMP106 Write Word Format
1
9
1
9
…
…
SCL
SDA
1
0
0
0
0
A0 R/W
0
0
0
0
0
0
P1
P0
Start By
Master
ACK By
TMP106
ACK By
TMP106
Frame 1 Two−Wire Slave Address Byte
Frame 2 Pointer Register Byte
1
9
1
9
SCL
(Continued)
…
SDA
(Continued)
…
0
0
A0
1
0
0
1
R/W
D7
D6
D5
D4 D3
D2
D1
D0
Start By
Master
ACK By
TMP106
From
TMP106
ACK By
Master
Frame 3 Two−Wire Slave Address Byte
9
Frame 4 Data Byte 1 Read Register
1
SCL
(Continued)
SDA
(Continued)
D7 D6
D5
D4
D3
D2
D1
D0
From
TMP106
ACK By
Master
Stop By
Master
Frame 5 Data Byte 2 Read Register
Figure 6. Two-Wire Timing Diagram for Read Word Format
11
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SLLS672A − OCTOBER 2005 − REVISED JANUARY 2006
ALERT
1
9
1
9
SCL
Status
SDA
0
0
0
1
1
0
0
R/W
1
0
0
1
0
0
A0
Start By
Master
ACK By
TMP106
From
TMP106
NACK By Stop By
Master Master
Frame 1 SMBus ALERT Response Address Byte
Frame 2 Slave Address Byte
Figure 7. Timing Diagram for SMBus ALERT
12
13
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TMP106YZCR
TMP106YZCT
ACTIVE
ACTIVE
DSBGA
DSBGA
YZC
YZC
6
6
3000 RoHS & Green
250 RoHS & Green
SNAGCU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
F7
F7
SNAGCU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jul-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TMP106YZCR
TMP106YZCT
DSBGA
DSBGA
YZC
YZC
6
6
3000
250
178.0
178.0
8.4
8.4
1.24
1.24
1.7
1.7
0.76
0.76
4.0
4.0
8.0
8.0
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jul-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TMP106YZCR
TMP106YZCT
DSBGA
DSBGA
YZC
YZC
6
6
3000
250
220.0
220.0
220.0
220.0
35.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
YZC0006
DSBGA - 0.625 mm max height
SCALE 9.000
DIE SIZE BALL GRID ARRAY
A
B
E
BALL A1
CORNER
D
0.625 MAX
C
SEATING PLANE
0.08 C
0.35
0.15
BALL TYP
0.5 TYP
0.25 TYP
C
SYMM
B
1
TYP
0.5
TYP
A
1
2
0.35
0.25
6X
0.015
SYMM
C A
B
4219522/A 02/2015
NanoFree Is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. NanoFreeTM package configuration.
www.ti.com
EXAMPLE BOARD LAYOUT
YZC0006
DSBGA - 0.625 mm max height
DIE SIZE BALL GRID ARRAY
(0.5) TYP
6X ( 0.265)
1
2
A
B
(0.5) TYP
SYMM
C
SYMM
LAND PATTERN EXAMPLE
SCALE:30X
0.05 MAX
0.05 MIN
(
0.265)
METAL
METAL
UNDER
SOLDER MASK
(
0.265)
SOLDER MASK
OPENING
SOLDER MASK
OPENING
NON-SOLDER MASK
SOLDER MASK
DEFINED
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
NOT TO SCALE
4219522/A 02/2015
NOTES: (continued)
4. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
For more information, see Texas Instruments literature number SNVA009 (www.ti.com/lit/snva009).
www.ti.com
EXAMPLE STENCIL DESIGN
YZC0006
DSBGA - 0.625 mm max height
DIE SIZE BALL GRID ARRAY
(0.5) TYP
6X ( 0.25)
(R0.05) TYP
1
2
A
B
(0.5)
TYP
SYMM
METAL
TYP
C
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
SCALE:40X
4219522/A 02/2015
NOTES: (continued)
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
www.ti.com
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