TMP6331QDYATQ1 [TI]
TMP63-Q1 ±1% 100-kΩ Automotive Grade Linear Thermistor With 0402 and 0603 Package Options;
| 型号： | TMP6331QDYATQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | TMP63-Q1 ±1% 100-kΩ Automotive Grade Linear Thermistor With 0402 and 0603 Package Options |
| 文件： | 总26页 (文件大小：1155K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TMP63-Q1
SNIS215C – JANUARY 2020 – REVISED SEPTEMBER 2020
TMP63-Q1 ±1% 100-kΩ Automotive Grade Linear Thermistor With 0402 and 0603
Package Options
1 Features
3 Description
•
•
AEC-Q100 qualified for automotive applications
Temperature Options:
– X1SON/DEC package grade 1: –40 °C ≤ TA ≤
125 °C
Get started today with the Thermistor Design Tool,
offering complete resistance vs temperature table (R-
T table) computation, other helpful methods to derive
temperature and example C-code.
– SOT-5X3/DYA package grade 0: –40 °C ≤ TA ≤
150 °C
Silicon-based thermistor with a
positive temperature coefficient (PTC)
Linear resistance change across temperature
100-kΩ nominal resistance at 25 °C (R25)
– ±1% maximum (0 °C to 70 °C)
Consistent sensitivity across temperature
– 6400 ppm/°C TCR (25 °C)
Linear thermistors offer linearity and consistent
sensitivity across temperature to enable simple and
accurate methods for temperature conversion. Low
power consumption and a small thermal mass
minimize the impact of self-heating. With built-in
failsafe behavior at high temperatures and powerful
immunity to environmental variation, these devices
are designed for a long lifetime of high performance.
The small size of the TMP6 series also allows for
close placement to heat sources and quick response
times.
•
•
•
•
– 0.2% typical TCR tolerance across temperature
range
Take advantage of benefits over NTC thermistors
such as no extra linearization circuitry, minimized
calibration, less resistance tolerance variation, larger
sensitivity at high temperatures, and simplified
conversion methods to save time and memory in the
processor.
•
•
Fast thermal response time of 0.6 s (DEC)
Long lifetime and robust performance
– Built-in fail-safe in case of short-circuit failures
– 0.3% typical long term sensor drift
2 Applications
The TMP63-Q1 is currently available in a 0402
footprint-compatible X1SON package and a 0603
footprint-compatible SOT-5X3 package.
•
Thermal compensation
– Display backlight
– Battery management systems
Thermal threshold detection
– Motor control
Device Information (1)
•
PART NUMBER
PACKAGE
X1SON (2)
SOT-5X3 (2)
BODY SIZE (NOM)
0.60 mm × 1.00 mm
0.80 mm × 1.20 mm
– On-board chargers & DC-DC converters
TMP63-Q1
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
220
200
180
160
140
120
100
80
VBIAS
VBIAS
IBIAS
RBIAS
+
+
VTEMP
VTEMP
RTMP63
RTMP63
œ
œ
60
-40 -20
0
20
40
60
80 100 120 140 160
VBIAS × RTMP63
RBIAS + RTMP63
Temperature (èC)
VTEMP = IBIAS × RTMP63
VTEMP
=
TMP6
Typical Resistances vs Ambient Temperature
Typical Implementation
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TMP63-Q1
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SNIS215C – JANUARY 2020 – REVISED SEPTEMBER 2020
Table of Contents
1 Features............................................................................1
2 Applications.....................................................................1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................4
Pin Functions.................................................................... 4
6 Specifications.................................................................. 5
6.1 Absolute Maximum Ratings ....................................... 5
6.2 ESD Ratings .............................................................. 5
6.3 Recommended Operating Conditions ........................5
6.4 Thermal Information ...................................................5
6.5 Electrical Characteristics ............................................6
6.6 Typical Characteristics................................................7
7 Detailed Description........................................................9
7.1 Overview.....................................................................9
7.2 Functional Block Diagram...........................................9
7.3 Feature Description.....................................................9
7.4 Device Functional Modes..........................................10
8 Application and Implementation.................................. 11
8.1 Application Information..............................................11
8.2 Typical Application.................................................... 11
9 Power Supply Recommendations................................16
10 Layout...........................................................................16
10.1 Layout Guidelines................................................... 16
10.2 Layout Example...................................................... 16
11 Device and Documentation Support..........................17
11.1 Receiving Notification of Documentation Updates..17
11.2 Support Resources................................................. 17
11.3 Trademarks............................................................. 17
11.4 Electrostatic Discharge Caution..............................17
11.5 Glossary..................................................................17
12 Mechanical, Packaging, and Orderable
Information.................................................................... 17
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (June 2020) to Revision C (September 2020)
Page
•
•
•
•
•
•
•
•
•
•
•
•
Updated the numbering format for tables, figures, and cross-references throughout the document..................1
Added AEC-Q100 Temperature Grade 0 rating for SOT-5X3/DYA package...................................................... 1
Moved HBM and CDM ESD classification levels to ESD Ratings table............................................................. 1
Removed DYA preview notice............................................................................................................................ 1
Updated Device Comparison table with 150 °C rating for DYA packages..........................................................3
Increased maximum junction temperature from 150 to 155 in Absolute Maximum Ratings Table..................... 5
Increased maximum storage temperature from 150 to 155 in Absolute Maximum Ratings Table......................5
Added DYA TA support to Recommended Operating Conditions Table............................................................. 5
Added DYA package to Thermal Information table.............................................................................................5
Added 1000 hour Long Term Drift specification for DYA package......................................................................6
Changed the Typical Characteristics section......................................................................................................7
Added Built-In Fail Safe section........................................................................................................................10
Changes from Revision A (March 2020) to Revision B (June 2020)
Page
•
•
•
•
Added DYA package as preview information......................................................................................................1
Updated Device Comparison table.....................................................................................................................3
Corrected view description in Pin Configuration and Functions......................................................................... 4
Changed Maximum ISNS from 400 µA to 40 µA in Recommended Operating Conditions Table ..................... 5
Changes from Revision * (December 2019) to Revision A (March 2020)
Page
•
•
•
•
•
•
Updated Title.......................................................................................................................................................1
Changed device status from Advanced Information to Production Data............................................................ 1
Updated features list...........................................................................................................................................1
Updated Applications..........................................................................................................................................1
Updated Description........................................................................................................................................... 1
Updated Thermistor Design Tool link................................................................................................................10
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SNIS215C – JANUARY 2020 – REVISED SEPTEMBER 2020
Device Comparison Table
PART
NUMBER
R25 TYP
R25 %TOL
RATING
TA
PACKAGE OPTIONS
–40 °C to 125 °C
–40 °C to 150 °C
–40 °C to 150 °C
–40 °C to 125 °C
–40 °C to 150 °C
–40 °C to 170 °C
–40 °C to 125 °C
–40 °C to 150 °C
–40 °C to 125 °C
–40 °C to 150 °C
X1SON / DEC (0402)
SOT-5X3 / DYA (0603)
TO-92S / LPG
TMP61
10k
1%
1%
Catalog
Automotive Grade-1
Automotive Grade-0
X1SON / DEC (0402)
SOT-5X3 / DYA (0603)
TO-92S / LPG
TMP61-Q1
10k
X1SON / DEC (0402)
SOT-5X3 / DYA (0603)
X1SON / DEC (0402)
SOT-5X3 / DYA (0603)
X1SON / DEC (0402)
SOT-5X3 / DYA (0603)
X1SON / DEC (0402)
SOT-5X3 / DYA (0603)
TMP63
100k
100k
47k
1%
1%
1%
1%
Catalog
Automotive Grade-1
Automotive Grade-0
TMP63-Q1
TMP64
Catalog
–40 °C to 125 °C
Automotive Grade-1
Automotive Grade-0
–40 °C to 125 °C
–40 °C to 150 °C
TMP64-Q1
47k
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5 Pin Configuration and Functions
œ
1
2
+
Figure 5-1. DEC Package 2-Pin X1SON Bottom View
ID Area
œ
1
2
+
Figure 5-2. DYA Package 2-Pin SOT-5X3 Top View
Pin Functions
PIN
TYPE
DESCRIPTION
NAME
NO.
–
+
1
2
Thermistor (–) and (+) terminals. For proper operation, ensure a positive bias where the +
terminal is at a higher voltage potential than the – terminal.
—
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
6
UNIT
V
Voltage across pins 2 (+) and 1(–)
Current through the device
Junction temperature (TJ)
450
155
155
µA
°C
–65
–65
Storage temperature (Tstg
)
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or anyother conditions beyond those indicated under
Recommended OperatingConditions. Exposure to absolute-maximum-rated conditions for extended periods mayaffect device
reliability.
6.2 ESD Ratings
VALUE
UNIT
Human-body model (HBM) per per AEC Q100-002 (1)
HBM classification level 2
±2000
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per AEC Q100- 011
CDM classification level C6
±1000
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
0
NOM
MAX UNIT
VSns
ISns
Voltage across pins 2 (+) and 1 (–)
5.5
40
V
Current through the device
0
µA
°C
°C
Operating free-air temperature (X1SON/DEC Package)
Operating free-air temperature (SOT-5X3/DYA Package)
–40
–40
125
150
TA
6.4 Thermal Information
TMP63-Q1
DEC (X1SON) DYA (SOT-5X3)
THERMAL METRIC (1)
Units
2 PINS
443.4
195.7
254.6
19.9
2 PINS
742.9
315.8
506.2
109.3
500.4
–
RθJA
Junction-to-ambient thermal resistance(2) (3)
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
RθJC(top)
RθJB
°C/W
°C/W
°C/W
°C/W
°C/W
ΨJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bot) thermal resistance
ΨJB
254.5
–
RθJC(bot)
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
(2) The junction to ambient thermal resistance (RθJA ) under natural convection is obtained in a simulation on a JEDEC-standard, High-K
board as specified in JESD51-7, in an environment described in JESD51-2. Exposed pad packages assume that thermal vias are
included in the PCB, per JESD 51-5.
(3) Changes in output due to self heating can be computed by multiplying the internal dissipation by the thermal resistance.
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6.5 Electrical Characteristics
TA = -40 °C - 125 °C, ISns = 20 μA (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
R25
Thermistor Resistance at 25 °C
TA = 25 °C
100
kΩ
TA = 25 °C
–1
–1
1
1
RTOL
Resistance Tolerance
TA = 0 °C - 70 °C
%
TA = -40 °C - 125 °C
T1 = -40 °C, T2 = -30 °C
T1 = 20 °C, T2 = 30 °C
T1 = 80 °C, T2 = 90 °C
T1 = -40 °C, T2 = -30 °C
T1 = 20 °C, T2 = 30 °C
T1 = 80 °C, T2 = 90 °C
–1.5
1.5
TCR-35
TCR25
TCR85
TCR-35
TCR25
TCR85
+6220
+6400
+5910
±0.4
Temperature Coefficient of Resistance
ppm/°C
%
%
Temperature Coefficient of Resistance
Tolerance
%
±0.2
%
±0.3
96 hours continuous operation at RH = 85
%, and TA = 130 °C
VBias = 5.5 V
-1
-1.5
-1.2
-1.2
±0.1
±0.3
±0.2
±0.3
1
1.8
1.2
1.2
600 hours continuous operation at TA = 150
°C
VBias = 5.5 V DEC Package
ΔR
Sensor Long Term Drift (Reliability)
%
600 hours continuous operation at TA = 150
°C
VBias = 5.5V, DYA Package
1000 hours continuous operation at TA
150 °C
=
VBias = 5.5V, DYA Package
tRES
T1 = 25 °C in Still Air to T2 = 125 °C in
Stirred Liquid
Thermal response to 63%
Thermal response to 63%
0.6
3.2
s
s
(stirred
liquid)
tRES (still
T1 = 25 °C to T2 = 70 °C in Still Air
air)
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6.6 Typical Characteristics
at TA = 25 °C, (unless otherwise noted)
TMP117_Datasheet_plots.xlsm
Sheet4
225
200
175
150
125
100
75
225
200
175
150
125
100
75
IBIAS = 1 mA
IBIAS = 2 mA
IBIAS = 10 mA
IBIAS = 20 mA
IBIAS = 40 mA
50
VBIAS = 1.8 V
VBIAS = 2.5 V
VBIAS = 3.3 V
VBIAS = 5.5 V
50
25
25
0
0
-40 -20
0
20
40
60
80 100 120 140 160
-40 -20
0
20
40
60
80 100 120 140 160
Temperature (èC)
Temperature (èC)
TMP6
TMP6
RBIAS = 100 kΩ with ±0.01 % tolerance
Figure 6-1. Resistance vs. Ambient Temperature
Using Multiple Bias Currents
Figure 6-2. Resistance vs. Ambient Temperature
Using Multiple Bias Voltages
6500
6400
6300
6200
6100
6000
6500
6400
6300
6200
6100
6000
0
5
10
15
20
25
30
35
40
1.5
2
2.5
3 3.5
Bias Voltage (V)
4
4.5
5
Bias Current (mA)
TMP61
TMP6
RBias = 100 kΩ with ±0.01 % Tolerance
Figure 6-3. TCR vs. Sense Currents (ISNS
)
Figure 6-4. TCR as a Function of Sense Voltages,
VSns
225
200
175
150
125
100
75
225
200
175
150
125
100
75
50
50
-40 èC
25 èC
50 èC
100 èC
125 èC
150 èC
-40 èC
25 èC
50 èC
100 èC
125 èC
150 èC
25
0
25
0
0
5
10
15
20
25
30
35
40
45
50
0
0.5
1
1.5
2
2.5
Voltage (V)
3
3.5
4
4.5
5
Current (mA)
TMP6
TMP6
RBias = 100 kΩ ( ±0.01 % tolerance)
Figure 6-5. Supply Dependence Resistance vs.
Bias Current
Figure 6-6. Supply Dependence vs. Bias Voltage
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2.5
2
180
160
140
120
100
80
VBIAS
VSNS
1.5
1
0.5
0
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14
0
1
2
3
4
5
Time (ms)
Time (s)
TMP61
TMP6
VSNS = 1 V.
Ambient material: stirred liquid. Temperature: 25 °C to 125 °C
Figure 6-7. Step Response
Figure 6-8. DEC Thermal Response Time
180
160
140
120
100
80
130
125
120
115
110
105
100
95
0
1
2
3
4
5
0
2
4
6
8
Time (s)
10
12
14
16
Time (s)
TMP6
TMP6
Ambient material: stirred liquid. Temperature: 25 °C to 125 °C
Ambient material: still air
Figure 6-9. DYA Thermal Response Time
Figure 6-10. Thermal Response Time
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7 Detailed Description
7.1 Overview
The TMP63-Q1 silicon linear thermistor has a linear positive temperature coefficient (PTC) that results in a
uniform and consistent temperature coefficient resistance (TCR) across a wide operating temperature range. TI
uses a special silicon process where the the doping level and active region areas devices control the key
characteristics (the temperature coefficient resistance (TCR) and nominal resistance (R25)) . The device has an
active area and a substrate due to the polarized terminals. Connect the positive terminal to the highest voltage
potential. Connect the negative terminal to the lowest voltage potential.
Unlike an NTC, which is a purely resistive device, the TMP63-Q1 resistance is affected by the current across the
device and the resistance changes when the temperature changes. In a voltage divider circuit, it is
recommended to maintain the top resistor value at 100 kΩ. Changing the top resistor value or the VBIAS value
changes the resistance vs temperature table (R-T table) of the TMP63-Q1, and subsequently the polynomials as
described in the Section 8.2.1.1. Consult Section 7.3.1 for more information.
Equation 1 can help the user approximate the TCR.
TCR (ppm/°C) = (RT2 – RT1) / ((T2 – T1) × R(T2+T1)/2
)
(1)
Key terms and definitions:
•
•
•
•
•
ISNS: Current flowing through the TMP63-Q1 device
VSNS: Voltage across the two TMP63-Q1 terminal
IBIAS: Current supplied by the biasing circuit.
VBIAS: Voltage supplied by the biasing circuit.
VTEMP: Output voltage that corresponds to the measured temperature. Note that this is different from VSNS. In
the use case of a voltage divider circuit with the TMP63-Q1 in the high side, VTEMP is measured across RBIAS
.
7.2 Functional Block Diagram
VBIAS
VBIAS
IBIAS
RBIAS
+
+
VTEMP
VTEMP
RTMP63
RTMP63
œ
œ
VBIAS × RTMP63
RBIAS + RTMP63
VTEMP = IBIAS × RTMP63
VTEMP
=
Figure 7-1. Typical Implementation Circuits
7.3 Feature Description
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7.3.1 TMP63-Q1 R-T table
The TMP63-Q1 R-T table must be re-calculated for any change in the bias voltage, bias resistor, or bias current.
TI provides a Thermistor Design Tool to calculate the R-T table. The system designer must always validate the
calculations provided.
7.3.2 Linear Resistance Curve
The TMP63-Q1 has good linear behavior across the whole temperature range as shown in Figure 6-3. This
range allows a simpler resistance-to-temperature conversion method that reduces look-up table memory
requirements. The linearization circuitry or midpoint calibration associated with traditional NTCs is not necessary
with the device .
The linear resistance across the entire temperature range allows the device to maintain sensitivity at higher
operating temperatures.
7.3.3 Positive Temperature Coefficient (PTC)
The TMP63-Q1 has a positive temperature coefficient. As temperature increases the device resistance
increases leading to a reduction in power consumption of the bias circuit. In comparison, a negative coefficient
system increases power consumption with temperature as the resistance decreases.
The TMP63-Q1 benefits from the reduced power consumption of the bias circuit with less self-heating than a
typical NTC system.
7.3.4 Built-In Fail Safe
The TMP6 family feature a positive tempeature coefficient. During a short-to-supply condition, the thermistor will
have increased current and power dissipated. Due to the positive temperature slope, the TMP6 will increase
resistance and limit self-heating by design.
In contrast, a NTC would continually reduce resistance due to self-heating leading to a positive feedback of
increasing power dissipation and decreasing resistance.
7.4 Device Functional Modes
The device operates in only one mode when operated within the Recommended Operating Conditions.
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8 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
8.1 Application Information
The TMP63-Q1 is a positive temperature coefficient (PTC) linear silicon thermistor. The device behaves as a
temperature-dependent resistor, and may be configured in a variety of ways to monitor temperature based on
the system-level requirements. The device has a nominal resistance at 25 °C (R25) of 100 kΩ , a maximum
operating voltage of 5.5 V (VSNS), and maximum supply current of 40 µA (ISNS). This device may be used in a
variety of applications to monitor temperature close to a heat source with the very small DEC package option
compatible with the typical 0402 (inch) footprint. Some of the factors that influence the total measurement error
include the ADC resolution (if applicable), the tolerance of the bias current or voltage, the tolerance of the bias
resistance in the case of a voltage divider configuration, and the location of the sensor with respect to the heat
source.
8.2 Typical Application
8.2.1 Thermistor Biasing Circuits
VBias
IBias
RBias
RT
VTemp
RT
VTemp
Figure 8-2. Current Biasing Circuit With Linear
Thermistor
Figure 8-1. Voltage Biasing Circuit With Linear
Thermistor
VBias
IBias
RBias
RP
RT
VTemp
RP
RT
VTemp
Figure 8-4. Current Biasing Circuit With Non-Linear
Thermistor
Figure 8-3. Voltage Biasing Circuit With Non-Linear
Thermistor
8.2.1.1 Design Requirements
Existing thermistors, in general, have a non-linear temperature vs. resistance curve. To linearize the thermistor
response, the engineer can use a voltage linearization circuit with a voltage divider configuration, or a resistance
linearization circuit by adding another resistance in parallel with the thermistor, RP. Section 8.2.1 highlights the
two implementations where RT is the thermistor resistance. To generate an output voltage across the thermistor,
the engineer can use a voltage divider circuit with the thermistor placed at either the high side (close to supply)
or low side (close to ground), depending on the desired voltage response (negative or positive). Alternatively, the
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thermistor can be biased directly using a precision current source (yielding the highest accuracy and voltage
gain). It is common to use a voltage divider with thermistors because of its simple implementation and lower
cost. The TMP63-Q1 has a linear positive temperature coefficient (PTC) of resistance such that the voltage
measured across it increases linearly with temperature. As such, the need for a linearization circuits is no longer
a requirement, and a simple current source or a voltage divider circuit can be used to generate the temperature
voltage.
This output voltage can be interpreted using a comparator against a voltage reference to trigger a temperature
trip point that is either tied directly to an ADC to monitor temperature across a wider range or used as feedback
input for an active feedback control circuit.
The voltage across the device, as described in Equation 2, can be translated to temperature using either a
lookup table method (LUT) or a fitting polynomial, V(T). The Thermistor Design Tool must be used to translate
Vtemp to Temperature. The temperature voltage must first be digitized using an ADC. The necessary resolution
of this ADC is dependent on the biasing method used. Additionally, for best accuracy, tie the bias voltage (VBIAS
)
to the reference voltage of the ADC to create a measurement where the difference in tolerance between the bias
voltage and the reference voltage cancels out. The application can also include a low-pass filter to reject system
level noise. In this case, place the filter as close to the ADC input as possible.
8.2.1.2 Detailed Design Procedure
The resistive circuit divider method produces an output voltage (VTEMP) scaled according to the bias voltage
(VBIAS). When VBIAS is also used as the reference voltage of the ADC, any fluctuations or tolerance error due to
the voltage supply are canceled and do not affect the temperature accuracy (as shown in Figure 8-5). Equation 2
describes the output voltage (VTEMP) based on the variable resistance of the TMP63-Q1 (RTMP63-Q1 ) and bias
resistor (RBIAS). The ADC code that corresponds to that output voltage, ADC full-scale range, and ADC
resolution is given in Equation 3.
VBias
RBias
RFilter
REF
IN
IN
ADC
CFilter
RTMP63
GND
Figure 8-5. Voltage Divider With an ADC
≈
∆
«
’
÷
RTMP63
VTEMP = VBIAS
ì
RBIAS + RTMP63 ◊
(2)
(3)
V
≈
’
TEMP
ADC Code =
ì 2n
∆
÷
FSR
«
◊
where
•
•
FSR is the full-scale range of the ADC, which is the voltage at REF to GND (VREF
n is the resolution of the ADC
)
Equation 4 shows whenever VREF = VBIAS, VBIAS cancels out.
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≈
∆
∆
∆
’
÷
÷
÷
≈
∆
«
’
÷
RTMP63
V
ì
BIAS
RBIAS + RTMP63 ◊
VBIAS
≈
∆
«
’
÷
RTMP63
ADC Code =
ì 2n =
ì 2n
RBIAS + RTMP63 ◊
∆
∆
«
÷
÷
◊
(4)
Use a polynomial equation or a LUT to extract the temperature reading based on the ADC code read in the
microcontroller. Use the Thermistor Design Tool to translate the TMP63-Q1 resistance to temperature.
The cancellation of VBIAS is one benefit to using a voltage-divider (ratiometric approach), but the sensitivity of the
output voltage of the divider circuit cannot increase much. Therefore, this application design does not use all of
the ADC codes due to the small voltage output range compared to the FSR. This application is very common,
however, and is simple to implement.
A current source-based circuit, such as the one shown in Figure 8-6, offers better control over the sensitivity of
the output voltage and achieve higher accuracy. In this case, the output voltage is simply V = I × R. For example,
if a current source of 40 µA is used with the device, the output voltage spans approximately 5.5 V and has a gain
up to 40 mV/°C. Having control over the voltage range and sensitivity allows for full use of the ADC codes and
full-scale range. Figure 8-11 shows the temperature voltage for various bias current conditions. Similar to the
ratiometric approach, if the ADC has a built-in current source that shares the same bias as the reference voltage
of the ADC, the tolerance of the supply current cancels out. In this case, a precision ADC is not required. This
method yields the best accuracy, but can increase the system implementation cost.
Precision
IBias
Current Source
RTMP63
VTemp
Figure 8-6. Biasing Circuit With Current Source
In comparison to the non-linear NTC thermistor in a voltage divider, the TMP63-Q1 has an enhanced linear
output characteristic. The two voltage divider circuits with and without a linearization parallel resistor, RP, are
shown in Figure 8-7. Consider an example where VBIAS = 5 V, RBIAS = 100 kΩ, and a parallel resistor (RP) is
used with the NTC thermistor (RNTC) to linearize the output voltage with an additional 100-kΩ resistor. The
device produces a linear curve across the entire temperature range while the NTC curve is only linear across a
small temperature region. When the parallel resistor (RP) is added to the NTC circuit, the added resistor makes
the curve much more linear but greatly affects the output voltage range.
VBias
VBias
RBias
RBias
RTMP63
RNTC
RP
VTemp
VTemp
Figure 8-7. TMP63-Q1 vs. NTC With Linearization Resistor (RP) Voltage Divider Circuits
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8.2.1.2.1 Thermal Protection With Comparator
Use the TMP63-Q1 device along with a voltage reference, and a comparator to program the thermal protection.
As shown in Figure 8-8, the output of the comparator remains low until the voltage of the thermistor divider, with
RBIAS and RTMP63-Q1, rises above the threshold voltage set by R1 and R2. When the output goes high, the
comparator signals an overtemperature warning signal. The engineer can also program the hysteresis to prevent
the output from continuously toggling around the temperature threshold when the output returns low. Either a
comparator with built-in hysteresis or feedback resistors may be used.
VBias
RBias
R1
VTrip
RTMP63
R2
Figure 8-8. Temperature Switch Using Voltage Divider and a Comparator
8.2.1.2.2 Thermal Foldback
One application that uses the output voltage of the TMP63-Q1 in an active control circuit is thermal foldback.
This is performed to reduce, or fold back, the current driving a string of LEDs, for example. At high temperatures,
the LEDs begin to heat up due to environmental conditions and self heating. Thus, at a certain temperature
threshold based on the LED's safe operating area, the driving current must be reduced to cool down the LEDs
and prevent thermal runaway. The device voltage output increases with temperature when the output is in the
lower position of the voltage divider and can provide a response used to fold back the current. Typically, the
device holds the current at a specified level until a high temperature is reached, known as the knee point, at
which the current must be rapidly reduced in order to continue operation. To better control the temperature/
voltage sensitivity, the device uses a rail-to-rail operational amplifier. Figure 8-9 shows the temperature knee
point where the foldback begins. The set by the reference voltage (2.5 V) at the positive input, and the feedback
resistors set the response of the foldback curve. The foldback knee point may be chosen based on the output of
the voltage divider and the corresponding temperature from Equation 5 (110°C, for example). The device uses a
buffer between the voltage divider with RTMP63-Q1 and the input to the op amp to prevent loading and variations
in VTEMP
.
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5 V
RFB
300 kꢀ
RBias
200 kꢀ
R2
200 kꢀ
R1
10 kꢀ
VTemp
VOut
VRef
RTMP63
R3
200 kꢀ
Figure 8-9. Thermal Foldback Using Voltage Divider and a Rail-to-Rail Op Amp
The op amp remains high as long as the voltage output is below VREF. When the temperature goes above
110°C, the output falls to the 0-V rail of the op amp. The rate at which the foldback occurs depends on the
feedback network, RFB and R1, which varies the gain of the op amp, G, as shown in Equation 6. The foldback
behavior controls the voltage and temperature sensitivity of the circuit. The device feeds this voltage output into
a LED driver circuit that adjusts output current accordingly. VOUT is the final output voltage used for thermal
foldback and is calculated in Equation 7. Figure 8-10 describes the output voltage curve in this example which
sets the knee point at 110°C.
≈
∆
«
’
÷
RTMP63
VTEMP = VBIAS
ì
RBIAS + RTMP63 ◊
(5)
RFB
G =
R1
(6)
(7)
VOUT = -Gì VTEMP + 1+ G ì V
REF
6
5
4
3
2
1
0
0
25
50
75
100
125
150
Temperature (èC)
D014
Figure 8-10. Thermal Foldback Voltage Output Curve
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8.2.2 Application Curve
9
IBias = 5 mA
8
7
6
5
4
3
2
1
0
IBias = 10 mA
IBias = 20 mA
IBias = 30 mA
IBias = 40 mA
-60 -40 -20
0
20
40
60
80 100 120 140
Temperature (èC)
TMP6
Figure 8-11. Temperature vs. Voltage at Varying Current Source Values
9 Power Supply Recommendations
The maximum recommended operating voltage of the TMP63-Q1 is 5.5 V (VSNS), and the maximum current
through the device is 40 µA (ISNS).
10 Layout
10.1 Layout Guidelines
The layout of the TMP63-Q1 is similar to that of a passive component. If the device is biased with a current
source, the positive pin 2 is connected to the source, while the negative pin 1 is connected to ground. If the
circuit is biased with a voltage source, and the device is placed on the lower side of the resistor divider, V– is
connected to ground, and V+ is connected to the output (VTEMP). If the device is placed on the upper side of the
divider, V+ is connected to the voltage source and V– is connected to the output voltage (VTEMP). Figure 10-1
shows the device layout.
10.2 Layout Example
Figure 10-1. DEC Package Recommended Layout
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11 Device and Documentation Support
11.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
11.2 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.3 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.5 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
4-Oct-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TMP6331QDECRQ1
TMP6331QDECTQ1
TMP6331QDYARQ1
TMP6331QDYATQ1
ACTIVE
X1SON
X1SON
DEC
2
2
2
2
10000 Green (RoHS
& no Sb/Br)
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 125
-40 to 125
-40 to 125
-40 to 125
HC
ACTIVE
ACTIVE
ACTIVE
DEC
250
3000
250
Green (RoHS
& no Sb/Br)
NIPDAU
SN
HC
SOT-5X3
SOT-5X3
DYA
Green (RoHS
& no Sb/Br)
1HG
1HG
DYA
Green (RoHS
& no Sb/Br)
SN
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
4-Oct-2020
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TMP63-Q1 :
Catalog: TMP63
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Addendum-Page 2
PACKAGE OUTLINE
DYA0002A
SOT - 0.77 mm max height
PLASTIC SMALL OUTLINE
1.7
1.5
PIN 1
ID AREA
A
0.85
0.75
NOTE 3
2
1
1.3
1.1
0.3
0.1
0.7
B
2X
TYP
0.5
0.77 MAX
C
SEATING PLANE
0.05 C
0.15
2X
0.08
SYMM
SYMM
0.35
0.25
2X
0.1
0.05
C A B
0.4
0.2
2X
4224978/A 04/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
www.ti.com
EXAMPLE BOARD LAYOUT
DYA0002A
SOT - 0.77 mm max height
PLASTIC SMALL OUTLINE
SYMM
2X (0.67)
(R0.05) TYP
SYMM
2
1
2X (0.4)
(1.48)
LAND PATTERN EXAMPLE
SCALE:40X
0.05 MIN
AROUND
0.05 MAX
AROUND
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDERMASK DETAILS
4224978/A 04/2019
NOTES: (continued)
4. Publication IPC-7351 may have alternate designs.
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DYA0002A
SOT - 0.77 mm max height
PLASTIC SMALL OUTLINE
SYMM
2X (0.67)
(R0.05) TYP
SYMM
2
1
2X (0.4)
(1.48)
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
SCALE:40X
4224978/A 04/2019
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
DEC0002A
X1SON - 0.5 mm max height
S
C
A
L
E
1
1
.
0
0
0
PLASTIC SMALL OUTLINE - NO LEAD
1.05
0.95
B
A
PIN 1 INDEX AREA
0.65
0.55
0.50
0.41
C
SEATING PLANE
0.05
0.00
0.03 C
0.65
1
2
SYMM
0.55
0.45
2X
0.1
C A B
PIN 1 ID
(45 X0.125)
SYMM
0.3
0.2
2X
0.1
C A B
4224506/A 08/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
DEC0002A
X1SON - 0.5 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
2X (0.25)
SYMM
1
2
SYMM
2X (0.5)
(R0.05) TYP
(0.65)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:60X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
METAL EDGE
METAL UNDER
SOLDER MASK
EXPOSED
METAL
EXPOSED
METAL
SOLDER MASK
OPENING
SOLDER MASK
OPENING
SOLDER MASK
DEFINED
(PREFERRED)
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4224506/A 08/2018
NOTES: (continued)
3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).
4. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view.
It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
DEC0002A
X1SON - 0.5 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(0.05)
2X (0.3)
2X (0.5)
SYMM
PCB PAD METAL
UNDER SOLDER PASTE
SYMM
2
1
(R0.05) TYP
(0.7)
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
SCALE:60X
4224506/A 08/2018
NOTES: (continued)
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
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These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
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