TMP75AIDRG4 [TI]

Digital Temperature Sensor with Two-Wire Interface; 数字温度传感器，具有双线接口


型号：	TMP75AIDRG4
厂家：	TEXAS INSTRUMENTS
描述：	Digital Temperature Sensor with Two-Wire Interface 数字温度传感器，具有双线接口传感器温度传感器
文件：	总20页 (文件大小：640K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TMP175

TMP75

SBOS288J − JANUARY 2004 − REVISED DECEMBER 2007

Digital Temperature Sensor

with Two-Wire Interface

F_DEATURES

DESCRIPTION

27 ADDRESSES (TMP175)

8 ADDRESSES (TMP75)

The TMP175 and TMP75 are two-wire, serial output

temperature sensors available in SO-8 and MSOP-8

packages. Requiring no external components, the

TMP175 and TMP75 are capable of reading temperatures

with a resolution of 0.0625°C.

DIGITAL OUTPUT: Two-Wire Serial Interface

RESOLUTION: 9- to 12-Bits, User-Selectable

ACCURACY:

1.5°C (max) from −25°C to +85°C

2.0°C (max) from −40°C to +125°C

The TMP175 and TMP75 feature a Two-Wire interface that

is SMBus-compatible, with the TMP175 allowing up to 27

devices on one bus and the TMP75 allowing up to eight

devices on one bus. The TMP175 and TMP75 both feature

an SMBus Alert function.

LOW QUIESCENT CURRENT:

50µA, 0.1µA Standby

WIDE SUPPLY RANGE: 2.7V to 5.5V

The TMP175 and TMP75 are ideal for extended

temperature measurement in a variety of communication,

computer, consumer, environmental, industrial, and

instrumentation applications.

SMALL SO-8 AND MSOP-8 PACKAGES

A_DPPLICATIONS

POWER-SUPPLY TEMPERATURE

MONITORING

The TMP175 and TMP75 are specified for operation over

a temperature range of −40°C to +125°C.

COMPUTER PERIPHERAL THERMAL

PROTECTION

Temperature

Diode

Te mp.

Sensor

NOTEBOOK COMPUTERS

CELL PHONES

Control

Logic

V+

SDA

SCL

BATTERY MANAGEMENT

OFFICE MACHINES

∆Σ

A/D

Converter

Serial

Interface

THERMOSTAT CONTROLS

ENVIRONMENTAL MONITORING AND HVAC

ALERT

GND

ELECTROMECHANICAL DEVICE

TEMPERATURE

Config.

and Temp.

OSC

TMP175, TMP75

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments

semiconductor products and disclaimers thereto appears at the end of this data sheet.

All trademarks are the property of their respective owners.

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SBOS288J − JANUARY 2004 − REVISED DECEMBER 2007

This integrated circuit can be damaged by ESD. Texas

Instruments recommends that all integrated circuits be

(1)

ABSOLUTE MAXIMUM RATINGS

Power Supply, V+ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0V

handledwith appropriate precautions. Failure to observe

(2)

proper handling and installation procedures can cause damage.

Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5V to 7.0V

Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10mA

Operating Temperature Range . . . . . . . . . . . . . . . −55°C to +127°C

Storage Temperature Range . . . . . . . . . . . . . . . . . −60°C to +130°C

ESD damage can range from subtle performance degradation to

complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could

cause the device not to meet its published specifications.

Junction Temperature (T max) . . . . . . . . . . . . . . . . . . . . . . +150°C

ESD Rating:

Human Body Model (HBM) . . . . . . . . . . . . . . . . . . . . . . . 4000V

Charged Device Model (CDM) . . . . . . . . . . . . . . . . . . . . 1000V

Machine Model (MM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300V

(1)

(2)

Stresses above these ratings may cause permanent damage.

Exposure to absolute maximum conditions for extended periods

may degrade device reliability. These are stress ratings only, and

functional operation of the device at these or any other conditions

beyond those specified is not supported.

Input voltage rating applies to all TMP175 and TMP75 input

voltages.

(1)

ORDERING INFORMATION

PRODUCT

TMP175

TMP75

PACKAGE-LEAD

SO-8

PACKAGE DESIGNATOR

PACKAGE MARKING

TMP175

MSOP-8

SO-8

DGK

DABQ

TMP75

MSOP-8

DGK

T127

(1)

For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website

at www.ti.com.

PIN ASSIGNMENTS

Top View

TMP175

TMP75

SDA

SCL

V+

SDA

SCL

V+

SDA

SCL

V+

SDA

SCL

V+

ALERT

GND

ALERT

GND

ALERT

GND

ALERT

GND

MSOP−8

SO−8

MSOP−8

NOTE: Pin 1 is determined by orienting the package marking as indicated in the diagram.

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ELECTRICAL CHARACTERISTICS

At T = −40°C to +125°C, and V+ = 2.7V to 5.5V, unless otherwise noted.

TMP175

TMP75

TYP

PARAMETER

CONDITION

UNITS

MIN

TYP

MAX

MIN

MAX

TEMPERATURE INPUT

Range

−40

+125

1.5

−40

+125

2.0

°C

Accuracy (Temperature Error)

−25°C to +85°C

−40°C to +125°C

0.5

1.0

0.5

1.0

2.0

3.0

°C

vs Supply

0.2

0.5

0.2

0.5

°C/V

°C

(1)

Resolution

Selectable

+0.0625

DIGITAL INPUT/OUTPUT

Input Capacitance

Input Logic Levels:

0.7(V+)

−0.5

6.0

0.3(V+)

0.7(V+)

−0.5

6.0

0.3(V+)

Leakage Input Current, I

Input Voltage Hysteresis

Output Logic Levels:

0V ≤ V ≤ 6V

µA

SCL and SDA Pins

500

SDA

= 3mA

= 4mA

0.15

9 to 12

27.5

0.4

0.15

9 to 12

27.5

0.4

ALERT

Resolution

Selectable

9-Bit

Bits

Conversion Time

37.5

10-Bit

11-Bit

110

150

300

110

150

300

12-Bit

220

Timeout Time

POWER SUPPLY

Operating Range

Quiescent Current

2.7

5.5

2.7

5.5

Serial Bus Inactive

100

410

0.1

100

410

0.1

µA

Serial Bus Active, SCL Freq = 400kHz

Serial Bus Active, SCL Freq = 3.4MHz

Serial Bus Inactive

Shutdown Current

Serial Bus Active, SCL Freq = 400kHz

Serial Bus Active, SCL Freq = 3.4MHz

380

TEMPERATURE RANGE

Specified Range

Operating Range

Thermal Resistance

MSOP-8

−40

−55

+125

+127

−40

−55

+125

+127

°C

250

150

250

150

°C/W

SO-8

(1)

Specified for 12-bit resolution.

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TYPICAL CHARACTERISTICS

At T = +25°C and V+ = 5.0V, unless otherwise noted.

SHUTDOWN CURRENT vs TEMPERATURE

QUIESCENT CURRENT vs TEMPERATURE

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0.0

V+ = 5V

V+ = 2.7V

Serial Bus Inactive

−

0.1

−

85 105 125 130

Temperature ( C)

CONVERSION TIME vs TEMPERATURE

V+ = 5V

TEMPERATURE ACCURACY vs TEMPERATURE

300

2.0

1.5

1.0

0.5

0.0

0.5

1.0

1.5

2.0

250

200

150

100

V+ = 2.7V

−

12−bit resolution.

65 85 105 125 130

3 typical units 12−bit resolution.

−

85 105 125 130

Temperature ( C)

QUIESCENT CURRENT WITH

BUS ACTIVITY vs TEMPERATURE

500

Hs MODE

FAST MODE

450

400

350

300

250

200

150

100

125 C

25 C

−

55 C

10k

100k

Frequency (Hz)

10M

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APPLICATIONS INFORMATION

Pointer

The TMP175 and TMP75 are digital temperature sensors

that are optimal for thermal management and thermal

protection applications. The TMP175 and TMP75 are

Two-Wire and SMBus interface-compatible, and are

specified over a temperature range of −40°C to +125°C.

Temperature

The TMP175 and TMP75 require no external components

for operation except for pull-up resistors on SCL, SDA, and

SCL

SDA

Configuration

ALERT, although

recommended, as shown in Figure 1.

0.1µF bypass capacitor is

I/O

Control

Interface

T_LOW

V+

T_HIGH

0.1 F

A₀

SCL

SDA

Figure 2. Internal Register Structure of the

TMP175 and TMP75

Two−Wire

Controller

TMP175

TMP75

A₁

A₂

ALERT

(Output)

Table 1. Pointer Register Byte

NOTE: SCL, SDA, and ALERT

pins require pull−up resistors.

GND

TemperatureRegister (READ Only)

Configuration Register (READ/WRITE)

Figure 1. Typical Connections of the TMP175 and

TMP75

LOW

HIGH

The sensing device of the TMP175 and TMP75 is the chip

itself. Thermal paths run through the package leads as well

as the plastic package. The lower thermal resistance of

metal causes the leads to provide the primary thermal

path.

Table 2. Pointer Addresses of the TMP175 and

TMP75

TEMPERATURE REGISTER

The Temperature Register of the TMP175 or TMP75 is a

12-bit, read-only register that stores the output of the most

recent conversion. Two bytes must be read to obtain data,

and are described in Table 3 and Table 4. Note that byte 1

is the most significant byte, followed by byte 2, the least

significant byte. The first 12 bits are used to indicate

temperature, with all remaining bits equal to zero. The

least significant byte does not have to be read if that

information is not needed. Data format for temperature is

summarized in Table 5. Following power-up or reset, the

Temperature Register will read 0°C until the first

conversion is complete.

To maintain accuracy in applications requiring air or

surface temperature measurement, care should be taken

to isolate the package and leads from ambient air

temperature. A thermally-conductive adhesive will assist

in achieving accurate surface temperature measurement.

POINTER REGISTER

Figure 2 shows the internal register structure of the

TMP175 and TMP75. The 8-bit Pointer Register of the

devices is used to address a given data register. The

Pointer Register uses the two LSBs to identify which of the

data registers should respond to a read or write command.

Table 1 identifies the bits of the Pointer Register byte.

Table 2 describes the pointer address of the registers

available in the TMP175 and TMP75. Power-up reset

value of P1/P0 is 00.

T11

T10

Table 3. Byte 1 of Temperature Register

Table 4. Byte 2 of Temperature Register

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POLARITY (POL)

TEMPERATURE

DIGITAL OUTPUT

(BINARY)

HEX

(°C)

The Polarity Bit of the TMP175 and TMP75 allows the user

to adjust the polarity of the ALERT pin output. If POL = 0,

the ALERT pin will be active LOW, as shown in Figure 3.

For POL = 1, the ALERT pin will be active HIGH, and the

state of the ALERT pin is inverted.

128

127.9375

100

0111 1111 1111

0110 0100 0000

0101 0000 0000

0100 1011 0000

0011 0010 0000

0001 1001 0000

0000 0000 0100

0000 0000 0000

1111 1111 1100

1110 0111 0000

1100 1001 0000

7FF

640

500

4B0

320

190

004

000

FFC

E70

C90

T_HIGH

0.25

Measured

Temperature

T_LOW

−0.25

−25

−55

TMP75/TMP175 ALERT PIN

(Comparator Mode)

POL = 0

Table 5. Temperature Data Format

TMP75/TMP175 ALERT PIN

(Interrupt Mode)

The user can obtain 9, 10, 11, or 12 bits of resolution by

addressing the Configuration Register and setting the

resolution bits accordingly. For 9-, 10-, or 11-bit resolution,

the most significant bits in the Temperature Register are

used with the unused LSBs set to zero.

POL = 0

TMP75/TMP175 ALERT PIN

(Comparator Mode)

POL = 1

TMP75/TMP175 ALERT PIN

(Interrupt Mode)

POL = 1

CONFIGURATION REGISTER

The Configuration Register is an 8-bit read/write register

used to store bits that control the operational modes of the

temperature sensor. Read/write operations are performed

MSB first. The format of the Configuration Register for the

TMP175 and TMP75 is shown in Table 6, followed by a

breakdown of the register bits. The power-up/reset value

of the Configuration Register is all bits equal to 0.

Read

Time

Read

Figure 3. Output Transfer Function Diagrams

FAULT QUEUE (F1/F0)

A fault condition is defined as when the measured

temperature exceeds the user-defined limits set in the

T_HIGHand T_LOWRegisters. Additionally, the number of

fault conditions required to generate an alert may be

programmed using the fault queue. The fault queue is

provided to prevent a false alert as a result of

environmental noise. The fault queue requires

consecutive fault measurements in order to trigger the

alert function. Table 7 defines the number of measured

faults that may be programmed to trigger an alert condition

in the device. For T_HIGHand T_LOWregister format and byte

order, see the section High and Low Limit Registers.

BYTE D7

POL

Table 6. Configuration Register Format

SHUTDOWN MODE (SD)

The Shutdown Mode of the TMP175 and TMP75 allows

the user to save maximum power by shutting down all

device circuitry other than the serial interface, which

reduces current consumption to typically less than 0.1µA.

Shutdown Mode is enabled when the SD bit is 1; the device

will shut down once the current conversion is completed.

When SD is equal to 0, the device will maintain a

continuous conversion state.

CONSECUTIVE FAULTS

THERMOSTAT MODE (TM)

The Thermostat Mode bit of the TMP175 and TMP75

indicates to the device whether to operate in Comparator

Mode (TM = 0) or Interrupt Mode (TM = 1). For more

information on comparator and interrupt modes, see the

High and Low Limit Registers section.

Table 7. Fault Settings of the TMP175 and TMP75

CONVERTER RESOLUTION (R1/R0)

The Converter Resolution Bits control the resolution of the

internal Analog-to-Digital (A/D) converter. This allows the

user to maximize efficiency by programming for higher

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resolution or faster conversion time. Table 8 identifies the

Resolution Bits and the relationship between resolution

and conversion time.

Both operational modes are represented in Figure 3.

Table 9 and Table 10 describe the format for the T_HIGHand

T_LOWregisters. Note that the most significant byte is sent

first, followed by the least significant byte. Power-up reset

values for T_HIGHand T_LOWare:

CONVERSION TIME

(typical)

27.5ms

55ms

RESOLUTION

9 Bits (0.5°C)

_HIGH= 80°C and T_LOW= 75°C

10 Bits (0.25°C)

11 Bits (0.125°C)

12 Bits (0.0625°C)

The format of the data for T_HIGHand T_LOWis the same as

for the Temperature Register.

110ms

220ms

Table 8. Resolution of the TMP175 and TMP75

BYTE D7

H11 H10

ONE-SHOT (OS)

The TMP175 and TMP75 feature a One-Shot Temperature

Measurement Mode. When the device is in Shutdown

Mode, writing a ‘1’ to the OS bit will start a single

temperature conversion. The device will return to the

shutdown state at the completion of the single conversion.

This is useful to reduce power consumption in the TMP175

and TMP75 when continuous temperature monitoring is

not required. When the configuration register is read, the

OS will always read zero.

BYTE D7

Table 9. Bytes 1 and 2 of T

HIGH

BYTE D7

L11

L10

BYTE D7

HIGH AND LOW LIMIT REGISTERS

Table 10. Bytes 1 and 2 of T

LOW

In Comparator Mode (TM = 0), the ALERT pin of the

TMP175 and TMP75 becomes active when the

temperature equals or exceeds the value in T_HIGHand

generates a consecutive number of faults according to

fault bits F1 and F0. The ALERT pin will remain active until

the temperature falls below the indicated T_LOWvalue for

the same number of faults.

All 12 bits for the Temperature, T_HIGH, and T_LOWregisters

are used in the comparisons for the ALERT function for all

converter resolutions. The three LSBs in T_HIGHand T_LOW

can affect the ALERT output even if the converter is

configured for 9-bit resolution.

In Interrupt Mode (TM = 1), the ALERT pin becomes active

when the temperature equals or exceeds T_HIGHfor a

consecutive number of fault conditions. The ALERT pin

remains active until a read operation of any register

occurs, or the device successfully responds to the SMBus

Alert Response Address. The ALERT pin will also be

cleared if the device is placed in Shutdown Mode. Once

the ALERT pin is cleared, it will only become active again

by the temperature falling below T_LOW. When the

temperature falls below T_LOW, the ALERT pin will become

active and remain active until cleared by a read operation

of any register or a successful response to the SMBus

Alert Response Address. Once the ALERT pin is cleared,

the above cycle will repeat, with the ALERT pin becoming

SERIAL INTERFACE

The TMP175 and TMP75 operate only as slave devices on

the Two-Wire bus and SMBus. Connections to the bus are

made via the open-drain I/O lines SDA and SCL. The SDA

and SCL pins feature integrated spike suppression filters

and Schmitt triggers to minimize the effects of input spikes

and bus noise. The TMP175 and TMP75 both support the

transmission protocol for fast (1kHz to 400kHz) and

high-speed (1kHz to 3.4MHz) modes. All data bytes are

transmitted MSB first.

SERIAL BUS ADDRESS

active when the temperature equals or exceeds T_HIGH

To communicate with the TMP175 and TMP75, the master

must first address slave devices via a slave address byte.

The slave address byte consists of seven address bits,

and a direction bit indicating the intent of executing a read

or write operation.

The ALERT pin can also be cleared by resetting the device

with the General Call Reset command. This will also clear

the state of the internal registers in the device returning the

device to Comparator Mode (TM = 0).

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The TMP175 features three address pins to allow up to 27

devices to be addressed on a single bus interface.

Table 11 describes the pin logic levels used to properly

connect up to 27 devices. ‘1’ indicates the pin is connected

to the supply (V_CC); ‘0’ indicates the pin is connected to

GND; Float indicates the pin is left unconnected. The state

of pins A0, A1, and A2 is sampled on every bus

communication and should be set prior to any activity on

the interface.

SLAVE ADDRESS

1001000

1001001

1001010

1001011

1001100

1001101

1001110

1001111

The TMP75 features three address pins allowing up to

eight devices to be connected per bus. Pin logic levels are

described in Table 12. The address pins of the TMP175

and TMP75 are read after reset, at start of communication,

or in response to a Two-Wire address acquire request.

Following reading the state of the pins the address is

latched to minimize power dissipation associated with

detection.

Table 12. Address Pins and Slave Addresses for

the TMP75

BUS OVERVIEW

The device that initiates the transfer is called a master, and

the devices controlled by the master are slaves. The bus

must be controlled by a master device that generates the

serial clock (SCL), controls the bus access, and generates

the START and STOP conditions.

SLAVE ADDRESS

1001000

1001001

1001010

1001011

1001100

1001101

1001110

1001111

1110000

1110001

1110010

1110011

1110100

1110101

1110110

1110111

0101000

0101001

0101010

0101011

0101100

0101101

0101110

0101111

0110101

0110110

0110111

To address a specific device, a START condition is

initiated, indicated by pulling the data-line (SDA) from a

HIGH to LOW logic level while SCL is HIGH. All slaves on

the bus shift in the slave address byte, with the last bit

indicating whether a read or write operation is intended.

During the ninth clock pulse, the slave being addressed

responds to the master by generating an Acknowledge

and pulling SDA LOW.

Data transfer is then initiated and sent over eight clock

pulses followed by an Acknowledge Bit. During data

transfer SDA must remain stable while SCL is HIGH, as

any change in SDA while SCL is HIGH will be interpreted

as a control signal.

Float

Once all data has been transferred, the master generates

a STOP condition indicated by pulling SDA from LOW to

HIGH, while SCL is HIGH.

Float

WRITING/READING TO THE TMP175 AND

TMP75

Accessing a particular register on the TMP175 and TMP75

is accomplished by writing the appropriate value to the

Pointer Register. The value for the Pointer Register is the

first byte transferred after the slave address byte with the

R/W bit LOW. Every write operation to the TMP175 and

TMP75 requires a value for the Pointer Register. (Refer to

Figure 5.)

Float

Table 11. Address Pins and Slave Addresses for

the TMP175

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When reading from the TMP175 and TMP75, the last value

stored in the Pointer Register by a write operation is used

to determine which register is read by a read operation. To

change the register pointer for a read operation, a new

value must be written to the Pointer Register. This is

accomplished by issuing a slave address byte with the

R/W bit LOW, followed by the Pointer Register Byte. No

additional data is required. The master can then generate

a START condition and send the slave address byte with

the R/W bit HIGH to initiate the read command. See

Figure 7 for details of this sequence. If repeated reads

from the same register are desired, it is not necessary to

continually send the Pointer Register bytes, as the

TMP175 and TMP75 will remember the Pointer Register

value until it is changed by the next write operation.

TMP75 or TMP175 is active, the devices will acknowledge

the SMBus Alert command and respond by returning its

slave address on the SDA line. The eighth bit (LSB) of the

slave address byte will indicate if the temperature

exceeding T_HIGHor falling below T_LOWcaused the ALERT

condition. This bit will be HIGH if the temperature is greater

than or equal to T_HIGH. This bit will be LOW if the

temperature is less than T_LOW. Refer to Figure 8 for details

of this sequence.

If multiple devices on the bus respond to the SMBus Alert

command, arbitration during the slave address portion of

the SMBus Alert command will determine which device

will clear its ALERT status. If the TMP75 or TMP175 wins

the arbitration, its ALERT pin will become inactive at the

completion of the SMBus Alert command. If the TMP75 or

TMP175 loses the arbitration, its ALERT pin will remain

active.

Note that register bytes are sent most-significant byte first,

followed by the least significant byte.

GENERAL CALL

SLAVE MODE OPERATIONS

The TMP175 and TMP75 respond to a Two-Wire General

Call address (0000000) if the eighth bit is 0. The device will

acknowledge the General Call address and respond to

commands in the second byte. If the second byte is

00000100, the TMP175 and TMP75 will latch the status of

their address pins, but will not reset. If the second byte is

00000110, the TMP175 and TMP75 will latch the status of

their address pins and reset their internal registers to their

power-up values.

The TMP175 and TMP75 can operate as slave receivers

or slave transmitters.

Slave Receiver Mode:

The first byte transmitted by the master is the slave

address, with the R/W bit LOW. The TMP175 or TMP75

then acknowledges reception of a valid address. The next

byte transmitted by the master is the Pointer Register. The

TMP175 or TMP75 then acknowledges reception of the

Pointer Register byte. The next byte or bytes are written to

the register addressed by the Pointer Register. The

TMP175 and TMP75 will acknowledge reception of each

data byte. The master may terminate data transfer by

generating a START or STOP condition.

HIGH-SPEED MODE

In order for the Two-Wire bus to operate at frequencies

above 400kHz, the master device must issue an Hs-mode

master code (00001XXX) as the first byte after a START

condition to switch the bus to high-speed operation. The

TMP175 and TMP75 will not acknowledge this byte, but

will switch their input filters on SDA and SCL and their

output filters on SDA to operate in Hs-mode, allowing

transfers at up to 3.4MHz. After the Hs-mode master code

has been issued, the master will transmit a Two-Wire slave

address to initiate a data transfer operation. The bus will

continue to operate in Hs-mode until a STOP condition

occurs on the bus. Upon receiving the STOP condition, the

TMP175 and TMP75 will switch the input and output filter

back to fast-mode operation.

Slave Transmitter Mode:

The first byte is transmitted by the master and is the slave

address, with the R/W bit HIGH. The slave acknowledges

reception of a valid slave address. The next byte is

transmitted by the slave and is the most significant byte of

the register indicated by the Pointer Register. The master

acknowledges reception of the data byte. The next byte

transmitted by the slave is the least significant byte. The

master acknowledges reception of the data byte. The

master may terminate data transfer by generating a

Not-Acknowledge on reception of any data byte, or

generating a START or STOP condition.

TIMEOUT FUNCTION

The TMP175 and TMP75 will reset the serial interface if

either SCL or SDA are held LOW for 54ms (typ) between

a START and STOP condition. The TMP175 and TMP75

will release the bus if it is pulled LOW and will wait for a

START condition. To avoid activating the timeout function,

it is necessary to maintain a communication speed of at

least 1kHz for SCL operating frequency.

SMBus ALERT FUNCTION

The TMP175 and TMP75 support the SMBus Alert

function. When the TMP75 and TMP175 are operating in

Interrupt Mode (TM = 1), the ALERT pin of the TMP75 or

TMP175 may be connected as an SMBus Alert signal.

When a master senses that an ALERT condition is present

on the ALERT line, the master sends an SMBus Alert

command (00011001) on the bus. If the ALERT pin of the

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ꢆ ꢠ ꢀꢢ ꢣ

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SBOS288J − JANUARY 2004 − REVISED DECEMBER 2007

Data Transfer: The number of data bytes transferred

between a START and a STOP condition is not limited and

is determined by the master device. The receiver

acknowledges the transfer of data.

TIMING DIAGRAMS

The TMP175 and TMP75 are Two-Wire and SMBus

compatible. Figure 4 to Figure 8 describe the various

operations on the TMP175 and TMP75. Bus definitions are

given below. Parameters for Figure 4 are defined in

Table 13.

Acknowledge: Each receiving device, when addressed,

is obliged to generate an Acknowledge bit. A device that

acknowledges must pull down the SDA line during the

Acknowledge clock pulse in such a way that the SDA line

is stable LOW during the HIGH period of the Acknowledge

clock pulse. Setup and hold times must be taken into

account. On a master receive, the termination of the data

transfer can be signaled by the master generating a

Not-Acknowledge on the last byte that has been

transmitted by the slave.

Bus Idle: Both SDA and SCL lines remain HIGH.

Start Data Transfer: A change in the state of the SDA line,

from HIGH to LOW, while the SCL line is HIGH, defines a

START condition. Each data transfer is initiated with a

START condition.

Stop Data Transfer: A change in the state of the SDA line

from LOW to HIGH while the SCL line is HIGH defines a

STOP condition. Each data transfer is terminated with a

repeated START or STOP condition.

FAST MODE

HIGH-SPEED MODE

PARAMETER

UNITS

MIN

MAX

MIN

0.001

160

MAX

SCL Operating Frequency

0.001

600

0.4

3.4

MHz

(SCL)

(BUF)

Bus Free Time Between STOP and START Condition

Hold time after repeated START condition.

After this period, the first clock is generated.

100

(HDSTA)

Repeated START Condition Setup Time

STOP Condition Setup Time

Data Hold Time

100

(SUSTA)

(SUSTO)

(HDDAT)

Data Setup Time

100

1300

600

(SUDAT)

SCL Clock LOW Period

SCL Clock HIGH Period

Clock/Data Fall Time

160

(LOW)

(HIGH)

300

160

Clock/Data Rise Time

for SCLK ≤ 100kHz

300

1000

Table 13. Timing Diagram Definitions for the TMP175 and TMP75

TWO-WIRE TIMING DIAGRAMS

t_(LOW)

t_F

t_R

t_(HDSTA)

SCL

SDA

t_(SUSTO)

t_(HDSTA)

t_(HIGH)t_(SUSTA)

t_(HDDAT)

t_(SUDAT)

t_(BUF)

Figure 4. Two-Wire Timing Diagram

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SBOS288J − JANUARY 2004 − REVISED DECEMBER 2007

SCL

SDA

…

A1 A0 R/W

ACK By

Start By

ACK By

TMP75

Master

TMP75

Frame 2 Pointer Register Byte

Frame 1 Two−Wire Slave Address Byte

SCL

(Continued)

SDA

(Continued)

D7 D6

D4 D3 D2 D1

ACK By

D3 D2

D1 D0

ACK By

Stop By

Master

TMP75

Frame 3 Data Byte 1

Frame 4 Data Byte 2

Figure 5. Two-Wire Timing Diagram for TMP75 Write Word Format

SCL

…

SDA

R/W

Start By

Master

ACK By

TMP175

ACK By

TMP175

Frame 1 Two−Wire Slave Address Byte

Frame 2 Pointer Register Byte

SCL

(Continued)

SDA

(Continued)

D7 D6

D4 D3 D2 D1

D3 D2

D1 D0

ACK By

Stop By

Master

TMP175

Frame 3 Data Byte 1

Frame 4 Data Byte 2

Figure 6. Two-Wire Timing Diagram for TMP175 Write Word Format

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…

SCL

SDA

R/W

Start By

Master

ACK By

TMP175 or TMP75

ACK By

TMP175 or TMP75

Frame 1 Two−Wire Slave Address Byte

Frame 2 Pointer Register Byte

SCL

(Continued)

…

SDA

(Continued)

…

R/W

D4 D3

Start By

Master

ACK By

TMP175 or TMP75

From

TMP175 or TMP75

ACK By

Master

Frame 3 Two−Wire Slave Address Byte

Frame 4 Data Byte 1 Read Register

SCL

(Continued)

SDA

(Continued)

D7 D6

From

TMP175 or TMP75

ACK By

Master

Stop By

Master

Frame 5 Data Byte 2 Read Register

NOTE: Address Pins A0, A1, A2 = 0

Figure 7. Two-Wire Timing Diagram for Read Word Format

ALERT

SCL

SDA

R/W

Status

Start By

Master

ACK By

TMP175 or TMP75

From

NACK By Stop By

Master

TMP175 or TMP75 Master

Frame 1 SMBus ALERT Response Address Byte

Frame 2 Slave Address Byte

NOTE: Address Pins A0, A1, A2 = 0

Figure 8. Timing Diagram for SMBus ALERT

PACKAGE OPTION ADDENDUM

www.ti.com

20-Oct-2012

PACKAGING INFORMATION

Status ⁽¹⁾

Eco Plan ⁽²⁾

MSL Peak Temp ⁽³⁾

Samples

Orderable Device

Package Type Package

Drawing

Pins

Package Qty

Lead/

Ball Finish

(Requires Login)

TMP175AID

TMP175AIDG4

TMP175AIDGKR

TMP175AIDGKRG4

TMP175AIDGKT

TMP175AIDGKTG4

TMP175AIDR

ACTIVE

SOIC

Green (RoHS

& no Sb/Br)

CU NIPDAU Level-2-250C-1 YEAR

Green (RoHS

& no Sb/Br)

CU NIPDAU Level-2-250C-1 YEAR

CU NIPDAU Level-2-260C-1 YEAR

VSSOP

SOIC

DGK

2500

250

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

250

Green (RoHS

& no Sb/Br)

2500

Green (RoHS

& no Sb/Br)

TMP175AIDRG4

TMP75AID

SOIC

Green (RoHS

& no Sb/Br)

SOIC

Green (RoHS

& no Sb/Br)

Call TI

Level-1-260C-UNLIM

TMP75AIDG4

SOIC

Green (RoHS

& no Sb/Br)

TMP75AIDGKR

TMP75AIDGKRG4

TMP75AIDGKT

TMP75AIDGKTG4

TMP75AIDR

VSSOP

SOIC

DGK

2500

250

Green (RoHS

& no Sb/Br)

CU NIPDAU Level-2-260C-1 YEAR

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

250

Green (RoHS

& no Sb/Br)

2500

Green (RoHS

& no Sb/Br)

Call TI

Level-1-260C-UNLIM

TMP75AIDRG4

SOIC

Green (RoHS

& no Sb/Br)

⁽¹⁾The marketing status values are defined as follows:

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

20-Oct-2012

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

⁽³⁾MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

16-Aug-2012

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

TMP175AIDGKR

TMP175AIDGKT

TMP175AIDR

VSSOP

SOIC

DGK

2500

250

330.0

180.0

330.0

12.4

5.3

6.4

5.3

6.4

3.4

3.3

3.4

5.2

3.4

5.2

1.4

1.3

1.4

2.1

1.4

2.1

8.0

12.0

250

2500

250

TMP75AIDGKR

TMP75AIDGKT

TMP75AIDR

VSSOP

SOIC

DGK

2500

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

16-Aug-2012

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

TMP175AIDGKR

TMP175AIDGKT

TMP175AIDR

VSSOP

SOIC

DGK

2500

250

366.0

370.0

195.0

366.0

367.0

366.0

367.0

364.0

355.0

200.0

364.0

367.0

364.0

367.0

50.0

55.0

45.0

50.0

35.0

50.0

35.0

250

2500

250

TMP75AIDGKR

TMP75AIDGKT

TMP75AIDR

VSSOP

SOIC

DGK

2500

Pack Materials-Page 2

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TMP75AIDRG4 [TI]

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