TMP75BQDQ1 [TI]
TMP75B-Q1 1.8-V Digital Temperature Sensor with Two-Wire Interface and Alert;
| 型号： | TMP75BQDQ1 |
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| 描述： | TMP75B-Q1 1.8-V Digital Temperature Sensor with Two-Wire Interface and Alert |
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TMP75B-Q1
SBOS721 –OCTOBER 2014
TMP75B-Q1 1.8-V Digital Temperature Sensor with Two-Wire Interface and Alert
1 Features
3 Description
The TMP75B-Q1 is an integrated digital temperature
sensor with a 12-bit analog-to-digital converter (ADC)
that can operate at a 1.8-V supply, and is pin and
register compatible with the industry-standard LM75
and TMP75. This device is available in SOIC-8 and
VSSOP-8 packages, and requires no external
components to sense the temperature. The TMP75B-
Q1 is capable of reading temperatures with a
resolution of 0.0625°C and is specified over a
temperature range of –40°C to 125°C.
1
•
Qualified for Automotive Applications
•
AEC-Q100 Qualified with the Following Results:
–
–
–
Temperature Grade 1: –40°C to 125°C
HBM ESD Classification 2
CDM ESD Classification C4B
•
•
•
•
•
•
•
•
Digital Output with Two-Wire Serial Interface
Up to 8 Pin-Programmable Bus Addresses
Programmable Overtemperature ALERT
Shutdown Mode for Power Saving
One-Shot Conversion Mode
The TMP75B-Q1 features SMBus and two-wire
interface compatibility, and allows up to eight devices
on the same bus with the SMBus overtemperature
alert function. The programmable temperature limits
and the ALERT pin allow the sensor to operate as a
stand-alone thermostat, or an overtemperature alarm
for power throttling or system shutdown.
Operating Temperature Range: –40°C to 125°C
Operating Supply Range: 1.4 V to 3.6 V
Quiescent Current:
–
–
45 μA Active (typ)
The factory-calibrated temperature accuracy and the
noise-immune digital interface make the TMP75B-Q1
the preferred solution for temperature compensation
of other sensors and electronic components, without
the need for additional system-level calibration or
elaborate board layout for distributed temperature
sensing.
0.3 μA Shutdown (typ)
•
Accuracy:
–
–
±0.5°C (typ) from –20°C to 85°C
±1°C (typ) from –40°C to 125°C
•
•
Resolution: 12 Bits (0.0625°C)
Packages: SOIC-8 and VSSOP-8
The TMP75B-Q1 is ideal for thermal management
and protection of a variety of automotive applications,
and is a high-performance alternative to a PCB-
mounted NTC thermistor.
2 Applications
•
•
•
•
•
•
•
Automotive Embedded Systems
ECU Processor Temperature Monitoring
TCM Processor Temperature Monitoring
BCM Processor Temperature Monitoring
LED Headlight Thermal Control
Device Information(1)
DEVICE NAME
PACKAGE
SOIC (8)
VSSOP (8)
BODY SIZE (NOM)
4.90 mm × 3.90 mm
3.00 mm × 3.00 mm
TMP75B-Q1
Battery Thermal Protection
(1) For all available packages, see the package option addendum
at the end of the datasheet.
Electrical Motor Driver Thermal Protection
Temperature Accuracy (Error) vs Ambient
Temperature
Simplified Schematic
1.4 V to 3.6 V
3
2
0.01 PF
1
TMP75B-Q1
1
2
3
4
8
7
6
5
SDA
SCL
VS
A0
A1
A2
0
Two-Wire
Host Controller
±1
ALERT
GND
Mean
±2
Mean - 61
Mean + 61
±3
±75 ±50 ±25
0
25
50
75
100 125 150
Temperature (C)
C005
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TMP75B-Q1
SBOS721 –OCTOBER 2014
www.ti.com
Table of Contents
7.4 Device Functional Modes........................................ 15
7.5 Programming........................................................... 16
7.6 Register Map........................................................... 16
Application and Implementation ........................ 19
8.1 Application Information............................................ 19
8.2 Typical Application .................................................. 19
Power-Supply Recommendations...................... 20
1
2
3
4
5
6
Features.................................................................. 1
Applications ........................................................... 1
Description ............................................................. 1
Revision History..................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 Handling Ratings....................................................... 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 4
6.5 Electrical Characteristics........................................... 5
6.6 Typical Characteristics.............................................. 6
Detailed Description .............................................. 7
7.1 Overview ................................................................... 7
7.2 Functional Block Diagram ......................................... 7
7.3 Feature Description................................................... 8
8
9
10 Layout................................................................... 21
10.1 Layout Guidelines ................................................. 21
10.2 Layout Example .................................................... 21
11 Device and Documentation Support ................. 22
11.1 Documentation Support ....................................... 22
11.2 Trademarks........................................................... 22
11.3 Electrostatic Discharge Caution............................ 22
11.4 Glossary................................................................ 22
7
12 Mechanical, Packaging, and Orderable
Information ........................................................... 22
4 Revision History
DATE
REVISION
NOTES
October 2014
*
Initial release.
2
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5 Pin Configuration and Functions
D and DGK Packages
SOIC-8 and VSSOP-8
(Top View)
SDA
SCL
1
2
3
4
8
7
6
5
VS
A0
A1
A2
ALERT
GND
Pin Functions
PIN
I/O
DESCRIPTION
NAME
A0
NO.
7
I
I
Address select. Connect to GND or VS.
Address select. Connect to GND or VS.
Address select. Connect to GND or VS.
A1
6
A2
5
I
ALERT
GND
SCL
SDA
VS
3
O
—
I
Overtemperature alert. Open-drain output; requires a pull-up resistor.
4
Ground
2
Serial clock
1
I/O
I
Serial data. Open-drain output; requires a pull-up resistor.
Supply voltage, 1.4 V to 3.6 V
8
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
UNIT
V
Supply voltage, VS
4
SDA, SCL, ALERT, A2, A1
–0.3
–0.3
4
(VS) + 0.3
10
V
Input voltage
A0
V
Sink current
SDA, ALERT
mA
°C
Operating junction temperature
–55
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 Handling Ratings
MIN
–60
MAX
150
UNIT
Tstg
Storage temperature range
Electrostatic discharge
°C
Human body model (HBM), per AEC Q100-002(1)
–2000
2000
Corner pins (1, 4, 5,
V(ESD)
–1000
–1000
1000
1000
V
Charged device model (CDM), per
AEC Q100-011
and 8)
Other pins
(1) AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
1.4
NOM
MAX
3.6
UNIT
Supply voltage
1.8
V
Operating free-air temperature, TA
–40
125
°C
6.4 Thermal Information
TMP75B-Q1
THERMAL METRIC(1)
D (SOIC)
8 PINS
125.4
71.5
DGK (VSSOP)
UNIT
8 PINS
188.1
79.1
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
RθJC(top)
RθJB
65.8
109.6
15.3
°C/W
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
21.1
ψJB
65.3
108
RθJC(bot)
N/A
N/A
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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6.5 Electrical Characteristics
At TA = –40°C to 125°C and VS = 1.4 V to 3.6 V, unless otherwise noted. Typical values at TA = 25°C and VS = 1.8 V.
PARAMETER
TEMPERATURE INPUT
Temperature range
TEST CONDITIONS
MIN
TYP
MAX
UNIT
–40
125
°C
°C
°C
°C
Temperature resolution
0.0625
±0.5
±1
–20°C to 85°C
–40°C to 125°C
±2
±3
Temperature accuracy
(error)
DIGITAL INPUT/OUTPUT
VIH
VIL
IIN
High-level input voltage
Low-level input voltage
Input current
0.7(VS)
–0.3
VS
0.3(VS)
1
V
V
0 V < VIN < (VS) + 0.3 V
S ≥ 2 V, IOUT = 3 mA
μA
V
0.4
V
Low-level output
voltage
VOL
VS < 2 V, IOUT = 3 mA
0.2(VS)
V
ADC resolution
Conversion time
12
27
37
18
9
Bit
One-shot mode
20
35
ms
CR1 = 0, CR0 = 0 (default)
CR1 = 0, CR0 = 1
CR1 = 1, CR0 = 0
CR1 = 1, CR0 = 1
Conv/s
Conv/s
Conv/s
Conv/s
ms
Conversion modes
Timeout time
4
38
54
70
POWER SUPPLY
Operating supply range
1.4
3.6
89
48
30
21
8
V
Serial bus inactive, CR1 = 0, CR0 = 0 (default)
Serial bus inactive, CR1 = 0, CR0 = 1
Serial bus inactive, CR1 = 1, CR0 = 0
Serial bus inactive, CR1 = 1, CR0 = 1
Serial bus inactive
45
22
μA
μA
μA
μA
μA
μA
μA
IQ
Quiescent current
Shutdown current
12
6.5
0.3
10
ISD
Serial bus active, SCL frequency = 400 kHz
Serial bus active, SCL frequency = 3.4 MHz
80
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6.6 Typical Characteristics
At TA = 25°C and VS = 1.8 V (unless otherwise noted).
100
10
9
8
7
6
5
4
3
2
1
0
CR = '0h'
Vs = 1.4V
Vs = 1.8V
Vs = 3.6V
90
80
70
60
50
40
30
20
10
0
CR = '1h'
CR = '2h'
CR = '3h'
±75 ±50 ±25
0
25
50
75
100 125 150
±75 ±50 ±25
0
25
50
75
100 125 150
Temperature (C)
Temperature (C)
C001
C002
Figure 1. Quiescent Current vs Temperature
Figure 2. Shutdown Current vs Temperature
30
29
28
27
26
25
24
23
22
21
20
200
175
150
125
100
75
Ta = -ꢀꢀÛ&
7Dꢁ ꢁꢂꢀÛ&
7Dꢁ ꢁꢃꢂꢀÛ&
50
Vs = 1.4V
Vs = 1.8V
Vs = 3.6V
25
0
±75 ±50 ±25
0
25
50
75
100 125 150
10
100
1000
10000
Temperature (C)
Bus Frequency (kHz)
C003
C004
Figure 3. Conversion Time vs Temperature
Figure 4. Quiescent Current vs Bus Frequency
3
2
1
0
±1
±2
±3
Mean
Mean - 61
Mean + 61
±75 ±50 ±25
0
25
50
75
100 125 150
Temperature (C)
C005
Temperature Error (C)
C006
Figure 6. Temperature Error at 25°C
Figure 5. Temperature Error vs Temperature
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7 Detailed Description
7.1 Overview
The TMP75B-Q1 is a digital temperature sensor optimal for thermal management and thermal protection
applications. The TMP75B-Q1 is two-wire and SMBus interface compatible, and is specified over a temperature
range of –40°C to 125°C.
The temperature sensing device for the TMP75B-Q1 is the chip itself. A bipolar junction transistor (BJT) inside
the chip is used in a band-gap configuration to produce a voltage proportional to the chip temperature. The
voltage is digitized and converted to a 12-bit temperature result in degrees Celsius, with a resolution of
0.0625°C. The package leads provide the primary thermal path because of the lower thermal resistance of the
metal. Thus, the temperature result is equivalent to the local temperature of the printed circuit board (PCB) where
the sensor is mounted.
7.2 Functional Block Diagram
VS
Device
Voltage Regulator
Serial Interface
Register Bank
Oscillator
SDA
SCL
A0
Control Logic
N x I
I
ALERT
A1
A2
ADC
Thermal
BJT
GND
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7.3 Feature Description
7.3.1 Digital Temperature Output
The 12-bit digital output from each temperature measurement conversion is stored in the read-only temperature
register. Two bytes must be read to obtain the data; see Figure 15. Note that byte 1 is the most significant byte,
followed by byte 2, the least significant byte. The temperature result is left-justified with the 12 most significant
bits used to indicate the temperature. There is no need to read the second byte if resolution below 1°C is not
required. Table 1 summarizes the temperature data format. One LSB equals 0.0625°C. Negative numbers are
represented in binary twos complement format.
Table 1. Temperature Data Format(1)
DIGITAL OUTPUT
TEMPERATURE (°C)
BINARY
HEX
7FF
7FF
640
500
4B0
320
190
004
000
FFC
E70
C90
128
127.9375
100
80
0111 1111 1111
0111 1111 1111
0110 0100 0000
0101 0000 0000
0100 1011 0000
0011 0010 0000
0001 1001 0000
0000 0000 0100
0000 0000 0000
1111 1111 1100
1110 0111 0000
1100 1001 0000
75
50
25
0.25
0
–0.25
–25
–55
(1) The temperature sensor resolution is 0.0625°C/LSB.
Table 1 does not supply a full list of all temperatures. Use the following rules to obtain the digital data format for
a given temperature, and vice versa.
To convert positive temperatures to a digital data format:
Divide the temperature by the resolution. Then, convert the result to binary code with a 12-bit, left-justified
format, and MSB = 0 to denote a positive sign.
Example: (50°C) / (0.0625°C / LSB) = 800 = 320h = 0011 0010 0000
To convert a positive digital data format to temperature:
Convert the 12-bit, left-justified binary temperature result, with the MSB = 0 to denote a positive sign, to a
decimal number. Then, multiply the decimal number by the resolution to obtain the positive temperature.
Example: 0011 0010 0000 = 320h = 800 × (0.0625°C / LSB) = 50°C
To convert negative temperatures to a digital data format:
Divide the absolute value of the temperature by the resolution, and convert the result to binary code with a
12-bit, left-justified format. Then, generate the twos complement of the result by complementing the binary
number and adding one. Denote a negative number with MSB = 1.
Example: (|–25°C|) / (0.0625°C / LSB) = 400 = 190h = 0001 1001 0000
Two's complement format: 1110 0110 1111 + 1 = 1110 0111 0000
To convert a negative digital data format to temperature:
Generate the twos compliment of the 12-bit, left-justified binary number of the temperature result (with MSB
= 1, denoting negative temperature result) by complementing the binary number and adding one. This
represents the binary number of the absolute value of the temperature. Convert to decimal number and
multiply by the resolution to get the absolute temperature, then multiply by –1 for the negative sign.
Example: 1110 0111 0000 has twos compliment of 0001 1001 0000 = 0001 1000 1111 + 1
Convert to temperature: 0001 1001 0000 = 190h = 400; 400 × (0.0625°C / LSB) = 25°C = (|–25°C|);
(|–25°C|) × (–1) = –25°C
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7.3.2 Temperature Limits and Alert
The temperature limits are stored in the TLOW and THIGH registers (Table 8 and Table 9) in the same format as
the temperature result, and their values are compared to the temperature result on every conversion. The
outcome of the comparison drives the behavior of the ALERT pin, which can operate as a comparator output or
an interrupt, and is set by the TM bit in the configuration register (Table 7).
In comparator mode (TM = 0, default), the ALERT pin becomes active when the temperature is equal to or
exceeds the value in THIGH (fault conditions) for a consecutive number of conversions as set by the FQ bits of the
configuration register. ALERT clears when the temperature falls below TLOW for the same consecutive number of
conversions. The difference between the two limits acts as a hysteresis on the comparator output, and a fault
counter prevents false alerts as a result of environmental noise.
In interrupt mode (TM = 1), the ALERT pin becomes active when the temperature equals or exceeds the value in
THIGH for a consecutive number of fault conditions. The ALERT pin remains active until a read operation of any
register occurs, or the device successfully responds to the SMBus alert response address. The ALERT pin is
also cleared if the device is placed in shutdown mode (see the Shutdown Mode section for shutdown mode
description). After the ALERT pin is cleared, this pin becomes active again only when the temperature falls below
TLOW for a consecutive number of fault conditions, and remains active until cleared by a read operation of any
register, or a successful response to the SMBus alert response address. After the ALERT pin is cleared, the
cycle repeats with the ALERT pin becoming active when the temperature equals or exceeds THIGH, and so on.
The ALERT pin can also be cleared by resetting the device with the general-call reset command. This action also
clears the state of the internal registers in the device and the fault counter memory, returning the device to
comparator mode (TM = 0).
The active state of the ALERT pin is set by the POL bit in the configuration register. When POL = 0 (default), the
ALERT pin is active low. When POL = 1, the ALERT pin is active high. The operation of the ALERT pin in
various modes is shown in Figure 7.
THIGH
Measured
Temperature
TLOW
Device ALERT PIN
(Comparator Mode)
POL = 0
Device ALERT PIN
(Interrupt Mode)
POL = 0
Device ALERT PIN
(Comparator Mode)
POL = 1
Device ALERT PIN
(Interrupt Mode)
POL = 1
Read
Read
Time
Read
Figure 7. ALERT Pin Modes of Operation
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7.3.3 Serial Interface
The TMP75B-Q1 operates as a slave device only on the two-wire bus and SMBus. Connections to the bus are
made using the open-drain I/O lines, SDA and SCL. The SDA and SCL pins feature integrated spike-suppression
filters and Schmitt triggers to minimize the effects of input spikes and bus noise. The TMP75B-Q1 supports the
transmission protocol for both fast (1 kHz to 400 kHz) and high-speed (1 kHz to 3 MHz) modes. All data bytes
are transmitted MSB first.
7.3.3.1 Bus Overview
The device that initiates the transfer is called a master, and the devices controlled by the master are slaves. The
bus must be controlled by a master device that generates the serial clock (SCL), controls the bus access, and
generates the start and stop conditions.
To address a specific device, initiate a start condition by pulling the data line (SDA) from a high to a low logic
level while SCL is high. All slaves on the bus shift in the slave address byte; the last bit indicates whether a read
or write operation follows. During the ninth clock pulse, the slave being addressed responds to the master by
generating an acknowledge bit and pulling SDA low.
Data transfer is then initiated and sent over eight clock pulses followed by an acknowledge bit. During data
transfer, SDA must remain stable while SCL is high because any change in SDA while SCL is high is interpreted
as a start or stop signal.
After all data have been transferred, the master generates a stop condition indicated by pulling SDA from low to
high, while SCL is high.
7.3.3.2 Serial Bus Address
To communicate with the TMP75B-Q1, the master must first communicate with slave devices using a slave
address byte. The slave address byte consists of seven address bits, and a direction bit indicating the intent of
executing either a read or write operation. The TMP75B-Q1 features three address pins that allow up to eight
devices to be addressed on a single bus. The TMP75B-Q1 latches the status of the address pins at the start of a
communication. Table 2 describes the pin logic levels and the corresponding address values.
Table 2. Address Pin Connections and Slave Addresses
DEVICE TWO-WIRE ADDRESS
A2
GND
GND
GND
GND
VS
A1
GND
GND
VS
A0
GND
VS
1001000
1001001
1001010
1001011
1001100
1001101
1001110
1001111
GND
VS
VS
GND
GND
VS
GND
VS
VS
VS
GND
VS
VS
VS
7.3.3.3 Writing and Reading Operation
Accessing a particular register on the TMP75B-Q1 is accomplished by writing the appropriate value to the pointer
register. The value for the pointer register is the first byte transferred after the slave address byte with the R/W
bit low. Every write operation to the TMP75B-Q1 requires a value for the pointer register (see Figure 9).
When reading from the TMP75B-Q1, the last value stored in the pointer register by a write operation is used to
determine which register is read by a read operation. To change the register pointer for a read operation, a new
value must be written to the pointer register. This action is accomplished by issuing a slave address byte with the
R/W bit low, followed by the pointer register byte. No additional data are required. The master can then generate
a start condition and send the slave address byte with the R/W bit high to initiate the read command. See
Figure 10 for details of this sequence. If repeated reads from the same register are desired, there is no need to
continually send the pointer register bytes because the TMP75B-Q1 stores the pointer register value until it is
changed by the next write operation.
Note that register bytes are sent with the most significant byte first, followed by the least significant byte.
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7.3.3.4 Slave-Mode Operations
The TMP75B-Q1 can operate as a slave receiver or slave transmitter.
7.3.3.4.1 Slave Receiver Mode:
The first byte transmitted by the master is the slave address, with the R/W bit low. The TMP75B-Q1 then
acknowledges reception of a valid address. The next byte transmitted by the master is the pointer register. The
TMP75B-Q1 then acknowledges reception of the pointer register byte. The next byte or bytes are written to the
register addressed by the pointer register. The TMP75B-Q1 acknowledges reception of each data byte. The
master can terminate data transfer by generating a start or stop condition.
7.3.3.4.2 Slave Transmitter Mode:
The first byte transmitted by the master is the slave address, with the R/W bit high. The slave acknowledges
reception of a valid slave address. The next byte is transmitted by the slave and is the most significant byte of
the register indicated by the pointer register. The master acknowledges reception of the data byte. The next byte
transmitted by the slave is the least significant byte. The master acknowledges reception of the data byte. The
master can terminate data transfer by generating a not-acknowledge bit on reception of any data byte, or by
generating a start or stop condition.
7.3.3.5 SMBus Alert Function
The TMP75B-Q1 supports the SMBus alert function. When the TMP75B-Q1 operates in interrupt mode (TM = 1),
the ALERT pin may be connected as an SMBus alert signal. When a master senses that an alert condition is
present on the ALERT line, the master sends an SMBus alert command (00011001) to the bus. If the ALERT pin
is active, the device acknowledges the SMBus alert command and responds by returning its slave address on
the SDA line. The eighth bit (LSB) of the slave address byte indicates whether the alert condition is caused by
the temperature exceeding THIGH or falling below TLOW. The LSB is high if the temperature is greater than THIGH
or low if the temperature is less than TLOW. See Figure 11 for details of this sequence.
,
If multiple devices on the bus respond to the SMBus alert command, arbitration during the slave address portion
of the SMBus alert command determines which device clears its alert status first. If the TMP75B-Q1 wins the
arbitration, its ALERT pin becomes inactive at the completion of the SMBus alert command. If the TMP75B-Q1
loses the arbitration, its ALERT pin remains active.
7.3.3.6 General Call
The TMP75B-Q1 responds to a two-wire general call address (0000000) if the eighth bit is 0. The device
acknowledges the general call address and responds to commands in the second byte. If the second byte is
00000100, the TMP75B-Q1 latches the status of the address pin, but does not reset. If the second byte is
00000110, the TMP75B-Q1 internal registers are reset to power-up values.
7.3.3.7 High-Speed (Hs) Mode
In order for the two-wire bus to operate at frequencies above 400 kHz, the master device must issue an SMBus
Hs-mode master code (00001xxx) as the first byte after a start condition to switch the bus to high-speed
operation. The TMP75B-Q1 does not acknowledge this byte, but does switch its input filters on SDA and SCL
and its output filters on SDA to operate in Hs-mode, allowing transfers at up to 3 MHz. After the Hs-mode master
code has been issued, the master transmits a two-wire slave address to initiate a data-transfer operation. The
bus continues to operate in Hs-mode until a stop condition occurs on the bus. Upon receiving the stop condition,
the TMP75B-Q1 switches the input and output filters back to fast-mode operation.
7.3.3.8 Timeout Function
The TMP75B-Q1 resets the serial interface if SCL or SDA are held low for 54 ms (typ) between a start and stop
condition. If the TMP75B-Q1 is pulled low, it releases the bus and then waits for a start condition. To avoid
activating the timeout function, it is necessary to maintain a communication speed of at least 1 kHz for the SCL
operating frequency.
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7.3.3.9 Two-Wire Timing
The TMP75B-Q1 is two-wire and SMBus compatible. Figure 8 to Figure 11 describe the various operations on
the TMP75B-Q1. Parameters for Figure 8 are defined in Table 3. Bus definitions are:
Bus Idle
Both SDA and SCL lines remain high.
Start Data Transfer A change in the state of the SDA line, from high to low, while the SCL line is high defines a
start condition. Each data transfer is initiated with a start condition.
Stop Data Transfer A change in the state of the SDA line from low to high while the SCL line is high defines a
stop condition. Each data transfer is terminated with a repeated start or stop condition.
Data Transfer The number of data bytes transferred between a start and a stop condition is not limited, and is
determined by the master device.
The receiver acknowledges the transfer of data. It is also possible to use the TMP75B-Q1 for
single-byte updates. To update only the MS byte, terminate communication by issuing a start
or stop condition on the bus.
Acknowledge Each receiving device, when addressed, must generate an acknowledge bit.
A device that acknowledges must pull down the SDA line during the acknowledge clock
pulse so that the SDA line is stable low during the high period of the acknowledge clock
pulse. Setup and hold times must be taken into account. When a master receives data, the
termination of the data transfer can be signaled by the master generating a not-acknowledge
(1) on the last byte transmitted by the slave.
Table 3. Timing Diagram Requirements
FAST MODE
MIN
HIGH-SPEED MODE
PARAMETER
MAX
0.4
MIN
0.001
0.001
160
MAX
UNIT
MHz
MHz
ns
V
S ≥ 1.8 V
VS < 1.8 V
S ≥ 1.8 V
VS < 1.8 V
0.001
3
f(SCL)
SCL operating frequency
0.001
0.4
2.5
V
1300
Bus free time between
stop and start conditions
t(BUF)
1300
260
ns
Hold time after repeated start condition.
After this period, the first clock is generated.
t(HDSTA)
600
160
ns
t(SUSTA)
t(SUSTO)
Repeated start condition setup time
Stop condition setup time
600
600
0
160
160
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
V
S ≥ 1.8 V
VS < 1.8 V
S ≥ 1.8 V
VS < 1.8 V
S ≥ 1.8 V
VS < 1.8 V
900
900
100
140
t(HDDAT)
t(SUDAT)
t(LOW)
Data hold time
0
0
V
100
100
1300
1300
600
10
Data setup time
SCL clock low period
20
V
190
240
60
t(HIGH)
SCL clock high period
Data rise and fall time
Clock rise and fall time
tR(SDA), tF(SDA)
tR(SCL), tF(SCL)
tR
300
300
80
40
Clock and data rise time for SCLK ≤ 100 kHz
1000
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7.3.3.10 Two-Wire Timing Diagrams
t(LOW)
tF
tR
t(HDSTA)
SCL
t(HDSTA)
t(HIGH) t(SUSTA)
t(SUSTO)
t(HDDAT)
t(SUDAT)
SDA
t(BUF)
P
S
S
P
Figure 8. Two-Wire Timing Diagram
1
9
1
9
SCL
SDA
¼
A2(1) A1(1) A0(1)
1
0
0
1
R/W
0
0
0
0
0
0
P1
P0
¼
Start By
Master
ACK By
ACK By
Device
Device
Frame 2 Pointer Register Byte
Frame 1 Two-Wire Slave Address Byte
1
9
1
9
SCL
(Continued)
SDA
D7 D6
D5
D4 D3
D2 D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
(Continued)
ACK By
Device
ACK By
Stop By
Master
Device
Frame 3 Data Byte 1
Frame 4 Data Byte 2
(1) The value of A0, A1, and A2 are determined by the connections of the corresponding pins.
Figure 9. Two-Wire Timing Diagram for Write Word Format
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1
9
1
9
¼
SCL
SDA
1
0
0
1
A2(1) A1(1) A0(1)
R/W
0
0
0
0
0
0
P1
P0
Start By
Master
ACK By
ACK By
Stop By
Master
Device
Device
Frame 1 Two-Wire Slave Address Byte
Frame 2 Pointer Register Byte
1
9
1
9
SCL
¼
(Continued)
SDA
A1(1) A0(1)
A2(1)
¼
1
0
0
1
R/W
D7
D6
D5
D4 D3
D2
D1
D0
(Continued)
Start By
Master
ACK By
From
Device
ACK By
Master(2)
Device
Frame 3 Two-Wire Slave Address Byte
Frame 4 Data Byte 1 Read Register
1
SCL
9
(Continued)
SDA
D7 D6
D5
D4
D3
D2
D1
D0
(Continued)
From
ACK By
Master(3)
Stop By
Master
Device
Frame 5 Data Byte 2 Read Register
(1) The value of A0, A1, and A2 are determined by the connections of the corresponding pins.
(2) Master should leave SDA high to terminate a single-byte read operation.
(3) Master should leave SDA high to terminate a two-byte read operation.
Figure 10. Two-Wire Timing Diagram for Read Word Format
ALERT
1
9
1
9
SCL
SDA
A2(1) A1(1) A0(1)
0
0
0
1
1
0
0
R/W
1
0
0
1
Status
Start By
Master
ACK By
From
NACK By Stop By
Master Master
Device
Device
Frame 1 SMBus ALERT Response Address Byte
Frame 2 Slave Address From Device
(1) The value of A0, A1, and A2 are determined by the connections of the corresponding pins.
Figure 11. Timing Diagram for SMBus Alert
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7.4 Device Functional Modes
7.4.1 Continuous-Conversion Mode
The default mode of the TMP75B-Q1 is continuous conversion, where the ADC performs continuous temperature
conversions and stores each result to the temperature register, overwriting the result from the previous
conversion. Conversion rate bits CR1 and CR0 in the configuration register configure the TMP75B-Q1 for typical
conversion rates of 37 Hz, 18 Hz, 9 Hz, or 4 Hz. The TMP75B-Q1 has a typical conversion time of 27 ms. To
achieve different conversion rates, the TMP75B-Q1 makes a conversion, and then powers down and waits for
the appropriate delay set by CR1 and CR0. The default rate is 37 Hz (no delay between conversions).Table 4
shows the settings for CR1 and CR0.
Table 4. Conversion Rate Settings
CR1
CR0
CONVERSION RATE (TYP)
IQ (TYP)
45 μA
0
0
1
1
0
1
0
1
37 Hz (continuous conversion, default)
18 Hz
9 Hz
4 Hz
22 μA
12 μA
6.5 μA
After power-up or a general-call reset, the TMP75B-Q1 immediately starts a conversion, as shown in Figure 12.
The first result is available after 27 ms (typical). The active quiescent current during conversion is 45 μA (typical
at 25°C). The quiescent current during delay is 1 μA (typical at 25°C).
Delay(1)
Delay(1)
27 ms
27 ms
27 ms
Startup
Start of
Conversion
Start of
Conversion
(1) Delay is set by the CR bits in the configuration register.
Figure 12. Conversion Start
7.4.2 Shutdown Mode
Shutdown mode saves maximum power by shutting down all device circuitry other than the serial interface, and
reduces current consumption to typically less than 0.3 μA. Shutdown mode is enabled when the SD bit in the
configuration register is set to 1; the device shuts down after the current conversion is completed. When SD is
equal to 0, the device operates in continuous-conversion mode. When shutdown mode is enabled, the ALERT
pin and fault counter clear in both comparator and interrupt modes; however, this clearing occurs with the rising
edge of the shutdown signal. After shutdown is enabled, reprogramming shutdown does not clear the ALERT pin
and the fault counter until a rising edge is generated on the shutdown signal.
7.4.3 One-Shot Mode
The TMP75B-Q1 features a one-shot temperature measurement mode. When the device is in shutdown mode,
writing a 1 to the OS bit starts a single temperature conversion. The device returns to the shutdown state at the
completion of the single conversion. This mode reduces power consumption in the TMP75B-Q1 when continuous
temperature monitoring is not required. When the configuration register is read, the OS bit always reads zero.
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7.5 Programming
Figure 13 shows the internal register structure of the TMP75B-Q1. Use the 8-bit pointer register to address a
given data register. The pointer register uses the two LSBs to identify which of the data registers respond to a
read or write command. Figure 14 identifies the bits of the pointer register byte.
Pointer
Register
Temperature
Register
SCL
Configuration
Register
I/O
Control
Interface
TLOW
Register
SDA
THIGH
Register
Figure 13. Internal Register Structure
7.6 Register Map
Table 5 describes the registers available in the TMP75B-Q1 with their pointer addresses, followed by the
description of the bits in each register.
Table 5. Register Map and Pointer Addresses
P1
0
P0
0
REGISTER
Temperature register (read only, default)
Configuration register (read/write)
TLOW register (read/write)
0
1
1
0
1
1
THIGH register (read/write)
Figure 14. Pointer Register (pointer = N/A) [reset = 00h]
7
6
5
4
3
2
1
0
Reserved
W-0h
P1
P0
W-0h
W-0h
LEGEND: R/W = Read/Write; R = Read only; W = Write only; -n = value after reset
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Figure 15. Temperature Register (pointer = 0h) [reset = 0000h]
15
14
13
T9
12
T8
11
T7
10
T6
9
8
T11
T10
T5
T4
R-0h
7
6
5
4
3
2
1
0
T3
T2
T1
T0
Reserved
R-0h
R-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 6. Temperature Register Description
Name
Description
T11 to T4
T3 to T0
The 8 MSBs of the temperature result (resolution of 1°C)
The 4 LSBs of the temperature result (resolution of 0.0625°C)
Figure 16. Configuration Register (pointer = 1h) [reset = 00FFh]
15
14
6
13
12
11
10
9
8
OS
CR
FQ
POL
TM
SD
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
7
5
4
3
2
1
0
Reserved
R-FFh
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7. Configuration Register Description
Name
Description
OS
One-shot mode
In shutdown (SD = 1), write 1 to start a conversion. OS always reads back 0.
Conversion rate control
CR
CR = 0h: 37-Hz conversion rate (typ) (default)
CR = 1h: 18-Hz conversion rate (typ)
CR = 2h: 9-Hz conversion rate (typ)
CR = 3h: 4-Hz conversion rate (typ)
Fault queue to trigger the ALERT pin
FQ = 0h: 1 fault (default)
FQ
FQ = 1h: 2 faults
FQ = 2h: 4 faults
FQ = 3h: 6 faults
POL
TM
ALERT polarity control
POL = 0: ALERT is active low (default)
POL = 1: ALERT is active high
ALERT thermostat mode control
TM = 0: ALERT is in comparator mode (default)
TM = 1: ALERT is in interrupt mode
Shutdown control bit
SD
SD = 0: Device is in continuous conversion mode (default)
SD = 1: Device is in shutdown mode
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Figure 17. TLOW: Temperature Low Limit Register (pointer = 2h) [reset = 4B00h](1)
15
14
13
L9
12
L8
11
L7
10
L6
9
8
L11
L10
L5
L4
R/W-4Bh
7
6
5
4
3
2
1
0
L3
L2
L1
L0
Reserved
R-0h
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
(1) 4B00h = 75°C.
Table 8. TLOW Register Description
Name
Description
The 8 MSBs of the temperature low limit (resolution of 1°C)
The 4 LSBs of the temperature low limit (resolution of 0.0625°C)
L11 to L4
L3 to L0
Figure 18. THIGH: Temperature High Limit Register (pointer = 3h) [reset = 5000h](1)
15
14
13
12
11
10
9
8
H11
H10
H9
H8
H7
H6
H5
H4
R/W-50h
7
6
5
4
3
2
1
0
H3
H2
H1
H0
Reserved
R-0h
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
(1) 5000h = 80°C.
Table 9. THIGH Register Description
Name
Description
The 8 MSBs of the temperature high limit (resolution of 1°C)
The 4 LSBs of the temperature high limit (resolution of 0.0625°C)
H11 to H4
H3 to H0
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TMP75B-Q1 is used to measure the PCB temperature of the location it is mounted. The programmable
address options allow up to eight locations on the board to be monitored on a single serial bus. Connecting the
ALERT pins together and programming the temperature limit registers to desired values allows for a temperature
watchdog operation of all devices, interrupting the host controller only if the temperature exceeds the limits.
8.2 Typical Application
1.4 V to 3.6 V
0.01 PF
TMP75B-Q1
1
2
3
4
8
7
6
5
SDA
VS
A0
A1
A2
Two-Wire
Host Controller
SCL
Connect to VS or
GND for up to 8
Address
ALERT
GND
Combinations
1.4 V to 3.6 V
TMP75B-Q1
0.01 PF
1
2
3
4
8
7
SDA
VS
A0
A1
A2
SCL
Connect to VS or
GND for up to 8
Address
6
5
ALERT
GND
Combinations
Additional
Sensor
Locations
Figure 19. Temperature Monitoring of Multiple Locations on a PCB
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Typical Application (continued)
8.2.1 Design Requirements
The TMP75B-Q1 only requires pull-up resistors on SDA and ALERT, although a pull-up resistor is typically
present on the SCL as well. A 0.01-μF bypass capacitor on the supply is recommended, as shown in Figure 19.
The SCL, SDA, and ALERT lines can be pulled up to a supply that is equal to or higher than VS through the pull-
up resistors. To configure one of eight different addresses on the bus, connect A0, A1, and A2 to either VS or
GND.
8.2.2 Detailed Design Procedure
The TMP75B-Q1 should be placed in close proximity to the heat source to be monitored, with a proper layout for
good thermal coupling. This ensures that temperature changes are captured within the shortest possible time
interval.
8.2.3 Application Curve
Figure 20 shows the step response of the TMP75B-Q1 to a submersion in an oil bath of 100°C from room
temperature (27°C). The time-constant, or the time for the output to reach 63% of the input step, is 1.5 seconds.
100
95
90
85
80
75
70
65
60
55
50
45
40
35
30
25
±1 0
1
2
3
4
5
6
7
8
9 1011121314151617181920
Time (s)
C007
Figure 20. Temperature Step Response
9 Power-Supply Recommendations
The TMP75B-Q1 operates with power supply in the range of 1.4 V to 3.6 V. It is optimized for operation at 1.8-V
supply but can measure temperature accurately in the full supply range.
A power-supply bypass capacitor is recommended; place this capacitor as close as possible to the supply and
ground pins of the device. A typical value for this supply bypass capacitor is 0.01 μF. Applications with noisy or
high-impedance power supplies may require additional decoupling capacitors to reject power-supply noise.
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10 Layout
10.1 Layout Guidelines
Place the temperature sensor as close as possible and run copper planes on the ground or other layers to
ensure good thermal coupling to the heat source for fast settling and accurate measurement of the temperature
of the hot spot.
Place the power-supply bypass capacitor as close as possible to the supply and ground pins.
Pull up the open-drain output pins (SDA and ALERT) to a supply voltage rail (VS or higher but up to 3.6 V)
through 10-kΩ pull-up resistors. Smaller values of the resistors can be used to compensate for long bus traces
that can cause an increase in capacitance and slow rise time for the open-drain outputs; the values should not
be less than 1kΩ to avoid self-heating effects due to increased current through the part in the low states of the
outputs.
10.2 Layout Example
Via to Power or Ground Plane
Via to Internal Layer
Pull-Up Resistors
Supply Bypass
Capacitor
Supply Voltage
SDA
VS
A0
A1
A2
SCL
ALERT
GND
Ground Plane for
Thermal Coupling
to Heat Source
Serial Bus Traces
Heat Source
Figure 21. Layout Example
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11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
SBOU141 — TMP75xEVM User's Guide
11.2 Trademarks
All trademarks are the property of their respective owners.
11.3 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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11-Apr-2015
PACKAGING INFORMATION
Orderable Device
TMP75BQDGKRQ1
TMP75BQDGKTQ1
TMP75BQDQ1
Status Package Type Package Pins Package
Eco Plan
Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 125
-40 to 125
-40 to 125
-40 to 125
Device Marking
Samples
Drawing
Qty
(1)
(2)
(6)
(3)
(4/5)
ACTIVE
VSSOP
VSSOP
SOIC
DGK
8
8
8
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
CU NIPDAUAG
CU NIPDAU-DCC
CU NIPDAU-DCC
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
T75BQ
ACTIVE
ACTIVE
ACTIVE
DGK
D
250
75
Green (RoHS
& no Sb/Br)
T75BQ
T75BQ
T75BQ
Green (RoHS
& no Sb/Br)
TMP75BQDRQ1
SOIC
D
2500
Green (RoHS
& no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2015
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TMP75B-Q1 :
Catalog: TMP75B
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
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15-Dec-2015
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TMP75BQDGKRQ1
TMP75BQDGKTQ1
TMP75BQDRQ1
VSSOP
VSSOP
SOIC
DGK
DGK
D
8
8
8
2500
250
330.0
330.0
330.0
12.4
12.4
12.4
5.3
5.3
6.4
3.4
3.4
5.2
1.4
1.4
2.1
8.0
8.0
8.0
12.0
12.0
12.0
Q1
Q1
Q1
2500
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
15-Dec-2015
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TMP75BQDGKRQ1
TMP75BQDGKTQ1
TMP75BQDRQ1
VSSOP
VSSOP
SOIC
DGK
DGK
D
8
8
8
2500
250
366.0
366.0
367.0
364.0
364.0
367.0
50.0
50.0
35.0
2500
Pack Materials-Page 2
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