TMS27C240-15JL [TI]
16-BIT PROGRAMMABLE READ-ONLY MEMORIES; 16位可编程只读存储器
| 型号： | TMS27C240-15JL |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 16-BIT PROGRAMMABLE READ-ONLY MEMORIES |
| 文件： | 总15页 (文件大小：203K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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SMLS240D− NOVEMBER 1990 − REVISED SEPTEMBER 1997
TMS27PC240 FN PACKAGE
(TOP VIEW)
D
D
D
D
D
Organization . . . 262144 by 16 Bits
Single 5-V Power Supply
All Inputs/Outputs Fully TTL Compatible
Static Operations (No Clocks, No Refresh)
Max Access/Min Cycle Time
6
5
4
3
2 1 44 43 42 41 40
A13
A12
A11
A10
A9
GND
NC
A8
7
DQ12
DQ11
DQ10
DQ9
39
38
37
36
35
34
33
32
31
30
29
8
V
10%
CC
9
’27C/PC240-10
’27C/PC240-12
’27C/PC240-15
100 ns
120 ns
150 ns
10
11
12
13
14
15
16
17
DQ8
†
†
GND
D
D
16-Bit Output For Use in
Microprocessor-Based Systems
NC
DQ7
DQ6
DQ5
DQ4
A7
A6
A5
Very High Speed SNAP! Pulse
Programming
D
D
D
D
Power-Saving CMOS Technology
3-State Output Buffers
18 19 20 21 22 23 24 25 26 27 28
400-mV Minimum DC Noise Immunity With
Standard TTL Loads
PIN NOMENCLATURE
Latchup Immunity of 250 mA on All Input
and Output Lines
A0−A17
Address Inputs
DQ0−DQ15 Inputs (programming)/Outputs
E
G
GND
NC
Chip Enable
Output Enable
Ground
No Connection
5-V Supply
D
No Pullup Resistors Required
D
Low Power Dissipation (V
= 5.5 V)
CC
− Active . . . 275 mW Worst Case
− Standby . . . 0.55 mW Worst Case
(CMOS-Input Levels)
V
CC
‡
V
PP
13-V Power Supply
D
Temperature Range Options
†
‡
Pins 11 and 30 (J package) and pins 12 and 34
(FN package) must be connected externally to
ground.
Only in program mode
description
The TMS27C240 series are 262144 by 16-bit (4194304-bit), ultraviolet-light erasable, electrically
programmable read-only memories (EPROMs).
The TMS27PC240 series are 262144 by 16-bit (4194304-bit), one-time programmable (OTP) electrically
programmable read-only memories (PROMs).
These devices are fabricated using power-saving CMOS technology for high speed and simple interface with
MOS and bipolar circuits. All inputs (including program data inputs) can be driven by Series 74 TTL circuits
without the use of external pull-up resistors. Each output can drive one Series 74 TTL circuit without external
resistors.
The TMS27C240 EPROM is offered in a dual-in-line ceramic package (J suffix) designed for insertion in
mounting hole rows on 15,2-mm (600-mil) centers. The TMS27C240 is offered with two choices of temperature
ranges of 0°C to 70°C (JL suffix) and − 40°C to 85°C (JE suffix). See Table 1.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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Copyright 1997, Texas Instruments Incorporated
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1
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
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ꢀ ꢁ ꢂ ꢃ ꢄꢔ ꢅꢃ ꢆꢇ ꢃ ꢈ ꢃ ꢉ ꢆ ꢆ ꢊꢋ ꢉ ꢈ ꢌꢊꢍ ꢀ
ꢔ ꢑꢕꢖꢑ ꢒ ꢁꢁ ꢒ ꢊꢓ ꢐ ꢑꢐ ꢒꢗ ꢌꢕꢘ ꢓꢋ ꢁꢐ ꢁꢕ ꢑ ꢍꢐꢂ
SMLS240D− NOVEMBER 1990 − REVISED SEPTEMBER 1997
TMS27C240 J PACKAGE
(TOP VIEW)
V
V
CC
1
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
PP
E
A17
A16
A15
A14
A13
A12
A11
A10
A9
2
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
3
4
5
6
7
8
9
DQ8
10
11
12
13
14
15
16
17
18
19
20
†
†
GND
GND
A8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
G
A7
A6
A5
A4
A3
A2
A1
A0
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POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
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SMLS240D− NOVEMBER 1990 − REVISED SEPTEMBER 1997
description (continued)
The TMS27PC240 OTP PROM is offered in a 44-lead plastic leaded chip carrier package using 1,25-mm
(50-mil) lead spacing (FN suffix). The TMS27PC240 is offered with two choices of temperature ranges of 0°C
to 70°C (FNL suffix) and −40°C to 85°C (FNE suffix). See Table 1.
Table 1. Temperature Range Suffixes
SUFFIX FOR OPERATING FREE-
AIR TEMPERATURE RANGES
0°C TO 70°C
− 40°C TO 85°C
TMS27C240-XXX
TMS27PC240-XXX
JL
JE
FNL
FNE
These EPROMs and OTP PROMs operate from a single 5-V supply (in the read mode), and they are ideal for
use in microprocessor-based systems. One other (13 V) supply is needed for programming . All programming
signals are TTL level. For programming outside the system, existing EPROM programmers can be used.
operation
The eight modes of operation for the TMS27C240 and TMS27PC240 are listed in Table 2. The read mode
requires a single 5-V supply. All inputs are TTL level except for V during programming (13 V for SNAP! Pulse),
PP
and 12 V on A9 for the signature mode.
Table 2. Operation Modes
†
FUNCTION
E
G
V
PP
V
CC
A9
A0
I/O
DQ0−DQ7
DQ8−DQ15
Read
V
IL
V
IL
V
CC
V
CC
X
X
Output Disable
Standby
V
V
V
V
V
CC
V
CC
V
CC
V
CC
V
CC
X
X
X
X
X
X
X
X
X
X
Hi-Z
Hi-Z
IL
IH
CC
V
IH
X
CC
Programming
Verify
V
V
IH
V
V
V
Data In
Data Out
Hi-Z
IL
IH
IH
PP
PP
PP
V
V
V
IL
Program Inhibit
V
IH
Manufacturer’s
Code
‡
Signature Mode (Mfg)
V
V
V
V
V
V
IL
IL
IL
IL
CC
CC
CC
CC
H
IL
0097
Device Code
0030
‡
Signature Mode (Device)
V
V
V
V
V
H
V
IH
†
‡
X can be V or V
IL IH
H
.
V
= 12 V 0.5 V.
read/output disable
When the outputs of two or more TMS27C240s or TMS27PC240s are connected in parallel on the same bus,
the output of any particular device in the circuit can be read with no interference from the competing outputs
of the other devices. To read the output of a single device, a low-level signal is applied to the E and G pins. All
other devices in the circuit should have their outputs disabled by applying a high-level signal to one of these
pins.
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ꢀ ꢁ ꢂ ꢃ ꢄꢔ ꢅꢃ ꢆꢇ ꢃ ꢈ ꢃ ꢉ ꢆ ꢆ ꢊꢋ ꢉ ꢈ ꢌꢊꢍ ꢀ
ꢔ ꢑꢕꢖꢑ ꢒ ꢁꢁ ꢒ ꢊꢓ ꢐ ꢑꢐ ꢒꢗ ꢌꢕꢘ ꢓꢋ ꢁꢐ ꢁꢕ ꢑ ꢍꢐꢂ
SMLS240D− NOVEMBER 1990 − REVISED SEPTEMBER 1997
latchup immunity
Latchup immunity on the TMS27C240 and TMS27PC240 is a minimum of 250 mA on all inputs and outputs.
This feature provides latchup immunity beyond any potential transients at the P.C. board level when the devices
are interfaced to industry-standard TTL or MOS logic devices. Input-output layout approach controls latchup
without compromising performance or packing density.
power down
Active I
supply current can be reduced from 50 mA to 1 mA by applying a high TTL input on E and to
CC
100 µA by applying a high CMOS input on E. In this mode all outputs are in the high-impedance state.
erasure (TMS27C240)
Before programming, the TMS27C240 is erased by exposing the chip through the transparent lid to a high
intensity ultraviolet light (wavelength 2537 Å). The recommended minimum exposure dose (UV intensity ×
2
2
exposure time) is 15-W⋅s/cm . A 12-mW/cm , filterless UV lamp erases the device in 21 minutes. The lamp
should be located about 2.5 cm above the chip during erasure. After erasure, all bits are in the high state. It
should be noted that normal ambient light contains the correct wavelength for erasure. Therefore, when using
the TMS27C240, the window should be covered with an opaque label.
initializing (TMS27PC240)
The one-time programmable TMS27PC240 PROM is provided with all bits in the logic high state, then logic lows
are programmed into the desired locations. Logic lows programmed into an OTP PROM cannot be erased.
SNAP! Pulse programming
The TMS27C240 and TMS27PC240 are programmed by using the SNAP! Pulse programming algorithm. The
programming sequence is shown in the SNAP! Pulse programming flow chart, shown in Figure 1.
The initial setup is V = 13 V, V
is presented in parallel (eight bits) on pins DQ0 through DQ15. Once addresses and data are stable, the
= 6.5 V, E = V , and G = V . Once the initial location is selected, the data
IH IH
PP
CC
programming mode is achieved when E is pulsed low (V ) with a pulse duration of t
programmed only once before going to interactive mode.
. Every location is
IL
w(PGM)
In the interactive mode, the word is verified at V = 13 V, V
is not read, the programming is performed by pulling E low with a pulse duration of t
verification and programming is performed up to a maximum of 10 times. When the device is fully programmed,
= 6.5 V, E = V , and G = V . If the correct data
PP
CC
IH
IL
. This sequence of
w(PGM)
all bytes are verified with V
= V = 5 V 10%.
CC
PP
program inhibit
Programming can be inhibited by maintaining a high level input on the E and G pins.
program verify
Programmed bits can be verified with V = 13 V when G = V and E = V .
PP
IL
IH
4
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
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SMLS240D− NOVEMBER 1990 − REVISED SEPTEMBER 1997
signature mode
The signature mode provides access to a binary code identifying the manufacturer and type. This mode is
activated when A9 (pin 31 for the J package) is forced to 12 V. Two identifier bytes are accessed by toggling
A0. DQ0−DQ7 contain the valid codes. All other addresses must be held low. The signature code for these
devices is 9730. A0 low selects the manufacturer’s code 97 (Hex), and A0 high selects the device code 30
(Hex), as shown in Table 3.
Table 3. Signature Mode
PINS
†
IDENTIFIER
A0
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
HEX
97
MANUFACTURER CODE
DEVICE CODE
V
1
0
0
0
0
1
1
1
0
0
1
0
1
0
1
0
IL
V
IH
30
†
E = G = V , A9 = V , A1−A8 = V , A10−A17 = V , V
IL IL IL PP
= V , PGM = V or V
.
H
CC IH IL
5
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
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ꢀ ꢁ ꢂ ꢃ ꢄꢔ ꢅꢃ ꢆꢇ ꢃ ꢈ ꢃ ꢉ ꢆ ꢆ ꢊꢋ ꢉ ꢈ ꢌꢊꢍ ꢀ
ꢔ ꢑꢕꢖꢑ ꢒ ꢁꢁ ꢒ ꢊꢓ ꢐ ꢑꢐ ꢒꢗ ꢌꢕꢘ ꢓꢋ ꢁꢐ ꢁꢕ ꢑ ꢍꢐꢂ
SMLS240D− NOVEMBER 1990 − REVISED SEPTEMBER 1997
Start
Address = First Location
Program
Mode
V
CC
= 6.5 V, V
= 13 V
PP
Program One Pulse = t = 100 µs
Increment Address
w
No
Last
Address?
Yes
Address = First Location
X = 0
Program One Pulse = t = 100 µs
w
No
Fail
Increment
Address
Verify
One Byte
X = X + 1
X = 10?
Interactive
Mode
Pass
No
Last
Address?
Yes
Yes
Device Failed
V
CC
= V = 5 V 10%
PP
Compare
All Bytes
To Original
Data
Fail
Final
Verification
Pass
Device Passed
Figure 1. SNAP! Pulse Programming Flow Chart
6
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
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SMLS240D− NOVEMBER 1990 − REVISED SEPTEMBER 1997
†
logic symbol
EPROM 256K × 16
21
22
23
24
25
26
27
28
29
31
32
33
34
35
36
37
38
39
A0
A1
0
19
A ∇
A ∇
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
18
17
16
15
14
13
12
10
9
A2
A ∇
A ∇
A ∇
A ∇
A ∇
A ∇
A ∇
A ∇
A ∇
A ∇
A ∇
A ∇
A ∇
A ∇
A3
A4
A5
A6
A7
0
A
262 143
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
8
7
6
5
4
3
17
2
E
[PWR DWN]
&
20
G
EN
†
These symbols are in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers are for the J package.
7
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ꢀ ꢁ ꢂ ꢃ ꢄꢔ ꢅꢃ ꢆꢇ ꢃ ꢈ ꢃ ꢉ ꢆ ꢆ ꢊꢋ ꢉ ꢈ ꢌꢊꢍ ꢀ
ꢔ ꢑꢕꢖꢑ ꢒ ꢁꢁ ꢒ ꢊꢓ ꢐ ꢑꢐ ꢒꢗ ꢌꢕꢘ ꢓꢋ ꢁꢐ ꢁꢕ ꢑ ꢍꢐꢂ
SMLS240D− NOVEMBER 1990 − REVISED SEPTEMBER 1997
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, V
Supply voltage range, V
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.6 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.6 V to 13 V
CC
PP
Input voltage range (see Note 1): All inputs except A9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.6 V to V
+ 1 V
CC
A9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.6 V to 13.5 V
Output voltage range (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.6 V to V + 1 V
CC
Operating free-air temperature range (’27C240-_ _JL; ’27PC240-_ _ FNL) . . . . . . . . . . . . . . . . 0° C to 70° C
Operating free-air temperature range (’27C240-_ _JE, ’27PC240-_ _FNE) . . . . . . . . . . . . . . − 40° C to 85° C
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150° C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to GND.
recommended operating conditions
MIN
4.5
NOM
5
MAX
5.5
UNIT
Read mode (see Note 2)
V
V
V
V
Supply voltage
V
CC
PP
IH
SNAP! Pulse programming algorithm
6.25
6.5
6.75
Read mode
V
−0.6
V
+0.6
CC
13.25
CC
Supply voltage
V
V
SNAP! Pulse programming algorithm
12.75
2
13
TTL
V
+0.5
CC
High-level dc input voltage
CMOS
TTL
V
− 0.2
CC
− 0.5
V
+0.5
CC
0.8
Low-level dc input voltage
V
IL
CMOS
− 0.5
0.2
’27C240-_ _JL
’27PC240-_ _ FNL
T
Operating free-air temperature
Operating free-air temperature
0
70
°C
°C
A
’27PC240-_ _FNE
’27C240-_ _JE
T
A
− 40
85
NOTE 2:
V
must be applied before or at the same time as V
PP
and removed after or at the same time as V . The device must not be inserted
PP
CC
into or removed from the board when V
or V
CC
is applied.
PP
8
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ꢌꢊ
ꢔ
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ꢁ
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ꢐ
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ꢌ
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SMLS240D− NOVEMBER 1990 − REVISED SEPTEMBER 1997
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature
PARAMETER
TEST CONDITIONS
= − 400 µA
MIN
MAX
UNIT
I
I
I
I
2.4
OH
OH
OL
OL
V
V
High-level dc output voltage
V
OH
= − 20 µA
V
− 0.1
CC
= 2.1 mA
0.4
0.1
1
Low-level dc output voltage
V
OL
= 20 µA
I
I
I
I
Input current (leakage)
Output current (leakage)
V = 0 V to 5.5 V
µA
µA
µA
mA
mA
µA
I
I
V
V
V
V
V
V
= 0 V to V
CC
1
O
O
V
V
supply current
= V
CC
= 5.5 V
10
50
1
PP1
PP2
PP
PP
PP
CC
CC
supply current (during program pulse)
= 13 V
PP
= 5.5 V,
= 5.5 V,
= 5.5 V,
E = V
E = V
E = V
IH
I
VCC supply current (standby)
CC1
CC2
100
CC
,
IL
CC
I
V
CC
supply current (active)
t
= minimum cycle time,
outputs open
50
mA
cycle
capacitance over recommended ranges of supply voltage and operating free-air
†
temperature, f = 1 MHz
‡
PARAMETER
TEST CONDITIONS
V = 0 V
MIN TYP
MAX
8
UNIT
pF
C
C
Input capacitance
Output capacitance
4
8
i
I
V
O
= 0 V
12
pF
o
†
‡
Capacitance measurements are made on a sample basis only.
Typical values are at T = 25°C and nominal voltages.
A
switching characteristics over recommended ranges of operating conditions (see Notes 3
and 4)
’27C240-10
’27C240-12
’27C240-15
’27PC240-10 ’27PC240-12 ’27PC240-15
PARAMETER
TEST CONDITIONS
UNIT
MIN
MAX
100
100
50
MIN
MAX
120
120
50
MIN
MAX
150
150
50
t
t
t
Access time from address
ns
ns
ns
a(A)
Access time from chip enable
Output enable time from G
a(E)
C
= 100 pF,
L
1 Series 74
TTL load,
Input t ≤ 20 ns,
en(G)
Output disable time from G or E, whichever
t
0
0
50
0
0
50
0
0
50
ns
ns
dis
r
f
†
occurs first
Input t ≤ 20 ns
Output data valid time after change of
address, E, or G, whichever occurs first
t
v(A)
§
§
Value calculated from 0.5 V delta to measured level.
NOTES: 3. For all switching characteristics, the input pulse levels are 0.4 V to 2.4 V. Timing measurements are made at 2 V for logic high and
0.8 V for logic low (see Figure 2).
4. Common test conditions apply for t
except during programming.
dis
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ꢀ ꢁ ꢂ ꢃ ꢄꢔ ꢅꢃ ꢆꢇ ꢃ ꢈ ꢃ ꢉ ꢆ ꢆ ꢊꢋ ꢉ ꢈ ꢌꢊꢍ ꢀ
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ꢔ ꢑꢕꢖꢑ ꢒ ꢁꢁ ꢒ ꢊꢓ ꢐ ꢑꢐ ꢒꢗ ꢌꢕꢘ ꢓꢋ ꢁꢐ ꢁꢕ ꢑ ꢍꢐꢂ
SMLS240D− NOVEMBER 1990 − REVISED SEPTEMBER 1997
switching characteristics for programming: V
(see Note 3)
= 6.5 V and V = 13 V (SNAP! Pulse), T = 25°C
PP
CC
A
PARAMETER
MIN
MAX
UNIT
ns
t
t
Output disable time from G
Output enable time from G
0
100
150
dis(G)
ns
en(G)
NOTE 3: For all switching characteristics the input pulse levels are 0.4 V to 2.4 V. Timing measurements are made at 2 V for logic high and
0.8 V for logic low. (See Figure 2)
timing requirements for programming
MIN NOM
MAX
UNIT
µs
t
t
t
t
t
t
t
t
t
Pulse duration, program
Setup time, address
Setup time, E
SNAP! Pulse programming algorithm
95
2
100
105
w(PGM)
µs
su(A)
2
µs
su(E)
Setup time, G
2
µs
su(G)
su(D)
Setup time, data
2
µs
Setup time, V
Setup time, V
2
µs
su(VPP)
su(VCC)
h(A)
PP
2
µs
CC
Hold time, address
Hold time, data
0
µs
2
µs
h(D)
10
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SMLS240D− NOVEMBER 1990 − REVISED SEPTEMBER 1997
PARAMETER MEASUREMENT INFORMATION
2.08 V
R
= 800 Ω
L
Output
Under Test
C
= 100 pF
L
(see Note A)
2.4 V
2 V
2 V
0.8 V
0.8 V
0.40 V
NOTES: A.
C
includes probe and fixture capacitance.
L
B. The ac testing inputs are driven at 2.4 V for logic high and 0.4 V for logic low. Timing
measurements are made at 2 V for logic high and 0.8 V for logic low for both inputs
and outputs.
Figure 2. The ac Testing Output Load Circuit and Waveform
A0−A17
Address Valid
E
G
t
a(E)
t
t
dis
v(A)
en(G)
t
t
a(A)
Output
Valid
DQ0−DQ15
Hi-Z
Hi-Z
Figure 3. Read-Cycle Timing
11
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢃ ꢆ ꢇ ꢃ ꢈꢃ ꢉ ꢆ ꢆ ꢊꢋ ꢉ ꢈ ꢌꢊꢍ ꢀ ꢎꢏ ꢐ ꢑꢒꢂ ꢒꢊꢓ ꢐ
ꢀ ꢁ ꢂ ꢃ ꢄꢔ ꢅꢃ ꢆꢇ ꢃ ꢈ ꢃ ꢉ ꢆ ꢆ ꢊꢋ ꢉ ꢈ ꢌꢊꢍ ꢀ
ꢔ ꢑꢕꢖꢑ ꢒ ꢁꢁ ꢒ ꢊꢓ ꢐ ꢑꢐ ꢒꢗ ꢌꢕꢘ ꢓꢋ ꢁꢐ ꢁꢕ ꢑ ꢍꢐꢂ
SMLS240D− NOVEMBER 1990 − REVISED SEPTEMBER 1997
PARAMETER MEASUREMENT INFORMATION
Verify
Program
A0−A17
Address Stable
t
t
h(A)
su(A)
Data-Out
Stable
DQ0−DQ15
Data-In Stable
Hi-Z
t
en(G)
t
t
dis(G)
su(D)
V
PP
t
su(VPP)
V
CC
t
su(E)
t
h(D)
t
su(VCC)
E
t
su(G)
t
w(PGM)
G
†
13-V V
PP
and 6.5-V V for SNAP! Pulse programming
CC
Figure 4. Programming-Cycle Timing (SNAP! Pulse Programming)
12
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SMLS240D− NOVEMBER 1990 − REVISED SEPTEMBER 1997
FN (S-PQCC-J**)
PLASTIC J-LEADED CHIP CARRIER
20 PIN SHOWN
Seating Plane
0.004 (0,10)
0.180 (4,57) MAX
0.120 (3,05)
D
0.090 (2,29)
D1
0.020 (0,51) MIN
3
1
19
0.032 (0,81)
0.026 (0,66)
4
18
D2/E2
D2/E2
E
E1
8
14
0.021 (0,53)
0.013 (0,33)
0.007 (0,18)
0.050 (1,27)
9
13
M
0.008 (0,20) NOM
D/E
D1/E1
D2/E2
NO. OF
PINS
**
MIN
0.385 (9,78)
MAX
MIN
MAX
MIN
MAX
0.395 (10,03)
0.350 (8,89)
0.356 (9,04)
0.141 (3,58)
0.191 (4,85)
0.291 (7,39)
0.341 (8,66)
0.169 (4,29)
0.219 (5,56)
0.319 (8,10)
0.369 (9,37)
20
28
44
52
68
84
0.485 (12,32) 0.495 (12,57) 0.450 (11,43) 0.456 (11,58)
0.685 (17,40) 0.695 (17,65) 0.650 (16,51) 0.656 (16,66)
0.785 (19,94) 0.795 (20,19) 0.750 (19,05) 0.756 (19,20)
0.985 (25,02) 0.995 (25,27) 0.950 (24,13) 0.958 (24,33) 0.441 (11,20) 0.469 (11,91)
1.185 (30,10) 1.195 (30,35) 1.150 (29,21) 1.158 (29,41) 0.541 (13,74) 0.569 (14,45)
4040005/B 03/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-018
13
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ꢈ
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ꢀ ꢁ ꢂ ꢃ ꢄꢔ ꢅꢃ ꢆꢇ ꢃ ꢈ ꢃ ꢉ ꢆ ꢆ ꢊꢋ ꢉ ꢈ ꢌꢊꢍ ꢀ
ꢎ
ꢏ
ꢐ
ꢑ
ꢒ
ꢂ
ꢒ
ꢊ
ꢓ
ꢐ
ꢔ ꢑꢕꢖꢑ ꢒ ꢁꢁ ꢒ ꢊꢓ ꢐ ꢑꢐ ꢒꢗ ꢌꢕꢘ ꢓꢋ ꢁꢐ ꢁꢕ ꢑ ꢍꢐꢂ
SMLS240D− NOVEMBER 1990 − REVISED SEPTEMBER 1997
J (R-CDIP-T**)
CERAMIC SIDE-BRAZE DUAL-IN-LINE PACKAGE
24 PIN SHOWN
B
13
24
C
12
1
Lens Protrusion
0.010 (0,25) MAX
0.065 (1,65)
0.045 (1,14)
0.090 (2,29)
0.060 (1,53)
0.175 (4,45)
A
0.140 (3,56)
0.018 (0,46) MIN
Seating Plane
0°−ā10°
0.125 (3,18) MIN
0.022 (0,56)
0.014 (0,36)
0.100 (2,54)
0.012 (0,30)
0.008 (0,20)
PINS**
24
28
32
40
DIM
NARR
WIDE
NARR
WIDE
NARR
WIDE
NARR
WIDE
0.624(15,85) 0.624(15,85) 0.624(15,85) 0.624(15,85) 0.624(15,85) 0.624(15,85) 0.624(15,85) 0.624(15,85)
0.590(14,99) 0.590(14,99) 0.590(14,99) 0.590(14,99) 0.590(14,99) 0.590(14,99) 0.590(14,99) 0.590(14,99)
1.265(32,13) 1.265(32,13) 1.465(37,21) 1.465(37,21) 1.668(42,37) 1.668(42,37) 2.068(52,53) 2.068(52,53)
1.235(31,37) 1.235(31,37) 1.435(36,45) 1.435(36,45) 1.632(41,45) 1.632(41,45) 2.032(51,61) 2.032(51,61)
0.541(13,74) 0.598(15,19) 0.541(13,74) 0.598(15,19) 0.541(13,74) 0.598(15,19) 0.541(13,74) 0.598(15,19)
0.514(13,06) 0.571(14,50) 0.514(13,06) 0.571(14,50) 0.514(13,06) 0.571(14,50) 0.514(13,06) 0.571(14,50)
MAX
MIN
MAX
MIN
MAX
MIN
A
B
C
4040084/B 04/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a ceramic lid using glass frit.
D. Index point is provided on cap for terminal identification only on press ceramic glass frit seal only.
14
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
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UVPROM, 32KX8, 100ns, CMOS, CDIP28, 0.600 INCH, WINDOWED, CERAMIC, DIP-28
ROCHESTER
TMS27C256-100JL4
UVPROM, 32KX8, 100ns, CMOS, CDIP28, 0.600 INCH, WINDOWED, CERAMIC, DIP-28
ROCHESTER
TMS27C256-10JL
UVPROM, 32KX8, 100ns, CMOS, CDIP28, 0.600 INCH, SIDE BRAZED, CERAMIC, DIP-28
ROCHESTER
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