TMS320C28344ZEP [TI]
TMS320C2834x Delfino Microcontrollers;型号: | TMS320C28344ZEP |
厂家: | TEXAS INSTRUMENTS |
描述: | TMS320C2834x Delfino Microcontrollers 微控制器 |
文件: | 总170页 (文件大小:4265K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
TMS320C28346, TMS320C28346-Q1, TMS320C28345, TMS320C28344
TMS320C28343, TMS320C28343-Q1,TMS320C28342,TMS320C28341
SPRS516F – MARCH 2009 – REVISED FEBRUARY 2021
TMS320C2834x Delfino Microcontrollers
– Six 32-Bit Enhanced Capture (eCAP) Modules
1 Features
•
Configurable as 3 Capture Inputs or
3 Auxiliary Pulse Width Modulator Outputs
Single-Shot Capture of up to Four Event
Timestamps
•
High-Performance Static CMOS Technology
– Up to 300 MHz (3.33-ns Cycle Time)
– 1.1-V/1.2-V Core, 3.3-V I/O, 1.8-V PLL/
Oscillator Design
•
– Three 32-Bit Quadrature Encoder Pulse (QEP)
Modules
– Six 32-Bit Timers and Nine 16-Bit Timers
Three 32-Bit CPU Timers
Serial Port Peripherals
– Up to 2 CAN Modules
– Up to 3 SCI (UART) Modules
– Up to 2 McBSP Modules (Configurable as SPI)
– Up to 2 SPI Modules
– One Inter-Integrated Circuit (I2C) Bus
External ADC Interface
Up to 88 Individually Programmable, Multiplexed
GPIO Pins With Input Filtering
Advanced Emulation Features
– Analysis and Breakpoint Functions
– Real-Time Debug Using Hardware
Package Options:
– 256-Ball Plastic Ball Grid Array (BGA) (ZFE)
– 179-Ball MicroStar BGA™ (ZHH)
Temperature Options:
•
High-Performance 32-Bit CPU (TMS320C28x)
– IEEE 754 Single-Precision Floating-Point Unit
(FPU)
•
•
– 16 × 16 and 32 × 32 MAC Operations
– 16 × 16 Dual MAC
– Harvard Bus Architecture
– Fast Interrupt Response and Processing
– Code-Efficient (in C/C++ and Assembly)
Six-Channel DMA Controller (for McBSP, XINTF,
and SARAM)
16-Bit or 32-Bit External Interface (XINTF)
– More Than 2M × 16 Address Reach
On-Chip Memory
•
•
•
•
•
•
•
•
– Up to 258K × 16 SARAM
– 8K × 16 Boot ROM
•
•
Clock and System Control
– On-Chip Oscillator
– Watchdog Timer Module
Peripheral Interrupt Expansion (PIE) Block That
Supports All 64 Peripheral Interrupts
Endianness: Little Endian
Enhanced Control Peripherals
– Eighteen Enhanced Pulse Width Modulator
(ePWM) Outputs
– T: –40°C to 105°C (ZFE, ZHH)
– S: –40°C to 125°C (ZFE)
– Q: –40°C to 125°C (ZFE)
•
•
(AEC Q100 Qualification for Automotive
Applications)
•
Dedicated 16-Bit Time-Based Counter With
Period and Frequency Control
2 Applications
•
Single-Edge, Dual-Edge Symmetric, or
Dual-Edge Asymmetric Outputs
Dead-Band Generation
PWM Chopping by High-Frequency Carrier
Trip Zone Input
•
•
•
•
•
•
Industrial AC Inverter Drives
Industrial Servo Amplifiers and Controllers
Computer Numerical Control (CNC) Machining
Uninterruptible and Server Power Supplies
Telecom Equipment Power
•
•
•
•
Up to 9 HRPWM Outputs With 55-ps MEP
Resolution at VDD = 1.1 V (65 ps at 1.2 V)
Solar Inverters
3 Description
The TMS320C2834x (C2834x) Delfino™ microcontroller unit (MCU) devices build on TI's existing F2833x high-
performance floating-point microcontrollers. The C2834x delivers up to 300 MHz of floating-point performance,
and has up to 516KB of on-chip RAM. Designed for real-time control applications, the C2834x is based on the
C28x core, making it code-compatible with all C28x microcontrollers. The on-chip peripherals and low-latency
core make the C2834x an excellent solution for performance-hungry real-time control applications.
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TMS320C28346, TMS320C28346-Q1, TMS320C28345, TMS320C28344
TMS320C28343, TMS320C28343-Q1, TMS320C28342, TMS320C28341
SPRS516F – MARCH 2009 – REVISED FEBRUARY 2021
www.ti.com
The TMS320C28346, TMS320C28345, TMS320C28344, TMS320C28343, TMS320C28342, and
TMS320C28341 devices, members of the Delfino™ MCU generation, are highly integrated, high-performance
solutions for demanding control applications.
Throughout this document, the devices are abbreviated as C28346, C28345, C28344, C28343, C28342, and
C28341, respectively. Device Comparison provides a summary of features for each device.
Device Information (1)
PART NUMBER
TMS320C28346ZFE
PACKAGE
BODY SIZE
BGA (256)
17.0 mm × 17.0 mm
17.0 mm × 17.0 mm
17.0 mm × 17.0 mm
17.0 mm × 17.0 mm
17.0 mm × 17.0 mm
17.0 mm × 17.0 mm
17.0 mm × 17.0 mm
17.0 mm × 17.0 mm
17.0 mm × 17.0 mm
17.0 mm × 17.0 mm
17.0 mm × 17.0 mm
17.0 mm × 17.0 mm
12.0 mm × 12.0 mm
12.0 mm × 12.0 mm
12.0 mm × 12.0 mm
TMS320C28345ZFE
TMS320C28344ZFE
TMS320C28343ZFE
TMS320C28342ZFE
TMS320C28341ZFE
TMS320C28346ZEP
TMS320C28345ZEP
TMS320C28344ZEP
TMS320C28343ZEP
TMS320C28342ZEP
TMS320C28341ZEP
TMS320C28345ZHH
TMS320C28343ZHH
TMS320C28341ZHH
BGA (256)
BGA (256)
BGA (256)
BGA (256)
BGA (256)
BGA (256)
BGA (256)
BGA (256)
BGA (256)
BGA (256)
BGA (256)
BGA MicroStar (179)
BGA MicroStar (179)
BGA MicroStar (179)
(1) For more information on these devices, see Mechanical, Packaging, and Orderable Information.
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Product Folder Links: TMS320C28346 TMS320C28346-Q1 TMS320C28345 TMS320C28344 TMS320C28343
TMS320C28343-Q1 TMS320C28342 TMS320C28341
TMS320C28346, TMS320C28346-Q1, TMS320C28345, TMS320C28344
TMS320C28343, TMS320C28343-Q1, TMS320C28342, TMS320C28341
www.ti.com
SPRS516F – MARCH 2009 – REVISED FEBRUARY 2021
3.1 Functional Block Diagram
L0 SARAM 8K x 16
(0-Wait)
M0 SARAM 1K x 16
(0-Wait)
H0 SARAM 32K x 16
(1 Wait, Prefetch)
L1 SARAM 8K x 16
(0-Wait)
M1 SARAM 1K x 16
(0-Wait)
H1 SARAM 32K x 16
(1 Wait, Prefetch)
L2 SARAM 8K x 16
(0-Wait)
H2 SARAM 32K x 16
(1 Wait, Prefetch)
L3 SARAM 8K x 16
(0-Wait)
H3 SARAM 32K x 16
(1 Wait, Prefetch)
L4 SARAM 8K x 16
(0-Wait)
H4 SARAM 32K x 16
(1 Wait, Prefetch)
L5 SARAM 8K x 16
(0-Wait)
Boot ROM
8K x 16
H5 SARAM 32K x 16
(1 Wait, Prefetch)
L6 SARAM 8K x 16
(1-Wait)
L7 SARAM 8K x 16
(1-Wait)
Memory Bus
XD31:0
FPU
TCK
TDI
XHOLDA
XHOLD
XREADY
XR/W
TMS
TDO
32-Bit CPU
(300 MHz @ 1.2 V
200 MHz @ 1.1 V)
GPIO
MUX
88 GPIOs
TRST
EMU0
EMU1
XZCS0
XZCS7
XZCS6
XWE0
XCLKIN
X1
CPU Timer 0
CPU Timer 1
CPU Timer 2
XA19:1
OSC,
PLL,
LPM,
WD
DMA
6 Ch
X2
XCLKOUT
XRS
XRD
PIE
(Interrupts)
XWE1
88 GPIOs
8 External Interrupts
GPIO
MUX
Memory Bus
EXTADCCLK
EXTSOC
ADC
SoC
DMA Bus
32-Bit Peripheral Bus
(DMA accessible)
32-Bit Peripheral Bus
16-Bit Peripheral Bus
FIFO
(16 Levels)
FIFO
(16 Levels)
FIFO
(16 Levels)
ePWM-1/../9
CAN-A/B
(32-mbox)
eQEP-1/2/3
McBSP-A/B
eCAP-1/../6
SCI-A/B/C
SPI-A/D
I2C
HRPWM-1/../9
GPIO MUX
88 GPIOs
Figure 3-1. Functional Block Diagram
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Product Folder Links: TMS320C28346 TMS320C28346-Q1 TMS320C28345 TMS320C28344 TMS320C28343
TMS320C28343-Q1 TMS320C28342 TMS320C28341
TMS320C28346, TMS320C28346-Q1, TMS320C28345, TMS320C28344
TMS320C28343, TMS320C28343-Q1, TMS320C28342, TMS320C28341
SPRS516F – MARCH 2009 – REVISED FEBRUARY 2021
www.ti.com
Table of Contents
1 Features............................................................................1
2 Applications.....................................................................1
3 Description.......................................................................1
3.1 Functional Block Diagram...........................................3
4 Revision History.............................................................. 5
5 Device Comparison.........................................................6
5.1 Related Products........................................................ 6
6 Terminal Configuration and Functions..........................8
6.1 Pin Diagrams.............................................................. 8
6.2 Signal Descriptions................................................... 16
7 Specifications................................................................ 29
7.1 Absolute Maximum Ratings (1) (2) .............................29
7.2 ESD Ratings – Automotive....................................... 29
7.3 ESD Ratings – Commercial...................................... 29
7.4 Recommended Operating Conditions.......................30
7.5 Power Consumption Summary................................. 31
7.6 Electrical Characteristics...........................................34
7.7 Thermal Resistance Characteristics......................... 35
7.8 Thermal Design Considerations................................36
7.9 Timing and Switching Characteristics....................... 37
8 Detailed Description......................................................86
8.1 Brief Descriptions......................................................86
8.2 Peripherals................................................................92
8.3 Memory Maps......................................................... 130
8.4 Register Map...........................................................136
8.5 Interrupts.................................................................139
8.6 System Control....................................................... 144
8.7 Low-Power Modes Block........................................ 151
9 Applications, Implementation, and Layout............... 152
9.1 TI Design or Reference Design...............................152
10 Device and Documentation Support........................153
10.1 Getting Started......................................................153
10.2 Device and Development Support Tool
Nomenclature............................................................153
10.3 Tools and Software............................................... 155
10.4 Documentation Support........................................ 156
10.5 Support Resources............................................... 158
10.6 Trademarks...........................................................158
10.7 Electrostatic Discharge Caution............................158
10.8 Glossary................................................................159
11 Mechanical, Packaging, and Orderable
Information.................................................................. 160
11.1 Packaging Information.......................................... 160
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Product Folder Links: TMS320C28346 TMS320C28346-Q1 TMS320C28345 TMS320C28344 TMS320C28343
TMS320C28343-Q1 TMS320C28342 TMS320C28341
TMS320C28346, TMS320C28346-Q1, TMS320C28345, TMS320C28344
TMS320C28343, TMS320C28343-Q1, TMS320C28342, TMS320C28341
www.ti.com
SPRS516F – MARCH 2009 – REVISED FEBRUARY 2021
4 Revision History
Changes from August 22, 2018 to February 1, 2021 (from Revision E (August 2018) to Revision
F (February 2021))
Page
•
•
•
Added Q1 Part Numbers................................................................................................................................ 0
Table 5-1: Added Q1 Part Numbers....................................................................................................................6
Section 7.9.4.5.1.1 (SPI Master Mode External Timing (Clock Phase = 0)): Updated MIN value (for both BRR
EVEN and BRR ODD) for Parameter 23, td(SPC)M............................................................................................ 56
Section 7.9.4.5.1.2 (SPI Master Mode External Timing (Clock Phase = 1)): Updated MIN value (for both BRR
EVEN and BRR ODD) for Parameter 23, td(SPC)M............................................................................................ 58
Figure 10-1: Added GPN information............................................................................................................. 153
•
•
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Product Folder Links: TMS320C28346 TMS320C28346-Q1 TMS320C28345 TMS320C28344 TMS320C28343
TMS320C28343-Q1 TMS320C28342 TMS320C28341
TMS320C28346, TMS320C28346-Q1, TMS320C28345, TMS320C28344
TMS320C28343, TMS320C28343-Q1, TMS320C28342, TMS320C28341
SPRS516F – MARCH 2009 – REVISED FEBRUARY 2021
www.ti.com
5 Device Comparison
Table 5-1. Device Comparison
C28346
C28343
C28343-Q1
(200 MHz)
C28345
(200 MHz)
C28344
(300 MHz)
C28342
(300 MHz)
C28341
(200 MHz)
FEATURE
TYPE(1) C28346-Q1
(300 MHz)
256-ball ZFE 256-ball ZFE 179-ball ZHH 256-ball ZFE 256-ball ZFE 179-ball ZHH 256-ball ZFE 256-ball ZFE 179-ball ZHH
Package type
–
BGA(2)
3.33 ns
Yes
BGA(2)
BGA
BGA(2)
3.33 ns
Yes
BGA(2)
BGA
BGA(2)
3.33 ns
Yes
BGA(2)
BGA
Instruction cycle
–
–
5 ns
Yes
5 ns
Yes
5 ns
Yes
Floating-point unit
Single-access RAM (SARAM)
(16-bit word)
–
258K
258K
130K
130K
98K
98K
Code security for on-chip SARAM
blocks
–
–
1
No
Yes
Yes
No
Yes
Yes
No
Yes
Yes
No
Yes
Yes
No
Yes
Yes
No
Yes
Yes
Boot ROM (8K ×16)
16-/32-bit External Interface
(XINTF)
6-channel Direct Memory Access
(DMA)
0
0
Yes
Yes
Yes
Yes
Yes
Yes
ePWM1/2/3/
4/5/6/7/8/9
ePWM1/2/3/
4/5/6/7/8/9
ePWM1/2/3/
4/5/6/7/8/9
ePWM1/2/3/
4/5/6/7/8/9
ePWM1/2/3/
4/5/6
ePWM1/2/3/
4/5/6
PWM channels
ePWM1A/2A/
3A/4A/5A/6A/
7A/8A/9A
ePWM1A/2A/
3A/4A/5A/6A/
7A/8A/9A
ePWM1A/2A/
3A/4A/5A/6A/
7A/8A/9A
ePWM1A/2A/
3A/4A/5A/6A/
7A/8A/9A
ePWM1A/2A/
3A/4A/5A/6A
ePWM1A/2A/
3A/4A/5A/6A
HRPWM channels
0
32-bit capture inputs or auxiliary
PWM outputs
0
0
6
3
6
3
6
3
6
3
4
2
4
2
32-bit QEP channels (four inputs/
channel)
Watchdog timer
–
–
–
Yes
Yes
3
Yes
Yes
3
Yes
Yes
3
Yes
Yes
3
Yes
Yes
3
Yes
Yes
3
External ADC interface
32-bit CPU timers
Multichannel Buffered Serial Port
(McBSP)/SPI
1
0
0
2
2
3
2
2
3
2
2
3
2
2
3
1
2
3
1
2
3
Serial Peripheral Interface (SPI)
Serial Communications Interface
(SCI)
Enhanced Controller Area
Network (eCAN)
0
0
–
–
–
2
1
2
1
2
1
2
1
2
1
2
1
Inter-Integrated Circuit (I2C)
General-Purpose Input/Output
(GPIO) pins (shared)
88
8
88
8
88
8
88
8
88
8
88
8
External interrupts
T: –40°C to
105°C
ZFE
ZFE
ZHH
–
ZFE
ZFE
ZHH
–
ZFE
ZFE
ZHH
–
S: –40°C to
Temperature 125°C
–
–
ZFE
ZFE
ZFE
ZFE
ZFE
ZFE
ZFE
ZFE
ZFE
ZFE
ZFE
ZFE
options
Q: –40°C to
125°C
(AEC Q100
qualification)
–
–
–
(1) A type change represents a major functional feature difference in a peripheral module. Within a peripheral type, there may be minor
differences between devices that do not affect the basic functionality of the module. These device-specific differences are listed in the
C2000 Real-Time Control Peripherals Reference Guide and in the peripheral reference guides.
(2) TMX samples will come with the ZEP designator. The designator will change to ZFE after TMS.
5.1 Related Products
For information about other devices in the Delfino family of products, see the following links:
Original Delfino™ series:
TMS320F2833x Delfino™ Microcontrollers
The F2833x series is the original Delfino MCU. It is the first C2000™ MCU that is offered with a floating-point unit
(FPU). It has the first-generation ePWM timers that are used throughout the rest of the Delfino and Piccolo™
families. The 12.5-MSPS, 12-bit ADC is still class-leading for an integrated analog-to-digital converter. The
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Product Folder Links: TMS320C28346 TMS320C28346-Q1 TMS320C28345 TMS320C28344 TMS320C28343
TMS320C28343-Q1 TMS320C28342 TMS320C28341
TMS320C28346, TMS320C28346-Q1, TMS320C28345, TMS320C28344
TMS320C28343, TMS320C28343-Q1, TMS320C28342, TMS320C28341
www.ti.com
SPRS516F – MARCH 2009 – REVISED FEBRUARY 2021
F2833x has a 150-MHz CPU and up to 512KB of on-chip Flash. It is available in a 176-pin QFP or 179-ball BGA
package.
TMS320C2834x Delfino™ Microcontrollers
The C2834x series removes the on-chip Flash memory and integrated ADC to enable the fastest available clock
speeds of up to 300 MHz. It is available in a 179-ball BGA or 256-ball BGA package.
Newest Delfino™ series:
TMS320F2837xD Delfino™ Microcontrollers
The F2837xD series sets a new standard for performance with dual subsystems. Each subsystem consists of a
C28x CPU and a parallel control law accelerator (CLA), each running at 200 MHz. Enhancing performance are
TMU and VCU accelerators. New capabilities include multiple 16-bit/12-bit mode ADCs, DAC, Sigma-Delta
filters, USB, configurable logic block (CLB), on-chip oscillators, and enhanced versions of all peripherals. The
F2837xD is available with up to 1MB of Flash. It is available in a 176-pin QFP or 337-pin BGA package.
TMS320F2837xS Delfino™ Microcontrollers
The F2837xS series is a pin-to-pin compatible version of F2837xD but with only one C28x-CPU-and-CLA
subsystem enabled. It is also available in a 100-pin QFP to enable compatibility with the Piccolo™
TMS320F2807x series.
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TMS320C28343-Q1 TMS320C28342 TMS320C28341
TMS320C28346, TMS320C28346-Q1, TMS320C28345, TMS320C28344
TMS320C28343, TMS320C28343-Q1, TMS320C28342, TMS320C28341
SPRS516F – MARCH 2009 – REVISED FEBRUARY 2021
www.ti.com
6 Terminal Configuration and Functions
6.1 Pin Diagrams
The 179-ball ZHH ball grid array (BGA) terminal assignments are shown in Figure 6-1 through Figure 6-4. The
256-ball ZFE plastic BGA terminal assignments are shown in Figure 6-5 through Figure 6-8. Table 6-1 describes
the function(s) of each pin.
1
2
3
4
5
6
7
GPIO19/
SPISTEA/
SCIRXDB/
CANTXA
GPIO23/
EQEP1I/
MFSXA/
SCIRXDB
GPIO24/
ECAP1/
EQEP2A/
MDXB
GPIO32/
SDAA/
VDD
P
N
EXTSOC2B
EXTSOC3B
P
N
EPWMSYNCI/
ADCSOCAO
GPIO22/
EQEP1S/
MCLKXA/
SCITXDB
GPIO33/
SCLA/
VDD
EXTSOC1A
EXTSOC3A EXTADCCLK
TDO
TRST
VSS
EPWMSYNCO/
ADCSOCBO
GPIO21/
EQEP1B/
MDRA/
GPIO25/
ECAP2/
EQEP2B/
MDRB
GPIO27/
ECAP4/
EQEP2S/
MFSXB
VDD
M
EXTSOC2A EXTSOC1B
M
CANRXB
GPIO18/
SPICLKA/
SCITXDB/
CANRXA
GPIO20/
EQEP1A/
MDXA/
VDDIO
VSS
VSS
L
TDI
L
CANTXB
GPIO15/
TZ4/XHOLDA/
SCIRXDB/
MFSXB
GPIO16/
SPISIMOA/
CANTXB/
TZ5
GPIO26/
ECAP3/
EQEP2I/
MCLKXB
VSS
VDD
VDDIO
VDDIO
K
K
6
7
GPIO17/
SPISOMIA/
CANRXB/
TZ6
VDDIO
VSS
VDD
VDD
J
J
GPIO12/
TZ1/
GPIO11/
EPWM6B/
SCIRXDB/
ECAP4
GPIO13/
TZ2/
GPIO14/
TZ3/XHOLD/
SCITXDB/
MCLKXB
VSS
H
H
CANTXB/
MDXB
CANRXB/
MDRB
1
2
3
4
5
Figure 6-1. C2834x 179-Ball ZHH MicroStar BGA Upper-Left Quadrant (Bottom VIew)
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TMS320C28343-Q1 TMS320C28342 TMS320C28341
TMS320C28346, TMS320C28346-Q1, TMS320C28345, TMS320C28344
TMS320C28343, TMS320C28343-Q1, TMS320C28342, TMS320C28341
www.ti.com
SPRS516F – MARCH 2009 – REVISED FEBRUARY 2021
8
9
10
11
12
13
14
GPIO54/
SPISIMOA/
XD25/
GPIO56/
SPICLKA/
XD23/
GPIO49/
ECAP6/
XD30/
GPIO58/
MCLKRA/
XD21/
VDDIO
P
TCK
P
XRS
EQEP3A
EQEP3S
SPISOMID
EPWM7A
GPIO55/
SPISOMIA/
XD24/
GPIO57/
SPISTEA/
XD22/
GPIO50/
EQEP1A/
XD29/
GPIO51/
EQEP1B/
XD28/
VDD
N
EMU0
N
XRSIO
TMS
VSS
EQEP3B
EQEP3I
SPICLKD
SPISTED
GPIO48/
ECAP5/
XD31/
GPIO59/
MFSRA/
XD20/
GPIO60/
MCLKRB/
XD19/
GPIO52/
EQEP1S/
XD27
VSS
VSS
M
M
SPISIMOD
EPWM7B
EPWM8A
GPIO61/
MFSRB/
XD18/
GPIO62/
SCIRXDC/
XD17/
GPIO53/
EQEP1I/
XD26
VDD
VDDIO
L
EMU1
L
EPWM8B
EPWM9A
GPIO63/
SCITXDC/
XD16/
GPIO64/
XD15
GPIO65/
XD14
VDDIO
VDD
VSS
VDD
K
K
EPWM9B
8
9
GPIO66/
XD13
GPIO67/
XD12
GPIO68/
XD11
VDDIO
VSS
J
J
GPIO70/
XD9
GPIO69/
XD10
VDD
VSS
VDD
H
H
10
11
12
13
14
Figure 6-2. C2834x 179-Ball ZHH MicroStar BGA Upper-Right Quadrant (Bottom View)
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Product Folder Links: TMS320C28346 TMS320C28346-Q1 TMS320C28345 TMS320C28344 TMS320C28343
TMS320C28343-Q1 TMS320C28342 TMS320C28341
TMS320C28346, TMS320C28346-Q1, TMS320C28345, TMS320C28344
TMS320C28343, TMS320C28343-Q1, TMS320C28342, TMS320C28341
SPRS516F – MARCH 2009 – REVISED FEBRUARY 2021
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1
2
3
4
5
GPIO9/
EPWM5B/
SCITXDB/
ECAP3
GPIO8/
EPWM5A/
CANTXB/
GPIO10/
EPWM6A/
CANRXB/
VDD
VSS
G
G
ADCSOCBO
ADCSOCAO
GPIO7/
EPWM4B/
MCLKRA/
ECAP2
GPIO6/
EPWM4A/
GPIO2/
VDDIO
VSS
F
E
F
EPWMSYNCI/
EPWMSYNCO
EPWM2A
6
7
GPIO5/
EPWM3B/
MFSRA/
ECAP1
GPIO3/
EPWM2B/
ECAP5/
GPIO4/
GPIO80/
XA8
GPIO46/
XA6
VDD
VDD
E
EPWM3A
MCLKRB
GPIO85/
XA13
GPIO84/
XA12
GPIO47/
XA7
VDD
VSS
VDDIO
VDDIO
VDD18
VDD
D
C
D
GPIO1/
EPWM1B/
ECAP6/
MFSRB
GPIO30/
CANRXA/
XA18
GPIO29/
SCITXDA/
XA19
GPIO81/
XA9
VDD
VDD
C
GPIO31/
CANTXA/
XA17
VDDIO
VDDIO
GPIO0/
GPIO87/
XA15
GPIO83/
XA11
B
A
B
A
EPWM1A
GPIO39/
XA16
GPIO86/
XA14
GPIO82/
XA10
VSS
VSS
VSS
1
2
3
4
5
6
7
Figure 6-3. C2834x 179-Ball ZHH MicroStar BGA Lower-Left Quadrant (Bottom View)
Copyright © 2021 Texas Instruments Incorporated
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TMS320C28346, TMS320C28346-Q1, TMS320C28345, TMS320C28344
TMS320C28343, TMS320C28343-Q1, TMS320C28342, TMS320C28341
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SPRS516F – MARCH 2009 – REVISED FEBRUARY 2021
10
11
12
13
14
GPIO71/
XD8
GPIO72/
XD7
G
G
VDD
VSS
VSS
GPIO78/
XD1
GPIO75/
XD4
GPIO74/
XD5
GPIO73/
XD6
VDDIO
F
F
E
8
9
GPIO40/
XA0
GPIO77/
XD2
GPIO76/
XD3
E
VDD18
VSS
VDD
VSS
GPIO37/
ECAP2/
XZCS7
GPIO41/
XA1
D
D
VSS
VDD
VSS
VDDIO
XCLKIN
GPIO38/
XWE0
GPIO79/
XD0
VDDIO
VDD
VDD
X1
XWE1
C
C
GPIO35/
SCITXDA/
XR/W
GPIO36/
SCIRXDA/
XZCS0
GPIO45/
XA5
GPIO42/
XA2
VSSK
XCLKOUT
VSS
B
A
B
A
GPIO28/
SCIRXDA/
XZCS6
GPIO34/
ECAP1
GPIO44/
XA4
GPIO43/
XA3
X2
8
VDDIO
XRD
14
XREADY
9
10
11
12
13
Figure 6-4. C2834x 179-Ball ZHH MicroStar BGA Lower-Right Quadrant (Bottom View)
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TMS320C28343, TMS320C28343-Q1, TMS320C28342, TMS320C28341
SPRS516F – MARCH 2009 – REVISED FEBRUARY 2021
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1
2
3
4
5
6
7
8
GPIO19/
SPISTEA/
SCIRXDB/
CANTXA
GPIO21/
EQEP1B/
MDRA/
GPIO24/
ECAP1/
EQEP2A/
MDXB
GPIO27/
ECAP4/
EQEP2S/
MFSXB
T
TDI
VSS
VSS
VDDIO
CANRXB
GPIO32/
SDAA/
GPIO20/
EQEP1A/
MDXA/
GPIO22/
EQEP1S/
GPIO25/
ECAP2/
VSS
VSS
EXTADCCLK
R
P
TRST
TDO
EPWMSYNCI/
ADCSOCAO
MCLKXA/ EQEP2B/
CANTXB
SCITXDB
MDRB
GPIO23/
EQEP1I/
MFSXA/
GPIO26/
ECAP3/
EQEP2I/
GPIO33/
SCLA/
VDD
VSS
VSS
EXTSOC3B
EPWMSYNCO/
ADCSOCBO
SCIRXDB MCLKXB
VSS
VDDIO
VDDIO
VDD
VSS
VSS
VDD
VSS
VSS
VSS
VDDIO
N
M
EXTSOC2A EXTSOC2B EXTSOC3A
GPIO18/
SPICLKA/
EXTSOC1A EXTSOC1B
SCITXDB/
VDDIO
VDDIO
VSS
VSS
VDD
VSS
VSS
VSS
CANRXA
GPIO16/
GPIO17/
SPISIMOA/
SPISOMIA/
VDD
VDD
VDD
VDD
L
CANTXB/
CANRXB/
TZ5
TZ6
GPIO15/
TZ4/XHOLDA/
K
VSS
VDD
VSS
SCIRXDB/
MFSXB
GPIO13/
TZ2/
GPIO14/
TZ3/XHOLD/
SCITXDB/
MCLKXB
VDDIO
VDDIO
VSS
J
CANRXB/
MDRB
Figure 6-5. C2834x 256-Ball ZFE Plastic BGA Upper-Left Quadrant (Bottom View)
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TMS320C28346, TMS320C28346-Q1, TMS320C28345, TMS320C28344
TMS320C28343, TMS320C28343-Q1, TMS320C28342, TMS320C28341
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SPRS516F – MARCH 2009 – REVISED FEBRUARY 2021
9
10
11
12
13
14
15
16
GPIO50/
EQEP1A/
XD29/
GPIO53/
EQEP1I/
XD26
VDDIO
VSS
VSS
TCK
T
XRSIO
XRS
SPICLKD
GPIO54/
GPIO56/
GPIO48/
ECAP5/
XD31/
GPIO51/
EQEP1B/
XD28/
SPISIMOA/ SPICLKA/
VDDIO
VSS
VSS
EMU1
EMU0
VSS
R
P
N
M
L
XD25/
XD23/
EQEP3A
EQEP3S
SPISIMOD SPISTED
GPIO55/
SPISOMIA/
XD24/
GPIO57/
SPISTEA/
XD22/
GPIO49/
GPIO52/
ECAP6/
EQEP1S/
VSS
VDD
TMS
VSS
VDD
VSS
XD30/
XD27
EQEP3B
EQEP3I
SPISOMID
GPIO59/
MFSRA/
XD20/
GPIO58/
MCLKRA/
XD21/
VSS
VDDIO
VDDIO
VSS
VSS
VDDIO
VDDIO
EPWM7B
EPWM7A
GPIO62/
SCIRXDC/
XD17/
GPIO61/
MFSRB/
XD18/
GPIO60/
MCLKRB/
XD19/
VDD
VDD
VSS
EPWM9A
EPWM8B
EPWM8A
GPIO63/
SCITXDC/
XD16/
GPIO65/
XD14
GPIO64/
XD15
VSS
VSS
VDD
VDD
VDD
EPWM9B
GPIO67/
XD12
GPIO66/
XD13
VSS
VSS
VSS
VSS
K
GPIO69/
XD10
GPIO68/
XD11
VSS
VSS
VSS
VDDIO
VDDIO
J
Figure 6-6. C2834x 256-Ball ZFE Plastic BGA Upper-Right Quadrant (Bottom View)
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TMS320C28346, TMS320C28346-Q1, TMS320C28345, TMS320C28344
TMS320C28343, TMS320C28343-Q1, TMS320C28342, TMS320C28341
SPRS516F – MARCH 2009 – REVISED FEBRUARY 2021
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GPIO10/
EPWM6A/ EPWM6B/
CANRXB/ SCIRXDB/ CANTXB/
GPIO11/
GPIO12/
TZ1/
VSS
VDD
VSS
VSS
VSS
VSS
VDD
VSS
VSS
H
G
ADCSOCBO ECAP4
MDXB
GPIO7/
EPWM4B/
MCLKRA/
ECAP2
GPIO8/
EPWM5A/
CANTXB/
GPIO9/
EPWM5B/
SCITXDB/
ECAP3
VSS
VDD
VSS
VSS
ADCSOCAO
GPIO5/
EPWM3B/
MFSRA/
ECAP1
GPIO6/
GPIO4/
EPWM4A/
VDDIO
VDDIO
VSS
VDD
VSS
VSS
F
E
D
C
B
A
EPWM3A
EPWMSYNCI/
EPWMSYNCO
GPIO1/
EPWM1B/
ECAP6/
MFSRB
GPIO3/
EPWM2B/
ECAP5/
GPIO2/
VSS
VDD
VDD
EPWM2A
MCLKRB
GPIO29/
SCITXDA/
XA19
GPIO0/
VSS
VDDIO
VDDIO
VDDIO
EPWM1A
GPIO30/
CANRXA/
XA18
GPIO86/
XA14
GPIO83/
XA11
GPIO81/
XA9
GPIO47/
XA7
VDD
VSS
VSS
GPIO31/
CANTXA/
XA17
GPIO39/
XA16
GPIO85/
XA13
GPIO82/
XA10
GPIO80/
XA8
GPIO46/
XA6
VSS
VSS
GPIO87/
XA15
GPIO84/
XA12
VSS
VSS
VDDIO
VDD18
VSSK
X1
1
2
3
4
5
6
7
8
Figure 6-7. C2834x 256-Ball ZFE Plastic BGA Lower-Left Quadrant (Bottom View)
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TMS320C28346, TMS320C28346-Q1, TMS320C28345, TMS320C28344
TMS320C28343, TMS320C28343-Q1, TMS320C28342, TMS320C28341
www.ti.com
SPRS516F – MARCH 2009 – REVISED FEBRUARY 2021
GPIO72/
XD7
GPIO71/
XD8
GPIO70/
XD9
VSS
VSS
VSS
VSS
VSS
VDD
VSS
VSS
VDD
H
G
F
GPIO75/
XD4
GPIO74/
XD5
GPIO73/
XD6
VSS
VSS
VDD
VSS
GPIO78/
XD1
GPIO77/
XD2
GPIO76/
XD3
VSS
VDD
VDDIO
VDDIO
VSS
VSS
GPIO38/
XWE0
GPIO79/
XD0
VDD
VDD
VSS
E
D
C
B
A
XWE1
VDDIO
VDDIO
VSS
VSS
XCLKOUT
XRD
GPIO35/
SCITXDA/
XR/W
GPIO45/
XA5
GPIO44/
XA4
GPIO42/
XA2
GPIO40/
XA0
VSS
VSS
VDD
GPIO37/
ECAP2/
XZCS7
GPIO28/
SCIRXDA/
XZCS6
GPIO34/
ECAP1/
XREADY
GPIO43/
XA3
GPIO41/
XA1
VDDIO
VSS
VSS
GPIO36/
SCIRXDA/
XZCS0
VDD18
VDDIO
VSS
VSS
VSS
X2
XCLKIN
9
10
11
12
13
14
15
16
Figure 6-8. C2834x 256-Ball ZFE Plastic BGA Lower-Right Quadrant (Bottom View)
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TMS320C28346, TMS320C28346-Q1, TMS320C28345, TMS320C28344
TMS320C28343, TMS320C28343-Q1, TMS320C28342, TMS320C28341
SPRS516F – MARCH 2009 – REVISED FEBRUARY 2021
www.ti.com
6.2 Signal Descriptions
Table 6-1 describes the signals. The GPIO function (shown in Italics) is the default at reset. The peripheral
signals that are listed under them are alternate functions. Some peripheral functions may not be available in all
devices. See Table 5-1 for details. Inputs are not 5-V tolerant. All XINTF pins have a drive strength of 4 mA
(typical). All GPIO pins are I/O/Z, 4-mA drive typical and have an internal pullup, which can be selectively
enabled or disabled on a per-pin basis. This feature only applies to the GPIO pins. The pullups on GPIO0–
GPIO11 and GPIO58–GPIO63 pins are not enabled at reset. The pullups on GPIO12–GPIO57 and GPIO64–
GPIO87 are enabled upon reset.
Table 6-1. Signal Descriptions
ZHH
BALL # BALL #
ZFE
NAME
DESCRIPTION
JTAG
JTAG test reset with internal pulldown. TRST, when driven high, gives the scan system control of
the operations of the device. If this signal is not connected or driven low, the device operates in its
functional mode, and the test reset signals are ignored.
NOTE: TRST is an active high test pin and must be maintained low at all times during normal
device operation. An external pulldown resistor is recommended on this pin. The value of this
resistor should be based on drive strength of the debugger pods applicable to the design. A 2.2-kΩ
resistor generally offers adequate protection. Because this is application-specific, TI recommends
validating each target board for proper operation of the debugger and the application. (I, ↓)
TRST
M7
R8
JTAG test clock. An external pullup resistor is required on this pin. A 2.2-kΩ resistor generally offers
adequate protection.(I)
TCK
TMS
TDI
P9
M8
L6
T11
P9
T8
JTAG test-mode select (TMS) with internal pullup. This serial control input is clocked into the TAP
controller on the rising edge of TCK. (I, ↑)
JTAG test data input (TDI) with internal pullup. TDI is clocked into the selected register (instruction
or data) on a rising edge of TCK. (I, ↑)
JTAG scan out, test data output (TDO). The contents of the selected register (instruction or data)
are shifted out of TDO on the falling edge of TCK.
TDO
N7
P8
Emulator pin 0. When TRST is driven high, this pin is used as an interrupt to or from the emulator
system and is defined as input/output through the JTAG scan. This pin is also used to put the
device into boundary-scan mode. With the EMU0 pin at a logic-high state and the EMU1 pin at a
logic-low state, a rising edge on the TRST pin would latch the device into boundary-scan mode.
NOTE: An external pullup resistor is recommended on this pin. The value of this resistor should be
based on the drive strength of the debugger pods applicable to the design. A 2.2-kΩ to 4.7-kΩ
resistor is generally adequate. Because this is application-specific, TI recommends validating each
each target board for proper operation of the debugger and the application.
EMU0
N9
P10
Emulator pin 1. When TRST is driven high, this pin is used as an interrupt to or from the emulator
system and is defined as input/output through the JTAG scan. This pin is also used to put the
device into boundary-scan mode. With the EMU0 pin at a logic-high state and the EMU1 pin at a
logic-low state, a rising edge on the TRST pin would latch the device into boundary-scan mode.
NOTE: An external pullup resistor is recommended on this pin. The value of this resistor should be
based on the drive strength of the debugger pods applicable to the design. A 2.2-kΩ to 4.7-kΩ
resistor is generally adequate. Because this is application-specific, TI recommends validating each
target board for proper operation of the debugger and the application.
EMU1
L9
R10
Clock
Output clock derived from SYSCLKOUT. XCLKOUT is either the same frequency, one-half the
frequency, one-fourth the frequency, or one-eighth the frequency of SYSCLKOUT. This is controlled
by bit 19 (BY4CLKMODE), bits 18:16 (XTIMCLK), and bit 2 (CLKMODE) in the XINTCNF2 register.
At reset, XCLKOUT = SYSCLKOUT/8. The XCLKOUT signal can be turned off by setting
XINTCNF2[CLKOFF] to 1. Unlike other GPIO pins, the XCLKOUT pin is not placed in high-
impedance state during a reset.
XCLKOUT
B14
D16
External Oscillator Input. This pin is to feed a clock from an external 3.3-V oscillator. In this case,
the X1 pin must be tied to VSSK. If a crystal/resonator is used (or if an external 1.8-V oscillator is
used to feed clock to X1 pin), this pin must be tied to VSS. (I)
XCLKIN
X1
D9
C8
A12
A7
Internal/External Oscillator Input. To use the internal oscillator, a quartz crystal may be connected
across X1 and X2. The X1 pin is referenced to the 1.8-V core digital power supply. A 1.8-V external
oscillator may be connected to the X1 pin. In this case, the XCLKIN pin must be connected to VSS
If a 3.3-V external oscillator is used with the XCLKIN pin, X1 must be tied to VSSK. (I)
.
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SPRS516F – MARCH 2009 – REVISED FEBRUARY 2021
Table 6-1. Signal Descriptions (continued)
ZHH
BALL # BALL #
ZFE
NAME
DESCRIPTION
Internal Oscillator Output. A quartz crystal may be connected across X1 and X2. If X2 is not used it
must be left unconnected. (O)
X2
A8
A9
Reset
Device Reset (in) and Watchdog Reset (out).
Device reset. XRS causes the device to terminate execution. The PC will point to the address
contained at the location 0x3FFFC0. When XRS is brought to a high level, execution begins at the
location pointed to by the PC. This pin is driven low by the MCU when a watchdog reset occurs.
During watchdog reset, the XRS pin is driven low for the watchdog reset duration of 512 OSCCLK
cycles. (I/OD, ↑)
XRS
P8
N8
T10
T9
The output buffer of this pin is an open drain with an internal pullup. It is recommended that this pin
be driven by an open-drain device.
XRS I/O Control (I) - This pin must be connected to the XRS pin on the target board. When XRS is
low (reset), the level detected on this pin puts all output buffers on the device in high-impedance
mode.
XRSIO
External ADC Interface Signals
EXTSOC1A
EXTSOC1B
EXTSOC2A
EXTSOC2B
EXTSOC3A
EXTSOC3B
EXTADCCLK
External ADC SOC Group 1 A Output. Trigger for external ADC, this signal is logical OR of
ePWM1/2/3 SOCA internal signals (O)
N1
M3
M2
P1
N2
M2
M3
N1
N2
N3
External ADC SOC Group 1 B Output. Trigger for external ADC, this signal is logical OR of
ePWM1/2/3 SOCB internal signals (O)
External ADC SOC Group 2 A Output. Trigger for external ADC, this signal is logical OR of
ePWM4/5/6 SOCA internal signals (O)
External ADC SOC Group 2 B Output. Trigger for external ADC, this signal is logical OR of
ePWM4/5/6 SOCB internal signals (O)
External ADC SOC Group 3 A Output. Trigger for external ADC, this signal is logical OR of
ePWM7/8/9 SOCA internal signals (O)
External ADC SOC Group3 B Output. Trigger for external ADC, this signal is logical OR of
ePWM7/8/9 SOCB internal signals (O)
P2
N3
P2
R3
External ADC Clock Signal. Clock for external ADC support, derived from SYSCLK (O)
GPIO and Peripheral Signals
GPIO0
General-purpose input/output 0 (I/O/Z)
EPWM1A
-
-
Enhanced PWM1 Output A and HRPWM channel (O)
-
-
B1
C1
F5
E4
E2
E3
D2
E1
E2
E3
F1
F2
GPIO1
General-purpose input/output 1 (I/O/Z)
Enhanced PWM1 Output B (O)
Enhanced Capture 6 input/output (I/O)
McBSP-B receive frame synch (I/O)
EPWM1B
ECAP6
MFSRB
GPIO2
EPWM2A
-
-
General-purpose input/output 2 (I/O/Z)
Enhanced PWM2 Output A and HRPWM channel (O)
-
-
GPIO3
EPWM2B
ECAP5
General-purpose input/output 3 (I/O/Z)
Enhanced PWM2 Output B (O)
Enhanced Capture 5 input/output (I/O)
McBSP-B receive clock (I/O)
MCLKRB
GPIO4
EPWM3A
-
-
General-purpose input/output 4 (I/O/Z)
Enhanced PWM3 output A and HRPWM channel (O)
-
-
GPIO5
General-purpose input/output 5 (I/O/Z)
Enhanced PWM3 output B (O)
McBSP-A receive frame synch (I/O)
Enhanced Capture input/output 1 (I/O)
EPWM3B
MFSRA
ECAP1
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TMS320C28343, TMS320C28343-Q1, TMS320C28342, TMS320C28341
SPRS516F – MARCH 2009 – REVISED FEBRUARY 2021
www.ti.com
Table 6-1. Signal Descriptions (continued)
ZHH
BALL # BALL #
ZFE
NAME
GPIO6
EPWM4A
EPWMSYNCI
EPWMSYNCO
DESCRIPTION
General-purpose input/output 6 (I/O/Z)
Enhanced PWM4 output A and HRPWM channel (O)
External ePWM sync pulse input (I)
F3
F2
G4
G2
G3
H3
H2
H4
F3
G1
G2
G3
H1
H2
H3
J2
External ePWM sync pulse output (O)
GPIO7
General-purpose input/output 7 (I/O/Z)
Enhanced PWM4 output B (O)
McBSP-A receive clock (I/O)
EPWM4B
MCLKRA
ECAP2
Enhanced capture input/output 2 (I/O)
GPIO8
General-purpose input/output 8 (I/O/Z)
Enhanced PWM5 output A and HRPWM channel (O)
Enhanced CAN-B transmit (O)
EPWM5A
CANTXB
ADCSOCAO
ADC start-of-conversion A (O)
GPIO9
General-purpose input/output 9 (I/O/Z)
Enhanced PWM5 output B (O)
SCI-B transmit data(O)
EPWM5B
SCITXDB
ECAP3
Enhanced capture input/output 3 (I/O)
GPIO10
General-purpose input/output 10 (I/O/Z)
Enhanced PWM6 output A and HRPWM channel (O)
Enhanced CAN-B receive (I)
EPWM6A
CANRXB
ADCSOCBO
ADC start-of-conversion B (O)
GPIO11
General-purpose input/output 11 (I/O/Z)
Enhanced PWM6 output B (O)
SCI-B receive data (I)
EPWM6B
SCIRXDB
ECAP4
Enhanced CAP Input/Output 4 (I/O)
GPIO12
TZ1
CANTXB
MDXB
General-purpose input/output 12 (I/O/Z)
Trip Zone input 1 (I)
Enhanced CAN-B transmit (O)
McBSP-B transmit serial data (O)
GPIO13
TZ2
CANRXB
MDRB
General-purpose input/output 13 (I/O/Z)
Trip Zone input 2 (I)
Enhanced CAN-B receive (I)
McBSP-B receive serial data (I)
GPIO14
General-purpose input/output 14 (I/O/Z)
Trip Zone input 3/External Hold Request. XHOLD, when active (low), requests the external interface
(XINTF) to release the external bus and place all buses and strobes into a high-impedance state. To
prevent this from happening when TZ3 signal goes active, disable this function by writing
XINTCNF2[HOLD] = 1. If this is not done, the XINTF bus will go into high impedance anytime TZ3
goes low. On the ePWM side, TZn signals are ignored by default, unless they are enabled by the
code. The XINTF will release the bus when any current access is complete and there are no
pending accesses on the XINTF. (I)
TZ3/ XHOLD
H5
J3
SCITXDB
MCLKXB
SCI-B Transmit (O)
McBSP-B transmit clock (I/O)
GPIO15
General-purpose input/output 15 (I/O/Z)
Trip Zone input 4/External Hold Acknowledge. The pin function for this option is based on the
direction chosen in the GPADIR register. If the pin is configured as an input, then TZ4 function is
chosen. If the pin is configured as an output, then XHOLDA function is chosen. XHOLDA is driven
active (low) when the XINTF has granted an XHOLD request. All XINTF buses and strobe signals
will be in a high-impedance state. XHOLDA is released when the XHOLD signal is released.
External devices should only drive the external bus when XHOLDA is active (low). (I/O)
TZ4/ XHOLDA
K2
K4
K2
L1
SCIRXDB
MFSXB
SCI-B receive (I)
McBSP-B transmit frame synch (I/O)
GPIO16
SPISIMOA
CANTXB
TZ5
General-purpose input/output 16 (I/O/Z)
SPI slave in, master out (I/O)
Enhanced CAN-B transmit (O)
Trip Zone input 5 (I)
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TMS320C28346, TMS320C28346-Q1, TMS320C28345, TMS320C28344
TMS320C28343, TMS320C28343-Q1, TMS320C28342, TMS320C28341
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NAME
SPRS516F – MARCH 2009 – REVISED FEBRUARY 2021
Table 6-1. Signal Descriptions (continued)
ZHH
BALL # BALL #
ZFE
DESCRIPTION
GPIO17
SPISOMIA
CANRXB
TZ6
General-purpose input/output 17 (I/O/Z)
SPI-A slave out, master in (I/O)
Enhanced CAN-B receive (I)
Trip zone input 6 (I)
J5
L1
L2
M1
T4
R4
T5
R5
P5
T6
R6
P6
T7
GPIO18
General-purpose input/output 18 (I/O/Z)
SPI-A clock input/output (I/O)
SCI-B transmit (O)
SPICLKA
SCITXDB
CANRXA
Enhanced CAN-A receive (I)
GPIO19
General-purpose input/output 19 (I/O/Z)
SPI-A slave transmit enable input/output (I/O)
SCI-B receive (I)
SPISTEA
SCIRXDB
CANTXA
P3
L4
Enhanced CAN-A transmit (O)
GPIO20
EQEP1A
MDXA
General-purpose input/output 20 (I/O/Z)
Enhanced QEP1 input A (I)
McBSP-A transmit serial data (O)
Enhanced CAN-B transmit (O)
CANTXB
GPIO21
EQEP1B
MDRA
General-purpose input/output 21 (I/O/Z)
Enhanced QEP1 input B (I)
McBSP-A receive serial data (I)
Enhanced CAN-B receive (I)
M4
N4
P4
P5
M5
K6
M6
CANRXB
GPIO22
General-purpose input/output 22 (I/O/Z)
Enhanced QEP1 strobe (I/O)
McBSP-A transmit clock (I/O)
SCI-B transmit (O)
EQEP1S
MCLKXA
SCITXDB
GPIO23
EQEP1I
MFSXA
SCIRXDB
General-purpose input/output 23 (I/O/Z)
Enhanced QEP1 index (I/O)
McBSP-A transmit frame synch (I/O)
SCI-B receive (I)
GPIO24
ECAP1
EQEP2A
MDXB
General-purpose input/output 24 (I/O/Z)
Enhanced capture 1 (I/O)
Enhanced QEP2 input A (I)
McBSP-B transmit serial data (O)
GPIO25
ECAP2
EQEP2B
MDRB
General-purpose input/output 25 (I/O/Z)
Enhanced capture 2 (I/O)
Enhanced QEP2 input B (I)
McBSP-B receive serial data (I)
GPIO26
ECAP3
EQEP2I
MCLKXB
General-purpose input/output 26 (I/O/Z)
Enhanced capture 3 (I/O)
Enhanced QEP2 index (I/O)
McBSP-B transmit clock (I/O)
GPIO27
ECAP4
EQEP2S
MFSXB
General-purpose input/output 27 (I/O/Z)
Enhanced capture 4 (I/O)
Enhanced QEP2 strobe (I/O)
McBSP-B transmit frame synch (I/O)
GPIO28
SCIRXDA
XZCS6
General-purpose input/output 28 (I/O/Z)
SCI receive data (I)
External Interface zone 6 chip select (O)
A12
C3
C2
B2
B13
D1
C2
B3
GPIO29
SCITXDA
XA19
General-purpose input/output 29. (I/O/Z)
SCI transmit data (O)
External Interface Address Line 19 (O)
GPIO30
CANRXA
XA18
General-purpose input/output 30 (I/O/Z)
Enhanced CAN-A receive (I)
External Interface Address Line 18 (O)
GPIO31
CANTXA
XA17
General-purpose input/output 31 (I/O/Z)
Enhanced CAN-A transmit (O)
External Interface Address Line 17 (O)
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TMS320C28346, TMS320C28346-Q1, TMS320C28345, TMS320C28344
TMS320C28343, TMS320C28343-Q1, TMS320C28342, TMS320C28341
SPRS516F – MARCH 2009 – REVISED FEBRUARY 2021
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Table 6-1. Signal Descriptions (continued)
ZHH
BALL # BALL #
ZFE
NAME
GPIO32
SDAA
EPWMSYNCI
ADCSOCAO
DESCRIPTION
General-purpose input/output 32 (I/O/Z)
I2C data open-drain bidirectional port (I/OD)
Enhanced PWM external sync pulse input (I)
ADC start-of-conversion A (O)
P6
N6
R7
P7
GPIO33
SCLA
EPWMSYNCO
ADCSOCBO
General-purpose input/output 33 (I/O/Z)
I2C clock open-drain bidirectional port (I/OD)
Enhanced PWM external synch pulse output (O)
ADC start-of-conversion B (O)
GPIO34
ECAP1
XREADY
General-purpose input/output 34 (I/O/Z)
Enhanced Capture input/output 1 (I/O)
External Interface Ready signal
A13
B13
B12
D11
B14
C15
A13
B12
GPIO35
SCITXDA
XR/ W
General-purpose input/output 35 (I/O/Z)
SCI-A transmit data (O)
External Interface read, not write strobe
GPIO36
SCIRXDA
XZCS0
General-purpose input/output 36 (I/O/Z)
SCI-A receive data (I)
External Interface zone 0 chip select (O)
GPIO37
ECAP2
XZCS7
General-purpose input/output 37 (I/O/Z)
Enhanced Capture input/output 2 (I/O)
External Interface zone 7 chip select (O)
General-purpose input/output 38 (I/O/Z)
-
External Interface Write Enable 0 (O). XWE0 defaults back to GPIO38 upon reset, during which
time it will be high-impedance.
GPIO38
-
XWE0
C12
E15
GPIO39
-
XA16
General-purpose input/output 39 (I/O/Z)
-
External Interface Address Line 16 (O)
A2
E10
D10
B10
A10
A9
B4
C12
B11
C11
B10
C10
C9
GPIO40
-
XA0
General-purpose input/output 40 (I/O/Z)
-
External Interface Address Line 0
GPIO41
-
XA1
General-purpose input/output 41 (I/O/Z)
-
External Interface Address Line 1 (O)
GPIO42
-
XA2
General-purpose input/output 42 (I/O/Z)
-
External Interface Address Line 2 (O)
GPIO43
-
XA3
General-purpose input/output 43 (I/O/Z)
-
External Interface Address Line 3 (O)
GPIO44
-
XA4
General-purpose input/output 44 (I/O/Z)
-
External Interface Address Line 4 (O)
GPIO45
-
General-purpose input/output 45 (I/O/Z)
-
B9
XA5
External Interface Address Line 5 (O)
GPIO46
General-purpose input/output 46 (I/O/Z)
-
E7
B8
-
XA6
External Interface Address Line 6 (O)
GPIO47
General-purpose input/output 47 (I/O/Z)
-
D6
C8
-
XA7
External Interface Address Line 7 (O)
GPIO48
ECAP5
XD31
General-purpose input/output 48 (I/O/Z)
Enhanced Capture input/output 5 (I/O)
External Interface Data Line 31 (O)
SPI-D slave in, master out (I/O)
M10
R11
SPISIMOD
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NAME
SPRS516F – MARCH 2009 – REVISED FEBRUARY 2021
Table 6-1. Signal Descriptions (continued)
ZHH
BALL # BALL #
ZFE
DESCRIPTION
GPIO49
ECAP6
XD30
General-purpose input/output 49 (I/O/Z)
Enhanced Capture input/output 6 (I/O)
External Interface Data Line 30 (O)
SPI-D slave out, master in (I/O)
P10
N10
N11
P11
T12
R12
SPISOMID
GPIO50
EQEP1A
XD29
General-purpose input/output 50 (I/O/Z)
Enhanced QEP 1input A (I)
External Interface Data Line 29 (O)
SPI-D Clock input/output (I/O)
SPICLKD
GPIO51
EQEP1B
XD28
General-purpose input/output 51 (I/O/Z)
Enhanced QEP 1input B (I)
External Interface Data Line 28 (O)
SPISTED
SPI-D slave transmit enable input/output (I/O)
GPIO52
EQEP1S
XD27
General-purpose input/output 52 (I/O/Z)
Enhanced QEP 1Strobe (I/O)
External Interface Data Line 27 (O)
M11
L11
P12
T13
GPIO53
EQEP1I
XD26
General-purpose input/output 53 (I/O/Z)
Enhanced QEP1 lndex (I/O)
External Interface Data Line 26 (O)
GPIO54
SPISIMOA
XD25
General-purpose input/output 54 (I/O/Z)
SPI-A slave in, master out (I/O)
External Interface Data Line 25 (O)
Enhanced QEP3 input A (I)
P12
N12
P13
N13
P14
M13
M14
L12
L13
K13
R13
P13
R14
P15
N16
N15
M16
M15
M14
L16
EQEP3A
GPIO55
SPISOMIA
XD24
General-purpose input/output 55 (I/O/Z)
SPI-A slave out, master in (I/O)
External Interface Data Line 24 (O)
Enhanced QEP3 input B (I)
EQEP3B
GPIO56
SPICLKA
XD23
General-purpose input/output 56 (I/O/Z)
SPI-A clock (I/O)
External Interface Data Line 23 (O)
Enhanced QEP3 strobe (I/O)
EQEP3S
GPIO57
SPISTEA
XD22
General-purpose input/output 57 (I/O/Z)
SPI-A slave transmit enable (I/O)
External Interface Data Line 22 (O)
Enhanced QEP3 index (I/O)
EQEP3I
GPIO58
MCLKRA
XD21
General-purpose input/output 58 (I/O/Z)
McBSP-A receive clock (I/O)
External Interface Data Line 21 (O)
EPWM7A
Enhanced PWM 7 output A and HRPWM channel (O)
GPIO59
MFSRA
XD20
General-purpose input/output 59 (I/O/Z)
McBSP-A receive frame synch (I/O)
External Interface Data Line 20 (O)
Enhanced PWM 7 output B (O)
EPWM7B
GPIO60
MCLKRB
XD19
General-purpose input/output 60 (I/O/Z)
McBSP-B receive clock (I/O)
External Interface Data Line 19 (O)
EPWM8A
Enhanced PWM 8 output A and HRPWM channel (O)
GPIO61
MFSRB
XD18
General-purpose input/output 61 (I/O/Z)
McBSP-B receive frame synch (I/O)
External Interface Data Line 18 (O)
Enhanced PWM8 output B (O)
EPWM8B
GPIO62
SCIRXDC
XD17
General-purpose input/output 62 (I/O/Z)
SCI-C receive data (I)
External Interface Data Line 17 (O)
Enhanced PWM9 output A and HRPWM channel (O)
EPWM9A
GPIO63
SCITXDC
XD16
General-purpose input/output 63 (I/O/Z)
SCI-C transmit data (O)
External Interface Data Line 16 (O)
Enhanced PWM9 output B (O)
EPWM9B
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TMS320C28346, TMS320C28346-Q1, TMS320C28345, TMS320C28344
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SPRS516F – MARCH 2009 – REVISED FEBRUARY 2021
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Table 6-1. Signal Descriptions (continued)
ZHH
BALL # BALL #
ZFE
NAME
GPIO64
DESCRIPTION
General-purpose input/output 64 (I/O/Z)
-
K12
K14
J11
J12
J13
H13
H12
G12
G13
F14
F13
F12
E13
E11
F10
C14
E6
L15
L14
K15
K14
J15
J14
H16
H15
H14
G16
G15
G14
F16
F15
F14
E16
B7
-
XD15
External Interface Data Line 15 (O)
GPIO65
-
XD14
General-purpose input/output 65 (I/O/Z)
-
External Interface Data Line 14 (O)
GPIO66
-
XD13
General-purpose input/output 66 (I/O/Z)
-
External Interface Data Line 13 (O)
GPIO67
-
XD12
General-purpose input/output 67 (I/O/Z)
-
External Interface Data Line 12 (O)
GPIO68
-
XD11
General-purpose input/output 68 (I/O/Z)
-
External Interface Data Line 11 (O)
GPIO69
-
XD10
General-purpose input/output 69 (I/O/Z)
-
External Interface Data Line 10 (O)
GPIO70
-
XD9
General-purpose input/output 70 (I/O/Z)
-
External Interface Data Line 9 (O)
GPIO71
-
XD8
General-purpose input/output 71 (I/O/Z)
-
External Interface Data Line 8 (O)
GPIO72
-
XD7
General-purpose input/output 72 (I/O/Z)
-
External Interface Data Line 7 (O)
GPIO73
-
XD6
General-purpose input/output 73 (I/O/Z)
-
External Interface Data Line 6 (O)
GPIO74
-
XD5
General-purpose input/output 74 (I/O/Z)
-
External Interface Data Line 5 (O)
GPIO75
-
XD4
General-purpose input/output 75 (I/O/Z)
-
External Interface Data Line 4 (O)
GPIO76
-
XD3
General-purpose input/output 76 (I/O/Z)
-
External Interface Data Line 3 (O)
GPIO77
-
XD2
General-purpose input/output 77 (I/O/Z)
-
External Interface Data Line 2 (O)
GPIO78
-
XD1
General-purpose input/output 78 (I/O/Z)
-
External Interface Data Line 1 (O)
GPIO79
-
XD0
General-purpose input/output 79 (I/O/Z)
-
External Interface Data Line 0 (O)
GPIO80
-
General-purpose input/output 80 (I/O/Z)
-
XA8
External Interface Address Line 8 (O)
GPIO81
General-purpose input/output 81 (I/O/Z)
-
C5
C7
-
XA9
External Interface Address Line 9 (O)
GPIO82
-
General-purpose input/output 82 (I/O/Z)
-
A5
B6
XA10
External Interface Address Line 10 (O)
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TMS320C28343, TMS320C28343-Q1, TMS320C28342, TMS320C28341
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NAME
SPRS516F – MARCH 2009 – REVISED FEBRUARY 2021
Table 6-1. Signal Descriptions (continued)
ZHH
BALL # BALL #
ZFE
DESCRIPTION
GPIO83
-
XA11
General-purpose input/output 83 (I/O/Z)
-
External Interface Address Line 11 (O)
B5
D5
D4
A3
B3
C6
A5
B5
C5
A4
GPIO84
-
XA12
General-purpose input/output 84 (I/O/Z)
-
External Interface Address Line 12 (O)
GPIO85
-
XA13
General-purpose input/output 85 (I/O/Z)
-
External Interface Address Line 13 (O)
GPIO86
-
XA14
General-purpose input/output 86 (I/O/Z)
-
External Interface Address Line 14 (O)
GPIO87
-
General-purpose input/output 87 (I/O/Z)
-
XA15
External Interface Address Line 15 (O)
External Interface Read Enable (O). The XRD pin is high-impedance on reset. It stays that way as
long as the XINTF clock is turned off (which happens on reset).
XRD
A14
C13
D15
E14
External Memory Interface Write Enable for Upper 16-bits (O). The XWE1 pin is high-impedance on
reset. It stays that way as long as the XINTF clock is turned off (which happens on reset).
XWE1
CPU and I/O Power Pins
VDD18
VDD18
VSSK
E8
C7
A6
Oscillator and PLL Power Pin (1.8 V)
A11
Oscillator Kelvin Reference Ground. This pin should not be connected to Vss. See Figure 8-29
through Figure 8-31 for proper application board connections.
B8
A8
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TMS320C28343, TMS320C28343-Q1, TMS320C28342, TMS320C28341
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Table 6-1. Signal Descriptions (continued)
ZHH
BALL # BALL #
ZFE
NAME
DESCRIPTION
VDD
D1
E1
C1
C16
E6
VDD
VDD
G1
VDD
K3
E7
VDD
M1
N5
E8
VDD
E9
VDD
P7
E10
E11
F5
VDD
J3
VDD
J4
VDD
K9
F12
G5
G12
H5
VDD
L10
N14
K11
H11
H14
G10
E12
D12
C11
C10
B7
VDD
VDD
VDD
H12
J5
VDD
CPU and logic digital power pins (1.1 V/1.2 V)
VDD
J12
K3
VDD
VDD
K5
VDD
K12
L3
VDD
VDD
L5
VDD
C6
L12
M6
M7
M8
M9
M10
M11
P1
VDD
E5
VDD
C4
VDD
VDD
VDD
VDD
VDD
VDD
P16
A3
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
D3
F1
A14
B9
J1
L2
D5
K5
K7
K8
P11
L14
D6
Digital I/O power pins (3.3 V)
D8
D11
D12
E4
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NAME
SPRS516F – MARCH 2009 – REVISED FEBRUARY 2021
Table 6-1. Signal Descriptions (continued)
ZHH
BALL # BALL #
ZFE
DESCRIPTION
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
J14
F11
D14
A11
C9
E13
F4
F13
J1
J4
D7
J13
J16
L4
B6
B4
L13
M4
M13
N5
Digital I/O power pins
N6
N8
N11
N12
R9
T3
T14
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TMS320C28346, TMS320C28346-Q1, TMS320C28345, TMS320C28344
TMS320C28343, TMS320C28343-Q1, TMS320C28342, TMS320C28341
SPRS516F – MARCH 2009 – REVISED FEBRUARY 2021
www.ti.com
Table 6-1. Signal Descriptions (continued)
ZHH
BALL # BALL #
ZFE
NAME
DESCRIPTION
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
D2
F4
A1
A2
G5
H1
A10
A15
A16
B1
J2
K1
L3
B2
L5
B15
B16
C3
L7
L8
M9
K10
M12
J10
H10
G14
G11
E14
D13
B11
E9
C4
C13
C14
D3
Digital ground pins
D4
D7
D9
D10
D13
D14
E5
D8
E12
F6
A7
A6
F7
A4
F8
F9
F10
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NAME
SPRS516F – MARCH 2009 – REVISED FEBRUARY 2021
Table 6-1. Signal Descriptions (continued)
ZHH
ZFE
DESCRIPTION
BALL # BALL #
F11
G4
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
G6
G7
G8
G9
G10
G11
G13
H4
H6
H7
H8
H9
H10
H11
H13
J6
J7
J8
J9
J10
J11
K1
Digital ground pins
K4
K6
K7
K8
K9
K10
K11
K13
K16
L6
L7
L8
L9
L10
L11
M5
M12
N4
N7
N9
N10
N13
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Table 6-1. Signal Descriptions (continued)
ZHH
BALL # BALL #
ZFE
NAME
DESCRIPTION
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
N14
P3
P4
P14
R1
R2
Digital ground pins
R15
R16
T1
T2
T15
T16
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7 Specifications
This section provides the absolute maximum ratings and the recommended operating conditions.
7.1 Absolute Maximum Ratings (1) (2)
MIN
MAX
4
UNIT
Supply voltage
Input voltage
VDDIO with respect to VSS
VDD with respect to VSS
VDD18 with respect to VSS
VIN (3.3 V)
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–20
1.5
2.4
4
V
V
VIN (1.8 V)
2.4
4
Output voltage
VO
V
(3)
Input clamp current
Output clamp current
Junction temperature
Storage temperature
IIK (VIN < 0 or VIN > VDDIO
)
20
mA
mA
°C
IOK (VO < 0 or VO > VDDIO
)
–20
20
(4)
TJ
–40
150
150
(4)
Tstg
–65
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Section 7.4 is not implied.
Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to VSS, unless otherwise noted.
(3) Continuous clamp current per pin is ±2 mA.
(4) One or both of the following conditions may result in a reduction of overall device life:
•
•
long-term high-temperature storage
extended use at maximum temperature
For additional information, see Semiconductor and IC Package Thermal Metrics.
7.2 ESD Ratings – Automotive
VALUE
UNIT
TMS320C2834x in ZFE Package
Human body model (HBM), per AEC Q100-002(1)
±2000
±500
±750
All pins
V(ESD) Electrostatic discharge
V
Charged-device model (CDM), per AEC Q100-011
Corner pins on 256-ball
ZFE: A1, A16, T1, T16
(1) AEC Q100-002 indicates HBM stressing is done in accordance wit hthe ANSI/ESDA/JEDEC JS-001 specification.
7.3 ESD Ratings – Commercial
VALUE
UNIT
TMS320C2834x in ZHH Package
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±2000
±500
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM), per JEDEC specification JESD22-
C101(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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7.4 Recommended Operating Conditions
MIN
3.14
1.14
1.05
NOM
3.3
1.2
1.1
0
MAX
3.46
1.26
1.16
UNIT
Device supply voltage, I/O, VDDIO
V
300-MHz devices
Device supply voltage CPU, VDD
V
200-MHz devices
Supply ground, VSS, VSSIO
Oscillator supply ground, VSSK
PLL/oscillator supply, VDD18
V
V
V
0
1.71
2
1.8
1.89
300
Device clock frequency (system clock),
fSYSCLKOUT
C28346/C28344/C28342
(VDD = 1.2 V ± 5%)
MHz
C28345/C28343/C28341
(VDD = 1.1 V ± 5%)
2
200
High-level input voltage, VIH (3.3 V)
High-level input voltage, VIH (1.8 V)
Low-level input voltage, VIL (3.3 V)
Low-level input voltage, VIL (1.8 V)
2
0.7 * VDD18
VSS – 0.3
VDDIO + 0.3
V
V
V
V
0.8
0.3 * VDD18
–4
High-level output source current,
VOH = 2.4 V, IOH
All I/Os
All I/Os
mA
mA
Low-level output sink current,
VOL = VOL MAX, IOL
4
T version
S version
–40
–40
–40
105
125
125
(1)
Junction temperature, TJ
°C
Q version
(AEC Q100 Qualification)
(1) TA (Ambient temperature) is product- and application-dependent and can go up to the specified TJ maximum of the device. See
Section 7.8, Thermal Design Considerations.
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7.5 Power Consumption Summary
7.5.1 TMS320C28346/C28344 (1) Current Consumption by Power-Supply Pins at 300-MHz SYSCLKOUT
(2)
IDD
IDDIO
IDD18
MODE
TEST CONDITIONS
25°C
105°C
125°C
25°C
105°C
125°C
25°C
105°C
125°C
The following peripheral clocks are
enabled:
•
ePWM1, ePWM2, ePWM3,
ePWM4, ePWM5, ePWM6,
ePWM7, ePWM8, ePWM9
•
•
•
•
•
•
•
•
•
•
eCAP1, eCAP2, eCAP3
eQEP1, eQEP2, eQEP3
eCAN-A
SCI-A, SCI-B (FIFO mode)
SPI-A (FIFO mode)
McBSP-A
Typical Operational
335 mA
555 mA
740 mA
75 mA
75 mA
80 mA
50 mA
47 mA
45 mA
I2C
XINTF
DMA
CPU-Timer 0, CPU-Timer 1,
CPU-Timer 2
All PWM pins are toggled at
300 kHz.
All I/O pins are left unconnected.
XCLKOUT is turned off. Pullups on
output pins and XINTF pins are
disabled.(3)
XCLKOUT is turned off.
Peripheral clocks are off.
IDLE
205 mA
140 mA
135 mA
425 mA
360 mA
355 mA
610 mA
545 mA
540 mA
15 mA
15 mA
15 mA
15 mA
15 mA
15 mA
18 mA
18 mA
18 mA
50 mA
50 mA
550 μA
47 mA
47 mA
550 μA
45 mA
45 mA
550 μA
STANDBY
HALT
Peripheral clocks are off.
Peripheral clocks are off.
Input clock is disabled.(4)
(1) The IDD numbers in this table are valid for the TMS320C28346 and TMS320C28344 devices only. For the TMS320C28342 device,
subtract the IDD current numbers for those peripherals that do not exist on this device (see Table 7-1) from the IDD current numbers
shown in this table.
(2) IDDIO current is dependent on the electrical loading on the I/O pins.
(3) The following is done in a loop:
•
•
•
•
•
Data is continuously transmitted out of the SCI-A, SCI-B, SPI-A, McBSP-A, and eCAN-A ports.
Floating-point multiplication and addition are performed.
32-bit read/write of the XINTF is performed.
DMA channels 1 and 2 transfer data from SARAM to SARAM.
GPIO19 is toggled.
(4) If a quartz crystal or ceramic resonator is used as the clock source, the HALT mode shuts down the internal oscillator.
Note
The IDD numbers in Section 7.5.1 are valid for the TMS320C28346 and TMS320C28344 devices only.
For the TMS320C28342 device, subtract the IDD current numbers for those peripherals that do not
exist on this device (see Table 7-1) from the IDD current numbers shown in Section 7.5.1.
Note
The peripheral - I/O multiplexing implemented in the device prevents all available peripherals from
being used at the same time. This is because more than one peripheral function may share an I/O pin.
It is, however, possible to turn on the clocks to all the peripherals at the same time, although such a
configuration is not useful. If this is done, the current drawn by the device will be more than the
numbers specified in the current consumption tables.
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7.5.2 TMS320C28345/C28343 (1) Current Consumption by Power-Supply Pins at 200-MHz SYSCLKOUT
(2)
IDD
IDDIO
IDD18
MODE
TEST CONDITIONS
25°C
105°C
125°C
25°C
105°C
125°C
25°C
105°C
125°C
The following peripheral clocks are
enabled:
•
ePWM1, ePWM2, ePWM3,
ePWM4, ePWM5, ePWM6,
ePWM7, ePWM8, ePWM9
•
•
•
•
•
•
•
•
•
•
eCAP1, eCAP2, eCAP3
eQEP1, eQEP2, eQEP3
eCAN-A
SCI-A, SCI-B (FIFO mode)
SPI-A (FIFO mode)
McBSP-A
Typical operation
200 mA
380 mA
500 mA
45 mA
45 mA
45 mA
45 mA
43 mA
40 mA
I2C
XINTF
DMA
CPU-TImers 0, CPU-Timer 1,
CPU-Timer 2
All PWM pins are toggled at 200 kHz.
All I/O pins are left unconnected.
XCLKOUT is turned off. Pullups on
output pins and XINTF pins are
disabled.(3)
Peripheral clocks are off. XCLKOUT is
turned off.
IDLE
95 mA
45 mA
40 mA
275 mA
225 mA
220 mA
395 mA
345 mA
340 mA
15 mA
15 mA
15 mA
15 mA
15 mA
15 mA
18 mA
18 mA
18 mA
45 mA
45 mA
550 μA
43 mA
43 mA
550 μA
40 mA
40 mA
550 μA
STANDBY
HALT
Peripheral clocks are off.
Peripheral clocks are off. Input clock is
disabled.(4)
(1) The IDD numbers in this table are valid for the TMS320C28345 and TMS320C28343 devices only. For the TMS320C28341 device,
subtract the IDD current numbers for those peripherals that do not exist on this device (see Table 7-1) from the IDD current numbers
shown in this table.
(2) IDDIO current is dependent on the electrical loading on the I/O pins.
(3) The following is done in a loop:
•
•
•
•
•
Data is continuously transmitted out of the SCI-A, SCI-B, SPI-A, McBSP-A, and eCAN-A ports.
Floating-point multiplication and addition are performed.
32-bit read/write of the XINTF is performed.
DMA channels 1 and 2 transfer data from SARAM to SARAM.
GPIO19 is toggled.
(4) If a quartz crystal or ceramic resonator is used as the clock source, the HALT mode shuts down the internal oscillator.
Note
The IDD numbers in Section 7.5.2 are valid for the TMS320C28345 and TMS320C28343 devices only.
For the TMS320C28341 device, subtract the IDD current numbers for those peripherals that do not
exist on this device (see Table 7-1) from the IDD current numbers shown in Section 7.5.2.
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7.5.3 Reducing Current Consumption
Methods of reducing current consumption include the following:
•
Turn off the clock to any peripheral module that is not used in a given application because each peripheral
unit has an individual clock-enable bit. Table 7-1 indicates the typical reduction in current consumption
achieved by turning off the clocks.
•
•
•
Use any one of the three low-power modes to reduce current even further.
Turn off XCLKOUT, reducing IDDIO current consumption by 15 mA (typical).
Disable the pullups on pins that assume an output function and on XINTF pins for significant savings in IDDIO
.
Note
The TMS320C2834x devices are manufactured in a high-performance process node. Compared to
the previous generation of the C28x devices, this process has more leakage current. Leakage current
is significantly impacted by the operating temperature, and the increase in current with temperature is
nonlinear. The total power for a given operating condition includes switching/active power plus
leakage power. Low-power HALT mode power is due to the leakage current alone.
Figure 7-1 shows the typical leakage current across temperature.
Temperature (°C) Vs Leakage current (mA)
600
500
400
300
200
100
0
-20
0
20
40
60
80
100
120
140
Temperature (°C)
Figure 7-1. Temperature Versus Leakage Current (Typical)
Table 7-1. Typical Current Consumption by Various
Peripherals (1)
PERIPHERAL
MODULE
IDD CURRENT
REDUCTION (mA)
I2C
5
5
3
eQEP
ePWM
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Table 7-1. Typical Current Consumption by Various
Peripherals (1) (continued)
PERIPHERAL
IDD CURRENT
MODULE
eCAP
SCI
REDUCTION (mA)
1
4
SPI
4
eCAN
McBSP
CPU-Timer
XINTF
DMA
2
8
1
4(2)
7
FPU
8
(1) All peripheral clocks (except CPU timer clocks) are disabled
upon reset. Writing to or reading from peripheral registers is
possible only after the peripheral clocks are turned on.
(2) Operating the XINTF bus has a significant effect on IDDIO
current. It will increase considerably based on the following:
•
How many address/data pins toggle from one cycle to
another
•
•
•
•
How fast they toggle
Whether 16-bit or 32-bit interface is used and
The load on these pins.
Whether internal pullups are enabled on the XINTF pins.
7.6 Electrical Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
2.4
TYP
MAX UNIT
IOH = IOH MAX
IOH = 50 μA
VOH High-level output voltage
V
VDDIO – 0.2
VOL
Low-level output voltage
Pin with pullup
IOL = IOL MAX
0.4
V
VDDIO = 3.3 V, VIN = 0 V
VDDIO = 3.3 V, VIN = 0 V
VDDIO = 3.3 V, VIN = VDDIO
VDDIO = 3.3 V, VIN = VDDIO
VO = VDDIO or 0 V
All I/Os (including XRS)
–190
–100
enabled
Input current
(low level)
IIL
μA
Pin with pulldown
enabled
±15
±3
Pin with pullup
enabled
Input current
(high level)
IIH
μA
Pin with pulldown
enabled
100
175
±15
Output current, pullup or pulldown
disabled
IOZ
CI
μA
pF
Input capacitance
2
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7.7 Thermal Resistance Characteristics
7.7.1 ZHH Package
°C/W(1) (2)
10.3
21.2
40.8
32.4
31.0
29.1
0.4
AIR FLOW (lfm)(3)
RΘJC
RΘJB
Junction-to-case
Junction-to-board
0
0
0
150
250
500
0
RΘJA
(High k PCB)
Junction-to-free air
Junction-to-package top
Junction-to-board
0.5
150
250
500
0
PsiJT
0.6
0.8
21.0
20.4
20.2
19.9
150
250
500
PsiJB
(1) °C/W = degrees Celsius per watt
(2) These values are based on a JEDEC-defined 2S2P system (with the exception of the Theta JC [RΘJC] value, which is based on a
JEDEC-defined 1S0P system) and will change based on environment as well as application. For more information, see these EIA/
JEDEC standards:
•
•
•
•
JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air)
JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements
(3) lfm = linear feet per minute
7.7.2 ZFE Package
°C/W(1) (2)
14
AIR FLOW (lfm)(3)
RΘJC
RΘJB
Junction-to-case
Junction-to-board
0
13.9
30
0
0
21.8
20.6
19.1
1.24
2.63
3.15
4.05
14
150
250
500
0
RΘJA
(High k PCB)
Junction-to-free air
Junction-to-package top
Junction-to-board
150
250
500
0
PsiJT
13.6
13.5
13.4
150
250
500
PsiJB
(1) °C/W = degrees Celsius per watt
(2) These values are based on a JEDEC-defined 2S2P system (with the exception of the Theta JC [RΘJC] value, which is based on a
JEDEC-defined 1S0P system) and will change based on environment as well as application. For more information, see these EIA/
JEDEC standards:
•
•
JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air)
JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
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•
•
JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements
(3) lfm = linear feet per minute
7.8 Thermal Design Considerations
Based on the end application design and operational profile, the IDD and IDDIO currents could vary. Systems that
exceed the recommended maximum power dissipation in the end product may require additional thermal
enhancements. Ambient temperature (TA) varies with the end application and product design. The critical factor
that affects reliability and functionality is TJ, the junction temperature, not the ambient temperature. Hence, care
should be taken to keep TJ within the specified limits. Tcase should be measured to estimate the operating
junction temperature TJ. Tcase is normally measured at the center of the package top-side surface. The thermal
application report Semiconductor and IC package thermal metrics helps to understand the thermal metrics and
definitions.
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7.9 Timing and Switching Characteristics
7.9.1 Timing Parameter Symbology
Timing parameter symbols used are created in accordance with JEDEC Standard 100. To shorten the symbols,
some of the pin names and other related terminology have been abbreviated as follows:
Lowercase subscripts and their
meanings:
Letters and symbols and their
meanings:
a
c
d
f
access time
cycle time (period)
delay time
H
L
High
Low
V
X
Z
Valid
fall time
Unknown, changing, or don't care level
High impedance
h
r
hold time
rise time
su
t
setup time
transition time
valid time
v
w
pulse duration (width)
7.9.1.1 General Notes on Timing Parameters
All output signals from the 28x devices (including XCLKOUT) are derived from an internal clock such that all
output transitions for a given half-cycle occur with a minimum of skewing relative to each other.
The signal combinations shown in the following timing diagrams may not necessarily represent actual cycles. For
actual cycle examples, see the appropriate cycle description section of this document.
7.9.1.2 Test Load Circuit
This test load circuit is used to measure all switching characteristics provided in this document.
Tester Pin Electronics
Data Sheet Timing Reference Point
Output
Under
Test
42 Ω
3.5 nH
Transmission Line
(Α)
Z0 = 50 Ω
(B)
Device Pin
4.0 pF
1.85 pF
A. Input requirements in this data sheet are tested with an input slew rate of < 4 Volts per nanosecond (4 V/ns) at the device pin.
B. The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its transmission line effects
must be taken into account. A transmission line with a delay of 2 ns or longer can be used to produce the desired transmission line
effect. The transmission line is intended as a load only. It is not necessary to add or subtract the transmission line delay (2 ns or longer)
from the data sheet timing.
Figure 7-2. 3.3-V Test Load Circuit
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7.9.1.3 Device Clock Table
This section provides the timing requirements and switching characteristics for the various clock options
available. Section 7.9.1.3.1 and Section 7.9.1.3.2 list the cycle times of various clocks.
7.9.1.3.1 Clocking and Nomenclature (300-MHz Devices)
MIN
33.3
8
NOM
MAX UNIT
tc(OSC), Cycle time
Frequency
125
30
ns
MHz
ns
On-chip oscillator clock (crystal/resonator–X1/X2)
tc(CI), Cycle time (C8)
Frequency
6.67
2
50
PLL enabled
150
250
150
50
MHz
ns
XCLKIN(5)
tc(CI), Cycle time (C8)
Frequency
6.67
4
PLL disabled
PLL enabled
PLL disabled
MHz
ns
tc(CI), Cycle time (C8)
Frequency
10
2
100
250
100
500
300
2000
75(4)
MHz
ns
X1(5)
tc(CI), Cycle time (C8)
Frequency
10
4
MHz
ns
tc(SCO), Cycle time
Frequency
3.33
2
SYSCLKOUT
MHz
ns
tc(XCO), Cycle time
Frequency
13.3
0.5
25
XCLKOUT
MHz
ns
tc(HCO), Cycle time
Frequency
HSPCLK/EXTADCCLK(2)
LSPCLK(1)
40
MHz
ns
tc(LCO), Cycle time
Frequency
6.67
13.3(3)
75(3)
150
MHz
(1) Lower LSPCLK and HSPCLK will reduce device power consumption.
(2) This frequency is limited by GPIO switching characteristics.
(3) This is the value if SYSCLKOUT = 300 MHz.
(4) Although the maximum XCLKOUT frequency is 75 MHz, this value may not be attainable depending on SYSCLKOUT and available
prescalers.
(5) The input clock frequency and PLLCR[DIV] values should be chosen such that the output frequency of the PLL(VCOCLK) lies between
400 MHz to 600 MHz.
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7.9.1.3.2 Clocking and Nomenclature (200-MHz Devices)
MIN
33.3
8
NOM
MAX UNIT
tc(OSC), Cycle time
Frequency
125
30
ns
MHz
ns
On-chip oscillator clock (crystal/resonator–X1/X2)
tc(CI), Cycle time (C8)
Frequency
6.67
2
50
PLL enabled
150
250
150
50
MHz
ns
XCLKIN(5)
tc(CI), Cycle time (C8)
Frequency
6.67
4
PLL disabled
MHz
ns
tc(CI), Cycle time (C8)
Frequency
10
2
PLL enabled
100
250
100
500
200
2000
75(4)
MHz
ns
X1(5)
tc(CI), Cycle time (C8)
Frequency
10
4
PLL disabled
MHz
ns
tc(SCO), Cycle time
Frequency
5
SYSCLKOUT
2
MHz
ns
tc(XCO), Cycle time
Frequency
13.3
0.5
8
XCLKOUT
MHz
ns
tc(HCO), Cycle time
Frequency
HSPCLK/EXTADCCLK(1)
40
MHz
ns
tc(LCO), Cycle time
Frequency
10
20(3)
50(3)
LSPCLK(2)
100
MHz
(1) This frequency is limited by GPIO switching characteristics.
(2) Lower LSPCLK and HSPCLK will reduce device power consumption.
(3) This is the value if SYSCLKOUT = 200 MHz.
(4) Although the maximum XCLKOUT frequency is 75 MHz, this value may not be attainable depending on SYSCLKOUT and available
prescalers.
(5) The input clock frequency and PLLCR[DIV] values should be chosen such that the output frequency of the PLL(VCOCLK) lies between
400 MHz to 600 MHz.
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7.9.2 Power Sequencing
No special requirements are placed on the power up/down sequence of the various power pins to ensure the
correct reset state for all the modules. However, if the 3.3-V transistors in the level shifting output buffers of the
I/O pins are powered prior to the 1.1-V/1.2-V transistors, it is possible for the output buffers to turn on, causing a
glitch to occur on the pin during power up. To avoid this behavior, power the VDD pins prior to or simultaneously
with the VDDIO pins, ensuring that the VDD pins have reached 0.7-V before the VDDIO pins reach 0.7 V. The 1.8-V
rail for the PLL and oscillator logic can be powered up along with VDD/VDDIO rails. The 1.8-V rail must be
powered even if the PLL is not used. It should never be left unpowered. In any configuration, all the rails should
ramp up within tpup (5 ms, typical) to allow early stability of clocks and IOs.
There is a requirement on the XRS pin:
•
During power up, the XRS pin must be held low for tw(RSL1) after the input clock is stable. This is to enable the
entire device to start from a known condition.
No voltage larger than a diode drop (0.7 V) above VDDIO should be applied to any digital pin before powering up
the device. Voltages applied to pins on an unpowered device can bias internal P-N junctions in unintended ways
and produce unpredictable results.
7.9.2.1 Power Management and Supervisory Circuit Solutions
LDO selection depends on the total power consumed in the end application. Go to the Power Management page
for a list of TI power management ICs. Click the Reference designs tab for specific power management
reference designs.
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VDDIO (3.3 V)
VDD18 (1.8 V)
VDD (1.2 V/1.1 V)
tpup
XCLKIN
X1/X2
(A)
OSCCLK/16
OSCCLK/64
XCLKOUT
User-Code Dependent
t
OSCST
t
w(RSL1)
XRS
Address/Data Valid. Internal Boot-ROM Code Execution Phase
Address/Data/
Control
(Internal)
User-Code Execution Phase
User-Code Dependent
t
d(EX)
(B)
h(boot-mode)
t
Boot-Mode
Pins
GPIO Pins as Input
Boot-ROM Execution Starts
Peripheral/GPIO Function
Based on Boot Code
(C)
GPIO Pins as Input (State Depends on Internal PU/PD)
User-Code Dependent
I/O Pins
A. Upon power up, SYSCLKOUT is OSCCLK/8. Because the XTIMCLK, CLKMODE, and BY4CLKMODE bits in the XINTFCNF2 register
come up with a reset state of 1, SYSCLKOUT is further divided by 8 before it applies to XCLKOUT. This explains why XCLKOUT =
OSCCLK/64 during this phase. Subsequently, boot ROM changes SYSCLKOUT to OSCLK/2. Because the XTIMCLK register is
unchanged by the boot ROM, XCLKOUT is OSCCLK/16 during this phase.
B. After reset, the boot ROM code samples Boot Mode pins. Based on the status of the Boot Mode pin, the boot code branches to
destination memory or boot code function. If boot ROM code executes after power-on conditions (in debugger environment), the boot
code execution time is based on the current SYSCLKOUT speed. The SYSCLKOUT will be based on user environment and could be
with or without PLL enabled.
C. See Section 7.9.2 for requirements to ensure a high-impedance state for GPIO pins during power up.
Figure 7-3. Power-on Reset
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7.9.2.2 Reset ( XRS) Timing Requirements
MIN
64tc(OSCCLK)
64tc(OSCCLK)
NOM
MAX UNIT
(1)
tw(RSL1)
tw(RSL2)
Pulse duration, stable input clock to XRS high
Pulse duration, XRS low
cycles
cycles
Warm reset
Pulse duration, reset pulse generated by
watchdog
tw(WDRS)
td(EX)
512tc(OSCCLK)
cycles
Delay time, address/data valid after XRS high
Oscillator start-up time
32tc(OSCCLK)
10
cycles
ms
(2)
tOSCST
th(boot-mode)
tpup
1
Hold time for boot-mode pins
Power-up time
200tc(OSCCLK)
cycles
ms
5
(1) In addition to the tw(RSL1) requirement, XRS must be low until VDD has reached the minimum operating voltage.
(2) Dependent on crystal/resonator and board design.
XCLKIN
X1/X2
OSCCLK/8
XCLKOUT
XRS
User-Code Dependent
OSCCLK * 5
t
w(RSL2)
User-Code Execution Phase
t
d(EX)
Address/Data/
Control
(Internal)
(Don’t Care)
User-Code Execution
(A)
t
Boot-ROM Execution Starts
GPIO Pins as Input
h(boot-mode)
Boot-Mode
Pins
Peripheral/GPIO Function
User-Code Dependent
Peripheral/GPIO Function
User-Code Execution Starts
I/O Pins
GPIO Pins as Input (State Depends on Internal PU/PD)
User-Code Dependent
A. After reset, the Boot ROM code samples BOOT Mode pins. Based on the status of the Boot Mode pin, the boot code branches to
destination memory or boot code function. If Boot ROM code executes after power-on conditions (in debugger environment), the Boot
code execution time is based on the current SYSCLKOUT speed. The SYSCLKOUT will be based on user environment and could be
with or without PLL enabled.
Figure 7-4. Warm Reset
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Figure 7-5 shows an example for the effect of writing into PLLCR register. In the first phase, PLLCR = 0x0003
and SYSCLKOUT = OSCCLK × 2. The PLLCR is then written with 0x0007 (setting for OSCCLK × 8). Right after
the PLLCR register is written, the PLL lock-up phase begins. During this phase, SYSCLKOUT = OSCCLK/2.
After the PLL lock-up is complete (which takes 2600 OSCCLK cycles), SYSCLKOUT reflects the new operating
frequency, OSCCLK × 4.
OSCCLK
Write to PLLCR
SYSCLKOUT
OSCCLK * 2
OSCCLK/2
OSCCLK * 4
(Current CPU
Frequency)
(CPU Frequency While PLL is Stabilizing
With the Desired Frequency. This Period
(PLL Lock-up Time, t ) is
(Changed CPU Frequency)
p
2600 OSCCLK Cycles Long.)
Figure 7-5. Example of Effect of Writing Into PLLCR Register
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MAX UNIT
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7.9.3 Clock Requirements and Characteristics
7.9.3.1 XCLKIN/X1 Timing Requirements – PLL Enabled
NO.
MIN
C9
tf(CI)
Fall time, XCLKIN(1)
4
4
ns
ns
C10 tr(CI)
Rise time, XCLKIN(1)
(1)
C11 tw(CIL)
C12 tw(CIH)
Pulse duration, XCLKIN low as a percentage of tc(OSCCLK)
40%
40%
60%
60%
(1)
Pulse duration, XCLKIN high as a percentage of tc(OSCCLK)
(1) This applies to the X1 pin also.
7.9.3.2 XCLKIN/X1 Timing Requirements – PLL Disabled
NO.
MIN
MAX UNIT
C9 tf(CI)
C10 tr(CI)
C11 tw(CIL)
C12 tw(CIH)
Fall time, XCLKIN(1)
2
2
ns
ns
Rise time, XCLKIN(1)
(1)
Pulse duration, XCLKIN low as a percentage of tc(OSCCLK)
Pulse duration, XCLKIN high as a percentage of tc(OSCCLK)
45%
45%
55%
55%
(1)
(1) This applies to the X1 pin also.
The possible configuration modes are shown in Table 8-34.
7.9.3.3 XCLKOUT Switching Characteristics (PLL Bypassed or Enabled) (1) (2)
NO.
PARAMETER
Cycle time, XCLKOUT
MIN
TYP
MAX UNIT
C1 tc(XCO)
C3 tf(XCO)
C4 tr(XCO)
C5 tw(XCOL)
C6 tw(XCOH)
tp
13.3
ns
ns
ns
Fall time, XCLKOUT
2
2
Rise time, XCLKOUT
Pulse duration, XCLKOUT low
Pulse duration, XCLKOUT high
PLL lock time
H – 2
H – 2
H + 2
ns
ns
H + 2
(3)
2600tc(OSCCLK)
cycles
(1) A load of 40 pF is assumed for these parameters.
(2) H = 0.5tc(XCO)
(3) OSCCLK is either the output of the on-chip oscillator or the output from an external oscillator.
7.9.3.4 Timing Diagram
C10
C9
C8
(A)
XCLKIN
C6
C3
C1
C4
C5
(B)
XCLKOUT
A. The relationship of XCLKIN to XCLKOUT depends on the divide factor chosen. The waveform relationship shown is intended to illustrate
the timing parameters only and may differ based on actual configuration.
B. XCLKOUT configured to reflect SYSCLKOUT.
Figure 7-6. Clock Timing
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7.9.4 Peripherals
7.9.4.1 General-Purpose Input/Output (GPIO)
7.9.4.1.1 GPIO - Output Timing
7.9.4.1.1.1 General-Purpose Output Switching Characteristics
PARAMETER
MIN
MAX
11
UNIT
ns
tr(GPO)
tf(GPO)
tfGPO
Rise time, GPIO switching low to high
Fall time, GPIO switching high to low
Toggling frequency, GPO pins
All GPIOs
All GPIOs
11
ns
40
MHz
GPIO
t
r(GPO)
t
f(GPO)
Figure 7-7. General-Purpose Output Timing
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7.9.4.1.2 GPIO - Input Timing
7.9.4.1.2.1 General-Purpose Input Timing Requirements
MIN
1tc(SCO)
MAX
UNIT
cycles
cycles
cycles
QUALPRD = 0
tw(SP)
Sampling period
QUALPRD ≠ 0
2tc(SCO) * QUALPRD
tw(SP) * (n(1) – 1)
2tc(SCO)
tw(IQSW)
Input qualifier sampling window
Pulse duration, GPIO low/high
Synchronous mode
With input qualifier
(2)
tw(GPI)
tw(IQSW) + tw(SP) + 1tc(SCO)
(1) "n" represents the number of qualification samples as defined by GPxQSELn register.
(2) For tw(GPI), pulse width is measured from VIL to VIL for an active low signal and VIH to VIH for an active high signal.
(A)
GPIO Signal
GPxQSELn = 1,0 (6 samples)
1
1
0
0
0
0
0
0
0
1
0
0
0
1
1
1
1
1
1
1
1
1
t
Sampling Period determined
(B)
w(SP)
by GPxCTRL[QUALPRD]
t
w(IQSW)
(C)
(SYSCLKOUT cycle * 2 * QUALPRD) * 5
)
Sampling Window
SYSCLKOUT
QUALPRD = 1
(SYSCLKOUT/2)
(D)
Output From
Qualifier
A. This glitch will be ignored by the input qualifier. The QUALPRD bit field specifies the qualification sampling period. It can vary from 00 to
0xFF. If QUALPRD = 00, then the sampling period is 1 SYSCLKOUT cycle. For any other value "n", the qualification sampling period in
2n SYSCLKOUT cycles (that is, at every 2n SYSCLKOUT cycles, the GPIO pin will be sampled).
B. The qualification period selected through the GPxCTRL register applies to groups of 8 GPIO pins.
C. The qualification block can take either three or six samples. The GPxQSELn Register selects which sample mode is used.
D. In the example shown, for the qualifier to detect the change, the input should be stable for 10 SYSCLKOUT cycles or greater. In other
words, the inputs should be stable for (5 × QUALPRD × 2) SYSCLKOUT cycles. This would ensure 5 sampling periods for detection to
occur. Because external signals are driven asynchronously, an 13-SYSCLKOUT-wide pulse ensures reliable recognition.
Figure 7-8. Sampling Mode
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7.9.4.1.3 Sampling Window Width for Input Signals
The following section summarizes the sampling window width for input signals for various input qualifier
configurations.
Sampling frequency denotes how often a signal is sampled with respect to SYSCLKOUT.
Sampling frequency = SYSCLKOUT/(2 * QUALPRD), if QUALPRD ≠ 0
Sampling frequency = SYSCLKOUT, if QUALPRD = 0
Sampling period = SYSCLKOUT cycle × 2 × QUALPRD, if QUALPRD ≠ 0
In the above equations, SYSCLKOUT cycle indicates the time period of SYSCLKOUT.
Sampling period = SYSCLKOUT cycle, if QUALPRD = 0
In a given sampling window, either 3 or 6 samples of the input signal are taken to determine the validity of the
signal. This is determined by the value written to GPxQSELn register.
Case 1:
Qualification using three samples
Sampling window width = (SYSCLKOUT cycle × 2 × QUALPRD) × 2, if QUALPRD ≠ 0
Sampling window width = (SYSCLKOUT cycle) × 2, if QUALPRD = 0
Case 2:
Qualification using six samples
Sampling window width = (SYSCLKOUT cycle × 2 × QUALPRD) × 5, if QUALPRD ≠ 0
Sampling window width = (SYSCLKOUT cycle) × 5, if QUALPRD = 0
SYSCLK
GPIOxn
tw(GPI)
Figure 7-9. General-Purpose Input Timing
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7.9.4.1.4 Low-Power Mode Wakeup Timing
The wakeup signal fed to a GPIO pin to wake up the device must meet the minimum pulse width requirement.
Furthermore, this signal must be free of glitches. If a noisy signal is fed to a GPIO pin, the wakeup behavior of
the device will not be deterministic and the device may not exit low-power mode for subsequent wakeup pulses.
Section 7.9.4.1.4.1 shows the timing requirements, Section 7.9.4.1.4.2 shows the switching characteristics, and
Figure 7-10 shows the timing diagram for IDLE mode.
7.9.4.1.4.1 IDLE Mode Timing Requirements (1)
MIN
2tc(SCO)
MAX
UNIT
Without input qualifier
With input qualifier
tw(WAKE-INT)
Pulse duration, external wake-up signal
cycles
5tc(SCO) + tw(IQSW)
(1) For an explanation of the input qualifier parameters, see Section 7.9.4.1.2.1.
7.9.4.1.4.2 IDLE Mode Switching Characteristics (1)
PARAMETER
TEST CONDITIONS
Without input qualifier
With input qualifier
MIN
MAX
UNIT
Delay time, external wake signal to
program execution resume (2)
20tc(SCO)
td(WAKE-IDLE)
cycles
20tc(SCO) + tw(IQSW)
•
Wake-up from SARAM
(1) For an explanation of the input qualifier parameters, see Section 7.9.4.1.2.1.
(2) This is the time taken to begin execution of the instruction that immediately follows the IDLE instruction. execution of an ISR (triggered
by the wake up) signal involves additional latency.
7.9.4.1.4.3 IDLE Mode Timing Diagram
t
d(WAKE−IDLE)
Address/Data
(internal)
XCLKOUT
t
w(WAKE−INT)
(A)
WAKE INT
A. WAKE INT can be any enabled interrupt, WDINT, XNMI, or XRS.
Figure 7-10. IDLE Entry and Exit Timing
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7.9.4.1.4.4 STANDBY Mode Timing Requirements
MIN
3tc(OSCCLK)
MAX
UNIT
Without input qualification
With input qualification(1)
Pulse duration, external
wake-up signal
tw(WAKE-INT)
cycles
(2 + QUALSTDBY) * tc(OSCCLK)
(1) QUALSTDBY is a 6-bit field in the LPMCR0 register.
7.9.4.1.4.5 STANDBY Mode Switching Characteristics
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
Delay time, IDLE instruction
executed to XCLKOUT low
td(IDLE-XCOL)
32tc(SCO)
45tc(SCO)
cycles
Delay time, external wake signal to Without input qualifier
program execution resume(1)
100tc(SCO)
td(WAKE-STBY)
cycles
With input qualifier
100tc(SCO) + tw(WAKE-INT)
•
Wake up from SARAM
(1) This is the time taken to begin execution of the instruction that immediately follows the IDLE instruction. execution of an ISR (triggered
by the wake up signal) involves additional latency.
7.9.4.1.4.6 STANDBY Mode Timing Diagram
(A)
(C)
(E)
(D)
(B)
(F)
Device
Status
STANDBY
STANDBY
Normal Execution
Flushing Pipeline
Wake-up
Signal
t
w(WAKE-INT)
t
d(WAKE-STBY)
X1/X2 or
X1 or
XCLKIN
XCLKOUT
t
d(IDLE−XCOL)
A. IDLE instruction is executed to put the device into STANDBY mode.
B. The PLL block responds to the STANDBY signal. SYSCLKOUT is held for 32 cycles before being turned off. This delay enables the CPU
pipeline and any other pending operations to flush properly. If an access to XINTF is in progress and its access time is longer than this
number then it will fail. TI recommends entering STANDBY mode from SARAM without an XINTF access in progress.
C. Clock to the peripherals are turned off. However, the PLL and watchdog are not shut down. The device is now in STANDBY mode.
D. The external wake-up signal is driven active.
E. After a latency period, the STANDBY mode is exited.
F. Normal execution resumes. The device will respond to the interrupt (if enabled).
Figure 7-11. STANDBY Entry and Exit Timing Diagram
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7.9.4.1.4.7 HALT Mode Timing Requirements
MIN
MAX
UNIT
cycles
cycles
(1)
tw(WAKE-GPIO)
tw(WAKE-XRS)
Pulse duration, GPIO wake-up signal
Pulse duration, XRS wakeup signal
toscst + 2tc(OSCCLK)
toscst + 8tc(OSCCLK)
(1) See Section 7.9.2.2 for an explanation of toscst
.
7.9.4.1.4.8 HALT Mode Switching Characteristics
PARAMETER
MIN
32tc(SCO)
MAX
45tc(SCO)
UNIT
cycles
cycles
td(IDLE-XCOL)
tp
Delay time, IDLE instruction executed to XCLKOUT low
PLL lock-up time
2600tc(OSCCLK)
Delay time, PLL lock to program execution resume
td(WAKE-HALT)
35tc(SCO)
cycles
•
Wake up from SARAM
7.9.4.1.4.9 HALT Mode Timing Diagram
(H)
(A)
(C)
(F)
(E)
(B)
(D)
(G)
Device
Status
HALT
HALT
Flushing Pipeline
PLL Lock-up Time
Normal
Execution
Wake-up Latency
GPIOn
t
d(WAKE−HALT)
t
w(WAKE-GPIO)
t
p
X1/X2
or XCLKIN
Oscillator Start-up Time
XCLKOUT
t
d(IDLE−XCOL)
A. IDLE instruction is executed to put the device into HALT mode.
B. The PLL block responds to the HALT signal. SYSCLKOUT is held for 32 cycles before oscillator is turned off and the CLKIN to the core is
stopped. This delay enables the CPU pipeline and any other pending operations to flush properly. If an access to XINTF is in progress
and its access time is longer than this number then it will fail. It is recommended to enter HALT mode from SARAM without an XINTF
access in progress.
C. Clocks to the peripherals are turned off and the PLL is shut down. If a quartz crystal or ceramic resonator is used as the clock source,
the internal oscillator is shut down as well. The device is now in HALT mode and consumes absolute minimum power.
D. When the GPIOn pin (used to bring the device out of HALT) is driven low, the oscillator is turned on and the oscillator wake-up sequence
is initiated. The GPIO pin should be driven high only after the oscillator has stabilized. This enables the provision of a clean clock signal
during the PLL lock sequence. Because the falling edge of the GPIO pin asynchronously begins the wakeup process, care should be
taken to maintain a low noise environment prior to entering and during HALT mode.
E. The wake-up signal fed to a GPIO pin to wake up the device must meet the minimum pulse width requirement. Furthermore, this signal
must be free of glitches. If a noisy signal is fed to a GPIO pin, the wake-up behavior of the device will not be deterministic and the device
may not exit low-power mode for subsequent wake-up pulses.
F. Once the oscillator has stabilized, the PLL lock sequence is initiated, which takes 2,600 OSCCLK (X1/X2 or X1 or XCLKIN) cycles.
G. Clocks to the core and peripherals are enabled. The HALT mode is now exited. The device will respond to the interrupt (if enabled), after
a latency.
H. Normal operation resumes.
Figure 7-12. HALT Wakeup Using GPIOn
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7.9.4.2 Enhanced Control Peripherals
7.9.4.2.1 Enhanced Pulse Width Modulator (ePWM) Timing
PWM refers to PWM outputs on ePWM1–6. Section 7.9.4.2.1.1 shows the ePWM timing requirements and
Section 7.9.4.2.1.2, ePWM switching characteristics.
7.9.4.2.1.1 ePWM Timing Requirements (1)
MIN
2tc(SCO)
MAX
UNIT
Asynchronous
Synchronous
tw(SYCIN)
Sync input pulse width
2tc(SCO)
cycles
With input qualifier
1tc(SCO) + tw(IQSW)
(1) For an explanation of the input qualifier parameters, see Section 7.9.4.1.2.1.
7.9.4.2.1.2 ePWM Switching Characteristics
PARAMETER
TEST CONDITIONS
MIN
20
MAX
UNIT
ns
tw(PWM)
Pulse duration, PWMx output high/low
Sync output pulse width
tw(SYNCOUT)
8tc(SCO)
cycles
Delay time, trip input active to PWM forced high
Delay time, trip input active to PWM forced low
td(PWM)tza
no pin load
25
20
ns
ns
td(TZ-PWM)HZ
Delay time, trip input active to PWM Hi-Z
7.9.4.2.2 Trip-Zone Input Timing
SYSCLK
tw(TZ)
TZ(A)
td(TZ-PWM)HZ
PWM(B)
A. TZ - TZ1, TZ2, TZ3, TZ4, TZ5, TZ6
B. PWM refers to all the PWM pins in the device. The state of the PWM pins after TZ is taken high depends on the PWM recovery software.
Figure 7-13. PWM Hi-Z Characteristics
7.9.4.2.2.1 Trip-Zone Input Timing Requirements (1)
MIN
1tc(SCO)
MAX UNIT
Asynchronous
Synchronous
tw(TZ)
Pulse duration, TZx input low
2tc(SCO)
cycles
With input qualifier
1tc(SCO) + tw(IQSW)
(1) For an explanation of the input qualifier parameters, see Section 7.9.4.1.2.1.
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7.9.4.2.3 High-Resolution PWM Timing
Section 7.9.4.2.3.1 shows the high-resolution PWM switching characteristics.
7.9.4.2.3.1 High-Resolution PWM Characteristics at SYSCLKOUT = (150–300 MHz)
MIN
TYP
55
MAX UNIT
VDD = 1.2 V
120
140
ps
ps
Micro Edge Positioning (MEP) step size(1)
VDD = 1.1 V
65
(1) The MEP step size will be largest at high temperature and minimum voltage on VDD. MEP step size will increase with higher
temperature and lower voltage and decrease with lower temperature and higher voltage.
Applications that use the HRPWM feature should use MEP Scale Factor Optimizer (SFO) estimation software functions. See the TI
software libraries for details of using SFO function in end applications. SFO functions help to estimate the number of MEP steps per
SYSCLKOUT period dynamically while the HRPWM is in operation.
7.9.4.2.4 Enhanced Capture (eCAP) Timing
Section 7.9.4.2.4.1 shows the eCAP timing requirement and Section 7.9.4.2.4.2 shows the eCAP switching
characteristics.
7.9.4.2.4.1 Enhanced Capture (eCAP) Timing Requirements (1)
MIN
2tc(SCO)
MAX UNIT
Asynchronous
Synchronous
tw(CAP)
Capture input pulse width
2tc(SCO)
cycles
With input qualifier
1tc(SCO) + tw(IQSW)
(1) For an explanation of the input qualifier parameters, see Section 7.9.4.1.2.1.
7.9.4.2.4.2 eCAP Switching Characteristics
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
tw(APWM)
Pulse duration, APWMx output high/low
20
ns
7.9.4.2.5 Enhanced Quadrature Encoder Pulse (eQEP) Timing
Section 7.9.4.2.5.1 shows the eQEP timing requirement and Section 7.9.4.2.5.2 shows the eQEP switching
characteristics.
7.9.4.2.5.1 Enhanced Quadrature Encoder Pulse (eQEP) Timing Requirements (1)
MIN
MAX
UNIT
Asynchronous(2)/synchronous
With input qualifier
2tc(SCO)
tw(QEPP)
QEP input period
cycles
2[1tc(SCO) + tw(IQSW)
]
Asynchronous(2)/synchronous
2tc(SCO)
2tc(SCO) + tw(IQSW)
2tc(SCO)
tw(INDEXH)
tw(INDEXL)
tw(STROBH)
tw(STROBL)
QEP Index Input High time
QEP Index Input Low time
QEP Strobe High time
QEP Strobe Input Low time
cycles
cycles
cycles
cycles
With input qualifier
Asynchronous(2)/synchronous
With input qualifier
2tc(SCO) + tw(IQSW)
2tc(SCO)
2tc(SCO) + tw(IQSW)
2tc(SCO)
Asynchronous(2)/synchronous
With input qualifier
Asynchronous(2)/synchronous
With input qualifier
2tc(SCO) + tw(IQSW)
(1) For an explanation of the input qualifier parameters, see Section 7.9.4.1.2.1.
(2) Refer to the TMS320C2834x Delfino™ MCUs Silicon Errata for limitations in the asynchronous mode.
7.9.4.2.5.2 eQEP Switching Characteristics
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
td(CNTR)xin
Delay time, external clock to counter increment
4tc(SCO)
cycles
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PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
Delay time, QEP input edge to position compare sync
output
td(PCS-OUT)QEP
6tc(SCO)
cycles
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7.9.4.2.6 ADC Start-of-Conversion Timing
7.9.4.2.6.1 External ADC Start-of-Conversion Switching Characteristics
PARAMETER
MIN
MAX
UNIT
tw(ADCSOCL)
Pulse duration, ADCSOCxO low
32tc(HCO )
cycles
7.9.4.2.6.2 ADCSOCAO or ADCSOCBO Timing
t
w(ADCSOCL)
ADCSOCAO
or
ADCSOCBO
Figure 7-14. ADCSOCAO or ADCSOCBO Timing
7.9.4.3 External Interrupt Timing
7.9.4.3.1 External Interrupt Timing Requirements (1)
MIN
1tc(SCO)
MAX
UNIT
Synchronous
With qualifier
(2)
tw(INT)
Pulse duration, INT input low/high
cycles
1tc(SCO) + tw(IQSW)
(1) For an explanation of the input qualifier parameters, see Section 7.9.4.1.2.1.
(2) This timing is applicable to any GPIO pin configured for ADCSOC functionality.
7.9.4.3.2 External Interrupt Switching Characteristics (1)
PARAMETER
MIN
MAX
tw(IQSW) + 12tc(SCO)
UNIT
td(INT)
Delay time, INT low/high to interrupt-vector fetch
cycles
(1) For an explanation of the input qualifier parameters, see Section 7.9.4.1.2.1.
7.9.4.3.3 External Interrupt Timing Diagram
t
w(INT)
XNMI, XINT1, XINT2
t
d(INT)
Address bus
(internal)
Interrupt Vector
Figure 7-15. External Interrupt Timing
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7.9.4.4 I2C Electrical Specification and Timing
7.9.4.4.1 I2C Timing
TEST CONDITIONS
MIN
MAX
400
UNIT
I2C clock module frequency is between
7 MHz and 12 MHz and I2C prescaler and
clock divider registers are configured
appropriately
fSCL
SCL clock frequency
kHz
vil
Low level input voltage
High level input voltage
Input hysteresis
0.3 VDDIO
V
V
V
V
Vih
Vhys
Vol
0.7 VDDIO
0.05 VDDIO
0
Low level output voltage
3-mA sink current
0.4
I2C clock module frequency is between
7 MHz and 12 MHz and I2C prescaler and
clock divider registers are configured
appropriately
tLOW
Low period of SCL clock
High period of SCL clock
1.3
μs
I2C clock module frequency is between
7 MHz and 12 MHz and I2C prescaler and
clock divider registers are configured
appropriately
tHIGH
0.6
μs
Input current with an input voltage
between 0.1 VDDIO and 0.9 VDDIO MAX
lI
–10
10
μA
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7.9.4.5 Serial Peripheral Interface (SPI) Timing
This section contains both Master Mode and Slave Mode timing data.
7.9.4.5.1 Master Mode Timing
Section 7.9.4.5.1.1 lists the master mode timing (clock phase = 0) and Section 7.9.4.5.1.2 lists the master mode
timing (clock phase = 1). Figure 7-16 and Figure 7-17 show the timing waveforms.
7.9.4.5.1.1 SPI Master Mode External Timing (Clock Phase = 0) (1) (2) (3) (4) (5)
BRR EVEN
MIN
BRR ODD
MIN
NO.
PARAMETER
UNIT
MAX
MAX
1
2
tc(SPC)M
Cycle time, SPICLK
4tc(LSPCLK)
128tc(LSPCLK)
5tc(LSPCLK)
127tc(LSPCLK)
ns
ns
Pulse duration, SPICLK first
pulse
0.5tc(SPC)M + 0.5tc(LSPCLK)
– 10
0.5tc(SPC)M
+
tw(SPC1)M
0.5tc(SPC)M – 10
0.5tc(SPC)M + 10
0.5tc(SPC)M + 10
10
0.5tc(LSPCLK) + 10
Pulse duration, SPICLK second
pulse
0.5tc(SPC)M – 0.5tc(LSPCLK)
– 10
0.5tc(SPC)M
–
3
4
tw(SPC2)M
td(SIMO)M
tv(SIMO)M
tsu(SOMI)M
th(SOMI)M
td(SPC)M
td(STE)M
0.5tc(SPC)M – 10
ns
ns
ns
ns
ns
ns
ns
0.5tc(LSPCLK) + 10
Delay time, SPICLK to
SPISIMO valid
10
Valid time, SPISIMO valid after
SPICLK
0.5tc(SPC)M – 0.5tc(LSPCLK)
– 10
5
0.5tc(SPC)M – 10
Setup time, SPISOMI before
SPICLK
8
20
0
20
0
Hold time, SPISOMI valid after
SPICLK
9
Delay time, SPISTE active to
SPICLK
0.5tc(SPC)M –
0.5tc(LSPCLK) – 10
23
24
tc(SPC)M – 10
0.5tc(SPC)M – 10
Delay time, SPICLK to SPISTE
inactive
0.5tc(SPC)M – 0.5tc(LSPCLK)
– 10
(1) The MASTER / SLAVE bit (SPICTL.2) is set and the CLOCK PHASE bit (SPICTL.3) is cleared.
(2) tc(SPC) = SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR +1)
(3) tc(LCO) = LSPCLK cycle time
(4) Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate:
Master mode transmit 25-MHz MAX, master mode receive 12.5-MHz MAX
Slave mode transmit 12.5-MAX, slave mode receive 12.5-MHz MAX.
(5) The active edge of the SPICLK signal referenced is controlled by the clock polarity bit (SPICCR.6).
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1
SPICLK
(clock polarity = 0)
2
3
SPICLK
(clock polarity = 1)
4
5
SPISIMO
Master Out Data Is Valid
8
9
Master In Data
Must Be Valid
SPISOMI
SPISTE
24
23
Figure 7-16. SPI Master Mode External Timing (Clock Phase = 0)
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UNIT
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7.9.4.5.1.2 SPI Master Mode External Timing (Clock Phase = 1) (1) (2) (3) (4) (5)
BRR EVEN
BRR ODD
MIN
NO.
PARAMETER
MIN
MAX
MAX
127tc(LSPCLK)
0.5tc(SPC)M –
1
2
tc(SPC)M
Cycle time, SPICLK
4tc(LSPCLK)
128tc(LSPCLK)
5tc(LSPCLK)
ns
ns
Pulse duration, SPICLK first
pulse
0.5tc(SPC)M
–
tw(SPC1)M
0.5tc(SPC)M – 10
0.5tc(SPC)M – 10
0.5tc(SPC)M – 10
0.5tc(SPC)M – 10
20
0.5tc(SPC)M + 10
0.5tc(SPC)M + 10
0.5tc(LSPCLK) – 10
0.5tc(LSPCLK) + 10
Pulse duration, SPICLK second
pulse
0.5tc(SPC)M
+
0.5tc(SPC)M
0.5tc(LSPCLK) + 10
+
3
6
tw(SPC2)M
td(SIMO)M
tv(SIMO)M
tsu(SOMI)M
th(SOMI)M
td(SPC)M
td(STE)M
ns
ns
ns
ns
ns
ns
ns
0.5tc(LSPCLK) – 10
Delay time, SPISIMO valid to
SPICLK
0.5tc(SPC)M
+
0.5tc(LSPCLK) – 10
Valid time, SPISIMO valid after
SPICLK
0.5tc(SPC)M
–
7
0.5tc(LSPCLK) – 10
Setup time, SPISOMI before
SPICLK
10
11
23
24
20
Hold time, SPISOMI valid after
SPICLK
0
0
Delay time, SPISTE active to
SPICLK
tc(SPC) – 10
0.5tc(SPC) – 10
tc(SPC) – 10
Delay time, SPICLK to SPISTE
inactive
0.5tc(SPC)
–
0.5tc(LSPCLK) – 10
(1) The MASTER/SLAVE bit (SPICTL.2) is set and the CLOCK PHASE bit (SPICTL.3) is set.
(2) tc(SPC) = SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR + 1)
(3) Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate:
Master mode transmit 25 MHz MAX, master mode receive 12.5 MHz MAX
Slave mode transmit 12.5 MHz MAX, slave mode receive 12.5 MHz MAX.
(4) tc(LCO) = LSPCLK cycle time
(5) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).
1
SPICLK
(clock polarity = 0)
2
3
SPICLK
(clock polarity = 1)
6
7
SPISIMO
Master Out Data Is Valid
10
11
Master In Data Must
Be Valid
SPISOMI
SPISTE
24
23
Figure 7-17. SPI Master Mode External Timing (Clock Phase = 1)
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7.9.4.5.2 Slave Mode Timing
Section 7.9.4.5.2.1 lists the slave mode timing (clock phase = 0) and Section 7.9.4.5.2.2 lists the slave mode
timing (clock phase = 1). Figure 7-18 and Figure 7-19 show the timing waveforms.
7.9.4.5.2.1 SPI Slave Mode External Timing (Clock Phase = 0) (1) (2) (4) (3) (5)
NO.
PARAMETER
Cycle time, SPICLK
MIN
4tc(SYSCLK)
MAX UNIT
12 tc(SPC)S
13 tw(SPC1)S
14 tw(SPC2)S
15 td(SOMI)S
16 tv(SOMI)S
19 tsu(SIMO)S
20 th(SIMO)S
25 tsu(STE)S
26 th(STE)S
ns
ns
ns
Pulse duration, SPICLK first pulse
2tc(SYSCLK) – 1
2tc(SYSCLK) – 1
Pulse duration, SPICLK second pulse
Delay time, SPICLK to SPISOMI valid
Valid time, SPISOMI data valid after SPICLK
Setup time, SPISIMO valid before SPICLK
Hold time, SPISIMO data valid after SPICLK
Setup time, SPISTE active before SPICLK
Hold time, SPISTE inactive after SPICLK
20
ns
ns
ns
ns
ns
ns
0
1.5tc(SYSCLK)
1.5tc(SYSCLK)
1.5tc(SYSCLK)
1.5tc(SYSCLK)
(1) The MASTER / SLAVE bit (SPICTL.2) is cleared and the CLOCK PHASE bit (SPICTL.3) is cleared.
(2) tc(SPC) = SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR + 1)
(3) tc(LCO) = LSPCLK cycle time
(4) Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate:
Master mode transmit 25-MHz MAX, master mode receive 12.5-MHz MAX
Slave mode transmit 12.5-MHz MAX, slave mode receive 12.5-MHz MAX.
(5) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).
12
SPICLK
(clock polarity = 0)
13
14
SPICLK
(clock polarity = 1)
15
16
SPISOMI
SPISOMI Data Is Valid
19
20
SPISIMO Data
Must Be Valid
SPISIMO
SPISTE
25
26
Figure 7-18. SPI Slave Mode External Timing (Clock Phase = 0)
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7.9.4.5.2.2 SPI Slave Mode External Timing (Clock Phase = 1) (1) (2) (3) (4)
NO.
PARAMETER
Cycle time, SPICLK
MIN
4tc(SYSCLK)
MAX UNIT
12 tc(SPC)S
13 tw(SPC1)S
14 tw(SPC2)S
17 td(SOMI)S
18 tv(SOMI)S
21 tsu(SIMO)S
22 th(SIMO)S
25 tsu(STE)S
26 th(STE)S
ns
ns
ns
ns
ns
ns
ns
ns
ns
Pulse duration, SPICLK first pulse
2tc(SYSCLK) – 1
2tc(SYSCLK) – 1
Pulse duration, SPICLK second pulse
Delay time, SPICLK to SPISOMI valid
Valid time, SPISOMI data valid after SPICLK
Setup time, SPISIMO valid before SPICLK
Hold time, SPISIMO data valid after SPICLK
Setup time, SPISTE active before SPICLK
Hold time, SPISTE inactive after SPICLK
20
0
1.5tc(SYSCLK)
1.5tc(SYSCLK)
1.5tc(SYSCLK)
1.5tc(SYSCLK)
(1) The MASTER / SLAVE bit (SPICTL.2) is cleared and the CLOCK PHASE bit (SPICTL.3) is cleared.
(2) tc(SPC) = SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR + 1)
(3) Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate:
Master mode transmit 25-MHz MAX, master mode receive 12.5-MHz MAX
Slave mode transmit 12.5-MHz MAX, slave mode receive 12.5-MHz MAX.
(4) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).
12
SPICLK
(clock polarity = 0)
13
14
SPICLK
(clock polarity = 1)
17
SPISOMI
SPISOMI Data Is Valid
Data Valid
Data Valid
18
21
22
SPISIMO Data
Must Be Valid
SPISIMO
SPISTE
26
25
Figure 7-19. SPI Slave Mode External Timing (Clock Phase = 1)
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SPRS516F – MARCH 2009 – REVISED FEBRUARY 2021
7.9.4.6 Multichannel Buffered Serial Port (McBSP) Timing
7.9.4.6.1 McBSP Transmit and Receive Timing
7.9.4.6.1.1 McBSP Timing Requirements (1) (2)
NO.
MIN
MAX UNIT
1
kHz
McBSP module clock (CLKG, CLKX, CLKR) range
40 (3)
MHz
ns
25
McBSP module cycle time (CLKG, CLKX, CLKR) range
1
ms
ns
M11 tc(CKRX)
M12 tw(CKRX)
M13 tr(CKRX)
M14 tf(CKRX)
Cycle time, CLKR/X
CLKR/X ext
CLKR/X ext
CLKR/X ext
CLKR/X ext
CLKR int
CLKR ext
CLKR int
CLKR ext
CLKR int
CLKR ext
CLKR int
CLKR ext
CLKX int
2P
Pulse duration, CLKR/X high or CLKR/X low
Rise time, CLKR/X
P – 4
ns
4
4
ns
Fall time, CLKR/X
ns
20
2
M15 tsu(FRH-CKRL)
M16 th(CKRL-FRH)
M17 tsu(DRV-CKRL)
M18 th(CKRL-DRV)
M19 tsu(FXH-CKXL)
M20 th(CKXL-FXH)
Setup time, external FSR high before CLKR low
Hold time, external FSR high after CLKR low
Setup time, DR valid before CLKR low
ns
ns
ns
ns
ns
ns
0
6
20
2
0
Hold time, DR valid after CLKR low
6
20
2
Setup time, external FSX high before CLKX low
Hold time, external FSX high after CLKX low
CLKX ext
CLKX int
0
CLKX ext
6
(1) Polarity bits CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that
signal are also inverted.
CLKSRG
(1 ) CLKGDV)
(2) 2P = 1/CLKG in ns. CLKG is the output of sample rate generator mux. CLKG =
CLKSRG can be LSPCLK, CLKX,
CLKR as source. CLKSRG ≤ (SYSCLKOUT/2). McBSP performance is limited by I/O buffer switching speed.
(3) Internal clock prescalers must be adjusted such that the McBSP clock (CLKG, CLKX, CLKR) speeds are not greater than the I/O buffer
speed limit (40 MHz).
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7.9.4.6.1.2 McBSP Switching Characteristics (1) (2)
NO.
M1
M2
M3
PARAMETER
Cycle time, CLKR/X
MIN
MAX UNIT
tc(CKRX)
CLKR/X int
CLKR/X int
CLKR/X int
CLKR int
CLKR ext
CLKX int
CLKX ext
CLKX int
CLKX ext
CLKX int
CLKX ext
CLKX int
CLKX ext
CLKX int
2P
ns
tw(CKRXH)
tw(CKRXL)
Pulse duration, CLKR/X high
Pulse duration, CLKR/X low
D – 2 (3)
D + 2 (3)
ns
ns
C – 2 (3)
C + 2 (3)
0
3
0
3
4
20
4
M4
M5
M6
td(CKRH-FRV)
td(CKXH-FXV)
tdis(CKXH-DXHZ)
Delay time, CLKR high to internal FSR valid
Delay time, CLKX high to internal FSX valid
ns
ns
ns
20
8
Disable time, CLKX high to DX high impedance
following last data bit
14
4
Delay time, CLKX high to DX valid.
This applies to all bits except the first bit transmitted.
20
4
Delay time, CLKX high to DX valid
DXENA = 0
M7
td(CKXH-DXV)
ns
ns
20
P + 4
Only applies to first bit transmitted when
in Data Delay 1 or 2 (XDATDLY=01b or DXENA = 1
10b) modes
CLKX ext
P + 20
CLKX int
CLKX ext
CLKX int
0
10
P
Enable time, CLKX high to DX driven
Only applies to first bit transmitted when
in Data Delay 1 or 2 (XDATDLY=01b or DXENA = 1
10b) modes
DXENA = 0
M8
M9
ten(CKXH-DX)
CLKX ext
P + 10
FSX int
FSX ext
FSX int
FSX ext
FSX int
FSX ext
FSX int
FSX ext
4
16
Delay time, FSX high to DX valid
DXENA = 0
DXENA = 1
DXENA = 0
DXENA = 1
td(FXH-DXV)
ns
ns
P + 4
P + 16
Only applies to first bit transmitted when
in Data Delay 0 (XDATDLY=00b) mode.
0
6
Enable time, FSX high to DX driven
M10 ten(FXH-DX)
P
Only applies to first bit transmitted when
in Data Delay 0 (XDATDLY=00b) mode
P + 6
(1) Polarity bits CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that
signal are also inverted.
(2) 2P = 1/CLKG in ns.
(3) C = CLKRX low pulse width = P
D = CLKRX high pulse width = P
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M1, M11
M2, M12
M13
M3, M12
CLKR
M4
M4
M14
FSR (int)
FSR (ext)
M15
M17
M16
M18
DR
(RDATDLY=00b)
Bit (n−1)
M17
(n−2)
(n−3)
(n−2)
(n−4)
(n−3)
(n−2)
M18
DR
(RDATDLY=01b)
Bit (n−1)
M17
M18
DR
(RDATDLY=10b)
Bit (n−1)
Figure 7-20. McBSP Receive Timing
M1, M11
M2, M12
M13
M3, M12
CLKX
FSX (int)
FSX (ext)
DX
M5
M5
M19
M20
M9
M7
M7
M10
Bit 0
Bit (n−1)
(n−2)
(n−3)
(n−2)
(XDATDLY=00b)
M8
DX
(XDATDLY=01b)
Bit (n−1)
M8
Bit 0
M6
M7
DX
(XDATDLY=10b)
Bit 0
Bit (n−1)
Figure 7-21. McBSP Transmit Timing
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7.9.4.6.2 McBSP as SPI Master or Slave Timing
7.9.4.6.2.1 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0) (1)
MASTER
SLAVE
MIN MAX
NO.
UNIT
MIN
30
1
MAX
M30 tsu(DRV-CKXL)
M31 th(CKXL-DRV)
M32 tsu(BFXL-CKXH)
M33 tc(CKX)
Setup time, DR valid before CLKX low
Hold time, DR valid after CLKX low
Setup time, FSX low before CLKX high
Cycle timez, CLKX
8P – 10
ns
ns
ns
ns
8P – 10
8P + 10
16P
2P(2)
(1) For all SPI slave modes, CLKX must be a minimum of 8 CLKG cycles. Furthermore, CLKG should be LSPCLK/2 by setting CLKSM =
CLKGDV = 1.
(2) 2P = 1/CLKG
7.9.4.6.2.2 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 0)
MASTER
MIN
SLAVE
MIN
NO.
PARAMETER
UNIT
MAX
MAX
M24
M25
M26
th(CKXL-FXL)
td(FXL-CKXH)
td(CLKXH-DXV)
Hold time, FSX low after CLKX low
Delay time, FSX low to CLKX high
Delay time, CLKX low to DX valid
2P(1)
ns
ns
ns
P
–2
0
3P + 6
6P + 6
4P + 6
5P + 20
Disable time, DX high impedance following
last data bit from FSX high
M28
M29
tdis(FXH-DXHZ)
td(FXL-DXV)
6
6
ns
ns
Delay time, FSX low to DX valid
(1) 2P = 1/CLKG
M33
M32
MSB
LSB
CLKX
M25
M24
FSX
M28
M29
M26
DX
DR
Bit 0
Bit(n-1)
(n-2)
(n-3)
(n-4)
M30
M31
Bit 0
Bit(n-1)
(n-2)
(n-3)
(n-4)
Figure 7-22. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0
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7.9.4.6.2.3 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 0) (1)
MASTER
SLAVE
MIN MAX
NO.
UNIT
MIN
30
1
MAX
M39 tsu(DRV-CKXH)
M40 th(CKXH-DRV)
M41 tsu(FXL-CKXH)
M42 tc(CKX)
Setup time, DR valid before CLKX high
Hold time, DR valid after CLKX high
Setup time, FSX low before CLKX high
Cycle time, CLKX
8P – 10
ns
ns
ns
ns
8P – 10
16P + 10
16P
2P(2)
(1) For all SPI slave modes, CLKX must be a minimum of 8 CLKG cycles. Furthermore, CLKG should be LSPCLK/2 by setting CLKSM =
CLKGDV = 1.
(2) 2P = 1/CLKG
7.9.4.6.2.4 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 0)
MASTER
MIN
SLAVE
MIN
NO.
PARAMETER
UNIT
MAX
MAX
M34 th(CKXL-FXL)
M35 td(FXL-CKXH)
M36 td(CLKXL-DXV)
Hold time, FSX low after CLKX low
Delay time, FSX low to CLKX high
Delay time, CLKX low to DX valid
P
2P(1)
–2
ns
ns
ns
0
3P + 6 5P + 20
7P + 6
Disable time, DX high impedance following last data bit
from CLKX low
M37 tdis(CKXL-DXHZ)
M38 td(FXL-DXV)
P + 6
6
ns
ns
Delay time, FSX low to DX valid
4P + 6
(1) 2P = 1/CLKG
M42
MSB
LSB
M41
CLKX
M35
M34
FSX
M38
M36
(n-2)
M40
(n-2)
M37
DX
DR
Bit 0
Bit(n-1)
Bit(n-1)
(n-3)
(n-4)
M39
Bit 0
(n-3)
(n-4)
Figure 7-23. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0
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UNIT
SPRS516F – MARCH 2009 – REVISED FEBRUARY 2021
7.9.4.6.2.5 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 1) (1)
MASTER
SLAVE
MIN MAX
NO.
MIN
30
1
MAX
M49 tsu(DRV-CKXH)
M50 th(CKXH-DRV)
M51 tsu(FXL-CKXL)
M52 tc(CKX)
Setup time, DR valid before CLKX high
Hold time, DR valid after CLKX high
Setup time, FSX low before CLKX low
Cycle time, CLKX
8P – 10
ns
ns
ns
ns
8P – 10
8P + 10
16P
2P(2)
(1) For all SPI slave modes, CLKX must be a minimum of 8 CLKG cycles. Furthermore, CLKG should be LSPCLK/2 by setting CLKSM =
CLKGDV = 1.
(2) 2P = 1/CLKG
7.9.4.6.2.6 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 1)
MASTER
SLAVE
MIN MAX
NO.
PARAMETER
UNIT
MIN
2P(1)
P
MAX
M43 th(CKXH-FXL)
M44 td(FXL-CKXL)
M45 td(CLKXL-DXV)
Hold time, FSX low after CLKX high
Delay time, FSX low to CLKX low
Delay time, CLKX low to DX valid
ns
ns
ns
–2
0
3P + 6 5P + 20
6P + 6
Disable time, DX high impedance following last data bit from
FSX high
M47 tdis(FXH-DXHZ)
M48 td(FXL-DXV)
6
6
ns
ns
Delay time, FSX low to DX valid
4P + 6
(1) 2P = 1/CLKG
M52
M51
MSB
LSB
CLKX
M43
M44
FSX
M48
M45
M47
DX
DR
Bit 0
Bit(n-1)
Bit(n-1)
(n-2)
(n-3)
(n-4)
(n-4)
M49
M50
(n-2)
Bit 0
(n-3)
Figure 7-24. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1
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7.9.4.6.2.7 McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 1) (1)
MASTER
SLAVE
MIN MAX
NO.
UNIT
MIN
30
1
MAX
M58 tsu(DRV-CKXL)
M59 th(CKXL-DRV)
M60 tsu(FXL-CKXL)
M61 tc(CKX)
Setup time, DR valid before CLKX low
Hold time, DR valid after CLKX low
Setup time, FSX low before CLKX low
Cycle time, CLKX
8P – 10
ns
ns
ns
ns
8P – 10
16P + 10
16P
2P(2)
(1) For all SPI slave modes, CLKX must be a minimum of 8 CLKG cycles. Furthermore, CLKG should be LSPCLK/2 by setting CLKSM =
CLKGDV = 1.
(2) 2P = 1/CLKG
7.9.4.6.2.8 McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 1) (1)
MASTER(2)
SLAVE
MIN
NO.
PARAMETER
UNIT
MIN
MAX
MAX
M53 th(CKXH-FXL)
M54 td(FXL-CKXL)
M55 td(CLKXH-DXV)
Hold time, FSX low after CLKX high
Delay time, FSX low to CLKX low
Delay time, CLKX high to DX valid
P
ns
ns
ns
2P(1)
–2
0
3P + 6
7P + 6
4P + 6
5P + 20
Disable time, DX high impedance following last data
bit from CLKX high
M56 tdis(CKXH-DXHZ)
M57 td(FXL-DXV)
P + 6
6
ns
ns
Delay time, FSX low to DX valid
(1) 2P = 1/CLKG
(2) C = CLKX low pulse width = P
D = CLKX high pulse width = P
M61
M60
MSB
M54
LSB
CLKX
M53
FSX
M56
M55
M57
DX
DR
Bit 0
Bit(n-1)
(n-2)
(n-3)
(n-4)
(n-4)
M58
M59
Bit 0
Bit(n-1)
(n-2)
(n-3)
Figure 7-25. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1
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7.9.5 Emulator Connection Without Signal Buffering for the MCU
Figure 7-26 shows the connection between the MCU and JTAG header for a single-processor configuration. If
the distance between the JTAG header and the MCU is greater than 6 inches, the emulation signals must be
buffered. If the distance is less than 6 inches, buffering is typically not needed. Figure 7-26 shows the simpler,
no-buffering situation. For the pullup/pulldown resistor values, see the pin description section. For details on
buffering JTAG signals and multiple processor connections, see the TMS320F/C24x DSP controllers CPU and
instruction set reference guide.
6 inches or less
VDDIO
VDDIO
13
14
2
5
EMU0
EMU1
TRST
TMS
TDI
EMU0
EMU1
TRST
TMS
PD
4
GND
1
6
GND
GND
GND
GND
3
8
TDI
7
10
12
TDO
TDO
11
9
TCK
TCK
TCK_RET
MCU
JTAG Header
Figure 7-26. Emulator Connection Without Signal Buffering for the MCU
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7.9.6 External Interface (XINTF) Timing
Each XINTF access consists of three parts: Lead, Active, and Trail. The user configures the Lead/Active/Trail
wait states in the XTIMING registers. There is one XTIMING register for each XINTF zone. Table 7-2 shows the
relationship between the parameters configured in the XTIMING register and the duration of the pulse in terms of
XTIMCLK cycles.
Table 7-2. Relationship Between Parameters Configured in XTIMING and Duration of Pulse
DURATION (ns)(1) (2)
DESCRIPTION
X2TIMING = 0
XRDLEAD × tc(XTIM)
X2TIMING = 1
(XRDLEAD × 2) × tc(XTIM)
LR
Lead period, read access
Active period, read access
Trail period, read access
Lead period, write access
Active period, write access
Trail period, write access
AR
TR
LW
AW
TW
(XRDACTIVE + WS + 1) × tc(XTIM)
XRDTRAIL × tc(XTIM)
(XRDACTIVE × 2 + WS + 1) × tc(XTIM)
(XRDTRAIL × 2) × tc(XTIM)
XWRLEAD × tc(XTIM)
(XWRLEAD × 2) × tc(XTIM)
(XWRACTIVE + WS + 1) × tc(XTIM)
XWRTRAIL × tc(XTIM)
(XWRACTIVE × 2 + WS + 1) × tc(XTIM)
(XWRTRAIL × 2) × tc(XTIM)
(1) tc(XTIM) − Cycle time, XTIMCLK
(2) WS refers to the number of wait states inserted by hardware when using XREADY. If the zone is configured to ignore XREADY
(USEREADY = 0), then WS = 0.
Minimum wait-state requirements must be met when configuring each zone’s XTIMING register. These
requirements are in addition to any timing requirements as specified by that device’s data sheet. No internal
device hardware is included to detect illegal settings.
7.9.6.1 USEREADY = 0
If the XREADY signal is ignored (USEREADY = 0), then:
Lead:
Active:
Trail:
LR ≥ 2 × tc(XTIM)
LW ≥ 3 × tc(XTIM)
AR ≥ 6 × tc(XTIM)
AW ≥ 1 × tc(XTIM)
TW ≥ 3 × tc(XTIM)
These requirements result in the following XTIMING register configuration restrictions:
XRDLEAD
XRDACTIVE
XRDTRAIL
XWRLEAD
XWRACTIVE
XWRTRAIL
X2TIMING
≥ 2
≥ 6
≥ 0
≥ 3(2)
≥ 1
≥ 3(2)
0(1)
(1) If X2TIMCLK is enabled, specified Lead, Active, and Trail restrictions can be divided by 2 for values with even numbers.
(2) Lead and trail write must be at least 7.5 ns.
Examples of valid and invalid timing when not sampling XREADY:
XRDLEAD
XRDACTIVE
XRDTRAIL
XWRLEAD
XWRACTIVE
XWRTRAIL
X2TIMING
0, 1
Invalid(1)
Valid(2)
0
2
0
6
0
0
0
3
0
1
0
3
0(3)
(1) No hardware to detect illegal XTIMING configurations
(2) Based on 300-MHz system clock speed.
(3) If X2TIMCLK is enabled, specified Lead, Active, and Trail restrictions can be divided by 2 for values with even numbers.
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7.9.6.2 Synchronous Mode (USEREADY = 1, READYMODE = 0)
If the XREADY signal is sampled in the synchronous mode (USEREADY = 1, READYMODE = 0), then:
1
2
3
Lead:
Active:
Trail:
LR ≥ 2 × tc(XTIM)
LW ≥ 3 × tc(XTIM)
AR ≥ 6 × tc(XTIM)
AW ≥ 2 × tc(XTIM)
TW ≥ 3 × tc(XTIM)
Note
Restriction does not include external hardware wait states.
These requirements result in the following XTIMING register configuration restrictions (based on 300-MHz
system clock speed):
XRDLEAD
XRDACTIVE
XRDTRAIL
XWRLEAD
XWRACTIVE
XWRTRAIL
X2TIMING
≥ 2
≥ 6
≥ 0
≥ 3(2)
≥ 2
≥ 3(2)
0(1)
(1) If X2TIMCLK is enabled, specified Lead, Active, and Trail restrictions can be divided by 2 for values with even numbers.
(2) Lead and trail write must be at least 7.5 ns.
Examples of valid and invalid timing when using synchronous XREADY:
XRDLEAD
XRDACTIVE
XRDTRAIL
XWRLEAD
XWRACTIVE
XWRTRAIL
X2TIMING
0, 1
Invalid(1)
Invalid(1)
Valid(2)
0
1
2
0
0
6
0
0
0
0
1
3
0
0
2
0
0
3
0, 1
0(3)
(1) No hardware to detect illegal XTIMING configurations
(2) Based on 300-MHz system clock speed
(3) If X2TIMCLK is enabled, specified Lead, Active, and Trail restrictions can be divided by 2 for values with even numbers.
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7.9.6.3 Asynchronous Mode (USEREADY = 1, READYMODE = 1)
If the XREADY signal is sampled in the asynchronous mode (USEREADY = 1, READYMODE = 1), then:
1
2
3
Lead:
Active:
Trail:
LR ≥ 2 × tc(XTIM)
LW ≥ 3 × tc(XTIM)
AR ≥ 6 × tc(XTIM)
AW ≥ 4 × tc(XTIM)
TW ≥ 3 × tc(XTIM)
Note
Restrictions do not include external hardware wait states.
These requirements result in the following XTIMING register configuration restrictions (based on 300-MHz
system clock speed):
XRDLEAD
XRDACTIVE
XRDTRAIL
XWRLEAD
XWRACTIVE
XWRTRAIL
X2TIMING
≥ 2
≥ 6
0
≥ 3(2)
≥ 4
≥3(2)
0(1)
(1) If X2TIMCLK is enabled, specified Lead, Active, and Trail restrictions can be divided by 2 for values with even numbers.
(2) Lead and trail write must be at least 7.5 ns.
Examples of valid and invalid timing when using asynchronous XREADY:
XRDLEAD
XRDACTIVE
XRDTRAIL
XWRLEAD
XWRACTIVE
XWRTRAIL
X2TIMING
Invalid(1)
Invalid(1)
Invalid(1)
Valid(2)
0
1
1
2
0
0
1
6
0
0
0
0
0
1
1
3
0
0
1
4
0
0
0
3
0, 1
0, 1
0
0(3)
(1) No hardware to detect illegal XTIMING configurations
(2) Based on 300-MHz system clock speed
(3) If X2TIMCLK is enabled, specified Lead, Active, and Trail restrictions can be divided by 2 for values with even numbers.
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Unless otherwise specified, all XINTF timing is applicable for the clock configurations listed in Table 7-3.
Table 7-3. XINTF Clock Configurations for SYSCLKOUT = 300 MHz
MODE
SYSCLKOUT
300 MHz
300 MHz
300 MHz
300 MHz
300 MHz
300 MHz
300 MHz
300 MHz
XTIMCLK
SYSCLKOUT
300 MHz
XCLKOUT(1)
1
SYSCLKOUT
300 MHz
Example:
2
SYSCLKOUT
300 MHz
1/2 SYSCLKOUT
150 MHz
Example:
3
SYSCLKOUT
300 MHz
1/2 SYSCLKOUT
150 MHz
Example:
4
SYSCLKOUT
300 MHz
1/4 SYSCLKOUT
75 MHz
Example:
5
Example:
6
1/2 SYSCLKOUT
150 MHz
1/2 SYSCLKOUT
150 MHz
1/2 SYSCLKOUT
150 MHz
1/4 SYSCLKOUT
75 MHz
Example:
7
1/2 SYSCLKOUT
150 MHz
1/4 SYSCLKOUT
75 MHz
Example:
8
1/2 SYSCLKOUT
150 MHz
1/8 SYSCLKOUT
37.5 MHz
Example:
(1) The XCLKOUT signal is limited to a maximum frequency of 75 MHz.
The relationship between SYSCLKOUT and XTIMCLK is shown in Figure 7-27.
PCLKR3[XINTFENCLK]
XTIMING0
LEAD/ACTIVE/TRAIL
XTIMING6
XTIMING7
XBANK
0
0
1
SYSCLKOUT
C28x
CPU
XTIMCLK
/2
1
0
/2
1
0
/2
1
0
XCLKOUT
XINTCNF2 (XTIMCLK)
XINTCNF2
(CLKMODE)
XINTCNF2
(BY4CLKMODE)
XINTCNF2
(CLKOFF)
Figure 7-27. Relationship Between SYSCLKOUT and XTIMCLK
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7.9.6.4 XINTF Signal Alignment to XCLKOUT
For each XINTF access, the number of lead, active, and trail cycles is based on the internal clock XTIMCLK.
Strobes such as XRD, XWE0, XWE1, and zone chip-select ( XZCS) change state in relationship to the rising
edge of XTIMCLK. The external clock, XCLKOUT, can be configured to be equal to, one-half, or one-fourth the
frequency of XTIMCLK.
For the case where XCLKOUT = XTIMCLK, all of the XINTF strobes will change state with respect to the rising
edge of XCLKOUT. For the case where XCLKOUT = one-half or one-fourth XTIMCLK, some strobes will change
state either on the rising edge of XCLKOUT or the falling edge of XCLKOUT. In the XINTF timing tables, the
notation XCOHL is used to indicate that the parameter is with respect to either case; XCLKOUT rising edge
(high) or XCLKOUT falling edge (low). If the parameter is always with respect to the rising edge of XCLKOUT,
the notation XCOH is used.
For the case where XCLKOUT = one-half XTIMCLK, the XCLKOUT edge with which the change will be aligned
can be determined based on the number of XTIMCLK cycles from the start of the access to the point at which
the signal changes. If this number of XTIMCLK cycles is even, the alignment will be with respect to the rising
edge of XCLKOUT. If this number is odd, then the signal will change with respect to the falling edge of
XCLKOUT. Examples include the following:
•
Strobes that change at the beginning of an access always align to the rising edge of XCLKOUT. This is
because all XINTF accesses begin with respect to the rising edge of XCLKOUT.
Examples:
XZCSL
Zone chip-select active low
XRNWL
XR/ W active low
•
Strobes that change at the beginning of the active period will align to the rising edge of XCLKOUT if the total
number of lead XTIMCLK cycles for the access is even. If the number of lead XTIMCLK cycles is odd, then
the alignment will be with respect to the falling edge of XCLKOUT.
Examples:
XRDL
XRD active low
XWEL
XWE1 or XWE0 active low
•
•
Strobes that change at the beginning of the trail period will align to the rising edge of XCLKOUT if the total
number of lead + active XTIMCLK cycles (including hardware waitstates) for the access is even. If the
number of lead + active XTIMCLK cycles (including hardware waitstates) is odd, then the alignment will be
with respect to the falling edge of XCLKOUT.
Examples:
XRDH
XRD inactive high
XWEH
XWE1 or XWE0 inactive high
Strobes that change at the end of the access will align to the rising edge of XCLKOUT if the total number of
lead + active + trail XTIMCLK cycles (including hardware waitstates) is even. If the number of lead + active +
trail XTIMCLK cycles (including hardware waitstates) is odd, then the alignment will be with respect to the
falling edge of XCLKOUT.
Examples:
XZCSH
Zone chip-select inactive high
XRNWH
XR/ W inactive high
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7.9.6.5 External Interface Read Timing
7.9.6.5.1 External Interface Read Timing Requirements
MIN
MAX
(LR + AR) – 13.5 (1)
AR – 13 (1)
UNIT
ns
ta(A)
Access time, read data from address valid
ta(XRD)
Access time, read data valid from XRD active low
Setup time, read data valid before XRD strobe inactive high
Hold time, read data valid after XRD inactive high
ns
tsu(XD)XRD
th(XD)XRD
13
0
ns
ns
(1) LR = Lead period, read access. AR = Active period, read access. See Table 7-2.
7.9.6.5.2 External Interface Read Switching Characteristics
PARAMETER
MIN
0
MAX
2
UNIT
ns
td(XCOH-XZCSL)
td(XCOHL-XZCSH)
td(XCOH-XA)
Delay time, XCLKOUT high to zone chip-select active low
Delay time, XCLKOUT high/low to zone chip-select inactive high
Delay time, XCLKOUT high to address valid
–0.2
0.9
1.5
0.8
0.8
ns
ns
td(XCOHL-XRDL)
td(XCOHL-XRDH)
th(XA)XZCSH
Delay time, XCLKOUT high/low to XRD active low
Delay time, XCLKOUT high/low to XRD inactive high
Hold time, address valid after zone chip-select inactive high
Hold time, address valid after XRD inactive high
–0.2
ns
–0.4
ns
(1)
ns
(1)
th(XA)XRD
ns
(1) During inactive cycles, the XINTF address bus always holds the last address put out on the bus . This includes alignment cycles.
Trail
(A)(B)
(C)
Active
Lead
XCLKOUT = XTIMCLK(D)
t
d(XCOH-XZCSL)
t
d(XCOHL-XZCSH)
XZCS0, XZCS6, XZCS7
XA[0:19]
t
d(XCOH-XA)
t
d(XCOHL-XRDH)
t
d(XCOHL-XRDL)
XRD
XWE, XWE1(E)
t
su(XD)XRD
XR/W
t
a(A)
t
h(XD)XRD
t
a(XRD)
XD[0:31], XD[0:15]
XREADY(F)
DIN
A. All XINTF accesses (lead period) begin on the rising edge of XCLKOUT. When necessary, the device inserts an alignment cycle before
an access to meet this requirement.
B. During alignment cycles, all signals transition to their inactive state.
C. XA[0:19] holds the last address put on the bus during inactive cycles, including alignment cycles except XA0, which remains high.
D. Timings are also relevant for XCLKOUT = 1/2 XTIMCLK and XCLKOUT = 1/4 XTIMCLK.
E. XWE1 is used in 32-bit data bus mode.
F. For USEREADY = 0, the external XREADY input signal is ignored.
Figure 7-28. Example Read Access
XTIMING register parameters used for this example (based on 300-MHz system clock):
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XRDLEAD
XRDACTIVE
XRDTRAIL
USEREADY
X2TIMING
XWRLEAD
XWRACTIVE
XWRTRAIL
READYMODE
≥ 2
≥ 5
≥ 0
0
0
N/A(1)
N/A(1)
N/A(1)
N/A(1)
(1) N/A = Not applicable (or “Don’t care”) for this example
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7.9.6.6 External Interface Write Timing
7.9.6.6.1 External Interface Write Switching Characteristics
PARAMETER
MIN
0
MAX
2
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
td(XCOH-XZCSL)
td(XCOHL-XZCSH)
td(XCOH-XA)
Delay time, XCLKOUT high to zone chip-select active low
Delay time, XCLKOUT high or low to zone chip-select inactive high
Delay time, XCLKOUT high to address valid
–0.2
0.9
1.5
0.7
0.5
1.5
0.6
td(XCOHL-XWEL)
td(XCOHL-XWEH)
td(XCOH-XRNWL)
td(XCOHL-XRNWH)
ten(XD)XWEL
Delay time, XCLKOUT high/low to XWE0, XWE1 low
Delay time, XCLKOUT high/low to XWE0, XWE1 high
Delay time, XCLKOUT high to XR/ W low
–0.3
–0.5
–0.2
0.3
Delay time, XCLKOUT high/low to XR/ W high
Enable time, data bus driven from XWE0, XWE1 low
Delay time, data valid after XWE0, XWE1 active low
Hold time, address valid after zone chip-select inactive high
Hold time, write data valid after XWE0, XWE1 inactive high
Maximum time for processor to release the data bus after XR/ W inactive high
–7.5
td(XWEL-XD)
0
4
(1)
th(XA)XZCSH
th(XD)XWE
TW – 7.5 (2)
tdis(XD)XRNW
0
(1) During inactive cycles, the XINTF address bus will always hold the last address put out on the bus except XA0, which remains high.
This includes alignment cycles.
(2) TW = Trail period, write access. See Table 7-2.
Active
(A) (B)
(C)
Lead
Trail
XCLKOUT = XTIMCLK(D)
XZCS0, XZCS6, XZCS7
t
d(XCOHL-XZCSH)
t
d(XCOH-XZCSL)
t
d(XCOH-XA)
XA[0:19]
XRD
t
t
d(XCOHL-XWEH)
d(XCOHL-XWEL)
XWE0, XWE1(E)
XR/W
t
t
d(XCOHL-XRNWH)
d(XCOH-XRNWL)
t
t
dis(XD)XRNW
d(XWEL-XD)
t
t
en(XD)XWEL
h(XD)XWEH
XD[0:31], XD[0:15]
XREADY(F)
DOUT
A. All XINTF accesses (lead period) begin on the rising edge of XCLKOUT. When necessary, the device inserts an alignment cycle before
an access to meet this requirement.
B. During alignment cycles, all signals transition to their inactive state.
C. XA[0:19] holds the last address put on the bus during inactive cycles, including alignment cycles except XA0, which remains high.
D. Timings are also relevant for XCLKOUT = 1/2 XTIMCLK and XCLKOUT = 1/4 XTIMCLK.
E. XWE1 is used in 32-bit data bus mode.
F. For USEREADY = 0, the external XREADY input signal is ignored.
Figure 7-29. Example Write Access
XTIMING register parameters used for this example (based on 300-MHz system clock):
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XRDLEAD
XRDACTIVE
XRDTRAIL
USEREADY
X2TIMING
XWRLEAD
XWRACTIVE
XWRTRAIL
READYMODE
N/A(1)
N/A(1)
N/A(1)
0
0
≥ 3
≥ 1
≥ 3
N/A(1)
(1) N/A = Not applicable (or “Don’t care”) for this example
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7.9.6.7 External Interface Ready-on-Read Timing With One External Wait State
7.9.6.7.1 External Interface Read Switching Characteristics (Ready-on-Read, One Wait State)
PARAMETER
MIN
0
MAX
2
UNIT
ns
td(XCOH-XZCSL)
td(XCOHL-XZCSH)
td(XCOH-XA)
Delay time, XCLKOUT high to zone chip-select active low
Delay time, XCLKOUT high/low to zone chip-select inactive high
Delay time, XCLKOUT high to address valid
–0.2
0.9
1.5
0.8
0.8
ns
ns
td(XCOHL-XRDL)
td(XCOHL-XRDH)
th(XA)XZCSH
Delay time, XCLKOUT high/low to XRD active low
Delay time, XCLKOUT high/low to XRD inactive high
Hold time, address valid after zone chip-select inactive high
Hold time, address valid after XRD inactive high
–0.2
ns
–0.4
ns
(1)
ns
(1)
th(XA)XRD
ns
(1) During inactive cycles, the XINTF address bus always holds the last address put out on the bus. This includes alignment cycles.
7.9.6.7.2 External Interface Read Timing Requirements (Ready-on-Read, One Wait State)
MIN
MAX
(LR + AR) – 13.5 (1)
AR – 13 (1)
UNIT
ns
ta(A)
Access time, read data from address valid
ta(XRD)
Access time, read data valid from XRD active low
Setup time, read data valid before XRD strobe inactive high
Hold time, read data valid after XRD inactive high
ns
tsu(XD)XRD
th(XD)XRD
13
0
ns
ns
(1) LR = Lead period, read access. AR = Active period, read access. See Table 7-2.
7.9.6.7.3 Synchronous XREADY Timing Requirements (Ready-on-Read, One Wait State) (1)
MIN
MAX
UNIT
ns
tsu(XRDYsynchL)XCOHL
th(XRDYsynchL)
tsu(XRDYsynchH)XCOHL
th(XRDYsynchH)XZCSH
Setup time, XREADY (synchronous) low before XCLKOUT high/low
Hold time, XREADY (synchronous) low
8
1tc(XTIM)
ns
Setup time, XREADY (synchronous) high before XCLKOUT high/low
Hold time, XREADY (synchronous) held high after zone chip select high
8
0
ns
ns
(1) The first XREADY (synchronous) sample occurs with respect to E in Figure 7-30:
E = (XRDLEAD + XRDACTIVE) tc(XTIM)
When first sampled, if XREADY (synchronous) is found to be high, then the access will finish. If XREADY (synchronous) is found to be
low, it is sampled again each tc(XTIM) until it is found to be high.
For each sample (n) the setup time (F) with respect to the beginning of the access can be calculated as:
F = (XRDLEAD + XRDACTIVE +n − 1) tc(XTIM) − tsu(XRDYsynchL)XCOHL
where n is the sample number: n = 1, 2, 3, and so forth.
7.9.6.7.4 Asynchronous XREADY Timing Requirements (Ready-on-Read, One Wait State)
MIN
MAX UNIT
tsu(XRDYAsynchL)XCOHL
th(XRDYAsynchL)
tsu(XRDYAsynchH)XCOHL
th(XRDYasynchH)XZCSH
Setup time, XREADY (asynchronous) low before XCLKOUT high/low
Hold time, XREADY (asynchronous) low
8
ns
ns
ns
ns
1tc(XTIM)
Setup time, XREADY (asynchronous) high before XCLKOUT high/low
Hold time, XREADY (asynchronous) held high after zone chip select high
8
0
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WS (Synch)
(A) (B)
(C)
Active
Lead
Trail
(D)
XCLKOUT = XTIMCLK
t
t
t
d(XCOHL-XZCSH)
d(XCOH-XZCSL)
d(XCOH-XA)
XZCS0, XZCS6, XZCS7
XA[0:19]
XRD
t
d(XCOHL-XRDH)
t
d(XCOHL-XRDL)
t
su(XD)XRD
(E)
XWE0, XWE1
t
a(XRD)
XR/W
t
a(A)
t
h(XD)XRD
XD[0:31], XD[0:15]
DIN
t
su(XRDYsynchL)XCOHL
t
h(XRDYsynchL)
t
h(XRDYsynchH)XZCSH
t
su(XRDHsynchH)XCOHL
XREADY(Synch)
Legend:
(F)
(G)
= Don’t care. Signal can be high or low during this time.
A. All XINTF accesses (lead period) begin on the rising edge of XCLKOUT. When necessary, the device inserts an alignment cycle before
an access to meet this requirement.
B. During alignment cycles, all signals transition to their inactive state.
C. During inactive cycles, the XINTF address bus always holds the last address put out on the bus except XA0, which remains high. This
includes alignment cycles.
D. Timings are also relevant for XCLKOUT = 1/2 XTIMCLK and XCLKOUT = 1/4 XTIMCLK.
E. XWE1 is valid only in 32-bit data bus mode.
F. For each sample, setup time from the beginning of the access (E) can be calculated as: D = (XRDLEAD + XRDACTIVE +n - 1) tc(XTIM)
tsu(XRDYsynchL)XCOHL
–
G. Reference for the first sample is with respect to this point: F = (XRDLEAD + XRDACTIVE) tc(XTIM) where n is the sample number: n = 1,
2, 3, and so forth.
Figure 7-30. Example Read With Synchronous XREADY Access
XTIMING register parameters used for this example (based on 300-MHz system clock):
XRDLEAD
XRDACTIVE
XRDTRAIL
USEREADY
X2TIMING
XWRLEAD
XWRACTIVE
XWRTRAIL
READYMODE
≥ 2
5
≥ 0
1
0
N/A(1)
N/A(1)
N/A(1)
0 = XREADY
(Synch)
(1) N/A = “Don’t care” for this example
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WS (Async)
(A) (B)
Active
Lead
Trail
(C)
(D)
XCLKOUT = XTIMCLK
t
t
t
d(XCOH-XZCSL)
d(XCOH-XA)
d(XCOHL-XZCSH)
XZCS0, XZCS6, XZCS7
XA[0:19]
XRD
t
d(XCOHL-XRDH)
t
d(XCOHL-XRDL)
t
su(XD)XRD
(E)
XWE0, XWE1
t
a(XRD)
XR/W
t
a(A)
t
h(XD)XRD
DIN
XD[0:31], XD[0:15]
t
su(XRDYasynchL)XCOHL
t
h(XRDYasynchH)XZCSH
t
h(XRDYasynchL)
t
su(XRDYasynchH)XCOHL
XREADY(Asynch)
(F)
(G)
Legend:
= Don’t care. Signal can be high or low during this time.
A. All XINTF accesses (lead period) begin on the rising edge of XCLKOUT. When necessary, the device will insert an alignment cycle
before an access to meet this requirement.
B. During alignment cycles, all signals will transition to their inactive state.
C. During inactive cycles, the XINTF address bus will always hold the last address put out on the bus except XA0, which remains high. This
includes alignment cycles.
D. Timings are also relevant for XCLKOUT = 1/2 XTIMCLK and XCLKOUT = 1/4 XTIMCLK.
E. XWE1 is valid only in 32-bit data bus mode.
F. For each sample, setup time from the beginning of the access can be calculated as: E = (XRDLEAD + XRDACTIVE -3 +n) tc(XTIM)
tsu(XRDYasynchL)XCOHL where n is the sample number: n = 1, 2, 3, and so forth.
–
G. Reference for the first sample is with respect to this point: F = (XRDLEAD + XRDACTIVE –2) tc(XTIM)
Figure 7-31. Example Read With Asynchronous XREADY Access
XTIMING register parameters used for this example (based on 300-MHz system clock):
XRDLEAD
XRDACTIVE
XRDTRAIL
USEREADY
X2TIMING
XWRLEAD
XWRACTIVE
XWRTRAIL
READYMODE
≥ 2
5
≥ 0
1
0
N/A(1)
N/A(1)
N/A(1)
1 = XREADY
(Async)
(1) N/A = “Don’t care” for this example
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7.9.6.8 External Interface Ready-on-Write Timing With One External Wait State
7.9.6.8.1 External Interface Write Switching Characteristics (Ready-on-Write, One Wait State)
PARAMETER
MIN
MAX
2
UNIT
ns
td(XCOH-XZCSL)
td(XCOHL-XZCSH)
td(XCOH-XA)
Delay time, XCLKOUT high to zone chip-select active low
Delay time, XCLKOUT high or low to zone chip-select inactive high
Delay time, XCLKOUT high to address valid
0
–0.2
0.9
1.5
0.7
0.5
1.5
0.6
ns
ns
td(XCOHL-XWEL)
td(XCOHL-XWEH)
td(XCOH-XRNWL)
td(XCOHL-XRNWH)
ten(XD)XWEL
Delay time, XCLKOUT high/low to XWE0, XWE1 low(3)
Delay time, XCLKOUT high/low to XWE0, XWE1 high(3)
Delay time, XCLKOUT high to XR/ W low
–0.3
–0.5
–0.2
0.3
ns
ns
ns
Delay time, XCLKOUT high/low to XR/ W high
ns
Enable time, data bus driven from XWE0, XWE1 low
Delay time, data valid after XWE0, XWE1 active low
Hold time, address valid after zone chip-select inactive high
Hold time, write data valid after XWE0, XWE1 inactive high(3)
–7.5
ns
td(XWEL-XD)
0
4
ns
(1)
th(XA)XZCSH
ns
th(XD)XWE
TW – 7.5 (2)
ns
Maximum time for processor to release the data bus after XR/ W
inactive high
tdis(XD)XRNW
0
ns
(1) During inactive cycles, the XINTF address bus always holds the last address put out on the bus . This includes alignment cycles.
(2) TW = trail period, write access (see Table 7-2)
(3) XWE1 is used in 32-bit data bus mode only. In 16-bit, this signal is XA0.
7.9.6.8.2 Synchronous XREADY Timing Requirements (Ready-on-Write, One Wait State) Table 8-23
MIN
MAX
UNIT
ns
tsu(XRDYsynchL)XCOHL
th(XRDYsynchL)
tsu(XRDYsynchH)XCOHL
th(XRDYsynchH)XZCSH
Setup time, XREADY (synchronous) low before XCLKOUT high/low
Hold time, XREADY (synchronous) low
8
1tc(XTIM)
ns
Setup time, XREADY (synchronous) high before XCLKOUT high/low
Hold time, XREADY (synchronous) held high after zone chip select high
8
0
ns
ns
7.9.6.8.3 Asynchronous XREADY Timing Requirements (Ready-on-Write, One Wait State) (1)
MIN
MAX UNIT
tsu(XRDYasynchL)XCOHL
th(XRDYasynchL)
tsu(XRDYasynchH)XCOHL
th(XRDYasynchH)XZCSH
Setup time, XREADY (asynchronous) low before XCLKOUT high/low
Hold time, XREADY (asynchronous) low
8
ns
ns
ns
ns
1tc(XTIM)
Setup time, XREADY (asynchronous) high before XCLKOUT high/low
Hold time, XREADY (asynchronous) held high after zone chip select high
8
0
(1) The first XREADY (synchronous) sample occurs with respect to E in Figure 7-32:
E = (XWRLEAD + XWRACTIVE –2) tc(XTIM). When first sampled, if XREADY (asynchronous) is high, then the access will complete. If
XREADY (asynchronous) is low, it is sampled again each tc(XTIM) until it is high.
For each sample, setup time from the beginning of the access can be calculated as:
F = (XWRLEAD + XWRACTIVE –3 + n) tc(XTIM) – tsu(XRDYasynchL)XCOHL
where n is the sample number: n = 1, 2, 3, and so forth.
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WS (Synch)
(A) (B)
Active
Lead 1
(C)
Trail
XCLKOUT = XTIMCLK(D)
t
t
d(XCOHL-XZCSH)
d(XCOH-XZCSL)
XZCS0, XZCS6, XZCS7
t
t
h(XRDYsynchH)XZCSH
d(XCOH-XA)
XA[0:18]
XRD
t
t
d(XCOHL-XWEH)
d(XCOHL-XWEL)
XWE
t
t
d(XCOHL-XRNWH)
d(XCOH-XRNWL)
XR/W
t
dis(XD)XRNW
t
d(XWEL-XD
)
t
h(XD)XWEH
t
en(XD)XWEL
XD[0:15]
DOUT
t
su(XRDYsynchL)XCOHL
t
h(XRDYsynchL)
t
su(XRDHsynchH)XCOHL
XREADY (Synch)
(E)
(F)
Legend:
= Don’t care. Signal can be high or low during this time.
A. All XINTF accesses (lead period) begin on the rising edge of XCLKOUT. When necessary, the device inserts an alignment cycle before
an access to meet this requirement.
B. During alignment cycles, all signals will transition to their inactive state.
C. During inactive cycles, the XINTF address bus always holds the last address put out on the bus except XA0, which remains high. This
includes alignment cycles.
D. Timings are also relevant for XCLKOUT = 1/2 XTIMCLK and XCLKOUT = 1/4 XTIMCLK.
E. XWE1 is used in 32-bit data bus mode only.
F. For each sample, setup time from the beginning of the access can be calculated as E = (XWRLEAD + XWRACTIVE + n –1) tc(XTIM)
tsu(XRDYsynchL)XCOH where n is the sample number: n = 1, 2, 3, and so forth.
–
G. Reference for the first sample is with respect to this point: F = (XWRLEAD + XWRACTIVE) tc(XTIM)
Figure 7-32. Write With Synchronous XREADY Access
XTIMING register parameters used for this example (based on 300-MHz system clock):
XRDLEAD
XRDACTIVE
XRDTRAIL
USEREADY
X2TIMING
XWRLEAD
XWRACTIVE
XWRTRAIL
READYMODE
N/A(1)
N/A(1)
N/A(1)
1
0
≥ 3
1
≥3
0 = XREADY
(Synch)
(1) N/A = "Don't care" for this example.
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WS (Async)
(A) (B)
(C)
Trail
Active
Lead 1
XCLKOUT = XTIMCLK(D)
t
t
d(XCOH-XZCSL)
d(XCOHL-XZCSH)
XZCS0, XZCS6, XZCS7
t
h(XRDYasynchH)XZCSH
t
d(XCOH-XA)
XA[0:19]
XRD
t
t
d(XCOHL-XWEH)
d(XCOHL-XWEL)
(E)
XWE0, XWE1
t
t
d(XCOH-XRNWL)
d(XCOHL-XRNWH)
XR/W
t
dis(XD)XRNW
t
d(XWEL-XD
)
t
h(XD)XWEH
t
en(XD)XWEL
XD[31:0], XD[15:0]
DOUT
t
su(XRDYasynchL)XCOHL
t
h(XRDYasynchL)
t
su(XRDYasynchH)XCOHL
XREADY(Asynch)
(F)
(G)
Legend:
= Don’t care. Signal can be high or low during this time.
A. All XINTF accesses (lead period) begin on the rising edge of XCLKOUT. When necessary, the device inserts an alignment cycle before
an access to meet this requirement.
B. During alignment cycles, all signals transition to their inactive state.
C. During inactive cycles, the XINTF address bus always holds the last address put out on the bus except XA0, which remains high. This
includes alignment cycles.
D. Timings are also relevant for XCLKOUT = 1/2 XTIMCLK and XCLKOUT = 1/4 XTIMCLK.
E. XWE1 is used in 32-bit data bus mode only.
F. For each sample, set up time from the beginning of the access can be calculated as: E = (XWRLEAD + XWRACTIVE -3 + n) tc(XTIM)
tsu(XRDYasynchL)XCOHL where n is the sample number: n = 1, 2, 3, and so forth.
–
G. Reference for the first sample is with respect to this point: F = (XWRLEAD + XWRACTIVE – 2) tc(XTIM)
Figure 7-33. Write With Asynchronous XREADY Access
XTIMING register parameters used for this example (based on 300-MHz system clock):
XRDLEAD
XRDACTIVE
XRDTRAIL
USEREADY
X2TIMING
XWRLEAD
XWRACTIVE
XWRTRAIL
READYMODE
N/A(1)
N/A(1)
N/A(1)
1
0
≥ 3
3
≥ 3
1 = XREADY
(Async)
(1) N/A = “Don’t care” for this example
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7.9.6.9 XHOLD and XHOLDA Timing
If the HOLD mode bit is set while XHOLD and XHOLDA are both low (external bus accesses granted), the
XHOLDA signal is forced high (at the end of the current cycle) and the external interface is taken out of high-
impedance mode.
On a reset ( XRS), the HOLD mode bit is set to 0. If the XHOLD signal is active low on a system reset, the bus
and all signal strobes must be in high-impedance mode, and the XHOLDA signal is also driven active low.
When HOLD mode is enabled and XHOLDA is active low (external bus grant active), the CPU can still execute
code from internal memory. If an access is made to the external interface, the CPU is stalled until the XHOLD
signal is removed.
An external DMA request, when granted, places the following signals in a high-impedance mode:
XA[19:0]
XZCS0
XZCS6
XZCS7
XD[31:0], XD[15:0]
XWE0, XWE1, XRD
XR/ W
All other signals not listed in this group remain in their default or functional operational modes during these
signal events.
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7.9.6.9.1 XHOLD/ XHOLDA Timing Requirements (1) (2) (3)
MIN
MAX
4tc(XTIM) + tc(XCO) + 20
4tc(XTIM) + 2tc(XCO) + 20
4tc(XTIM) + 20
UNIT
ns
td(HL-HiZ)
td(HL-HAL)
td(HH-HAH)
td(HH-BV)
Delay time, XHOLD low to Hi-Z on all address, data, and control
Delay time, XHOLD low to XHOLDA low
Delay time, XHOLD high to XHOLDA high
Delay time, XHOLD high to bus valid
ns
ns
6tc(XTIM) + 20
ns
(1) When a low signal is detected on XHOLD, all pending XINTF accesses will be completed before the bus is placed in a high-impedance
state.
(2) The state of XHOLD is latched on the rising edge of XTIMCLK.
(3) After the XHOLD is detected low or high, all bus transitions and XHOLDA transitions occur with respect to the rising edge of
XCLKOUT. Thus, for this mode where XCLKOUT = 1/2 XTIMCLK, the transitions can occur up to 1 XTIMCLK cycle earlier than the
maximum value specified.
XCLKOUT
t
d(HL-Hiz)
XHOLD
t
d(HH-HAH)
XHOLDA
t
d(HL-HAL)
t
d(HH-BV)
XR/W
High-Impedance
XZCS0, XZCS6, XZCS7
Valid
XA[19:0]
Valid
High-Impedance
XD[31:0], XD[15:0]
Valid
(A)
(B)
A. All pending XINTF accesses are completed.
B. Normal XINTF operation resumes.
Figure 7-34. External Interface Hold Waveform
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8 Detailed Description
8.1 Brief Descriptions
8.1.1 C28x CPU
The C2834x (C28x+FPU) family is a member of the TMS320C2000™ microcontroller unit (MCU) platform. The
C28x+FPU based controllers have the same 32-bit fixed-point architecture as TI's existing C28x MCUs, but also
include a single-precision (32-bit) IEEE 754 floating-point unit (FPU). It is a very efficient C/C++ engine,
enabling users to develop their system control software in a high-level language. It also enables math algorithms
to be developed using C/C++. The device is as efficient at DSP math tasks as it is at system control tasks . This
efficiency removes the need for a second processor in many systems. The 32 × 32-bit MAC 64-bit processing
capabilities enable the controller to handle higher numerical resolution problems efficiently. Add to this the fast
interrupt response with automatic context save of critical registers, resulting in a device that is capable of
servicing many asynchronous events with minimal latency. The device has an 8-level-deep protected pipeline
with pipelined memory accesses. This pipelining enables it to execute at high speeds without resorting to
expensive high-speed memories. Special branch-look-ahead hardware minimizes the latency for conditional
discontinuities. Special store conditional operations further improve performance.
8.1.2 Memory Bus (Harvard Bus Architecture)
As with many MCU type devices, multiple buses are used to move data between the memories and peripherals
and the CPU. The C28x memory bus architecture contains a program read bus, data read bus and data write
bus. The program read bus consists of 22 address lines and 32 data lines. The data read and write buses
consist of 32 address lines and 32 data lines each. The 32-bit-wide data buses enable single cycle 32-bit
operations. The multiple bus architecture, commonly termed Harvard Bus, enables the C28x to fetch an
instruction, read a data value and write a data value in a single cycle. All peripherals and memories attached to
the memory bus will prioritize memory accesses. Generally, the priority of memory bus accesses can be
summarized as follows:
Highest:
Data Writes
Program Writes
Data Reads
Program Reads
Fetches
(Simultaneous data and program writes cannot occur on the memory bus.)
(Simultaneous data and program writes cannot occur on the memory bus.)
(Simultaneous program reads and fetches cannot occur on the memory bus.)
(Simultaneous program reads and fetches cannot occur on the memory bus.)
Lowest:
8.1.3 Peripheral Bus
To enable migration of peripherals between various TI MCU family of devices, the C2834x devices adopt a
peripheral bus standard for peripheral interconnect. The peripheral bus bridge multiplexes the various buses that
make up the processor Memory Bus into a single bus consisting of 16 address lines and 16 or 32 data lines and
associated control signals. Three versions of the peripheral bus are supported. One version supports only 16-bit
accesses (called peripheral frame 2). Another version supports both 16- and 32-bit accesses (called peripheral
frame 1). The third version supports DMA access and both 16- and 32-bit accesses (called peripheral frame 3).
8.1.4 Real-Time JTAG and Analysis
The C2834x devices implement the standard IEEE 1149.1 JTAG interface. Additionally, the devices support real-
time mode of operation whereby the contents of memory, peripheral and register locations can be modified while
the processor is running and executing code and servicing interrupts. The user can also single step through
nontime-critical code while enabling time-critical interrupts to be serviced without interference. The device
implements the real-time mode in hardware within the CPU. This is a feature unique to the C2834x device,
requiring no software monitor. Additionally, special analysis hardware is provided that allows setting of hardware
breakpoint or data/address watch-points and generate various user-selectable break events when a match
occurs.
8.1.5 External Interface (XINTF)
This asynchronous interface consists of 20 address lines, 32 data lines, and three chip-select lines. The chip-
select lines are mapped to three external zones, Zones 0, 6, and 7. Each of the three zones can be programmed
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with a different number of wait states, strobe signal setup and hold timing and each zone can be programmed for
extending wait states externally or not. The programmable wait state, chip-select and programmable strobe
timing enables glueless interface to external memories and peripherals.
8.1.6 M0, M1 SARAMs
All C2834x devices contain these two blocks of single access memory, each 1K × 16 in size. The stack pointer
points to the beginning of block M1 on reset. The M0 and M1 blocks, like all other memory blocks on C28x
devices, are mapped to both program and data space. Hence, the user can use M0 and M1 to execute code or
for data variables. The partitioning is performed within the linker. The C28x device presents a unified memory
map to the programmer. This makes for easier programming in high-level languages.
8.1.7 L0, L1, L2, L3, L4, L5, L6, L7, H0, H1, H2, H3, H4, H5 SARAMs
The 2834x has up to 256K × 16 single-access RAM (SARAM) divided up into the following categories:
L0, L1, L2, L3, L4, L5 SARAM Blocks
Up to 48K × 16 of SARAM at all frequencies. Each block is 8K × 16.
L6, L7 SARAM Blocks
These 8K × 16 SARAM blocks are single-wait state at all frequencies.
H0, H1, H2, H3, H4, H5 SARAM Blocks
H0–H5 are each 32K × 16 and 1-wait state at all frequencies. A program-access
prefetch buffer is used to improve performance of linear code.
All SARAM blocks are mapped to both program and data space. L0–L7 are accessible by both the CPU and the
DMA (1 wait state).
8.1.8 Boot ROM
The Boot ROM is factory-programmed with boot-loading software. Boot-mode signals are provided to tell the
bootloader software what boot mode to use on power up. The user can select to boot normally or to download
new software from an external connection or to select boot software that is programmed in the internal ROM.
The Boot ROM also contains standard tables, such as SIN/COS waveforms, for use in math related algorithms.
Table 8-1. Boot Mode Selection
MODE
GPIO87/XA15
GPIO86/XA14
GPIO85/XA13
GPIO84/XA12
MODE(1)
F
E
D
C
B
A
9
8
7
6
5
4
3
2
1
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Secure boot(2)
SCI-A boot
SPI-A boot
I2C-A boot Timing 1
eCAN-A boot Timing 1
McBSP-A boot
Jump to XINTF x16
Reserved
eCAN-A boot Timing 2
Parallel GPIO I/O boot
Parallel XINTF boot
Jump to SARAM
Branch to check boot mode
I2C-A boot Timing 2
Reserved
TI Test Only
(1) All four GPIO pins have an internal pullup.
(2) This mode is available on secure devices only. See Section 8.1.9, Security.
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8.1.9 Security
The 128-bit password locations on these devices will always read back 0xFFFF. To preserve compatibility with
other C28x designs with code security, the password locations at 0x33FFF8–0x33FFFF must be read after a
device reset; otherwise, certain memory locations will be inaccessible. The Boot ROM code performs this read
during start-up. If during debug the Boot ROM is bypassed, then it is the responsibility of the application software
to read the password locations after a reset.
Custom Encryption: Activating the Code Security Module (CSM) and Emulation Code Security Logic
(ECSL)
Custom secure versions of these devices enable the CSM and ECSL logic. In the custom version, the 128-bit
password locations are set to a customer-chosen value, activating the Code Security Module (CSM), which
protects the Hx RAM memories from unauthorized access. Additionally, a TI-generated AES decryption routine is
embedded into an on-chip secure ROM, providing a method to secure application code that is stored externally.
Requests for custom secure versions are not accepted by TI anymore.
Note
THE CODE SECURITY MODULE (CSM) INCLUDED ON THIS DEVICE WAS DESIGNED TO
PASSWORD PROTECT THE DATA STORED IN THE ASSOCIATED MEMORY (Hx RAM) AND IS
WARRANTED BY TEXAS INSTRUMENTS (TI), IN ACCORDANCE WITH ITS STANDARD TERMS
AND CONDITIONS, TO CONFORM TO TI'S PUBLISHED SPECIFICATIONS FOR THE WARRANTY
PERIOD APPLICABLE FOR THIS DEVICE.
TI DOES NOT, HOWEVER, WARRANT OR REPRESENT THAT THE CSM CANNOT BE
COMPROMISED OR BREACHED OR THAT THE DATA STORED IN THE ASSOCIATED MEMORY
CANNOT BE ACCESSED THROUGH OTHER MEANS. MOREOVER, EXCEPT AS SET FORTH
ABOVE, TI MAKES NO WARRANTIES OR REPRESENTATIONS CONCERNING THE CSM OR
OPERATION OF THIS DEVICE, INCLUDING ANY IMPLIED WARRANTIES OF MERCHANTABILITY
OR FITNESS FOR A PARTICULAR PURPOSE.
IN NO EVENT SHALL TI BE LIABLE FOR ANY CONSEQUENTIAL, SPECIAL, INDIRECT,
INCIDENTAL, OR PUNITIVE DAMAGES, HOWEVER CAUSED, ARISING IN ANY WAY OUT OF
YOUR USE OF THE CSM OR THIS DEVICE, WHETHER OR NOT TI HAS BEEN ADVISED OF THE
POSSIBILITY OF SUCH DAMAGES. EXCLUDED DAMAGES INCLUDE, BUT ARE NOT LIMITED
TO LOSS OF DATA, LOSS OF GOODWILL, LOSS OF USE OR INTERRUPTION OF BUSINESS OR
OTHER ECONOMIC LOSS.
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8.1.10 Peripheral Interrupt Expansion (PIE) Block
The PIE block serves to multiplex numerous interrupt sources into a smaller set of interrupt inputs. The PIE block
can support up to 96 peripheral interrupts. On the C2834x, 64 of the possible 96 interrupts are used by
peripherals. The 96 interrupts are grouped into blocks of 8 and each group is fed into 1 of 12 CPU interrupt lines
(INT1 to INT12). Each of the 96 interrupts is supported by its own vector stored in a dedicated RAM block that
can be overwritten by the user. The vector is automatically fetched by the CPU on servicing the interrupt. It takes
eight CPU clock cycles to fetch the vector and save critical CPU registers. Hence the CPU can quickly respond
to interrupt events. Prioritization of interrupts is controlled in hardware and software. Each individual interrupt can
be enabled or disabled within the PIE block.
8.1.11 External Interrupts (XINT1–XINT7, XNMI)
The devices support eight masked external interrupts (XINT1–XINT7, XNMI). XNMI can be connected to the
INT13 or NMI interrupt of the CPU. Each of the interrupts can be selected for negative, positive, or both negative
and positive edge triggering and can also be enabled or disabled (including the XNMI). XINT1, XINT2, and XNMI
also contain a 16-bit free-running up counter, which is reset to zero when a valid interrupt edge is detected. This
counter can be used to accurately time-stamp the interrupt. Unlike the 281x devices, there are no dedicated pins
for the external interrupts. XINT1 XINT2, and XNMI interrupts can accept inputs from GPIO0–GPIO31 pins.
XINT3–XINT7 interrupts can accept inputs from GPIO32–GPIO63 pins.
8.1.12 Oscillator and PLL
The device can be clocked by an external oscillator or by a crystal attached to the on-chip oscillator circuit. A
PLL is provided supporting up to 31 input-clock-scaling ratios. The PLL ratios can be changed on-the-fly in
software, enabling the user to scale back on operating frequency if lower power operation is desired. Refer to
Section 7.9.4.4 for timing details. The PLL block can be set in bypass mode.
8.1.13 Watchdog
The devices contain a watchdog timer. The user software must regularly reset the watchdog counter within a
certain time frame; otherwise, the watchdog will generate a reset to the processor. The watchdog can be
disabled if necessary.
8.1.14 Peripheral Clocking
The clocks to each individual peripheral can be enabled or disabled so as to reduce power consumption when a
peripheral is not in use. Additionally, the system clock to the serial ports (except I2C and eCAN) blocks can be
scaled relative to the CPU clock. This enables the timing of peripherals to be decoupled from increasing CPU
clock speeds.
8.1.15 Low-Power Modes
The devices are full static CMOS devices. Three low-power modes are provided:
IDLE:
Place CPU into low-power mode. Peripheral clocks may be turned off selectively and only those peripherals that
need to function during IDLE are left operating. An enabled interrupt from an active peripheral or the watchdog
timer will wake the processor from IDLE mode.
STANDBY:
HALT:
Turns off clock to CPU and peripherals. This mode leaves the oscillator and PLL functional. An external interrupt
event will wake the processor and the peripherals. Execution begins on the next valid cycle after detection of the
interrupt event
Turns off the internal oscillator. This mode basically shuts down the device and places it in the lowest possible
power consumption mode. A reset or external signal can wake the device from this mode.
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8.1.16 Peripheral Frames 0, 1, 2, 3 (PFn)
The device segregates peripherals into four sections. The mapping of peripherals is as follows:
PF0:
PIE:
PIE Interrupt Enable and Control Registers Plus PIE Vector Table
External Interface Registers
XINTF:
DMA
DMA Registers
Timers:
eCAN:
GPIO:
ePWM:
eCAP:
eQEP:
SYS:
CPU-Timers 0, 1, 2 Registers
PF1:
eCAN Mailbox and Control Registers
GPIO MUX Configuration and Control Registers
Enhanced Pulse Width Modulator Module and Registers
Enhanced Capture Module and Registers
Enhanced Quadrature Encoder Pulse Module and Registers
System Control Registers
PF2:
SCI:
Serial Communications Interface (SCI) Control and RX/TX Registers
Serial Port Interface (SPI) Control and RX/TX Registers
External ADC Interface
SPI:
ADC:
I2C:
Inter-Integrated Circuit Module and Registers
External Interrupt Registers
XINT
PF3:
McBSP
Multichannel Buffered Serial Port Registers
8.1.17 General-Purpose Input/Output (GPIO) Multiplexer
Most of the peripheral signals are multiplexed with GPIO signals. This enables the user to use a pin as GPIO if
the peripheral signal or function is not used. On reset, GPIO pins are configured as inputs. The user can
individually program each pin for GPIO mode or peripheral signal mode. For specific inputs, the user can also
select the number of input qualification cycles. This is to filter unwanted noise glitches. The GPIO signals can
also be used to bring the device out of specific low-power modes.
8.1.18 32-Bit CPU-Timers (0, 1, 2)
CPU-Timers 0, 1, and 2 are identical 32-bit timers with presettable periods and with 16-bit clock prescaling. The
timers have a 32-bit count down register, which generates an interrupt when the counter reaches zero. The
counter is decremented at the CPU clock speed divided by the prescale value setting. When the counter reaches
zero, it is automatically reloaded with a 32-bit period value. CPU-Timer 2 is reserved for Real-Time OS (RTOS)/
BIOS applications. It is connected to INT14 of the CPU. If DSP/BIOS™ or SYS/BIOS is not being used, CPU-
Timer 2 is available for general use. CPU-Timer 1 is for general use and can be connected to INT13 of the CPU.
CPU-Timer 0 is also for general use and is connected to the PIE block.
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8.1.19 Control Peripherals
The C2834x devices support the following peripherals which are used for embedded control and communication:
ePWM:
eCAP:
eQEP:
The enhanced PWM peripheral supports independent and complementary PWM generation, adjustable dead-
band generation for leading and trailing edges, latched and cycle-by-cycle trip mechanism. Some of the PWM
pins support HRPWM features.
The enhanced capture peripheral uses a 32-bit time base and registers up to four programmable events in
continuous/one-shot capture modes.
This peripheral can also be configured to generate an auxiliary PWM signal.
The enhanced QEP peripheral uses a 32-bit position counter, supports low-speed measurement using capture
unit and high-speed measurement using a 32-bit unit timer.
This peripheral has a watchdog timer to detect motor stall and input error detection logic to identify simultaneous
edge transition in QEP signals.
8.1.20 Serial Port Peripherals
The devices support the following serial communication peripherals:
eCAN:
This is the enhanced version of the CAN peripheral. It supports 32 mailboxes, time-stamping of messages, and is
compliant with ISO 11898-1 (CAN 2.0B).
McBSP:
The multichannel buffered serial port (McBSP) connects to E1/T1 lines, phone-quality codecs for modem
applications or high-quality stereo audio DAC devices. The McBSP receive and transmit registers are supported
by the DMA to significantly reduce the overhead for servicing this peripheral. Each McBSP module can be
configured as an SPI as required.
SPI:
The SPI is a high-speed, synchronous serial I/O port that allows a serial bit stream of programmed length (1 to
16 bits) to be shifted into and out of the device at a programmable bit-transfer rate. Normally, the SPI is used for
communications between the MCU and external peripherals or another processor. Typical applications include
external I/O or peripheral expansion through devices such as shift registers, display drivers, and ADCs.
Multidevice communications are supported by the master/slave operation of the SPI. The SPI contains a 16-level
receive and transmit FIFO for reducing interrupt servicing overhead.
SCI:
I2C:
The serial communications interface is a 2-wire asynchronous serial port, commonly known as UART. The SCI
contains a 16-level receive and transmit FIFO for reducing interrupt servicing overhead.
The inter-integrated circuit (I2C) module provides an interface between an MCU and other devices compliant with
Philips Semiconductors Inter-IC bus (I2C-bus) specification version 2.1 and connected by way of an I2C-bus.
External components attached to this 2-wire serial bus can transmit/receive up to 8-bit data to/from the MCU
through the I2C module. The I2C contains a 16-level receive and transmit FIFO for reducing interrupt servicing
overhead.
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8.2 Peripherals
The integrated peripherals are described in the following subsections:
•
•
•
6-channel Direct Memory Access (DMA)
Three 32-bit CPU-Timers
Up to nine enhanced PWM modules (ePWM1, ePWM2, ePWM3, ePWM4, ePWM5, ePWM6, ePWM7,
ePWM8, ePWM9)
•
•
•
•
•
•
•
•
•
•
Up to six enhanced capture modules (eCAP1, eCAP2, eCAP3, eCAP4, eCAP5, eCAP6)
Up to three enhanced QEP modules (eQEP1, eQEP2, eQEP3)
External analog-to-digital converter (ADC) Interface
Up to two enhanced controller area network (eCAN) modules (eCAN-A, eCAN-B)
Up to three serial communications interface modules (SCI-A, SCI-B, SCI-C)
Up to two serial peripheral interface (SPI) modules (SPI-A, SPI-D)
Inter-integrated circuit (I2C) module
Up to two multichannel buffered serial port (McBSP-A, McBSP-B) modules
Digital I/O and shared pin functions
External Interface (XINTF)
8.2.1 DMA Overview
Features:
•
•
6 channels with independent PIE interrupts
Trigger sources:
– McBSP-A and McBSP-B transmit and receive logic
– XINT1–7 and XINT13
– CPU timers
– Software
•
Data sources and destinations:
– L0–L7 64K × 16 SARAM
– All XINTF zones
– McBSP-A and McBSP-B transmit and receive buffers
Word Size: 16-bit or 32-bit (McBSPs limited to 16-bit)
Throughput: 4 cycles/word (5 cycles/word for McBSP reads)
•
•
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CPU bus
INT7
L0
I/F
L0 RAM
L1 RAM
L2 RAM
L3 RAM
L4 RAM
L5 RAM
L6 RAM
L7 RAM
External
interrupts
CPU
timers
PIE
L1
I/F
L2
I/F
L3
I/F
CPU
L4
I/F
McBSP A
Event
triggers
DMA
6-ch
L5
I/F
PF3
I/F
L6
I/F
McBSP B
L7
I/F
DMA bus
Figure 8-1. DMA Functional Block Diagram
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8.2.2 32-Bit CPU-Timer 0, CPU-Timer 1, CPU-Timer 2
There are three 32-bit CPU-timers on the devices (CPU-Timer 0, CPU-Timer 1, CPU-Timer 2).
CPU-Timer 2 is reserved for DSP/BIOS or SYS/BIOS. CPU-Timer 0 and CPU-Timer 1 can be used in user
applications. These timers are different from the timers that are present in the ePWM modules.
Note
If the application is not using DSP/BIOS or SYS/BIOS, then CPU-Timer 2 can be used in the
application.
Reset
Timer Reload
16-Bit Timer Divide-Down
32-Bit Timer Period
TDDRH:TDDR
PRDH:PRD
16-Bit Prescale Counter
PSCH:PSC
SYSCLKOUT
TCR.4
(Timer Start Status)
32-Bit Counter
TIMH:TIM
Borrow
Borrow
TINT
Figure 8-2. CPU-Timers
The timer interrupt signals ( TINT0, TINT1, TINT2) are connected as shown in Figure 8-3.
INT1
TINT0
PIE
CPU-TIMER 0
to
INT12
28x
CPU
TINT1
CPU-TIMER 1
INT13
INT14
XINT13
CPU-TIMER 2
(Reserved for
DSP/BIOS or SYS/BIOS)
TINT2
A. The timer registers are connected to the memory bus of the C28x processor.
B. The timing of the timers is synchronized to SYSCLKOUT of the processor clock.
Figure 8-3. CPU-Timer Interrupt Signals and Output Signal
The general operation of the timer is as follows: The 32-bit counter register "TIMH:TIM" is loaded with the value
in the period register "PRDH:PRD". The counter register decrements at the SYSCLKOUT rate of the C28x.
When the counter reaches 0, a timer interrupt output signal generates an interrupt pulse. The registers listed in
Table 8-2 are used to configure the timers. For more information, see the TMS320x2834x Delfino System
Control and Interrupts Reference Guide .
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Table 8-2. CPU-Timers 0, 1, 2 Configuration and Control Registers
NAME
ADDRESS
0x0C00
0x0C01
0x0C02
0x0C03
0x0C04
0x0C05
0x0C06
0x0C07
0x0C08
0x0C09
0x0C0A
0x0C0B
0x0C0C
0x0C0D
0x0C0E
0x0C0F
0x0C10
0x0C11
SIZE (x16)
DESCRIPTION
TIMER0TIM
TIMER0TIMH
TIMER0PRD
TIMER0PRDH
TIMER0TCR
Reserved
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
40
CPU-Timer 0, Counter Register
CPU-Timer 0, Counter Register High
CPU-Timer 0, Period Register
CPU-Timer 0, Period Register High
CPU-Timer 0, Control Register
TIMER0TPR
TIMER0TPRH
TIMER1TIM
TIMER1TIMH
TIMER1PRD
TIMER1PRDH
TIMER1TCR
Reserved
CPU-Timer 0, Prescale Register
CPU-Timer 0, Prescale Register High
CPU-Timer 1, Counter Register
CPU-Timer 1, Counter Register High
CPU-Timer 1, Period Register
CPU-Timer 1, Period Register High
CPU-Timer 1, Control Register
TIMER1TPR
TIMER1TPRH
TIMER2TIM
TIMER2TIMH
TIMER2PRD
TIMER2PRDH
TIMER2TCR
Reserved
CPU-Timer 1, Prescale Register
CPU-Timer 1, Prescale Register High
CPU-Timer 2, Counter Register
CPU-Timer 2, Counter Register High
CPU-Timer 2, Period Register
0x0C12
0x0C13
0x0C14
0x0C15
0x0C16
0x0C17
0x0C18 – 0x0C3F
CPU-Timer 2, Period Register High
CPU-Timer 2, Control Register
TIMER2TPR
TIMER2TPRH
Reserved
CPU-Timer 2, Prescale Register
CPU-Timer 2, Prescale Register High
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8.2.3 Enhanced PWM Modules
The devices contain up to nine enhanced PWM (ePWM) modules (ePWM1 to ePWM9). Figure 8-4 shows a
block diagram of multiple ePWM modules. Figure 8-5 shows the signal interconnections with the ePWM.
Table 8-3 and Table 8-4 show the complete ePWM register set per module .
EXTSOC1A
POLSEL
0
EXTSOC1A
1
ePWM1SOCA
ePWM1
EXTSOC1B
POLSEL
ePWM1SOCB
ePWM2SOCA
ePWM2
0
1
ePWM2SOCB
EXTSOC1B
ePWM3SOCA
ePWM3
ePWM4
ePWM5
ePWM6
ePWM7
ePWM8
ePWM9
EXTSOC2A
POLSEL
ePWM3SOCB
ePWM4SOCA
0
ePWM4SOCB
EXTSOC2A
1
ePWM5SOCA
ePWM5SOCB
EXTSOC2B
POLSEL
ePWM6SOCA
ePWM6SOCB
0
EXTSOC2B
1
ePWM7SOCA
ePWM7SOCB
EXTSOC3A
POLSEL
ePWM8SOCA
ePWM8SOCB
0
1
EXTSOC3A
ePWM9SOCA
ePWM9SOCB
EXTSOC3B
POLSEL
0
1
EXTSOC3B
Figure 8-4. Generation of SOC Pulses to the External ADC Module
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Table 8-3. ePWM1–ePWM4 Control and Status Registers
SIZE (x16) /
#SHADOW
ePWM1
ePWM2
ePWM3
ePWM4
DESCRIPTION
Time Base Control Register
TBCTL
0x6800
0x6801
0x6802
0x6803
0x6804
0x6805
0x6807
0x6808
0x6809
0x680A
0x680B
0x680C
0x680D
0x680E
0x680F
0x6810
0x6840
0x6841
0x6842
0x6843
0x6844
0x6845
0x6847
0x6848
0x6849
0x684A
0x684B
0x684C
0x684D
0x684E
0x684F
0x6850
0x6880
0x6881
0x6882
0x6883
0x6884
0x6885
0x6887
0x6888
0x6889
0x688A
0x688B
0x688C
0x688D
0x688E
0x688F
0x6890
0x68C0
0x68C1
0x68C2
0x68C3
0x68C4
0x68C5
0x68C7
0x68C8
0x68C9
0x68CA
0x68CB
0x68CC
0x68CD
0x68CE
0x68CF
0x68D0
1 / 0
1 / 0
1 / 0
1 / 0
1 / 0
1 / 1
1 / 0
1 / 1
1 / 1
1 / 1
1 / 0
1 / 0
1 / 0
1 / 1
1 / 1
TBSTS
Time Base Status Register
TBPHSHR
TBPHS
Time Base Phase HRPWM Register
Time Base Phase Register
TBCTR
Time Base Counter Register
TBPRD
CMPCTL
CMPAHR
CMPA
Time Base Period Register Set
Counter Compare Control Register
Time Base Compare A HRPWM Register
Counter Compare A Register Set
CMPB
Counter Compare B Register Set
AQCTLA
AQCTLB
AQSFRC
AQCSFRC
DBCTL
Action Qualifier Control Register For Output A
Action Qualifier Control Register For Output B
Action Qualifier Software Force Register
Action Qualifier Continuous S/W Force Register Set
Dead-Band Generator Control Register
DBRED
Dead-Band Generator Rising Edge Delay Count
Register
1 / 0
1 / 0
DBFED
0x6811
0x6851
0x6891
0x68D1
Dead-Band Generator Falling Edge Delay Count
Register
TZSEL
TZCTL
TZEINT
TZFLG
TZCLR
TZFRC
ETSEL
ETPS
0x6812
0x6814
0x6815
0x6816
0x6817
0x6818
0x6819
0x681A
0x681B
0x681C
0x681D
0x681E
0x6820
0x6852
0x6854
0x6855
0x6856
0x6857
0x6858
0x6859
0x685A
0x685B
0x685C
0x685D
0x685E
0x6860
0x6892
0x6894
0x6895
0x6896
0x6897
0x6898
0x6899
0x689A
0x689B
0x689C
0x689D
0x689E
0x68A0
0x68D2
0x68D4
0x68D5
0x68D6
0x68D7
0x68D8
0x68D9
0x68DA
0x68DB
0x68DC
0x68DD
0x68DE
0x68E0
1 / 0
1 / 0
1 / 0
1 / 0
1 / 0
1 / 0
1 / 0
1 / 0
1 / 0
1 / 0
1 / 0
1 / 0
1 / 0
Trip Zone Select Register(1)
Trip Zone Control Register(1)
Trip Zone Enable Interrupt Register(1)
Trip Zone Flag Register
Trip Zone Clear Register(1)
Trip Zone Force Register(1)
Event Trigger Selection Register
Event Trigger Prescale Register
Event Trigger Flag Register
Event Trigger Clear Register
Event Trigger Force Register
PWM Chopper Control Register
HRPWM Configuration Register(1)
ETFLG
ETCLR
ETFRC
PCCTL
HRCNFG
(1) Registers that are EALLOW protected.
Table 8-4. ePWM5–ePWM9 Control and Status Registers
SIZE
(x16) /
#SHADO
W
NAME
ePWM5
ePWM6
ePWM7
ePWM8
ePWM9
DESCRIPTION
TBCTL
0x6900
0x6901
0x6902
0x6903
0x6904
0x6905
0x6907
0x6908
0x6940
0x6941
0x6942
0x6943
0x6944
0x6945
0x6947
0x6948
0x6980
0x6981
0x6982
0x6983
0x6984
0x6985
0x6987
0x6988
0x69C0
0x69C1
0x69C2
0x69C3
0x69C4
0x69C5
0x69C7
0x69C8
0x6600
0x6601
0x6602
0x6603
0x6604
0x6605
0x6607
0x6608
1 / 0
1 / 0
1 / 0
1 / 0
1 / 0
1 / 1
1 / 0
1 / 1
Time Base Control Register
TBSTS
Time Base Status Register
TBPHSHR
TBPHS
Time Base Phase HRPWM Register
Time Base Phase Register
TBCTR
Time Base Counter Register
TBPRD
Time Base Period Register Set
Counter Compare Control Register
Time Base Compare A HRPWM Register
CMPCTL
CMPAHR
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Table 8-4. ePWM5–ePWM9 Control and Status Registers (continued)
SIZE
(x16) /
#SHADO
W
NAME
ePWM5
ePWM6
ePWM7
ePWM8
ePWM9
DESCRIPTION
CMPA
0x6909
0x690A
0x690B
0x690C
0x690D
0x690E
0x6949
0x694A
0x694B
0x694C
0x694D
0x694E
0x6989
0x698A
0x698B
0x698C
0x698D
0x698E
0x69C9
0x69CA
0x69CB
0x69CC
0x69CD
0x69CE
0x6609
0x660A
0x660B
0x660C
0x660D
0x660E
1 / 1
1 / 1
1 / 0
1 / 0
1 / 0
Counter Compare A Register Set
Counter Compare B Register Set
CMPB
AQCTLA
AQCTLB
AQSFRC
AQCSFRC
Action Qualifier Control Register For Output A
Action Qualifier Control Register For Output B
Action Qualifier Software Force Register
Action Qualifier Continuous S/W Force
Register Set
1 / 1
1 / 1
1 / 0
DBCTL
DBRED
0x690F
0x6910
0x694F
0x6950
0x698F
0x6990
0x69CF
0x69D0
0x660F
0x6610
Dead-Band Generator Control Register
Dead-Band Generator Rising Edge Delay
Count Register
DBFED
0x6911
0x6951
0x6991
0x69D1
0x6611
Dead-Band Generator Falling Edge Delay
Count Register
1 / 0
TZSEL
TZCTL
TZEINT
TZFLG
TZCLR
TZFRC
ETSEL
ETPS
0x6912
0x6914
0x6915
0x6916
0x6917
0x6918
0x6919
0x691A
0x691B
0x691C
0x691D
0x691E
0x6920
0x6952
0x6954
0x6955
0x6956
0x6957
0x6958
0x6959
0x695A
0x695B
0x695C
0x695D
0x695E
0x6960
0x6992
0x6994
0x6995
0x6996
0x6997
0x6998
0x6999
0x699A
0x699B
0x699C
0x699D
0x699E
0x69A0
0x69D2
0x69D4
0x69D5
0x69D6
0x69D7
0x69D8
0x69D9
0x69DA
0x69DB
0x69DC
0x69DD
0x69DE
0x69E0
0x6612
0x6614
0x6615
0x6616
0x6617
0x6618
0x6619
0x661A
0x661B
0x661C
0x661D
0x661E
0x6620
1 / 0
1 / 0
1 / 0
1 / 0
1 / 0
1 / 0
1 / 0
1 / 0
1 / 0
1 / 0
1 / 0
1 / 0
1 / 0
Trip Zone Select Register(1)
Trip Zone Control Register(1)
Trip Zone Enable Interrupt Register(1)
Trip Zone Flag Register
Trip Zone Clear Register(1)
Trip Zone Force Register(1)
Event Trigger Selection Register
Event Trigger Prescale Register
Event Trigger Flag Register
Event Trigger Clear Register
Event Trigger Force Register
PWM Chopper Control Register
HRPWM Configuration Register(1)
ETFLG
ETCLR
ETFRC
PCCTL
HRCNFG
(1) Registers that are EALLOW protected.
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Time−base (TB)
Sync
CTR=ZERO
CTR=CMPB
Disabled
in/out
select
Mux
TBPRD shadow (16)
TBPRD active (16)
EPWMxSYNCO
EPWMxSYNCI
CTR=PRD
TBCTL[SYNCOSEL]
TBCTL[PHSEN]
Counter
up/down
(16 bit)
TBCTL[SWFSYNC]
(software forced sync)
CTR=ZERO
CTR_Dir
TBCTR
active (16)
TBPHSHR (8)
16
8
CTR = PRD
CTR = ZERO
Phase
control
Event
trigger
and
interrupt
(ET)
EPWMxINT
TBPHS active (24)
CTR = CMPA
CTR = CMPB
CTR_Dir
EPWMxSOCA
EPWMxSOCB
Counter compare (CC)
CTR=CMPA
CMPAHR (8)
Action
qualifier
(AQ)
16
8
HRPWM
CMPA active (24)
EPWMA
EPWMB
EPWMxAO
CMPA shadow (24)
CTR=CMPB
Dead
band
(DB)
PWM
chopper
(PC)
Trip
zone
(TZ)
16
EPWMxBO
EPWMxTZINT
TZ1 to TZ6
CMPB active (16)
CMPB shadow (16)
CTR = ZERO
Figure 8-5. ePWM Submodules Showing Critical Internal Signal Interconnections
8.2.4 High-Resolution PWM (HRPWM)
The HRPWM module offers PWM resolution (time granularity) which is significantly better than what can be
achieved using conventionally derived digital PWM methods. The key points for the HRPWM module are:
•
•
Significantly extends the time resolution capabilities of conventionally derived digital PWM
Typically used when effective PWM resolution falls below approximately 9 or 10 bits. This occurs at PWM
frequencies greater than approximately 500 kHz when using a CPU/System clock of 300 MHz or
approximately 375 kHz when using a CPU/system clock of 200 MHz.
•
•
This capability can be used in both duty cycle and phase-shift control methods.
Finer time granularity control or edge positioning is controlled through extensions to the Compare A and
Phase registers of the ePWM module.
•
HRPWM capabilities are offered only on the A signal path of an ePWM module (that is, on the EPWMxA
output). EPWMxB output has conventional PWM capabilities.
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8.2.5 Enhanced CAP Modules
The device contains up to six enhanced capture (eCAP) modules (eCAP1 to eCAP6). Figure 8-6 shows a
functional block diagram of a module.
CTRPHS
(Phase Register - 32-bit)
APWM Mode
SYNCIn
CTR_OVF
OVF
CTR [0-31]
PRD [0-31]
CMP [0-31]
TSCTR
(Counter - 32-bit)
SYNCOut
PWM
Compare
Logic
Delta Mode
RST
32
CTR=PRD
CTR=CMP
CTR [0-31]
PRD [0-31]
32
32
LD1
CAP1
(APRD Active)
Polarity
Select
eCAPx
LD
APRD
Shadow
32
CMP [0-31]
32
Polarity
Select
LD2
32
CAP2
(ACMP Active)
LD
Event
Qualifier
ACMP
Shadow
Event
Prescale
32
Polarity
Select
LD3
LD4
32
32
CAP3
(APRD Shadow)
LD
CAP4
(ACMP Shadow)
Polarity
Select
LD
4
Capture Events
4
CEVT[1:4]
Interrupt
Trigger
and
Flag
Control
Continuous/
One-Shot
Capture Control
to PIE
CTR_OVF
CTR=PRD
CTR=CMP
Figure 8-6. eCAP Functional Block Diagram
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The eCAP modules are clocked at the SYSCLKOUT rate.
The clock enable bits (ECAP1ENCLK, ECAP2ENCLK, ECAP3ENCLK, ECAP4ENCLK, ECAP5ENCLK,
ECAP6ENCLK) in the PCLKCR1 register are used to turn off the eCAP modules individually (for low power
operation). Upon reset, ECAP1ENCLK, ECAP2ENCLK, ECAP3ENCLK, ECAP4ENCLK, ECAP5ENCLK, and
ECAP6ENCLK are set to low, indicating that the peripheral clock is off.
Table 8-5. eCAP Control and Status Registers
SIZE
(x16)
NAME
TSCTR
eCAP1
eCAP2
eCAP3
eCAP4
eCAP5
eCAP6
DESCRIPTION
Timestamp Counter
0x6A00
0x6A02
0x6A04
0x6A06
0x6A08
0x6A0A
0x6A20
0x6A22
0x6A24
0x6A26
0x6A28
0x6A2A
0x6A40
0x6A42
0x6A44
0x6A46
0x6A48
0x6A4A
0x6A60
0x6A62
0x6A64
0x6A66
0x6A68
0x6A6A
0x6A80
0x6A82
0x6A84
0x6A86
0x6A88
0x6A8A
0x6AA0
0x6AA2
0x6AA4
0x6AA6
0x6AA8
0x6AAA
2
2
2
2
2
2
CTRPHS
CAP1
Counter Phase Offset Value Register
Capture 1 Register
CAP2
Capture 2 Register
CAP3
Capture 3 Register
CAP4
Capture 4 Register
0x6A0C- 0x6A2C-0x6
0x6A4C-
0x6A52
0x6A6C-
0x6A72
0x6A8C-0 0x6AAC-
Reserved
8
Reserved
0x6A12
0x6A14
0x6A15
0x6A16
0x6A17
0x6A18
0x6A19
A32
x6A92
0x6A94
0x6A95
0x6A96
0x6A97
0x6A98
0x6A99
0x6AB2
0x6AB4
0x6AB5
0x6AB6
0x6AB7
0x6AB8
0x6AB9
ECCTL1
ECCTL2
ECEINT
ECFLG
ECCLR
ECFRC
0x6A34
0x6A35
0x6A36
0x6A37
0x6A38
0x6A39
0x6A54
0x6A55
0x6A56
0x6A57
0x6A58
0x6A59
0x6A74
0x6A75
0x6A76
0x6A77
0x6A78
0x6A79
1
1
1
1
1
1
Capture Control Register 1
Capture Control Register 2
Capture Interrupt Enable Register
Capture Interrupt Flag Register
Capture Interrupt Clear Register
Capture Interrupt Force Register
0x6A1A-
0x6A1F
0x6A3A-
0x6A3F
0x6A5A-
0x6A5F
0x6A7A-
0x6A7F
0x6A9A-0x 0x6ABA-
6A9F 0x6ABF
Reserved
6
Reserved
8.2.6 Enhanced QEP Modules
The device contains up to three enhanced quadrature encoder (eQEP) modules with 32-bit resolution (eQEP1,
eQEP2, eQEP3). Figure 8-7 shows the block diagram of the eQEP module.
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System Control
Registers
To CPU
EQEPxENCLK
SYSCLKOUT
QCPRD
QCAPCTL
16
QCTMR
16
16
Quadrature
Capture
Unit
QCTMRLAT
QCPRDLAT
(QCAP)
QUTMR
QUPRD
QWDTMR
QWDPRD
Registers
Used by
Multiple Units
32
16
QEPCTL
QEPSTS
QFLG
UTOUT
QWDOG
UTIME
QDECCTL
16
WDTOUT
EQEPxAIN
EQEPxBIN
EQEPxIIN
EQEPxA/XCLK
EQEPxB/XDIR
EQEPxI
QCLK
QDIR
QI
EQEPxINT
16
PIE
Position Counter/
Control Unit
(PCCU)
EQEPxIOUT
EQEPxIOE
EQEPxSIN
EQEPxSOUT
EQEPxSOE
Quadrature
Decoder
(QDU)
QS
GPIO
MUX
QPOSLAT
QPOSSLAT
QPOSILAT
PHE
PCSOUT
EQEPxS
32
32
16
QPOSCNT
QPOSINIT
QPOSMAX
QEINT
QFRC
QPOSCMP
QCLR
QPOSCTL
Enhanced QEP (eQEP) Peripheral
Figure 8-7. eQEP Functional Block Diagram
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Table 8-6 provides a summary of the eQEP registers.
Table 8-6. eQEP Control and Status Registers
eQEPx
SIZE(x16)/
#SHADOW
eQEP1
ADDRESS
eQEP2
ADDRESS
eQEP3
ADDRESS
NAME
REGISTER DESCRIPTION
QPOSCNT
QPOSINIT
QPOSMAX
QPOSCMP
QPOSILAT
QPOSSLAT
QPOSLAT
QUTMR
0x6B00
0x6B02
0x6B04
0x6B06
0x6B08
0x6B0A
0x6B0C
0x6B0E
0x6B10
0x6B12
0x6B13
0x6B14
0x6B15
0x6B16
0x6B17
0x6B18
0x6B19
0x6B1A
0x6B1B
0x6B1C
0x6B1D
0x6B1E
0x6B1F
0x6B20
0x6B40
0x6B42
0x6B44
0x6B46
0x6B48
0x6B4A
0x6B4C
0x6B4E
0x6B50
0x6B52
0x6B53
0x6B54
0x6B55
0x6B56
0x6B57
0x6B58
0x6B59
0x6B5A
0x6B5B
0x6B5C
0x6B5D
0x6B5E
0x6B5F
0x6B60
0x6B80
0x6B82
0x6B84
0x6B86
0x6B88
0x6B8A
0x6B8C
0x6B8E
0x6B90
0x6B92
0x6B93
0x6B94
0x6B95
0x6B96
0x6B97
0x6B98
0x6B99
0x6B9A
0x6B9B
0x6B9C
0x6B9D
0x6B9E
0x6B9F
0x6BA0
2/0
2/0
2/0
2/1
2/0
2/0
2/0
2/0
2/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
eQEP Position Counter
eQEP Initialization Position Count
eQEP Maximum Position Count
eQEP Position-compare
eQEP Index Position Latch
eQEP Strobe Position Latch
eQEP Position Latch
eQEP Unit Timer
QUPRD
eQEP Unit Period Register
eQEP Watchdog Timer
QWDTMR
QWDPRD
QDECCTL
QEPCTL
QCAPCTL
QPOSCTL
QEINT
eQEP Watchdog Period Register
eQEP Decoder Control Register
eQEP Control Register
eQEP Capture Control Register
eQEP Position-compare Control Register
eQEP Interrupt Enable Register
eQEP Interrupt Flag Register
eQEP Interrupt Clear Register
eQEP Interrupt Force Register
eQEP Status Register
QFLG
QCLR
QFRC
QEPSTS
QCTMR
eQEP Capture Timer
QCPRD
eQEP Capture Period Register
eQEP Capture Timer Latch
eQEP Capture Period Latch
QCTMRLAT
QCPRDLAT
0x6BBA1 -
0x6BBF
Reserved
0x6B21 - 0x6B3F 0x6B61 - 0x6B7F
31/0
8.2.7 External ADC Interface
The external ADC interface operation is configured, controlled, and monitored by the External SoC Configuration
Register (EXTSOCCFG) at address 0x702E. Figure 8-8 shows how the Start-of-Conversion signals for external
ADCs are generated by the on-chip PWM modules.
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EXTSOC1A
POLSEL
0
EXTSOC1A
1
ePWM1SOCA
ePWM1SOCB
ePWM1
ePWM2
ePWM3
ePWM4
ePWM5
ePWM6
ePWM7
ePWM8
ePWM9
EXTSOC1B
POLSEL
ePWM2SOCA
ePWM2SOCB
0
1
EXTSOC1B
ePWM3SOCA
EXTSOC2A
POLSEL
ePWM3SOCB
ePWM4SOCA
0
ePWM4SOCB
EXTSOC2A
1
ePWM5SOCA
ePWM5SOCB
EXTSOC2B
POLSEL
ePWM6SOCA
ePWM6SOCB
0
EXTSOC2B
1
ePWM7SOCA
ePWM7SOCB
EXTSOC3A
POLSEL
ePWM8SOCA
ePWM8SOCB
0
1
EXTSOC3A
ePWM9SOCA
ePWM9SOCB
EXTSOC3B
POLSEL
0
EXTSOC3B
1
Figure 8-8. External ADC Interface
Table 8-7. External ADC Interface Registers
NAME
DESCRIPTION
ADDRESS
EXTSOCCFG
External SoC Configuration Register
0x00 702E
8.2.8 Multichannel Buffered Serial Port (McBSP) Module
The McBSP module has the following features:
•
•
Compatible to McBSP in TMS320C54x/TMS320C55x DSP devices
Full-duplex communication
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•
•
•
•
•
•
•
•
Double-buffered data registers that allow a continuous data stream
Independent framing and clocking for receive and transmit
External shift clock generation or an internal programmable frequency shift clock
A wide selection of data sizes including 8, 12, 16, 20, 24, or 32 bits
8-bit data transfers with LSB or MSB first
Programmable polarity for both frame synchronization and data clocks
Highly programmable internal clock and frame generation
Direct interface to industry-standard CODECs, Analog Interface Chips (AICs), and other serially connected
A/D and D/A devices
•
•
Works with SPI-compatible devices
The following application interfaces can be supported on the McBSP:
– T1/E1 framers
– IOM-2 compliant devices
– AC97-compliant devices (the necessary multiphase frame synchronization capability is provided.)
– IIS-compliant devices
– SPI
•
McBSP clock rate,
CLKSRG
CLKG =
1+ CLKGDV
(
)
where CLKSRG source could be LSPCLK, CLKX, or CLKR. Serial port performance is limited by I/O buffer
switching speed. Internal prescalers must be adjusted such that the peripheral speed is less than the I/O
buffer speed limit.
Note
See Section 7 for maximum I/O pin toggling speed.
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Figure 8-9 shows the block diagram of the McBSP module.
TX
Interrupt
MXINT
Peripheral Write Bus
CPU
TX Interrupt Logic
To CPU
16
16
McBSP Transmit
Interrupt Select Logic
DXR2 Transmit Buffer
16
DXR1 Transmit Buffer
16
LSPCLK
MFSXx
MCLKXx
Compand Logic
XSR2
XSR1
MDXx
MDRx
CPU
DMA Bus
RSR1
16
RSR2
16
MCLKRx
Expand Logic
MFSRx
RBR2 Register
16
RBR1 Register
16
DRR2 Receive Buffer
DRR1 Receive Buffer
McBSP Receive
16
16
Interrupt Select Logic
RX
Interrupt
RX Interrupt Logic
MRINT
CPU
Peripheral Read Bus
To CPU
Figure 8-9. McBSP Module
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Table 8-8 provides a summary of the McBSP registers.
Table 8-8. McBSP Register Summary
McBSP-A
ADDRESS
McBSP-B
ADDRESS
NAME
TYPE
RESET VALUE
DESCRIPTION
Data Registers, Receive, Transmit
DRR2
0x5000
0x5001
0x5002
0x5003
0x5040
0x5041
0x5042
0x5043
R
R
0x0000
0x0000
0x0000
0x0000
McBSP Data Receive Register 2
DRR1
DXR2
DXR1
McBSP Data Receive Register 1
McBSP Data Transmit Register 2
McBSP Data Transmit Register 1
W
W
McBSP Control Registers
SPCR2
SPCR1
RCR2
0x5004
0x5005
0x5006
0x5007
0x5008
0x5009
0x500A
0x500B
0x5044
0x5045
0x5046
0x5047
0x5048
0x5049
0x504A
0x504B
R/W
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
McBSP Serial Port Control Register 2
R/W
R/W
R/W
R/W
R/W
R/W
R/W
McBSP Serial Port Control Register 1
McBSP Receive Control Register 2
McBSP Receive Control Register 1
McBSP Transmit Control Register 2
McBSP Transmit Control Register 1
McBSP Sample Rate Generator Register 2
McBSP Sample Rate Generator Register 1
RCR1
XCR2
XCR1
SRGR2
SRGR1
Multichannel Control Registers
MCR2
0x500C
0x500D
0x500E
0x500F
0x5010
0x5011
0x5012
0x5013
0x5014
0x5015
0x5016
0x5017
0x5018
0x5019
0x501A
0x501B
0x501C
0x501D
0x501E
0x5023
0x5024
0x504C
0x504D
0x504E
0x504F
0x5050
0x5051
0x5052
0x5053
0x5054
0x5055
0x5056
0x5057
0x5058
0x5059
0x505A
0x505B
0x505C
0x505D
0x505E
0x5063
0x5064
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
McBSP Multichannel Register 2
MCR1
McBSP Multichannel Register 1
RCERA
RCERB
XCERA
XCERB
PCR
McBSP Receive Channel Enable Register Partition A
McBSP Receive Channel Enable Register Partition B
McBSP Transmit Channel Enable Register Partition A
McBSP Transmit Channel Enable Register Partition B
McBSP Pin Control Register
RCERC
RCERD
XCERC
XCERD
RCERE
RCERF
XCERE
XCERF
RCERG
RCERH
XCERG
XCERH
MFFINT
MFFST
McBSP Receive Channel Enable Register Partition C
McBSP Receive Channel Enable Register Partition D
McBSP Transmit Channel Enable Register Partition C
McBSP Transmit Channel Enable Register Partition D
McBSP Receive Channel Enable Register Partition E
McBSP Receive Channel Enable Register Partition F
McBSP Transmit Channel Enable Register Partition E
McBSP Transmit Channel Enable Register Partition F
McBSP Receive Channel Enable Register Partition G
McBSP Receive Channel Enable Register Partition H
McBSP Transmit Channel Enable Register Partition G
McBSP Transmit Channel Enable Register Partition H
McBSP Interrupt Enable Register
McBSP Pin Status Register
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8.2.9 Enhanced Controller Area Network (eCAN) Modules (eCAN-A and eCAN-B)
The CAN module has the following features:
•
•
•
Fully compliant with ISO 11898-1 (CAN 2.0B)
Supports data rates up to 1 Mbps
Thirty-two mailboxes, each with the following properties:
– Configurable as receive or transmit
– Configurable with standard or extended identifier
– Has a programmable receive mask
– Supports data and remote frame
– Composed of 0 to 8 bytes of data
– Uses a 32-bit timestamp on receive and transmit message
– Protects against reception of new message
– Holds the dynamically programmable priority of transmit message
– Employs a programmable interrupt scheme with two interrupt levels
– Employs a programmable alarm on transmission or reception time-out
Low-power mode
Programmable wake-up on bus activity
Automatic reply to a remote request message
Automatic retransmission of a frame in case of loss of arbitration or error
•
•
•
•
•
32-bit local network time counter synchronized by a specific message (communication in conjunction with
mailbox 16)
•
Self-test mode
– Operates in a loopback mode receiving its own message. A "dummy" acknowledge is provided, thereby
eliminating the need for another node to provide the acknowledge bit.
Note
For a SYSCLKOUT of 300 MHz, the smallest bit rate possible is 11.719 kbps.
For a SYSCLKOUT of 200 MHz, the smallest bit rate possible is 7.8125 kbps.
The CAN has passed the conformance test per ISO/DIS 16845. Contact TI for test report and exceptions.
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eCAN0INT
eCAN1INT
Controls Address
Data
32
Enhanced CAN Controller
Message Controller
Mailbox RAM
(512 Bytes)
Memory Management
Unit
eCAN Memory
(512 Bytes)
Registers and
CPU Interface,
Receive Control Unit,
Timer Management Unit
32-Message Mailbox
of 4 x 32-Bit Words
Message Objects Control
32
32
32
eCAN Protocol Kernel
Receive Buffer
Transmit Buffer
Control Buffer
Status Buffer
SN65HVD23x
3.3-V CAN Transceiver
CAN Bus
Figure 8-10. eCAN Block Diagram and Interface Circuit
Table 8-9. 3.3-V eCAN Transceivers
SUPPLY
VOLTAGE
LOW-POWER
MODE
SLOPE
CONTROL
PART NUMBER
VREF
OTHER
TA
SN65HVD230Q
SN65HVD231Q
SN65HVD232Q
SN65HVD233
SN65HVD234
SN65HVD235
ISO1050
3.3 V
3.3 V
Standby
Sleep
Adjustable
Adjustable
None
Yes
–
–40°C to 125°C
–40°C to 125°C
–40°C to 125°C
–40°C to 125°C
–40°C to 125°C
–40°C to 125°C
–55°C to 105°C
Yes
–
3.3 V
None
None
None
None
None
None
–
3.3 V
Standby
Adjustable
Adjustable
Adjustable
None
Diagnostic Loopback
–
3.3 V
Standby and Sleep
Standby
3.3 V
Autobaud Loopback
3–5.5 V
None
•
•
•
•
•
Built-in isolation
Low-prop delay
Thermal shutdown
Fail-safe operation
Dominant time-out
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eCAN-A Control and Status Registers
Mailbox Enable - CANME
Mailbox Direction - CANMD
Transmission Request Set - CANTRS
Transmission Request Reset - CANTRR
Transmission Acknowledge - CANTA
Abort Acknowledge - CANAA
eCAN-A Memory (512 Bytes)
6000h
Received Message Pending - CANRMP
Received Message Lost - CANRML
Remote Frame Pending - CANRFP
Global Acceptance Mask - CANGAM
Control and Status Registers
603Fh
6040h
Local Acceptance Masks (LAM)
(32 x 32-Bit RAM)
607Fh
6080h
Master Control - CANMC
Message Object Timestamps (MOTS)
(32 x 32-Bit RAM)
Bit-Timing Configuration - CANBTC
60BFh
60C0h
Error and Status - CANES
Message Object Time-Out (MOTO)
(32 x 32-Bit RAM)
Transmit Error Counter - CANTEC
Receive Error Counter - CANREC
Global Interrupt Flag 0 - CANGIF0
Global Interrupt Mask - CANGIM
Global Interrupt Flag 1 - CANGIF1
Mailbox Interrupt Mask - CANMIM
Mailbox Interrupt Level - CANMIL
60FFh
eCAN-A Memory RAM (512 Bytes)
6100h-6107h
6108h-610Fh
6110h-6117h
6118h-611Fh
6120h-6127h
Mailbox 0
Mailbox 1
Mailbox 2
Mailbox 3
Mailbox 4
Overwrite Protection Control - CANOPC
TX I/O Control - CANTIOC
RX I/O Control - CANRIOC
Timestamp Counter - CANTSC
Time-Out Control - CANTOC
Time-Out Status - CANTOS
61E0h-61E7h
61E8h-61EFh
61F0h-61F7h
61F8h-61FFh
Mailbox 28
Mailbox 29
Mailbox 30
Mailbox 31
Reserved
Message Mailbox (16 Bytes)
Message Identifier - MSGID
Message Control - MSGCTRL
Message Data Low - MDL
Message Data High - MDH
61E8h-61E9h
61EAh-61EBh
61ECh-61EDh
61EEh-61EFh
Figure 8-11. eCAN-A Memory Map
Note
If the eCAN module is not used in an application, the RAM available (LAM, MOTS, MOTO, and
mailbox RAM) can be used as general-purpose RAM. The CAN module clock should be enabled for
this.
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eCAN-B Control and Status Registers
Mailbox Enable - CANME
Mailbox Direction - CANMD
Transmission Request Set - CANTRS
Transmission Request Reset - CANTRR
Transmission Acknowledge - CANTA
eCAN-B Memory (512 Bytes)
Abort Acknowledge - CANAA
Received Message Pending - CANRMP
Received Message Lost - CANRML
Remote Frame Pending - CANRFP
Global Acceptance Mask - CANGAM
6200h
Control and Status Registers
623Fh
6240h
Local Acceptance Masks (LAM)
(32 x 32-Bit RAM)
627Fh
6280h
Master Control - CANMC
Message Object Timestamps (MOTS)
(32 x 32-Bit RAM)
Bit-Timing Configuration - CANBTC
62BFh
62C0h
Error and Status - CANES
Message Object Time-Out (MOTO)
(32 x 32-Bit RAM)
Transmit Error Counter - CANTEC
Receive Error Counter - CANREC
Global Interrupt Flag 0 - CANGIF0
Global Interrupt Mask - CANGIM
Global Interrupt Flag 1 - CANGIF1
Mailbox Interrupt Mask - CANMIM
Mailbox Interrupt Level - CANMIL
62FFh
eCAN-B Memory RAM (512 Bytes)
6300h-6307h
6308h-630Fh
6310h-6317h
6318h-631Fh
6320h-6327h
Mailbox 0
Mailbox 1
Mailbox 2
Mailbox 3
Mailbox 4
Overwrite Protection Control - CANOPC
TX I/O Control - CANTIOC
RX I/O Control - CANRIOC
Timestamp Counter - CANTSC
Time-Out Control - CANTOC
Time-Out Status - CANTOS
63E0h-63E7h
63E8h-63EFh
63F0h-63F7h
63F8h-63FFh
Mailbox 28
Mailbox 29
Mailbox 30
Mailbox 31
Reserved
Message Mailbox (16 Bytes)
Message Identifier - MSGID
Message Control - MSGCTRL
Message Data Low - MDL
Message Data High - MDH
63E8h-63E9h
63EAh-63EBh
63ECh-63EDh
63EEh-63EFh
Figure 8-12. eCAN-B Memory Map
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The CAN registers listed in Table 8-10 are used by the CPU to configure and control the CAN controller and the
message objects. eCAN control registers only support 32-bit read/write operations. Mailbox RAM can be
accessed as 16 bits or 32 bits. Thirty-two-bit accesses are aligned to an even boundary.
Table 8-10. CAN Register Map (1)
eCAN-A
ADDRESS
eCAN-B
ADDRESS
SIZE
(x32)
REGISTER NAME
DESCRIPTION
CANME
0x6000
0x6002
0x6004
0x6006
0x6008
0x600A
0x600C
0x600E
0x6010
0x6012
0x6014
0x6016
0x6018
0x601A
0x601C
0x601E
0x6020
0x6022
0x6024
0x6026
0x6028
0x602A
0x602C
0x602E
0x6030
0x6032
0x6200
0x6202
0x6204
0x6206
0x6208
0x620A
0x620C
0x620E
0x6210
0x6212
0x6214
0x6216
0x6218
0x621A
0x621C
0x621E
0x6220
0x6222
0x6224
0x6226
0x6228
0x622A
0x622C
0x622E
0x6230
0x6232
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Mailbox enable
CANMD
Mailbox direction
CANTRS
CANTRR
CANTA
Transmit request set
Transmit request reset
Transmission acknowledge
Abort acknowledge
CANAA
CANRMP
CANRML
CANRFP
CANGAM
CANMC
Receive message pending
Receive message lost
Remote frame pending
Global acceptance mask
Master control
CANBTC
CANES
Bit-timing configuration
Error and status
CANTEC
CANREC
CANGIF0
CANGIM
CANGIF1
CANMIM
CANMIL
CANOPC
CANTIOC
CANRIOC
CANTSC
CANTOC
CANTOS
Transmit error counter
Receive error counter
Global interrupt flag 0
Global interrupt mask
Global interrupt flag 1
Mailbox interrupt mask
Mailbox interrupt level
Overwrite protection control
TX I/O control
RX I/O control
Timestamp counter (Reserved in SCC mode)
Time-out control (Reserved in SCC mode)
Time-out status (Reserved in SCC mode)
(1) These registers are mapped to Peripheral Frame 1.
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8.2.10 Serial Communications Interface (SCI) Modules (SCI-A, SCI-B, SCI-C)
The devices include three serial communications interface (SCI) modules. The SCI modules support digital
communications between the CPU and other asynchronous peripherals that use the standard nonreturn-to-zero
(NRZ) format. The SCI receiver and transmitter are double-buffered, and each has its own separate enable and
interrupt bits. Both can be operated independently or simultaneously in the full-duplex mode. To ensure data
integrity, the SCI checks received data for break detection, parity, overrun, and framing errors. The bit rate is
programmable to more than 65000 different speeds through a 16-bit baud-select register.
Features of each SCI module include:
•
Two external pins:
– SCITXD: SCI transmit-output pin
– SCIRXD: SCI receive-input pin
Note
Both pins can be used as GPIO if not used for SCI.
– Baud rate programmable to 64K different rates:
LSPCLK
Baud rate =
when BRR ¹ 0
when BRR = 0
(BRR + 1) * 8
LSPCLK
Baud rate =
16
Note
See Section 7 for maximum I/O pin toggling speed.
•
Data-word format
– One start bit
– Data-word length programmable from one to eight bits
– Optional even/odd/no parity bit
– One or two stop bits
•
•
•
•
•
Four error-detection flags: parity, overrun, framing, and break detection
Two wake-up multiprocessor modes: idle-line and address bit
Half- or full-duplex operation
Double-buffered receive and transmit functions
Transmitter and receiver operations can be accomplished through interrupt-driven or polled algorithms with
status flags.
– Transmitter: TXRDY flag (transmitter-buffer register is ready to receive another character) and TX EMPTY
flag (transmitter-shift register is empty)
– Receiver: RXRDY flag (receiver-buffer register is ready to receive another character), BRKDT flag (break
condition occurred), and RX ERROR flag (monitoring four interrupt conditions)
Separate enable bits for transmitter and receiver interrupts (except BRKDT)
NRZ (nonreturn-to-zero) format
•
•
Note
All registers in this module are 8-bit registers that are connected to Peripheral Frame 2. When a
register is accessed, the register data is in the lower byte (7-0), and the upper byte (15-8) is read as
zeros. Writing to the upper byte has no effect.
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Enhanced features:
•
•
Auto baud-detect hardware logic
16-level transmit/receive FIFO
The SCI port operation is configured and controlled by the registers listed in Table 8-11, Table 8-12, and Table
8-13.
Table 8-11. SCI-A Registers (1)
NAME
SCICCRA
ADDRESS
0x7050
0x7051
0x7052
0x7053
0x7054
0x7055
0x7056
0x7057
0x7059
0x705A
0x705B
0x705C
0x705F
SIZE (x16)
DESCRIPTION
SCI-A Communications Control Register
SCI-A Control Register 1
1
1
1
1
1
1
1
1
1
1
1
1
1
SCICTL1A
SCIHBAUDA
SCILBAUDA
SCICTL2A
SCI-A Baud Register, High Bits
SCI-A Baud Register, Low Bits
SCI-A Control Register 2
SCIRXSTA
SCIRXEMUA
SCIRXBUFA
SCITXBUFA
SCIFFTXA(2)
SCIFFRXA(2)
SCIFFCTA(2)
SCIPRIA
SCI-A Receive Status Register
SCI-A Receive Emulation Data Buffer Register
SCI-A Receive Data Buffer Register
SCI-A Transmit Data Buffer Register
SCI-A FIFO Transmit Register
SCI-A FIFO Receive Register
SCI-A FIFO Control Register
SCI-A Priority Control Register
(1) Registers in this table are mapped to Peripheral Frame 2 space. This space only allows 16-bit accesses. 32-bit accesses produce
undefined results.
(2) These registers are new registers for the FIFO mode.
Table 8-12. SCI-B Registers (1) (2)
NAME
SCICCRB
ADDRESS
0x7750
0x7751
0x7752
0x7753
0x7754
0x7755
0x7756
0x7757
0x7759
0x775A
0x775B
0x775C
0x775F
SIZE (x16)
DESCRIPTION
SCI-B Communications Control Register
SCI-B Control Register 1
1
1
1
1
1
1
1
1
1
1
1
1
1
SCICTL1B
SCIHBAUDB
SCILBAUDB
SCICTL2B
SCI-B Baud Register, High Bits
SCI-B Baud Register, Low Bits
SCI-B Control Register 2
SCIRXSTB
SCIRXEMUB
SCIRXBUFB
SCITXBUFB
SCIFFTXB(2)
SCIFFRXB(2)
SCIFFCTB(2)
SCIPRIB
SCI-B Receive Status Register
SCI-B Receive Emulation Data Buffer Register
SCI-B Receive Data Buffer Register
SCI-B Transmit Data Buffer Register
SCI-B FIFO Transmit Register
SCI-B FIFO Receive Register
SCI-B FIFO Control Register
SCI-B Priority Control Register
(1) Registers in this table are mapped to Peripheral Frame 2 space. This space only allows 16-bit accesses. 32-bit accesses produce
undefined results.
(2) These registers are new registers for the FIFO mode.
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Table 8-13. SCI-C Registers (1) (2)
NAME
ADDRESS
0x7770
0x7771
0x7772
0x7773
0x7774
0x7775
0x7776
0x7777
0x7779
0x777A
0x777B
0x777C
0x777F
SIZE (x16)
DESCRIPTION
SCI-C Communications Control Register
SCI-C Control Register 1
SCICCRC
1
1
1
1
1
1
1
1
1
1
1
1
1
SCICTL1C
SCIHBAUDC
SCILBAUDC
SCICTL2C
SCI-C Baud Register, High Bits
SCI-C Baud Register, Low Bits
SCI-C Control Register 2
SCIRXSTC
SCIRXEMUC
SCIRXBUFC
SCITXBUFC
SCIFFTXC(2)
SCIFFRXC(2)
SCIFFCTC(2)
SCIPRC
SCI-C Receive Status Register
SCI-C Receive Emulation Data Buffer Register
SCI-C Receive Data Buffer Register
SCI-C Transmit Data Buffer Register
SCI-C FIFO Transmit Register
SCI-C FIFO Receive Register
SCI-C FIFO Control Register
SCI-C Priority Control Register
Figure 8-13 shows the SCI module block diagram.
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SCICTL1.1
SCITXD
SCITXD
TXSHF
Register
Frame Format and Mode
TXENA
TX EMPTY
Parity
Even/Odd Enable
SCICTL2.6
8
SCICCR.6 SCICCR.5
TX INT ENA
TXRDY
Transmitter-Data
Buffer Register
SCICTL2.7
SCICTL2.0
8
TXWAKE
TXINT
To CPU
TX FIFO _0
SCICTL1.3
TX Interrupt Logic
TX FIFO _1
- - - - -
TX
FIFO
Interrupts
1
SCI TX Interrupt Select Logic
TX FIFO _15
WUT
SCITXBUF.7-0
TX FIFO Registers
SCIFFENA
AutoBaud Detect Logic
SCIRXD
SCIFFTX.14
SCIHBAUD. 15 - 8
Baud Rate
MSbyte
Register
SCIRXD
RXSHF Register
RXWAKE
LSPCLK
SCIRXST.1
SCILBAUD. 7 - 0
RXENA
SCICTL1.0
8
Baud Rate
LSbyte
Register
SCICTL2.1
RXRDY
RX/BK INT ENA
Receive-Data
Buffer Register
SCIRXBUF.7-0
SCIRXST.6
BRKDT
8
SCIRXST.5
RX FIFO _15
- - - - -
RX
FIFO
Interrupts
RX FIFO _1
RX FIFO _0
RXINT
To CPU
RX Interrupt Logic
SCIRXBUF.7-0
RX FIFO Registers
RXFFOVF
SCIRXST.7 SCIRXST.4 - 2
SCIFFRX.15
RX Error
FE OE PE
RX Error
RX ERR INT ENA
SCI RX Interrupt Select Logic
SCICTL1.6
Figure 8-13. Serial Communications Interface (SCI) Module Block Diagram
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8.2.11 Serial Peripheral Interface (SPI) Module (SPI-A, SPI-D)
The device includes the four-pin serial peripheral interface (SPI) module. Two SPI modules (SPI-A and SPI-D)
are available. The SPI is a high-speed, synchronous serial I/O port that allows a serial bit stream of programmed
length (1 to 16 bits) to be shifted into and out of the device at a programmable bit-transfer rate. Normally, the SPI
is used for communications between the MCU controller and external peripherals or another processor. Typical
applications include external I/O or peripheral expansion through devices such as shift registers, display drivers,
and ADCs. Multidevice communications are supported by the master/slave operation of the SPI.
The SPI module features include:
•
Four external pins:
– SPISOMI: SPI slave-output/master-input pin
– SPISIMO: SPI slave-input/master-output pin
– SPISTE: SPI slave transmit-enable pin
– SPICLK: SPI serial-clock pin
Note
All four pins can be used as GPIO if the SPI module is not used.
•
Two operational modes: master and slave
Baud rate: 125 different programmable rates.
LSPCLK
Baud rate =
when SPIBRR = 3 to127
when SPIBRR = 0,1, 2
(SPIBRR + 1)
LSPCLK
4
Baud rate =
Note
See Section 7 for maximum I/O pin toggling speed.
Data word length: 1 to 16 data bits
•
•
Four clocking schemes (controlled by clock polarity and clock phase bits) include:
– Falling edge without phase delay: SPICLK active-high. SPI transmits data on the falling edge of the
SPICLK signal and receives data on the rising edge of the SPICLK signal.
– Falling edge with phase delay: SPICLK active-high. SPI transmits data one half-cycle ahead of the falling
edge of the SPICLK signal and receives data on the falling edge of the SPICLK signal.
– Rising edge without phase delay: SPICLK inactive-low. SPI transmits data on the rising edge of the
SPICLK signal and receives data on the falling edge of the SPICLK signal.
– Rising edge with phase delay: SPICLK inactive-low. SPI transmits data one half-cycle ahead of the rising
edge of the SPICLK signal and receives data on the rising edge of the SPICLK signal.
Simultaneous receive and transmit operation (transmit function can be disabled in software)
Transmitter and receiver operations are accomplished through either interrupt-driven or polled algorithms.
Nine SPI module control registers: Located in control register frame beginning at address 7040h.
•
•
•
Note
All registers in this module are 16-bit registers that are connected to Peripheral Frame 2. When a
register is accessed, the register data is in the lower byte (7–0), and the upper byte (15–8) is read
as zeros. Writing to the upper byte has no effect.
Enhanced features:
•
•
16-level transmit/receive FIFO
Delayed transmit control
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The SPI port operation is configured and controlled by the registers listed in Table 8-14 and Table 8-15 .
Table 8-14. SPI-A Registers
SIZE (x16)
NAME
ADDRESS
0x7040
0x7041
0x7042
0x7044
0x7046
0x7047
0x7048
0x7049
0x704A
0x704B
0x704C
0x704F
DESCRIPTION(1)
SPICCR
SPICTL
SPISTS
SPIBRR
1
1
1
1
1
1
1
1
1
1
1
1
SPI-A Configuration Control Register
SPI-A Operation Control Register
SPI-A Status Register
SPI-A Baud Rate Register
SPIRXEMU
SPIRXBUF
SPITXBUF
SPIDAT
SPI-A Receive Emulation Buffer Register
SPI-A Serial Input Buffer Register
SPI-A Serial Output Buffer Register
SPI-A Serial Data Register
SPIFFTX
SPIFFRX
SPIFFCT
SPIPRI
SPI-A FIFO Transmit Register
SPI-A FIFO Receive Register
SPI-A FIFO Control Register
SPI-A Priority Control Register
(1) Registers in this table are mapped to Peripheral Frame 2. This space only allows 16-bit accesses. 32-bit accesses produce undefined
results.
Table 8-15. SPI-D Registers
SIZE (x16)
NAME
ADDRESS
0x7780
0x7781
0x7782
0x7784
0x7786
0x7787
0x7788
0x7789
0x778A
0x778B
0x778C
0x778F
DESCRIPTION(1)
SPICCR
SPICTL
SPISTS
SPIBRR
1
1
1
1
1
1
1
1
1
1
1
1
SPI-D Configuration Control Register
SPI-D Operation Control Register
SPI-D Status Register
SPI-D Baud Rate Register
SPIRXEMU
SPIRXBUF
SPITXBUF
SPIDAT
SPI-D Receive Emulation Buffer Register
SPI-D Serial Input Buffer Register
SPI-D Serial Output Buffer Register
SPI-D Serial Data Register
SPIFFTX
SPIFFRX
SPIFFCT
SPIPRI
SPI-D FIFO Transmit Register
SPI-D FIFO Receive Register
SPI-D FIFO Control Register
SPI-D Priority Control Register
(1) Registers in this table are mapped to Peripheral Frame 2. This space only allows 16-bit accesses. 32-bit accesses produce undefined
results.
Figure 8-14 is a block diagram of the SPI in slave mode.
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SPIFFENA
Overrun
INT ENA
Receiver
Overrun Flag
SPIFFTX.14
RX FIFO registers
SPIRXBUF
SPISTS.7
SPICTL.4
RX FIFO _0
RX FIFO _1
SPIINT/SPIRXINT
RX FIFO Interrupt
−−−−−
RX FIFO _15
RX Interrupt
Logic
16
SPIRXBUF
Buffer Register
SPIFFOVF FLAG
SPIFFRX.15
To CPU
TX FIFO registers
SPITXBUF
TX FIFO _15
TX Interrupt
Logic
TX FIFO Interrupt
−−−−−
TX FIFO _1
SPITXINT
TX FIFO _0
16
SPI INT
ENA
SPI INT FLAG
SPISTS.6
SPITXBUF
Buffer Register
16
SPICTL.0
16
M
S
M
SPIDAT
Data Register
S
SW1
SW2
SPISIMO
SPISOMI
M
S
M
SPIDAT.15 − 0
S
Talk
SPICTL.1
(A)
SPISTE
State Control
Master/Slave
SPICTL.2
SPI Char
SPICCR.3 − 0
S
3
2
1
0
SW3
Clock
Polarity
Clock
Phase
M
S
SPI Bit Rate
LSPCLK
SPICCR.6
SPICTL.3
SPICLK
SPIBRR.6 − 0
M
6
5
4
3
2
1
0
A. SPISTE is driven low by the master for a slave device.
Figure 8-14. SPI Module Block Diagram (Slave Mode)
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8.2.12 Inter-Integrated Circuit (I2C)
The device contains one I2C Serial Port. Figure 8-15 shows how the I2C peripheral module interfaces within the
device.
System Control Block
C28x CPU
I2CAENCLK
SYSCLKOUT
SYSRS
Control
Data[16]
Data[16]
SDAA
SCLA
I2C-A
Addr[16]
I2CINT1A
I2CINT2A
GPIO
MUX
PIE
Block
A. The I2C registers are accessed at the SYSCLKOUT rate. The internal timing and signal waveforms of the I2C port are also at the
SYSCLKOUT rate.
B. The clock enable bit (I2CAENCLK) in the PCLKCR0 register turns off the clock to the I2C port for low power operation. Upon reset,
I2CAENCLK is clear, which indicates the peripheral internal clocks are off.
Figure 8-15. I2C Peripheral Module Interfaces
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The I2C module has the following features:
•
Compliance with the Philips Semiconductors I2C-bus specification (version 2.1):
– Support for 1-bit to 8-bit format transfers
– 7-bit and 10-bit addressing modes
– General call
– START byte mode
– Support for multiple master-transmitters and slave-receivers
– Support for multiple slave-transmitters and master-receivers
– Combined master transmit/receive and receive/transmit mode
– Data transfer rate from 10 kbps up to 400 kbps (I2C Fast-mode rate)
One 16-word receive FIFO and one 16-word transmit FIFO
One interrupt that can be used by the CPU. This interrupt can be generated as a result of one of the following
conditions:
•
•
– Transmit-data ready
– Receive-data ready
– Register-access ready
– No-acknowledgment received
– Arbitration lost
– Stop condition detected
– Addressed as slave
•
•
•
An additional interrupt that can be used by the CPU when in FIFO mode
Module-enable and module-disable capability
Free data format mode
The registers in Table 8-16 configure and control the I2C port operation.
Table 8-16. I2C-A Registers
NAME
ADDRESS
0x7900
0x7901
0x7902
0x7903
0x7904
0x7905
0x7906
0x7907
0x7908
0x7909
0x790A
0x790C
0x7920
0x7921
–
DESCRIPTION
I2COAR
I2CIER
I2C own address register
I2C interrupt enable register
I2C status register
I2CSTR
I2CCLKL
I2CCLKH
I2CCNT
I2CDRR
I2CSAR
I2CDXR
I2CMDR
I2CISRC
I2CPSC
I2CFFTX
I2CFFRX
I2CRSR
I2CXSR
I2C clock low-time divider register
I2C clock high-time divider register
I2C data count register
I2C data receive register
I2C slave address register
I2C data transmit register
I2C mode register
I2C interrupt source register
I2C prescaler register
I2C FIFO transmit register
I2C FIFO receive register
I2C receive shift register (not accessible to the CPU)
I2C transmit shift register (not accessible to the CPU)
–
8.2.13 GPIO MUX
On the 2834x devices, the GPIO MUX can multiplex up to three independent peripheral signals on a single
GPIO pin in addition to providing individual pin bit-banging I/O capability. The GPIO MUX block diagram per pin
is shown in Figure 8-16. Because of the open-drain capabilities of the I2C pins, the GPIO MUX block diagram for
these pins differ. See the TMS320x2834x Delfino System Control and Interrupts Reference Guide for details.
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Note
There is a 2-SYSCLKOUT cycle delay from when the write to the GPxMUXn and GPxQSELn registers
occurs to when the action is valid.
GPIOXINT1SEL
GPIOXINT2SEL
GPIOXINT3SEL
GPIOLMPSEL
LPMCR0
GPIOXINT7SEL
GPIOXNMISEL
Low-Power
Modes Block
External Interrupt
MUX
PIE
GPxDAT (read)
Asynchronous
path
GPxQSEL1/2
GPxCTRL
GPxPUD
00
01
N/C
Peripheral 1 Input
Input
Qualification
Internal
Pullup
Peripheral 2 Input
Peripheral 3 Input
10
11
Asynchronous path
GPxTOGGLE
GPxCLEAR
GPxSET
GPIOx pin
00
01
10
11
GPxDAT (latch)
Peripheral 1 Output
Peripheral 2 Output
Peripheral 3 Output
High-Impedance
Output Control
00
01
GPxDIR (latch)
Peripheral 1 Output Enable
0 = Input, 1 = Output
XRS
Peripheral 2 Output Enable
Peripheral 3 Output Enable
10
11
= Default at Reset
GPxMUX1/2
A. x stands for the port, either A or B. For example, GPxDIR refers to either the GPADIR and GPBDIR register depending on the particular
GPIO pin selected.
B. GPxDAT latch/read are accessed at the same memory location.
C. This is a generic GPIO MUX block diagram. Not all options may be applicable for all GPIO pins. See the TMS320x2834x Delfino System
Control and Interrupts Reference Guide for pin-specific variations.
Figure 8-16. GPIO MUX Block Diagram
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The device supports 88 GPIO pins. The GPIO control and data registers are mapped to Peripheral Frame 1 to
enable 32-bit operations on the registers (along with 16-bit operations). Table 8-17 shows the GPIO register
mapping.
Table 8-17. GPIO Registers
NAME
ADDRESS
GPIO CONTROL REGISTERS (EALLOW PROTECTED)
0x6F80 GPIO A Control Register (GPIO0 to 31)
SIZE (x16)
DESCRIPTION
GPACTRL
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
8
2
2
2
2
18
GPAQSEL1
GPAQSEL2
GPAMUX1
GPAMUX2
GPADIR
0x6F82
0x6F84
GPIO A Qualifier Select 1 Register (GPIO0 to 15)
GPIO A Qualifier Select 2 Register (GPIO16 to 31)
GPIO A MUX 1 Register (GPIO0 to 15)
0x6F86
0x6F88
GPIO A MUX 2 Register (GPIO16 to 31)
0x6F8A
GPIO A Direction Register (GPIO0 to 31)
GPIO A Pullup Disable Register (GPIO0 to 31)
GPAPUD
0x6F8C
Reserved
GPBCTRL
GPBQSEL1
GPBQSEL2
GPBMUX1
GPBMUX2
GPBDIR
0x6F8E – 0x6F8F
0x6F90
GPIO B Control Register (GPIO32 to 63)
GPIO B Qualifier Select 1 Register (GPIO32 to 47)
GPIOB Qualifier Select 2 Register (GPIO48 to 63)
GPIO B MUX 1 Register (GPIO32 to 47)
0x6F92
0x6F94
0x6F96
0x6F98
GPIO B MUX 2 Register (GPIO48 to 63)
0x6F9A
GPIO B Direction Register (GPIO32 to 63)
GPIO B Pullup Disable Register (GPIO32 to 63)
GPBPUD
Reserved
GPCMUX1
GPCMUX2
GPCDIR
0x6F9C
0x6F9E – 0x6FA5
0x6FA6
GPIO C MUX1 Register (GPIO64 to 79)
GPIO C MUX2 Register (GPIO80 to 87)
GPIO C Direction Register (GPIO64 to 87)
GPIO C Pullup Disable Register (GPIO64 to 87)
0x6FA8
0x6FAA
GPCPUD
Reserved
0x6FAC
0x6FAE – 0x6FBF
GPIO DATA REGISTERS (NOT EALLOW PROTECTED)
GPADAT
0x6FC0
0x6FC2
2
2
2
2
2
2
2
2
2
2
2
2
8
GPIO A Data Register (GPIO0 to 31)
GPASET
GPIO A Data Set Register (GPIO0 to 31)
GPIO A Data Clear Register (GPIO0 to 31)
GPIO A Data Toggle Register (GPIO0 to 31)
GPIO B Data Register (GPIO32 to 63)
GPACLEAR
GPATOGGLE
GPBDAT
0x6FC4
0x6FC6
0x6FC8
GPBSET
0x6FCA
GPIO B Data Set Register (GPIO32 to 63)
GPIO B Data Clear Register (GPIO32 to 63)
GPIOB Data Toggle Register (GPIO32 to 63)
GPIO C Data Register (GPIO64 to 87)
GPIO C Data Set Register (GPIO64 to 87)
GPIO C Data Clear Register (GPIO64 to 87)
GPIO C Data Toggle Register (GPIO64 to 87)
GPBCLEAR
GPBTOGGLE
GPCDAT
0x6FCC
0x6FCE
0x6FD0
GPCSET
0x6FD2
GPCCLEAR
GPCTOGGLE
Reserved
0x6FD4
0x6FD6
0x6FD8 – 0x6FDF
GPIO INTERRUPT AND LOW-POWER MODES SELECT REGISTERS (EALLOW PROTECTED)
GPIOXINT1SEL
GPIOXINT2SEL
GPIOXNMISEL
GPIOXINT3SEL
GPIOXINT4SEL
0x6FE0
0x6FE1
0x6FE2
0x6FE3
0x6FE4
1
1
1
1
1
XINT1 GPIO Input Select Register (GPIO0 to 31)
XINT2 GPIO Input Select Register (GPIO0 to 31)
XNMI GPIO Input Select Register (GPIO0 to 31)
XINT3 GPIO Input Select Register (GPIO32 to 63)
XINT4 GPIO Input Select Register (GPIO32 to 63)
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Table 8-17. GPIO Registers (continued)
NAME
GPIOXINT5SEL
GPIOXINT6SEL
GPIOINT7SEL
GPIOLPMSEL
Reserved
ADDRESS
SIZE (x16)
DESCRIPTION
0x6FE5
0x6FE6
1
1
XINT5 GPIO Input Select Register (GPIO32 to 63)
XINT6 GPIO Input Select Register (GPIO32 to 63)
XINT7 GPIO Input Select Register (GPIO32 to 63)
LPM GPIO Select Register (GPIO0 to 31)
0x6FE7
1
0x6FE8
2
0x6FEA – 0x6FFF
22
Table 8-18. GPIO-A Mux Peripheral Selection Matrix
REGISTER BITS
PERIPHERAL SELECTION
GPADIR
GPADAT
GPASET
GPAMUX1
GPAQSEL1
GPIOx
GPAMUX1 = 0,0
PER1
GPAMUX1 = 0, 1
PER2
GPAMUX1 = 1, 0
PER3
GPAMUX1 = 1, 1
GPACLR
GPATOGGLE
0
1
1, 0
GPIO0 (I/O)
GPIO1 (I/O)
GPIO2 (I/O)
GPIO3 (I/O)
GPIO4 (I/O)
GPIO5 (I/O)
GPIO6 (I/O)
GPIO7 (I/O)
GPIO8 (I/O)
GPIO9 (I/O)
GPIO10 (I/O)
GPIO11 (I/O)
GPIO12 (I/O)
GPIO13 (I/O)
GPIO14 (I/O)
GPIO15 (I/O)
EPWM1A (O)
EPWM1B (O)
EPWM2A (O)
EPWM2B (O)
EPWM3A (O)
EPWM3B (O)
EPWM4A (O)
EPWM4B (O)
EPWM5A (O)
EPWM5B (O)
EPWM6A (O)
EPWM6B (O)
TZ1 (I)
Reserved
ECAP6 (I/O)
Reserved
Reserved
MFSRB (I/O)
Reserved
3, 2
2
5, 4
3
7, 6
ECAP5 (I/O)
Reserved
MCLKRB (I/O)
Reserved
QUALPRD0
4
9, 8
5
11, 10
13, 12
15, 14
17, 16
19, 18
21, 20
23, 22
25, 24
27, 26
29, 28
31, 30
MFSRA (I/O)
EPWMSYNCI (I)
MCLKRA (I/O)
CANTXB (O)
SCITXDB (O)
CANRXB (I)
SCIRXDB (I)
CANTXB (O)
CANRXB (I)
SCITXDB (O)
SCIRXDB (I)
ECAP1 (I/O)
EPWMSYNCO (O)
ECAP2 (I/O)
ADCSOCAO (O)
ECAP3 (I/O)
ADCSOCBO (O)
ECAP4 (I/O)
MDXB (O)
6
7
8
9
10
11
12
13
14
15
QUALPRD1
TZ2 (I)
MDRB (I)
TZ3 (I)/ XHOLD (I)
TZ4 (I)/ XHOLDA (O)
MCLKXB (I/O)
MFSXB (I/O)
GPAMUX2
GPAQSEL2
GPAMUX2 = 0, 0
GPAMUX2 = 0, 1
GPAMUX2 = 1, 0
GPAMUX2 = 1, 1
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
1, 0
GPIO16 (I/O)
GPIO17 (I/O)
GPIO18 (I/O)
GPIO19 (I/O)
GPIO20 (I/O)
GPIO21 (I/O)
GPIO22 (I/O)
GPIO23 (I/O)
GPIO24 (I/O)
GPIO25 (I/O)
GPIO26 (I/O)
GPIO27 (I/O)
GPIO28 (I/O)
GPIO29 (I/O)
GPIO30 (I/O)
GPIO31 (I/O)
SPISIMOA (I/O)
SPISOMIA (I/O)
SPICLKA (I/O)
SPISTEA (I/O)
EQEP1A (I)
CANTXB (O)
CANRXB (I)
SCITXDB (O)
SCIRXDB (I)
MDXA (O)
TZ5 (I)
3, 2
TZ6 (I)
5, 4
CANRXA (I)
CANTXA (O)
CANTXB (O)
CANRXB (I)
SCITXDB (O)
SCIRXDB (I)
MDXB (O)
7, 6
QUALPRD2
9, 8
11, 10
13, 12
15, 14
17, 16
19, 18
21, 20
23, 22
25, 24
27, 26
29, 28
31, 30
EQEP1B (I)
MDRA (I)
EQEP1S (I/O)
EQEP1I (I/O)
ECAP1 (I/O)
ECAP2 (I/O)
ECAP3 (I/O)
ECAP4 (I/O)
SCIRXDA (I)
SCITXDA (O)
CANRXA (I)
MCLKXA (I/O)
MFSXA (I/O)
EQEP2A (I)
EQEP2B (I)
EQEP2I (I/O)
EQEP2S (I/O)
MDRB (I)
MCLKXB (I/O)
MFSXB (I/O)
QUALPRD3
XZCS6 (O)
XA19 (O)
XA18 (O)
XA17 (O)
CANTXA (O)
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Table 8-19. GPIO-B Mux Peripheral Selection Matrix
REGISTER BITS
GPBDIR
PERIPHERAL SELECTION
GPBDAT
GPBSET
GPBCLR
GPBMUX1
GPBQSEL1
GPIOx
GPBMUX1 = 0, 0
PER1
GPBMUX1 = 0, 1
PER2
GPBMUX1 = 1, 0
PER3
GPBMUX1 = 1, 1
GPBTOGGLE
0
1
1, 0
GPIO32 (I/O)
GPIO33 (I/O)
GPIO34 (I/O)
GPIO35 (I/O)
GPIO36 (I/O)
GPIO37 (I/O)
GPIO38 (I/O)
GPIO39 (I/O)
GPIO40 (I/O)
GPIO41 (I/O)
GPIO42 (I/O)
GPIO43 (I/O)
GPIO44 (I/O)
GPIO45 (I/O)
GPIO46 (I/O)
GPIO47 (I/O)
SDAA (I/OC)(1)
SCLA (I/OC)(1)
ECAP1 (I/O)
SCITXDA (O)
SCIRXDA (I)
ECAP2 (I/O)
EPWMSYNCI (I)
ADCSOCAO (O)
ADCSOCBO (O)
3, 2
EPWMSYNCO (O)
2
5, 4
XREADY (I)
3
7, 6
XR/ W (O)
XZCS0 (O)
XZCS7 (O)
XWE0 (O)
XA16 (O)
XA0 (O)
QUALPRD0
4
9, 8
5
11, 10
13, 12
15, 14
17, 16
19, 18
21, 20
23, 22
25, 24
27, 26
29, 28
31, 30
6
7
8
9
XA1 (O)
10
11
12
13
14
15
XA2 (O)
Reserved
XA3 (O)
QUALPRD1
XA4 (O)
XA5 (O)
XA6 (O)
XA7 (O)
GPBMUX2
GPBQSEL2
GPBMUX2 = 0, 0
GPBMUX2 = 0, 1
GPBMUX2 = 1, 0
GPBMUX2 = 1, 1
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
1, 0
GPIO48 (I/O)
GPIO49 (I/O)
GPIO50 (I/O)
GPIO51 (I/O)
GPIO52 (I/O)
GPIO53 (I/O)
GPIO54 (I/O)
GPIO55 (I/O)
GPIO56 (I/O)
GPIO57 (I/O)
GPIO58 (I/O)
GPIO59 (I/O)
GPIO60 (I/O)
GPIO61 (I/O)
GPIO62 (I/O)
GPIO63 (I/O)
ECAP5 (I/O)
ECAP6 (I/O)
XD31 (I/O)
XD30 (I/O)
XD29 (I/O)
XD28 (I/O)
XD27 (I/O)
XD26 (I/O)
XD25 (I/O)
XD24 (I/O)
XD23 (I/O)
XD22 (I/O)
XD21 (I/O)
XD20 (I/O)
XD19 (I/O)
XD18 (I/O)
XD17 (I/O)
XD16 (I/O)
SPISIMOD (I/O)
SPISOMID (I/O)
SPICLKD (I/O)
SPISTED (I/O)
Reserved
3, 2
5, 4
EQEP1A (I)
7, 6
EQEP1B (I)
QUALPRD2
9, 8
EQEP1S (I/O)
EQEP1I (I/O)
SPISIMOA (I/O)
SPISOMIA (I/O)
SPICLKA (I/O)
SPISTEA (I/O)
MCLKRA (I/O)
MFSRA (I/O)
MCLKRB (I/O)
MFSRB (I/O)
SCIRXDC (I)
SCITXDC (O)
11, 10
13, 12
15, 14
17, 16
19, 18
21, 20
23, 22
25, 24
27, 26
29, 28
31, 30
Reserved
EQEP3A (I)
EQEP3B (I)
EQEP3S (I/O)
EQEP3I (I/O)
EPWM7A (O)
EPWM7B (O)
EPWM8A (O)
EPWM8B (O)
EPWM9A (O)
EPWM9B (O)
QUALPRD3
(1) Open drain
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Table 8-20. GPIO-C Mux Peripheral Selection Matrix
REGISTER BITS
PERIPHERAL SELECTION
GPCDIR
GPCDAT
GPCSET
GPIOx or PER1
GPCMUX1 = 0, 0 or 0, 1
PER2 or PER3
GPCMUX1 = 1, 0 or 1, 1
GPCMUX1
GPCCLR
GPCTOGGLE
0
1, 0
3, 2
GPIO64 (I/O)
GPIO65 (I/O)
GPIO66 (I/O)
GPIO67 (I/O)
GPIO68 (I/O)
GPIO69 (I/O)
GPIO70 (I/O)
GPIO71 (I/O)
GPIO72 (I/O)
GPIO73 (I/O)
GPIO74 (I/O)
GPIO75 (I/O)
GPIO76 (I/O)
GPIO77 (I/O)
GPIO78 (I/O)
GPIO79 (I/O)
GPCMUX2 = 0, 0 or 0, 1
GPIO80 (I/O)
GPIO81 (I/O)
GPIO82 (I/O)
GPIO83 (I/O)
GPIO84 (I/O)
GPIO85 (I/O)
GPIO86 (I/O)
GPIO87 (I/O)
XD15 (I/O)
XD14 (I/O)
XD13 (I/O)
XD12 (I/O)
XD11 (I/O)
XD10 (I/O)
XD9 (I/O)
1
2
3
4
5
6
7
8
9
5, 4
7, 6
no qual
9, 8
11, 10
13, 12
15, 14
17, 16
19, 18
21, 20
23, 22
25, 24
27, 26
29, 28
31, 30
GPCMUX2
1, 0
XD8 (I/O)
XD7 (I/O)
XD6 (I/O)
10
11
12
13
14
15
XD5 (I/O)
XD4 (I/O)
no qual
XD3 (I/O)
XD2 (I/O)
XD1 (I/O)
XD0 (I/O)
GPCMUX2 = 1, 0 or 1, 1
XA8 (O)
16
17
18
19
20
21
22
23
3, 2
XA9 (O)
5, 4
XA10 (O)
7, 6
XA11 (O)
no qual
9, 8
XA12 (O)
11, 10
13, 12
15, 14
XA13 (O)
XA14 (O)
XA15 (O)
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The user can select the type of input qualification for each GPIO pin through the GPxQSEL1/2 registers from
four choices:
•
Synchronization To SYSCLKOUT Only (GPxQSEL1/2 = 0, 0): This is the default mode of all GPIO pins at
reset and it simply synchronizes the input signal to the system clock (SYSCLKOUT).
•
Qualification Using Sampling Window (GPxQSEL1/2 = 0, 1 and 1, 0): In this mode the input signal, after
synchronization to the system clock (SYSCLKOUT), is qualified by a specified number of cycles before the
input is allowed to change.
Time Between Samples
GPyCTRL Reg
Input Signal
Qualified by
3 or 6 Samples
Qualification
GPIOx
SYNC
GPxQSEL
SYSCLKOUT
Number of Samples
Figure 8-17. Qualification Using Sampling Window
•
•
The sampling period is specified by the QUALPRD bits in the GPxCTRL register and is configurable in
groups of 8 signals. It specifies a multiple of SYSCLKOUT cycles for sampling the input signal. The sampling
window is either 3-samples or 6-samples wide and the output is only changed when all samples are the same
(all 0s or all 1s) as shown in Figure 8-17 (for 6-sample mode).
No Synchronization (GPxQSEL1/2 = 1,1): This mode is used for peripherals where synchronization is not
required (synchronization is performed within the peripheral).
Due to the multilevel multiplexing that is required on the device, there may be cases where a peripheral input
signal can be mapped to more then one GPIO pin. Also, when an input signal is not selected, the input signal will
default to either a 0 or 1 state, depending on the peripheral.
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8.2.14 External Interface (XINTF)
This section gives a top-level view of the external interface (XINTF) that is implemented on the C2834x devices.
The XINTF is a nonmultiplexed asynchronous bus, similar to the 2812 XINTF. The XINTF is mapped into three
fixed zones shown in Figure 8-18.
Data Space
Prog Space
0x0000−0000
XD(31:0)
XA(19:0)
XZCS0
0x0000−4000
0x0000−5000
XINTF Zone 0
(8K x 16)
0x0010−0000
0x0020−0000
0x0030−0000
XZCS6
XINTF Zone 6
(1M x 16)
XZCS7
XWE1
XINTF Zone 7
(1M x 16)
XWE0
XRD
XR/W
XREADY
XHOLD
XHOLDA
XCLKOUT
Figure 8-18. External Interface Block Diagram
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Figure 8-19 and Figure 8-20 show typical 16-bit and 32-bit data bus XINTF connections, illustrating how the
functionality of the XA0 and XWE1 signals change, depending on the configuration. Table 8-21 defines XINTF
configuration and control registers.
XINTF
External
wait-state
generator
XREADY
16-bits
XCLKOUT
XZCS0, XZCS6, XZCS7
CS
A(19:0)
XA(19:0)
XWE1
X
OE
WE
XRD
XWE0
D(15:0)
XD(15:0)
Figure 8-19. Typical 16-Bit Data Bus XINTF Connections
XINTF
External
wait-state
generator
XREADY
Low 16-bits
XCLKOUT
CS
A(18:0)
OE
X
XA(0)
XA(19:1)
XRD
WE
XWE0
XD(15:0)
D(15:0)
High 16-bits
A(18:0)
CS
OE
WE
XZCS0, XZCS6, XZCS7
XWE1
D(31:16)
XD(31:16)
Figure 8-20. Typical 32-Bit Data Bus XINTF Connections
Table 8-21. XINTF Configuration and Control Register Mapping
NAME
ADDRESS
0x00−0B20
0x00−0B2C
0x00−0B2E
0x00−0B34
0x00−0B38
0x00−0B3A
0x00−0B3D
SIZE (x16)
DESCRIPTION
XTIMING0
XTIMING6(1)
XTIMING7
XINTCNF2(2)
XBANK
2
2
2
2
1
1
1
XINTF Timing Register, Zone 0
XINTF Timing Register, Zone 6
XINTF Timing Register, Zone 7
XINTF Configuration Register
XINTF Bank Control Register
XINTF Revision Register
XREVISION
XRESET
XINTF Reset Register
(1) XTIMING1 - XTIMING5 are reserved for future expansion and are not currently used.
(2) XINTCNF1 is reserved and not currently used.
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8.3 Memory Maps
In Figure 8-21 to Figure 8-23, the following apply:
•
•
Memory blocks are not to scale.
Peripheral Frame 0, Peripheral Frame 1, Peripheral Frame 2, and Peripheral Frame 3 memory maps are
restricted to data memory only. A user program cannot access these memory maps in program space.
Protected means the order of "Write followed by Read" operations is preserved rather than the pipeline order.
See the TMS320x2834x Delfino System Control and Interrupts Reference Guide for more details.
Certain memory ranges are EALLOW protected against spurious writes after configuration.
•
•
•
If the eCAN module is not used in an application, the RAM available (LAM, MOTS, MOTO, and mailbox
RAM) can be used as general-purpose RAM. The CAN module clock should be enabled for this.
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Block
Start Address
On-Chip Memory
External Memory XINTF
Data Space
Prog Space
Data Space
Prog Space
0x00 0000
0x00 0040
M0 Vector - RAM (32 x 32)
(Enable if VMAP = 0)
M0 SARAM (1K x 16)
M1 SARA
0x00 0400
0x00 0800
Peripheral Frame 0
Reserved
0x00 0D00
PIE Vector - RAM
(256 x 16)
(Enabled if
VMAP = 1,
ENPIE =1)
Reserved
0x00 0E00
0x00 2000
Peripheral Frame 0
0x00 4000
0x00 5000
Res
0x00 5000
0x00 6000
0x00 7000
Peripheral Frame 3
(Protected) DMA Accessible
Peripheral Frame 1
(Protected)
Reserved
Peripheral Frame 2
(Protected)
0x00 8000
0x00 A000
0x00 C000
0x00 E000
0x01 0000
0x01 2000
0x01 4000
0x01 6000
0x01 8000
L0 SARAM (8K x 16, DMA Accessible)
L1 SARAM (8K x 16, DMA Accessible)
L2 SARAM (8K x 16, DMA Accessible)
L3 SARAM (8K x 16, DMA Accessible)
L4 SARAM (8K x 16, DMA Accessible)
L5 SARAM (8K x 16, DMA Accessible)
L6 SARAM (8K x 16, DMA Accessible)
L7 SARAM (8K x 16, DMA Accessible)
Reserved
0x10 0000
0x20 0000
0x30 0000
XINTF Zone 6 (1M x 16, XZCS6) (DMA Accessible)
XINTF Zone 7 (1M x 16, XZCS7) (DMA Accessible)
Reserved
0x30 0000
0x30 8000
0x31 0000
0x31 8000
0x32 0000
H0 SARAM
(32K x 16 Prefetch)
H1 SARAM
(32K x 16 Prefetch)
H2 SARAM
(32K x 16 Prefetch)
H3 SARAM
(32K x 16 Prefetch)
H4 SARAM
(32K x 16 Prefetch)
H5 SARAM
(32K x 16 Prefetch)
0x32 8000
0x33 0000
Reserved
Reserved
0x33 FFF8
0x33 FFFF
(A)
128-Bit Password
Reserved
0x3F E000
Boot ROM (8K x 16)
0x3F FFC0
BROM Vector - ROM (32 x 32)
(Enable if VMAP = 1, ENPIE = 0)
LEGEND:
Only one of these vector maps-M0 vector, PIE vector, BROM vector-should be enabled at a time.
A. These locations support compatibility with legacy C28x designs only. See Section 8.1.9.
Figure 8-21. C28346, C28345 Memory Map
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Block
On-Chip Memory
Start Address
External Memory XINTF
Data Space
Prog Space
Data Space
Prog Space
0x00 0000
0x00 0040
M0 Vector - RAM (32 x 32)
(Enable if VMAP = 0)
M0 SARAM (1K x 16)
M1 SARA
0x00 0400
0x00 0800
Peripheral Frame 0
Reserved
0x00 0D00
PIE Vector - RAM
(256 x 16)
(Enabled if
VMAP = 1,
ENPIE =1)
Reserved
0x00 0E00
0x00 2000
Peripheral Frame 0
0x00 4000
0x00 5000
XINTF Zone 0 (4K x 16, )
(Protected) DMA Accessible
Res
0x00 5000
0x00 6000
0x00 7000
Peripheral Frame 3
(Protected) DMA Accessible
Peripheral Frame 1
(Protected)
Reserved
Peripheral Frame 2
(Protected)
0x00 8000
0x00 A000
0x00 C000
0x00 E000
0x01 0000
0x01 2000
0x01 4000
0x01 6000
0x01 8000
L0 SARAM (8K x 16, DMA Accessible)
Reserved
L1 SARAM (8K x 16, DMA Accessible)
L2 SARAM (8K x 16, DMA Accessible)
L3 SARAM (8K x 16, DMA Accessible)
L4 SARAM (8K x 16, DMA Accessible)
L5 SARAM (8K x 16, DMA Accessible)
L6 SARAM (8K x 16, DMA Accessible)
L7 SARAM (8K x 16, DMA Accessible)
0x10 0000
0x20 0000
XINTF Zone 6 (1M x 16, XZCS6) (DMA Accessible)
XINTF Zone 7 (1M x 16, XZCS7) (DMA Accessible)
Reserved
0x30 0000
0x30 0000
0x30 8000
0x31 0000
H0 SARAM
(32K x 16 Prefetch)
H1 SARAM
(32K x 16 Prefetch)
Reserved
Reserved
0x33 FFF8
0x33 FFFF
(A)
128-Bit Password
Reserved
0x3F E000
0x3F FFC0
Boot ROM (8K x 16)
BROM Vector - ROM (32 x 32)
(Enable if VMAP = 1, ENPIE = 0)
LEGEND:
Only one of these vector maps-M0 vector, PIE vector, BROM vector-should be enabled at a time.
A. These locations support compatibility with legacy C28x designs only. See Section 8.1.9.
Figure 8-22. C28344, C28343 Memory Map
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Block
Start Address
On-Chip Memory
External Memory XINTF
Data Space
Prog Space
Data Space
Prog Space
0x00 0000
0x00 0040
M0 Vector - RAM (32 x 32)
(Enable if VMAP = 0)
M0 SARAM (1K x 16)
M1 SARA
0x00 0400
0x00 0800
Peripheral Frame 0
Reserved
0x00 0D00
PIE Vector - RAM
(256 x 16)
(Enabled if
VMAP = 1,
ENPIE =1)
Reserved
0x00 0E00
0x00 2000
Peripheral Frame 0
0x00 4000
0x00 5000
Res
0x00 5000
0x00 6000
0x00 7000
Peripheral Frame 3
(Protected) DMA Accessible
Peripheral Frame 1
(Protected)
Reserved
Peripheral Frame 2
(Protected)
0x00 8000
0x00 A000
0x00 C000
0x00 E000
0x01 0000
L0 SARAM (8K x 16, DMA Accessible)
Reserved
L1 SARAM (8K x 16, DMA Accessible)
L2 SARAM (8K x 16, DMA Accessible)
L3 SARAM (8K x 16, DMA Accessible)
Reserved
0x10 0000
0x20 0000
0x30 0000
XINTF Zone 6 (1M x 16, XZCS6) (DMA Accessible)
XINTF Zone 7 (1M x 16, XZCS7) (DMA Accessible)
0x30 0000
0x30 8000
0x31 0000
H0 SARAM
(32K x 16 Prefetch)
H1 SARAM
(32K x 16 Prefetch)
Reserved
Reserved
0x33 FFF8
0x33 FFFF
(A)
128-Bit Password
Reserved
0x3F E000
0x3F FFC0
Boot ROM (8K x 16)
BROM Vector - ROM (32 x 32)
(Enable if VMAP = 1, ENPIE = 0)
LEGEND:
Only one of these vector maps-M0 vector, PIE vector, BROM vector-should be enabled at a time.
A. These locations support compatibility with legacy C28x designs only. See Section 8.1.9.
Figure 8-23. C28342, C28341 Memory Map
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Peripheral Frame 1, Peripheral Frame 2, and Peripheral Frame 3 are grouped together to enable these blocks to
be write/read peripheral block protected. The protected mode ensures that all accesses to these blocks happen
as written. Because of the C28x pipeline, a write immediately followed by a read, to different memory locations,
will appear in reverse order on the memory bus of the CPU. This can cause problems in certain peripheral
applications where the user expected the write to occur first (as written). The C28x CPU supports a block
protection mode where a region of memory can be protected so as to make sure that operations occur as written
(the penalty is extra cycles are added to align the operations). This mode is programmable and by default, it will
protect the selected zones.
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The wait states for the various spaces in the memory map area are listed in Table 8-22.
Table 8-22. Wait States
WAIT STATES
(CPU)
WAIT STATES
(DMA)(1)
AREA
COMMENTS
M0 and M1 SARAMs
Peripheral Frame 0
0-wait
No access
No access (writes)
0-wait (reads)
0-wait (writes)
1-wait (reads)
Fixed
0-wait (writes)
1-wait (reads)
0-wait (writes)
2-wait (reads)
0-wait (writes)
Peripheral Frame 3
Peripheral Frame 1
Assumes no conflicts between CPU and DMA.
Cycles can be extended by peripheral generated ready.
No access
No access
Consecutive writes to the CAN will experience a 1-cycle
pipeline hit.
2-wait (reads)
Peripheral Frame 2
0-wait (writes)
2-wait (reads)
Fixed. Cycles cannot be extended by the peripheral.
L0 SARAM
L1 SARAM
L2 SARAM
L3 SARAM
L4 SARAM
L5 SARAM
L6 SARAM
L7 SARAM
0-wait data and
program
Assumes no CPU conflicts
1-wait
Assumes no conflicts between CPU and DMA
1-wait
Programmable
1-wait minimum
Programmed through the XTIMING registers or extendable
through external XREADY signal.
XINTF
1-wait is minimum wait states allowed on external waveforms
for both reads and writes on XINTF.
0-wait minimum writes
with write buffer
enabled
0-wait data (write)
0-wait data (read)
0-wait minimum for writes assumes write buffer enabled and
not full.
Assumes no conflicts between CPU and DMA. When DMA
and CPU try simultaneous conflict, 1-cycle delay is added for
arbitration.
H0 SARAM
H1 SARAM
H2 SARAM
H3 SARAM
H4 SARAM
H5 SARAM
Boot-ROM
1-wait
A program-access prefetch mechanism is enabled on these
memories to improve instruction fetch performance for linear
code execution.
No access
No access
1-wait
(1) The DMA has a base of four cycles/word.
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8.4 Register Map
The devices contain four peripheral register spaces. The spaces are categorized as follows:
Peripheral Frame 0:
Peripheral Frame 1
These are peripherals that are mapped directly to the CPU memory bus. See Table 8-23.
These are peripherals that are mapped to the 32-bit peripheral bus.
See Table 8-24.
Peripheral Frame 2:
Peripheral Frame 3:
These are peripherals that are mapped to the 16-bit peripheral bus.
See Table 8-25.
These are peripherals that are mapped to the 32-bit DMA-accessible peripheral bus. See Table 8-26.
Table 8-23. Peripheral Frame 0 Registers (1)
NAME
Device Emulation Registers
Code Security Module Registers
XINTF Registers
ADDRESS RANGE
0x00 0880 – 0x00 09FF
0x00 0AE0 – 0x00 0AEF
0x00 0B20 – 0x00 0B3F
SIZE (x16)
ACCESS TYPE(2)
EALLOW protected
384
16
EALLOW protected
32
Not EALLOW protected
CPU-Timer 0, CPU-Timer 1, CPU-Timer 2
Registers
0x00 0C00 – 0x00 0C3F
64
Not EALLOW protected
PIE Registers
0x00 0CE0 – 0x00 0CFF
0x00 0D00 – 0x00 0DFF
0x00 1000 – 0x00 11FF
32
Not EALLOW protected
EALLOW protected
EALLOW protected
PIE Vector Table
DMA Registers
256
512
(1) Registers in Frame 0 support 16-bit and 32-bit accesses.
(2) If registers are EALLOW protected, then writes cannot be performed until the EALLOW instruction is executed. The EDIS instruction
disables writes to prevent stray code or pointers from corrupting register contents.
Table 8-24. Peripheral Frame 1 Registers
NAME
ADDRESS RANGE
0x00 6000 – 0x00 61FF
0x00 6200 – 0x00 63FF
0x00 6800 – 0x00 683F
0x00 6840 – 0x00 687F
0x00 6880 – 0x00 68BF
0x00 68C0 – 0x00 68FF
0x00 6900 – 0x00 693F
0x00 6940 – 0x00 697F
0x00 6980 – 0x00 69BF
0x00 69C0 – 0x00 69FF
0x00 6600 – 0x00 663F
0x00 6A00 – 0x00 6A1F
0x00 6A20 – 0x00 6A3F
0x00 6A40 – 0x00 6A5F
0x00 6A60 – 0x00 6A7F
0x00 6A80 – 0x00 6A9F
0x00 6AA0 – 0x00 6ABF
0x00 6B00 – 0x00 6B3F
0x00 6B40 – 0x00 6B7F
0x00 6B80 – 0x00 6BBF
0x00 6F80 – 0x00 6FFF
SIZE (x16)
512
512
64
eCAN-A Registers
eCAN-B Registers
ePWM1 + HRPWM1 Registers
ePWM2 + HRPWM2 Registers
ePWM3 + HRPWM3 Registers
ePWM4 + HRPWM4 Registers
ePWM5 + HRPWM5 Registers
ePWM6 + HRPWM6 Registers
ePWM7 + HRPWM7 Registers
ePWM8 + HRPWM8 Registers
ePWM9 + HRPWM9 Registers
eCAP1 Registers
64
64
64
64
64
64
64
64
32
eCAP2 Registers
32
eCAP3 Registers
32
eCAP4 Registers
32
eCAP5 Registers
32
eCAP6 Registers
32
eQEP1 Registers
64
eQEP2 Registers
64
eQEP3 Registers
64
GPIO Registers
128
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Table 8-25. Peripheral Frame 2 Registers
NAME
ADDRESS RANGE
SIZE (x16)
System Control Registers
SPI-A Registers
0x00 7010 – 0x00 702F
0x00 7040 – 0x00 704F
0x00 7050 – 0x00 705F
0x00 7070 – 0x00 707F
0x00 7750 – 0x00 775F
0x00 7770 – 0x00 777F
0x00 7780 – 0x00 778F
0x00 7900 – 0x00 793F
32
16
16
16
16
16
16
64
SCI-A Registers
External Interrupt Registers
SCI-B Registers
SCI-C Registers
SPI-D Registers
I2C-A Registers
Table 8-26. Peripheral Frame 3 Registers
NAME
ADDRESS RANGE
SIZE (x16)
McBSP-A Registers
McBSP-B Registers
0x00 5000 – 0x00 503F
0x00 5040 – 0x00 507F
64
64
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8.4.1 Device Emulation Registers
These registers are used to control the protection mode of the C28x CPU and to monitor some critical device
signals. The registers are defined in Table 8-27.
Table 8-27. Device Emulation Registers
ADDRESS
RANGE
NAME
SIZE (x16)
DESCRIPTION
0x0880
0x0881
DEVICECNF
PARTID
2
1
Device Configuration Register
0x0882
Part ID Register
TMS320C28346
0xFFD0
TMS320C28345
TMS320C28344
TMS320C28343
TMS320C28342
TMS320C28341
0xFFD1
0xFFD2
0xFFD3
0xFFD4
0xFFD5
REVID
0x0883
1
Revision ID
Register
0x0000 - Silicon Rev. 0 - TMS
PROTSTART
PROTRANGE
0x0884
0x0885
1
1
Block Protection Start Address Register
Block Protection Range Address Register
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8.5 Interrupts
Figure 8-24 shows how the various interrupt sources are multiplexed.
Peripherals
(SPI, SCI, I2C, CAN, McBSP(A),
EPWM, ECAP, EQEP)
Clear
DMA
WDINT
Watchdog
Low Power Models
WAKEINT
DMA
Sync
LPMINT
SYSCLKOUT
XINT1
XINT1
Latch
Interrupt Control
XINT1CR(15:0)
XINT1CTR(15:0)
INT1
to
INT12
GPIOXINT1SEL(4:0)
C28
Core
XINT2
DMA
XINT2
Latch
Interrupt Control
XINT2CR(15:0)
XINT2CTR(15:0)
GPIOXINT2SEL(4:0)
DMA
TINT0
CPU Timer 0
DMA
TINT2
CPU Timer 2
CPU Timer 1
INT14
INT13
TINT1
GPIO0.int
XNMI_
XINT13
GPIO
Mux
Latch
Interrupt Control
XNMICR(15:0)
XNMICTR(15:0)
NMI
GPIO31.int
1
GPIOXNMISEL(4:0)
DMA
A. DMA-accessible
Figure 8-24. External and PIE Interrupt Sources
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DMA
XINT3
Interrupt Control
XINT3CR(15:0)
Latch
GPIOXINT3SEL(4:0)
DMA
XINT4
Interrupt Control
XINT4CR(15:0)
Latch
GPIOXINT4SEL(4:0)
DMA
XINT5
INT1
to
INT12
PIE
Latch
Interrupt Control
XINT5CR(15:0)
C28
Core
GPIOXINT5SEL(4:0)
DMA
XINT6
Interrupt Control
XINT6CR(15:0)
Latch
GPIOXINT6SEL(4:0)
DMA
XINT7
GPIO32.int
GPIO63.int
GPIO
Mux
Interrupt Control
XINT7CR(15:0)
Latch
GPIOXINT7SEL(4:0)
Figure 8-25. External Interrupts
Eight PIE block interrupts are grouped into one CPU interrupt. In total, 12 CPU interrupt groups, with 8 interrupts
per group equals 96 possible interrupts. On the C2834x devices, 64 of these are used by peripherals as shown
in Table 8-28.
The TRAP #VectorNumber instruction transfers program control to the interrupt service routine corresponding to
the vector specified. TRAP #0 tries to transfer program control to the address pointed to by the reset vector. The
PIE vector table does not, however, include a reset vector. Therefore, TRAP #0 should not be used when the
PIE is enabled. Doing so will result in undefined behavior.
When the PIE is enabled, TRAP #1 to TRAP #12 will transfer program control to the interrupt service routine
corresponding to the first vector within the PIE group. For example: TRAP #1 fetches the vector from INT1.1,
TRAP #2 fetches the vector from INT2.1, and so forth.
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IFR(12:1)
IER(12:1)
INTM
INT1
INT2
1
CPU
MUX
0
INT11
INT12
Global
Enable
(Flag)
(Enable)
INTx.1
INTx.2
INTx.3
INTx.4
INTx.5
From
Peripherals
or
External
Interrupts
INTx
MUX
INTx.6
INTx.7
INTx.8
PIEACKx
(Enable)
(Flag)
(Enable/Flag)
PIEIERx(8:1)
PIEIFRx(8:1)
Figure 8-26. Multiplexing of Interrupts Using the PIE Block
Table 8-28. PIE Peripheral Interrupts (1)
PIE INTERRUPTS
CPU
INTERRUPTS
INTx.8
INTx.7
INTx.6
INTx.5
INTx.4
INTx.3
INTx.2
INTx.1
WAKEINT
(LPM/WD)
TINT0
(TIMER 0)
INT1
INT2
INT3
INT4
INT5
INT6
INT7
INT8
INT9
INT10
INT11
INT12
Reserved
XINT2
XINT1
Reserved
Reserved
Reserved
EPWM8_TZINT
(ePWM8)
EPWM7_TZINT
(ePWM7)
EPWM6_TZINT
(ePWM6)
EPWM5_TZINT
(ePWM5)
EPWM4_TZINT
(ePWM4)
EPWM3_TZINT
(ePWM3)
EPWM2_TZINT
(ePWM2)
EPWM1_TZINT
(ePWM1)
EPWM8_INT
(ePWM8)
EPWM7_INT
(ePWM7)
EPWM6_INT
(ePWM6)
EPWM5_INT
(ePWM5)
EPWM4_INT
(ePWM4)
EPWM3_INT
(ePWM3)
EPWM2_INT
(ePWM2)
EPWM1_INT
(ePWM1)
ECAP6_INT
(eCAP6)
ECAP5_INT
(eCAP5)
ECAP4_INT
(eCAP4)
ECAP3_INT
(eCAP3)
ECAP2_INT
(eCAP2)
ECAP1_INT
(eCAP1)
Reserved
Reserved
Reserved
Reserved
EQEP3_INT
(eQEP3)
EQEP2_INT
(eQEP2)
EQEP1_INT
(eQEP1)
Reserved
Reserved
Reserved
SPITXINTD
(SPI-D)
SPIRXINTD
(SPI-D)
MXINTA
(McBSP-A)
MRINTA
(McBSP-A)
MXINTB
(McBSP-B)
MRINTB
(McBSP-B)
SPITXINTA
(SPI-A)
SPIRXINTA
(SPI-A)
DINTCH6
(DMA)
DINTCH5
(DMA)
DINTCH4
(DMA)
DINTCH3
(DMA)
DINTCH2
(DMA)
DINTCH1
(DMA)
Reserved
Reserved
Reserved
Reserved
SCITXINTC
(SCI-C)
SCIRXINTC
(SCI-C)
I2CINT2A
(I2C-A)
I2CINT1A
(I2C-A)
Reserved
Reserved
ECAN1_INTB
(CAN-B)
ECAN0_INTB
(CAN-B)
ECAN1_INTA
(CAN-A)
ECAN0_INTA
(CAN-A)
SCITXINTB
(SCI-B)
SCIRXINTB
(SCI-B)
SCITXINTA
(SCI-A)
SCIRXINTA
(SCI-A)
EPWM9_TZINT
(ePWM9)
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
XINT7
Reserved
Reserved
XINT6
Reserved
Reserved
XINT5
Reserved
Reserved
XINT4
EPWM9_INT
(ePWM9)
LUF
(FPU)
LVF
(FPU)
XINT3
(1) Out of the 96 possible interrupts, 64 interrupts are currently used. The remaining interrupts are reserved for future devices. These
interrupts can be used as software interrupts if they are enabled at the PIEIFRx level, provided none of the interrupts within the group
is being used by a peripheral. Otherwise, interrupts coming in from peripherals may be lost by accidentally clearing their flag while
modifying the PIEIFR. To summarize, there is one safe case when the reserved interrupts could be used as software interrupts:
1) No peripheral within the group is asserting interrupts.
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Table 8-29. PIE Configuration and Control Registers
NAME
PIECTRL
PIEACK
PIEIER1
PIEIFR1
PIEIER2
PIEIFR2
PIEIER3
PIEIFR3
PIEIER4
PIEIFR4
PIEIER5
PIEIFR5
PIEIER6
PIEIFR6
PIEIER7
PIEIFR7
PIEIER8
PIEIFR8
PIEIER9
PIEIFR9
PIEIER10
PIEIFR10
PIEIER11
PIEIFR11
PIEIER12
PIEIFR12
Reserved
ADDRESS
0x0CE0
0x0CE1
0x0CE2
0x0CE3
0x0CE4
0x0CE5
0x0CE6
0x0CE7
0x0CE8
0x0CE9
0x0CEA
0x0CEB
0x0CEC
0x0CED
0x0CEE
0x0CEF
0x0CF0
0x0CF1
0x0CF2
0x0CF3
0x0CF4
0x0CF5
0x0CF6
0x0CF7
0x0CF8
0x0CF9
0x0CFA – 0x0CFF
SIZE (x16)
DESCRIPTION(1)
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
6
PIE, Control Register
PIE, Acknowledge Register
PIE, INT1 Group Enable Register
PIE, INT1 Group Flag Register
PIE, INT2 Group Enable Register
PIE, INT2 Group Flag Register
PIE, INT3 Group Enable Register
PIE, INT3 Group Flag Register
PIE, INT4 Group Enable Register
PIE, INT4 Group Flag Register
PIE, INT5 Group Enable Register
PIE, INT5 Group Flag Register
PIE, INT6 Group Enable Register
PIE, INT6 Group Flag Register
PIE, INT7 Group Enable Register
PIE, INT7 Group Flag Register
PIE, INT8 Group Enable Register
PIE, INT8 Group Flag Register
PIE, INT9 Group Enable Register
PIE, INT9 Group Flag Register
PIE, INT10 Group Enable Register
PIE, INT10 Group Flag Register
PIE, INT11 Group Enable Register
PIE, INT11 Group Flag Register
PIE, INT12 Group Enable Register
PIE, INT12 Group Flag Register
Reserved
(1) The PIE configuration and control registers are not protected by EALLOW mode. The PIE vector
table is protected.
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8.5.1 External Interrupts
Table 8-30. External Interrupt Registers
NAME
XINT1CR
XINT2CR
XINT3CR
XINT4CR
XINT5CR
XINT6CR
XINT7CR
XNMICR
ADDRESS
0x00 7070
0x00 7071
0x00 7072
0x00 7073
0x00 7074
0x00 7075
0x00 7076
0x00 7077
0x00 7078
0x00 7079
0x707A – 0x707E
0x00 707F
SIZE (x16)
DESCRIPTION
XINT1 configuration register
XINT2 configuration register
XINT3 configuration register
XINT4 configuration register
XINT5 configuration register
XINT6 configuration register
XINT7 configuration register
XNMI configuration register
XINT1 counter register
1
1
1
1
1
1
1
1
1
1
5
1
XINT1CTR
XINT2CTR
Reserved
XNMICTR
XINT2 counter register
XNMI counter register
Each external interrupt can be enabled or disabled or qualified using positive, negative, or both positive and
negative edge. For more information, see the TMS320x2834x Delfino System Control and Interrupts Reference
Guide.
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8.6 System Control
This section describes the oscillator, PLL and clocking mechanisms, the watchdog function and the low-power
modes. Figure 8-27 shows the various clock and reset domains that will be discussed.
C28x Core
SYSCLKOUT
System
control
register
Clock enables
LSPCLK
LOSPCP
Bridge
I/O
Peripheral
SPI-A/D, SCI-A/B/C
registers
Clock enables
/4
I/O
Peripheral
eCAN-A/B
registers
Clock enables
GPIO
Mux
Bridge
I/O
I/O
Peripheral
registers
ePWM1/../9, HRPWM1/../9,
eCAP1/../6, eQEP1/../3
Clock enables
LSPCLK
LOSPCP
Peripheral
registers
McBSP-A/B
Clock enable
Bridge
CPU timer
registers
CPU timer 0/1/2
Clock enable
EXTADCCLK
EXTSOC
HISPCP
Bridge
ADC SOC
Peripheral
registers
I2C-A
DMA
Clock Enables
Figure 8-27. Clock and Reset Domains
Note
There is a 2-SYSCLKOUT cycle delay from when the write to the PCLKCR0, PCLKCR1, and
PCLKCR2 registers (enables peripheral clocks) occurs to when the action is valid. This delay must be
considered before trying to access the peripheral configuration registers.
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The PLL, clocking, watchdog and low-power modes, are controlled by the registers listed in Table 8-31.
Table 8-31. PLL, Clocking, Watchdog, and Low-Power Mode Registers
NAME
ADDRESS
SIZE (x16)
DESCRIPTION
PLLSTS
0x00 7011
1
7
1
1
1
1
1
1
1
1
1
1
1
1
1
3
1
3
1
1
PLL Status Register
Reserved
Reserved
PCLKCR2
HISPCP
0x00 7012 – 0x00 7018
0x00 7019
Peripheral Clock Control Register 2
High-Speed Peripheral Clock Prescaler Register
Low-Speed Peripheral Clock Prescaler Register
Peripheral Clock Control Register 0
Peripheral Clock Control Register 1
Low-Power Mode Control Register 0
Reserved
0x00 701A
LOSPCP
PCLKCR0
PCLKCR1
LPMCR0
Reserved
PCLKCR3
PLLCR
0x00 701B
0x00 701C
0x00 701D
0x00 701E
0x00 701F
0x00 7020
Peripheral Clock Control Register 3
PLL Control Register
0x00 7021
SCSR
0x00 7022
System Control and Status Register
Watchdog Counter Register
Reserved
WDCNTR
Reserved
WDKEY
0x00 7023
0x00 7024
0x00 7025
Watchdog Reset Key Register
Reserved
Reserved
WDCR
0x00 7026 – 0x00 7028
0x00 7029
Watchdog Control Register
Reserved
Reserved
EXTSOCCFG
Reserved
0x00 702A – 0x00 702C
0x00 702D
External ADC SOC Configuration Register
Reserved
0x00 702E
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8.6.1 OSC and PLL Block
Figure 8-28 shows the OSC and PLL block.
OSCCLK
OSCCLK
VCOCLK
/1
XCLKIN
(3.3-V clock input
from external
oscillator)
0
n
OSCCLK or
VCOCLK
/2
/4
/8
CLKIN
To
CPU
PLLSTS[OSCOFF]
PLL
n ≠ 0
PLLSTS[PLLOFF]
PLLSTS[DIVSEL]
5-bit multiplier PLLCR[DIV]
X1
External
Crystal or
Resonator
On-chip
oscillator
X2
Figure 8-28. OSC and PLL Block Diagram
The on-chip oscillator circuit enables a crystal/resonator to be attached to the C2834x devices using the X1 and
X2 pins. If the on-chip oscillator is not used, an external oscillator can be used in either one of the following
configurations:
•
A 3.3-V external oscillator can be directly connected to the XCLKIN pin. The X2 pin should be left
unconnected and the X1 pin tied to VSSK . The logic-high level in this case should not exceed VDDIO
.
•
A 1.8-V external oscillator can be directly connected to the X1 pin. The X2 pin should be left unconnected
and the XCLKIN pin tied to VSS . The logic-high level in this case should not exceed VDD18
.
The three possible input-clock configurations are shown in Figure 8-29 to Figure 8-31.
XCLKIN
X1
X2
VSSK
NC
External Clock Signal
(Toggling 0 -VDDIO
)
Figure 8-29. Using a 3.3-V External Oscillator
XCLKIN
X1
X2
External Clock Signal
)
NC
(Toggling 0-VDD
Figure 8-30. Using a 1.8-V External Oscillator
VSSK
VDD18
X1
X2
XCLKIN
Crystal
1.8 V
C1
C2
Figure 8-31. Using the Internal Oscillator
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8.6.1.1 External Reference Oscillator Clock Option
The on-chip oscillator requires an external crystal to be connected across the X1 and X2 pins.
The connection of the required circuit, consisting of the crystal and two load capacitors, is shown in Figure 8-31.
The load capacitors, C1 and C2, must be chosen such that the equation below is satisfied (typical values are on
the order of C1 = C2 = 10 pF). CL in the equation is the load specified for the crystal. All discrete components
used to implement the oscillator circuit must be placed as close as possible to the associated oscillator pins (X1,
X2, and VSSK).
Note
The external crystal load capacitors must be connected only to the oscillator ground pin (VSSK). Do not
connect to board ground (VSS).
C1C2
CL +
(C1 ) C2)
Where: CL equals the crystal load capacitance.
TI recommends that customers have the crystal vendor characterize the operation of their device with the MCU
chip. The crystal vendor has the equipment and expertise to tune the crystal circuit. The vendor can also advise
the customer regarding the proper component values that will produce proper start up and stability over the
entire operating range.
8.6.1.2 PLL-Based Clock Module
The devices have an on-chip, PLL-based clock module. This module provides all the necessary clocking signals
for the device, as well as control for low-power mode entry. The PLL has a 5-bit ratio control PLLCR[DIV] to
select different CPU clock rates. The watchdog module should be disabled before writing to the PLLCR register.
It can be re-enabled (if need be) after the PLL module has stabilized. The input clock and PLLCR[DIV] bits
should be chosen in such a way that the output frequency of the PLL (VCOCLK) falls between 400 MHz and
600 MHz. The PLLSTS[DIVSEL] bit should be selected such that SYSCLKOUT(CLKIN) does not exceed the
maximum operating frequency allowed for the device (300 MHz or 200 MHz). For example, suppose it is desired
to operate a 300-MHz device at 100 MHz using a 20-MHz OSCCLK input (that is, for power savings). The PLL
should be configured for OSCCLK * 20, which produces VCOCLK = 400 MHz. PLLSTS[DIVSEL] should then be
configured for /4 mode, resulting in the desired 100-MHz CLKIN to the CPU. The PLL should not be configured
for OSCCLK * 10 with PLLSTS[DIVSEL] set for /2 mode. This combination would produce VCOCLK = 200 MHz,
which does not fall within the required 400 MHz to 600 MHz range.
Table 8-32. PLL Settings (1)
SYSCLKOUT (CLKIN)
PLLCR[DIV]
VALUE(3) (4)
PLLSTS[DIVSEL] = 0
PLLSTS[DIVSEL] = 1
PLLSTS[DIVSEL] = 2
PLLSTS[DIVSEL] = 3 (2)
00000 (PLL bypass)
00001
OSCCLK/8 (Default)
(OSCCLK * 2)/8
(OSCCLK * 3)/8
(OSCCLK * 4)/8
(OSCCLK * 5)/8
(OSCCLK * 6)/8
(OSCCLK * 7)/8
(OSCCLK * 8)/8
(OSCCLK * 9)/8
(OSCCLK * 10)/8
(OSCCLK * 11)/8
OSCCLK/4
OSCCLK/2
OSCCLK
(OSCCLK * 2)/4
(OSCCLK * 3)/4
(OSCCLK * 4)/4
(OSCCLK * 5)/4
(OSCCLK * 6)/4
(OSCCLK * 7)/4
(OSCCLK * 8)/4
(OSCCLK * 9)/4
(OSCCLK * 10)/4
(OSCCLK * 11)/4
(OSCCLK * 2)/2
(OSCCLK * 3)/2
(OSCCLK * 4)/2
(OSCCLK * 5)/2
(OSCCLK * 6)/2
(OSCCLK * 7)/2
(OSCCLK * 8)/2
(OSCCLK * 9)/2
(OSCCLK * 10)/2
(OSCCLK * 11)/2
–
–
–
–
–
–
–
–
–
–
00010
00011
00100
00101
00110
00111
01000
01001
01010
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Table 8-32. PLL Settings (1) (continued)
SYSCLKOUT (CLKIN)
PLLCR[DIV]
VALUE(3) (4)
PLLSTS[DIVSEL] = 0
PLLSTS[DIVSEL] = 1
PLLSTS[DIVSEL] = 2
PLLSTS[DIVSEL] = 3 (2)
01011 – 11111
(OSCCLK * 12)/8 –
(OSCCLK * 32)/8
(OSCCLK * 12)/4 –
(OSCCLK * 32)/4
(OSCCLK * 12)/2 –
(OSCCLK * 32)/2
–
(1) PLLSTS[DIVSEL] must be 0 before writing to the PLLCR and must be set only to 1 or 2 after PLLSTS[PLLLOCKS] = 1. At reset,
PLLSTS[DIVSEL] is configured for /8. The boot ROM changes this to /2 or /1, depending on the boot option.
(2) PLLSTS[DIVSEL] = 3 should be used only when the PLL is bypassed or off.
(3) The PLL control register (PLLCR) and PLL Status Register (PLLSTS) are reset to their default state by the XRS signal or a watchdog
reset only. A reset issued by the debugger or the missing clock detect logic have no effect.
(4) This register is EALLOW protected. See the TMS320x2834x Delfino System Control and Interrupts Reference Guide for more
information.
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Table 8-33. CLKIN Divide Options
PLLSTS [DIVSEL]
CLKIN DIVIDE
0
1
2
3
/8
/4
/2
/1
The PLL-based clock module provides two modes of operation:
•
Crystal-operation - This mode allows the use of an external crystal/resonator to provide the time base to the
device.
•
External clock source operation - This mode allows the internal oscillator to be bypassed. The device clocks
are generated from an external clock source input on the X1 or the XCLKIN pin.
Table 8-34. Possible PLL Configuration Modes
CLKIN AND
SYSCLKOUT
PLL MODE
REMARKS
PLLSTS[DIVSEL](1)
Invoked by the user setting the PLLOFF bit in the PLLSTS register. The PLL block
is disabled in this mode. This can be useful to reduce system noise and for low
power operation. The PLLCR register must first be set to 0x0000 (PLL Bypass)
before entering this mode. The CPU clock (CLKIN) is derived directly from the
input clock on either X1/X2, X1 or XCLKIN.
0
1
2
3
OSCCLK/8
OSCCLK/4
OSCCLK/2
OSCCLK/1
PLL Off
PLL Bypass is the default PLL configuration upon power up or after an external
reset ( XRS). This mode is selected when the PLLCR register is set to 0x0000 or
while the PLL locks to a new frequency after the PLLCR register has been
modified. In this mode, the PLL itself is bypassed but the PLL is not turned off.
0
1
2
3
OSCCLK/8
OSCCLK/4
OSCCLK/2
OSCCLK/1
PLL Bypass
PLL Enable
0
1
2
3
OSCCLK*n/8
OSCCLK*n/4
OSCCLK*n/2
Achieved by writing a nonzero value n into the PLLCR register. Upon writing to the
PLLCR the device will switch to PLL Bypass mode until the PLL locks.
(2)
–
(1) PLLSTS[DIVSEL] must be 0 before writing to the PLLCR and must be set to 1 or 2 only after PLLSTS[PLLLOCKS] = 1. See the
TMS320x2834x Delfino System Control and Interrupts Reference Guide for more information.
(2) PLLSTS[DIVSEL] should not be set to /1 mode while the PLL is enabled and not bypassed.
8.6.1.3 Loss of Input Clock
Applications in which the correct CPU operating frequency is absolutely critical should implement a mechanism
by which the MCU will be held in reset, should the input clocks ever fail. For example, an R-C circuit may be
used to trigger the XRS pin of the MCU, should the capacitor ever get fully charged. An I/O pin may be used to
discharge the capacitor on a periodic basis to prevent it from getting fully charged.
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8.6.2 Watchdog Block
The watchdog block on the C2834x device is similar to the one used on the 240x and 281x devices. The
watchdog module generates an output pulse, 512 oscillator clocks wide (OSCCLK), whenever the 8-bit
watchdog up counter has reached its maximum value. To prevent this, the user disables the counter or the
software must periodically write a 0x55 + 0xAA sequence into the watchdog key register which will reset the
watchdog counter. Figure 8-32 shows the various functional blocks within the watchdog module.
WDCR (WDPS[2:0])
WDCR (WDDIS)
WDCNTR[7:0]
OSCCLK
WDCLK
Watchdog
Prescaler
8-Bit
Watchdog
Counter
CLR
/512
Clear Counter
Internal
Pullup
WDKEY[7:0]
WDRST
WDINT
Generate
Output Pulse
(512 OSCCLKs)
Watchdog
55 + AA
Key Detector
Good Key
XRS
Bad
WDCHK
Key
Core-reset
SCSR (WDENINT)
WDCR (WDCHK[2:0])
WDRST(A)
A. The WDRST signal is driven low for 512 OSCCLK cycles.
1
0
1
Figure 8-32. Watchdog Module
The WDINT signal enables the watchdog to be used as a wakeup from IDLE/STANDBY mode.
In STANDBY mode, all peripherals are turned off on the device. The only peripheral that remains functional is
the watchdog. The WATCHDOG module will run off OSCCLK. The WDINT signal is fed to the LPM block so that
it can wake the device from STANDBY (if enabled). See Section 8.7, Low-Power Modes Block, for more details.
In IDLE mode, the WDINT signal can generate an interrupt to the CPU, through the PIE, to take the CPU out of
IDLE mode.
In HALT mode, this feature cannot be used because the oscillator (and PLL) are turned off and hence so is the
WATCHDOG.
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8.7 Low-Power Modes Block
The low-power modes on the C2834x devices are similar to the 240x devices. Table 8-35 summarizes the
various modes.
Table 8-35. Low-Power Modes
MODE
LPMCR0(1:0)
OSCCLK
CLKIN
SYSCLKOUT
EXIT(1)
XRS, watchdog interrupt, any enabled
interrupt, XNMI
IDLE
00
On
On
On(2)
On
XRS, watchdog interrupt, GPIO Port A
signal, debugger(3), XNMI
STANDBY
HALT
01
1X
Off
Off
Off
Off
(watchdog still running)
Off
XRS, GPIO port A signal, XNMI,
debugger(3)
(oscillator and PLL turned off,
watchdog not functional)
(1) The EXIT column lists which signals or under what conditions the low-power mode will be exited. A low signal, on any of the signals,
will exit the low power condition. This signal must be kept low long enough for an interrupt to be recognized by the device. Otherwise,
the low-power mode will not be exited and the device will go back into the indicated low-power mode.
(2) The IDLE mode on the C28x behaves differently than on the 24x/240x. On the C28x, the clock output from the CPU (SYSCLKOUT) is
still functional while on the 24x/240x the clock is turned off.
(3) On the C28x, the JTAG port can still function even if the CPU clock (CLKIN) is turned off.
The various low-power modes operate as follows:
IDLE mode:
This mode is exited by any enabled interrupt or an XNMI that is recognized by the processor. The
LPM block performs no tasks during this mode as long as the LPMCR0(LPM) bits are set to 0,0.
STANDBY mode:
Any GPIO port A signal (GPIO[31:0]) can wake the device from STANDBY mode. The user must
select which signal(s) will wake the device in the GPIOLPMSEL register. The selected signal(s) are
also qualified by the OSCCLK before waking the device. The number of OSCCLKs is specified in the
LPMCR0 register.
HALT mode:
Only the XRS and any GPIO port A signal (GPIO[31:0]) can wake the device from HALT mode. The
user selects the signal in the GPIOLPMSEL register.
Note
The low-power modes do not affect the state of the output pins (PWM pins included). They will be in
whatever state the code left them in when the IDLE instruction was executed. See the TMS320x2834x
Delfino System Control and Interrupts Reference Guide for more details.
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9 Applications, Implementation, and Layout
Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 TI Design or Reference Design
TI Designs Reference Design Library is a robust reference design library spanning analog, embedded processor,
and connectivity. Created by TI experts to help you jump start your system design, all TI Designs include
schematic or block diagrams, BOMs, and design files to speed your time to market. Search and download
designs at TIDesigns.
C2000 Resolver to Digital Conversion Kit
This is a motherboard-style Resolver to Digital conversion kit used to experiment with various C2000™
microcontrollers for software-based resolver to digital conversion using on-chip ADCs. The Resolver Kit also
allows interface to resolvers and inverter control processor.
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10 Device and Documentation Support
10.1 Getting Started
This section gives a brief overview of the steps to take when first developing for a C28x device. For more detail
on each of these steps, see the following:
•
•
•
•
C2000 Real-Time Control MCUs – Getting started
C2000 Real-Time Control MCUs – Tools & software
Motor drive and control
Digital power
10.2 Device and Development Support Tool Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all
TMS320™ MCU devices and support tools. Each TMS320™ commercial family member has one of three
prefixes: TMX, TMP, or TMS (for example, TMS 320C28345). Texas Instruments recommends two of three
possible prefix designators for its support tools: TMDX and TMDS. These prefixes represent evolutionary stages
of product development from engineering prototypes (TMX/TMDX) through fully qualified production devices/
tools (TMS/TMDS).
Device development evolutionary flow:
TMX
TMP
Experimental device that is not necessarily representative of the final device's electrical specifications
Final silicon die that conforms to the device's electrical specifications but has not completed quality and reliability
verification
TMS
Fully qualified production device
Support tool development evolutionary flow:
TMDX
TMDS
Development-support product that has not yet completed Texas Instruments internal qualification testing
Fully qualified development-support product
TMX and TMP devices and TMDX development-support tools are shipped against the following disclaimer:
"Developmental product is intended for internal evaluation purposes."
TMS devices and TMDS development-support tools have been characterized fully, and the quality and reliability
of the device have been demonstrated fully. TI's standard warranty applies.
Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard production
devices. Texas Instruments recommends that these devices not be used in any production system because their
expected end-use failure rate still is undefined. Only qualified production devices are to be used.
TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package type
(for example, ZFE) and temperature range (for example, T). Figure 10-1 provides a legend for reading the
complete device name for any family member.
For device part numbers and further ordering information, see the Package Option Addendum of this document,
the TI website (www.ti.com), or contact your TI sales representative.
For additional description of the device nomenclature markings on the die, see the TMS320C2834x Delfino™
MCUs Silicon Errata .
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Figure 10-1. Example of C2834x Device Nomenclature
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10.3 Tools and Software
TI offers an extensive line of development tools. Some of the tools and software to evaluate the performance of
the device, generate code, and develop solutions are listed below. To view all available tools and software for
C2000™ real-time control MCUs, visit the C2000 MCU Tools and Software page.
Design Kits and Evaluation Modules
C2000 Delfino MCUs F28377S LaunchPad Development Kit
The C2000™ Delfino™ MCUs LaunchPad™ development kit is an inexpensive evaluation platform that provides
designers with a low-cost development kit for high-performance digital control applications. This tool provides a
great starting point for development of many high-end digital control applications such as industrial drives and
automation; power line communications; solar inverters; and more.
Delfino C28343 controlCARD
The C28343 controlCARD allows users to easily evaluate all the functionality of the 200-MHz C28343 floating-
point controller and is compatible with existing controlCARD tool kits. The card provides all the chip support
necessary, needing only a 5-V supply to be fully functional. The controlCARD also has two onboard 12-bit ADCs
and a 64KB EEPROM for nonvolatile program storage. Based on the standard DIM100 controlCARD form factor,
it is pin-compatible with other C2000 controlCARDs.
Software
C2000 DesignDRIVE Software for Industrial Drives and Motor Control
The DesignDRIVE platform combines software solutions with DesignDRIVE Development Kits to make it easy to
develop and evaluate solutions for many industrial drive and servo topologies. DesignDRIVE offers support for a
wide variety of motor types, sensing technologies, position sensors and communications networks, including
specific examples for vector control of motors, incorporating current, speed and position loops, to help
developers jumpstart their evaluation and development. Based on the real-time control architecture of TI’s
C2000™ microcontrollers (MCUs), DesignDRIVE is ideal for the development of industrial inverter and servo
drives used in robotics, computer numerical control machinery (CNC), elevators, materials conveyance and
other industrial manufacturing applications.
powerSUITE Digital Power Supply Software Frequency Response Analyzer Tool for C2000™ MCUs
The Software Frequency Response Analyzer (SFRA) is one of several tools included in the powerSUITE Digital
Power Supply Design Software Tools for C2000™ Microcontrollers. The SFRA includes a software library that
enables developers to quickly measure the frequency response of their digital power converter. The SFRA library
contains software functions that inject a frequency into the control loop and measure the response of the system
using the C2000 MCUs’ on-chip analog to digital converter (ADC). This process provides the plant frequency
response characteristics and the open loop gain frequency response of the closed loop system. The user can
then view the plant and open loop gain frequency response on a PC-based GUI. All of the frequency response
data is exported into a CSV file, or optionally an Excel® spreadsheet, which can then be used to design the
compensation loop using the Compensation Designer.
C2000Ware for C2000 MCUs
C2000Ware for C2000™ microcontrollers is a cohesive set of development software and documentation
designed to minimize software development time. From device-specific drivers and libraries to device peripheral
examples, C2000Ware provides a solid foundation to begin development and evaluation of your product.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback 155
Product Folder Links: TMS320C28346 TMS320C28346-Q1 TMS320C28345 TMS320C28344 TMS320C28343
TMS320C28343-Q1 TMS320C28342 TMS320C28341
TMS320C28346, TMS320C28346-Q1, TMS320C28345, TMS320C28344
TMS320C28343, TMS320C28343-Q1, TMS320C28342, TMS320C28341
SPRS516F – MARCH 2009 – REVISED FEBRUARY 2021
www.ti.com
Development Tools
C2000 Gang Programmer
The C2000 Gang Programmer is a C2000 device programmer that can program up to eight identical C2000
devices at the same time. The C2000 Gang Programmer connects to a host PC using a standard RS-232 or
USB connection and provides flexible programming options that allow the user to fully customize the process.
Code Composer Studio™ (CCS) Integrated Development Environment (IDE) for C2000 Microcontrollers
Code Composer Studio is an integrated development environment (IDE) that supports TI's Microcontroller and
Embedded Processors portfolio. Code Composer Studio comprises a suite of tools used to develop and debug
embedded applications. It includes an optimizing C/C++ compiler, source code editor, project build environment,
debugger, profiler, and many other features. The intuitive IDE provides a single user interface taking the user
through each step of the application development flow. Familiar tools and interfaces allow users to get started
faster than ever before. Code Composer Studio combines the advantages of the Eclipse software framework
with advanced embedded debug capabilities from TI resulting in a compelling feature-rich development
environment for embedded developers.
Models
Various models are available for download from the product Tools & Software pages. These include I/O Buffer
Information Specification (IBIS) Models and Boundary-Scan Description Language (BSDL) Models. To view all
available models, visit the Models section of the Tools & Software page for each device.
10.4 Documentation Support
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
The current documentation that describes the processor, related peripherals, and other technical collateral is
listed below.
Errata
TMS320C2834x Delfino™ MCUs Silicon Errata describes the advisories and usage notes for different versions
of silicon.
CPU User's Guides
TMS320C28x CPU and Instruction Set Reference Guide describes the central processing unit (CPU) and the
assembly language instructions of the TMS320C28x fixed-point digital signal processors (DSPs). It also
describes emulation features available on these DSPs.
TMS320C28x Extended Instruction Sets Technical Reference Manual describes the architecture, pipeline, and
instruction set of the TMU, VCU-II, and FPU accelerators.
Peripheral Guides
C2000 Real-Time Control MCU Peripherals Reference Guide describes the peripheral reference guides of the
28x digital signal processors (DSPs).
TMS320x2834x Delfino System Control and Interrupts Reference Guide This document describes the various
interrupts and system control features of the x2834x microcontroller (MCUs).
TMS320x2834x Delfino External Interface (XINTF) Reference Guide This document describes the XINTF, which
is a nonmultiplexed asynchronous bus, as it is used on the x2834x device.
TMS320x2834x Delfino Boot ROM Reference Guide This document describes the purpose and features of the
bootloader (factory-programmed boot-loading software) and provides examples of code. It also describes other
contents of the device on-chip boot ROM and identifies where all of the information is located within that
memory.
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156 Submit Document Feedback
Product Folder Links: TMS320C28346 TMS320C28346-Q1 TMS320C28345 TMS320C28344 TMS320C28343
TMS320C28343-Q1 TMS320C28342 TMS320C28341
TMS320C28346, TMS320C28346-Q1, TMS320C28345, TMS320C28344
TMS320C28343, TMS320C28343-Q1, TMS320C28342, TMS320C28341
www.ti.com
SPRS516F – MARCH 2009 – REVISED FEBRUARY 2021
TMS320x2834x Delfino Multichannel Buffered Serial Port (McBSP) Reference Guide This document describes
the McBSP available on the x2834x devices. The McBSPs allow direct interface between a microcontroller
(MCU) and other devices in a system.
TMS320x2834x Delfino Direct Memory Access (DMA) Module Reference Guide This document describes the
DMA on the x2834x microcontroller (MCUs).
TMS320x2834x Delfino Enhanced Pulse Width Modulator (ePWM) Module Reference Guide This document
describes the main areas of the enhanced pulse width modulator that include digital motor control, switch mode
power supply control, UPS (uninterruptible power supplies), and other forms of power conversion.
TMS320x2834x Delfino High Resolution Pulse Width Modulator (HRPWM) Reference Guide This document
describes the operation of the high-resolution extension to the pulse width modulator (HRPWM).
TMS320x2834x Delfino Enhanced Capture (eCAP) Module Reference Guide This document describes the
enhanced capture module. It includes the module description and registers.
TMS320x2834x Delfino Enhanced Quadrature Encoder Pulse (eQEP) Module Reference Guide This document
describes the eQEP module, which is used for interfacing with a linear or rotary incremental encoder to get
position, direction, and speed information from a rotating machine in high performance motion and position
control systems. It includes the module description and registers.
TMS320x2834x Delfino Enhanced Controller Area Network (eCAN) Reference Guide This document describes
the eCAN that uses established protocol to communicate serially with other controllers in electrically noisy
environments.
TMS320x2834x Delfino Serial Communications Interface (SCI) Reference Guide This document describes the
SCI, which is a 2-wire asynchronous serial port, commonly known as a UART. The SCI modules support digital
communications between the CPU and other asynchronous peripherals that use the standard nonreturn-to-zero
(NRZ) format.
TMS320x2834x Delfino Serial Peripheral Interface (SPI) Reference Guide This document describes the SPI - a
high-speed synchronous serial input/output (I/O) port - that allows a serial bit stream of programmed length (1 to
16 bits) to be shifted into and out of the device at a programmed bit-transfer rate.
TMS320x2834x Delfino Inter-Integrated Circuit (I2C) Module Reference Guide This document describes the
features and operation of the inter-integrated circuit (I2C) module.
Tools Guides
TMS320C28x Assembly Language Tools v20.2.0.LTS User's Guide describes the assembly language tools
(assembler and other tools used to develop assembly language code), assembler directives, macros, common
object file format, and symbolic debugging directives for the TMS320C28x device.
TMS320C28x Optimizing C/C++ Compiler v20.2.0.LTS User's Guide describes the TMS320C28x C/C++
compiler. This compiler accepts ANSI standard C/C++ source code and produces TMS320 DSP assembly
language source code for the TMS320C28x device.
TMS320C28x DSP/BIOS 5.x Application Programming Interface (API) Reference Guide describes development
using DSP/BIOS.
Application Reports
The SMT & packaging application notes website lists documentation on TI’s surface mount technology (SMT)
and application notes on a variety of packaging-related topics.
TMS320C28x FPU Primer provides an overview of the floating-point unit (FPU) in the C2000™ Delfino
microcontroller devices.
Running an Application from Internal Flash Memory on the TMS320F28xxx DSP covers the requirements
needed to properly configure application software for execution from on-chip flash memory. Requirements for
both DSP/BIOS and non-DSP/BIOS projects are presented. Example code projects are included.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback 157
Product Folder Links: TMS320C28346 TMS320C28346-Q1 TMS320C28345 TMS320C28344 TMS320C28343
TMS320C28343-Q1 TMS320C28342 TMS320C28341
TMS320C28346, TMS320C28346-Q1, TMS320C28345, TMS320C28344
TMS320C28343, TMS320C28343-Q1, TMS320C28342, TMS320C28341
SPRS516F – MARCH 2009 – REVISED FEBRUARY 2021
www.ti.com
Programming TMS320x28xx and TMS320x28xxx Peripherals in C/C++ explores a hardware abstraction layer
implementation to make C/C++ coding easier on 28x DSPs. This method is compared to traditional #define
macros and topics of code efficiency and special case registers are also addressed.
Using PWM Output as a Digital-to-Analog Converter on a TMS320F280x Digital Signal Controller presents a
method for using the on-chip pulse width modulated (PWM) signal generators on the TMS320F280x family of
digital signal controllers as a digital-to-analog converter (DAC).
TMS320F280x Digital Signal Controller USB Connectivity using the TUSB3410 USB-to-UART Bridge Chip
presents hardware connections as well as software preparation and operation of the development system using
a simple communication echo program.
Using the Enhanced Quadrature Encoder Pulse (eQEP) Module in TMS320x280x, 28xxx as a Dedicated
Capture provides a guide for the use of the eQEP module as a dedicated capture unit and is applicable to the
TMS320x280x, 28xxx family of processors.
Using the ePWM Module for 0% - 100% Duty Cycle Control provides a guide for the use of the ePWM module to
provide 0% to 100% duty cycle control and is applicable to the TMS320x280x family of processors.
TMS320x2833x/2823x to TMS320x2834x Delfino Migration Overview This application report describes
differences between the Texas Instruments TMS320x2833x/2823x and the TMS320x2834x devices to assist in
application migration.
Online Stack Overflow Detection on the TMS320C28x DSP presents the methodology for online stack overflow
detection on the TMS320C28x DSP. C-source code is provided that contains functions for implementing the
overflow detection on both DSP/BIOS and non-DSP/BIOS applications.
Semiconductor Packing Methodology describes the packing methodologies employed to prepare semiconductor
devices for shipment to end users.
Calculating Useful Lifetimes of Embedded Processors provides a methodology for calculating the useful lifetime
of TI embedded processors (EPs) under power when used in electronic systems. It is aimed at general
engineers who wish to determine if the reliability of the TI EP meets the end system reliability requirement.
Semiconductor and IC Package Thermal Metrics describes traditional and new thermal metrics and puts their
application in perspective with respect to system-level junction temperature estimation.
An Introduction to IBIS (I/O Buffer Information Specification) Modeling discusses various aspects of IBIS
including its history, advantages, compatibility, model generation flow, data requirements in modeling the input/
output structures and future trends.
10.5 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
10.6 Trademarks
MicroStar BGA™, Delfino™, C2000™, Piccolo™, DSP/BIOS™, Code Composer Studio™, and TI E2E™ are
trademarks of Texas Instruments.
Excel® is a registered trademark of Microsoft Corporation in the United States and/or other countries.
All trademarks are the property of their respective owners.
10.7 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
Copyright © 2021 Texas Instruments Incorporated
158 Submit Document Feedback
Product Folder Links: TMS320C28346 TMS320C28346-Q1 TMS320C28345 TMS320C28344 TMS320C28343
TMS320C28343-Q1 TMS320C28342 TMS320C28341
TMS320C28346, TMS320C28346-Q1, TMS320C28345, TMS320C28344
TMS320C28343, TMS320C28343-Q1, TMS320C28342, TMS320C28341
www.ti.com
SPRS516F – MARCH 2009 – REVISED FEBRUARY 2021
10.8 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback 159
Product Folder Links: TMS320C28346 TMS320C28346-Q1 TMS320C28345 TMS320C28344 TMS320C28343
TMS320C28343-Q1 TMS320C28342 TMS320C28341
TMS320C28346, TMS320C28346-Q1, TMS320C28345, TMS320C28344
TMS320C28343, TMS320C28343-Q1, TMS320C28342, TMS320C28341
SPRS516F – MARCH 2009 – REVISED FEBRUARY 2021
www.ti.com
11 Mechanical, Packaging, and Orderable Information
11.1 Packaging Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2021 Texas Instruments Incorporated
160 Submit Document Feedback
Product Folder Links: TMS320C28346 TMS320C28346-Q1 TMS320C28345 TMS320C28344 TMS320C28343
TMS320C28343-Q1 TMS320C28342 TMS320C28341
PACKAGE OPTION ADDENDUM
www.ti.com
19-Jan-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
ZAY
ZHH
ZFE
Qty
160
160
90
(1)
(2)
(3)
(4/5)
(6)
TMS320C28341ZAYT
TMS320C28341ZHHT
TMS320C28342ZFET
TMS320C28343ZAYT
TMS320C28343ZFEQ
TMS320C28343ZHHT
TMS320C28344ZFET
TMS320C28345ZAYT
TMS320C28345ZFET
TMS320C28345ZHHT
TMS320C28346ZFEQ
TMS320C28346ZFET
TMS320C28346ZFETR
ACTIVE
NFBGA
179
179
256
179
256
179
256
179
256
179
256
256
256
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
RoHS & Green
SNAGCU
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 105
0 to 0
TMS320
C28341ZAYT
LIFEBUY
ACTIVE
ACTIVE
ACTIVE
LIFEBUY
ACTIVE
ACTIVE
ACTIVE
LIFEBUY
ACTIVE
ACTIVE
ACTIVE
BGA
MICROSTAR
SNAGCU
SNAGCU
SNAGCU
SNAGCU
SNAGCU
SNAGCU
SNAGCU
SNAGCU
SNAGCU
SNAGCU
SNAGCU
SNAGCU
C28341ZHHT
TMS320
BGA
NFBGA
BGA
-40 to 105
-40 to 105
-40 to 125
0 to 0
TMS
320C28342ZFET
ZAY
ZFE
160
90
TMS320
C28343ZAYT
TMS
320C28343ZFEQ
BGA
MICROSTAR
ZHH
ZFE
160
90
C28343ZHHT
TMS320
BGA
NFBGA
BGA
-40 to 105
-40 to 105
-40 to 105
0 to 0
TMS
320C28344ZFET
ZAY
ZFE
160
90
TMS320
C28345ZAYT
TMS
320C28345ZFET
BGA
MICROSTAR
ZHH
ZFE
160
90
C28345ZHHT
TMS320
BGA
BGA
BGA
-40 to 125
-40 to 105
-40 to 105
TMS
320C28346ZFEQ
ZFE
90
TMS
320C28346ZFET
ZFE
750
TMS320
C28346ZFET
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
19-Jan-2021
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE OUTLINE
ZHH0179A
UBGA - 1.4 mm max height
SCALE 1.200
BALL GRID ARRAY
12.1
11.9
B
A
BALL A1
CORNER
12.1
11.9
0.9
C
SEATING PLANE
0.1 C
BALL TYP
1.4 MAX
0.45
0.35
10.4 TYP
SYMM
P
N
M
L
K
10.4
TYP
J
H
G
F
SYMM
E
D
0.8
C
TYP
B
A
9
10
1
2
3
4
5
6
7
8
11
12
13 14
0.55
0.45
179X
0.15
0.08
C A B
C
0.8 TYP
4220265/A 05/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This is a Pb-free solder ball design.
www.ti.com
EXAMPLE BOARD LAYOUT
ZHH0179A
UBGA - 1.4 mm max height
BALL GRID ARRAY
(0.8) TYP
179X ( 0.4)
1
3
4
5
6
7
8
2
9
10 11 12 13 14
A
(0.8) TYP
B
C
D
E
F
G
H
J
SYMM
K
L
M
N
P
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 8X
0.05 MIN
0.05 MAX
METAL UNDER
SOLDER MASK
(
0.4)
METAL
(
0.4)
EXPOSED
EXPOSED
METAL
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
NOT TO SCALE
4220265/A 05/2017
NOTES: (continued)
4. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
See Texas Instruments Literature No. SSZA002 (www.ti.com/lit/ssza002).
www.ti.com
EXAMPLE STENCIL DESIGN
ZHH0179A
UBGA - 1.4 mm max height
BALL GRID ARRAY
(0.8) TYP
179X 0.4
(0.8) TYP
2
3
4
5
6
7
8
9
10
11
12
13
14
1
A
B
C
D
E
F
G
H
J
SYMM
K
L
M
N
P
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.15 mm THICK STENCIL
SCALE: 10X
4220265/A 05/2017
NOTES: (continued)
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
www.ti.com
PACKAGE OUTLINE
ZAY0179A
NFBGA - 1.4 mm max height
S
C
A
L
E
1
.
2
0
0
PLASTIC BALL GRID ARRAY
12.1
11.9
B
A
BALL A1
CORNER
12.1
11.9
1.4 MAX
C
SEATING PLANE
0.45
0.35
⌓ 0.12 C
10.4 TYP
(0.8)
(0.8)
SYMM
℄
P
N
M
L
K
J
SYMM
℄
H
G
10.4 TYP
F
E
D
C
0.55
179X
0.45
B
A
⌀0.15Ⓜ C A B
⌖
⌀0.08Ⓜ C
1
2
3
4
5
6
7
8
9
10 11 12 13 14
0.8 TYP
0.8 TYP
4225014/C 07/2020
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
ZAY0179A
NFBGA - 1.4 mm max height
PLASTIC BALL GRID ARRAY
(0.8) TYP
179X ( 0.4)
(0.8) TYP
1
2
4
5
7
13
3
9
10
11
14
6
8
12
A
B
C
D
E
F
G
H
J
SYMM
℄
K
L
M
N
P
SYMM
℄
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
METAL UNDER
SOLDER MASK
EXPOSED METAL
(
0.4)
(
0.4)
SOLDER MASK
OPENING
SOLDER MASK
OPENING
EXPOSED METAL
METAL EDGE
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
NOT TO SCALE
4225014/C 07/2020
NOTES: (continued)
3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
For information, see Texas Instruments literature number SPRAA99 (www.ti.com/lit/spraa99).
www.ti.com
EXAMPLE STENCIL DESIGN
ZAY0179A
NFBGA - 1.4 mm max height
PLASTIC BALL GRID ARRAY
(0.8) TYP
179X ( 0.4)
(0.8) TYP
1
2
4
5
7
13
3
9
10
11
14
6
8
12
A
B
C
D
E
F
G
H
J
SYMM
℄
K
L
M
N
P
SYMM
℄
SOLDER PASTE EXAMPLE
BASED ON 0.150 mm THICK STENCIL
SCALE: 10X
4225014/C 07/2020
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
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