TMS320C6201GJL200 [TI]
FIXED-POINT DIGITAL SIGNAL PROCESSOR;
| 型号： | TMS320C6201GJL200 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | FIXED-POINT DIGITAL SIGNAL PROCESSOR 时钟 外围集成电路 |
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TMS320C6201, TMS320C6201B
DIGITAL SIGNAL PROCESSORS
SPRS051F – JANUARY 1997 – REVISED AUGUST 1999
GJC/GJL/GGP
352-PIN BALL GRID ARRAY (BGA) PACKAGES
(BOTTOM VIEW)
Highest Performance Fixed-Point Digital
Signal Processor (DSP) TMS320C6201
– 6-, 5-ns Instruction Cycle Time
– 167-, 200-MHz Clock Rate
AF
AE
AD
AC
AB
AA
Y
– Eight 32-Bit Instructions/Cycle
– 1336, 1600 MIPS
Highest Performance Fixed-Point Digital
Signal Processor (DSP) TMS320C6201B
– 5-, 4.3-ns Instruction Cycle Time
– 200-, and 233-MHz Clock Rates
– Eight 32-Bit Instructions/Cycle
– 1600, 1860 MIPS
W
V
U
T
R
P
N
M
L
K
J
H
G
F
VelociTI Advanced Very Long Instruction
Word (VLIW) ’C62x CPU Core
– Eight Independent Functional Units:
– Six ALUs (32-/40-Bit)
E
D
C
B
A
1
3
5
7
9
11 13 15 17 19 21 23 25
10 12 14 16 18 20 22 24 26
2
4
6
8
– Two 16-Bit Multipliers (32-Bit Results)
– Load-Store Architecture With 32 32-Bit
General-Purpose Registers
– Instruction Packing Reduces Code Size
– All Instructions Conditional
16-Bit Host-Port Interface (HPI)
– Access to Entire Memory Map
Instruction Set Features
– Byte-Addressable (8-, 16-, 32-Bit Data)
– 32-Bit Address Range
– 8-Bit Overflow Protection
– Saturation
– Bit-Field Extract, Set, Clear
– Bit-Counting
– Normalization
Two Multichannel Buffered Serial Ports
(McBSPs)
– Direct Interface to T1/E1, MVIP, SCSA
Framers
– ST-Bus-Switching Compatible
– Up to 256 Channels Each
– AC97-Compatible
– Serial Peripheral Interface (SPI)
Compatible (Motorola )
1M-Bit On-Chip SRAM
– 512K-Bit Internal Program/Cache
(16K 32-Bit Instructions)
Two 32-Bit General-Purpose Timers
Flexible Phase-Locked Loop (PLL) Clock
Generator
– 512K-Bit Dual-Access Internal Data
(64K Bytes) Organized as a Single Block
(’6201)
†
IEEE-1149.1 (JTAG ) Boundary-Scan
– 512K-Bit Dual-Access Internal Data
(64K Bytes) Organized as Two Blocks for
Improved Concurrency (’6201B)
Compatible
352-Pin BGA Package (GGP Suffix) (’6201)
352-Pin BGA Package (GJC Suffix) (’6201B)
352-Pin BGA Package (GJL Suffix) (’6201B)
32-Bit External Memory Interface (EMIF)
– Glueless Interface to Synchronous
Memories: SDRAM and SBSRAM
– Glueless Interface to Asynchronous
Memories: SRAM and EPROM
CMOS Technology
– 0.25-µm/5-Level Metal Process (’6201)
– 0.18-µm/5-Level Metal Process (’6201B)
3.3-V I/Os, 2.5-V Internal (’6201)
3.3-V I/Os, 1.8-V Internal (’6201B)
Four-Channel Bootloading
Direct-Memory-Access (DMA) Controller
with an Auxiliary Channel
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
VelociTI is a trademark of Texas Instruments Incorporated.
Motorola is a trademark of Motorola, Inc.
†
IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
Copyright 1999, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
1
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS320C6201, TMS320C6201B
DIGITAL SIGNAL PROCESSORS
SPRS051F – JANUARY 1997 – REVISED AUGUST 1999
description
†
The TMS320C62x DSPs (including the TMS320C6201 and the TMS320C6201B devices) are the fixed-point
DSP family in the TMS320C6000 platform. The TMS320C6201 (’C6201) and the TMS320C6201B (’C6201B)
devices are based on the high-performance, advanced VelociTI very-long-instruction-word (VLIW) architecture
developed by Texas Instruments (TI ), making these DSPs an excellent choice for multichannel and
multifunction applications. With performance of up to 1600 million instructions per second (MIPS) at a clock rate
of 200 MHz, the ’C6201 offers cost-effective solutions to high-performance DSP programming challenges. The
’C6201B is a newer revision of the ’C6201 with performance of up to 1860 MIPS at a clock rate of 233 MHz.
The ’C6201/’C6201B DSPs possess the operational flexibility of high-speed controllers and the numerical
capability of array processors. Each of these processors have 32 general-purpose registers of 32-bit word
length and eight highly independent functional units. The eight functional units provide six arithmetic logic units
(ALUs) for a high degree of parallelism and two 16-bit multipliers for a 32-bit result. Both the ’C6201 and the
’C6201B can produce two multiply-accumulates (MACs) per cycle—for a total of 400 million MACs per second
(MMACS) for the ’C6201, and a total of 466 MMACS for the ’C6201B. The ’C62x DSP also has
application-specific hardware logic, on-chip memory, and additional on-chip peripherals.
The ’C6201/’C6201B includes a large bank of on-chip memory and has a powerful and diverse set of
peripherals. Program memory consists of a 64K-byte block that is user-configurable as cache or
memory-mapped program space. Data memory of the ’C6201 consists of a 64K-byte block of RAM, while data
memory of the ’C6201B consists of two 32K-byte blocks of RAM for improved concurrency. The peripheral set
includes two multichannel buffered serial ports (McBSPs), two general-purpose timers, a host-port interface
(HPI), and a glueless external memory interface (EMIF) capable of interfacing to SDRAM or SBSRAM and
asynchronous peripherals.
The ’C62x has a complete set of development tools which includes: a new C compiler, an assembly optimizer
to simplify programming and scheduling, and a Windows debugger interface for visibility into source code
execution.
device characteristics
Table 1 provides an overview of the ’C62x DSP. The table shows significant features of each device, including
the capacity of on-chip RAM, the peripherals, the execution time, and the package type with pin count.
Table 1. Characteristics of the ’C6201/’C6201B Processors
CHARACTERISTICS
DESCRIPTION
TMS320C6201B
Device Number
TMS320C6201
512-Kbit Program Memory
512-Kbit Data Memory (organized as a single block)
512-Kbit Program Memory
512-Kbit Data Memory (organized as two blocks)
On-Chip Memory
Peripherals
2 Multichannel Buffered Serial Ports (McBSPs)
2 General-Purpose Timers
Host-Port Interface (HPI)
2 Multichannel Buffered Serial Ports (McBSPs)
2 General-Purpose Timers
Host-Port Interface (HPI)
External Memory Interface (EMIF)
External Memory Interface (EMIF)
5 ns (TMS320C6201-200),
6 ns (TMS320C6201-167)
4.3 ns (TMS320C6201B-233),
5 ns (TMS320C6201B-200)
Cycle Time
35 mm × 35 mm, 352-Pin BGA (GJC),
27 mm × 27 mm, 352-Pin BGA (GJL)
Package Type
Nominal Voltage
35 mm × 35 mm, 352-Pin BGA (GGP)
2.5 V Core
3.3 V I/O
1.8 V Core
3.3 V I/O
TI is a trademark of Texas Instruments Incorporated.
Windows is a registered trademark of the Microsoft Corporation.
†
Where unique device characteristics are specified, TMS320C6201 and TMS320C6201B identifiers are used. For generic characteristics, no
identifiers are needed, ’C62x is used, or ’C6000 is used.
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POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS320C6201, TMS320C6201B
DIGITAL SIGNAL PROCESSORS
SPRS051F – JANUARY 1997 – REVISED AUGUST 1999
functional block diagram
Timers
Interrupt Selector
McBSPs
Data Memory
Peripheral
Bus
Controller
HPI Control
DMA Control
EMIF Control
Data Memory
Controller
DMA
Controller
Host-Port Interface
PLL
CPU
EMIF
Power
Down
Program Memory Controller
Boot-
Config.
Program Memory/Cache
3
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS320C6201, TMS320C6201B
DIGITAL SIGNAL PROCESSORS
SPRS051F – JANUARY 1997 – REVISED AUGUST 1999
CPU description
The CPU fetches VelociTI advanced very-long instruction words (VLIW) (256 bits wide) to supply up to eight
32-bit instructions to the eight functional units during every clock cycle. The VelociTI VLIW architecture features
controls by which all eight units do not have to be supplied with instructions if they are not ready to execute. The
first bit of every 32-bit instruction determines if the next instruction belongs to the same execute packet as the
previous instruction, or whether it should be executed in the following clock as a part of the next execute packet.
Fetch packets are always 256 bits wide; however, the execute packets can vary in size. The variable-length
executepacketsareakeymemory-savingfeature, distinguishingthe’C62xCPUfromotherVLIWarchitectures.
The CPU features two sets of functional units. Each set contains four units and a register file. One set contains
functional units .L1, .S1, .M1, and .D1; the other set contains units .D2, .M2, .S2, and .L2. The two register files
eachcontain1632-bitregistersforatotalof32general-purposeregisters. Thetwosetsoffunctionalunits, along
with two register files, compose sides A and B of the CPU (see Figure 1 and Figure 2). The four functional units
on each side of the CPU can freely share the 16 registers belonging to that side. Additionally, each side features
a single data bus connected to all the registers on the other side, by which the two sets of functional units can
access data from the register files on the opposite side. While register access by functional units on the same
side of the CPU as the register file can service all the units in a single clock cycle, register access using the
register file across the CPU supports one read and one write per cycle.
Another key feature of the ’C62x CPU is the load/store architecture, where all instructions operate on registers
(as opposed to data in memory). Two sets of data-addressing units (.D1 and .D2) are responsible for all data
transfers between the register files and the memory. The data address driven by the .D units allows data
addresses generated from one register file to be used to load or store data to or from the other register file. The
’C62x CPU supports a variety of indirect addressing modes using either linear- or circular-addressing modes
with 5- or 15-bit offsets. All instructions are conditional, and most can access any one of the 32 registers. Some
registers, however, are singled out to support specific addressing or to hold the condition for conditional
instructions (if the condition is not automatically “true”). The two .M functional units are dedicated for multiplies.
The two .S and .L functional units perform a general set of arithmetic, logical, and branch functions with results
available every clock cycle.
The processing flow begins when a 256-bit-wide instruction fetch packet is fetched from a program memory.
The 32-bit instructions destined for the individual functional units are “linked” together by “1” bits in the least
significant bit (LSB) position of the instructions. The instructions that are “chained” together for simultaneous
execution (up to eight in total) compose an execute packet. A “0” in the LSB of an instruction breaks the chain,
effectivelyplacing the instructions that follow it in the next execute packet. If an execute packet crosses the fetch
packet boundary (256 bits wide), the assembler places it in the next fetch packet, while the remainder of the
current fetch packet is padded with NOP instructions. The number of execute packets within a fetch packet can
vary from one to eight. Execute packets are dispatched to their respective functional units at the rate of one per
clock cycle and the next 256-bit fetch packet is not fetched until all the execute packets from the current fetch
packet have been dispatched. After decoding, the instructions simultaneously drive all active functional units
for a maximum execution rate of eight instructions every clock cycle. While most results are stored in 32-bit
registers, they can be subsequently moved to memory as bytes or half-words as well. All load and store
instructions are byte-, half-word, or word-addressable.
4
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS320C6201, TMS320C6201B
DIGITAL SIGNAL PROCESSORS
SPRS051F – JANUARY 1997 – REVISED AUGUST 1999
CPU description (continued)
Program Memory
32-Bit Address
256-Bit Data
’C62x CPU
Program Fetch
Control
Registers
Instruction Dispatch
Instruction Decode
Data Path A
Data Path B
Control
Logic
External Memory
Interface
Register File A
Register File B
Test
Emulation
Interrupts
.M2
.S2 .L2
.L1 .S1 .M1 .D1
.D2
Additional
Peripherals:
Timers,
Serial Ports,
etc.
Data Memory
32-Bit Address
8-, 16-, 32-Bit Data
Figure 1. TMS320C62x CPU Block Diagram
5
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS320C6201, TMS320C6201B
DIGITAL SIGNAL PROCESSORS
SPRS051F – JANUARY 1997 – REVISED AUGUST 1999
CPU description (continued)
src1
src2
dst
long dst
long src
.L1
8
8
32
ST1
8
long src
long dst
dst
Register
File A
Data Path A
.S1
src1
(A0–A15)
src2
dst
src1
.M1
.D1
src2
LD1
dst
src1
src2
DA1
2X
1X
src2
src1
dst
DA2
.D2
LD2
src2
.M2
.S2
src1
dst
src2
Register
File B
(B0–B15)
Data Path B
src1
dst
long dst
long src
8
32
8
ST2
8
long src
long dst
dst
.L2
src2
src1
Control
Register
File
Figure 2. TMS320C62x CPU Data Paths
6
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS320C6201, TMS320C6201B
DIGITAL SIGNAL PROCESSORS
SPRS051F – JANUARY 1997 – REVISED AUGUST 1999
signal groups description
CLKIN
CLKOUT2
CLKOUT1
CLKMODE1
CLKMODE0
PLLFREQ3
PLLFREQ2
PLLFREQ1
PLLV
BOOTMODE4
BOOTMODE3
BOOTMODE2
BOOTMODE1
BOOTMODE0
Boot Mode
Clock/PLL
RESET
NMI
PLLG
PLLF
EXT_INT7
EXT_INT6
EXT_INT5
EXT_INT4
IACK
Reset and
Interrupts
INUM3
INUM2
TMS
TDO
INUM1
INUM0
TDI
TCK
TRST
EMU1
EMU0
JTAG
Emulation
Little ENDIAN
Big ENDIAN
LENDIAN
RSV9
RSV8
RSV7
RSV6
RSV5
RSV4
RSV3
RSV2
RSV1
RSV0
DMAC3
DMAC2
DMAC1
DMAC0
DMA Status
Reserved
Power-Down
Status
PD
Control/Status
HPI
16
(Host-Port Interface)
HD[15:0]
Data
HAS
HR/W
HCS
HDS1
HDS2
HRDY
HINT
HCNTL0
HCNTL1
Register Select
Control
HHWIL
HBE1
HBE0
Half-Word/Byte
Select
Figure 3. CPU and Peripheral Signals
7
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS320C6201, TMS320C6201B
DIGITAL SIGNAL PROCESSORS
SPRS051F – JANUARY 1997 – REVISED AUGUST 1999
signal groups description (continued)
32
ED[31:0]
Data
ARE
Asynchronous
Memory
AOE
AWE
ARDY
CE3
CE2
CE1
CE0
Control
Memory Map
Space Select
SSADS
SSOE
SSWE
SSCLK
SBSRAM
Control
20
EA[21:2]
Word Address
Byte Enables
BE3
BE2
BE1
BE0
SDA10
SDRAS
SDCAS
SDWE
SDRAM
Control
SDCLK
HOLD
HOLD/
HOLDA
HOLDA
EMIF
(External Memory Interface)
TOUT1
TINP1
TOUT0
TINP0
Timer 1
Timer 0
Timers
McBSP1
Transmit
McBSP0
Transmit
CLKX1
FSX1
DX1
CLKX0
FSX0
DX0
CLKR1
FSR1
DR1
CLKR0
FSR0
DR0
Receive
Clock
Receive
Clock
CLKS1
CLKS0
McBSPs
(Multichannel Buffered Serial Ports)
Figure 4. Peripheral Signals
8
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS320C6201, TMS320C6201B
DIGITAL SIGNAL PROCESSORS
SPRS051F – JANUARY 1997 – REVISED AUGUST 1999
Signal Descriptions
SIGNAL
†
TYPE
DESCRIPTION
GGP, GJC
PIN NO.
GJL
PIN NO.
NAME
CLOCK/PLL
CLKIN
C10
AF22
AF20
C6
B9
AC18
AC16
D8
I
Clock Input
CLKOUT1
CLKOUT2
CLKMODE1
CLKMODE0
PLLFREQ3
O
O
Clock output at full device speed
Clock output at half of device speed
Clock-mode select
I
C5
C7
•
Selects whether the CPU clock frequency = input clock frequency x4 or x1
PLL frequency range (3, 2, and 1)
The target range for CLKOUT1 frequency is determined by the 3-bit value of the
PLLFREQ pins.
A9
A9
•
PLLFREQ2
D11
D11
I
PLLFREQ1
B10
D12
C12
A11
B10
B11
C12
D12
‡
§
A
§
A
§
A
PLLV
PLL analog V connection for the low-pass filter
CC
‡
PLLG
PLL analog GND connection for the low-pass filter
PLL low-pass filter connection to external components and a bypass capacitor
JTAG EMULATION
PLLF
TMS
TDO
TDI
L3
W2
R4
R3
T1
L3
U4
T2
I
JTAG test port mode select (features an internal pullup)
JTAG test port data out
O/Z
I
I
I
JTAG test port data in (features an internal pullup)
JTAG test port clock
TCK
R3
R4
V3
W2
TRST
EMU1
EMU0
JTAG test port reset (features an internal pulldown)
¶
¶
Y1
W3
I/O/Z
I/O/Z
Emulation pin 1, pullup with a dedicated 20-kΩ resistor
Emulation pin 0, pullup with a dedicated 20-kΩ resistor
RESET AND INTERRUPTS
RESET
NMI
K2
L2
K2
L2
I
I
Device reset
Nonmaskable interrupt
•
Edge-driven (rising edge)
EXT_INT7
EXT_INT6
EXT_INT5
EXT_INT4
IACK
U3
V2
U2
T4
External interrupts
Edge-driven (rising edge)
I
•
W1
U4
V1
V2
Y2
Y1
O
O
Interrupt acknowledge for all active interrupts serviced by the CPU
Active interrupt identification number
INUM3
AA1
W4
AA2
AB1
V4
INUM2
Y2
•
•
Valid during IACK for all active interrupts (not just external)
Encoding order follows the interrupt-service fetch-packet ordering
INUM1
AA1
W4
INUM0
LITTLE ENDIAN/BIG ENDIAN
If high, LENDIAN selects little-endian byte/half-word addressing order within a word
If low, LENDIAN selects big-endian addressing
LENDIAN
H3
G2
I
POWER-DOWN STATUS
PD
D3
E2
O
Power-down mode 2 or 3 (active if high)
†
‡
§
¶
I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground
PLLV and PLLG are not part of external voltage supply or ground. See the clock PLL section for information on how to connect these pins.
A = Analog Signal (PLL Filter)
For emulation and normal operation, pull up EMU1 and EMU0 with a dedicated 20-kΩ resistor. For boundary scan, pull down EMU1 and EMU0
with a dedicated 20-kΩ resistor.
9
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS320C6201, TMS320C6201B
DIGITAL SIGNAL PROCESSORS
SPRS051F – JANUARY 1997 – REVISED AUGUST 1999
Signal Descriptions (Continued)
SIGNAL
†
TYPE
DESCRIPTION
GGP, GJC
PIN NO.
GJL
PIN NO.
NAME
HOST-PORT INTERFACE (HPI)
HINT
H26
F23
D25
C26
E23
D24
C23
B13
B14
C14
B15
D15
B16
A17
B17
D16
B18
A19
C18
B19
C19
B20
B21
C22
B23
D22
A24
J24
J26
G24
F25
E26
F24
E25
B22
A12
D13
C13
D14
B15
C15
D15
B16
C16
B17
D16
A18
B18
D17
C18
A20
C20
B21
C21
D20
J25
O
I
Host interrupt (from DSP to host)
HCNTL1
HCNTL0
HHWIL
HBE1
HBE0
HR/W
HD15
HD14
HD13
HD12
HD11
HD10
HD9
Host control – selects between control, address, or data registers
Host control – selects between control, address, or data registers
Host half-word select – first or second half-word (not necessarily high or low order)
Host byte select within word or half-word
I
I
I
I
Host byte select within word or half-word
I
Host read or write select
HD8
I/O/Z
Host-port data (used for transfer of data, address, and control)
HD7
HD6
HD5
HD4
HD3
HD2
HD1
HD0
HAS
I
I
Host address strobe
Host chip select
HCS
HDS1
HDS2
HRDY
I
Host data strobe 1
Host data strobe 2
Host ready (from DSP to host)
BOOT MODE
I
O
BOOTMODE4
BOOTMODE3
BOOTMODE2
BOOTMODE1
BOOTMODE0
D8
B4
A3
D5
C4
C8
B6
D7
C6
B5
I
Boot mode
†
I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground
10
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS320C6201, TMS320C6201B
DIGITAL SIGNAL PROCESSORS
SPRS051F – JANUARY 1997 – REVISED AUGUST 1999
Signal Descriptions (Continued)
SIGNAL
†
TYPE
DESCRIPTION
GGP, GJC
PIN NO.
GJL
PIN NO.
NAME
EMIF – CONTROL SIGNALS COMMON TO ALL TYPES OF MEMORY
CE3
AE22
AD26
AB24
AC26
AB25
AA24
Y23
AD20
CE2
CE1
CE0
BE3
BE2
BE1
BE0
AA24
AB26
AA25
Y24
Memory space enables
O/Z
O/Z
•
•
Enabled by bits 24 and 25 of the word address
Only one asserted during any external data access
Byte-enable control
W23
AA26
W25
•
•
•
Decoded from the two lowest bits of the internal address
Byte-write enables for most types of memory
Can be directly connected to SDRAM read and write mask signal (SDQM)
EMIF – ADDRESS
AA26
EA21
EA20
EA19
EA18
EA17
EA16
EA15
EA14
EA13
EA12
EA11
EA10
EA9
J26
K25
L24
K26
M26
M25
P25
P24
R25
T26
R23
U26
U25
T23
V26
V25
W26
V24
W25
Y26
K25
L24
L25
M23
M25
M24
N23
P24
P23
R25
R24
R23
T25
T24
U25
T23
V26
V25
U23
V24
O/Z
External address (word address)
EA8
EA7
EA6
EA5
EA4
EA3
EA2
†
I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground
11
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS320C6201, TMS320C6201B
DIGITAL SIGNAL PROCESSORS
SPRS051F – JANUARY 1997 – REVISED AUGUST 1999
Signal Descriptions (Continued)
SIGNAL
†
TYPE
DESCRIPTION
GGP, GJC
PIN NO.
GJL
PIN NO.
NAME
EMIF – DATA
ED31
AB2
AC1
Y3
ED30
ED29
ED28
ED27
ED26
ED25
ED24
ED23
ED22
ED21
ED20
ED19
ED18
ED17
ED16
ED15
ED14
ED13
ED12
ED11
ED10
ED9
AA2
AA4
AB1
AD1
AA3
AC3
AB2
AD4
AE5
AF3
AD6
AE4
AC7
AD5
AE6
AF4
AD7
AE5
AC8
AD6
AD8
AE6
AC9
AD7
AF7
AC8
AD9
AF7
AC10
AE9
I/O/Z
External data
AD9
AD10
AF9
AF9
AC11
AE10
AD11
AE11
AC12
AD12
AE12
AC13
AD14
AC14
AE15
AD15
AE16
AD16
AC11
AE10
AE11
AF11
AE14
AF15
AE15
AF16
AC15
AE17
AF18
AF19
AC17
ED8
ED7
ED6
ED5
ED4
ED3
ED2
ED1
ED0
EMIF – ASYNCHRONOUS MEMORY CONTROL
ARE
Y24
AC24
AD23
W23
V23
AB25
AE22
Y26
O/Z
O/Z
O/Z
I
Asynchronous memory read enable
Asynchronous memory output enable
Asynchronous memory write enable
Asynchronous memory ready input
AOE
AWE
ARDY
†
I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground
12
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TMS320C6201, TMS320C6201B
DIGITAL SIGNAL PROCESSORS
SPRS051F – JANUARY 1997 – REVISED AUGUST 1999
Signal Descriptions (Continued)
SIGNAL
†
TYPE
DESCRIPTION
GGP, GJC
PIN NO.
GJL
PIN NO.
NAME
EMIF – SYNCHRONOUS BURST SRAM (SBSRAM) CONTROL
SSADS
AC20
AF21
AD19
AD17
AD19
AD18
AF18
AC15
O/Z
O/Z
O/Z
O
SBSRAM address strobe
SBSRAM output enable
SBSRAM write enable
SBSRAM clock
SSOE
SSWE
SSCLK
EMIF – SYNCHRONOUS DRAM (SDRAM) CONTROL
SDA10
SDRAS
SDCAS
SDWE
SDCLK
AD21
AF24
AD22
AF23
AE20
AC19
AD21
AC20
AE21
AC17
O/Z
O/Z
O/Z
O/Z
O
SDRAM address 10 (separate for deactivate command)
SDRAM row-address strobe
SDRAM column-address strobe
SDRAM write enable
SDRAM clock
EMIF – BUS ARBITRATION
Hold request from the host
HOLD
AA25
A7
Y25
C9
I
HOLDA
O
Hold-request acknowledge to the host
TIMERS
TOUT1
TINP1
TOUT0
TINP0
H24
K24
M4
K23
L23
M4
O
I
Timer 1 or general-purpose output
Timer 1 or general-purpose input
Timer 0 or general-purpose output
Timer 0 or general-purpose input
DMA ACTION COMPLETE STATUS
O
I
K4
H2
DMAC3
DMAC2
DMAC1
DMAC0
D2
F4
D1
E2
E1
F2
G3
H4
O
DMA action complete
MULTICHANNEL BUFFERED SERIAL PORT 1 (McBSP1)
CLKS1
CLKR1
CLKX1
DR1
E25
H23
F26
D26
G23
E26
F25
F26
H25
J24
I
External clock source (as opposed to internal)
Receive clock
I/O/Z
I/O/Z
I
Transmit clock
H23
G25
J23
Receive data
DX1
O/Z
I/O/Z
I/O/Z
Transmit data
FSR1
FSX1
Receive frame sync
Transmit frame sync
G26
†
I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground
13
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TMS320C6201, TMS320C6201B
DIGITAL SIGNAL PROCESSORS
SPRS051F – JANUARY 1997 – REVISED AUGUST 1999
Signal Descriptions (Continued)
SIGNAL
†
TYPE
DESCRIPTION
GGP, GJC
PIN NO.
GJL
PIN NO.
NAME
MULTICHANNEL BUFFERED SERIAL PORT 0 (McBSP0)
CLKS0
L4
M2
L1
J1
L4
M2
M3
J1
I
External clock source (as opposed to internal)
Receive clock
CLKR0
CLKX0
DR0
I/O/Z
I/O/Z
I
Transmit clock
Receive data
DX0
R1
P4
P3
P4
N3
N4
O/Z
I/O/Z
I/O/Z
Transmit data
FSR0
FSX0
Receive frame sync
Transmit frame sync
RESERVED FOR TEST
RSV0
RSV1
RSV2
RSV3
RSV4
RSV5
RSV6
RSV7
RSV8
RSV9
T2
G2
T3
F1
I
I
Reserved for testing, pullup with a dedicated 20-kΩ resistor
Reserved for testing, pullup with a dedicated 20-kΩ resistor
Reserved for testing, pullup with a dedicated 20-kΩ resistor
Reserved for testing, pullup with a dedicated 20-kΩ resistor
Reserved for testing, pulldown with a dedicated 20-kΩ resistor
Reserved (leave unconnected, do not connect to power or ground)
Reserved for testing, pullup with a dedicated 20-k resistor
Reserved for testing, pullup with a dedicated 20-k resistor
Reserved for testing, pullup with a dedicated 20-k resistor
Reserved (leave unconnected, do not connect to power or ground)
UNCONNECTED PINS
C11
B9
C11
D10
D9
I
I
A6
I
C8
A7
O
I
C21
B22
A23
E4
D18
C19
D19
F3
I
I
O
A8
B8
AF20
AE18
AE17
–
C9
D10
D21
G1
H1
H2
J2
–
NC
J4
Unconnected pins
J3
G1
K4
K3
J2
R2
R2
†
I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground
14
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DIGITAL SIGNAL PROCESSORS
SPRS051F – JANUARY 1997 – REVISED AUGUST 1999
Signal Descriptions (Continued)
SIGNAL
†
TYPE
DESCRIPTION
GGP, GJC
PIN NO.
GJL
PIN NO.
NAME
3.3-V SUPPLY VOLTAGE PINS
A10
A15
A5
A11
A16
A22
B7
A18
A21
A22
B7
B8
C1
B19
B20
C10
C14
C17
G4
D17
F3
G24
G25
H25
J25
G23
H3
L25
M3
H24
K3
N3
N23
R26
T24
K24
L1
L26
N24
P3
U24
W24
Y4
DV
S
3.3-V supply voltage
DD
T1
AB3
AB4
AB26
AC6
AC10
AC19
AC21
AC22
AC25
AD11
AD13
AD15
AD18
AE18
AE21
AF5
AF6
AF17
T26
U3
U24
W3
W24
Y4
Y23
AD10
AD13
AD17
AE7
AE8
AE19
AE20
AF5
AF11
AF16
AF22
†
I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground
15
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TMS320C6201, TMS320C6201B
DIGITAL SIGNAL PROCESSORS
SPRS051F – JANUARY 1997 – REVISED AUGUST 1999
Signal Descriptions (Continued)
SIGNAL
†
TYPE
DESCRIPTION
GGP, GJC
PIN NO.
GJL
PIN NO.
NAME
2.5-V SUPPLY VOLTAGE PINS FOR ’C6201
1.8-V SUPPLY VOLTAGE PINS FOR ’C6201B
A5
A12
A16
A20
B2
A1
A2
A3
A24
A25
A26
B1
B6
B11
B12
B25
C3
B2
B3
B24
B25
B26
C1
C15
C20
C24
D4
C2
D6
C3
D7
C4
D9
C23
C24
C25
C26
D3
D14
D18
D20
D23
E1
2.5-V supply voltage for ’C6201
1.8-V supply voltage for ’C6201B
CV
S
DD
D4
F1
D5
H4
D22
D23
D24
E4
J4
J23
K1
K23
M1
M24
N4
E23
AB4
AB23
AC3
AC4
AC5
AC22
AC23
AC24
AD1
AD2
N25
P2
P23
T3
T4
U1
V4
†
I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground
16
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TMS320C6201, TMS320C6201B
DIGITAL SIGNAL PROCESSORS
SPRS051F – JANUARY 1997 – REVISED AUGUST 1999
Signal Descriptions (Continued)
SIGNAL
†
TYPE
DESCRIPTION
GGP, GJC
PIN NO.
GJL
PIN NO.
NAME
2.5-V SUPPLY VOLTAGE PINS FOR ’C6201
1.8-V SUPPLY VOLTAGE PINS FOR ’C6201B (CONTINUED)
V23
AC4
AC9
AC12
AC13
AC18
AC23
AD3
AD8
AD14
AD24
AE2
AE8
AE12
AE25
AF12
–
AD3
AD4
AD23
AD24
AD25
AD26
AE1
AE2
AE3
2.5-V supply voltage for ’C6201
1.8-V supply voltage for ’C6201B
CV
S
DD
AE24
AE25
AE26
AF1
AF2
AF3
AF24
AF25
AF26
–
GROUND PINS
A1
A2
A4
A6
A4
A8
A13
A14
A25
A26
B1
A10
A13
A14
A15
A17
A19
A21
A23
B4
B3
V
SS
B5
GND
Ground pins
B24
B26
C2
B12
B13
B14
B23
C5
C7
C13
C16
C17
C25
D13
C22
D1
†
I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground
17
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TMS320C6201, TMS320C6201B
DIGITAL SIGNAL PROCESSORS
SPRS051F – JANUARY 1997 – REVISED AUGUST 1999
Signal Descriptions (Continued)
SIGNAL
†
TYPE
DESCRIPTION
GGP, GJC
PIN NO.
GJL
PIN NO.
NAME
GROUND PINS (CONTINUED)
D19
E3
D2
D6
E24
F2
D21
D25
D26
E3
F24
G3
G4
E24
F4
G26
J3
F23
H1
L23
L26
M23
N1
H26
K1
K26
M1
N2
N24
N26
P1
M26
N1
N2
P26
R24
T25
U2
N25
N26
P1
V
SS
GND
Ground pins
P2
U23
V1
P25
P26
R1
V3
Y3
R26
U1
Y25
AA3
AA23
AB23
AC2
AC5
AC7
AC14
AC16
AD2
AD12
AD16
AD20
U26
W1
W26
AA4
AA23
AB3
AB24
AC1
AC2
AC6
AC21
AC25
†
I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground
18
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TMS320C6201, TMS320C6201B
DIGITAL SIGNAL PROCESSORS
SPRS051F – JANUARY 1997 – REVISED AUGUST 1999
Signal Descriptions (Continued)
SIGNAL
†
TYPE
DESCRIPTION
GGP, GJC
PIN NO.
GJL
PIN NO.
NAME
GROUND PINS (CONTINUED)
AD25
AE1
AC26
AD5
AE3
AD22
AE4
AE7
AE9
AE13
AE14
AE23
AF4
AE13
AE16
AE19
AE23
AE24
AE26
AF1
AF6
V
SS
AF8
GND
Ground pins
AF10
AF12
AF13
AF14
AF15
AF17
AF19
AF21
AF23
AF2
AF8
AF10
AF13
AF14
AF25
AF26
†
I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground
19
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TMS320C6201, TMS320C6201B
DIGITAL SIGNAL PROCESSORS
SPRS051F – JANUARY 1997 – REVISED AUGUST 1999
development support
Texas Instruments offers an extensive line of development tools for the ’C6000 generation of DSPs, including
tools to evaluate the performance of the processors, generate code, develop algorithm implementations, and
fully integrate and debug software and hardware modules.
The following products support development of ’C6000-based applications:
Software Development Tools:
Assembly optimizer
Assembler/Linker
Simulator
Optimizing ANSI C compiler
Application algorithms
C/Assembly debugger and code profiler
Hardware Development Tools:
Extended development system (XDS ) emulator (supports ’C6000 multiprocessor system debug)
EVM (Evaluation Module)
The TMS320 DSP Development Support Reference Guide (SPRU011) contains information about
development-support products for all TMS320 family member devices, including documentation. See this
document for further information on TMS320 documentation or any TMS320 support products from Texas
Instruments. An additional document, the TMS320 Third-Party Support Reference Guide (SPRU052), contains
informationaboutTMS320-relatedproductsfromothercompaniesintheindustry. ToreceiveTMS320literature,
contact the Literature Response Center at 800/477-8924.
See Table 2 for a complete listing of development-support tools for the ’C6000. For information on pricing and
availability, contact the nearest TI field sales office or authorized distributor.
Table 2. TMS320C6000 Development-Support Tools
DEVELOPMENT TOOL
PLATFORM
Software
PART NUMBER
C Compiler/Assembler/Linker/Assembly Optimizer
C Compiler/Assembler/Linker/Assembly Optimizer
Simulator
Win32
TMDX3246855-07
SPARC Solaris
Win32
TMDX324655-07
TMDS3246851-07
TMDS3246551-07
TMDX324016X-07
Simulator
SPARC Solaris
Win32, Windows NT
Hardware
XDS510 Debugger/Emulation Software
†
XDS510 Emulator
PC
TMDS00510
‡
XDS510WS Emulator
SCSI
TMDS00510WS
Software/Hardware
PC/Win95/Windows NT
PC/Win95/Windows NT
EVM Evaluation Kit
TMDX3260A6201
TMDX326006201
EVM Evaluation Kit (including TMDX3246855–07)
†
‡
Includes XDS510 board and JTAG emulation cable. TMDX324016X-07 C-source Debugger/Emulation software is not included.
Includes XDS510WS box, SCSI cable, power supply, and JTAG emulation cable.
XDS, XDS510, and XDS510WS are trademarks of Texas Instruments Incorporated.
Win32 and Windows NT are trademarks of Microsoft Corporation.
SPARC is a trademark of SPARC International, Inc.
Solaris is a trademark of Sun Microsystems, Inc.
20
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TMS320C6201, TMS320C6201B
DIGITAL SIGNAL PROCESSORS
SPRS051F – JANUARY 1997 – REVISED AUGUST 1999
device and development-support tool nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all TMS320
devices and support tools. Each TMS320 member has one of three prefixes: TMX, TMP, or TMS. Texas
Instruments recommends two of three possible prefix designators for support tools: TMDX and TMDS. These
prefixes represent evolutionary stages of product development from engineering prototypes (TMX/TMDX)
through fully qualified production devices/tools (TMS/TMDS). This development flow follows.
Device development evolutionary flow:
TMX
TMP
TMS
Experimental device that is not necessarily representative of the final device’s electrical
specifications
Final silicon die that conforms to the device’s electrical specifications but has not completed
quality and reliability verification
Fully qualified production device
Support tool development evolutionary flow:
TMDX
Development-support product that has not yet completed Texas Instruments internal qualification
testing.
TMDS
Fully qualified development-support product
TMX and TMP devices and TMDX development-support tools are shipped against the following disclaimer:
“Developmental product is intended for internal evaluation purposes.”
TMS devices and TMDS development-support tools have been characterized fully, and the quality and reliability
of the device have been demonstrated fully. TI’s standard warranty applies.
Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard production
devices. TexasInstrumentsrecommendsthatthesedevicesnotbeusedinanyproductionsystembecausetheir
expected end-use failure rate still is undefined. Only qualified production devices are to be used.
TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package type
(for example, GGP, GJC, or GJL), the temperature range (for example, blank is the default commercial
temperature range), and the device speed range in megahertz (for example, -200 is 200 MHz). Figure 5
provides a legend for reading the complete device name for any TMS320 family member.
21
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TMS320C6201, TMS320C6201B
DIGITAL SIGNAL PROCESSORS
SPRS051F – JANUARY 1997 – REVISED AUGUST 1999
device and development-support tool nomenclature (continued)
(A)
TMS 320
C
6201 GGP
–200
PREFIX
DEVICE SPEED RANGE
–100 MHz
TMX= Experimental device
TMP= Prototype device
TMS= Qualified device
SMJ = MIL-STD-883C
–150 MHz
–167 MHz
–200 MHz
–233 MHz
SM = High Rel (non-883C)
–250 MHz
–300 MHz
DEVICE FAMILY
320 = TMS320 family
TEMPERATURE RANGE (DEFAULT: 0°C TO 90°C)
Blank = 0°C to 90°C, commercial temperature
A
= –40°C to 105°C, extended temperature
†
PACKAGE TYPE
N
=
=
=
=
=
=
=
=
=
=
Plastic DIP
J
Ceramic DIP
TECHNOLOGY
JD
GB
FZ
FN
FD
PJ
PQ
PZ
Ceramic DIP side-brazed
Ceramic PGA
Ceramic CC
Plastic leaded CC
Ceramic leadless CC
100-pin plastic EIAJ QFP
132-pin plastic bumpered QFP
100-pin plastic TQFP
C
E
F
=
=
=
CMOS
CMOS EPROM
CMOS Flash EEPROM
PBK = 128-pin plastic TQFP
PGE = 144-pin plastic TQFP
GFN = 256-pin plastic BGA
GGU = 144-pin plastic BGA
GGP = 352-pin plastic BGA
GJC = 352-pin plastic BGA
GJL = 352-pin plastic BGA
GLS = 384-pin plastic BGA
DEVICE
’1x DSP:
10
14
15
16
17
’2x DSP:
’2xx DSP:
’3x DSP:
25
26
203 206 240
204 209
30
31
32
’4x DSP:
’5x DSP:
40
44
50
51
52
53
56
57
’54x DSP:
’6x DSP:
541 545
542 546
543 548
†
DIP
PGA
CC
=
=
=
=
Dual-In-Line Package
Pin Grid Array
Chip Carrier
6201
6201B
6202
6203
6211
6701
6711
QFP
Quad Flat Package
TQFP = Thin Quad Flat Package
BGA Ball Grid Array
=
Figure 5. TMS320 Device Nomenclature (Including TMS320C6201/TMS320C6201B)
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TMS320C6201, TMS320C6201B
DIGITAL SIGNAL PROCESSORS
SPRS051F – JANUARY 1997 – REVISED AUGUST 1999
documentation support
Extensive documentation supports all TMS320 family generations of devices from product announcement
through applications development. The types of documentation available include: data sheets, such as this
document, with design specifications; complete user’s reference guides for all devices; technical briefs;
development-support tools; and hardware and software applications. The following is a brief, descriptive list of
support documentation specific to the ’C6x devices:
The TMS320C6000 CPU and Instruction Set Reference Guide (literature number SPRU189) describes the
’C6000 CPU architecture, instruction set, pipeline, and associated interrupts.
The TMS320C6000 Peripherals Reference Guide (literature number SPRU190) describes the functionality of
the peripherals available on ’C6x devices, such as the external memory interface (EMIF), host-port interface
(HPI), multichannel buffered serial ports (McBSPs), direct-memory-access (DMA), enhanced
direct-memory-access (EDMA) controller, expansion bus (XB), clocking and phase-locked loop (PLL); and
power-down modes. This guide also includes information on internal data and program memories.
The TMS320C6000 Programmer’s Guide (literature number SPRU198) describes ways to optimize C and
assembly code for ’C6x devices and includes application program examples.
The TMS320C6x C Source Debugger User’s Guide (literature number SPRU188) describes how to invoke the
’C6x simulator and emulator versions of the C source debugger interface and discusses various aspects of the
debugger, including: command entry, code execution, data management, breakpoints, profiling, and analysis.
The TMS320C6x Peripheral Support Library Programmer’s Reference (literature number SPRU273) describes
the contents of the ’C6x peripheral support library of functions and macros. It lists functions and macros both
by header file and alphabetically, provides a complete description of each, and gives code examples to show
how they are used.
TMS320C6000 Assembly Language Tools User’s Guide (literature number SPRU186) describes the assembly
language tools (assembler, linker, and other tools used to develop assembly language code), assembler
directives, macros, common object file format, and symbolic debugging directives for the ’C6000 generation of
devices.
The TMS320C6x Evaluation Module Reference Guide (literature number SPRU269) provides instructions for
installing and operating the ’C6x evaluation module. It also includes support software documentation,
application programming interfaces, and technical reference material.
TMS320C62x Multichannel Evaluation Module User’s Guide (literature number SPRU285) provides
instructions for installing and operating the ’C62x multichannel evaluation module. It also includes support
software documentation, application programming interfaces, and technical reference material.
TMS320C62x Multichannel Evaluation Module Technical Reference (SPRU308) provides provides technical
reference information for the ’C62x multichannel evaluation module (McEVM). It includes support software
documentation, application programming interface references, and hardware descriptions for the ’C62x
McEVM.
TMS320C6000 DSP/BIOS User’s Guide (literature number SPRU303) describes how to use DSP/BIOS tools
and APIs to analyze embedded real-time DSP applications.
Code Composer User’s Guide (literature number SPRU296) explains how to use the Code Composer
development environment to build and debug embedded real-time DSP applications.
Code Composer Studio Tutorial(literaturenumberSPRU301)introducestheCodeComposerStudiointegrated
development environment and software tools.
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TMS320C6201, TMS320C6201B
DIGITAL SIGNAL PROCESSORS
SPRS051F – JANUARY 1997 – REVISED AUGUST 1999
documentation support (continued)
The TMS320C6000 Technical Brief (literature number SPRU197) gives an introduction to the ’C62x/C67x
devices, associated development tools, and third-party support.
A series of DSP textbooks is published by Prentice-Hall and John Wiley & Sons to support DSP research and
education. The TMS320 newsletter, Details on Signal Processing, is published quarterly and distributed to
update TMS320 customers on product information. The TMS320 DSP bulletin board service (BBS) provides
access to information pertaining to the TMS320 family, including documentation, source code, and object code
for many DSP algorithms and utilities. The BBS can be reached at 281/274-2323.
Information regarding TI DSP products is also available on the Worldwide Web at http://www.ti.com uniform
resource locator (URL).
24
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TMS320C6201, TMS320C6201B
DIGITAL SIGNAL PROCESSORS
SPRS051F – JANUARY 1997 – REVISED AUGUST 1999
clock PLL
All of the ’C62x clocks are generated from a single source through the CLKIN pin. This source clock either drives
the PLL, which generates the internal CPU clock, or bypasses the PLL to become the CPU clock.
To use the PLL to generate the CPU clock, the filter circuit shown in Figure 6 must be properly designed. Note
that for ’C6201, the EMI filter must be powered by the core voltage (2.5 V), and for ’C6201B, it must be powered
by the I/O voltage (3.3 V).
To configure the ’C62x PLL clock for proper operation, see Figure 6 and Table 3. To minimize the clock jitter,
a single clean power supply should power both the ’C62x device and the external clock oscillator circuit. The
minimum CLKIN rise and fall times should also be observed. See the input and output clocks section for input
clock timing requirements.
’C6201 CLKOUT1 Frequency Range 40–200 MHz – 0 1 0 – ’C6201B CLKOUT1 Frequency Range 130–233 MHz
’C6201 CLKOUT1 Frequency Range 35–160 MHz – 0 0 1 – ’C6201B CLKOUT1 Frequency Range 65–200 MHz
’C6201 CLKOUT1 Frequency Range 25–135 MHz – 0 0 0 – ’C6201B CLKOUT1 Frequency Range 50–140 MHz
3.3 V 2.5 V
3 OUT
’320C6201/C6201B
EMIF
PLLV
PLLF
R1
CLKOUT1
CLKOUT2
SSCLK
1 IN
CLKOUT
2
PLLG
10 µF
0.1 µF C1 C2
GND
(Bypass)
SDCLK
CLKIN
1 1 – MULT×4
0 1 – Reserved
1 0 – Reserved
0 0 – MULT×1
f(CLKOUT)=f(CLKIN)×4
f(CLKOUT)=f(CLKIN)
NOTES: A. For the ’C6201 CLKMODE x4, values for C1, C2, and R1 depend on CLKIN and CLKOUT frequencies.
For the ’C6201B CLKMODE x4, values for C1, C2, and R1 are fixed and apply to all valid frequency ranges of CLKIN and CLKOUT.
B. For CLKMODE x1, the PLL is bypassed and all six external PLL components can be removed. For this case, the PLLV terminal has
to be connected to a clean supply and the PLLG and PLLF terminals should be tied together.
C. Due to overlap of frequency ranges when choosing the PLLFREQ, more than one frequency range can contain the CLKOUT1
frequency. Choose the lowest frequency range that includes the desired frequency. For example, for CLKOUT1 = 133 MHz, a
PLLFREQ value of 000b should be used for both the ’C6201 and the ’C6201B. For CLKOUT1 = 200 MHz, PLLFREQ should be set
to 010b for the ’C6201 or 001b for the ’C6201B. PLLFREQ values other than 000b, 001b, and 010b are reserved.
D. EMI filter manufacturer TDK part number ACF451832-153-T
E. For the ’C6201B, the 3.3-V supply for the EMI filter (and PLLV) must be from the same 3.3-V power plane supplying the I/O voltage,
DV
.
DD
Figure 6. PLL Block Diagram
25
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS320C6201, TMS320C6201B
DIGITAL SIGNAL PROCESSORS
SPRS051F – JANUARY 1997 – REVISED AUGUST 1999
clock PLL (continued)
Table 3. TMS320C6201 PLL Component Selection Table
TYPICAL
CYCLE TIME
(ns)
CLKIN
(MHz)
CLKOUT1
(MHz)
R1
(Ω)
C1
(µF)
C2
(pF)
CLKMODE
LOCK TIME
†
(µs)
59
49
68
70
72
84
77
67
68
65
68
5
5.5
6
x4
x4
x4
x4
x4
x4
x4
x4
x4
x4
x4
50
200
181.8
166.7
153.8
142.9
133.3
125
16.9
13.7
17.4
16.2
15
0.15
0.18
0.15
0.18
0.22
0.22
0.27
0.33
0.39
0.39
0.47
2700
3900
3300
3900
3900
3900
4700
6800
6800
8200
8200
45.5
41.6
38.5
35.7
33.3
31.3
29.4
27.7
26.3
25
6.5
7
7.5
8
16.2
14
8.5
9
117.7
111.1
105.3
100
11.8
11
9.5
10
10.5
10
†
Under some operating conditions, the maximum PLL lock time may vary as much as 150% from the specified typical value. For example, if the
typical lock time is specified as 100 µs, the maximum value may be as long as 250 µs.
Table 4. TMS320C6201B PLL Component Selection Table
CPU CLOCK
FREQUENCY
(CLKOUT1)
CLKIN
RANGE
(MHz)
CLKOUT2
RANGE
(MHz)
TYPICAL
R1
(Ω)
C1
(nF)
C2
(pF)
CLKMODE
LOCK TIME
†
(µs)
RANGE (MHz)
x4
12.5–50
50–200
25–100
60.4
27
560
75
†
Under some operating conditions, the maximum PLL lock time may vary as much as 150% from the specified typical value. For example, if the
typical lock time is specified as 100 µs, the maximum value may be as long as 250 µs.
power supply sequencing
For the ’C6201 device, the 2.5-V supply powers the core and the 3.3-V supply powers the I/O buffers. For the
’C6201B device, the 1.8-V supply powers the core and the 3.3-V supply powers the I/O buffers. The core supply
should be powered up first, or at the same time as the I/O buffers. This is to ensure that the I/O buffers have
valid inputs from the core before the output buffers are powered up, thus preventing bus contention with other
chips on the board.
26
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS320C6201, TMS320C6201B
DIGITAL SIGNAL PROCESSORS
SPRS051F – JANUARY 1997 – REVISED AUGUST 1999
†
absolute maximum ratings over operating case temperature range (unless otherwise noted)
Supply voltage range, CV
Supply voltage range, CV
Supply voltage range, DV
(see Note 1) for ’C6201 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 3 V
(see Note 1) for ’C6201B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 2.3 V
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 4 V
DD
DD
DD
Input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 4 V
Output voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 4 V
Operating case temperature range T : (default) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 C to 90 C
C
(A version) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40 C to 105 C
Storage temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55 C to 150 C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to V
SS
.
recommended operating conditions
’C6201
’C6201B
UNIT
MIN NOM
MAX
2.62
3.46
0
MIN NOM
MAX
1.89
3.46
0
CV
DV
Supply voltage
2.38
3.14
0
2.50
3.30
0
1.71
3.14
0
1.8
3.30
0
V
V
DD
DD
Supply voltage
V
V
V
Supply ground
V
SS
High-level input voltage
Low-level input voltage
High-level output current
Low-level output current
2.0
2.0
V
IH
IL
0.8
–12
12
0.8
–12
12
V
I
mA
mA
OH
OL
I
Default
0
90
0
90
T
C
Operating case temperature
C
A version
–40
105
27
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS320C6201, TMS320C6201B
DIGITAL SIGNAL PROCESSORS
SPRS051F – JANUARY 1997 – REVISED AUGUST 1999
electrical characteristics over recommended ranges of supply voltage and operating case
temperature (unless otherwise noted)
’C6201
TYP
’C6201B
TYP
PARAMETER
TEST CONDITIONS
UNIT
MIN
MAX
MIN
MAX
DV
= MIN,
= MAX
DD
V
V
High-level output voltage
Low-level output voltage
2.4
2.4
V
V
OH
I
OH
DV
= MIN,
= MAX
DD
0.6
0.6
OL
I
OL
V = V
†
I
I
Input current
to DV
±10
±10
±10
±10
uA
uA
I
I
SS
= DV
DD
or 0 V
Off-state output current
V
O
OZ
DD
= NOM,
Supply current, CPU + CPU memory
CV
DD
CPU clock = 167 MHz
I
I
I
1860
200
380
240
90
mA
mA
mA
DD2V
‡
access
CV = NOM,
DD
CPU clock = 167 MHz
§
Supply current, peripherals
DD2V
DD3V
DV = NOM,
DD
CPU clock = 167 MHz
¶
Supply current, I/O pins
100
C
C
Input capacitance
Output capacitance
10
10
10
10
pF
pF
i
o
†
TMS and TDI are not included due to internal pullups.
TRST is not included due to internal pulldown.
Measured with average CPU activity:
‡
50% of time:
50% of time:
Measured with average peripheral activity:
50% of time:
50% of time:
Measured with average I/O activity (30-pF load):
8 instructions per cycle, 32-bit DMEM access per cycle
2 instructions per cycle, 16-bit DMEM access per cycle
§
¶
Timers at max rate, McBSPs at E1 rate, and DMA burst transfer between DMEM and SDRAM
Timers at max rate, McBSPs at E1 rate, and DMA servicing McBSPs
25% of time:
25% of time:
50% of time:
Reads from external SDRAM
Writes to external SDRAM
No activity
28
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS320C6201, TMS320C6201B
DIGITAL SIGNAL PROCESSORS
SPRS051F – JANUARY 1997 – REVISED AUGUST 1999
PARAMETER MEASUREMENT INFORMATION
I
OL
Tester Pin
Electronics
Output
Under
Test
50 Ω
V
ref
†
= 30 pF
C
T
I
OH
†
Typical distributed load circuit capacitance
Figure 7. TTL-Level Outputs
signal transition levels
All input and output timing parameters are referenced to 1.5 V for both “0” and “1” logic levels.
V
ref
= 1.5 V
Figure 8. Input and Output Voltage Reference Levels for AC Timing Measurements
29
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS320C6201, TMS320C6201B
DIGITAL SIGNAL PROCESSORS
SPRS051F – JANUARY 1997 – REVISED AUGUST 1999
INPUT AND OUTPUT CLOCKS
†
timing requirements for CLKIN (see Figure 9) (’C6201)
’C6201-167
’C6201-200
CLKMODE
= x4
CLKMODE
= x1
CLKMODE
CLKMODE
= x1
NO.
UNIT
= x4
MIN MAX
MIN MAX
MIN MAX
MIN MAX
1
2
3
4
t
t
t
t
Cycle time, CLKIN
24
9.8
9.8
5
6
2.7
2.7
0.6
20
8
5
2.25
2.25
0.6
ns
ns
ns
ns
c(CLKIN)
w(CLKINH)
w(CLKINL)
t(CLKIN)
Pulse duration, CLKIN high
Pulse duration, CLKIN low
Transition time, CLKIN
8
5
†
The reference points for the rise and fall transitions are measured at 20% and 80%, respectively, of V
IH
.
timing requirements for CLKIN (see Figure 9) (’C6201B)
’C6201B-200
’C6201B-233
CLKMODE
= x4
CLKMODE
= x1
CLKMODE
= x4
CLKMODE
= x1
NO.
UNIT
MIN MAX
MIN MAX
MIN MAX
MIN MAX
1
2
3
4
t
t
t
t
Cycle time, CLKIN
20
8
5
2.25
2.25
0.6
17.2
6.9
6.9
5
4.3
1.9
1.9
0.6
ns
ns
ns
ns
c(CLKIN)
w(CLKINH)
w(CLKINL)
t(CLKIN)
Pulse duration, CLKIN high
Pulse duration, CLKIN low
Transition time, CLKIN
8
5
1
4
2
CLKIN
3
4
Figure 9. CLKIN Timings
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
30
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS320C6201, TMS320C6201B
DIGITAL SIGNAL PROCESSORS
SPRS051F – JANUARY 1997 – REVISED AUGUST 1999
INPUT AND OUTPUT CLOCKS (CONTINUED)
†‡
switching characteristics for CLKOUT1 (see Figure 10) (’C6201)
’C6201-167
’C6201-200
NO.
PARAMETER
UNIT
CLKMODE = x4
CLKMODE = x1
MIN
MAX
P + 0.7
MIN
MAX
1
2
3
4
t
t
t
t
Cycle time, CLKOUT1
P – 0.7
P – 0.7
PH – 0.5
PL – 0.5
P + 0.7
PH + 0.5
PL + 0.5
0.6
ns
ns
ns
ns
c(CKO1)
w(CKO1H)
w(CKO1L)
t(CKO1)
Pulse duration, CLKOUT1 high
Pulse duration, CLKOUT1 low
Transition time, CLKOUT1
(P/2) – 0.5 (P/2 )+ 0.5
(P/2) – 0.5 (P/2 )+ 0.5
0.6
†
‡
PH is the high period of CLKIN in ns and PL is the low period of CLKIN in ns.
P = 1/CPU clock frequency in nanoseconds (ns).
†‡
switching characteristics for CLKOUT1 (see Figure 10) (’C6201B)
’C6201B
NO.
PARAMETER
CLKMODE = x4
MIN MAX
P + 0.7
CLKMODE = x1
MIN MAX
UNIT
1
2
3
4
t
t
t
t
Cycle time, CLKOUT1
P – 0.7
(P/2) – 0.5
(P/2) – 0.5
P – 0.7
PH – 0.5
PL – 0.5
P + 0.7
PH + 0.5
PL + 0.5
0.6
ns
ns
ns
ns
c(CKO1)
w(CKO1H)
w(CKO1L)
t(CKO1)
Pulse duration, CLKOUT1 high
Pulse duration, CLKOUT1 low
Transition time, CLKOUT1
(P/2 ) + 0.5
(P/2 ) + 0.5
0.6
†
‡
PH is the high period of CLKIN in ns and PL is the low period of CLKIN in ns.
P = 1/CPU clock frequency in nanoseconds (ns).
1
4
2
CLKOUT1
3
4
Figure 10. CLKOUT1 Timings
31
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS320C6201, TMS320C6201B
DIGITAL SIGNAL PROCESSORS
SPRS051F – JANUARY 1997 – REVISED AUGUST 1999
INPUT AND OUTPUT CLOCKS (CONTINUED)
†
switching characteristics for CLKOUT2 (see Figure 11)
’C6201-167
’C6201-200
’C6201B
MIN
NO.
PARAMETER
UNIT
MIN
MAX
MAX
1
2
3
4
t
t
t
t
Cycle time, CLKOUT2
2P – 0.7
P – 0.7
P – 0.7
2P + 0.7
P + 0.7
P + 0.7
0.6
2P – 0.7
P – 0.7
P – 0.7
2P + 0.7
P + 0.7
P + 0.7
0.6
ns
ns
ns
ns
c(CKO2)
w(CKO2H)
w(CKO2L)
t(CKO2)
Pulse duration, CLKOUT2 high
Pulse duration, CLKOUT2 low
Transition time, CLKOUT2
†
P = 1/CPU clock frequency in ns.
1
4
2
CLKOUT2
3
4
Figure 11. CLKOUT2 Timings
SDCLK, SSCLK timing parameters
SDCLK timing parameters are the same as CLKOUT2 parameters.
SSCLK timing parameters are the same as CLKOUT1 or CLKOUT2 parameters, depending on SSCLK
configuration.
switching characteristics for the relation of SSCLK, SDCLK, and CLKOUT2 to CLKOUT1
†
(see Figure 12)
’C6201-167
’C6201B
’C6201-200
NO.
PARAMETER
UNIT
MIN
MAX
MIN
MAX
1
2
t
t
Delay time, CLKOUT1 edge to SSCLK edge
–1.2
1.6 (P/2) + 0.2 (P/2) + 4.2
ns
ns
d(CKO1-SSCLK)
Delay time, CLKOUT1 edge to SSCLK edge
(1/2 clock rate)
–1.0
2.4
(P/2) – 1 (P/2) + 2.4
d(CKO1-SSCLK1/2)
3
4
t
t
Delay time, CLKOUT1 edge to CLKOUT2 edge
Delay time, CLKOUT1 edge to SDCLK edge
–1.0
–1.0
2.4
2.4
(P/2) – 1 (P/2) + 2.4
(P/2) – 1 (P/2) + 2.4
ns
ns
d(CKO1-CKO2)
d(CKO1-SDCLK)
†
P = 1/CPU clock frequency in ns.
32
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS320C6201, TMS320C6201B
DIGITAL SIGNAL PROCESSORS
SPRS051F – JANUARY 1997 – REVISED AUGUST 1999
INPUT AND OUTPUT CLOCKS (CONTINUED)
CLKOUT1
SSCLK
1
2
3
4
SSCLK (1/2rate)
CLKOUT2
SDCLK
Figure 12. Relation of CLKOUT2, SDCLK, and SSCLK to CLKOUT1
33
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS320C6201, TMS320C6201B
DIGITAL SIGNAL PROCESSORS
SPRS051F – JANUARY 1997 – REVISED AUGUST 1999
ASYNCHRONOUS MEMORY TIMING
†
timing requirements for asynchronous memory cycles (see Figure 13 and Figure 14)
’C6201-167
’C6201B
’C6201-200
NO.
UNIT
MIN MAX
MIN MAX
6
7
t
t
t
t
Setup time, read EDx valid before CLKOUT1 high
Hold time, read EDx valid after CLKOUT1 high
Setup time, ARDY valid before CLKOUT1 high
Hold time, ARDY valid after CLKOUT1 high
5.0
0
4.0
0.8
3.0
1.8
ns
ns
ns
ns
su(EDV-CKO1H)
h(CKO1H-EDV)
su(ARDY-CKO1H)
h(CKO1H-ARDY)
10
11
5.0
0
†
To ensure data setup time, simply program the strobe width wide enough. ARDY is internally synchronized. If ARDY does meet setup or hold
time, it may be recognized in the current cycle or the next cycle. Thus, ARDY can be an asynchronous input.
‡
switching characteristics for asynchronous memory cycles (see Figure 13 and Figure 14)
’C6201-167
’C6201B
’C6201-200
NO.
PARAMETER
UNIT
MIN
MAX
5.0
MIN
MAX
4.0
1
2
t
t
t
t
t
t
t
t
t
t
Delay time, CLKOUT1 high to CEx valid
Delay time, CLKOUT1 high to BEx valid
Delay time, CLKOUT1 high to BEx invalid
Delay time, CLKOUT1 high to EAx valid
Delay time, CLKOUT1 high to EAx invalid
Delay time, CLKOUT1 high to AOE valid
Delay time, CLKOUT1 high to ARE valid
Delay time, CLKOUT1 high to EDx valid
Delay time, CLKOUT1 high to EDx invalid
Delay time, CLKOUT1 high to AWE valid
–1.0
–0.2
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
d(CKO1H-CEV)
d(CKO1H-BEV)
d(CKO1H-BEIV)
d(CKO1H-EAV)
d(CKO1H-EAIV)
d(CKO1H-AOEV)
d(CKO1H-AREV)
d(CKO1H-EDV)
d(CKO1H-EDIV)
d(CKO1H-AWEV)
5.0
4.0
3
–1.0
–0.2
4
5.0
4.0
5
–1.0
–1.0
–1.0
–0.2
–0.2
–0.2
8
5.0
5.0
5.0
4.0
4.0
4.0
9
12
13
14
–1.0
–1.0
–0.2
–0.2
5.0
4.0
‡
The minimum delay is also the minimum output hold after CLKOUT1 high.
34
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS320C6201, TMS320C6201B
DIGITAL SIGNAL PROCESSORS
SPRS051F – JANUARY 1997 – REVISED AUGUST 1999
ASYNCHRONOUS MEMORY TIMING (CONTINUED)
Not ready = 2
Setup = 2
Strobe = 5
HOLD = 1
CLKOUT1
CEx
1
2
4
1
3
BE[3:0]
EA[21:2]
ED[31:0]
AOE
5
7
6
8
8
9
9
ARE
AWE
11
11
10
10
ARDY
Figure 13. Asynchronous Memory Read Timing
Not ready = 2
Setup = 2
Strobe = 5
HOLD = 1
CLKOUT1
1
2
4
1
3
5
CEx
BE[3:0]
EA[21:2]
12
13
14
ED[31:0]
AOE
ARE
14
AWE
11
11
10
10
ARDY
Figure 14. Asynchronous Memory Write Timing
35
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS320C6201, TMS320C6201B
DIGITAL SIGNAL PROCESSORS
SPRS051F – JANUARY 1997 – REVISED AUGUST 1999
SYNCHRONOUS-BURST MEMORY TIMING
timing requirements for synchronous-burst SRAM cycles (full-rate SSCLK) (see Figure 15)
’C6201-167
’C6201B
’C6201-200
NO.
UNIT
MIN
1.5
MAX
MIN
1.5
MAX
7
8
t
t
Setup time, read EDx valid before SSCLK high
Hold time, read EDx valid after SSCLK high
ns
ns
su(EDV-SSCLKH)
1.2
1.5
h(SSCLKH-EDV)
†
switching characteristics for synchronous-burst SRAM cycles (full-rate SSCLK)
(see Figure 15 and Figure 16)
’C6201-167
’C6201-200
’C6201B
NO.
PARAMETER
UNIT
MIN
P – 4
0
MAX
MIN
0.5P – 1.3
0.5P – 2.3
0.5P – 1.3
0.5P – 2.3
0.5P – 1.3
0.5P – 2.3
0.5P – 1.3
0.5P – 2.3
0.5P – 1.3
0.5P – 2.3
0.5P – 1.3
0.5P – 2.3
0.5P – 1.3
0.5P – 2.3
MAX
1
2
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Output setup time, CEx valid before SSCLK high
Output hold time, CEx valid after SSCLK high
Output setup time, BEx valid before SSCLK high
Output hold time, BEx invalid after SSCLK high
Output setup time, EAx valid before SSCLK high
Output hold time, EAx invalid after SSCLK high
Output setup time, SSADS valid before SSCLK high
Output hold time, SSADS valid after SSCLK high
Output setup time, SSOE valid before SSCLK high
Output hold time, SSOE valid after SSCLK high
Output setup time, EDx valid before SSCLK high
Output hold time, EDx invalid after SSCLK high
Output setup time, SSWE valid before SSCLK high
Output hold time, SSWE valid after SSCLK high
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
osu(CEV-SSCLKH)
oh(SSCLKH-CEV)
osu(BEV-SSCLKH)
oh(SSCLKH-BEIV)
osu(EAV-SSCLKH)
oh(SSCLKH-EAIV)
osu(ADSV-SSCLKH)
oh(SSCLKH-ADSV)
osu(OEV-SSCLKH)
oh(SSCLKH-OEV)
osu(EDV-SSCLKH)
oh(SSCLKH-EDIV)
osu(WEV-SSCLKH)
oh(SSCLKH-WEV)
3
P – 4
1
4
5
P – 4
1
6
9
P – 3
0
10
11
12
13
14
15
16
P – 4
0
P – 4
1
P – 3
0
†
When the PLL is used (CLKMODE x4), P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
For CLKMODE x1, 0.5P is defined as PH (pulse duration of CLKIN high) for all output setup times; 0.5P is defined as PL (pulse duration of CLKIN
low) for all output hold times.
36
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS320C6201, TMS320C6201B
DIGITAL SIGNAL PROCESSORS
SPRS051F – JANUARY 1997 – REVISED AUGUST 1999
SYNCHRONOUS-BURST MEMORY TIMING (CONTINUED)
SSCLK
CEx
1
3
5
2
4
BE[3:0]
BE1
A1
BE2
BE3
BE4
6
EA[21:2]
A2
7
A3
8
A4
Q1
Q2
Q3
Q4
ED[31:0]
SSADS
9
10
11
12
SSOE
SSWE
Figure 15. SBSRAM Read Timing (Full-Rate SSCLK)
SSCLK
CEx
1
3
2
4
BE[3:0]
BE1
A1
BE2
A2
BE3
A3
BE4
5
6
EA[21:2]
ED[31:0]
A4
13
14
D4
D1
D2
D3
9
10
SSADS
SSOE
15
16
SSWE
Figure 16. SBSRAM Write Timing (Full-Rate SSCLK)
37
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS320C6201, TMS320C6201B
DIGITAL SIGNAL PROCESSORS
SPRS051F – JANUARY 1997 – REVISED AUGUST 1999
SYNCHRONOUS-BURST MEMORY TIMING (CONTINUED)
timing requirements for synchronous-burst SRAM cycles (half-rate SSCLK)
(see Figure 17) (’C6201)
’C6201-167
’C6201-200
NO.
UNIT
MIN
3.6
MAX
MIN
3.6
MAX
7
8
t
t
Setup time, read EDx valid before SSCLK high
Hold time, read EDx valid after SSCLK high
ns
ns
su(EDV-SSCLKH)
1.2
1.2
h(SSCLKH-EDV)
†
switching characteristics for synchronous-burst SRAM cycles (half-rate SSCLK)
(see Figure 17 and Figure 18) (’C6201)
’C6201-167
’C6201-200
NO.
PARAMETER
UNIT
MIN
P – 3.4
P – 5
MAX
MIN
P – 3.4
P – 4
MAX
1
2
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Output setup time, CEx valid before SSCLK high
Output hold time, CEx valid after SSCLK high
Output setup time, BEx valid before SSCLK high
Output hold time, BEx invalid after SSCLK high
Output setup time, EAx valid before SSCLK high
Output hold time, EAx invalid after SSCLK high
Output setup time, SSADS valid before SSCLK high
Output hold time, SSADS valid after SSCLK high
Output setup time, SSOE valid before SSCLK high
Output hold time, SSOE valid after SSCLK high
Output setup time, EDx valid before SSCLK high
Output hold time, EDx invalid after SSCLK high
Output setup time, SSWE valid before SSCLK high
Output hold time, SSWE valid after SSCLK high
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
osu(CEV-SSCLKH)
oh(SSCLKH-CEV)
osu(BEV-SSCLKH)
oh(SSCLKH-BEIV)
osu(EAV-SSCLKH)
oh(SSCLKH-EAIV)
osu(ADSV-SSCLKH)
oh(SSCLKH-ADSV)
osu(OEV-SSCLKH)
oh(SSCLKH-OEV)
osu(EDV-SSCLKH)
oh(SSCLKH-EDIV)
osu(WEV-SSCLKH)
oh(SSCLKH-WEV)
3
P – 3.3
P – 5
P – 2.3
P – 4
4
5
P – 3.3
P – 5
P – 2.3
P – 4
6
9
P – 3.3
P – 5
P – 2.3
P – 4
10
11
12
13
14
15
16
P – 3.3
P – 5
P – 3.1
P – 4
P – 3.3
P – 5
P – 2.3
P – 4
P – 3.3
P – 5
P – 2.3
P – 4
†
P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
38
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS320C6201, TMS320C6201B
DIGITAL SIGNAL PROCESSORS
SPRS051F – JANUARY 1997 – REVISED AUGUST 1999
SYNCHRONOUS-BURST MEMORY TIMING (CONTINUED)
timing requirements for synchronous-burst SRAM cycles (half-rate SSCLK)
(see Figure 17) (’C6201B)
’C6201B-200
’C6201B-233
NO.
UNIT
MIN
2.5
MAX
MIN
1.1
MAX
7
8
t
t
Setup time, read EDx valid before SSCLK high
Hold time, read EDx valid after SSCLK high
ns
ns
su(EDV-SSCLKH)
1.5
1.5
h(SSCLKH-EDV)
†
switching characteristics for synchronous-burst SRAM cycles (half-rate SSCLK)
(see Figure 17 and Figure 18) (’C6201B)
’C6201B-200
’C6201B-233
NO.
PARAMETER
UNIT
MIN
MAX
MIN
MAX
1
2
3
4
5
6
t
t
t
t
t
t
Output setup time, CEx valid before SSCLK high
Output hold time, CEx valid after SSCLK high
Output setup time, BEx valid before SSCLK high
Output hold time, BEx invalid after SSCLK high
Output setup time, EAx valid before SSCLK high
Output hold time, EAx invalid after SSCLK high
1.5P – 3
0.5P – 1.5
1.5P – 3
0.5P – 1.5
1.5P – 3
0.5P – 1.5
1.5P – 2.2
0.5P – 1.1
1.5P – 2.2
0.5P – 1.1
1.5P – 2.2
0.5P – 1.1
ns
ns
ns
ns
ns
ns
osu(CEV-SSCLKH)
oh(SSCLKH-CEV)
osu(BEV-SSCLKH)
oh(SSCLKH-BEIV)
osu(EAV-SSCLKH)
oh(SSCLKH-EAIV)
Output setup time, SSADS valid before SSCLK
high
9
t
t
t
1.5P – 3
0.5P – 1.5
1.5P – 3
1.5P – 2.2
0.5P – 1.1
1.5P – 2.2
ns
ns
ns
osu(ADSV-SSCLKH)
oh(SSCLKH-ADSV)
osu(OEV-SSCLKH)
10
11
Output hold time, SSADS valid after SSCLK high
Output setup time, SSOE valid before SSCLK
high
12
13
14
t
t
t
Output hold time, SSOE valid after SSCLK high
Output setup time, EDx valid before SSCLK high
Output hold time, EDx invalid after SSCLK high
0.5P – 1.5
1.5P – 3
0.5P – 1.1
1.5P – 2.2
0.5P – 1.1
ns
ns
ns
oh(SSCLKH-OEV)
osu(EDV-SSCLKH)
oh(SSCLKH-EDIV)
0.5P – 1.5
Output setup time, SSWE valid before SSCLK
high
15
t
1.5P – 3
1.5P – 2.2
ns
ns
osu(WEV-SSCLKH)
16
t
Output hold time, SSWE valid after SSCLK high
0.5P – 1.5
0.5P – 1.1
oh(SSCLKH-WEV)
†
When the PLL is used (CLKMODE x4), P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
For CLKMODE x1:
1.5P = P + PH, where P = 1/CPU clock frequency, and PH = pulse duration of CLKIN high.
0.5P = PL, where PL = pulse duration of CLKIN low.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
39
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS320C6201, TMS320C6201B
DIGITAL SIGNAL PROCESSORS
SPRS051F – JANUARY 1997 – REVISED AUGUST 1999
SYNCHRONOUS-BURST MEMORY TIMING (CONTINUED)
SSCLK
1
2
CEx
3
4
6
BE[3:0]
BE1
BE2
A2
BE3
A3
BE4
5
A1
A4
8
EA[21:2]
7
Q1
Q2
Q3
10
Q4
ED[31:0]
SSADS
9
11
12
SSOE
SSWE
Figure 17. SBSRAM Read Timing (1/2 Rate SSCLK)
SSCLK
1
3
2
CEx
BE[3:0]
4
6
BE1
BE2
A2
BE3
A3
BE4
5
EA[21:2]
A1
A4
Q4
13
14
10
Q1
Q2
Q3
ED[31:0]
9
SSADS
SSOE
15
16
SSWE
Figure 18. SBSRAM Write Timing (1/2 Rate SSCLK)
40
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS320C6201, TMS320C6201B
DIGITAL SIGNAL PROCESSORS
SPRS051F – JANUARY 1997 – REVISED AUGUST 1999
SYNCHRONOUS DRAM TIMING
timing requirements for synchronous DRAM cycles (see Figure 19) (’C6201)
’C6201-167
’C6201-200
MIN MAX
1.5
NO.
UNIT
MIN MAX
7
8
t
t
Setup time, read EDx valid before SDCLK high
Hold time, read EDx valid after SDCLK high
3.5
1.2
ns
ns
su(EDV-SDCLKH)
1.2
h(SDCLKH-EDV)
†
switching characteristics for synchronous DRAM cycles (see Figure 19–Figure 24) (’C6201)
’C6201-167
MAX
’C6201-200
MAX
NO.
PARAMETER
UNIT
MIN
P – 3.5
P – 4.5
P – 3.5
P – 4.5
P – 3.5
P – 4.5
P – 3.5
P – 4.5
P – 3.5
P – 4.5
P – 3.5
P – 4.5
P – 3.5
P – 4.5
P – 3.5
P – 4.5
MIN
P – 2.5
P – 3.5
P – 2.5
P – 3.5
P – 2.5
P – 3.5
P – 2.5
P – 3.5
P – 2.5
P – 3.5
P – 2.5
P – 3.5
P – 2.5
P – 3.5
P – 2.5
P – 3.5
1
2
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Output setup time, CEx valid before SDCLK high
Output hold time, CEx valid after SDCLK high
Output setup time, BEx valid before SDCLK high
Output hold time, BEx invalid after SDCLK high
Output setup time, EAx valid before SDCLK high
Output hold time, EAx invalid after SDCLK high
Output setup time, SDCAS valid before SDCLK high
Output hold time, SDCAS valid after SDCLK high
Output setup time, EDx valid before SDCLK high
Output hold time, EDx invalid after SDCLK high
Output setup time, SDWE valid before SDCLK high
Output hold time, SDWE valid after SDCLK high
Output setup time, SDA10 valid before SDCLK high
Output hold time, SDA10 invalid after SDCLK high
Output setup time, SDRAS valid before SDCLK high
Output hold time, SDRAS valid after SDCLK high
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
osu(CEV-SDCLKH)
oh(SDCLKH-CEV)
3
osu(BEV-SDCLKH)
oh(SDCLKH-BEIV)
osu(EAV-SDCLKH)
oh(SDCLKH-EAIV)
osu(SDCAS-SDCLKH)
oh(SDCLKH-SDCAS)
osu(EDV-SDCLKH)
oh(SDCLKH-EDIV)
osu(SDWE-SDCLKH)
oh(SDCLKH-SDWE)
osu(SDA10V-SDCLKH)
oh(SDCLKH-SDA10IV)
osu(SDRAS-SDCLKH)
oh(SDCLKH-SDRAS)
4
5
6
9
10
11
12
13
14
15
16
17
18
†
P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
41
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS320C6201, TMS320C6201B
DIGITAL SIGNAL PROCESSORS
SPRS051F – JANUARY 1997 – REVISED AUGUST 1999
SYNCHRONOUS DRAM TIMING (CONTINUED)
timing requirements for synchronous DRAM cycles (see Figure 19) (’C6201B)
’C6201B-200
’C6201B-233
NO.
UNIT
MIN MAX
MIN MAX
7
8
t
t
Setup time, read EDx valid before SDCLK high
Hold time, read EDx valid after SDCLK high
0.5
3
0.5
3
ns
ns
su(EDV-SDCLKH)
h(SDCLKH-EDV)
†
switching characteristics for synchronous DRAM cycles (see Figure 19–Figure 24) (’C6201B)
’C6201B-200
’C6201B-233
NO.
PARAMETER
UNIT
MIN
MAX
MIN
MAX
1
2
3
4
5
6
t
t
t
t
t
t
Output setup time, CEx valid before SDCLK high
Output hold time, CEx valid after SDCLK high
Output setup time, BEx valid before SDCLK high
Output hold time, BEx invalid after SDCLK high
Output setup time, EAx valid before SDCLK high
Output hold time, EAx invalid after SDCLK high
1.5P – 3.5
0.5P – 1
1.5P – 3.5
0.5P – 1
1.5P – 3.5
0.5P – 1
1.5P – 2.4
0.5P – 0.6
1.5P – 2.4
0.5P – 0.6
1.5P – 2.4
0.5P – 0.6
ns
ns
ns
ns
ns
ns
osu(CEV-SDCLKH)
oh(SDCLKH-CEV)
osu(BEV-SDCLKH)
oh(SDCLKH-BEIV)
osu(EAV-SDCLKH)
oh(SDCLKH-EAIV)
Output setup time, SDCAS valid before SDCLK
high
9
t
1.5P – 3.5
1.5P – 2.4
ns
osu(SDCAS-SDCLKH)
10
11
12
t
t
t
Output hold time, SDCAS valid after SDCLK high
Output setup time, EDx valid before SDCLK high
Output hold time, EDx invalid after SDCLK high
0.5P – 1
1.5P – 3.5
0.5P – 1
0.5P – 0.6
1.5P – 2.4
0.5P – 0.6
ns
ns
ns
oh(SDCLKH-SDCAS)
osu(EDV-SDCLKH)
oh(SDCLKH-EDIV)
Output setup time, SDWE valid before SDCLK
high
13
14
15
t
t
t
1.5P – 3.5
0.5P – 1
1.5P – 2.4
0.5P – 0.6
1.5P – 2.4
ns
ns
ns
osu(SDWE-SDCLKH)
oh(SDCLKH-SDWE)
osu(SDA10V-SDCLKH)
Output hold time, SDWE valid after SDCLK high
Output setup time, SDA10 valid before SDCLK
high
1.5P – 3.5
Output hold time, SDA10 invalid after SDCLK
high
16
t
0.5P – 1
0.5P – 0.6
ns
oh(SDCLKH-SDA10IV)
Output setup time, SDRAS valid before SDCLK
high
17
18
t
t
1.5P – 3.5
0.5P – 1
1.5P – 2.4
0.5P – 0.6
ns
ns
osu(SDRAS-SDCLKH)
Output hold time, SDRAS valid after SDCLK high
oh(SDCLKH-SDRAS)
†
When the PLL is used (CLKMODE x4), P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
For CLKMODE x1:
1.5P = P + PH, where P = 1/CPU clock frequency, and PH = pulse duration of CLKIN high.
0.5P = PL, where PL = pulse duration of CLKIN low.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
42
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS320C6201, TMS320C6201B
DIGITAL SIGNAL PROCESSORS
SPRS051F – JANUARY 1997 – REVISED AUGUST 1999
SYNCHRONOUS DRAM TIMING (CONTINUED)
READ
READ
READ
SDCLK
CEx
1
5
2
3
4
BE[3:0]
EA[15:2]
BE1
BE2
CA3
BE3
7
6
CA1
CA2
8
D1
D2
D3
ED[31:0]
15
9
16
10
SDA10
SDRAS
SDCAS
SDWE
Figure 19. Three SDRAM Read Commands
WRITE
WRITE
WRITE
SDCLK
CEx
1
2
3
4
BE[3:0]
BE1
CA1
BE2
CA2
D2
BE3
5
6
EA[15:2]
CA3
D3
11
12
D1
ED[31:0]
SDA10
15
16
SDRAS
SDCAS
9
10
14
13
SDWE
Figure 20. Three SDRAM WRT Commands
43
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS320C6201, TMS320C6201B
DIGITAL SIGNAL PROCESSORS
SPRS051F – JANUARY 1997 – REVISED AUGUST 1999
SYNCHRONOUS DRAM TIMING (CONTINUED)
ACTV
SDCLK
1
5
2
CEx
BE[3:0]
Bank Activate/Row Address
EA[15:2]
ED[31:0]
15
Row Address
SDA10
17
18
SDRAS
SDCAS
SDWE
Figure 21. SDRAM ACTV Command
DCAB
SDCLK
1
2
CEx
BE[3:0]
EA[15:2]
ED[31:0]
15
17
16
18
SDA10
SDRAS
SDCAS
13
14
SDWE
Figure 22. SDRAM DCAB Command
44
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS320C6201, TMS320C6201B
DIGITAL SIGNAL PROCESSORS
SPRS051F – JANUARY 1997 – REVISED AUGUST 1999
SYNCHRONOUS DRAM TIMING (CONTINUED)
REFR
SDCLK
CEx
1
2
BE[3:0]
EA[15:2]
ED[31:0]
SDA10
SDRAS
17
9
18
10
SDCAS
SDWE
Figure 23. SDRAM REFR Command
MRS
SDCLK
1
2
6
CEx
BE[3:0]
5
EA[15:2]
ED[31:0]
SDA10
MRS Value
17
18
SDRAS
9
10
14
SDCAS
SDWE
13
Figure 24. SDRAM MRS Command
45
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS320C6201, TMS320C6201B
DIGITAL SIGNAL PROCESSORS
SPRS051F – JANUARY 1997 – REVISED AUGUST 1999
HOLD/HOLDA TIMING
†
timing requirements for the HOLD/HOLDA cycles (see Figure 25)
’C6201-167
’C6201-200
’C6201B
NO.
UNIT
MIN MAX
MIN MAX
1
2
t
t
Setup time, HOLD high before CLKOUT1 high
Hold time, HOLD low after CLKOUT1 high
5
2
1
4
ns
ns
su(HOLDH-CKO1H)
h(CKO1H-HOLDL)
†
HOLD is synchronized internally. Therefore, if setup and hold times are not met, it will either be recognized in the current cycle or in the next cycle.
Thus, HOLD can be an asynchronous input.
‡
switching characteristics for the HOLD/HOLDA cycles (see Figure 25)
’C6201-167
’C6201-200
’C6201B
NO.
PARAMETER
UNIT
MIN
4P
P
MAX
MIN
4P
P
MAX
§
§
3
4
5
6
7
8
9
t
t
t
t
t
t
t
Response time, HOLD low to EMIF Bus high impedance
Response time, EMIF Bus high impedance to HOLDA low
Response time, HOLD high to HOLDA high
ns
ns
ns
ns
ns
ns
ns
R(HOLDL-BHZ)
R(BHZ-HOLDAL)
R(HOLDH-HOLDAH)
d(CKO1H-HOLDAL)
d(CKO1H-BHZ)
2P
6P
5
2P
7P
8
4P
–1
–1
–1
3P
4P
1
Delay time, CLKOUT1 high to HOLDA valid
¶
Delay time, CLKOUT1 high to EMIF Bus high impedance
5
3
11
11
6P
¶
Delay time, CLKOUT1 high to EMIF Bus low impedance
Response time, HOLD high to EMIF Bus low impedance
5
3
d(CKO1H-BLZ)
5P
3P
R(HOLDH-BLZ)
‡
§
P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
All pending EMIF transactions are allowed to complete before HOLDA is asserted. The worst cases for this is an asynchronous read or write
with external ARDY used or a minimum of eight consecutive SDRAM reads or writes when RBTR8 = 1. If no bus transactions are occurring, then
the minimum delay time can be achieved. Also, bus hold can be indefinitely delayed by setting NOHOLD = 1.
¶
EMIF Bus consists of CE[3:0], BE[3:0], ED[31:0], EA[21:2], ARE, AOE, AWE, SSADS, SSOE, SSWE, SDA10, SDRAS, SDCAS, and SDWE.
DSP Owns Bus
External Requester
DSP Owns Bus
5
4
9
2
3
CLKOUT1
HOLD
2
1
1
6
6
HOLDA
7
8
†
EMIF Bus
’C62x
Ext Req
’C62x
†
EMIF Bus consists of CE[3:0], BE[3:0], ED[31:0], EA[21:2], ARE, AOE, AWE, SSADS, SSOE, SSWE, SDA10, SDRAS, SDCAS, and SDWE.
Figure 25. HOLD/HOLDA Timing
46
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS320C6201, TMS320C6201B
DIGITAL SIGNAL PROCESSORS
SPRS051F – JANUARY 1997 – REVISED AUGUST 1999
RESET TIMING
timing requirements for reset (see Figure 26)
’C6201-167
’C6201B
’C6201-200
UNIT
NO.
MIN
MAX
MIN
MAX
CLKOUT1
cycles
†
Width of the RESET pulse (PLL stable)
10
10
1
t
w(RST)
‡
Width of the RESET pulse (PLL needs to sync up)
250
250
µs
†
‡
This parameter applies to CLKMODE x1 when CLKIN is stable and applies to CLKMODE x4 when CLKIN and PLL are stable.
This parameter only applies to CLKMODE x4. The RESET signal is not connected internally to the clock PLL circuit. The PLL, however, may
need up to 250 µs to stabilize following device power up or after PLL configuration has been changed. During that time, RESET must be asserted
to ensure proper device operation. See the clock PLL section for PLL lock times.
§¶
switching characteristics during reset (see Figure 26)
’C6201-167
’C6201-200
’C6201B
NO.
PARAMETER
UNIT
MIN
2
MAX
MIN
2
MAX
CLKOUT1
cycles
2
t
Response time to change of value in RESET signal
R(RST)
3
4
t
t
t
t
t
t
t
t
t
t
t
t
Delay time, CLKOUT1 high to CLKOUT2 invalid
Delay time, CLKOUT1 high to CLKOUT2 valid
Delay time, CLKOUT1 high to SDCLK invalid
Delay time, CLKOUT1 high to SDCLK valid
Delay time, CLKOUT1 high to SSCLK invalid
Delay time, CLKOUT1 high to SSCLK valid
Delay time, CLKOUT1 high to low group invalid
Delay time, CLKOUT1 high to low group valid
Delay time, CLKOUT1 high to high group invalid
Delay time, CLKOUT1 high to high group valid
Delay time, CLKOUT1 high to Z group high impedance
Delay time, CLKOUT1 high to Z group valid
–1
–1
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
d(CKO1H-CKO2IV)
d(CKO1H-CKO2V)
d(CKO1H-SDCLKIV)
d(CKO1H-SDCLKV)
d(CKO1H-SSCKIV)
d(CKO1H-SSCKV)
d(CKO1H-LOWIV)
d(CKO1H-LOWV)
d(CKO1H-HIGHIV)
d(CKO1H-HIGHV)
d(CKO1H-ZHZ)
10
10
10
10
10
10
10
10
10
10
10
10
5
–1
–1
–1
–1
–1
–1
–1
–1
–1
–1
6
7
8
9
10
11
12
13
14
d(CKO1H-ZV)
§
¶
Low group consists of:
High group consists of:
Z group consists of:
IACK, INUM[3:0], DMAC[3:0], PD, TOUT0, and TOUT1
HINT
EA[21:2], ED[31:0], CE[3:0], BE[3:0], ARE, AWE, AOE, SSADS, SSOE, SSWE, SDA10, SDRAS, SDCAS,
SDWE, HD[15:0], CLKX0, CLKX1, FSX0, FSX1, DX0, DX1, CLKR0, CLKR1, FSR0, and FSR1.
HRDY is gated by input HCS.
If HCS = 0 at device reset, HRDY belongs to the high group.
If HCS = 1 at device reset, HRDY belongs to the low group.
47
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS320C6201, TMS320C6201B
DIGITAL SIGNAL PROCESSORS
SPRS051F – JANUARY 1997 – REVISED AUGUST 1999
RESET TIMING (CONTINUED)
CLKOUT1
1
2
2
RESET
3
4
6
CLKOUT2
5
SDCLK
7
8
SSCLK
9
10
12
14
†‡
LOW GROUP
HIGH GROUP
Z GROUP
11
13
†‡
†‡
†
‡
Low group consists of:
High group consists of:
Z group consists of:
IACK, INUM[3:0], DMAC[3:0], PD, TOUT0, and TOUT1
HINT
EA[21:2], ED[31:0], CE[3:0], BE[3:0], ARE, AWE, AOE, SSADS, SSOE, SSWE, SDA10, SDRAS, SDCAS,
SDWE, HD[15:0], CLKX0, CLKX1, FSX0, FSX1, DX0, DX1, CLKR0, CLKR1, FSR0, and FSR1.
HRDY is gated by input HCS.
If HCS = 0 at device reset, HRDY belongs to the high group.
If HCS = 1 at device reset, HRDY belongs to the low group.
Figure 26. Reset Timing
48
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS320C6201, TMS320C6201B
DIGITAL SIGNAL PROCESSORS
SPRS051F – JANUARY 1997 – REVISED AUGUST 1999
EXTERNAL INTERRUPT TIMING
†‡
timing requirements for interrupt response cycles (see Figure 27)
’C6201-167
’C6201-200
’C6201B
NO.
UNIT
MIN
2P
MAX
MIN
2P
MAX
2
3
t
t
Width of the interrupt pulse low
Width of the interrupt pulse high
ns
ns
w(ILOW)
2P
2P
w(IHIGH)
†
‡
Interrupt signals are synchronized internally and are potentially recognized one cycle later if setup and hold times are violated. Thus, they can
be connected to asynchronous inputs.
P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
§
switching characteristics during interrupt response cycles (see Figure 27)
’C6201-167
’C6201-200
’C6201B
NO.
PARAMETER
UNIT
MIN
9P
0
MAX
MIN
MAX
1
4
5
6
t
t
t
t
Response time, EXT_INTx high to IACK high
Delay time, CLKOUT2 low to IACK valid
Delay time, CLKOUT2 low to INUMx valid
Delay time, CLKOUT2 low to INUMx invalid
9P
ns
ns
ns
ns
R(EINTH-IACKH)
d(CKO2L-IACKV)
d(CKO2L-INUMV)
d(CKO2L-INUMIV)
10 –4 – 0.5P 6 – 0.5P
10
6 – 0.5P
0
–4 – 0.5P
§
P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
When the PLL is used (CLKMODE x4), 0.5P = 1/(2 × CPU clock frequency).
For CLKMODE x1: 0.5P = PH, where PH is the high period of CLKIN.
1
CLKOUT2
3
2
EXT_INTx, NMI
Intr Flag
4
4
IACK
6
5
INUMx
Interrupt Number
Figure 27. Interrupt Timing
49
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS320C6201, TMS320C6201B
DIGITAL SIGNAL PROCESSORS
SPRS051F – JANUARY 1997 – REVISED AUGUST 1999
HOST-PORT INTERFACE TIMING
†‡
timing requirements for host-port interface cycles (see Figure 28, Figure 29, Figure 30, and
Figure 31)
’C6201-167
’C6201B
’C6201-200
NO.
UNIT
MIN
1
MAX
MIN
4
MAX
§
1
2
t
t
t
t
t
t
t
t
Setup time, select signals valid before HSTROBE low
ns
ns
ns
ns
ns
ns
ns
ns
su(SEL-HSTBL)
h(HSTBL-SEL)
w(HSTBL)
§
Hold time, select signals valid after HSTROBE low
2
2
3
Pulse duration, HSTROBE low
2P
2P
1
2P
2P
4
4
Pulse duration, HSTROBE high between consecutive accesses
w(HSTBH)
§
Setup time, select signals valid before HAS low
10
11
12
13
su(SEL-HASL)
h(HASL-SEL)
su(HDV-HSTBH)
h(HSTBH-HDV)
§
Hold time, select signals valid after HAS low
2
2
Setup time, host data valid before HSTROBE high
Hold time, host data valid after HSTROBE high
1
3
1
2
Hold time, HSTROBE low after HRDY low. HSTROBE shoul
not be inactivated until HRDY is active (low); otherwise, HPI
writes will not complete properly.
14
t
1
1
ns
h(HRDYL-HSTBL)
18
19
t
t
Setup time, HAS low before HSTROBE low
Hold time, HAS low after HSTROBE low
2
2
2
2
ns
ns
su(HASL-HSTBL)
h(HSTBL-HASL)
†
‡
HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
The effects of internal clock jitter are included at test. There is no need to adjust timing numbers for internal clock jitter. P = 1/CPU clock frequency
in ns. For example, when running parts at 200 MHz, use P = 5 ns.
§
Select signals include: HCNTRL[1:0], HR/W, and HHWIL.
†‡
switching characteristics during host-port interface cycles (see Figure 28, Figure 29, Figure 30,
and Figure 31)
’C6201-167
’C6201B
’C6201-200
NO.
PARAMETER
UNIT
MIN MAX
MIN MAX
¶
5
6
t
t
Delay time, HCS to HRDY
1
3
7
1
3
9
ns
ns
d(HCS-HRDY)
#
Delay time, HSTROBE low to HRDY high
12
12
d(HSTBL-HRDYH)
Output hold time, HD low impedance after HSTROBE low
for an HPI read
7
t
4
4
ns
oh(HSTBL-HDLZ)
8
9
t
t
t
t
Delay time, HD valid to HRDY low
P – 2
P
P – 3 P + 3
ns
ns
ns
ns
d(HDV-HRDYL)
oh(HSTBH-HDV)
d(HSTBH-HDHZ)
d(HSTBL-HDV)
Output hold time, HD valid after HSTROBE high
Delay time, HSTROBE high to HD high impedance
Delay time, HSTROBE low to HD valid
3
3
3
12
12
12
2
3
2
12
12
12
15
16
||
Delay time, HSTROBE high to HRDY high
17
t
3
12
3
12
ns
d(HSTBH-HRDYH)
†
‡
HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
The effects of internal clock jitter are included at test. There is no need to adjust timing numbers for internal clock jitter. P = 1/CPU clock frequency
in ns. For example, when running parts at 200 MHz, use P = 5 ns.
¶
#
||
HCS enables HRDY, and HRDY is always low when HCS is high. The case where HRDY goes high when HCS falls indicates that HPI is busy
completing a previous HPID write or READ with autoincrement.
This parameter is used during an HPID read. At the beginning of the first half-word transfer on the falling edge of HSTROBE, the HPI sends the
request to the DMA auxiliary channel, and HRDY remains high until the DMA auxiliary channel loads the requested data into HPID.
This parameter is used after the second half-word of an HPID write or autoincrement read. HRDY remains low if the access is not an HPID write
or autoincrement read. Reading or writing to HPIC or HPIA does not affect the HRDY signal.
50
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS320C6201, TMS320C6201B
DIGITAL SIGNAL PROCESSORS
SPRS051F – JANUARY 1997 – REVISED AUGUST 1999
HOST-PORT INTERFACE TIMING (CONTINUED)
HAS
HCNTL[1:0]
HR/W
1
1
1
1
2
2
2
2
2
2
1
1
HHWIL
4
3
3
†
HSTROBE
HCS
15
9
15
9
7
16
HD[15:0] (output)
HRDY (case 1)
HRDY (case 2)
5
5
1st Half-Word
2nd Half-Word
5
8
8
17
17
6
†
HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
Figure 28. HPI Read Timing (HAS Not Used, Tied High)
HAS
19
11
19
11
10
10
10
10
HCNTL[1:0]
HR/W
11
11
11
11
10
10
HHWIL
4
3
†
HSTROBE
18
18
HCS
15
15
7
9
16
9
17
17
HD[15:0] (output)
HRDY (case 1)
HRDY (case 2)
1st half-word
2nd half-word
5
8
8
5
5
6
†
HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
Figure 29. HPI Read Timing (HAS Used)
51
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS320C6201, TMS320C6201B
DIGITAL SIGNAL PROCESSORS
SPRS051F – JANUARY 1997 – REVISED AUGUST 1999
HOST-PORT INTERFACE TIMING (CONTINUED)
HAS
1
1
2
2
HCNTL[1:0]
HBE[1:0]
12
12
13
13
1
1
1
2
2
2
2
HR/W
1
HHWIL
3
3
4
14
†
HSTROBE
HCS
HD[15:0] (input)
HRDY
12
12
13
2nd Half-Word
13
17
1st Half-Word
5
5
†
HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
Figure 30. HPI Write Timing (HAS Not Used, Tied High)
HAS
12
12
19
13
19
13
HBE[1:0]
11
11
11
11
11
11
10
10
10
10
HCNTL[1:0]
10
10
HR/W
HHWIL
3
4
14
†
HSTROBE
18
12
18
HCS
HD[15:0] (input)
HRDY
12
13
13
1st half-word
2nd half-word
5
5
17
†
HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
Figure 31. HPI Write Timing (HAS Used)
52
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS320C6201, TMS320C6201B
DIGITAL SIGNAL PROCESSORS
SPRS051F – JANUARY 1997 – REVISED AUGUST 1999
MULTICHANNEL BUFFERED SERIAL PORT TIMING
†‡
timing requirements for McBSP (see Figure 32)
’C6201-167
’C6201-200
’C6201B
NO.
UNIT
MIN
2P
P – 1
13
4
MAX
MIN
MAX
2
3
t
t
Cycle time, CLKR/X
CLKR/X ext
CLKR/X ext
CLKR int
CLKR ext
CLKR int
CLKR ext
CLKR int
CLKR ext
CLKR int
CLKR ext
CLKX int
CLKX ext
CLKX int
CLKX ext
2P
ns
ns
c(CKRX)
Pulse duration, CLKR/X high or CLKR/X low
P – 1
w(CKRX)
9
2
6
3
8
0
3
4
9
2
6
3
5
6
t
t
t
t
t
t
Setup time, external FSR high before CLKR low
Hold time, external FSR high after CLKR low
Setup time, DR valid before CLKR low
ns
ns
ns
ns
ns
ns
su(FRH-CKRL)
h(CKRL-FRH)
su(DRV-CKRL)
h(CKRL-DRV)
su(FXH-CKXL)
h(CKXL-FXH)
7
3
10
1
7
4
8
Hold time, DR valid after CLKR low
4
13
4
10
11
Setup time, external FSX high before CLKX low
Hold time, external FSX high after CLKX low
7
3
†
‡
CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also inverted.
P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
53
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS320C6201, TMS320C6201B
DIGITAL SIGNAL PROCESSORS
SPRS051F – JANUARY 1997 – REVISED AUGUST 1999
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
†‡§
switching characteristics for McBSP
(see Figure 32)
’C6201-167
’C6201-200
’C6201B
MIN
NO.
PARAMETER
UNIT
MIN
MAX
MAX
Delay time, CLKS high to CLKR/X high for
internal CLKR/X generated from CLKS
input
1
t
4
15
3
10
ns
d(CKSH-CKRXH)
2
3
t
t
Cycle time, CLKR/X
CLKR/X int
CLKR/X int
2P
2P
ns
ns
c(CKRX)
Pulse duration, CLKR/X high or CLKR/X
low
¶
¶
¶
¶
3
C – 1
C + 1
C – 1.3
C + 1
w(CKRX)
Delay time, CLKR high to internal FSR
valid
4
9
t
CLKR int
–2
4
4
–2
ns
ns
d(CKRH-FRV)
d(CKXH-FXV)
CLKX int
CLKX ext
CLKX int
CLKX ext
CLKX int
CLKX ext
0
3
0
3
0
3
–2
3
3
9
4
9
4
9
Delay time, CLKX high to internal FSX
valid
t
16
4
–1
3
Disable time, DX high impedance follow-
ing last data bit from CLKX high
12
13
t
ns
ns
dis(CKXH-DXHZ)
d(CKXH-DXV)
16
4
–1
3
t
Delay time, CLKX high to DX valid
Delay time, FSX high to DX valid
16
FSX int
FSX ext
–2
3
4
–1
3
3
9
14
t
ns
d(FXH-DXV)
ONLY applies when in data
delay 0 (XDATDLY = 00b) mode
16
†
‡
§
¶
CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also inverted.
Minimum delay times also represent minimum output hold times.
P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
C = H or L
S = sample rate generator input clock = P if CLKSM = 1 (P = 1/CPU clock frequency)
=
sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
54
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS320C6201, TMS320C6201B
DIGITAL SIGNAL PROCESSORS
SPRS051F – JANUARY 1997 – REVISED AUGUST 1999
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
CLKS
1
2
3
3
CLKR
FSR (int)
FSR (ext)
DR
4
4
5
6
7
8
Bit(n-1)
(n-2)
(n-3)
2
3
3
CLKX
9
FSX (int)
11
10
FSX (ext)
FSX (XDATDLY=00b)
13
(n-2)
14
13
12
DX
Bit 0
Bit(n-1)
(n-3)
Figure 32. McBSP Timings
55
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS320C6201, TMS320C6201B
DIGITAL SIGNAL PROCESSORS
SPRS051F – JANUARY 1997 – REVISED AUGUST 1999
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
timing requirements for FSR when GSYNC = 1 (see Figure 33)
’C6201-167
’C6201-200
’C6201B
NO.
UNIT
MIN
4
MAX
MIN
4
MAX
1
2
t
t
Setup time, FSR high before CLKS high
Hold time, FSR high after CLKS high
ns
ns
su(FRH-CKSH)
4
4
h(CKSH-FRH)
CLKS
1
2
FSR External
CLKR/X (no need to resync)
CLKR/X (needs resync)
Figure 33. FSR Timing When GSYNC = 1
56
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS320C6201, TMS320C6201B
DIGITAL SIGNAL PROCESSORS
SPRS051F – JANUARY 1997 – REVISED AUGUST 1999
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
†‡
timing requirements for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 0 (see Figure 34)
(’C6201)
’C6201-167
’C6201-200
NO.
UNIT
MASTER
SLAVE
MIN MAX
MIN
12
4
MAX
4
5
t
t
Setup time, DR valid before CLKX low
Hold time, DR valid after CLKX low
2 – 3P
5 + 6P
ns
ns
su(DRV-CKXL)
h(CKXL-DRV)
†
‡
P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
†‡
switching characteristics for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 0
(see Figure 34) (’C6201)
’C6201-167
’C6201-200
NO.
PARAMETER
UNIT
§
MASTER
SLAVE
MIN
MIN MAX
MAX
¶
1
2
3
t
t
t
Hold time, FSX low after CLKX low
T – 2 T + 3
L – 2 L + 3
ns
ns
ns
h(CKXL-FXL)
d(FXL-CKXH)
d(CKXH-DXV)
#
Delay time, FSX low to CLKX high
Delay time, CLKX high to DX valid
–2
4
3P + 4 5P + 17
Disable time, DX high impedance following last data bit from
CLKX low
6
t
L – 2 L + 3
ns
dis(CKXL-DXHZ)
Disable time, DX high impedance following last data bit from
FSX high
7
8
t
t
P + 4 3P + 17
2P + 4 4P + 17
ns
ns
dis(FXH-DXHZ)
Delay time, FSX low to DX valid
d(FXL-DXV)
†
‡
§
P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
S = sample rate generator input clock = P if CLKSM = 1 (P = 1/CPU clock frequency)
=
sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
T = CLKX period = (1 + CLKGDV) * S
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX
and FSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
¶
#
FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock
(CLKX).
57
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS320C6201, TMS320C6201B
DIGITAL SIGNAL PROCESSORS
SPRS051F – JANUARY 1997 – REVISED AUGUST 1999
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
†‡
timing requirements for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 0
(see Figure 34) (’C6201B)
’C6201B
NO.
MASTER
SLAVE
MIN MAX
UNIT
MIN
12
4
MAX
4
5
t
t
Setup time, DR valid before CLKX low
Hold time, DR valid after CLKX low
2 – 3P
5 + 6P
ns
ns
su(DRV-CKXL)
h(CKXL-DRV)
†
‡
P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
†‡
switching characteristics for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 0
(see Figure 34) (’C6201B)
’C6201B
§
NO.
PARAMETER
MASTER
MIN MAX
SLAVE
MIN
UNIT
MAX
¶
1
2
3
t
t
t
Hold time, FSX low after CLKX low
T – 2 T + 3
L – 2 L + 3
ns
ns
ns
h(CKXL-FXL)
d(FXL-CKXH)
d(CKXH-DXV)
#
Delay time, FSX low to CLKX high
Delay time, CLKX high to DX valid
–2
4
3P + 4 5P + 17
Disable time, DX high impedance following last data bit from
CLKX low
6
t
L – 2 L + 3
ns
dis(CKXL-DXHZ)
Disable time, DX high impedance following last data bit from
FSX high
7
8
t
t
P + 3 3P + 17
2P + 2 4P + 17
ns
ns
dis(FXH-DXHZ)
Delay time, FSX low to DX valid
d(FXL-DXV)
†
‡
§
P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
S = sample rate generator input clock = P if CLKSM = 1 (P = 1/CPU clock frequency)
=
sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
T = CLKX period = (1 + CLKGDV) * S
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX
and FSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
¶
#
FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock
(CLKX).
58
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS320C6201, TMS320C6201B
DIGITAL SIGNAL PROCESSORS
SPRS051F – JANUARY 1997 – REVISED AUGUST 1999
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
CLKX
FSX
1
2
8
7
6
3
DX
DR
Bit 0
Bit(n-1)
Bit(n-1)
(n-2)
(n-3)
(n-4)
4
5
Bit 0
(n-2)
(n-3)
(n-4)
Figure 34. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0
59
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS320C6201, TMS320C6201B
DIGITAL SIGNAL PROCESSORS
SPRS051F – JANUARY 1997 – REVISED AUGUST 1999
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
†‡
timing requirements for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 0 (see Figure 35)
(’C6201)
’C6201-167
’C6201-200
NO.
UNIT
MASTER
SLAVE
MIN MAX
MIN
12
4
MAX
4
5
t
t
Setup time, DR valid before CLKX high
Hold time, DR valid after CLKX high
2 – 3P
5 + 6P
ns
ns
su(DRV-CKXH)
h(CKXH-DRV)
†
‡
P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
†‡
switching characteristics for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 0
(see Figure 35) (’C6201)
’C6201-167
’C6201-200
NO.
PARAMETER
UNIT
§
MASTER
SLAVE
MIN
MIN MAX
MAX
¶
1
2
3
t
t
t
Hold time, FSX low after CLKX low
L – 2 L + 3
T – 2 T + 3
ns
ns
ns
h(CKXL-FXL)
d(FXL-CKXH)
d(CKXL-DXV)
#
Delay time, FSX low to CLKX high
Delay time, CLKX low to DX valid
–2
4
3P + 4 5P + 17
3P + 4 5P + 17
2P + 4 4P + 17
Disable time, DX high impedance following last data bit from
CLKX low
6
t
–2
4
ns
ns
dis(CKXL-DXHZ)
7
t
Delay time, FSX low to DX valid
H – 2 H + 4
d(FXL-DXV)
†
‡
§
P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
S = sample rate generator input clock = P if CLKSM = 1 (P = 1/CPU clock frequency)
=
sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
T = CLKX period = (1 + CLKGDV) * S
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX
and FSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
¶
#
FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock
(CLKX).
60
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS320C6201, TMS320C6201B
DIGITAL SIGNAL PROCESSORS
SPRS051F – JANUARY 1997 – REVISED AUGUST 1999
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
†‡
timing requirements for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 0 (see Figure 35)
(’C6201B)
’C6201B
NO.
MASTER
SLAVE
MIN MAX
UNIT
MIN
12
4
MAX
4
5
t
t
Setup time, DR valid before CLKX high
Hold time, DR valid after CLKX high
2 – 3P
5 + 6P
ns
ns
su(DRV-CKXH)
h(CKXH-DRV)
†
‡
P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
†‡
switching characteristics for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 0
(see Figure 35) (’C6201B)
’C6201B
§
NO.
PARAMETER
MASTER
MIN MAX
SLAVE
MIN
UNIT
MAX
¶
1
2
3
t
t
t
Hold time, FSX low after CLKX low
L – 2 L + 3
T – 2 T + 3
ns
ns
ns
h(CKXL-FXL)
d(FXL-CKXH)
d(CKXL-DXV)
#
Delay time, FSX low to CLKX high
Delay time, CLKX low to DX valid
–2
4
3P + 4 5P + 17
3P + 3 5P + 17
Disable time, DX high impedance following last data bit from
CLKX low
6
t
–2
4
ns
ns
dis(CKXL-DXHZ)
7
t
Delay time, FSX low to DX valid
H – 2 H + 4
2P + 2 4P + 17
d(FXL-DXV)
†
‡
§
P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
S = sample rate generator input clock = P if CLKSM = 1 (P = 1/CPU clock frequency)
=
sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
T = CLKX period = (1 + CLKGDV) * S
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX
and FSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
¶
#
FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock
(CLKX).
61
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS320C6201, TMS320C6201B
DIGITAL SIGNAL PROCESSORS
SPRS051F – JANUARY 1997 – REVISED AUGUST 1999
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
CLKX
FSX
DX
1
2
7
6
3
Bit 0
Bit(n-1)
Bit(n-1)
(n-2)
(n-3)
(n-3)
(n-4)
4
5
DR
Bit 0
(n-2)
(n-4)
Figure 35. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0
62
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS320C6201, TMS320C6201B
DIGITAL SIGNAL PROCESSORS
SPRS051F – JANUARY 1997 – REVISED AUGUST 1999
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
†‡
timing requirements for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 1 (see Figure 36)
(’C6201)
’C6201-167
’C6201-200
NO.
UNIT
MASTER
SLAVE
MIN MAX
MIN
12
4
MAX
4
5
t
t
Setup time, DR valid before CLKX high
Hold time, DR valid after CLKX high
2 – 3P
5 + 6P
ns
ns
su(DRV-CKXH)
h(CKXH-DRV)
†
‡
P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
†‡
switching characteristics for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 1
(see Figure 36) (’C6201)
’C6201-167
’C6201-200
NO.
PARAMETER
UNIT
§
MASTER
SLAVE
MIN
MIN MAX
MAX
¶
1
2
3
t
t
t
Hold time, FSX low after CLKX high
T – 2 T + 3
H – 2 H + 3
ns
ns
ns
h(CKXH-FXL)
d(FXL-CKXL)
d(CKXL-DXV)
#
Delay time, FSX low to CLKX low
Delay time, CLKX low to DX valid
–2
4
3P + 4 5P + 17
Disable time, DX high impedance following last data bit from
CLKX high
6
t
H – 2 H + 3
ns
dis(CKXH-DXHZ)
Disable time, DX high impedance following last data bit from
FSX high
7
8
t
t
P + 4 3P + 17
2P + 4 4P + 17
ns
ns
dis(FXH-DXHZ)
Delay time, FSX low to DX valid
d(FXL-DXV)
†
‡
§
P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
S = sample rate generator input clock = P if CLKSM = 1 (P = 1/CPU clock frequency)
=
sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
T = CLKX period = (1 + CLKGDV) * S
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX
and FSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
¶
#
FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock
(CLKX).
63
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS320C6201, TMS320C6201B
DIGITAL SIGNAL PROCESSORS
SPRS051F – JANUARY 1997 – REVISED AUGUST 1999
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
†‡
timing requirements for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 1 (see Figure 36)
(’C6201B)
’C6201B
NO.
MASTER
SLAVE
MIN MAX
UNIT
MIN
12
4
MAX
4
5
t
t
Setup time, DR valid before CLKX high
Hold time, DR valid after CLKX high
2 – 3P
5 + 6P
ns
ns
su(DRV-CKXH)
h(CKXH-DRV)
†
‡
P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
†‡
switching characteristics for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 1
(see Figure 36) (’C6201B)
’C6201B
§
NO.
PARAMETER
MASTER
MIN MAX
SLAVE
MIN
UNIT
MAX
¶
1
2
3
t
t
t
Hold time, FSX low after CLKX high
T – 2 T + 3
H – 2 H + 3
ns
ns
ns
h(CKXH-FXL)
d(FXL-CKXL)
d(CKXL-DXV)
#
Delay time, FSX low to CLKX low
Delay time, CLKX low to DX valid
–2
4
3P + 4 5P + 17
Disable time, DX high impedance following last data bit from
CLKX high
6
t
H – 2 H + 3
ns
dis(CKXH-DXHZ)
Disable time, DX high impedance following last data bit from
FSX high
7
8
t
t
P + 3 3P + 17
2P + 2 4P + 17
ns
ns
dis(FXH-DXHZ)
Delay time, FSX low to DX valid
d(FXL-DXV)
†
‡
§
P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
S = sample rate generator input clock = P if CLKSM = 1 (P = 1/CPU clock frequency)
=
sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
T = CLKX period = (1 + CLKGDV) * S
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX
and FSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
¶
#
FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock
(CLKX).
64
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS320C6201, TMS320C6201B
DIGITAL SIGNAL PROCESSORS
SPRS051F – JANUARY 1997 – REVISED AUGUST 1999
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
CLKX
FSX
1
2
8
7
6
3
DX
DR
Bit 0
Bit(n-1)
Bit(n-1)
(n-2)
(n-3)
(n-4)
4
5
Bit 0
(n-2)
(n-3)
(n-4)
Figure 36. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1
65
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS320C6201, TMS320C6201B
DIGITAL SIGNAL PROCESSORS
SPRS051F – JANUARY 1997 – REVISED AUGUST 1999
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
†‡
timing requirements for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 1 (see Figure 37)
(’C6201)
’C6201-167
’C6201-200
NO.
UNIT
MASTER
SLAVE
MIN MAX
MIN
12
4
MAX
4
5
t
t
Setup time, DR valid before CLKX low
Hold time, DR valid after CLKX low
2 – 3P
5 + 6P
ns
ns
su(DRV-CKXL)
h(CKXL-DRV)
†
‡
P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
†‡
switching characteristics for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 1
(see Figure 37) (’C6201)
’C6201-167
’C6201-200
NO.
PARAMETER
UNIT
§
MASTER
SLAVE
MIN
MIN MAX
MAX
¶
1
2
3
t
t
t
Hold time, FSX low after CLKX high
H – 2 H + 3
T – 2 T + 1
ns
ns
ns
h(CKXH-FXL)
d(FXL-CKXL)
d(CKXH-DXV)
#
Delay time, FSX low to CLKX low
Delay time, CLKX high to DX valid
–2
4
3P + 4 5P + 17
3P + 4 5P + 17
2P + 4 4P + 17
Disable time, DX high impedance following last data bit from
CLKX high
6
t
–2
4
ns
ns
dis(CKXH-DXHZ)
7
t
Delay time, FSX low to DX valid
L – 2 L + 4
d(FXL-DXV)
†
‡
§
P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
S = sample rate generator input clock = P if CLKSM = 1 (P = 1/CPU clock frequency)
=
sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
T = CLKX period = (1 + CLKGDV) * S
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX
and FSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
¶
#
FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock
(CLKX).
66
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS320C6201, TMS320C6201B
DIGITAL SIGNAL PROCESSORS
SPRS051F – JANUARY 1997 – REVISED AUGUST 1999
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
†‡
timing requirements for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 1 (see Figure 37)
(’C6201B)
’C6201B
NO.
MASTER
SLAVE
MIN MAX
UNIT
MIN
12
4
MAX
4
5
t
t
Setup time, DR valid before CLKX low
Hold time, DR valid after CLKX low
2 – 3P
5 + 6P
ns
ns
su(DRV-CKXL)
h(CKXL-DRV)
†
‡
P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
†‡
switching characteristics for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 1
(see Figure 37) (’C6201B)
’C6201B
§
NO.
PARAMETER
MASTER
MIN MAX
SLAVE
MIN
UNIT
MAX
¶
1
2
3
t
t
t
Hold time, FSX low after CLKX high
H – 2 H + 3
T – 2 T + 1
ns
ns
ns
h(CKXH-FXL)
d(FXL-CKXL)
d(CKXH-DXV)
#
Delay time, FSX low to CLKX low
Delay time, CLKX high to DX valid
–2
4
3P + 4 5P + 17
3P + 3 5P + 17
Disable time, DX high impedance following last data bit from
CLKX high
6
t
–2
4
ns
ns
dis(CKXH-DXHZ)
7
t
Delay time, FSX low to DX valid
L – 2 L + 4
2P + 2 4P + 17
d(FXL-DXV)
†
‡
§
P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
S = sample rate generator input clock = P if CLKSM = 1 (P = 1/CPU clock frequency)
=
sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
T = CLKX period = (1 + CLKGDV) * S
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX
and FSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
¶
#
FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock
(CLKX).
67
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS320C6201, TMS320C6201B
DIGITAL SIGNAL PROCESSORS
SPRS051F – JANUARY 1997 – REVISED AUGUST 1999
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
CLKX
FSX
DX
1
2
7
6
3
Bit 0
Bit 0
Bit(n-1)
Bit(n-1)
(n-2)
(n-3)
(n-4)
4
5
DR
(n-2)
(n-3)
(n-4)
Figure 37. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1
68
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS320C6201, TMS320C6201B
DIGITAL SIGNAL PROCESSORS
SPRS051F – JANUARY 1997 – REVISED AUGUST 1999
DMAC, TIMER, POWER-DOWN TIMING
switching characteristics for DMAC outputs (see Figure 38)
’C6201-167
’C6201-200
’C6201B
NO.
PARAMETER
UNIT
MIN
MAX
MIN
MAX
10
1
t
Delay time, CLKOUT1 high to DMAC valid
2
7
2
ns
d(CKO1H-DMACV)
CLKOUT1
DMAC[0:3]
1
1
Figure 38. DMAC Timing
†
timing requirements for timer inputs (see Figure 39)
’C6201-167
’C6201-200
’C6201B
NO.
UNIT
MIN
MAX
MIN
MAX
1
t
Pulse duration, TINP high or low
2P
2P
ns
w(TINP)
†
P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
switching characteristics for timer outputs (see Figure 39)
’C6201-167
’C6201-200
’C6201B
NO.
PARAMETER
UNIT
MIN
MAX
MIN
MAX
2
t
Delay time, CLKOUT1 high to TOUT valid
3
9
2
9
ns
d(CKO1H-TOUTV)
CLKOUT1
TINP
1
2
2
TOUT
Figure 39. Timer Timing
69
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS320C6201, TMS320C6201B
DIGITAL SIGNAL PROCESSORS
SPRS051F – JANUARY 1997 – REVISED AUGUST 1999
DMAC, TIMER, POWER-DOWN TIMING (CONTINUED)
switching characteristics for power-down outputs (see Figure 40)
’C6201-167
’C6201-200
’C6201B
NO.
PARAMETER
UNIT
MIN
MAX
MIN
MAX
1
t
Delay time, CLKOUT1 high to PD valid
3
5
2
9
ns
d(CKO1H-PDV)
CLKOUT1
PD
1
1
Figure 40. Power-Down Timing
70
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS320C6201, TMS320C6201B
DIGITAL SIGNAL PROCESSORS
SPRS051F – JANUARY 1997 – REVISED AUGUST 1999
JTAG TEST-PORT TIMING
timing requirements for JTAG test port (see Figure 41)
’C6201,
’C6201B
NO.
UNIT
MIN
MAX
1
3
4
t
t
t
Cycle time, TCK
50
ns
ns
ns
c(TCK)
Setup time, TDI/TMS/TRST valid before TCK high
Hold time, TDI/TMS/TRST valid after TCK high
10
5
su(TDIV-TCKH)
h(TCKH-TDIV)
switching characteristics for JTAG test port (see Figure 41)
’C6201,
’C6201B
NO.
PARAMETER
UNIT
MIN
MAX
15
2
t
Delay time, TCK low to TDO valid
0
ns
d(TCKL-TDOV)
1
TCK
TDO
2
2
4
3
TDI/TMS/TRST
Figure 41. JTAG Test-Port Timing
71
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS320C6201, TMS320C6201B
DIGITAL SIGNAL PROCESSORS
SPRS051F – JANUARY 1997 – REVISED AUGUST 1999
MECHANICAL DATA
GGP (S-PBGA-N352)
PLASTIC BALL GRID ARRAY (CAVITY DOWN)
31,75 TYP
35,20
SQ
1,27
34,80
0,635
AF
AE
AD
AC
AB
AA
Y
W
V
U
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
1
3
5
7
9
11 13 15 17 19 21 23 25
10 12 14 16 18 20 22 24 26
2
4
6
8
Heat Slug
1,70 MAX
0,91 NOM
Seating Plane
0,15
0,90
0,60
M
0,30
0,50 MIN
4073223/B 11/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Thermally enhanced plastic package with metal heat slug (HSL).
thermal resistance characteristics (S-PBGA package)
†
NO
°C/W
0.94
11.11
9.61
8.24
7.10
Air Flow LFPM
1
2
3
4
5
RΘ
RΘ
RΘ
RΘ
RΘ
Junction-to-case
N/A
0
JC
JA
JA
JA
JA
Junction-to-free air
Junction-to-free air
Junction-to-free air
Junction-to-free air
100
250
500
†
LFPM = Linear Feet Per Minute
72
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS320C6201, TMS320C6201B
DIGITAL SIGNAL PROCESSORS
SPRS051F – JANUARY 1997 – REVISED AUGUST 1999
MECHANICAL DATA
GJC (S-PBGA-N352)
PLASTIC BALL GRID ARRAY
35,20
34,80
SQ
SQ
33,20
32,80
31,75 TYP
1,27
21,00 NOM
0,635
AF
AE
AD
AC
AB
AA
Y
W
V
U
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
1
3
5
7
9
11 13 15 17 19 21 23 25
10 12 14 16 18 20 22 24 26
2
4
6
8
Heat Slug
See Note E
3,50 MAX
1,00 NOM
Seating Plane
0,15
0,90
0,60
M
0,10
0,50 MIN
4173506-2/D 07/99
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Thermally enhanced plastic package with heat slug (HSL).
D. Flip chip application only
E. Possible protrusion in this area, but within 3,50 max package height specification
F. Falls within JEDEC MO-151/BAR-2
thermal resistance characteristics (S-PBGA package)
†
NO
°C/W
0.74
11.31
9.60
8.34
7.30
Air Flow LFPM
1
2
3
4
5
RΘ
RΘ
RΘ
RΘ
RΘ
Junction-to-case
N/A
0
JC
JA
JA
JA
JA
Junction-to-free air
Junction-to-free air
Junction-to-free air
Junction-to-free air
100
250
500
†
LFPM = Linear Feet Per Minute
73
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS320C6201, TMS320C6201B
DIGITAL SIGNAL PROCESSORS
SPRS051F – JANUARY 1997 – REVISED AUGUST 1999
MECHANICAL DATA
GJL (S-PBGA-N352)
PLASTIC BALL GRID ARRAY
27,20
SQ
26,80
25,20
SQ
25,00 TYP
24,80
1,00
16,30 NOM
0,50
AF
AE
AD
AC
AB
AA
Y
W
V
U
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
1
3
5
7
9
11 13 15 17 19 21 23 25
2
4
6
8
10 12 14 16 18 20 22 24 26
Heat Slug
See Note E
3,50 MAX
1,00 NOM
Seating Plane
0,15
0,70
0,10
0,50
M
0,60
0,40
4173516-2/C 07/99
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Thermally enhanced plastic package with heat slug (HSL).
D. Flip chip application only
E. Possible protrusion in this area, but within 3,50 max package height specification
F. Falls within JEDEC MO-151/AAL-1
thermal resistance characteristics (S-PBGA package)
†
NO
°C/W
0.47
14.2
12.3
10.2
8.6
Air Flow LFPM
1
2
3
4
5
RΘ
RΘ
RΘ
RΘ
RΘ
Junction-to-case
N/A
0
JC
JA
JA
JA
JA
Junction-to-free air
Junction-to-free air
Junction-to-free air
Junction-to-free air
100
250
500
†
LFPM = Linear Feet Per Minute
74
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
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