TMS320DM647ZUTD9 [TI]
Digital Media Processor; 数字媒体处理器![TMS320DM647ZUTD9](http://pdffile.icpdf.com/pdf1/p00129/img/icpdf/TMS32_709866_icpdf.jpg)
型号: | TMS320DM647ZUTD9 |
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描述: | Digital Media Processor |
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TMS320DM647
TMS320DM648
www.ti.com
SPRS372F–JANUARY 2010–REVISED SEPTEMBER 2009
TMS320DM647/TMS320DM648 Digital Media Processor
Check for Samples: TMS320DM647, TMS320DM648
1 Features
1
•
Additional Instructions to Support
Complex Multiplies
• High-Performance Digital Media Processor
– 720-MHz, 800-MHz, 900-MHz, 1.1-GHz
C64x+™ Clock Rates
• C64x+ L1/L2 Memory Architecture
– 256K-bit (32K-byte) L1P Program RAM/Cache
[Direct Mapped]
– 1.39 ns (-720), 1.25 ns (-800), 1.11 ns (-900),
0.91 ns (-1100) Instruction Cycle Time
– 256K-bit (32K-byte) L1D Data RAM/Cache
[2-Way Set-Associative]
– 2M-bit/256K-byte (DM647) or
– 5760, 6400, 7200, 8800 MIPS
– Eight 32-Bit C64x+ Instructions/Cycle
– Fully Software-Compatible With C64x/Debug
– Commercial Temperature Ranges (-720, -900,
and -1100 only)
– Extended Temperature Ranges (-800 only)
4M-Bit/512K-byte) (DM648) L2 Unified
Mapped RAM/Cache [Flexible Allocation]
• Supports Little Endian Mode Only
• Five Configurable Video Ports
– Industrial Temperature Ranges (-720, -900,
and -1100 only)
– Providing a Glueless I/F to Common Video
Decoder and Encoder Devices
– Supports Multiple Resolutions/Video
Standards
• VelociTI.2™ Extensions to VelociTI™
Advanced Very-Long-Instruction-Word (VLIW)
TMS320C64x+™ DSP Core
• VCXO Interpolated Control Port (VIC)
– Supports Audio/Video Synchronization
• External Memory Interfaces (EMIFs)
– Eight Highly Independent Functional Units
With VelociTI.2 Extensions:
•
Six ALUs (32-/40-Bit), Each Supports
Single 32-bit, Dual 16-bit, or Quad 8-bit
Arithmetic per Clock Cycle
– 32-Bit DDR2 SDRAM Memory Controller With
512M-Byte(1) Address Space (1.8-V I/O)
•
Two Multipliers Support Four 16 x 16-bit
Multiplies (32-bit Results) per Clock Cycle
or Eight 8 x 8-bit Multiplies (16-Bit
Results) per Clock Cycle
– Asynchronous 16-Bit Wide EMIF (EMIFA)
•
•
Up to 128M-Byte Total Address Reach
64M-Byte Address Reach per CE Space
– Glueless Interface to Asynchronous
Memories (SRAM, Flash, and EEPROM)
– Synchronous Memories (SBSRAM and ZBT
SRAM)
– Supports Interface to Standard Sync Devices
and Custom Logic (FPGA, CPLD, ASICs,
etc.)
– Load-Store Architecture With Non-Aligned
Support
– 64 32-bit General-Purpose Registers
– Instruction Packing Reduces Code Size
– All Instructions Conditional
– Additional C64x+™ Enhancements
•
•
Protected Mode Operation
Exceptions Support for Error Detection
and Program Redirection
• Enhanced Direct-Memory-Access (EDMA)
Controller (64 Independent Channels)
• 3-Port Gigabit Ethernet Switch Subsystem
•
Hardware Support for Modulo Loop
Auto-Focus Module Operation
• Four 64-Bit General-Purpose Timers (Each
Configurable as Two 32-Bit Timers)
• C64x+ Instruction Set Features
– Byte-Addressable (8-/16-/32-/64-bit Data)
– 8-bit Overflow Protection
• One UART (With RTS and CTS Flow Control)
• One 4-wire Serial Port Interface (SPI) With Two
Chip-Selects
• Master/Slave Inter-Integrated Circuit (I2C
Bus™)
• Multichannel Audio Serial Port (McASP)
– Ten Serializers and SPDIF (DIT) Mode
– Bit-Field Extract, Set, Clear
– Normalization, Saturation, Bit-Counting
– VelociTI.2 Increased Orthogonality
– C64x+ Extensions
•
Compact 16-bit Instructions
(1) From Silicon revision 1.1 and onward. In silicon revision 1.0,
the address space is 256M-Bytes.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2010–2009, Texas Instruments Incorporated
TMS320DM647
TMS320DM648
SPRS372F–JANUARY 2010–REVISED SEPTEMBER 2009
www.ti.com
• 16/32-Bit Host-Port Interface (HPI)
• Advanced Event Triggering (AET) Compatible
• 32 General-Purpose I/O (GPIO) Pins
(Multiplexed With Other Device Functions)
• Package:
• 32-Bit 33-/66-MHz, 3.3-V Peripheral Component
Interconnect (PCI) Master/Slave Interface
Conforms to PCI Specification 2.3
• VLYNQ™ Interface (FPGA Interface)
• On-Chip ROM Bootloader
• Individual Power-Saving Modes
• Flexible PLL Clock Generators
– 529-pin nFBGA (ZUT suffix)
– 19x19 mm 0.8 mm pitch BGA
– 0.09-mm/6-Level Cu Metal Process (CMOS)
• 3.3-V and 1.8-V I/O, 1.2-V Internal (-720, -800,
-900, -1100)
• Applications:
• IEEE-1149.1 (JTAG™)
– Digital Video Recording
Boundary-Scan-Compatible
1.1 Trademarks
TMS320C64x+, C64x, C64x+, VelociTI, VelociTI.2, VLYNQ, TMS320C6000, C6000, TI, and TMS320 are
trademarks of Texas Instruments.
I2C Bus is a registered trademark of Koninklijke Philips Electronics N.V.
Windows is a registered trademark of Microsoft Corporation in the United States and/or other countries.
All trademarks are the property of their respective owners.
1.2 Description
The TMS320C64x+™ DSPs (including the TMS320DM647/TMS320DM648 devices) are the
highest-performance fixed-point DSP generation in the TMS320C6000™ DSP platform. The DM647,
DM648 devices are based on the third-generation high-performance, advanced VelociTI™
very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making these DSPs
an excellent choice for digital media applications. The C64x+™ devices are upward code-compatible from
previous devices that are part of the C6000™ DSP platform. The C64x™ DSPs support added
functionality and have an expanded instruction set from previous devices.
Any reference to the C64x DSP or C64x CPU also applies, unless otherwise noted, to the C64x+ DSP and
C64x+ CPU, respectively.
With performance of up to 8800 million instructions per second (MIPS) at a clock rate of 1.1 GHz, the
C64x+ core offers solutions to high-performance DSP programming challenges. The DSP core possesses
the operational flexibility of high-speed controllers and the numerical capability of array processors. The
C64x+ DSP core processor has 64 general-purpose registers of 32-bit word length and eight highly
independent functional units—two multipliers for a 32-bit result and six arithmetic logic units (ALUs). The
eight functional units include instructions to accelerate the performance in video and imaging applications.
The DSP core can produce four 16-bit multiply-accumulates (MACs) per cycle for up to 4400 million MACs
per second (MMACS), or eight 8-bit MACs per cycle for up tp 8800 MMACS. For more details on the
C64x+ DSP, see the TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide (literature
number SPRU732).
The devices also have application-specific hardware logic, on-chip memory, and additional on-chip
peripherals similar to the other C6000 DSP platform devices. The core uses a two-level cache-based
architecture. The Level 1 program cache (L1P) is a 256K-bit direct mapped cache and the Level 1 data
cache (L1D) is a 256K-bit 2-way set-associative cache. The Level 2 memory/cache (L2) consists of a
4M-bit (DM648) or 2M-bit (DM647) memory space that is shared between program and data space. L2
memory can be configured as mapped memory, cache, or combinations of the two.
The peripheral set includes five configurable 16-bit video port peripherals (VP0, VP1, VP2, VP3, and
VP4). These video port peripherals provide a glueless interface to common video decoder and encoder
devices. The video port peripherals support multiple resolutions and video standards (e.g., CCIR601,
ITU-BT.656, BT.1120, SMPTE 125M, 260M, 274M, and 296M), a VCXO interpolated control port (VIC); a
1000 Mbps Ethernet Switch Subsystem with a management data input/output (MDIO) module and two
2
Features
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SGMII ports (DM648) or one SGMII port (only DM647); a 4-bit transmit, 4-bit receive VLYNQ interface; an
inter-integrated circuit (I2C) bus interface; a multichannel audio serial port (McASP) with ten serializers;
four 64-bit general-purpose timers each configurable as two independent 32-bit timers; a user-configurable
16-bit or 32-bit host-port interface (HPI); 32 pins for general-purpose input/output (GPIO) with
programmable interrupt/event generation modes, multiplexed with other peripherals; one UART; and two
glueless external memory interfaces: a synchronous and asynchronous external memory interface
(EMIFA) for slower memories/peripherals, and a higher DDR2 SDRAM interface.
The video port peripherals provide a glueless interface to common video decoder and encoder devices.
The video port peripherals support multiple resolutions and video standards (e.g., CCIR601, ITU-BT.656,
BT.1120, SMPTE 125M, 260M, 274M, and 296M).
The video port peripherals are configurable and can support either video capture and/or video display
modes. Each video port consists of two channels (A and B) with a 5120-byte capture/display buffer that is
splittable between the two channels.
For more details on the video port peripherals, see the TMS320DM647/DM648 Video Port User's Guide
(literature number SPRUEM1).
The management data input/output (MDIO) module continuously polls all 32 MDIO addresses to
enumerate all PHY devices in the system.
The I2C and VLYNQ ports allow the device to easily control peripheral modules and/or communicate with
host processors.
The rich peripheral set provides the ability to control external peripheral devices and communicate with
external processors. For details on each of the peripherals, see the related sections later in this document
and the associated peripheral reference guides.
The devices have a complete set of development tools. These include C compilers, a DSP assembly
optimizer to simplify programming and scheduling, and a Windows™ debugger interface for visibility into
source code execution.
Copyright © 2010–2009, Texas Instruments Incorporated
Features
3
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1.3 Functional Block Diagram
Figure 1-1 shows the functional block diagram of the device.
Timers
(4 64-bit
or 8 32-bit)
PCI66
PLL
JTAG
EDMA 3.0
or
UHPI
CC
3-port Ethernet
Switch
Subsystem
GPIO x32
TC
TC
TC
TC
SGMII
(x2, DM648)
(x1, DM647)
VIC
VLYNQ
Switched Central Resource
DDR2
EMIFA 16-bit
Video Ports (5)
McASP
L2 RAM
L1D 32KB
256KB
(DM647)
C64x+
Mega
512KB
(DM648)
UART
SPI
L2 ROM
64KB
L1P 32KB
I2C
Imaging Coprocessor
Figure 1-1. Functional Block Diagram
4
Features
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6.2
Recommended Clock and Control Signal Transition
1
Features ................................................... 1
Behavior ............................................ 59
1.1 Trademarks .......................................... 2
1.2 Description ........................................... 2
1.3 Functional Block Diagram ............................ 4
6.3 Power Supplies ..................................... 59
6.4 PLL1 Controller ..................................... 65
6.5 PLL2 Controller ..................................... 69
Revision History .............................................. 6
2
6.6
Enhanced Direct Memory Access (EDMA3)
Controller ........................................... 71
Device Overview ........................................ 7
2.1 Device Characteristics ............................... 7
2.2 CPU (DSP Core) Description ........................ 8
2.3 C64x+ CPU ......................................... 11
2.4 Memory Map Summary ............................. 12
2.5 Pin Assignments .................................... 16
2.6 Terminal Functions ................................. 20
2.7 Device Support ..................................... 34
Device Configuration ................................. 38
3.1 System Module Registers .......................... 38
3.2 Bootmode Registers ................................ 39
6.7 Reset Controller .................................... 84
6.8 Interrupts ............................................ 89
6.9 DDR2 Memory Controller ........................... 93
6.10 External Memory Interface A (EMIFA) ............ 104
6.11 Video Port ......................................... 111
6.12 VCXO Interpolated Control (VIC) ................. 119
6.13 Universal Asynchronous Receiver/Transmitter
(UART) ............................................ 121
6.14 Serial Peripheral Interface Port (SPI) ............. 123
6.15 Inter-Integrated Circuit (I2C) ...................... 127
6.16 Host-Port Interface (HPI) Peripheral .............. 131
6.17 Peripheral Component Interconnect (PCI) ........ 142
6.18 Multichannel Audio Serial Port (McASP) .......... 147
6.19 3-Port Ethernet Switch Subsystem (3PSW) ....... 155
6.20 Management Data Input/Output (MDIO) .......... 165
6.21 Timers ............................................. 166
6.22 VLYNQ Peripheral ................................. 168
6.23 General-Purpose Input/Output (GPIO) ............ 171
6.24 Emulation Features and Capability ............... 173
6.25 IEEE 1149.1 JTAG ................................ 174
Mechanical Data ...................................... 176
3
4
3.3 Pullup/Pulldown Resistors .......................... 49
System Interconnect .................................. 50
4.1
Internal Buses, Bridges, and Switch Fabrics ....... 50
4.2 Data Switch Fabric Connections ................... 50
4.3 Configuration Switch Fabric ........................ 52
Device Operating Conditions ....................... 54
5
6
5.1 Absolute Maximum Ratings ........................ 54
5.2 Recommended Operating Conditions .............. 55
5.3 Electrical Characteristics ........................... 56
7
7.1 Thermal Data for ZUT ............................. 176
7.2 Packaging Information ............................ 177
Peripheral Information and Electrical
Specifications .......................................... 57
6.1 Parameter Information .............................. 57
Copyright © 2010–2009, Texas Instruments Incorporated
Contents
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Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
The following table lists the technical changes made for this revision.
DM647/DM648 Revision History
SEE
ADDITIONS, DELETIONS, MODIFICATIONS
Updated TYP values for ICDD and IDDD
Added row for 0x00A4 0000 to 0x00A7 FFFF.
Section 5.3
Table 2-3
6
Contents
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2 Device Overview
2.1 Device Characteristics
Table 2-1, provides an overview of the DSP. The tables show significant features of the devices, including
the capacity of on-chip RAM, the peripherals, the CPU frequency, and the package type with pin count.
Table 2-1. Characteristics of the Processor
HARDWARE FEATURES
DDR2 memory controller (32-bit
DM647
DM648
1
1
bus width) [1.8 V I/O]
16-bit bus width
synchronous/asynchronous
EMIF [EMIFA]
1
1
1
EDMA3 (64 independent
channels, 8 QDMA channels)
1
4 64-bit General Purpose
(each configurable as 1 64-bit or 2
32-bit)
4 64-bit General Purpose
(each configurable as 1 64-bit or 2 32-bit)
Timers
UART
I2C
(with RTS and CTS flow control)
1 (Master/Slave)
(with RTS and CTS flow control)
1 (Master/Slave)
Peripherals
Not all peripheral
pins are available
at the same time
(For more detail,
see Section 3.)
SPI
1 (4-wire, 2 chip select)
1 (10 serializers)
1 (4-wire, 2 chip select)
1 (10 serializers)
McASP
3-port Ethernet Switch
Subsystem supporting
10/100/1000 Base-T
Management data input/output
(MDIO)
1 SGMII port available
2 SGMII ports available
VLYNQ
1
Up to 32 pins
1
1
Up to 32 pins
1
General-purpose input/output
port (GPIO)
HPI (16/32-bit)
PCI (32 bit) (33 MHz or 66
MHz)
1 (PCI33 or PCI66)
1 (PCI33 or PCI66)
VIC
1
1
Configurable video ports
Size (bytes)
5
5
320KB RAM, 64KB ROM
576KB RAM, 64KB ROM
32KB L1 program (L1P)/cache (up to
32KB)
32KB L1 data (L1D)/cache (up to
32KB)
256KB unified mapped RAM/Cache
(L2)
32KB L1 program (L1P)/cache (up to 32KB)
32KB L1 data (L1D)/cache (up to 32KB)
512 KB unified mapped RAM/Cache (L2)
64KB Boot ROM
On-Chip Memory
Organization
64KB Boot ROM
Revision ID Register
(MM_REVID[15:0])
(address location 0x0181 2000)
MegaModule
Rev ID
0x0003
0x1000
0x0003
0x1000
CPU ID + CPU
Rev ID
Control Status Register
(CSR.[31:16])
JTAGID register
(address location: 0x0204 9018)
JTAG BSDL_ID
CPU Frequency
0x1B77 A02F
0x1B77 A02F
MHz
720, 900, 1100
720, 800, 900, 1100
1.39 ns (-720)
1.25 ns (-800)
1.11 ns (-900)
0.91 ns (-1100)
1.39 ns (-720)
1.11 ns (-900)
0.91 ns (-1100)
Cycle Time
Voltage
ns
Core (V)
I/O (V)
1.2 V (-720, -900, -1100)
1.8 V, 3.3 V
1.2 V (-720, -800, -900, -1100)
1.8 V, 3.3 V
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Device Overview
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Table 2-1. Characteristics of the Processor (continued)
HARDWARE FEATURES
DM647
DM648
x1 (Bypass),
x1 (Bypass),
PLL Options
CLKIN1 frequency multiplier
PLLM = 15, 16, …, 31
PLLM = 15, 16, …, 31
(x16, x17, …, x32)(1)
(x16, x17, …, x32)(1)
BGA Package
529-Pin Flip Chip Plastic BGA (ZUT)
529-Pin Flip Chip Plastic BGA (ZUT)
Process
Technology
0.09-mm/6-Level Cu Metal
Process (CMOS)
0.09 mm
0.09 mm
Product Status(2) Production Data (PD)
PD
PD
(1) The maximum CPU frequency must not be violated.
(2) See Section 2.7 for a description of each stage of development.
2.2 CPU (DSP Core) Description
The C64x+ central processing unit (CPU) consists of eight functional units, two register files, and two data
paths as shown in Figure 2-1. The two general-purpose register files (A and B) each contain 32 32-bit
registers for a total of 64 registers. The general-purpose registers can be used for data or can be data
address pointers. The data types supported include packed 8-bit data, packed 16-bit data, 32-bit data,
40-bit data, and 64-bit data. Values larger than 32 bits, such as 40-bit-long or 64-bit-long values are stored
in register pairs, with the 32 LSBs of data placed in an even register and the remaining 8 or 32 MSBs in
the next upper register (which is always an odd-numbered register).
The eight functional units (.M1, .L1, .D1, .S1, .M2, .L2, .D2, and .S2) are each capable of executing one
instruction every clock cycle. The .M functional units perform all multiply operations. The .S and .L units
perform a general set of arithmetic, logical, and branch functions. The .D units primarily load data from
memory to the register file and store results from the register file into memory.
The C64x+ CPU extends the performance of the C64x core through enhancements and new features.
Each C64x+ .M unit can perform one of the following each clock cycle: one 32 x 32 bit multiply, one 16 x
32 bit multiply, two 16 x 16 bit multiplies, two 16 x 32 bit multiplies, two 16 x 16 bit multiplies with
add/subtract capabilities, four 8 x 8 bit multiplies, four 8 x 8 bit multiplies with add operations, and four
16 x 16 multiplies with add/subtract capabilities (including a complex multiply). There is also support for
Galois field multiplication for 8-bit and 32-bit data. Many communications algorithms such as FFTs and
modems require complex multiplication. The complex multiply (CMPY) instruction takes for 16-bit inputs
and produces a 32-bit real and a 32-bit imaginary output. There are also complex multiplies with rounding
capability that produces one 32-bit packed output that contain 16-bit real and 16-bit imaginary values. The
32 x 32 bit multiply instructions provide the extended precision necessary for audio and other
high-precision algorithms on a variety of signed and unsigned 32-bit data types.
The .L or (Arithmetic Logic Unit) now incorporates the ability to do parallel add/subtract operations on a
pair of common inputs. Versions of this instruction exist to work on 32-bit data or on pairs of 16-bit data
performing dual 16-bit add and subtracts in parallel. There are also saturated forms of these instructions.
The C64x+ core enhances the .S unit in several ways. In the C64x core, dual 16-bit MIN2 and MAX2
comparisons were available only on the .L units. On the C64x+ core they are also available on the .S unit,
which increases the performance of algorithms that do searching and sorting. Finally, to increase data
packing and unpacking throughput, the .S unit allows sustained high performance for the quad 8-bit/16-bit
and dual 16-bit instructions. Unpack instructions prepare 8-bit data for parallel 16-bit operations. Pack
instructions return parallel results to output precision including saturation support.
Other new features include:
•
SPLOOP - A small instruction buffer in the CPU that aids in creation of software pipelining loops where
multiple iterations of a loop are executed in parallel. The SPLOOP buffer reduces the code size
associated with software pipelining. Furthermore, loops in the SPLOOP buffer are fully interruptible.
8
Device Overview
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•
Compact Instructions - The native instruction size for the C6000 devices is 32 bits. Many common
instructions such as MPY, AND, OR, ADD, and SUB can be expressed as 16 bits if the C64x+
compiler can restrict the code to use certain registers in the register file. This compression is
performed by the code generation tools.
•
Instruction Set Enhancement - As noted above, there are new instructions such as 32-bit
multiplications, complex multiplications, packing, sorting, bit manipulation, and 32-bit Galois field
multiplication.
•
•
Exceptions Handling - Intended to aid the programmer in isolating bugs. The C64x+ CPU is able to
detect and respond to exceptions, both from internally detected sources (such as illegal opcodes).
Privilege - Defines user and supervisor modes of operation, allowing the operating system to give a
basic level of protection to sensitive resources. Local memory is divided into multiple pages, each with
read, write, and execute permissions.
•
Time-Stamp Counter - Primarily targeted for real-time operating system (RTOS) robustness, a
free-running time-stamp counter that is not sensitive to system stalls is implemented in the CPU.
For more details on the C64x+ CPU and its enhancements over the C64x architecture, see the following
documents:
•
•
•
•
TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide (literature number SPRU732)
TMS320C64x+ DSP Megamodule Reference Guide (literature number SPRU871)
TMS320C64x to TMS320C64x+ CPU Migration Guide Application Report (literature number SPRAA84)
TMS320C64x+ DSP Cache User's Guide (literature number SPRU862)
Copyright © 2010–2009, Texas Instruments Incorporated
Device Overview
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Even
register
file A
(A0, A2,
A4...A30)
src1
src2
Odd
register
file A
(A1, A3,
A5...A31)
.L1
odd dst
even dst
long src
(D)
8
32 MSB
32 LSB
ST1b
ST1a
8
long src
even dst
odd dst
src1
(D)
Data path A
.S1
src2
32
32
(A)
(B)
dst2
dst1
src1
.M1
src2
(C)
32 MSB
32 LSB
LD1b
LD1a
dst
src1
src2
.D1
.D2
DA1
2x
1x
Even
register
file B
(B0, B2,
B4...B30)
Odd
register
file B
(B1, B3,
B5...B31)
src2
DA2
src1
dst
32 LSB
LD2a
LD2b
32 MSB
src2
(C)
.M2
src1
dst2
32
32
(B)
(A)
dst1
src2
src1
.S2
odd dst
even dst
long src
(D)
Data path B
8
8
32 MSB
32 LSB
ST2a
ST2b
long src
even dst
(D)
odd dst
.L2
src2
src1
Control Register
A. On .M unit, dst2 is 32 MSB.
B. On .M unit, dst1 is 32 LSB.
C. On C64x CPU .M unit, src2 is 32 bits; on C64x+ CPU .M unit, src2 is 64 bits.
D. On .L and .S units, odd dst connects to odd register files and even dst connects to even register files.
Figure 2-1. TMS320C64x+™ CPU (DSP Core) Data Paths
10
Device Overview
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2.3 C64x+ CPU
The C64x+ core uses a two-level cache-based architecture. The Level 1 program memory/cache (L1P)
consists of 32KB memory space that can be configured as mapped memory or direct mapped cache. The
Level 1 data memory/cache (L1D) consists of 32KB that can be configured as mapped memory or 2-way
associated cache. The Level 2 memory/cache (L2) consists of a 256KB (DM647)/512 KB (DM648)
memory space that is shared between program and data space. L2 memory can be configured as mapped
memory, cache, or a combination of both.
Table 2-2 shows a memory map of the C64x+ CPU cache registers for the device.
Table 2-2. C64x+ Cache Registers
HEX ADDRESS RANGE
0x0184 0000
REGISTER ACRONYM
L2CFG
L1PCFG
L1PCC
L1DCFG
L1DCC
-
DESCRIPTION
L2 cache configuration register
0x0184 0020
L1P size cache configuration register
L1P freeze mode cache configuration register
L1D size cache configuration register
L1D freeze mode cache configuration register
Reserved
0x0184 0024
0x0184 0040
0x0184 0044
0x0184 0048 - 0x0184 0FFC
0x0184 1000
-
Reserved
0x0184 1004 - 0x0184 1FFC
0x0184 2000
-
Reserved
L2ALLOC0
L2ALLOC1
L2ALLOC2
L2ALLOC3
-
L2 allocation register 0
0x0184 2004
L2 allocation register 1
0x0184 2008
L2 allocation register 2
0x0184 200C
L2 allocation register 3
0x0184 2010 - 0x0184 3FFF
0x0184 4000
Reserved
L2WBAR
L2WWC
L2WIBAR
L2WIWC
L2IBAR
L2IWC
L2 writeback base address register
L2 writeback word count register
L2 writeback invalidate base address register
L2 writeback invalidate word count register
L2 invalidate base address register
L2 invalidate word count register
L1P invalidate base address register
L1P invalidate word count register
L1D writeback invalidate base address register
L1D writeback invalidate word count register
Reserved
0x0184 4004
0x0184 4010
0x0184 4014
0x0184 4018
0x0184 401C
0x0184 4020
L1PIBAR
L1PIWC
L1DWIBAR
L1DWIWC
-
0x0184 4024
0x0184 4030
0x0184 4034
0x0184 4038
0x0184 4040
L1DWBAR
L1DWWC
L1DIBAR
L1DIWC
-
L1D block writeback
0x0184 4044
L1D block writeback
0x0184 4048
L1D invalidate base address register
L1D invalidate word count register
Reserved
0x0184 404C
0x0184 4050 - 0x0184 4FFF
0x0184 5000
L2WB
L2 writeback all register
0x0184 5004
L2WBINV
L2INV
L2 writeback invalidate all register
L2 global invalidate without writeback
Reserved
0x0184 5008
0x0184 500C - 0x0184 5027
0x0184 5028
-
L1PINV
-
L1P global invalidate
0x0184 502C - 0x0184 5039
0x0184 5040
Reserved
L1DWB
L1DWBINV
L1DINV
L1D global writeback
0x0184 5044
L1D global writeback with invalidate
L1D global invalidate without writeback
0x0184 5048
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Table 2-2. C64x+ Cache Registers (continued)
HEX ADDRESS RANGE
0x0184 8000 - 0x0184 80FC
0x0184 80C0 - 0x0184 80FC
0x0184 8100 - 0x0184 813C
0x0184 8140 - 0x0184 827C
0x0184 8280 - 0x0184 82BC
0x0184 82C0 - 0x0184 82FC
0x0184 8130 - 0x0184 813C
0x0184 8300 - 0x0184 837C
0x0184 8380 - 0x0184 83BC
0x0184 83C0 - 0x0184 83FC
REGISTER ACRONYM
MAR0 - MAR63
DESCRIPTION
Reserved 0x0000 0000 - 0x3FFF FFFF
Reserved 0x3000 0000 - 0x3FFF FFFF
MAR48 - MAR63
MAR64 - MAR79
Memory attribute registers for PCI Data 0x4000 0000 - 0x4FFF FFFF
Reserved 0x5000 0000 - 0x9FFF FFFF
MAR80 - MAR159
MAR160 - MAR175
MAR176 - MAR191
MAR76 - MAR79
Memory attribute registers for EMIFA CE2 0xA000 0000 - 0xA3FF FFFF
Memory attribute registers for EMIFA CE3 0xB000 0000 - 0xB3FF FFFF
Memory Attribute Registers for VLYNQ 0x4C00 0000 - 0x4FFF FFFF
Reserved 0xC000 0000 - 0xDFFF FFFF
MAR192 - MAR223
MAR224 - MAR239
MAR240 - MAR255
Memory attribute registers for DDR2 0xE000 0000 - 0xEFFF FFFF
Memory attribute registers for DDR2 0xF000 0000 - 0xFFFF FFFF
2.4 Memory Map Summary
Table 2-3 shows the memory map address ranges of the device. The device has multiple on-chip
memories associated with its processor and various subsystems. To help simplify software development,
a unified memory map is used where possible to maintain a consistent view of device resources across all
bus masters.
Table 2-3. Memory Map Summary
START
END
SIZE
C64x+
ADDRESS
ADDRESS
(Bytes)
MEMORY MAP
0x0000 0000
0x0010 0000
0x0020 0000
0x0080 0000
0x008C 0000
0x00A0 0000
0x00A4 0000
0x00A8 0000
0x00E0 0000
0x00E0 8000
0x00F0 0000
0x00F0 8000
0x0100 0000
0x0180 0000
0x0181 0000
0x0181 1000
0x0181 2000
0x0181 3000
0x0182 0000
0x0182 0410
0x0183 0000
0x0184 0000
0x0185 0000
0x01BC 0000
0x01BD 0000
0x01BE 0000
0x01BE 0000
0x0200 0000
0x0200 0080
0x0204 0000
0x000F FFFF
0x0011 FFFF
0x007F FFFF
0x008B FFFF
0x009F FFFF
0x00A3 FFFF
0x00A7 FFFF
0x00DF FFFF
0x00E0 7FFF
0x00EF FFFF
0x00F0 7FFF
0x00FF FFFF
0x017F FFFF
0x0180 FFFF
0x0181 0FFF
0x0181 1FFF
0x0181 2FFF
0x0181 FFFF
0x0182 040F
0x0182 FFFF
0x0183 FFFF
0x0184 FFFF
0x01BB FFFF
0x01BC FFFF
0x01BD FFFF
0x01BF FFFF
0x01FF FFFF
0x0200 007F
0x0203 FFFF
0x0204 3FFF
1M
128K
6M
Reserved
VICP
Reserved
Internal ROM
Reserved
768K
2M - 768K
256K
256K
4M - 512K
32K
L2 SRAM (for both DM647 and DM648)
L2 SRAM (for DM648 only)
Reserved
L1P SRAM
1M – 32K
32K
Reserved
L1D SRAM
1M – 32K
8M
Reserved
Reserved
64K
C64x+ Interrupt Controller
C64x+ Power-down Control
C64x+ Security ID
C64x+ Revision ID
Reserved
4K
4K
4K
52K
1040B
64K – 16
64K
C64x+ EMC
Reserved
Reserved
64K
C64x+ Memory control
Reserved
3, 520K
64K
Emulation
64K
Reserved
128K
4.125M
128B
256K – 128
16K
Reserved
Reserved
HPI Control
Reserved
McASP Control
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Table 2-3. Memory Map Summary (continued)
START
END
SIZE
C64x+
ADDRESS
0x0204 4000
0x0204 4400
0x0204 4800
0x0204 4C00
0x0204 5000
0x0204 5400
0x0204 6000
0x0204 7000
0x0204 7400
0x0204 7800
0x0204 7C00
0x0204 8000
0x0204 8400
0x0204 8800
0x0204 9000
0x0204 A000
0x0208 0000
0x020A 0000
0x020E 0000
0x020E 0200
0x0212 0000
0x0212 0200
0x0216 0000
0x02A0 0000
0x02A0 8000
0x02A2 0000
0x02A2 8000
0x02A3 0000
0x02A3 8000
0x02A4 0000
0x02A8 0000
0x02A8 0500
0x02AC 0000
0x02AE 0000
0x02B0 0000
0x02B0 0100
0x02B0 4000
0x02B0 4080
0x02B4 0000
0x02B4 0200
0x02B8 0000
0x02BA 0000
0x02BC 0000
0x02C0 0000
0x02C0 4000
0x02C0 8000
0x02C0 C000
0x02C1 0000
0x02C1 4000
0x02C4 0000
ADDRESS
(Bytes)
MEMORY MAP
0x0204 43FF
0x0204 47FF
0x0204 4BFF
0x0204 4FFF
0x0204 53FF
0x0204 5FFF
0x0204 6FFF
0x0204 73FF
0x0204 77FF
0x0204 7BFF
0x0204 7FFF
0x0204 83FF
0x0204 87FF
0x0204 8FFF
0x0204 9FFF
0x0207 FFFF
0x0209 FFFF
0x020D FFFF
0x020E 01FF
0x0211 FFFF
0x0212 01FF
0x0215 FFFF
0x029C FFFF
0x02A0 7FFF
0x02A1 FFFF
0x02A2 7FFF
0x02A2 FFFF
0x02A3 7FFF
0x02A3 FFFF
0x02A7 FFFF
0x02A8 04FF
0x02AB FFFF
0x02AD FFFF
0x02AF FFFF
0x02B0 00FF
0x02B0 3FFF
0x02B0 407F
0x02B3 FFFF
0x02B4 01FF
0x02B7 FFFF
0x02B9 FFFF
0x02BB FFFF
0x02BF FFFF
0x02C0 3FFF
0x02C0 7FFF
0x02C0 BFFF
0x02C0 FFFF
0x02C1 3FFF
0x02C3 FFFF
0x02C7 FFFF
1K
1K
McASP Data
Timer0
1K
Timer1
1K
Timer2
1K
Timer3
3K
Reserved
PSC
4K
1K
UART
1K
VIC Control
SPI
1K
1K
I2C Data and Control
GPIO
1K
1K
PCI Control
Reserved
Chip-Level Registers
Reserved
VICP Configuration
Reserved
PLL Controller 1
Reserved
PLL Controller 2
Reserved
Reserved
EDMA3CC
Reserved
EDMA3TC0
EDMA3TC1
EDMA3TC2
EDMA3TC3
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
VP0 Control
VP1 Control
VP2 Control
VP3 Control
VP4 Control
Reserved
Reserved
2K
4K
216K
128K
256K
512
256K – 512
512
256K – 512
9M - 576K
32K
96K
32K
32K
32K
32K
256K
1.25K
256K – 1.25K
128K
128K
256
16K – 256
128
256K – 128
512
256K – 512
128K
128K
256K
16K
16K
16K
16K
16K
176K
256K
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Table 2-3. Memory Map Summary (continued)
START
END
SIZE
C64x+
ADDRESS
ADDRESS
(Bytes)
MEMORY MAP
0x02C8 0000
0x02CC 0000
0x02D0 0000
0x02D0 2000
0x02D0 3000
0x02D0 4000
0x02D0 4800
0x02D0 4C00
0x02D0 5000
0x02D0 5800
0x02DC 0000
0x02E0 0000
0x02E0 4000
0x0300 0000
0x0400 0000
0x1000 0000
0x2000 0000
0x3000 0000
0x3000 0100
0x3400 0000
0x3400 0100
0x3800 0000
0x3C00 0000
0x3D00 0000
0x3E00 0000
0x4000 0000
0x5000 0000
0x5200 0000
0x5400 0000
0x5600 0000
0x5800 0000
0x5A00 0000
0x5C00 0000
0x5E00 0000
0x6000 0000
0x6200 0000
0x6400 0000
0x6600 0000
0x6800 0000
0x7000 0000
0x7800 0000
0x8000 0000
0x9000 0000
0xA000 0000
0xA400 0000
0xB000 0000
0x02CB FFFF
0x02CF FFFF
0x02D0 1FFF
0x02D0 2FFF
0x02D0 3FFF
0x02D0 47FF
0x02D0 4BFF
0x02D0 4FFF
0x02D0 57FF
0x02DB FFFF
0x02DF FFFF
0x02E0 3FFF
0x02FF FFFF
0x03FF FFFF
0x0FFF FFFF
0x1FFF FFFF
0x2FFF FFFF
0x3000 00FF
0x33FF FFFF
0x3400 00FF
0x37FF FFFF
0x3BFF FFFF
0x3CFF FFFF
0x3DFF FFFF
0x3FFF FFFF
0x4FFF FFFF
0x51FF FFFF
0x53FF FFFF
0x55FF FFFF
0x57FF FFFF
0x59FF FFFF
0x5BFF FFFF
0x5DFF FFFF
0x5FFF FFFF
0x61FF FFFF
0x63FF FFFF
0x65FF FFFF
0x67FF FFFF
0x6FFF FFFF
0x77FF FFFF
0x7FFF FFFF
0x8FFF FFFF
0x9FFF FFFF
0xA3FF FFFF
0xAFFF FFFF
0xB3FF FFFF
256K
256K
8K
Reserved
Reserved
Ethernet Subsystem CPPI RAM(1)
Ethernet Subsystem Control
Ethernet Subsystem 3PSW
Ethernet Subsystem MDIO
Ethernet Subsystem SGMII0
Ethernet Subsystem SGMII1 (DM648 only)
Reserved
4K
4K
2K
1K
1K
2K
746K
256K
16K
Reserved
Reserved
Reserved
2M – 16K
16M
Reserved
Reserved
192M
256M
256M
256
Reserved
Reserved
Reserved
Reserved
64M – 256
256
Reserved
Reserved
64M – 256
64M
Reserved
VLYNQ
16M
Reserved
16M
Reserved
32M
Reserved
256M
32M
PCI Data
VP0 ChannelA Data
VP0 ChannelB Data
VP1 ChannelA Data
VP1 ChannelB Data
VP2 ChannelA Data
VP2 ChannelB Data
Reserved
32M
32M
32M
32M
32M
32M
32M
Reserved
32M
VP3 ChannelA Data
VP3 ChannelB Data
VP4 ChannelA Data
VP4 ChannelB Data
Reserved
32M
32M
32M
128M
128M
128M
256M
256M
64M
EMIFA Configuration
DDR2 EMIF Configuration
Reserved
Reserved
EMIFA CE2(2)
256 - 64M
64M
Reserved
EMIFA CE3(2)
(1) The 8K CPPI Descriptor memory is mapped to an address range 0x02C8 2000 - 0x02C8 3FFF, from the perspective of the Ethernet
subsystem 3PSW. The buffer descriptors, when accessed from the C64x+, are addressed from 0x02D0 0000. However, within these
buffer descriptors, when the pointer to the next buffer descriptor is programmed, the Ethernet subsystem 3PSW is interpreting this value.
Thus, this programmed value should be in the address range starting from 0x02C8 2000.
(2) The EMIFA CS0 and CS1 are not functionally supported; therefore, they are not pinned out.
14
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Table 2-3. Memory Map Summary (continued)
START
END
SIZE
C64x+
ADDRESS
0xB400 0000
0xC000 0000
0xD000 0000
0xE000 0000
0xF000 0000
ADDRESS
(Bytes)
MEMORY MAP
0xBFFF FFFF
0xCFFF FFFF
0xDFFF FFFF
0xEFFF FFFF
0xFFFF FFFF
256 - 64M
256M
Reserved
Reserved
256M
Reserved
256M
DDR2 SDRAM
DDR2 SDRAM
256M
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2.5 Pin Assignments
Extensive use of pin multiplexing is used to accommodate the largest number of peripheral functions in
the smallest possible package. Pin multiplexing is controlled using a combination of hardware
configuration at device reset and software programmable register settings. For more information on pin
muxing, see Section 3.2.6, PINMUX Register.
2.5.1 Pin Map (Bottom View)
Figure 2-2 through Figure 2-5 show the bottom view of the ZUT package pin assignments in four
quadrants (A, B, C, and D).
1
2
3
4
5
6
7
8
9
10
11
12
AC
AB
AA
Y
VSS
DVDD33
DVDD33
VSS
VSS
VSS
AHCLKX
AHCLKR
ACLKR
ACLKX
SGMII1RXN
REFCLKN
AVDDR
VSS
DVDD33
AVDDT
DVDD33
VP2CLK0
VP2CTL0
VP2CTL1
AMUTEIN
AXR3
AXR0
SGMII1RXP
REFCLKP
VDAC/
AXR9
PREQ/
GP03
VSS
VSS
VSS
SGMII0TXP
SGMII0TXN
AVDDA
VP2D03
VP2D06
AXR6
AXR2
AXR1
AFSX
SGMII0RXP SGMII0RXN
VP2CTL2/
VSCRUN
STCLK/
AXR8
DVDD33
DVDD33
VSS
VSS
VP2D04
VP2D07
AXR4
RSV21
RSV22
VP2CLK1/
VCLK
VP2D12/
VRXD0
VSS
AVDDA
VP2D09
VP2D02
VP2D08
AFSR
AXR7
SGMII1TXP SGMII1TXN
W
V
VP2D13
/VRXD1
VP2D14/
VRXD2
PINTA/
GP02
VSS
DVDD33
CVDD
VSS
AXR5
RSV17
DVDDD
DVDDD
VSS
VP2D15/
VRXD3
VP2D17/
VTXD1
VP2D16/
VTXD0
VP2D19/
VTXD3
VP2D18/
VTXD2
PRST/
GP01
AVDDT
U
AMUTE
VP2D05
MDIO
MDCLK
VP3CLK0/
VP3CTL0/
VP3D05/
AED03
VP3D04/
AED02
VP3D03/
AED01
VP3D02/
AED00
VSS
DVDD33
VSS
VSS
DVDD33
T
AECLKIN AAWE/ASWE
VP3CTL1/
AR/W
VP3D12/
AED08
VP3D09/
AED07
VP3D08/
AED06
VP3D07/
AED05
VP3D06/
AED04
CVDDESS
CVDDESS
DVDD33
CVDD
DVDD33
VSS
VSS
R
VP3CLK1/
VP3CTL2/
VP3D16/
AED12
VP3D15/
AED11
VP3D14/
AED10
VP3D13/
AED09
VSS
VSS
CVDD
VSS
CVDD
P
AECLKOUT AAOE/ASOE
VP3D17/
AED13
VP3D19/
AED15
VP3D18/
AED14
VSS
DVDD33
DVDD33
VSS
VSS
N
CVDD
CVDD
PLLV1
VP4D03/
ABE01
VP4D04/
AEA10
VSS
DVDD33
VSS
VSS
CVDD
CVDD
M
CLKIN1
RSV9
SYSCLK5
VP4D05
Figure 2-2. ZUT Pin Map [Top Left Quadrant]
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13
14
15
16
17
18
19
20
21
22
23
AD26/
HD26
AD22/
HD22
PCLK/
AD14/
HD14
AD02/
HD02
AD04/
HD04
PCBE1/
HDS2
PCBE0/
GP04
VSS
DVDD33
DVDD33
AC
AB
AA
Y
HHWIL
AD27/
HD27
AD23/
HD23
AD17/
HD17
AD12/
HD12
AD08/
HD08
AD05/
HD05
AD01/
HD01
PIRDY/
HRDY
DVDD33
VSS
VSS
AD28/
HD28
PIDSEL/
GP06
AD18/
HD18
PFRAME/ PTRDY/
AD15/
HD15
AD13/
HD13
AD09/
HD09
AD06/
HD06
AD00/
HD00
AD03/
HD03
HINT
GP05
PDEVSEL/ PSTOP/
HCNTL1 HCNTL0
AD29/
HD29
AD19/
HD19
AD16/
HD16
AD11/
HD11
AD10/
HD10
AD07/
HD07
PCBE3/
GP07
VP0CTL0 VP0CLK0
AD30/
HD30
AD24/
HD24
AD20/
HD20
PPAR/
HAS
PCBE2/
HR/W
PPERR/
HCS
PSERR/
HDS1
VSS
DVDD33
VP0D02
VP0D09
VP0D16
VP0D06
W
V
AD31/
HD31
Ad25/
HD25
AD21/
HD21
VP0D12/
GP12
DVDD33
VSS
DVDD33
VSS
VP0D03
VP0D04
VP0D07
VP0D19
VP0D05
VP0D08
VP0CTL1 VP0CLK1
VP0D17 VP0CTL2
PGNT/
GP00
VSS
DVDD33
VSS
DVDD33
VSS
VP0D18
U
VP0D13/
GP13
VP0D14/ VP0D15/
CVDD
VSS
CVDD
VSS
VSS
VSS
DVDD33
T
GP14
GP15
VP1D02/
GP16
VP1D07/
GP21
VP1D06/
GP20
VP1D05/
GP19
CVDD
VSS
DVDD33
VSS
DVDD33
VP1CTL0
R
VP1D04/
GP18
VP1D03/
GP17
VP1D14/
GP26
VP1D13/
GP25
CVDD
VSS
CVDD
VSS
VSS
VP1CTL1 VP1CLK0
VP1CTL2 VP1CLK1
P
VP1D17/
GP29
VP1D12/
GP24
VP1D09/
GP23
VP1D08/
GP22
CVDD
VSS
DVDD33
N
VP1D16/
GP28
VP1D19/
GP31
VP1D15/
GP27
VP1D18/
GP30
VSS
CVDD
DVDD33
VSS
VSS
DVDD33
M
Figure 2-3. ZUT Pin Map [Top Right Quadrant]
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VP4CLK0/
AARDY
VP4D02/
ABE00
VP4D06/
ACE2
VP4D07/
ACE3
VP4D08/
AEA00
VP4D13/
AEA03
DVDD33
VSS
DVDD33
VSS
CVDD
VSS
CVDD
VSS
CVDD
VSS
L
K
J
VP4CTL2/
VP4D09/
AEA01
VP4D12/
AEA02
VP4D14/
AEA04
VP4D19/
AEA09
VSS
VSS
CVDD
VSS
VP4CLK1
ASADS/ASRE
VP4CTL1/ VP4CTL0/
VP4D15/
AEA05
VP4D16/
AEA06
VP4D17/
AEA07
VP4D18/
AEA08
DVDD33
CVDD
VSS
CVDD
ABA1
ABA0
HPIWIDTH/
AEA16
RSV_BOOT/
AEA15
H
G
F
VSS
CVDD1
DVDD18
VSS
DVDD18
UHPIEN
AEA23
AEA19
RSV7
RSV8
EMIFA
WIDTH/
AEA22
AECLKIN
SEL/
BOOT
MODE3/
AEA14
FASTBOOT
/AEA21
PCI66/
AEA18
DVDD33
VSS
DVDD18
VSS
DVDD18
VSS
PLLV2
AEA17
DEVICE
ENABLE0/
AEA20
BOOT
MODE0/
AEA11
BOOT
MODE1/
AEA12
BOOT
MODE2/
AEA13
DDR_A13
DDR_RAS
DDR_A06
DDR_A08
VSS
DVDD18
DDR_CS
CLKIN2
RSV12
RSV18
DDR_D07 DDR_D04
DDR_D00
DDR_BA[2] DDR_A12
E
D
C
B
A
DVDD18
VSS
RSV11
RSV14
RSV13
DDR_
DDR_
DDR_D10
DDR_D05
VSS
VSS
DDR_CAS DDR_WE
RSV4
RSV3
RSV6
RSV5
DQM[1]
DQGATE0
DDR_
DVDD18
VREF
DDR_D15
DDR_D08 DDR_D06 DDR_D03 DDR_D01
DDR_BA[0]
DVDD18
VSS
RSV20
RSV19
DDR_
DDR_
AVDLL1
DDR_D12 DDR_D14
DDR_D11 DDR_D13
DDR_D09
DDR_D02
DDR_CKE DDR_BA[1]
DVDD18
VDD18MON
DVDD18
DQM[0]
DQGATE1
DDR_
DDR_
DDR_
DDR_
VSS
VSS
DDR_CLK
DDR_CLK
RSV10
2
RSV15
10
DQS[1]
DQS[0]
DQS[1]
DQS[0]
1
3
4
5
6
7
8
9
11
12
Figure 2-4. ZUT Pin Map [Bottom Left Quadrant]
18
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CVDD
VSS
VSS
CVDD
VSS
VCCMON
L
CVDD
DVDD33
EMU4
EMU11
NMI
RSV1
EMU3
EMU8
EMU9
RSV2
EMU2
EMU5
TMS
EMU1
TDI
TRST
EMU0
TDO
K
J
VSS
VSS
DVDD33
VSS
EMU6
CVDD1
CVDD
VSS
DVDD33
EMU10
RESETSTAT
DVDD33
H
G
F
VSS
DVDD18
VSS
DVDD18
VSS
DVDD33
VSS
DVDD18
VSS
DVDD33
EMU7
TCLK
POR
SPIDI/
VDD33MON
VSS
DVDD18
VSS
VSS
VSS
RESET
UARTRTS
SPICS2/
UARTRX
SPIDO/
DVDD18
DVDD18
DVDD18
VSS
DVDD33
DDR_A02
SPICLK
DVDD33
SCL
UARTCTS
DDR_
T0INP12/
GP08
T1INP12/
GP10
E
D
C
B
A
DDR_
VSS
DDR_ODT0 DDR_A03
DDR_D19 DDR_D23
DDR_D31
DQGATE2
DQM[2]
SPICS1/
UARTTX
T0OUT12/
GP09
VSS
DDR_A09
DDR_A04 DDR_A00 DDR_D18
DDR_D22 DDR_D25 DDR_D29
T1OUT12/
GP11
DVDD18
DVDD18
DDR_A05 DDR_A01 DDR_D17 DDR_D21 DDR_D24 DDR_D27 DDR_D30
SDA
DDR_
DVDD18
DVDD18
AVDLL2
DVDD18
DDR_A11 DDR_A07
DDR_A10 DDR_ODT1
DDR_D16 DDR_D20
DDR_D26 DDR_D28
DQM[3]
DDR_
DDR_
DQS[2]
DDR_
DDR_
DQS[3]
DDR_
VSS
VSS
RSV16
22
VSS
DQS[2]
DQGATE3
DQS[3]
13
14
15
16
17
18
19
20
21
23
Figure 2-5. ZUT Pin Map [Bottom Right Quadrant]
Copyright © 2010–2009, Texas Instruments Incorporated
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2.6 Terminal Functions
The terminal functions tables (Table 2-4 through Table 2-5) identify the external signal names, the
associated pin (ball) numbers along with the mechanical package designator, the pin type, whether the pin
has any internal pullup or pulldown resistors, and a functional pin description. For more detailed
information on device configuration, peripheral selection, multiplexed/shared pin, and debugging
considerations, see Section 3.
All device boot and configuration pins are multiplexed with functional pins. These pins function as device
boot and configuration pins only during device reset. When both the reset pin (RESET) and the power-on
reset pin (POR) are deasserted, the input states of these multiplexed device boot and configuration pins
are sampled and latched into the BOOTCFG register. For proper device operation, these pins must be
pulled up/down to the desired value via an external resistor.
Table 2-4. Terminal Functions
TERMINAL NAME
NO
TYPE
INTERNAL
PULLUP/
OPER
VOLT
DESCRIPTION
PULLDOWN
Clock/PLL Configuration
CLKIN1
M1
F1
I
IPD
IPD
3.3 V
3.3 V
Clock Input for PLL1
CLKIN2
I
Clock Input for PLL2
REFCLKN(1)
REFCLKP(1)
PLLV1
AC11
AB11
N3
I
Differential Reference Clock input (negative) for SGMII
Differential Reference Clock input (positive) for SGMII
1.8-V I/O Supply Voltage for PLL1
1.8-V I/O Supply Voltage for PLL2
Clock out of device speed/4
I
A
1.8 V
1.8 V
3.3 V
PLLV2
G7
A
SYSCLK5
M3
I/O/Z
IPD
JTAG
TCLK
TDI
H23
J22
J23
L22
L23
K23
K22
K21
K20
L18
J21
K19
H21
J20
H20
J19
K18
I
IPU
IPU
IPU
IPU
IPD
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
JTAG Test Port Clock
I
JTAG Test Port Data In
TDO
OZ
JTAG Test Port Data Out
JTAG Test Port Mode Select
JTAG Test Port Reset
TMS
I
TRST
EMU0
EMU1
EMU2
EMU3
EMU4
EMU5
EMU6
EMU7
EMU8
EMU9
EMU10
EMU11
I
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
JTAG Test Port Emulation 0
JTAG Test Port Emulation 1
JTAG Test Port Emulation 2
JTAG Test Port Emulation 3
JTAG Test Port Emulation 4
JTAG Test Port Emulation 5
JTAG Test Port Emulation 6
JTAG Test Port Emulation 7
JTAG Test Port Emulation 8
JTAG Test Port Emulation 9
JTAG Test Port Emulation 10
JTAG Test Port Emulation 11
RESET/INTERRUPTS
NMI
J18
H19
G20
H18
I
O
I
IPD
3.3 V
3.3 V
3.3 V
3.3 V
Nonmaskable Interrupt
RESETSTAT
RESET
POR
Reset Status Pin
Device Reset
I
Power On Reset
(1) The clock input buffers on the REFCLKP/N pins are compatible with LVDS and LVPECL clock sources. These input buffers include a
100-Ω termination (P to N) and a common-mode biasing. Because the common-mode biasing is included, the clock source must be AC
coupled.
20
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Table 2-4. Terminal Functions (continued)
TERMINAL NAME
NO
TYPE
INTERNAL
PULLUP/
OPER
VOLT
DESCRIPTION
PULLDOWN
HOST-PORT INTERFACE (HPI) or PERIPHERAL COMPONENT INTERCONNECT (PCI) or GPIO[0:7]
AD00/HD00
AD01/HD01
AD02/HD02
AD03/HD03
AD04/HD04
AD05/HD05
AD06/HD06
AD07/HD07
AD08/HD08
AD09/HD09
AD10/HD10
AD11/HD11
AD12/HD12
AD13/HD13
AD14/HD14
AD15/HD15
AD16/HD16
AD17/HD17
AD18/HD18
AD19/HD19
AD20/HD20
AD21/HD21
AD22/HD22
AD23/HD23
AD24/HD24
AD25/HD25
AD26/HD26
AD27/HD27
AD28/HD28
AD29/HD29
AD30/HD30
AD31/HD31
PPAR/HAS
PSTOP/HCNTL0
AA22 I/O/Z
AB22 I/O/Z
AC21 I/O/Z
AA23 I/O/Z
AC22 I/O/Z
AB21 I/O/Z
AA21 I/O/Z
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPU
IPD
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
Host Port data [15:00] pin or PCI data-address bus [15:00]
[default]
Y21
I/O/Z
AB20 I/O/Z
AA20 I/O/Z
Y20
Y19
I/O/Z
I/O/Z
AB18 I/O/Z
AA19 I/O/Z
AC18 I/O/Z
AA18 I/O/Z
Y16
I/O/Z
Host Port data [31:16] pin or PCI data-address bus [31:16]
[default]
AB15 I/O/Z
AA15 I/O/Z
Y15
W15
V15
I/O/Z
I/O/Z
I/O/Z
AC14 I/O/Z
AB14 I/O/Z
W14
V14
I/O/Z
I/O/Z
AC13 I/O/Z
AB13 I/O/Z
AA13 I/O/Z
Y13
W13
V13
W19
Y18
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
Host Address Strobe (I) or PCI parity [default]
Host Control selects between control, address, or data registers (I)
or PCI Stop [default]
PDEVSEL/HCNTL1
Y17
I/O/Z
IPD
3.3 V
Host Control selects between control, address, or data registers (I)
or PCI Device Select [default]
PPERR/HCS
PSERR/ HDS1
PCBE0/GP04
PCBE1/HDS2
PCBE2/HR/W
PCBE3/GP07
PCLK/HHWIL
W17
W18
I/O/Z
I/O/Z
IPU
IPU
IPU
IPU
IPU
IPU
IPU
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
Host Chip Select (I) or PCI Parity Error [default]
Host Data Strobe 1 (I) or PCI System Error [default]
PCI Command/Byte Enable 0 or GP[2] [default
PCI Command/Byte Enable 1 or host data strobe 2
PCI Command/Byte Enable 2 or host read or write select (I)
PCI Command/Byte Enable 3 or GPIO[7]
AC20 I/O/Z
AC17
W16
Y14
I
I/O/Z
I/O/Z
AC15 I/O/Z
PCI Clock (I) [default] or host Half-word Select - first or second
half-word (not necessarily high or low order) [For HPI16 bus width
selection only] (I)
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Table 2-4. Terminal Functions (continued)
TERMINAL NAME
NO
TYPE
INTERNAL
PULLUP/
OPER
VOLT
DESCRIPTION
PULLDOWN
PFRAME/HINT
PIRDY/HRDY
PGNT/GP00
PRST/GP01
PINTA/GP02
PREQ/GP03
PTRDY/GP05
PIDSEL/GP06
AA16 I/O/Z
AB17 I/O/Z
IPU
IPD
IPD
IPD
IPD
IPD
IPD
IPD
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
PCI Frame or host interrupt from DSP to host (O/Z)
PCI Initiator Ready [default] or Host Ready from DSP to host (O/Z)
PCI Bus Grant (I) or GPIO[0]
U13
U12
V12
I/O/Z
I/O/Z
I/O/Z
PCI Reset (I) or GPIO[1]
PCI Interrupt A (O/Z) or GPIO[2]
AA12 I/O/Z
AA17 I/O/Z
AA14 I/O/Z
PCI Bus Request (O/Z) or GPIO[3]
PCI Target Ready or GPIO[5]
PCI Initialization Device Select (I) or GPIO[6]
DDR2 MEMORY CONTROLLER
DDR2 Memory Controller Bank Address Control
DDR_BA[0]
DDR_BA[1]
DDR_BA[2]
DDR_CS
C12
B12
E11
F9
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
DDR2 Memory Controller Memory Space Enable
DDR2 Memory Controller External Address
DDR_A00
DDR_A01
DDR_A02
DDR_A03
DDR_A04
DDR_A05
DDR_A06
DDR_A07
DDR_A08
DDR_A09
DDR_A10
DDR_A11
DDR_A12
DDR_A13
DDR_CLK
D15
C15
F13
E14
D14
C14
F11
B14
F12
D13
A13
B13
E12
F10
A12
Negative DDR2 Memory Controller Output Clock (CLKIN2
frequency x 10)
DDR_CLK
DDR_D00
DDR_D01
DDR_D02
DDR_D03
DDR_D04
DDR_D05
DDR_D06
DDR_D07
DDR_D08
DDR_D09
DDR_D10
DDR_D11
DDR_D12
DDR_D13
DDR_D14
DDR_D15
A11
E9
C9
B9
C8
E8
D8
C7
E7
C6
B7
D6
A3
B3
A4
B4
C5
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
DDR2 Memory Controller Output Clock (CLKIN2 frequency x 10)
DDR2 Memory Controller External Data
22
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Table 2-4. Terminal Functions (continued)
TERMINAL NAME
NO
TYPE
INTERNAL
PULLUP/
OPER
VOLT
DESCRIPTION
PULLDOWN
DDR_D16
DDR_D17
DDR_D18
DDR_D19
DDR_D20
DDR_D21
DDR_D22
DDR_D23
DDR_D24
DDR_D25
DDR_D26
DDR_D27
DDR_D28
DDR_D29
DDR_D30
DDR_D31
DDR_ODT0
DDR_ODT1
B16
C16
D16
E16
B17
C17
D17
E17
C18
D18
B19
C19
B20
D19
C20
E19
E13
A14
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
DDR2 Memory Controller External Data (continued)
On-die termination signals to external DDR2 SDRAM. These pins
are reserved for future use and should not be connected to the
DDR2 SDRAM.
Note: There are no on-die termination resistors implemented on
the DM647/DM648 DSP die.
DDR_CAS
D10
B11
D7
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
DDR2 Memory Controller SDRAM column address strobe
DDR2 Memory Controller SDRAM clock-enable
DDR2 Memory Controller Data Strobe Gate
DDR_CKE
DDR_DQGATE0
DDR_DQGATE1
DDR_DQGATE2
DDR_DQGATE3
DDR_DQM[0]
DDR_DQM[1]
DDR_DQM[2]
DDR_DQM[3]
DDR_DQS[0]
DDR_DQS[1]
DDR_DQS[2]
DDR_DQS[3]
DDR_DQS[0]
DDR_DQS[1]
DDR_DQS[2]
DDR_DQS[3]
DDR_RAS
B6
E18
A21
B8
DDR2 Memory Controller Byte-enable Controls. Decoded from the
low-order address bits. The number of address bits or byte
enables used depends on the width of external memory. Byte-write
enables for most types of memory. Can be directly connected to
SDRAM read and write mask signal (SDQM).
D5
E15
B21
A9
DDR2 Memory Controller Data Strobe [3:0]
A7
A17
A20
A8
DDR2 Memory Controller Data Strobe [3:0] Negative
A6
A16
A19
E10
D11
DDR2 Memory Controller SDRAM Row Address Strobe
DDR2 Memory Controller SDRAM Write Enable
DDR_WE
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Table 2-4. Terminal Functions (continued)
TERMINAL NAME
NO
TYPE
INTERNAL
PULLUP/
OPER
VOLT
DESCRIPTION
PULLDOWN
CONFIGURATION AND EMIFA
DEVICEENABLE0/
AEA20
F2
I/O/Z
I/O/Z
IPD
IPD
3.3 V
EMIFA External Address 20 (word address). (O/Z) For proper
device operation, this pin must be externally pulled up with a 1-kΩ
resistor at device reset
EMIFAWIDTH/
AEA22
G3
3.3 V
EMIFA External Address 22 (word address). (O/Z) EMIFA data
bus width selection pin state captured at the rising edge of
RESET.
0 - sets EMIFA CS2 to 8-bit data bus width
1 - sets EMIFA CS2 to 16 bit data bus width. For details, see
Section 3.
FASTBOOT/
AEA21
G2
H2
I/O/Z
I
IPD
IPD
3.3 V
3.3 V
EMIFA External Address 22 (word address). (O/Z) Enables FAST
BOOT of the device. For details, see Section 3.
UHPIEN
UHPI Enable Pin. This pin controls the selection (enable/disable)
of the HPI and GPIO[0:7] muxed with PCI. For details, see
Section 3.
HPIWIDTH/
AEA16
H3
H6
G5
I/O/Z
I/O/Z
I/O/Z
IPD
IPU
IPD
3.3 V
3.3 V
3.3 V
EMIFA External Address 16 (word address) (O/Z) HPI peripheral
bus width (HPI_WIDTH) select (Applies only when HPI is enabled;
UHPIEN pin = 1)
RSV_BOOT/
AEA15
EMIFA External Address 15 (word address) (O/Z) For proper
device operation, this pin must be externally pulled up with a 1-kΩ
resistor at device reset.
PCI66/AEA18
PCI Frequency Selection (PCI66). The PCI peripheral must be
enabled (UHPIEN = 0) to use this function. PCI66_AEA18 selects
the PCI operating frequency of 66 MHz or 33 MHz. PCI operating
frequency is selected at reset via the pullup/pulldown resistor on
the PCI66 pin AEA18:
0 - PCI operates at 33 MHz (default)
1 - PCI operates at 66 MHz.
BOOTMODE0/AEA11
BOOTMODE1/AEA12
BOOTMODE2/AEA13
BOOTMODE3/AEA14
F3
F4
F5
G6
I/O/Z
IPD
3.3 V
The BOOTMODE[3:0] defines what boot code is executed on
device reset. See Section 3.2.1 for more details.
INTER-INTEGRATED CIRCUIT (I2C)
SCL
SDA
D22
C23
I/O/Z
I/O/Z
3.3 V
I2C clock. When the I2C module is used, use an external pullup
resistor.
3.3 V
I2C data. When I2C is used, make certain there is an external
pullup resistor.
SGMII0/1 and MDIO(1)(2)
SGMII0RXN
SGMII0RXP
SGMII0TXN
SGMII0TXP
SGMII1RXN
SGMII1RXP
SGMII1TXN
SGMII1TXP
MDCLK
AA10
AA9
W11
Y11
AC9
AB9
W9
I
I
1.2 V
1.2 V
1.2 V
1.2 V
1.2 V
1.2 V
1.2 V
1.2 V
3.3 V
Differential SGMII Port 0 RX input (negative)
Differential SGMII Port 0 RX input (positive)
Differential SGMII Port 0 TX output (negative)
Differential SGMII Port 0 TX output (positive)
Differential SGMII Port 1 RX input (negative)
Differential SGMII Port 1 RX input (positive)
Differential SGMII Port 1 TX output (negative)
Differential SGMII Port 1 TX output (positive)
MDIO Serial Clock (MDCLK)
O
O
I
I
O
O
OZ
W8
U9
IPD
(1) For DM647: Leave the SGMII1RXP/N and SGMII1TXP/N pins disconnected. Disable ENTX/ENRX bits in CFGTX1/CFGRX1 for SGMII1
and still configure the CFGPLL because the SerDes TXBCLK0 is used as the internal VBUS clock. For DM648: if one of the SGMII pair
is not used, the same approach must be used.
(2) If the Ethernet Subsystem is not used at all, these connections must be followed:
•
•
•
•
Disconnect AA10, AA9, W11,Y11, AC9, AB9, W9, W8, and U9
Connect AC11 to CVDD
Connect AB11 to VSS
Directly connect V11 (VDDA), W10 (VDDA), T10 (VDDD), U10 (VDDD) , AB8 (VDDT), U11 (VDDT), R9 (ESS core power), R11 (ESS core
power) to CVDD
•
Directly connect AB10, (VDDR) to DVDD18
24
Device Overview
Copyright © 2010–2009, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): TMS320DM647 TMS320DM648
TMS320DM647
TMS320DM648
www.ti.com
SPRS372F–JANUARY 2010–REVISED SEPTEMBER 2009
Table 2-4. Terminal Functions (continued)
TERMINAL NAME
NO
TYPE
INTERNAL
PULLUP/
OPER
VOLT
DESCRIPTION
PULLDOWN
MDIO
U8
I/O/Z
IPU
3.3 V
MDIO Serial Data (MDIO)
SPI or UART
SPICLK
F22
D23
F23
G23
F21
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
IPU
IPU
IPU
IPU
IPU
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
SPI Clock Output
SPICS1/UARTTX
SPICS2/UARTRX
SPIDI/UARTRTS
SPIDO/UARTCTS
SPI Chip Select 1 or UART Transmit (O/Z)
SPI Chip Select 2 or UART Receive
SPI Data input or UART Ready to send (O/Z)
SPI Data Output or UART Clear to send
TIMER 0/1 or GPIO[8:11]
T0INP12/GP08
T0OUT12/GP09
T1INPL/GP10
E20
D21
E21
C22
I/O/Z
I/O/Z
I/O/Z
I/O/Z
IPD
IPD
IPD
IPD
3.3 V
3.3 V
3.3 V
3.3 V
Timer 0 input pin for lower 32-bit counter (I) or GPIO 8
Timer 0 output pin for lower 32-bit counter (O/Z) or GPIO 9
Timer 1 input pin for lower 32-bit counter (I) or GPIO 10
Timer 1 output pin for lower 32-bit counter(O/Z) or GPIO 11
T1OUT12/GP11
McASP OR VIDEO PORT OR VIC
McASP Receive high-frequency master clock
AHCLKR
AHCLKX
ACLKR
ACLKX
AFSR
AC4
AC3
AC6
AC7
W6
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
McASP Transmit high-frequency master clock
McASP Receive master clock
McASP Transmit master clock
McASP Receive Frame sync or left/right clock (LRCLK)
McASP Transmit Frame sync or left/right clock (LRCLK)
McASP Data Pin [0:7]
AFSX
AA7
AB6
Y6
AXR0
AXR1
AXR2
AA6
AB4
Y5
AXR3
AXR4
AXR5
V7
AXR6
AA4
V6
AXR7
STCLK/AXR8
Y7
I/O/Z
I/O/Z
The STCLK signal drives the hardware counter for use by the
video ports (I) or McASP data pin 8.
VDAC/AXR9
AA5
IPD
3.3 V
VCXO Interpolated Control Port (VIC) single-bit digital-to-analog
converter (VDAC) output (O) or McASP data pin 9
AMUTEIN
AMUTE
AB3
U7
I/O/Z
I/O/Z
IPD
IPD
3.3 V
3.3 V
McASP Mute Input
McASP Mute Output
VIDEO PORT 0 OR GPIO[12:15]
VP0CLK0
VP0CLK1
VP0CTL0
VP0CTL1
VP0CTL2
VP0D02
VP0D03
VP0D04
VP0D05
VP0D06
VP0D07
VP0D08
Y23
V23
Y22
V22
U23
W20
V18
U18
V19
W21
T18
U19
I
IPU
IPU
IPU
IPU
IPU
IPD
IPD
IPD
IPD
IPD
IPD
IPD
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
Video Port 0 Clock 0 (I)
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
Video Port 0 Clock 1
Video Port 0 Control 0
Video Port 0 Control 1
Video Port 0 Control 2
Video Port 0 Data 2
Video Port 0 Data 3
Video Port 0 Data 4
Video Port 0 Data 5
Video Port 0 Data 6
Video Port 0 Data 7
Video Port 0 Data 8
Copyright © 2010–2009, Texas Instruments Incorporated
Device Overview
25
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TMS320DM647
TMS320DM648
SPRS372F–JANUARY 2010–REVISED SEPTEMBER 2009
www.ti.com
Table 2-4. Terminal Functions (continued)
TERMINAL NAME
NO
TYPE
INTERNAL
PULLUP/
OPER
VOLT
DESCRIPTION
PULLDOWN
VP0D09
V20
V21
T19
T20
T21
U20
U22
U21
R18
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
Video Port 0 Data 9
VP0D12/GP12
VP0D13/GP13
VP0D14/GP14
VP0D15/GP15
VP0D16
Video Port 0 Data 12 or GPIO 12
Video Port 0 Data 13 or GPIO 13
Video Port 0 Data 14 or GPIO 14
Video Port 0 Data 15 or GPIO 15
Video Port 0 Data 16
VP0D17
Video Port 0 Data 17
VP0D18
Video Port 0 Data 18
VP0D19
Video Port 0 Data 19
VIDEO PORT 1 OR GPIO[16:31]
Video Port 1 Clock 0
VP1CLK0
P23
N23
R23
P22
N22
R19
P19
P18
R22
R21
R20
N21
N20
N19
P21
P20
M20
M18
N18
M21
M19
I
IPU
IPU
IPU
IPU
IPU
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
VP1CLK1
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
Video Port 1 Clock 1
VP1CTL0
Video Port 1 Control 0
VP1CTL1
Video Port 1 Control 1
VP1CTL2
Video Port 1 Control 2
VP1D02/GP16
VP1D03/GP17
VP1D04/GP18
VP1D05/GP19
VP1D06/GP20
VP1D07/GP21
VP1D08/GP22
VP1D09/GP23
VP1D12/GP24
VP1D13/GP25
VP1D14/GP26
VP1D15/GP27
VP1D16/GP28
VP1D17/GP29
VP1D18/GP30
VP1D19/GP31
Video Port 1 Data 2 or GPIO 16
Video Port 1 Data 3 or GPIO 17
Video Port 1 Data 4 or GPIO 18
Video Port 1 Data 5 or GPIO 19
Video Port 1 Data 6 or GPIO 20
Video Port 1 Data 7 or GPIO 21
Video Port 1 Data 8 or GPIO 22
Video Port 1 Data 9 or GPIO 23
Video Port 1 Data 12 or GPIO 24
Video Port 1 Data 13 or GPIO 25
Video Port 1 Data 14 or GPIO 26
Video Port 1 Data 15 or GPIO 27
Video Port 1 Data 16 or GPIO 28
Video Port 1 Data 17 or GPIO 29
Video Port 1 Data 18 or GPIO 30
Video Port 1 Data 19 or GPIO 31
VIDEO PORT 2 OR VLYNQ
Video Port 2 Clock 0 (I)
VP2CLK0
VP2CLK1/VCLK
VP2CTL0
VP2CTL1
VP2CTL2/VSCRUN
VP2D02
AB1
W1
AA1
AB2
Y1
I
IPU
IPU
IPU
IPU
IPU
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
Video Port 2 Clock 1 or VLYNQ Clock (I/O)
Video Port 2 Control 0
Video Port 2 Control 1
Video Port 2 Control 2 or VLYNQ serial clock run request (I/O)
Video Port 2 Data 2
W5
AA2
Y3
VP2D03
Video Port 2 Data 3
VP2D04
Video Port 2 Data 4
VP2D05
U6
Video Port 2 Data 5
VP2D06
Y2
Video Port 2 Data 6
VP2D07
W3
V5
Video Port 2 Data 7
VP2D08
Video Port 2 Data 8
VP2D09
W4
W2
Video Port 2 Data 9
VP2D12/VRXD0
Video Port 2 Data 12 or VLYNQ receive data pin [0] (I)
26
Device Overview
Copyright © 2010–2009, Texas Instruments Incorporated
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Product Folder Link(s): TMS320DM647 TMS320DM648
TMS320DM647
TMS320DM648
www.ti.com
SPRS372F–JANUARY 2010–REVISED SEPTEMBER 2009
Table 2-4. Terminal Functions (continued)
TERMINAL NAME
NO
TYPE
INTERNAL
PULLUP/
OPER
VOLT
DESCRIPTION
PULLDOWN
VP2D13/VRXD1
VP2D14/VRXD2
VP2D15/VRXD3
VP2D16/VTXD0
VP2D17/VTXD1
VP2D18/VTXD2
VP2D19/VTXD3
V3
V4
U1
U3
U2
U5
U4
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
IPD
IPD
IPD
IPD
IPD
IPD
IPD
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
Video Port 2 Data 13 or VLYNQ receive data pin [1] (I)
Video Port 2 Data 14 or VLYNQ receive data pin [2] (I)
Video Port 2 Data 15 or VLYNQ receive data pin [3] (I)
Video Port 2 Data 16 or VLYNQ transmit data pin [0] (O)
Video Port 2 Data 17 or VLYNQ transmit data pin [1] (O)
Video Port 2 Data 18 or VLYNQ transmit data pin [2] (O)
Video Port 2 Data 19 or VLYNQ transmit data pin [3] (O)
VIDEO PORT 3 OR EMIFA
VP3CLK0/ AECLKIN
T1
P1
I
IPD
IPD
3.3 V
3.3 V
Video Port 3 Clock 0 (I) or EMIFA external input clock (I)
VP3CLK1/
I/O/Z
Video Port 3 Clock 1 or EMIFA output clock (O/Z)
AECLKOUT
VP3CTL0/
AAWE/ASWE
T2
I/O/Z
IPU
3.3 V
Video Port 3 Control 0 or Asynchronous memory write
enable/Programmable synchronous interface write-enable
VP3CTL1/ AR/W
R1
P2
I/O/Z
I/O/Z
IPU
IPU
3.3 V
3.3 V
Video Port 3 Control 1 or Asynchronous memory read/write (O/Z)
VP3CTL2/
AAOE/ASOE
Video Port 3 Control 2 or Asynchronous/Programmable
synchronous memory output-enable (O/Z)
VP3D02/AED00
VP3D03/AED01
VP3D04/AED02
VP3D05/AED03
VP3D06/AED04
VP3D07/AED05
VP3D08/AED06
VP3D09/AED07
VP3D12/AED08
VP3D13/AED09
VP3D14/AED10
VP3D15/AED11
VP3D16/AED12
VP3D17/AED13
VP3D18/AED14
VP3D19/AED15
T6
T5
T4
T3
R6
R5
R4
R3
R2
P6
P5
P4
P3
N4
N6
N5
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
Video Port 3 Data 2 or EMIFA External Data 0
Video Port 3 Data 3 or EMIFA External Data 1
Video Port 3 Data 4 or EMIFA External Data 2
Video Port 3 Data 5 or EMIFA External Data 3
Video Port 3 Data 6 or EMIFA External Data 4
Video Port 3 Data 7 or EMIFA External Data 5
Video Port 3 Data 8 or EMIFA External Data 6
Video Port 3 Data 9 or EMIFA External Data 7
Video Port 3 Data 12 or EMIFA External Data 8
Video Port 3 Data 13 or EMIFA External Data 9
Video Port 3 Data 14 or EMIFA External Data 10
Video Port 3 Data 15 or EMIFA External Data 11
Video Port 3 Data 16 or EMIFA External Data 12
Video Port 3 Data 17 or EMIFA External Data 13
Video Port 3 Data 18 or EMIFA External Data 14
Video Port 3 Data 19 or EMIFA External Data 15
VIDEO PORT 4 OR EMIFA
VP4CLK0/AARDY
VP4CLK1
L1
K1
J2
I
IPU
IPD
IPD
3.3 V
3.3 V
3.3 V
Video Port 4 Clock 0 (I) or Asynchronous memory ready input (I)
I/O/Z
I/O/Z
Video Port 4 Clock 1
VP4CTL0/ABA0
Video Port 4 Control 0 or EMIFA bank address control (ABA[1:0])
(O/Z). Active-low bank selects for the 16-bit EMIFA. When
interfacing to 16-bit asynchronous devices, ABA1 carries bit 1 of
the byte address. For an 8-bit asynchronous interface, ABA[1:0]
are used to carry bits 1 and 0 of the byte address.
VP4CTL1/ABA1
J1
I/O/Z
IPD
3.3 V
Video Port 4 Control 1 or EMIFA bank address control (ABA[1:0])
(O/Z). Active-low bank selects for the 16-bit EMIFA. WHEN
interfacing to 16-bit asynchronous devices, ABA1 carries bit 1 of
the byte address. For an 8-bit asynchronous interface, ABA[1:0]
are used to carry bits 1 and 0 of the byte address.
Copyright © 2010–2009, Texas Instruments Incorporated
Device Overview
27
Submit Documentation Feedback
Product Folder Link(s): TMS320DM647 TMS320DM648
TMS320DM647
TMS320DM648
SPRS372F–JANUARY 2010–REVISED SEPTEMBER 2009
www.ti.com
Table 2-4. Terminal Functions (continued)
TERMINAL NAME
NO
TYPE
INTERNAL
PULLUP/
OPER
VOLT
DESCRIPTION
PULLDOWN
VP4CTL2/ ASADS/
ASRE
K2
I/O/Z
IPD
3.3 V
Video Port 4 Control 2 or Programmable synchronous address
strobe or read-enable. For programmable synchronous interface,
the r_enable field in the ChipSelect x Configuration Register
selects between ASADS and ASRE:
– If r_enable = 0, then the ASADS/ASRE signal functions as the
ASADS signal.
– If r_enable = 1, then the ASADS/ASRE signal functions as the
ASRE signal.
VP4D02/ ABE00
L2
I/O/Z
IPU
3.3 V
Video Port 4 Data 2 or EMIFA byte-enable control 0. Decoded
from the low-order address bits. The number of address bits or
byte enables used depends on the width of external memory.
Byte-write enables for most types of memory.
VP4D03/ABE01
VP4D04/AEA10
M4
M5
I/O/Z
I/O/Z
IPU
IPU
3.3 V
3.3 V
Video Port 4 Data 3 or EMIFA byte-enable control 1. Number of
address bits or byte enables used depends on the width of
external memory. Byte-write enables for most types of memory.
Video Port 4 Data 4 or EMIFA External Address 10 (word address)
(O/Z)
VP4D05
M6
L3
L4
L5
I/O/Z
I/O/Z
I/O/Z
I/O/Z
IPU
IPU
IPU
IPD
3.3 V
3.3 V
3.3 V
3.3 V
Video Port 4 Data 5
VP4D06/ACE2
VP4D07/ACE3
VP4D08/AEA00
Video Port 4 Data 6 or EMIFA memory space enable 2
Video Port 4 Data 7 or EMIFA memory space enable 3
Video Port 4 Data 8 or EMIFA External Address 0 (word address)
(O/Z)
VP4D09/AEA01
VP4D12/AEA02
VP4D13/AEA03
VP4D14/AEA04
VP4D15/AEA05
VP4D16/AEA06
VP4D17/AEA07
VP4D18/AEA08
VP4D19/AEA09
K3
K4
L6
K5
J3
J4
J5
J6
K6
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
Video Port 4 Data 9 or EMIFA External Address 1 (word address)
(O/Z)
Video Port 4 Data 12 or EMIFA External Address 2 (word address)
(O/Z)
Video Port 4 Data 13 or EMIFA External Address 3 (word address)
(O/Z)
Video Port 4 Data 14 or EMIFA External Address 4 (word address)
(O/Z)
Video Port 4 Data 15 or EMIFA External Address 5 (word address)
(O/Z)
Video Port 4 Data 16 or EMIFA External Address 6 (word address)
(O/Z)
Video Port 4 Data 17 or EMIFA External Address 7 (word address)
(O/Z)
Video Port 4 Data 18 or EMIFA External Address 8 (word address)
(O/Z)
Video Port 4 Data 19 or EMIFA External Address 9 (word address)
(O/Z)
EMIFA
AEA23
H4
H5
G4
OZ
O/Z
IPD
IPU
IPD
3.3 V
3.3 V
3.3 V
EMIFA External Address 23 (word address) (O/Z)
EMIFA External Address 19 (word address) (O/Z)
AEA19
AECLKINSEL/AEA17
I/O/Z
Select EMIFA external clock (I) (The EMIFA input clock AECLKIN
or SYSCLK4 is selected at reset via the pullup/pulldown resistor
on this pin. Note: AECLKIN is the default for the EMIFA input
clock.)
or EMIFA external address 17 (word address) (O/Z)
Table 2-5. Terminal Functions (Ground and Power Supply)
TERMINAL
NAME
NO
TYPE
INTERNAL
PULLUP/
OPER
VOLT
DESCRIPTION
PULLDOWN
VSS
VSS
A1
A5
Ground
Ground
28
Device Overview
Copyright © 2010–2009, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): TMS320DM647 TMS320DM648
TMS320DM647
TMS320DM648
www.ti.com
SPRS372F–JANUARY 2010–REVISED SEPTEMBER 2009
Table 2-5. Terminal Functions (Ground and Power Supply) (continued)
TERMINAL
NAME
NO
TYPE
INTERNAL
PULLUP/
OPER
VOLT
DESCRIPTION
PULLDOWN
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A15
A18
A23
C4
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
D9
D12
D20
E6
E23
F7
F15
F17
F19
G8
G10
G12
G14
G16
G18
G22
H1
H11
H13
H15
H17
J8
J10
J12
J14
J16
K7
K9
K11
K13
K15
K17
L8
L10
L12
L14
L16
M7
M9
M11
M13
M15
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Table 2-5. Terminal Functions (Ground and Power Supply) (continued)
TERMINAL
NAME
NO
TYPE
INTERNAL
PULLUP/
OPER
VOLT
DESCRIPTION
PULLDOWN
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
M17
M22
N1
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
N8
N10
N12
N14
N16
P7
P9
P11
P13
P15
P17
R10
R12
R14
R16
T7
T9
T11
T13
T15
T17
T22
U14
U16
V1
V9
V17
W7
W22
Y9
Y10
AA3
AA8
AA11
AB5
AB19
AB23
AC1
AC8
AC10
AC12
AC16
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Table 2-5. Terminal Functions (Ground and Power Supply) (continued)
TERMINAL
NAME
NO
TYPE
INTERNAL
PULLUP/
OPER
VOLT
DESCRIPTION
PULLDOWN
POWER PINS
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDDESS
CVDDESS
AVDLL1
AVDLL2
CVDD1
J9
1.2-V Core Power Supply
1.2-V Core Power Supply
1.2-V Core Power Supply
1.2-V Core Power Supply
1.2-V Core Power Supply
1.2-V Core Power Supply
1.2-V Core Power Supply
1.2-V Core Power Supply
1.2-V Core Power Supply
1.2-V Core Power Supply
1.2-V Core Power Supply
1.2-V Core Power Supply
1.2-V Core Power Supply
1.2-V Core Power Supply
1.2-V Core Power Supply
1.2-V Core Power Supply
1.2-V Core Power Supply
1.2-V Core Power Supply
1.2-V Core Power Supply
1.2-V Core Power Supply
1.2-V Core Power Supply
1.2-V Core Power Supply
1.2-V Core Power Supply
1.2-V Core Power Supply
1.2-V Core Power Supply
1.2-V Core Power Supply for Ethernet Subsystem
1.2-V Core Power Supply for Ethernet Subsystem
1.8-V I/O supply
J11
J15
K10
K12
K14
L9
L11
L13
L15
M10
M12
M14
N11
N13
N15
P10
P12
P14
R13
N9
T16
R8
R15
V8
R11
R9
B10
B22
H9
1.8-V I/O supply
1.2-V Power supply for DDR, DDR I/Os, EMIF-DDR
Subsystem
CVDD1
J13
1.2-V Power supply for DDR, DDR I/Os, EMIF-DDR
Subsystem
AVDDA
AVDDA
DVDDD
DVDDD
AVDDR
AVDDT
AVDDT
DVDD33
DVDD33
DVDD33
DVDD33
DVDD33
V11
W10
T10
U10
AB10
AB8
U11
E22
F20
G1
1.2-V SerDes Analog supply
1.2-V SerDes Analog supply
1.2-V SerDes Digital Supply
1.2-V SerDes Digital Supply
1.8-V SerDes Analog Supply (Regulator)
1.2-V SerDes Analog Supply
1.2-V SerDes Analog Supply
3.3-V I/O supply voltage
3.3-V I/O supply voltage
3.3-V I/O supply voltage
G19
J7
3.3-V I/O supply voltage
3.3-V I/O supply voltage
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Table 2-5. Terminal Functions (Ground and Power Supply) (continued)
TERMINAL
NAME
NO
TYPE
INTERNAL
PULLUP/
OPER
VOLT
DESCRIPTION
PULLDOWN
DVDD33
DVDD33
DVDD33
DVDD33
DVDD33
DVDD33
DVDD33
DVDD33
DVDD33
DVDD33
DVDD33
DVDD33
DVDD33
DVDD33
DVDD33
DVDD33
DVDD33
DVDD33
DVDD33
DVDD33
DVDD33
DVDD33
DVDD33
DVDD33
DVDD33
DVDD33
DVDD33
DVDD33
DVDD33
DVDD33
DVDD33
DVDD33
DVDD33
DVDD33
DVDD33
DVDD18
DVDD18
DVDD18
DVDD18
DVDD18
DVDD18
DVDD18
DVDD18
DVDD18
DVDD18
DVDD18
H16
H22
J17
K8
3.3-V I/O supply voltage
3.3-V I/O supply voltage
3.3-V I/O supply voltage
3.3-V I/O supply voltage
K16
L7
3.3-V I/O supply voltage
3.3-V I/O supply voltage
L17
M8
3.3-V I/O supply voltage
3.3-V I/O supply voltage
M16
M23
N2
3.3-V I/O supply voltage
3.3-V I/O supply voltage
3.3-V I/O supply voltage
N7
3.3-V I/O supply voltage
N17
P8
3.3-V I/O supply voltage
3.3-V I/O supply voltage
P16
R7
3.3-V I/O supply voltage
3.3-V I/O supply voltage
R17
T8
3.3-V I/O supply voltage
3.3-V I/O supply voltage
T12
T14
T23
AB7
U15
U17
V2
3.3-V I/O supply voltage
3.3-V I/O supply voltage
3.3-V I/O supply voltage
3.3-V I/O supply voltage
3.3-V I/O supply voltage
3.3-V I/O supply voltage
3.3-V I/O supply voltage
V16
W23
Y4
3.3-V I/O supply voltage
3.3-V I/O supply voltage
3.3-V I/O supply voltage
Y8
3.3-V I/O supply voltage
AB16
AC2
AC5
AB12
AC19
AC23
B1
3.3-V I/O supply voltage
3.3-V I/O supply voltage
3.3-V I/O supply voltage
3.3-V I/O supply voltage
3.3-V I/O supply voltage
3.3-V I/O supply voltage
1.8-V I/O supply voltage (DDR2 Memory Controller)
1.8-V I/O supply voltage (DDR2 Memory Controller)
1.8-V I/O supply voltage (DDR2 Memory Controller)
1.8-V I/O supply voltage (DDR2 Memory Controller)
1.8-V I/O supply voltage (DDR2 Memory Controller)
1.8-V I/O supply voltage (DDR2 Memory Controller)
1.8-V I/O supply voltage (DDR2 Memory Controller)
1.8-V I/O supply voltage (DDR2 Memory Controller)
1.8-V I/O supply voltage (DDR2 Memory Controller)
1.8-V I/O supply voltage (DDR2 Memory Controller)
1.8-V I/O supply voltage (DDR2 Memory Controller)
B5
B15
B18
B23
C3
C10
C13
C21
E5
F8
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Table 2-5. Terminal Functions (Ground and Power Supply) (continued)
TERMINAL
NAME
NO
TYPE
INTERNAL
PULLUP/
OPER
VOLT
DESCRIPTION
PULLDOWN
DVDD18
DVDD18
DVDD18
DVDD18
DVDD18
DVDD18
DVDD18
DVDD18
DVDD18
DVDD18
DVDD18
DDR_VREF
F14
F16
F18
G9
1.8-V I/O supply voltage (DDR2 Memory Controller)
1.8-V I/O supply voltage (DDR2 Memory Controller)
1.8-V I/O supply voltage (DDR2 Memory Controller)
1.8-V I/O supply voltage (DDR2 Memory Controller)
1.8-V I/O supply voltage (DDR2 Memory Controller)
1.8-V I/O supply voltage (DDR2 Memory Controller)
1.8-V I/O supply voltage (DDR2 Memory Controller)
1.8-V I/O supply voltage (DDR2 Memory Controller)
1.8-V I/O supply voltage (DDR2 Memory Controller)
1.8-V I/O supply voltage (DDR2 Memory Controller)
1.8-V I/O supply voltage (DDR2 Memory Controller)
G11
G13
G15
G17
H10
H12
H14
C11
(DVDD18/2)-V reference for SSTL buffer (DDR2 Memory
Controller0. This input voltage cn be generated directly from
DVDD18 using two 1-KΩ resistors to form a resister divider
circuit.
VCCMON
VDD18MON
VDD33MON
L19
B2
Die-side 1.2-V core supply voltage monitor pin. The monitor
pins indicate the voltage on the die, and, therefore, provide the
best probe point for voltage monitoring purposes. If the VCCMON
pin is not used, it should be connected directly to the 1.2-V
core supply.
Die-side 1.8-V I/O supply voltage monitor pin. The monitor pins
indicate the voltage on the die and, therefore, provide the best
probe point for voltage monitoring purposes. If the VDD18MON
pin is not used, it should be connected directly to the 1.8-V I/O
supply (DVDD18).
G21
Die-side 3.3-V I/O supply voltage monitor pin. The monitor pins
indicate the voltage on the die and, therefore, provide the best
probe point for voltage monitoring purposes. If the VDD33MON
pin is not used, it should be connected directly to the 3.3-V I/O
supply (DVDD33).
Reserved
RSV 1
RSV 2
RSV 3
RSV 4
RSV 5
RSV 6
RSV 7
L20
L21
D2
D1
D4
D3
H7
A
A
Reserved. Unconnected
Reserved. Unconnected
Reserved. Unconnected
Reserved. Unconnected
Reserved. Unconnected
Reserved. Unconnected
O
O
O
O
A
Reserved. These pins must be connected directly to VSS for
proper device operation.
RSV 8
H8
A
Reserved. These pins must be connected directly to VSS for
proper device operation.
RSV 9
RSV 10
RSV 11
M2
A2
E2
A
A
Reserved. Unconnected
Reserved. Unconnected
Reserved This pin must be connected directly to VSS for proper
device operation.
RSV 12
RSV 13
RSV 14
RSV 15
E1
E4
Reserved. This pin must be connected directly to 1.8-V I/O
supply
Reserved This pin must be connected directly to VSS for proper
device operation.
E3
Reserved. This pin must be connected directly to 1.8-V I/O
supply
A10
A
Reserved. Unconnected
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Table 2-5. Terminal Functions (Ground and Power Supply) (continued)
TERMINAL
NAME
NO
TYPE
INTERNAL
PULLUP/
OPER
VOLT
DESCRIPTION
PULLDOWN
RSV 16
RSV 17
RSV 18
A22
V10
F6
A
A
I
Reserved. Unconnected
Reserved. Unconnected
Reserved. These pins must be connected directly to 1.8-V I/O
supply(DVDD18) for proper device operation.
RSV 19
C2
Reserved. This pin must be connected to the 1.8-V I/O supply
(DVDD18) via a 200-Ω resistor for proper device operation.
NOTE: If the DDR2 Memory Controller is not used, the
DDR_VREF, RSV19, and RSV20 pins can be directly
connected to ground (VSS) to save power. However,
connecting these pins directly to ground will prevent boundary
scan from functioning on the DDR2 Memory Controller pins. To
preserve boundary-scan functionality on the DDR2 Memory
Controller pins, see Section 6.3.6.
RSV 20
C1
Reserved. This pin must be connected to ground (VSS) via a
200-Ω resistor for proper device operation.
NOTE: If the DDR2 Memory Controller is not used, the RSV 19
and RSV 20 pins can be directly connected to ground (VSS) to
save power. However, connecting these pins directly to ground
will prevent boundary scan from functioning on the DDR2
Memory Controller pins. To preserve boundary-scan
functionality on the DDR2 Memory Controller pins, see
Section 6.3.6.
RSV 21
RSV 22
Y12
Reserved. This pin must be connected via a 20-Ω resistor
directly to 3.3-V I/O Supply (DVDD33) for proper device
operation. The resistor used should have a minimal rating of
250 mW.
W12
Reserved. This pin must be connected via a 40-Ω resistor
directly to ground (VSS) for proper device operation. The
resistor used should have a minimal rating of 100 mW.
2.7 Device Support
2.7.1 Development Support
TI offers an extensive line of development tools for the TMS320DM64x DMP platform, including tools to
evaluate the performance of the processors, generate code, develop algorithm implementations, and fully
integrate and debug software and hardware modules. The tools support documentation is electronically
available within the Code Composer Studio™ Integrated Development Environment (IDE).
The following products support development of TMS320DM64xx DMP-based applications:
Software Development Tools:
Code Composer Studio™ Integrated Development Environment (IDE): including Editor
C/C++/Assembly Code Generation, and Debug plus additional development tools
Scalable, Real-Time Foundation Software (DSP/BIOS™), which provides the basic run-time target
software needed to support any SoC application.
Hardware Development Tools:
Extended Development System (XDS™) Emulator (supports TMS320DM64x multiprocessor system
debug) EVM (Evaluation Module)
For a complete listing of development-support tools for the TMS320DM64x platform, visit the Texas
Instruments website at www.ti.com. For information on pricing and availability, contact the nearest TI
field sales office or authorized distributor.
2.7.2 Device and Development-Support Tool Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all
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DSP devices and support tools. Each DSP commercial family member has one of three prefixes: TMX,
TMP, or TMS (e.g., TMS320DM648ZUTA7). Texas Instruments recommends two of three possible prefix
designators for its support tools: TMDX and TMDS. These prefixes represent evolutionary stages of
product development from engineering prototypes (TMX/TMDX) through fully qualified production
devices/tools (TMS/TMDS).
Device development evolutionary flow:
TMX
TMP
TMS
Experimental device that is not necessarily representative of the final device's electrical
specifications.
Final silicon die that conforms to the device's electrical specifications but has not completed
quality and reliability verification.
Fully-qualified production device.
Support tool development evolutionary flow:
TMDX
Development-support product that has not yet completed Texas Instruments internal
qualification testing.
TMDS
Fully qualified development-support product.
TMX and TMP devices and TMDX development-support tools are shipped against the following
disclaimer:
"Developmental product is intended for internal evaluation purposes."
TMS devices and TMDS development-support tools have been characterized fully, and the quality and
reliability of the device have been demonstrated fully. TI's standard warranty applies.
Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard
production devices. Texas Instruments recommends that these devices not be used in any production
system because their expected end-use failure rate still is undefined. Only qualified production devices are
to be used.
TI device nomenclature also includes a suffix with the device family name. This suffix indicates the
package type (for example, ZUT), the temperature range (for example, "Blank" is the commercial
temperature range), and the device speed range in megahertz (for example, "Blank" is the default
[720-MHz]).
Figure 2-6 provides a legend for reading the complete device name for the devices.
( ) (7)
TMS
320 DM648
ZUT
DEVICE SPEED RANGE
PREFIX
7
8
9
1
= 720 MHz
= 800 MHZ
= 900 MHZ
= 1.1 GHz
TMX = Experimental device
TMS = Qualified device
DEVICE FAMILY
TEMPERATURE RANGE
Blank
320 = TMS320 DSP family
= 0° C to 90° C, Commercial Temperature (720, 900, 1100)
= -40° C to 105° C, Extended Temperature (800)
= -40° C to 90° C, Industrial Temperature (720, 900, 1100)
A
D
DEVICE
C64x+
DSP
DM647
DM648
PACKAGE TYPE
ZUT = 520-pin plastic ball grid array (BGA)
Figure 2-6. Device Nomenclature
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2.7.3 Related Documentation From Texas Instruments
The following documents describe the devices. Copies of these documents are available on the Internet at
www.ti.com. Tip: Enter the literature number in the search box provided at www.ti.com.
The current documentation that describes the DM64x DMP, related peripherals, and other technical
collateral, is available in the C6000 DSP product folder at: www.ti.com/c6000.
SPRU732
TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide describes the CPU
architecture, pipeline, instruction set, and interrupts for the TMS320C64x and TMS320C64x+
digital signal processors (DSPs) of the TMS320C6000 DSP family. The C64x/C64x+ DSP
generation comprises fixed-point devices in the C6000 DSP platform. The C64x+ DSP is an
enhancement of the C64x DSP with added functionality and an expanded instruction set.
SPRUEK5 TMS320DM647/DM648 DSP DDR2 Memory Controller User's Guide describes the DDR2
memory controller in the TMS320DM647/DM648 Digital Signal Processor (DSP). The
DDR2/mDDR memory controller is used to interface with JESD79D-2A standard compliant
DDR2 SDRAM devices and standard Mobile DDR SDRAM devices.
SPRUEK6 TMS320DM647/DM648 DSP External Memory Interface (EMIF) User's Guide describes
the operation of the asynchronous external memory interface (EMIF) in the
TMS320DM647/DM648 Digital Signal Processor (DSP). The EMIF supports a glueless
interface to a variety of external devices.
SPRUEK7 TMS320DM647/DM648 DSP General-Purpose Input/Output (GPIO) User's Guide
describes the general-purpose input/output (GPIO) peripheral in the TMS320DM647/DM648
Digital Signal Processor (DSP). The GPIO peripheral provides dedicated general-purpose
pins that can be configured as either inputs or outputs. When configured as an input, you
can detect the state of the input by reading the state of an internal register. When configured
as an output, you can write to an internal register to control the state driven on the output
pin.
SPRUEK8 TMS320DM647/DM648 DSP Inter-Integrated Circuit (I2C) Module User's Guide describes
the inter-integrated circuit (I2C) peripheral in the TMS320DM647/DM648 Digital Signal
Processor (DSP). The I2C peripheral provides an interface between the DSP and other
devices compliant with the I2C-bus specification and connected by way of an I2C-bus.
External components attached to this 2-wire serial bus can transmit and receive up to 8-bit
wide data to and from the DSP through the I2C peripheral. This document assumes the
reader is familiar with the I2C-bus specification.
SPRUEL0 TMS320DM647/DM648 DSP 64-Bit Timer User's Guide describes the operation of the
64-bit timer in the TMS320DM647/DM648 Digital Signal Processor (DSP). The timer can be
configured as a general-purpose 64-bit timer or dual general-purpose 32-bit timers.
SPRUEL1 TMS320DM647/DM648 DSP Multichannel Audio Serial Port (McASP) User's Guide
describes the multichannel audio serial port (McASP) in the TMS320DM647/DM648 Digital
Signal Processor (DSP). The McASP functions as a general-purpose audio serial port
optimized for the needs of multichannel audio applications. The McASP is useful for
time-division multiplexed (TDM) stream, Inter-Integrated Sound (I2S) protocols, and
intercomponent digital audio interface transmission (DIT).
SPRUEL2 TMS320DM647/DM648 DSP Enhanced DMA (EDMA) Controller User's Guide describes
the operation of the enhanced direct memory access (EDMA3) controller in the
TMS320DM647/DM648 Digital Signal Processor (DSP). The EDMA3 controller’s primary
purpose is to service user-programmed data transfers between two memory-mapped slave
endpoints on the DSP.
SPRUEL4 TMS320DM647/DM648 DSP Peripheral Component Interconnect (PCI) User's Guide
describes the peripheral component interconnect (PCI) port in the TMS320DM647/DM648
Digital Signal Processor (DSP). The PCI port supports connection of the C642x DSP to a
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PCI host via the integrated PCI master/slave bus interface. The PCI port interfaces to the
DSP via the enhanced DMA (EDMA) controller. This architecture allows for both PCI master
and slave transactions, while keeping the EDMA channel resources available for other
applications.
SPRUEL5 TMS320DM647/DM648 DSP Host Port Interface (UHPI) User's Guide describes the host
port interface (HPI) in the TMS320DM647/DM648 Digital Signal Processor (DSP). The HPI is
a parallel port through which a host processor can directly access the CPU memory space.
The host device functions as a master to the interface, which increases ease of access. The
host and CPU can exchange information via internal or external memory. The host also has
direct access to memory-mapped peripherals. Connectivity to the CPU memory space is
provided through the enhanced direct memory access (EDMA) controller.
SPRUEL8 TMS320DM647/DM648 DSP Universal Asynchronous Receiver/Transmitter (UART)
User's Guide describes the universal asynchronous receiver/transmitter (UART) peripheral
in the TMS320DM647/DM648 Digital Signal Processor (DSP). The UART peripheral
performs serial-to-parallel conversion on data received from a peripheral device, and
parallel-to-serial conversion on data received from the CPU.
SPRUEL9 TMS320DM647/DM648 DSP VLYNQ Port User's Guide describes the VLYNQ port in the
TMS320DM647/DM648 Digital Signal Processor (DSP). The VLYNQ port is a high-speed
point-to-point serial interface for connecting to host processors and other VLYNQ compatible
devices. It is a full-duplex serial bus where transmit and receive operations occur separately
and simultaneously without interference.
SPRUEM1 TMS320DM647/DM648 DSP Video Port/VCXO Interpolated Control (VIC) Port User's
Guide discusses the video port and VCXO interpolated control (VIC) port in the
TMS320DM647/DM648 Digital Signal Processor (DSP). The video port can operate as a
video capture port, video display port, or transport channel interface (TCI) capture port. The
VIC port provides single-bit interpolated VCXO control with resolution from 9 bits to up to 16
bits. When the video port is used in TCI mode, the VIC port is used to control the system
clock, VCXO, for MPEG transport channel.
SPRUEM2 TMS320DM647/DM648 DSP Serial Port Interface (SPI) User's Guide discusses the Serial
Port Interface (SPI) in the TMS320DM647/DM648 Digital Signal Processor (DSP). This
reference guide provides the specifications for a 16-bit configurable, synchronous serial
peripheral interface. The SPI is a programmable-length shift register, used for high speed
communication between external peripherals or other DSPs.
SPRUEU6 TMS320DM647/DM648 DSP Subsystem User's Guide describes the subsystem in the
TMS320DM647/DM648 Digital Signal Processor (DSP). The subsystem is responsible for
performing digital signal processing for digital media applications. The subsystem acts as the
overall system controller, responsible for handling many system functions such as
system-level initialization, configuration, user interface, user command execution,
connectivity functions, and overall system control.
SPRUF57 TMS320DM647/DM648 DSP 3 Port Switch (3PSW) Ethernet Subsystem User's Guide
describes the operation of the 3 port switch (3PSW) ethernet subsystem in the
TMS320DM647/DM648 Digital Signal Processor (DSP). The 3 port switch gigabit ethernet
subsystem provides ethernet packet communication and can be configured as an ethernet
switch (DM648 only). It provides the serial gigabit media independent interface (SGMII), the
management data input output (MDIO) for physical layer device (PHY) management.
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3 Device Configuration
3.1 System Module Registers
The system module includes status and control registers required for configuration of the device. Brief
descriptions of the various registers are shown in Table 3-1. System Module registers required for device
configuration are described in the following sections.
Table 3-1. System Module Register Memory Map
HEX ADDRESS RANGE
0x0204 9000
REGISTER NAME
PINMUX
DESCRIPTION
Pin multiplexing control 0
Reserved
0x0204 9004
Reserved
0x0204 9008
DSPBOOTADDR
BOOTCMPLT
Boot Address of DSP, decoded by bootloader software for host boots
0x0204 900C
0x0204 9010
Boot Complete
Reserved
0x0204 9014
BOOTCFG
JTAGID
Device boot configuration
0x0204 9018
Device ID number. See Section 6.25 for details.
Bus master priority control. See Section 4 for details
Reserved
0x0204 901C
0x0204 9020 -0x0204 9053
0x0204 9054
PRI_ALLOC
Reserved
KEY_REG
Reserved
Key Register to protect against accidental writes.
Reserved
0x0204 9060 - 0x0204 90A7
0x0204 90A8
CFGPLL
CFGPLL inputs for SerDes
Reserved
0x0204 90AC
0x0204 90B0
Reserved
(1)
CFGRX0
Configure SGMII0 RX
(1)
0x0204 90B4
CFGRX1
Configure SGMII1 RX
0x0204 90B8
CFGTX0
Configure SGMII0 TX.(1)
(1)
0x0204 90BC
0x0204 90C0
0x0204 90C4
0x0204 90C8
0x0204 90CC
0x0204 90D0
0x0204 90D4
CFGTX1
Configure SGMII1 TX
Reserved
Reserved
MAC_ADDR_R0
MAC_ADDR_R1
MAC_ADDR_RW0
MAC_ADDR_RW0
ESS_LOCK
MAC Address Read Only Register 0
MAC Address Read Only Register 1
MAC Address Read/Write Register 0
MAC Address Read/Write Register 1
Ethernet Sub System Lock Register
(1) See the TMS320DM647/DM648 DSP Ethernet Subsystem User's Guide Reference Guide (literature number SPRUF57) for details.
38
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3.2 Bootmode Registers
The BOOTCFG and DSPBOOTADDR registers are described in the following sections. At reset, the status
levels of various pins required for proper boot are stored within these registers.
3.2.1 Boot Configuration (BOOTCFG) Register
Configuration pins latched at reset are presented in the BOOTCFG register accessible through the system
module. This is a read-only register. The bits show the true latched value of the corresponding input at
RESET or POR deassertion. This is desirable since the most important use of this MMR is for the user to
debug/view the actual value driven on the pins during device reset.
Figure 3-1. BOOTCFG Register
31
24
Reserved
R-0
23
22
21
HPIWIDTH
R-L
20
Reserved
19
FASTBOOT
R-L
18
17
DUHPIEN
R-L
16
EMIFAWIDTH
R-L
AECLKINSEL
PC166
Reserved
15
8
Reserved
R-0
7
4
3
0
Reserved
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
BOOTMODE
R-L
Table 3-2. BOOTCFG Register Field Descriptions
Bit
Field
Value Description
Reserved
31:24 Reserved
23
22
21
AECLKINSEL
Controls the clock input for EMIFA. Latched from AECLKINSEL at RESET or POR deassertion
1
0
EMIFA clocked from internal SYSCLK
EMIFA clocked from outside from AECLKIN
PCI66
Controls PCI speed. PCI. Latched from PCI66 at RESET or POR deassertion
0
1
33 MHz PCI
66 MHz
HPIWIDTH
Controls HPI bus width. Latched from HPIWIDTH at RESET or POR deassertion
0
1
1
16 bit
32 bit
20
19
Reserved
Reserved
FASTBOOT
Fast Boot. Latched from FASTBOOT at RESET or POR deassertion
0
1
No Fast Boot
Fast Boot
18
17
Reserved
DUHPIEN
Reserved
PCI Enable Default. Latched from UHPIEN at RESET or POR deassertion
0
1
UHPI disabled
UHPI enabled
16
EMIFAWIDTH
Reserved
EMIFA CS2 Bus Width Default. Latched from EMIFAWIDTH at RESET or POR deassertion
0
1
8-bit
16-bit
15:4
Reserved
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Table 3-2. BOOTCFG Register Field Descriptions (continued)
Bit
Field
Value Description
3:0
BOOTMODE
Boot Mode. Latched from Bootmode at RESET or POR deassertion
Table 3-3. Boot Modes
DEVICE BOOT AND
CONFIGURATION PINS
DM647, DM648
(MASTER/SLAVE)
DSPBOOTADDR
(DEFAULT)
(2)
BOOT DESCRIPTION(1)
BOOTMODE[3:0]
UHPIEN
FASTBOOT
0 or 1
0000
0 or 1
No boot (emulation boot)
PCI boot no auto-initialization
HPI boot
-
0x0080 0000
0x0080 0000
0x0080 0000
0x0080 0000
0x0080 0000
0x0080 0000
0xA000 0000
0x0080 0000
0x0080 0000
0x0080 0000
0x0080 0000
0x0080 0000
0
1
Slave
Slave
Slave
Slave
Slave
Master
Master
Master
Master
-
0001
1
0
0 or 1
1
PCI boot with auto-initialization
HPI boot
0010
0011
0100
1
0 or 1
0
0 or 1
UART boot with no hardware flow control
EMIFA ROM direct boot (PLL bypass mode)
EMIFA ROM AIS boot
0
0 or 1
1
0101
0110
0111
1000
0 or 1
0 or 1
0 or 1
0 or 1
0 or 1
0 or 1
0 or 1
0 or 1
I2C Boot (standard mode)
SPI boot
Reserved
SGMII0 - Boot port, no packet forwarding
Slave
SGMII0 - Boot port, SGMII1 packet
forwarding (reserved in DM647)
1001
1010
0 or 1
0 or 1
0 or 1
0 or 1
Slave
Slave
0x0080 0000
0x0080 0000
SGMII1 - Boot port, SGMII0 packet
forwarding (reserved in DM647)
1011
1100
1101
0 or 1
0 or 1
0 or 1
0 or 1
0 or 1
0 or 1
Reserved
Reserved
Reserved
-
-
-
0x0080 0000
0x0080 0000
0x0080 0000
UART Boot with hardware flow control
[UART0]
1110
1111
0 or 1
0 or 1
0
Slave
-
0x0080 0000
0x0080 0000
0 or 1
Reserved
(1) In all bootmodes other than EMIFA ROM Direct Boot (BOOTMODE[3:0] = 0100b, UHPIEN = 0b or 1b, FASTBOOT = 0b) all C64x+
cache is disabled (L1P,L1D,L2).
(2) For details of the boot process, see Using the TMS320DM647 Bootloader Application Report (literature number SPRAAJ1).
3.2.2 DSPBOOTADDR Register Description
The DSPBOOTADDR register contains the upper 22 bits of the C64x+ DSP reset vector. The register
format is shown in Figure 3-2 and bit field descriptions are shown in Table 3-4. DSPBOOTADDR is
readable and writable by software after reset. DSPBOOTADDR Decode: This decode logic determines the
default of the DSPBOOTADDR Register. It can default to the base address of L2 ROM (0x00800000) or
the base address of EMIFA CS2 (0xA0000000).
Figure 3-2. DSPBOOTADDR Register
31
10
9
0
BOOTADDR
Reserved
R-0
R/W-0100 0010 0010 0000 0000 00
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 3-4. DSPBOOTADDR Register Field Descriptions
Bit
Field
Value Description
31:10 BOOTADDR
Upper 22 bits of the C64x+ DSP bootmode address
Reserved
9:0
Reserved
40
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3.2.3 Boot Complete (BOOTCMPLT) register
The BOOTCMPLT register contains a BC (boot complete) field in bit 0, and a ERR (boot error) field in bits
19:16.
The BC field is written by the external host to indicates that it has completed boot. In the bootloader code,
the CPU can poll for this bit. Once this bit = 1, the CPU can begin executing from DSPBOOTADDR.
The ERR field is written by the bootloader software if the software detects a boot error. Coming out of a
boot, application software can read this field to determine if boot was accomplished. Actual error code is
determined by software.
Figure 3-3. BOOTCMPLT Register 3
31
15
20
19
16
Reserved
R-0
ERR
R-0
1
0
Reserved
R-0
BC
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 3-5. BOOTCMPLT Register Field Descriptions
Bit
Field
Value
Description
Reserved
Boot error
No error
31:20 Reserved
19:16 ERR
0000
0001 – 1111
Bootloader software detected boot error. For details on boot errors, see the Using the
TMS320DM647/DM648 Bootloader Application Report (literature number SPRAAJ1).
15:1
0
Reserved
BC
Reserved
Boot Complete Flag from host. This is applicable only to host boots.
Host has not completed booting this device.
0
1
Host has completed booting this device and the DSP can begin executing from
DSPBOOTADDR.
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3.2.4 Priority Allocation (PRI_ALLOC)
Each of the masters (excluding the C64x+ Megamodule) is assigned a priority via the Priority Allocation
Register (PRI_ALLOC), see Figure 3-4. The priority is enforced when several masters in the system are
vying for the same endpoint. A value of 000b has the highest priority, while 111b has the lowest priority.
Note that the configuration SCR port on the data SCR is considered a single endpoint meaning priority will
be enforced when multiple masters try to access the configuration SCR. Priority is also enforced on the
configuration SCR side when a master (through the data SCR) tries to access the same endpoint as the
C64x+ Megamodule.
The Ethernet Subsystem and VLYNQ fields specify the priority of the Ethernet Subsystem and VLYNQ
peripherals, respectively. Similarly, the HOST field applies to the priority of the HPI and PCI peripherals.
Other master peripherals are not present in the PRI_ALLOC register as they have their own registers to
program their priorities. For more information on the default priority values in these peripheral registers,
see the device-compatible peripheral reference guides.
TI recommends that these priority registers be reprogrammed during device initialization.
Table 3-6. Default Master Priorities
MASTER
DEFAULT PRIORITY
EDMA3TC0
EDMA3TC1
EDMA3TC2
EDMA3TC3
64x+_DMAP
64x+_CFGP
Ethernet Subsystem
VLYNQ
0 (EDMA CC QUEPRI Register)
0 (EDMA CC QUEPRI Register)
0 (EDMA CC QUEPRI Register)
0 (EDMA CC QUEPRI Register)
7 (C64x+ MDMAARBE.PRI Register bit field)
1 (C64x+ MDMAARBE.PRI Register bit field)
3 (PRI_ALLOC register)
4 (PRI_ALLOC register)
UHPI
4 (PRI_ALLOC register)
PCI
4 (PRI_ALLOC register)
VICP
5 (PRI_ALLOC register)
Figure 3-4. Priority Allocation Register (PRI_ALLOC)
31
16
0
Reserved
R-0000000000001000
15
12
11
9
8
6
5
3
2
Reserved
R-0000
VICP
VLYNQ
HOST
Ethernet Subsystem
R/W-011
R/W-101
R/W-100
R/W-100
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
42
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3.2.5 KEY_REG (write protection)
KEY_REG protects against accidental writes to certain system configuration registers. The complete set of
registers protected by the KEY_REG is:
•
•
•
•
•
•
•
•
•
•
PINMUX
BOOTCFG
PRI_ALLOC
CFGPLL
CFGRX0
CFGTX0
CFGRX1
CFGTX1
MAC_ADDR_RW0
MAC_ADDR_RW1
Writes to these registers are locked/blocked by default. To enable writes to these registers, write
0xADDDECAF to the KEY_REG. After enabling writes to protected registers by doing the above, the
register writes should occur within 10000 CPU/6 cycles, after which the key will be reset.
Figure 3-5. KEY_REG
31
0
KEY_REG
W-0x00000000
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
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3.2.6 PINMUX Register
All pin multiplexing options are controlled by software via PINMUX register (except the ones mentioned in
Table 3-8, whose default is selected by configuration pins). This PINMUX register reside within the system
module portion of the CFG bus memory map. The format of the registers and a description of the pins
they control are in the following sections.
The PINMUX Register controls all the software-controlled pin muxing. The register format is shown in
Figure 3-6. A brief description of each field is shown in Table 3-7.
Figure 3-6. PINMUX Register
31
15
22
21
GPIO_EN
R/W-00
20
19
Reserved
R-00
18
17
VPI_EN
R/W-00
16
Reserved
R-0000 0000 00
14
13
12
11
Reserved
R-00
10
9
8
7
6
5
4
3
1
0
TIMER
_EN
VP34_EN
SPI_UART_EN
MCASP_EN
Reserved
R-00
VLYNQ_EN
R/W-00
Reserved
R-000
R/W-00
R/W-00
R/W-00
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 3-7. PINMUX Register Field Descriptions
Bit
Field
Value Description
31:22 Reserved
21:20 GPIO_EN
Reserved
Controls the pin muxing between Video Port 0 and the GPIO[12:15]
(2)
UNMUXED(1)
.VP0D16-19
3-state
UNMUXED
VP0D02-09/CLK/CTL
3-state
SECONDARY MUXED(3)
VP0D12-15 GP12-15
00
01
10
11
3-state
3-state
3-state
3-state
Enable
Enable
VP0D12-15
GP12-15
3-state
Enable
19:18 Reserved
17:16 VP1_EN
Reserved
Controls the pin muxing between Video Port 1 and GPIO[16:31]
UNMUXED(4)
(5)
MUXED
VP1CLK0-
1/VP1CTL0-2
VP1 Data
(V1D02-09/12-19)
GP[16-31]
00
01
10
11
3-state
3-state
3-state
Enable
3-state
3-state
GP16-31
VP1D02-09 and VP1D12-19
(1) The complete list of pins: U20, U21, U22, R18.
(2) The complete list of pins: Y23, V23, Y22, V22, U23, W20, V18, U18, V19, W21, T18, U19, V20.
(3) The complete list of pins: V21, T19, T20, T21.
(4) The complete list of pins: P23, N23, R23, P22, N22
(5) The complete list of pins: R19, P19, P18, R22, R21, R20, N21, N20, N19, P21, P20, M20, M18, N18, M21, M19
44
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Table 3-7. PINMUX Register Field Descriptions (continued)
Bit
Field
Value Description
(6)
15:14 VP34_EN
Controls the pin muxing between Video Port 3-4 and EMIFA
UNMUXED(7)
MUXED(8)
VP4D05/VP4CLK1
VP3/VP4
EMIFA
00
01
10
11
3-state
3-state
3-state
3-state
Disable
Enable
EMIFA
VP3/VP4
13:12 SPI_UART_EN
Controls the pin muxing between SPI and UART
(9)
(10)
UNMUXED
MUXED
SPI or UART
3-state
SPICLK
3-state
Enable
Disable
Enable
00
01
10
11
SPI
UART
SPIDI
SPIDO
UART_TX
UART_RX
11:10 Reserved
Reserved
(6) The value of VP34_EN depends on the BOOTMODE[3:0] pin value at reset. If the BOOTMODE[3:0] is 0100, the VP3/4 and the EMIFA
mux defaults to EMIFA enable (the value is 10b).
(7) The complete list of pins: K1, M6.
(8) The complete list of pins: T1, P1, T2, R1, P2, T6, T5, T4, T3, R6, R5, R4, R3, R2, P6, P5, P4, P3, N4, N6, N5, L1, J2, J1, K2, L2, M4,
M5, L3, L4, L5, K3, K4, L6, K5, J3, J4, J5, J6, K6.
(9) The complete list of pin:F22
(10) The complete list of pins: D23, F23, G23, F21
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Table 3-7. PINMUX Register Field Descriptions (continued)
Bit
Field
Value Description
9:8
MCASP_EN
Controls the pin muxing between McASP and VIC
UNMUXED
(11)
MUXED
STCLK, VCTL, or McASP
3-state
00
01
10
McASP (all McASP Pins)
(McASP without AXR8, AXR9)
ACLKR
AFSR
AXR0
AXR1
AC:LKX
AFSX
AXR2
AXR3
AHCLKR
AMUTEIN
AXR4
AXR5
AHCLKX
AMUTE
AXR6
AXR7
STCLK
VCTL
11
Reserved
7:6
5:4
Reserved
Reserved
VLYNQ_EN
Controls the pin muxing between Video Port 2 and VLYNQ
UNMUXED(12)
MUXED(13)
VP2#2 VLYNQ
VP2#1
00
01
10
11
3-state
3-state
3-state
3-state
Enable
VP2D12-19, VP2CLK1, VP2CTL2
Enable
VRXD0-3 and VTXD0-3, VCLK, VSCRUN
3:1
0
Reserved
Reserved
Controls the pin muxing between TIMER and GPIO[8:11]
TIMER_EN
MUXED(14)
GPIO[8:11]
Timer 0/1
0
1
(11) The complete list of pins: AC4, AC3, AC6, AC7, W6, AA7, AB6, Y6, AA6, AB4, Y5, V7, AA4, V6, Y7, AA5, AB3, U7
(12) For the first half of the Video Port 2, the complete list of pins with function: AB1(VP2CLK0), AA1 (VP2CTL0), AB2 (VP2CTL1) and W5,
AA2, Y3, U6, Y2, W3, V5, W4 (VP2D02, VP2D03, VP2D04, VP2D05, VP2D06, VP2D07, VP2D08, VP2D09)
(13) For the second half of the Video Port 2, the complete list of pins with function: W1 (VP2CLK1/VCLK), Y1(VP2CTL2/VSCRUN), W2, V3,
V4, U1, U3, U2, U5, U4 (VP2D12/VRXD0, VP2D13/VRXD1, VP2D14/VRXD2, VP2D15/VRXD3, VP2D16/VTXD0, VP2D17/VTXD1,
VP2D18/VTXD2, VP2D19/VTXD3)
(14) The complete list of pins:E20, D21, E21, C22
46
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Table 3-8. PCI/UHPI/GPIO Block: PCI MUXed With UHPI and GPIO[0:7]
MUXED(1)
PCI
UHPI/GPIO[0:7]
UHPIEN (pin)
1
0
UHPI/GPIO[0:7]
PCI
(1) The complete list of pin:AA22, AB22, AC21, AA23, AC22, AB21, AA21, Y21, AB20, AA20, Y20, Y19, AB18, AA19, AC18, AA18, Y16,
AB15, AA15, Y15, W15, V15, AC14, AB14, W14, V14, AC13, AB13, AA13, Y13 , W13, V13, W19, Y18, Y17, W17, W18, AC20, AC17,
W16, Y14, AC15, AA16, AB17, U13, U12, V12, AA12, AA17, AA14.
For information on the Ethernet Subsystem registers, see the TMS320DM647/DM648 DSP Subsystem
Reference Guide (literature number SPRUEU6).
3.2.7 MAC Address Registers
•
•
•
•
MAC_ADDR_R0
MAC_ADDR_R1
MAC_ADDR_RW0
MAC_ADDR_RW1
Two sets of registers provide default MAC addresses for the device. One set - MAC_ADDR_R0 and
MAC_ADDR_R1 - is read only and the other set - MAC_ADDR_RW0 and MAC_ADDR_RW1 - includes
read and write registers.
Figure 3-7. MAC_ADDR_R0 Register
31
0
MAC_ID
R-MAC ADDRESS[31:0]
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 3-9. MAC_ADDR_R0 Register Field Descriptions
Bit
Field
Value
Description
31:0
MAC_ID
Mac
Bit 0 of MAC_ID is bit 0 of MAC Address
Address[31:0] of
the device
Figure 3-8. MAC_ADDR_R1 Register
31
15
24
23
16
0
CRC
Reserved
R-CRC for the MAC_ID
R-00000000
MAC_ID
R-MAC ADDRESS[47:32]
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 3-10. MAC_ADDR_R1 Register Field Descriptions
Bit
Field
Value
Description
31:24 CRC
CRC of the MAC This field will hold the CRC of the MAC address of that particular device.
ID
23:16 Reserved
0x00
Reserved
15:0
MAC_ID
Mac
Bit 0 of MAC_ID is Bit 32 of MAC Address
Address[47:32] of
the device
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Figure 3-9. MAC_ADDR_RW0 Register
31
0
MAC_ADDR_R0
R/W - MAC ID[31:0]
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 3-11. MAC_ADDR_RW0 Register Field Descriptions
Bit
Field
Value
Description
Bit 0 of MAC_ID is bit 0 of MAC Address
31:0
MAC_ID
Mac
Address[31:0] of
the device
Figure 3-10. MAC_ADDR_RW1 Register
31
15
24
23
16
0
CRC
Reserved
R/W-CRC for the MAC_ID
R/W-00000000
MAC_ID
R-MAC ADDRESS[47:32]
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 3-12. MAC_ADDR_RW1 Register Field Descriptions
Bit
Field
Value
Description
31:24 CRC
CRC of the
MAC ID
This field will hold the CRC of the MAC address of that particular device.
23:16 Reserved
0x00
Reserved
15:0
MAC_ID
Mac
Bit 0 of MAC_ID is Bit 32 of MAC Address
Address[47:32]
of the device
48
Device Configuration
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3.3 Pullup/Pulldown Resistors
Proper board design should specify that input pins to the device always be at a valid logic level and not
floating. This may be achieved via pullup/pulldown resistors. The device features internal pullup (IPU) and
internal pulldown (IPD) resistors on most pins to eliminate the need, unless otherwise noted, for external
pullup/pulldown resistors.
An external pullup/pulldown resistor must be used in the following situations:
•
Boot and Configuration Pins: If the pin is both routed out and in high-impedance mode, an external
pullup/pulldown resistor must be used, even if the IPU/IPD matches the desired value/state.
•
Other Input Pins: If the IPU/IPD does not match the desired value/state, use an external
pullup/pulldown resistor to pull the signal to the opposite rail.
If the boot and configuration pins are both routed out and in high-impedance mode, it is recommended
that an external pullup/pulldown resistor be used. Although internal pullup/pulldown resistors exist on
these pins and they may match the desired configuration value, providing external connectivity can help
specify that valid logic levels are latched on these important boot configuration pins. In addition, applying
external pullup/pulldown resistors on the boot and configuration pins adds convenience to the user in
debugging and flexibility in switching operating modes.
Tips for choosing an external pullup/pulldown resistor:
•
•
Select a resistor with the largest possible resistance
Calculate the worst-case leakage current that flows through this external resistor. Worst-case leakage
current can be calculated by adding up all the leakage current at the pin—e.g., the input current (II)
from the device, and leakage current from the other device(s) to which this pin is connected.
•
Specify that the voltage at the pin stays well within the low-/high-level input voltages (VIL or VIH) when
worst-case leakage current is flowing through this external resistor.
–
–
To oppose an IPU and pull the signal to a logic low, the voltage at the pin must stay well below VIL.
To oppose an IPD and pull the signal to a logic high, the voltage at the pin must stay well above
VIH.
For most systems, a 1-kΩ resistor can be used to oppose the IPU/IPD while meeting the above criteria.
Users should confirm this resistor value is correct for their specific application.
For most systems, a 20-kΩ resistor can be used to complement the IPU/IPD on the boot and configuration
pins while meeting the above criteria. Users should confirm this resistor value is correct for their specific
application.
For more detailed information on input current (II), and the low-/high-level input voltages (VIL and VIH) , see
Section 5.3, Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating
Temperature.
For the internal pullup/pulldown resistors for all device pins, see the peripheral/system-specific terminal
functions table.
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Device Configuration
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4 System Interconnect
The C64x+ Megamodule, the EDMA3 transfer controllers, and the system peripherals are interconnected
through two switch fabrics. The switch fabrics allow for low-latency, concurrent data transfers between
master peripherals and slave peripherals. Through a switch fabric, the CPU can send data to the video
ports without affecting a data transfer between the PCI and the DDR2 memory controller. The switch
fabrics also allow for seamless arbitration between the system masters when accessing system slaves.
4.1 Internal Buses, Bridges, and Switch Fabrics
Two types of buses exist in the device: data buses and configuration buses. Some device peripherals
have both a data bus and a configuration bus interface, while others only have one type of interface.
Furthermore, the bus interface width and speed varies from peripheral to peripheral. Configuration buses
are mainly used to access the register space of a peripheral and the data buses are used mainly for data
transfers. However, in some cases, the configuration bus is also used to transfer data. For example, data
is transferred to the UART or I2C via their configuration bus. Similarly, the data bus can also be used to
access the register space of a peripheral. For example, the EMIFA and DDR2 memory controller registers
are accessed through their data bus interface.
The C64x+ Megamodule, the EDMA3 traffic controllers, and the various system peripherals can be divided
into two categories: masters and slaves. Masters are capable of initiating read and write transfers in the
system and do not rely on the EDMA3 for their data transfers. Slaves, on the other hand, rely on the
EDMA3 to perform transfers to and from them. Masters include the EDMA3 traffic controllers and PCI.
Slaves include the McASP, video ports, and I2C.
The device contains two switch fabrics through which masters and slaves communicate. The data switch
fabric, known as the data switched central resource (SCR), is a high-throughput interconnect mainly used
to move data across the system (for more information, see Section 4.2). The data SCR connects masters
to slaves via 128-bit data buses running at a SYSCLK1 frequency (SYSCLK1 is generated from PLL1
controller). Peripherals that have a 128-bit data bus interface running at this speed can connect directly to
the data SCR; other peripherals require a bridge.
The configuration switch fabric, also known as the configuration switch central resource (SCR) is mainly
used by the C64x+ Megamodule to access peripheral registers (for more information, see Section 4.3).
The configuration SCR connects the C64x+ Megamodule to slaves via 32-bit configuration buses running
at a SYSCLK1 frequency (SYSCLK1 is generated from the PLL1 controller). As with the data SCR, some
peripherals require the use of a bridge to interface to the configuration SCR. Note that the data SCR also
connects to the configuration SCR. Bridges perform a variety of functions:
•
•
•
Conversion between configuration bus and data bus.
Width conversion between peripheral bus width and SCR bus width
Frequency conversion between peripheral bus frequency and SCR bus frequency
For example, the EMIFA memory controller require a bridge to convert their 64-bit data bus interface into a
128-bit interface so that they can connect to the data SCR.
Some peripherals can be accessed through the data SCR and also through the configuration SCR.
4.2 Data Switch Fabric Connections
Figure 4-1 shows the connection between slaves and masters through the data switched central resource
(SCR). Masters are shown on the right and slaves on the left. The data SCR connects masters to slaves
via 128-bit data buses running at a SYSCLK1 frequency. SYSCLK1 is supplied by the PLL1 controller and
is fixed at a frequency equal to the CPU frequency divided by 3. Some peripherals, like PCI and the
C64x+ Megamodule, have both slave and master ports. Each EDMA3 transfer controller has an
independent connection to the data SCR.
Masters can access the configuration SCR through the data SCR. The configuration SCR is described in
Section 4.3.
50
System Interconnect
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Not all masters on the device may connect to all slaves. Allowed connections are summarized in
Table 4-1.
128 SYSCLK1
S
Megamodule
M
M
128 SYSCLK1
128 SYSCLK1
S
0
S
1
M0
DDR2
Memory
Controller
128 SYSCLK1
EDMA3 M1
Transfer
S
S
2
128 SYSCLK1
128 SYSCLK1
Controller
M2
128
SYSCLK1
64
SYSCLK1
S
3
M3
M
S
EMIFA
Bridge
64
SYSCLK1
64
SYSCLK1
128 SYSCLK1
32 SYSCLK3
S
S
S
S
Video Port 0
Megamodule
M
64
SYSCLK1
S
Video Port 1
M
Bridge
32 SYSCLK3
32 SYSCLK3
64
SYSCLK1
HPI
M
M
M
S
S
Video Port 2
Video Port 3
128 SYSCLK1
Bridge
PCI
64
SYSCLK1
64
SYSCLK1
VLYNQ
32 SYSCLK3
32 TXBCLK
128 SYSCLK1
64
SYSCLK1
Bridge
M
128 SYSCLK1
3-port Gigabit
Ethernet Switch
S
Video Port 4
M
Bridge
128 SYSCLK1
32
SYSCLK3
32
SYSCLK3
S
PCI
32
SYSCLK3
Bridge
M
S
VLYNQ
128 SYSCLK1
32
SYSCLK1
128
SYSCLK1
S
Config SCR
Bridge
M
Figure 4-1. Data SCR
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Table 4-1. Connectivity Matrix for Data SCR
MEGAMODULE
DDR2 EMIF
EMIFA
VIDEO
PORT 0-2 PORT 3-4
VIDEO
PCI
VLYNQ
Configuration
SCR
TC0
Y
Y
Y
Y
N
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
N
N
N
N
N
Y
Y
Y
Y
N
N
N
N
N
Y
Y
Y
N
Y
Y
Y
Y
N
Y
Y
Y
N
Y
Y
Y
Y
N
Y
Y
Y
N
N
Y
Y
Y
N
TC1
TC2
TC3
Megamodule
HPI
PCI
VLYNQ
Ethernet Subsystem
4.3 Configuration Switch Fabric
Figure 4-2 shows the connection between the C64x+ megamodule and the configuration SCR, which is
mainly used by the C64x+ Megamodule to access peripheral registers. The data SCR also has a
connection to the configuration SCR that allows masters to access most peripheral registers. The only
registers not accessible by the data SCR through the configuration SCR are the device configuration
registers and the PLL1 and PLL2 controller registers; these can be accessed only by the C64x+
Megamodule. The configuration SCR uses 32-bit configuration buses running at SYSCLK1 frequency.
SYSCLK1 is supplied by the PLL1 controller and is fixed at a frequency equal to the CPU frequency
divided by 3.
52
System Interconnect
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32-bit
32-bit
SYSCLK1
TXBCLK
Ethernet
SubSystem
Config SCR
M
Bridge
S
32-bit
SYSCLK1
32-bit
S
S
Video Port 0
Video Port 1
Video Port 2
Video Port 3
SYSCLK1
32-bit
SYSCLK1
32-bit
SYSCLK1
M
Bridge
S
32-bit
SYSCLK1
S
S
32-bit
128-bit
SYSCLK1
SYSCLK1
Video Port 4
UART
32-bit
SYSCLK3
S
S
32-bit
SYSCLK3
I2C
32-bit
SYSCLK3
S
S
Timer 0
Timer 1
Timer 2
Timer 3
32-bit
SYSCLK3
32-bit
SYSCLK3
S
S
32-bit
SYSCLK3
32-bit SYSCLK1
S
32-bit
Megamodule
M
M
SYSCLK3
32-bit
PSC
S
S
SYSCLK3
32-bit
32-bit SYSCLK1
SYSCLK3
S
S
Data SCR
VICP
PLL Controllers
PCI
M
Bridge
32-bit
32-bit
32-bit
SYSCLK3
SYSCLK3
SYSCLK1
S
S
Bridge
M
32-bit
SYSCLK3
32-bit
SYSCLK1
McASP
SPI
32-bit
SYSCLK3
S
32-bit
SYSCLK3
S
S
VIC
32-bit
SYSCLK3
GPIO
32-bit
SYSCLK3
S
S
VICP CFG
HPI
32-bit
SYSCLK3
32-bit
SYSCLK1
S
S
EDMA3 CC
EDMA3 TC0
32-bit
32-bit
SYSCLK1
SYSCLK1
32-bit
SYSCLK1
S
S
EDMA3 TC1
EDMA3 TC2
M
Bridge
32-bit
SYSCLK1
32-bit
32-bit
SYSCLK1
S
SYSCLK1
EDMA3 TC3
Figure 4-2. Configuration SCR
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System Interconnect
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5 Device Operating Conditions
5.1 Absolute Maximum Ratings
Over Operating Temperature Range (Unless Otherwise Noted)(1)
Supply voltage ranges:
Core (CVDD, CVDDESS, CVDD1, AVDDA
,
1.20-V operation
-0.5 V to 1.5 V
(2)
DVDDD, AVDDT
)
(2)
I/O, 3.3V (DVDD33
)
-0.5 V to 4.2 V
-0.5 to 2.5 V
(2)
I/O, 1.8V (DVDD18, AVDLL1, AVDLL2, AVDDR
VI I/O, 3.3-V pins
VI I/O, 1.8 V
)
Input voltage ranges:
-0.5 V to 4.2 V
-0.5 V to 2.5 V
-0.5 V to 4.2 V
-0.5 V to 2.5 V
0°C to 90°C
Output voltage ranges:
VO I/O, 3.3-V pins
VO I/O, 1.8 V
Operating case temperature, Tcase
Commercial
Extended
-40°C to 105°C
-40°C to 90°C
-65°C to 150°C
Industrial
Storage temperature range, Tstg
(default)
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to VSS.
54
Device Operating Conditions
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5.2 Recommended Operating Conditions
MIN
NOM
MAX
UNIT
(1)
CVDD
Supply voltage, Core
(1)
CVDDESS
CVDD1
AVDDA
DVDDD
AVDDT
Supply voltage, Ethernet Subsystem Core
(1)
Supply voltage, DDR Core
(-720, -800, -900,
-1100 devices)
1.14
1.2
1.26
V
(1)
Supply voltage, SerDes Analog
(1)
Supply voltage, SerDes Digital
(1)
Supply voltage, SerDes Analog
DVDD33
DVDD18
AVDLL1
AVDLL2
AVDDR
VSS
Supply voltage, I/O, 3.3 V
Supply voltage, DDR I/O, 1.8 V
Supply voltage, I/O, 1.8 V
Supply voltage, I/O, 1.8 V
3.14
1.71
3.3
1.8
3.46
1.89
V
V
Supply voltage, 1.8-V SerDes Analog Supply (Regulator)
Supply ground (VSS
)
0
0.49DVDD18
2
0
0
V
V
V
V
V
DDR_VREF
DDR2 reference voltage(2)
0.5DVDD18
0.51DVDD18
High-level input voltage, 3.3 V (except PCI-capable and I2C pins)
High-level input voltage, I2C
0.7DVDD33
0.5DVDD33
VIH
PCI-capable pins
DVDD33 + 0.5
DVDD18 + 0.3
DDR_VREF +
0.125
DDR2 memory controller pins (DC)
V
Low-level input voltage, 3.3 V(except PCI-capable and I2C pins)
Low-level input voltage, I2C
0.8
V
V
V
V
0
-0.5
-0.3
0
0.3DVDD33
VIL
PCI-capable pins
0.3DVDD33
DDR2 memory controller pins (DC)
Commercial
DDR_VREF - 0.125
(3)
90
105
90
Tcase
Operating case temperature
Extended(4)
-40
°C
Industrial
-40
(-1100 devices)(3)
(-900 devices)
(-720 devices)
(-800 devices)
33.3
33.3
33.3
33.3
1100
900
720
800
MHz
MHz
MHz
MHz
FSYSCLK1
DSP Operating Frequency (SYSCLK1)
(1) Future variants of TI SOC devices may operate at voltages ranging from 0.9 V to 1.4 V to provide a range of system power/performance
options. TI highly recommends that users design-in a supply that can handle multiple voltages within this range (i.e., 1.0 V, 1.05 V,
1.1 V, 1.14 V, 1.2, 1.26 V with ± 3% tolerances) by implementing simple board changes such as reference resistor values or input pin
configuration modifications. Not incorporating a flexible supply may limit the system ability to easily adapt to future versions of TI SOC
devices.
(2) DDR_VREF is expected to equal 0.5DVDDR2 of the transmitting device and to track variations in the DVDD18
.
(3) To avoid significant device degradation for 1.1GHz devices, the device power-on hours (POH) must be limited to less than 87.6K.
(4) To avoid significant device degradation for extended temperature devices (- 40°C ≤ Tcase ≤ 105°C), the device power-on hours (POH)
must be limited to less than 50K.
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5.3 Electrical Characteristics
Over Recommended Ranges of Supply Voltage and Operating Temperature (Unless Otherwise Noted)
(1)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
3.3-V pins (except PCI-capable
and I2C pins)
DVDD33 = MIN, IOH = MAX
0.8DVDD33
V
VOH High-level
output voltage
PCI-capable pins(2)
DVDD33 = 3.3V, IOH = -0.5 mA
DVDD33 = MIN, IOL = MAX
0.9DVDD33
1.4
DDR2 memory controller pins
3.3-V pins (except PCI-capable
and I2C pins)
0.22DVDD33
VOL Low-level
output voltage
PCI-capable pins(2)
I2C pins
DVDD33 = 3.3V, IOL = 1.5 mA
0.1DVDD33
0.4
Pulled up to 3.3 V, 3 mA sink current
DDR2 memory controller pins
0.4
V
VI = VSS to DVDD33 without internal pullup oe
pulldown resistor
-1
50
1
400
-50
mA
3.3-V pins (except PCI-capable VI = VSS to DVDD33 with internal pullup resistor
100
mA
mA
(2)
and I2C pins)
II Input current [dc]
VI = VSS to DVDD33 with opposing internal
-400
-100
(2)
pulldown resistor
Input current [dc] (I2C)
PCI-capable pins(4)
0.1DVDD33 ≤ VI ≤ 0.9DVDD33
-10
10
mA
mA
-600
600
IOH High-level
output current [dc] and PCI
All peripherals other than DDR2
-8
mA
DDR2 memory controller pins
-4
mA
mA
PCI-capable pins(2)
-0.5
IOL Low-level
output current [dc] , PCI and I2C
All peripherals other than DDR2
8
mA
I2C pins
3
4
mA
mA
mA
DDR2 memory controller pins
PCI-capable pins(2)
3.3-V pins
1.5
IOZ I/O Off-state
output current [DC]
-20
20
mA
CVDD = 1.2-V, DSP clock = 720 MHz
CVDD = 1.2-V, DSP clock = 800 MHz
CVDD = 1.2-V, DSP clock = 900 MHz
CVDD = 1.2-V, DSP clock = 1100 MHz
2497
2605
2741
3013
mA
mA
mA
mA
Core (CVDD, VDDA_1P1V) supply
current(3)
ICDD
3.3-V I/O (DVDD33) supply
current(3)
DVDD = 3.3-V, DSP clock = 720 MHz, 800 MHz,
900 MHz, 1100 MHz
227
mA
1.8-V I/O (DVDDR2
,
IDDD
DDR_VDDDLL, PLLVPRW18
VDDA_1P8V, MXVDD) supply
current(3)
,
DVDD = 1.8-V, DSP clock = 720 MHz, 800 MHz,
900 MHz, 1100 MHz
311
mA
CI
Input capacitance
Output capacitance
10
10
pF
pF
Co
(1) For test conditions shown as MIN, MAX, or NOM, use the appropriate value specified in the recommended operating conditions table.
(2) Applies only to pins with an internal pullup (IPU) or pulldown (IPD) resistor.
(3) Assumes the following conditions: 50% DSP CPU utilization; (peripheral configurations, other housekeeping activities) DDR2 at 50%
utilization (266 MHz ), 50% writes, 32 bits, 100% bit switching, 110-MHz Video Ports at 100% utilization, MCASP operating at 25 Mhz
with 100% utilization with 10 serializers, Timer0,1 at 100% utilization, VICP with 100% utilization, PCI operating at 66 Mhz with 50%
writes at room temp (25°C) using ZUT package. (as in the power appnote) for the three items.
56
Device Operating Conditions
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6 Peripheral Information and Electrical Specifications
6.1 Parameter Information
Tester Pin Electronics
Data Sheet Timing Reference Point
42 Ω
3.5 nH
Output
Under
Test
Transmission Line
Z0 = 50 Ω
(see Note)
Device Pin
(see Note)
4.0 pF
1.85 pF
NOTE: The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its transmission line effects must
be taken into account. A transmission line with a delay of 2 ns can be used to produce the desired transmission line effect. The transmission
line is intended as a load only. It is not necessary to add or subtract the transmission line delay (2 ns) from the data sheet timings.
Input requirements in this data sheet are tested with an input slew rate of < 4 Volts per nanosecond (4 V/ns) at the device pin.
Figure 6-1. Test Load Circuit for AC Timing Measurements
The load capacitance value stated is only for characterization and measurement of ac timing signals. This
load capacitance value does not indicate the maximum load the device is capable of driving.
6.1.1 3.3-V Signal Transition Levels
All input and output timing parameters are referenced to Vref for both 0 and 1 logic levels. For 3.3-V I/O,
Vref = 1.5 V. For 1.8-V I/O, Vref = 0.9 V.
V
ref
Figure 6-2. Input and Output Voltage Reference Levels for ac Timing Measurements
All rise and fall transition timing parameters are referenced to VIL MAX and VIH MIN for input clocks,
VOLMAX and VOH MIN for output clocks.
V
ref
= V MIN (or V MIN)
IH OH
V
ref
= V MAX (or V MAX)
IL OL
Figure 6-3. Rise and Fall Transition Time Voltage Reference Levels
6.1.2 3.3-V Signal Transition Rates
All timings are tested with an input edge rate of 4 volts per nanosecond (4 V/ns).
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6.1.3 Timing Parameters and Board Routing Analysis
The timing parameter values specified in this data manual do not include delays caused by board routings.
As a good board design practice, such delays must always be taken into account. Timing values may be
adjusted by increasing/decreasing such delays. TI recommends utilizing the available I/O buffer
information specification (IBIS) models to analyze the timing characteristics correctly. To properly use IBIS
models to attain accurate timing analysis for a given system, see the Using IBIS Models for Timing
Analysis Application Report (literature number SPRA839). If needed, external logic hardware such as
buffers may be used to compensate for any timing differences.
For inputs, timing is most impacted by the round-trip propagation delay from the DSP to the external
device and from the external device to the DSP. This round-trip delay tends to negatively impact the input
setup time margin, but also tends to improve the input hold time margins (see Table 6-1 and Figure 6-4).
Figure 6-4 represents a general transfer between the DSP and an external device. The figure also
represents board route delays and how they are perceived by the DSP and the external device.
Table 6-1. Board-Level Timing Example
(see Figure 6-4)
NO.
1
DESCRIPTION
Clock route delay
2
Minimum DSP hold time
3
Minimum DSP setup time
External device hold time requirement
External device setup time requirement
Control signal route delay
External device hold time
4
5
6
7
8
External device access time
DSP hold time requirement
DSP setup time requirement
Data route delay
9
10
11
(Output from DSP)
1
(Input to External Device)
2
Control Signals(A)
(Output from DSP)
3
4
5
6
Control Signals
(Input to External Device)
7
8
Data Signals(B)
(Output from External Device)
9
10
Data Signals(B)
(Input to DSP)
11
A. Control signals include data for writes.
B. Data signals are generated during reads from an external device.
Figure 6-4. Board-Level Input/Output Timings
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6.2 Recommended Clock and Control Signal Transition Behavior
All clocks and control signals must transition between VIH and VIL (or between VIL and VIH) in a monotonic
manner.
6.3 Power Supplies
For more information regarding TI's power management products and suggested devices to power TI
DSPs, visit www.ti.com/dsppower.
6.3.1 Power-Supply Sequencing
The device includes 1.2-V core supply (CVDD, CVDDESS, CVDD1, AVDDA, DVDDD, AVDDT), and two I/O
supplies—3.3-V (DVDD33) and 1.8-V (DVDD18, AVDLL1, AVDLL2, AVDDR). To ensure proper device operation,
a specific power-up sequence must be followed. Some TI power-supply devices include features that
facilitate power sequencing — for example, Auto-Track and Slow-Start/Enable features. For more
information on TI power supplies and their features, visit www.ti.com/dsppower.
Following is a summary of the power sequencing requirements:
•
The power ramp order must be 3.3-V (DVDD33) before 1.8-V (DVDD18, AVDLL1, AVDLL2, AVDDR), and
1.8-V (DVDD18, AVDLL1, AVDLL2, AVDDR) before 1.2-V core supply (CVDD, CVDDESS, CVDD1, AVDDA
,
DVDDD, AVDDT) —meaning during power up, the voltage at the 1.8-V rail should never exceed the
voltage at the 3.3-V rail. Similarly, the voltage at the 1.2-V rail should never exceed the voltage at the
DVDDR2 rail.
•
From the time that power ramp begins, all power supplies (3.3 V, 1.8 V, 1.2 V) must be stable within
200 ms. The term "stable" means reaching the recommended operating condition (see Section 5.2).
6.3.2 Power-Supply Design Considerations
Core and I/O supply voltage regulators should be located close to the DSP to minimize inductance and
resistance in the power delivery path. Additionally, when designing for high-performance applications
utilizing the device, the PC board should include separate power planes for core, I/O, and ground; all
bypassed with high-quality low-ESL/ESR capacitors.
6.3.3 Power-Supply Decoupling
In order to properly decouple the supply planes from system noise, place as many capacitors (caps) as
possible close to the DSP. These caps need to be close to the DSP, no more than 1.25 cm maximum
distance to be effective. Physically smaller caps are better, such as 0402, but need to be evaluated from a
yield/manufacturing point-of-view. Parasitic inductance limits the effectiveness of the decoupling
capacitors; therefore physically smaller capacitors should be used while maintaining the largest available
capacitance value. Larger caps for each supply can be placed further away for bulk decoupling. Large
bulk caps (on the order of 100 mF) should be furthest away, but still as close as possible. Large caps for
each supply should be placed outside of the BGA footprint.
6.3.4 Power and Sleep Controller (PSC)
The power and sleep controller (PSC) controls power by turning off unused power domains or by gating
off clocks to individual peripherals/modules. The device uses the clock-gating feature of the PSC only for
power savings. The PSC consists of a global PSC (GPSC) and a set of local PSCs (LPSCs).
The GPSC contains memory mapped registers, PSC interrupt control, and a state machine for each
peripheral/module. An LPSC is associated with each peripheral/module and provides clock and reset
control. The LPSCs are shown in Table 6-2. The PSC register memory map is given in Table 6-3. For
more details on the PSC, see the TMS320DM647/TMS320DM648 DSP Subsystem Reference Guide
(literature number SPRUEU6).
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Table 6-2. LPSC Assignments
LPSC NUMBER
PERIPHERAL/ MODULE
EDMA3CC
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
DDR2 Memory Controller
UHPI
0
1
2
3
4
5
6
7
8
9
VLYNQ
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
GPIO
TIMER0
TIMER1
Reserved
Reserved
Reserved
Reserved
SPI
I2C
PCI
VP0
VP1
VP2
VP3
VP4
EMIFA
TIMER2
TIMER3
VIC
McASP
UART
VICP
Reserved
C64x+ CPU
Ethernet Subsystem
Table 6-3. PSC Register Memory Map
HEX ADDRESS RANGE
0x0204 6000
REGISTER ACRONYM
DESCRIPTION
PID
–
Peripheral Revision and Class Information Register
0x0204 6004- 0x0204 600F
0x0204 6010
Reserved
–
Reserved
0x0204 6014
Reserved
0x0204 6018
INTEVAL
Interrupt Evaluation Register
0x0204 601C- 0x0204 603F
0x0204 6040
–
Reserved
–
Reserved
0x0204 6044
MERRPR1
–
Module Error Pending 1 (mod 32- 63) Register
Reserved
0x0204 6048- 0x0204 604F
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Table 6-3. PSC Register Memory Map (continued)
HEX ADDRESS RANGE
0x0204 6050
REGISTER ACRONYM
DESCRIPTION
–
Reserved
0x0204 6054
MERRCR1
Module Error Clear 1 (mod 32 - 63) Register
Reserved
0x0204 6058- 0x0204 605F
0x0204 6060
–
–
Reserved
0x0204 6064- 0x0204 6067
0x0204 6068
–
Reserved
–
Reserved
0x0204 606C- 0x0204 611F
0x0204 6120
–
Reserved
PTCMD
Power Domain Transition Command Register
Reserved
0x0204 6124- 0x0204 6127
0x0204 6128
–
PTSTAT
Power Domain Transition Status Register
Reserved
0x0204 612C- 0x0204 61FF
0x0204 6200
–
PDSTAT0
Power Domain Status 0 Register (Always On)
Reserved
0x0204 6204- 0x0204 62FF
0x0204 6300
–
PDCTL0
Power Domain Control 0 Register (Always On)
Reserved
0x0204 6304- 0x1C4 150F
0x0204 6510
–
–
Reserved
0x0204 6514
–
Reserved
0x0204 6518- 0x0204 65FF
0x0204 6600- 0x0204 67FF
0x0204 6800
–
Reserved
–
Reserved
MDSTAT0
–
Module Status 0 Register (EDMACC)
Reserved
0x0204 6804
0x0204 6808
–
Reserved
0x0204 680C
–
Reserved
0x0204 6810
–
Reserved
0x0204 6814
–
Reserved
0x0204 6818
–
Reserved
0x0204 681C
MDSTAT7
MDSTAT8
MDSTAT9
MDSTAT10
MDSTAT11
MDSTAT12
–
Module Status 7 Register (DDR2)
Module Status 8 Register (HPI)
Module Status 9 Register (VLYNQ)
Module Status 10 Register (GPIO)
Module Status 11 Register (TIMER 0)
Module Status 12 Register (TIMER 1)
Reserved
0x0204 6820
0x0204 6824
0x0204 6828
0x0204 682C
0x0204 6830
0x0204 6834
0x0204 6838
–
Reserved
0x0204 683C
–
Reserved
0x0204 6840
–
Reserved
0x0204 6844
MDSTAT17
MDSTAT18
MDSTAT19
MDSTAT20
MDSTAT21
MDSTAT22
MDSTAT23
MDSTAT24
MDSTAT25
MDSTAT26
MDSTAT27
Module Status 17 Register (SPI)
Module Status 18 Register (I2C)
Module Status 19 Register (PCI)
Module Status 20 Register (Video Port 0)
Module Status 21 Register (Video Port 1)
Module Status 22 Register (Video Port 2)
Module Status 23 Register (Video Port 3)
Module Status 24 Register (Video Port 4)
Module Status 25 Register (EMIFA)
Module Status 26 Register (TIMER 2)
Module Status 27 Register (TIMER 3)
0x0204 6848
0x0204 684C
0x0204 6850
0x0204 6854
0x0204 6858
0x0204 685C
0x0204 6860
0x0204 6864
0x0204 6868
0x0204 686C
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Table 6-3. PSC Register Memory Map (continued)
HEX ADDRESS RANGE
0x0204 6870
0x0204 6874
0x0204 6878
0x0204 687C
0x0204 6880
0x0204 6884
0x0204 6888
0x0204 688C-0x0204 69FF
0x0204 6A00
0x0204 6A04
0x0204 6A08
0x0204 6A0C
0x0204 6A10
0x0204 6A14
0x0204 6A18
0x0204 6A1C
0x0204 6A20
0x0204 6A24
0x0204 6A28
0x0204 6A2C
0x0204 6A30
0x0204 6A34
0x0204 6A38
0x0204 6A3C
0x0204 6A40
0x0204 6A44
0x0204 6A48
0x0204 6A4C
0x0204 6A50
0x0204 6A54
0x0204 6A58
0x0204 6A5C
0x0204 6A60
0x0204 6A64
0x0204 6A68
0x0204 6A6C
0x0204 6A70
0x0204 6A74
0x0204 6A78
0x0204 6A7C
0x0204 6A80
0x0204 6A84
0x0204 6A88
0x0204 6A90- 0x0204 6FFF
REGISTER ACRONYM
MDSTAT28
MDSTAT29
MDSTAT30
MDSTAT31
–
DESCRIPTION
Module Status 28 Register (VIC)
Module Status 29 Register (McASP)
Module Status 30 Register (UART)
Module Status 31 Register (VICP)
Reserved
MDSTAT33
MDSTAT34
–
Module Status 33 Register (C64x+ CPU)
Module Status 34 Register (Ethernet Subsystem)
Reserved
MDCTL0
–
Module Control 0 Register (EDMACC)
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
–
Reserved
MDCTL7
MDCTL8
MDCTL9
MDCTL10
MDCTL11
MDCTL12
–
Module Control 7 Register (DDR2)
Module Control 8 Register (HPI)
Module Control 9 Register (VLYNQ)
Module Control 10 Register (GPIO)
Module Control 11 Register (TIMER 0)
Module Control 12 Register (TIMER 1)
Reserved
–
Reserved
–
Reserved
–
Reserved
MDCTL17
MDCTL18
MDCTL19
MDCTL20
MDCTL21
MDCTL22
MDCTL23
MDCTL24
MDCTL25
MDCTL26
MDCTL27
MDCTL28
MDCTL29
MDCTL30
MDCTL31
–
Module Control 17 Register (SPI)
Module Control 18 Register (I2C)
Module Control 19 Register (PCI)
Module Control 20 Register (Video Port 0)
Module Control 21 Register (Video Port 1)
Module Control 22 Register (Video Port 2)
Module Control 23 Register (Video Port 3)
Module Control 24 Register (Video Port 4)
Module Control 25 Register (EMIFA)
Module Control 26 Register (TIMER 2)
Module Control 27 Register (TIMER 3)
Module Control 28 Register (VIC)
Module Control 29 Register (McASP)
Module Control 30 Register (UART)
Module Control 31 Register (VICP)
Reserved
MDCTL33
MDCTL34
–
Module Control 33 Register (C64x+ CPU)
Module Control 34 Register (Ethernet Subsystem)
Reserved
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6.3.5 Power and Clock Domains
The device includes two power domains: the System Domain and the Ethernet Subsystem Domain. Both
of these power domains are always on when the chip is on. Both of these domains are powered by the
CVDD pins of the device.
The primary PLL controller generates the input clock to the C64x+ megamodule as well as most of the
system peripherals such as the multichannel audio serial ports (McASPs) and the external memory
interface (EMIFA). The secondary PLL controller generates interface clocks for the DDR2 memory
controller. The Ethernet Subsystem is clocked through the SerDes module, which takes input from
REFCLKP/N. The primary PLL controller (PLL1 controller) uses the device input clock CLKIN1 and the
secondary PLL controller (PLL2 controller) uses the device input clock CLKIN2.
Table 6-4 provides a listing of the clock domains.
Table 6-4. Power and Clock Domains
POWER DOMAIN
System Domain
System Domain
System Domain
System Domain
System Domain
System Domain
System Domain
System Domain
System Domain
System Domain
System Domain
System Domain
System Domain
System Domain
System Domain
System Domain
System Domain
System Domain
System Domain
System Domain
System Domain
System Domain
System Domain
System Domain
System Domain
System Domain
System Domain
System Domain
System Domain
Ethernet Subsystem Domain
CLOCK DOMAIN
CLKDIV1
CLKDIV3
CLKDIV3
CLKDIV3
CLKDIV3
CLKDIV3
CLKDIV3
CLKDIV3
CLKDIV3
CLKDIV6
CLKDIV6
CLKDIV6
CLKDIV6
CLKDIV6
CLKDIV6
CLKDIV6
CLKDIV6
CLKDIV6
CLKDIV6
CLKDIV6
CLKDIV6
CLKDIV6
CLKDIV6
CLKDIV6
CLKDIV6
CLKDIV4 0
CLKDIV4 1
CLKDIV4 2
CLKDIV2
SerDes TXBCLK
PERIPHERAL/MODULE/USAGE
C64x+ CPU
EDMA/SCR
DDR Subsystem
Video Port 0
Video Port 1
Video Port 2
Video Port 3
Video Port 4
EMIFA
HPI
PCI
VLYNQ
UART
I2C
TIMER 0
TIMER 1
TIMER 2
TIMER 3
SPI
McASP
VIC
GPIO
PLL Controller 1
PLL Controller 2
Config SCR
Internal EMIFA Clock
Emulation and Trace
VICP cop_clk/2
VICP cop_clk
Ethernet Subsystem
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The device architecture is divided into the power and clock domains shown in Table 6-5, which further
shows the clock domains and their ratios.
Table 6-5. Clock Domain Assignment
SUBSYSTEM
CLOCK DOMAIN
DOMAIN CLOCK SOURCE
FIXED RATIO vs SYSREFCLK
FREQUENCY
DSP Subsystem
CLKDIV1
CLKDIV3
PLLC1.REFSYSCLK
PLLC1.SYSCLK1
PLLC1.SYSCLK2
PLLC1.SYSCLK3
PLLC1.SYSCLK4
PLLC1.SYSCLK5
PLLC1.SYSCLK6
-
Peripherals (CLKDIV3 Domain)
Emulation/Trace
1:3
1:4
1:6
1:4(1)
1:4
1:2
CLKDIV4 1
CLKDIV6
Peripherals (CLKDIV6 Domain)
Internal EMIFA Clock
VICP cop_clk/2
CLKDIV4 0
CLKDIV4 2
CLKDIV2
VICP cop_clk
(1) There is a /2 divider in the path of PLLC1.SYSCLK4 so the effective EMIFA clock is PLLC1.SYSCLK4/2. By default the internal EMIFA
Clock is 1:8.
6.3.6 Preserving Boundary-Scan Functionality on DDR2 Memory Pins
Similarly, when the DDR2 Memory Controller is not used, the DDR_VREF, RSV19, and RSV20 pins can
be connected directly to ground (VSS) to save power. However, this will prevent boundary-scan from
functioning on the DDR2 Memory Controller pins. To preserve boundary-scan functionality on the DDR2
Memory Controller pins, DDR_VREF, RSV19, and RSV20 should be connected as follows:
•
DDR_VREF - connect to a voltage of DVDD18/2. The DVDD18/2 voltage can be generated directly from
the DVDD18 supply using two 1-kΩ resistors to form a resistor divider circuit.
•
•
RSV19 - connect this pin to the 1.8-V I/O supply (DVDD18) via a 200-Ω resistor
RSV20 - connect this pin to ground (VSS) via a 200-Ω resistor.
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6.4 PLL1 Controller
The primary PLL controller generates the input clock to the C64x+ megamodule (including the CPU) as
well as most of the system peripherals such as the multichannel audio serial ports (McASPs) and the
external memory interface (EMIFA). Figure 6-5 shows a functional block diagram of the PLL Input Clock.
+1.8 V
PLLV1
C2
560 pF 0.1
C1
EMI Filter
F
PLL1 Controller
PLL1
PLLEN (PLLCTL.[0])
SYSREFCLK
DIVIDER PREDIV
/1, /2, /3
PLLM
x1,
x16 to x32
CLKIN1
(C64x+ MegaModule)
DIVIDER D1
/3
1
0
ENA
SYSCLK1
PREDEN (PREDIV.[15])
DIVIDER D2
/1, /2,
..., /8
ENA
SYSCLK2
(Emulation and Trace)
D2EN (PLLDIV2.[15])
DIVIDER D3
/6
SYSCLK3
SYSCLK4
DIVIDER D4
/4 ... /8
/2
ENA
D4EN (PLLDIV4.[15])
(Internal
EMIF Clock
Input)
DIVIDER D5
/4
SYSCLK5
VICP cop_clk/2
DIVIDER D6
/2
SYSCLK6
VICP cop_clk
AECLKIN (External EMIF Clock Input)
VCLK
/1, /2,
..., /8
CLKDIV
(CTRL.[18:16])
0
1
AECLKINSEL
(AEA[17] pin)
1
0
CLKDIR
(CTRL.[15])
EMIFA
VLYNQ
(EMIF Input Clock)
AECLKOUT
SYSCLK5
Figure 6-5. PLL Input Clock
As shown in Figure 6-5, the PLL1 controller features a software-programmable PLL multiplier controller
(PLLM) and seven dividers (PREDIV, D1, D2, D3, D4, D5). The PLL1 controller uses the device input
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clock CLKIN1 to generate a system reference clock (SYSREFCLK) and system clocks (SYSCLK1,
SYSCLK2, SYSCLK3, SYSCLK4, SYSCLK5). PLL1 power is supplied externally via the PLL1
power-supply pin (PLLV1). An external EMI filter circuit must be added to PLLV1. The 1.8-V supply of the
EMI filter must be from the same 1.8-V power plane supplying the I/O power-supply pin, DVDD18. TI
requires EMI filter manufacturer Murata, part number NFM18CC222R1C3.
All PLL external components (C1, C2, and the EMI Filter) must be placed as close to the C64x+ DSP
device as possible. For the best performance, TI recommends that all the PLL external components be on
a single side of the board without jumpers, switches, or components other than the ones shown. For
reduced PLL jitter, maximize the spacing between switching signals and the PLL external components
(C1, C2, and the EMI Filter). The minimum CLKIN1 rise and fall times should also be observed. For the
input clock timing requirements, see Section 6.4.4.
6.4.1 PLL1 Controller Device-Specific Information
As shown in Figure 6-5, the PLL1 controller generates several internal clocks including the system
reference clock (SYSREFCLK), and the system clocks (SYSCLK1/2/3/4/5/6). The high-frequency clock
signal SYSREFCLK is directly used to clock the C64x+ megamodule (including the CPU) and also serves
as a reference clock for the rest of the DSP system. Dividers D1, D2, D3, D4, D5, and D6 divide the
high-frequency clock SYSREFCLK to generate SYSCLK1, SYSCLK2, SYSCLK3, SYSCLK4, SYSCLK5,
and SYSCLK6, respectively.
The system clocks are used to clock different portions of the DSP as follows:
•
SYSCLK1 is used for the following modules: 3PDMA, the SCR and the bridges, DDR Subsystem
internal logic, Video Port 0, Video Port 1, Video Port 2, Video Port 3, Video Port 4, EMIFA internal
logic.
•
•
SYSCLK2 is used for Emulation and Trace
SYSCLK3 is used for most of the peripherals. These modules are clocked from SYSCLK3: HPI, PCI,
VLYNQ, UART, I2C, TIMER 0, TIMER 1, TIMER 2, TIMER 3, SPI, McASP, VIC, GPIO, PLL Controller
1, PLL Controller 2, Config SCR
•
•
•
SYSCLK4 is used as the EMIFA AECLKOUT
SYSCLK5 is used as the VICP internal clock
SYSCLK6 is used as the VICP internal clock
The PLL multiplier controller (PLLM) must be programmed after reset. There is no hardware CLKMODE
selection on the device. Since the divider ratio bits for dividers D1, D3, D5, and D6 are fixed, the
frequency of SYSCLK1, SYCLK3, SYSCLK5, and SYSCLK6 is tied to the frequency of SYSREFCLK.
However, the frequency of SYSCLK2 and SYSCLK4 depends on the configuration of dividers D2 and D4.
For example, with PLLM in the PLL1 multiply control register set to 10011b (x20 mode) and a 35-MHz
CLKIN1 input, the PLL output PLLOUT is set to 700 MHz and SYSCLK1 and SYSCLK3 run at 233 MHz
and 117 MHz, respectively. Divider D4 can be programmed through the PLLDIV4 register to divide
SYSREFCLK by 8 (2 * (PLLDIV4.RATIO+1)) such that SYSCLK4 runs at 87.5 MHz.
Note that there is a minimum and maximum operating frequency for PLLREF, PLLOUT, and SYSCLK4.
The PLL1 Controller must not be configured to exceed any of these constraints (certain combinations of
external clock input, internal dividers, and PLL multiply ratios might not be supported). For the PLL clocks
input and output frequency ranges, see Table 6-6.
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Table 6-6. PLL1 Clock Frequency Ranges
CLOCK SIGNAL
MIN
25
MAX
66.6
UNIT
MHz
MHz
MHz
MHz
MHz
MHz
MHz
CLKIN1
PLLREF (PLLEN = 1)(1)
25
66.6
(1)
PLLOUT
400
720 (-720 devices)
800 (-800 devices)(2)
900 (-900 devices)
1100 (-1100 devices)
PLLOUT/ (2*(PLLDIV4.RATIO+1))(4)
400
400
400
1/16P(3)
SYSCLK4
(1) Only applies when the PLL1 Controller is set to PLL mode (PLLEN = 1 in the PLLCTL register). Based on CLKIN1 and PLLOUT, PLL1
multiplier factor ranges from x16 to x32.
(2) Only for Extended Temperature Range device (-800 MHz)
(3) P = 1/CPU clock frequency in ns
(4) PLLDIV4.RATIO =3
6.4.2 PLL1 Controller Operating Modes
The PLL1 controller has two modes of operation: bypass mode and PLL mode. The mode of operation is
determined by the PLLEN bit of the PLL control register (PLLCTL). In PLL mode, SYSREFCLK is
generated from the device input clock CLKIN1 using the divider PREDIV and the PLL multiplier PLLM. In
bypass mode, CLKIN1 is fed directly to SYSREFCLK.
All hosts (i.e., HPI) must hold off accesses to the DSP while the frequency of its internal clocks is
changing. A mechanism must be in place such that the DSP notifies the host when the PLL configuration
has completed.
6.4.3 PLL1 Stabilization, Lock, and Reset Times
The PLL stabilization time is the amount of time that must be allotted for the internal PLL regulators to
become stable after device power-up. The PLL should not be operated until this stabilization time has
finished.
The PLL reset time is the amount of wait time needed when resetting the PLL (writing PLLRST = 1) for the
PLL to properly reset, before bringing the PLL out of reset (writing PLLRST = 0). For the PLL1 reset time
value, see Table 6-7.
Table 6-7. PLL1 Stabilization, Lock, and Reset Times
MIN
TYP
MAX
UNIT
ms
PLL stabilization time
PLL lock time
150
2000 × C(1)
ms
PLL reset time
128 × C(1)
ms
(1) C = CLKIN1 cycle time in ns. For example, when CLKIN1 frequency is 50 MHz, use C = 20 ns.
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6.4.4 PLL1 Controller Input and Output Clock Electrical Data/Timing
Table 6-8. Timing Requirements for CLKIN1(1)(2) (see Figure 6-6)
720, 800, 900, 1100
NO.
PLL MODES(3)
UNIT
MIN
15
MAX
1
2
3
4
5
tc(CLKIN1)
tw(CLKIN1H)
tw(CLKIN1L)
tt(CLKIN1)
Cycle time, CLKIN1
40
ns
ns
ns
ns
ps
Pulse duration, CLKIN1 high
Pulse duration, CLKIN1 low
Transition time, CLKIN1
0.4C
0.4C
1.2
tJ(CLKIN1)
Period jitter, (peak-to-peak), CLKIN1
100
(1) The reference points for the rise and fall transitions are measured at 3.3-V VIL MAX and VIH MIN.
(2) C = CLKIN1 cycle time in ns. For example, when CLKIN1 frequency is 50 MHz, use C = 20 ns.
(3) The PLL1 multiplier factors (x1 [BYPASS], x16 to x32) further limit the MIN and MAX values for tc(CLKIN1). See Section 6.3.5 for
supported PLL1 multiplier factors.
1
5
4
2
CLKIN
3
4
Figure 6-6. CLKIN1 Timing
6.4.5 PLL1 Controller Register Description(s)
A summary of the PLL1 controller registers is shown in Table 6-9.
Table 6-9. PLL1 and Reset Controller Registers Memory Map
HEX ADDRESS RANGE
0x020E 0000
0x020E 00E4
0x020E 0100
0x020E 0110
0x020E 0114
0x020E 011C
0x020E 0138
0x020E 013C
0x020E 0140
0x020E 0144
0x020E 0150
REGISTER NAME
PID
DESCRIPTION
Peripheral Identification and Revision Information Register
Reset Type Register
RSTYPE
PLLCTL
PLL Controller 1 Operations Control Register
PLL Controller 1 Multiplier Control Register
PLL Pre-Divider Control Register
PLLM
PREDIV
PLLDIV2
PLLCMD
PLLSTAT
ALNCTL
DCHANGE
SYSTAT
PLL Controller 1 Control-Divider 2 Register (SYSCLK2)
PLL Controller 1 Command Register
PLL Controller 1 Status Register (Shows PLLC1 Status)
PLL Controller Clock Align Control Register
PLLDIV Ratio Change Status Register
PLL Controller 1 System Clock Status 1 Register (Indicates SYSCLK on/off
Status)
0x020E 0160
PLLDIV4
PLL Controller 1 Control-Divider 4 Register (SYSCLK4)
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6.5 PLL2 Controller
The secondary PLL controller generates interface clocks for the DDR2 memory controller.
As shown in Figure 6-7, the PLL2 controller features a PLL multiplier controller. The PLL multiplier is fixed
to a x20 multiplier rate. PLL2 power is supplied externally via the PLL2 power supply (PLLV2). An external
PLL filter circuit must be added to PLLV2 as shown in Figure 6-7. The 1.8-V supply for the EMI filter must
be from the same 1.8-V power plane supplying the I/O power-supply pin, DVDD18. TI requires EMI filter
manufacturer Murata, part number NFM18CC222R1C3.
+1.8 V
PLLV2
C161
C162
SYSCLK1 (From PLL Controller 1)
DDR2 Memory Controller
EMI Filter
560 pF 0.1 mF
CLKIN2
PLLREF
PLLOUT
PLL2
PLLM
x20
Figure 6-7. PLL Controller
All PLL external components (C161, C162, and the EMI Filter) should be placed as close to the C64x+
DSP device as possible. For the best performance, TI requires that all the PLL external components be on
a single side of the board without jumpers, switches, or components other than the ones shown. For
reduced PLL jitter, maximize the spacing between switching signals and the PLL external components
(C161, C162, and the EMI Filter). The minimum CLKIN2 rise and fall times should also be observed. For
the input clock timing requirements, see Section 6.5.3, PLL2 Controller Input Clock Electrical Data/Timing.
6.5.1 PLL2 Controller Device-Specific Information
As shown in Figure 6-7, the output of PLL2, PLLOUT, is directly fed to the DDR2 memory controller. This
clock is used by the DDR2 memory controller to generate DDR2CLKOUT and DDR2CLKOUTz. Note that,
internally, the data bus interface of the DDR2 memory controller is clocked by SYSCLK1 of the PLL1
controller.
Note that there is a minimum and maximum operating frequency for PLLREF and PLLOUT. The clock
generator must not be configured to exceed any of these constraints. For the PLL clocks input and output
frequency ranges, see Table 6-10.
Table 6-10. PLL2 Clock Frequency Ranges
CLOCK SIGNAL
PLLREF (CLKIN2 )
PLLOUT (DDR2 clock)
REQUIRED FREQUENCY
20 - 26.6
UNIT
MHz
MHz
400 - 533(1)
(1) This clock is the 2x of the DDR clock. The DDR PHY divides the clock down /2.
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6.5.2 PLL2 Controller Operating Modes
Unlike the PLL1 controller that can operate in bypass and a PLL mode, the PLL2 controller only operates
in PLL mode. PLL2 is unlocked only during the power-up sequence (see Section 6.7) and is locked by the
time the RESETSTAT pin goes high. It does not lose lock during any of the other resets.
6.5.3 PLL2 Controller Input Clock Electrical Data/Timing
Table 6-11. Timing Requirements for CLKIN2(1) (2) (see Figure 6-8)
720, 800, 900, 1100
NO.
PLL MODE x20
UNIT
MIN
37.5
0.4C
0.4C
MAX
50 ns
1
2
3
4
5
tc(CLKIN2)
tw(CLKIN2H)
tw(CLKIN2L)
tt(CLKIN2)
Cycle time, CLKIN2
Pulse duration, CLKIN2 high
Pulse duration, CLKIN2 low
Transition time, CLKIN2
ns
ns
1.2 ns
100 ps
tJ(CLKIN2)
Period jitter, (peak-to-peak) CLKIN2
(1) The reference points for the rise and fall transitions are measured at 3.3-V VIL MAX and VIH MIN.
(2) C = CLKIN2 cycle time in ns. For example, when CLKIN2 frequency is 25 MHz, use C = 40 ns.
1
5
4
2
CLKIN
3
4
Figure 6-8. CLKIN2 Timing
6.5.4 PLL2 Controller Register Description(s)
A summary of the PLL2 controller registers is shown in Table 6-12.
Table 6-12. PLL2 and Reset Controller Registers Memory Map
HEX ADDRESS RANGE
0x0212 0000
REGISTER NAME
PID
DESCRIPTION
Peripheral Identification and Revision Information Register
PLL Controller 2 Operations Control Register
PLL Controller 2 Multiplier Control Register
PLL Controller 2 Command Register
0x0212 0100
PLLCTL
0x0212 0110
PLLM
0x0212 0138
PLLCMD
PLLSTAT
0x0212 013C
PLL Controller 2 Status Register (Shows PLLC1 Status)
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6.6 Enhanced Direct Memory Access (EDMA3) Controller
The EDMA controller handles all data transfers between memories and the device slave peripherals on
the device. These data transfers include cache servicing, non-cacheable memory accesses,
user-programmed data transfers, and host accesses. These are summarized as follows:
•
•
•
Transfer to/from on-chip memories
–
–
DSP L1D memory
DSP L2 memory
Transfer to/from external storage
–
–
DDR2 SDRAM
Synchronous/Asynchronous EMIF (EMIFA)
Transfer to/from peripherals/hosts
–
–
–
–
–
–
–
–
VLYNQ
HPI
McASP
UART
Video Port 0/1/2/3/4
Timer 0/1/2/3
SPI
I2C
6.6.1 EDMA3 Channel Synchronization Events
The EDMA supports up to 64 EDMA channels that service peripheral devices and external memory.
Table 6-13 lists the source of EDMA synchronization events associated with each of the programmable
EDMA channels. The association of an event to a channel is fixed; each of the EDMA channels has one
specific event associated with it. These specific events are captured in the EDMA event registers (ER,
ERH) even if the events are disabled by the EDMA event enable registers (EER, EERH). For more
detailed information on the EDMA module and how EDMA events are enabled, captured, processed,
linked, chained, and cleared, etc., see the TMS320DM647/DM648 DSP Enhanced DMA (EDMA)
Controller User's Guide (literature number SPRUEL2).
Table 6-13. EDMA Channel Synchronization Events
TPCC
DEFAULT BINARY
DEFAULT EVENT
TPCC
DEFAULT BINARY
DEFAULT EVENT
CHANNEL EVENT#
CHANNEL EVENT #
0
1
0
1
000 0000
000 0001
000 0010
000 0011
000 0100
000 0101
000 0110
000 0111
000 1000
000 1001
000 1010
000 1011
000 1100
000 1101
000 1110
000 1111
HPI/PCI : DSPINT
TIMER0 : TINT0L
TIMER0 : TINT0H
TIMER2 : TINT2L
TIMER2 : TINT2H
TIMER3 : TINT3L
TIMER3 : TINT3H
VICP: IMXINT
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
010 0000
010 0001
010 0010
010 0011
010 0100
010 0101
010 0110
010 0111
010 1000
010 1001
010 1010
010 1011
010 1100
010 1101
010 1110
010 1111
VP2EVTYA
VP2EVTCbA
VP2EVTCrA
VP2EVTYB
VP2EVTCbB
VP2EVTCrB
VP3EVTYA
VP3EVTCbA
VP3EVTCrA
VP3EVTYB
VP3EVTCbB
VP3EVTCrB
ICREVT
2
2
3
3
4
4
5
5
6
6
7
7
8
8
VICP: VLCDINT
VICP: DSQINT
9
9
10
11
12
13
14
15
10
11
12
13
14
15
McASP: AXEVTE
McASP: AXEVTO
McASP: AXEVT
McASP: AREVTE
McASP: AREVTO
McASP: AREVT
ICXEVT
SPI: SPIXEVT
SPI: SPIREVT
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Table 6-13. EDMA Channel Synchronization Events (continued)
TPCC
DEFAULT BINARY
DEFAULT EVENT
TPCC
DEFAULT BINARY
DEFAULT EVENT
CHANNEL EVENT#
CHANNEL EVENT #
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
001 0000
001 0001
001 0010
001 0011
001 0100
001 0101
001 0110
001 0111
001 1000
001 1001
001 1010
001 1011
001 1100
001 1101
001 1110
001 1111
TIMER1 : TINT1L
TIMER1 : TINT1H
UART: URXEVT
UART: UTXEVT
VP0EVTYA
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
011 0000
011 0001
011 0010
011 0011
011 0100
011 0101
011 0110
011 0111
011 1000
011 1001
011 1010
011 1011
011 1100
011 1101
011 1110
011 1111
VP4EVTYA
VP4EVTCbA
VP4EVTCrA
VP4EVTYB
VP4EVTCbB
VP0EVTCbA
VP0EVTCrA
VP0EVTYB
VP4EVTCrB
GPIO : GPINT6
GPIO : GPINT7
GPIO : GPINT8
GPIO : GPINT9
GPIO : GPINT10
GPIO : GPINT11
GPIO : GPINT12
GPIO : GPINT13
GPIO : GPINT14
GPIO : GPINT15
VP0EVTCbB
VP0EVTCrB
VP1EVTYA
VP1EVTCbA
VP1EVTCrA
VP1EVTYB
VP1EVTCbB
VP1EVTCrB
6.6.2 EDMA Peripheral Register Description(s)
Table 6-14 lists the EDMA registers, their corresponding acronyms, and device memory locations.
Table 6-14. EDMA Channel Controller Registers
HEX ADDRESS
0x02A0 0000
0x02A0 0004
0x02A0 0008 - 0x02A0 00FC
0x02A0 0100
0x02A0 0104
0x02A0 0108
0x02A0 010C
0x02A0 0110
0x02A0 0114
0x02A0 0118
0x02A0 011C
0x02A0 0120
0x02A0 0124
0x02A0 0128
0x02A0 012C
0x02A0 0130
0x02A0 0134
0x02A0 0138
0x02A0 013C
0x02A0 0140
0x02A0 0144
0x02A0 0148
0x02A0 014C
0x02A0 0150
ACRONYM
PID
REGISTER NAME
Peripheral ID Register
CCCFG
EDMA3CC Configuration Register
Reserved
DCHMAP0
DCHMAP1
DCHMAP2
DCHMAP3
DCHMAP4
DCHMAP5
DCHMAP6
DCHMAP7
DCHMAP8
DCHMAP9
DCHMAP10
DCHMAP11
DCHMAP12
DCHMAP13
DCHMAP14
DCHMAP15
DCHMAP16
DCHMAP17
DCHMAP18
DCHMAP19
DCHMAP20
DMA Channel 0 Mapping Register
DMA Channel 1 Mapping Register
DMA Channel 2 Mapping Register
DMA Channel 3 Mapping Register
DMA Channel 4 Mapping Register
DMA Channel 5 Mapping Register
DMA Channel 6 Mapping Register
DMA Channel 7 Mapping Register
DMA Channel 8 Mapping Register
DMA Channel 9 Mapping Register
DMA Channel 10 Mapping Register
DMA Channel 11 Mapping Register
DMA Channel 12 Mapping Register
DMA Channel 13 Mapping Register
DMA Channel 14 Mapping Register
DMA Channel 15 Mapping Register
DMA Channel 16 Mapping Register
DMA Channel 17 Mapping Register
DMA Channel 18 Mapping Register
DMA Channel 19 Mapping Register
DMA Channel 20 Mapping Register
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Table 6-14. EDMA Channel Controller Registers (continued)
HEX ADDRESS
0x02A0 0154
0x02A0 0158
0x02A0 015C
0x02A0 0160
0x02A0 0164
0x02A0 0168
0x02A0 016C
0x02A0 0170
0x02A0 0174
0x02A0 0178
0x02A0 017C
0x02A0 0180
0x02A0 0184
0x02A0 0188
0x02A0 018C
0x02A0 0190
0x02A0 0194
0x02A0 0198
0x02A0 019C
0x02A0 01A0
0x02A0 01A4
0x02A0 01A8
0x02A0 01AC
0x02A0 01B0
0x02A0 01B4
0x02A0 01B8
0x02A0 01BC
0x02A0 01C0
0x02A0 01C4
0x02A0 01C8
0x02A0 01CC
0x02A0 01D0
0x02A0 01D4
0x02A0 01D8
0x02A0 01DC
0x02A0 01E0
0x02A0 01E4
0x02A0 01E8
0x02A0 01EC
0x02A0 01F0
0x02A0 01F4
0x02A0 01F8
0x02A0 01FC
0x02A0 0200
0x02A0 0204
0x02A0 0208
0x02A0 020C
ACRONYM
DCHMAP21
DCHMAP22
DCHMAP23
DCHMAP24
DCHMAP25
DCHMAP26
DCHMAP27
DCHMAP28
DCHMAP29
DCHMAP30
DCHMAP31
DCHMAP32
DCHMAP33
DCHMAP34
DCHMAP35
DCHMAP36
DCHMAP37
DCHMAP38
DCHMAP39
DCHMAP40
DCHMAP41
DCHMAP42
DCHMAP43
DCHMAP44
DCHMAP45
DCHMAP46
DCHMAP47
DCHMAP48
DCHMAP49
DCHMAP50
DCHMAP51
DCHMAP52
DCHMAP53
DCHMAP54
DCHMAP55
DCHMAP56
DCHMAP57
DCHMAP58
DCHMAP59
DCHMAP60
DCHMAP61
DCHMAP62
DCHMAP63
QCHMAP0
QCHMAP1
QCHMAP2
QCHMAP3
REGISTER NAME
DMA Channel 21 Mapping Register
DMA Channel 22 Mapping Register
DMA Channel 23 Mapping Register
DMA Channel 24 Mapping Register
DMA Channel 25 Mapping Register
DMA Channel 26 Mapping Register
DMA Channel 27 Mapping Register
DMA Channel 28 Mapping Register
DMA Channel 29 Mapping Register
DMA Channel 30 Mapping Register
DMA Channel 31 Mapping Register
DMA Channel 32 Mapping Register
DMA Channel 33 Mapping Register
DMA Channel 34 Mapping Register
DMA Channel 35 Mapping Register
DMA Channel 36 Mapping Register
DMA Channel 37 Mapping Register
DMA Channel 38 Mapping Register
DMA Channel 39 Mapping Register
DMA Channel 40 Mapping Register
DMA Channel 41 Mapping Register
DMA Channel 42 Mapping Register
DMA Channel 43 Mapping Register
DMA Channel 44 Mapping Register
DMA Channel 45 Mapping Register
DMA Channel 46 Mapping Register
DMA Channel 47 Mapping Register
DMA Channel 48 Mapping Register
DMA Channel 49 Mapping Register
DMA Channel 50 Mapping Register
DMA Channel 51 Mapping Register
DMA Channel 52 Mapping Register
DMA Channel 53 Mapping Register
DMA Channel 54 Mapping Register
DMA Channel 55 Mapping Register
DMA Channel 56 Mapping Register
DMA Channel 57 Mapping Register
DMA Channel 58 Mapping Register
DMA Channel 59 Mapping Register
DMA Channel 60 Mapping Register
DMA Channel 61 Mapping Register
DMA Channel 62 Mapping Register
DMA Channel 63 Mapping Register
QDMA Channel 0 Mapping to PaRAM Register
QDMA Channel 1 Mapping to PaRAM Register
QDMA Channel 2 Mapping to PaRAM Register
QDMA Channel 3 Mapping to PaRAM Register
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Table 6-14. EDMA Channel Controller Registers (continued)
HEX ADDRESS
0x02A0 0210
ACRONYM
QCHMAP4
QCHMAP5
QCHMAP6
QCHMAP7
-
REGISTER NAME
QDMA Channel 4 Mapping to PaRAM Register
QDMA Channel 5 Mapping to PaRAM Register
QDMA Channel 6 Mapping to PaRAM Register
QDMA Channel 7 Mapping to PaRAM Register
Reserved
0x02A0 0214
0x02A0 0218
0x02A0 021C
0x02A0 0220 - 0x02A0 021C
0x02A0 0220 - 0x02A0 023C
0x02A0 0240
-
Reserved
DMAQNUM0
DMAQNUM1
DMAQNUM2
DMAQNUM3
DMAQNUM4
DMAQNUM5
DMAQNUM6
DMAQNUM7
QDMAQNUM
-
DMA Queue Number Register 0 (Channels 00 to 07)
DMA Queue Number Register 1 (Channels 08 to 15)
DMA Queue Number Register 2 (Channels 16 to 23)
DMA Queue Number Register 3 (Channels 24 to 31)
DMA Queue Number Register 4 (Channels 32 to 39)
DMA Queue Number Register 5 (Channels 40 to 47)
DMA Queue Number Register 6 (Channels 48 to 55)
DMA Queue Number Register 7 (Channels 56 to 63)
CC QDMA Queue Number
0x02A0 0244
0x02A0 0248
0x02A0 024C
0x02A0 0250
0x02A0 0254
0x02A0 0258
0x02A0 025C
0x02A0 0260
0x02A0 0264 - 0x02A0 0280
0x02A0 0284
Reserved
QUEPRI
-
Queue Priority Register
0x02A0 0288 - 0x02A0 02FC
0x02A0 0300
Reserved
EMR
Event Missed Register
0x02A0 0304
EMRH
Event Missed Register High
0x02A0 0308
EMCR
Event Missed Clear Register
0x02A0 030C
EMCRH
QEMR
Event Missed Clear Register High
0x02A0 0310
QDMA Event Missed Register
0x02A0 0314
QEMCR
CCERR
CCERRCLR
EEVAL
QDMA Event Missed Clear Register
0x02A0 0318
EDMA3CC Error Register
0x02A0 031C
EDMA3CC Error Clear Register
0x02A0 0320
Error Evaluate Register
0x02A0 0324 - 0x02A0 033C
0x02A0 0340
-
Reserved
DRAE0
DMA Region Access Enable Register for Region 0
DMA Region Access Enable Register High for Region 0
DMA Region Access Enable Register for Region 1
DMA Region Access Enable Register High for Region 1
DMA Region Access Enable Register for Region 2
DMA Region Access Enable Register High for Region 2
DMA Region Access Enable Register for Region 3
DMA Region Access Enable Register High for Region 3
DMA Region Access Enable Register for Region 4
DMA Region Access Enable Register High for Region 4
DMA Region Access Enable Register for Region 5
DMA Region Access Enable Register High for Region 5
DMA Region Access Enable Register for Region 6
DMA Region Access Enable Register High for Region 6
DMA Region Access Enable Register for Region 7
DMA Region Access Enable Register High for Region 7
QDMA Region Access Enable Register for Region 0
QDMA Region Access Enable Register for Region 1
QDMA Region Access Enable Register for Region 2
0x02A0 0344
DRAEH0
DRAE1
0x02A0 0348
0x02A0 034C
DRAEH1
DRAE2
0x02A0 0350
0x02A0 0354
DRAEH2
DRAE3
0x02A0 0358
0x02A0 035C
DRAEH3
DRAE4
0x02A0 0360
0x02A0 0364
DRAEH4
DRAE5
0x02A0 0368
0x02A0 036C
DRAEH5
DRAE6
0x02A0 0370
0x02A0 0374
DRAEH6
DRAE7
0x02A0 0378
0x02A0 037C
DRAEH7
QRAE0
0x02A0 0380
0x02A0 0384
QRAE1
0x02A0 0388
QRAE2
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Table 6-14. EDMA Channel Controller Registers (continued)
HEX ADDRESS
0x02A0 038C
0x02A0 0390
0x02A0 0394
0x02A0 0398
0x02A0 039C
0x02A0 0400
0x02A0 0404
0x02A0 0408
0x02A0 040C
0x02A0 0410
0x02A0 0414
0x02A0 0418
0x02A0 041C
0x02A0 0420
0x02A0 0424
0x02A0 0428
0x02A0 042C
0x02A0 0430
0x02A0 0434
0x02A0 0438
0x02A0 043C
0x02A0 0440
0x02A0 0444
0x02A0 0448
0x02A0 044C
0x02A0 0450
0x02A0 0454
0x02A0 0458
0x02A0 045C
0x02A0 0460
0x02A0 0464
0x02A0 0468
0x02A0 046C
0x02A0 0470
0x02A0 0474
0x02A0 0478
0x02A0 047C
0x02A0 0480
0x02A0 0484
0x02A0 0488
0x02A0 048C
0x02A0 0490
0x02A0 0494
0x02A0 0498
0x02A0 049C
0x02A0 04A0
0x02A0 04A4
ACRONYM
QRAE3
QRAE4
QRAE5
QRAE6
QRAE7
Q0E0
REGISTER NAME
QDMA Region Access Enable Register for Region 3
QDMA Region Access Enable Register for Region 4
QDMA Region Access Enable Register for Region 5
QDMA Region Access Enable Register for Region 6
QDMA Region Access Enable Register for Region 7
Event Queue 0 Entry Register 0
Event Queue 0 Entry Register 1
Event Queue 0 Entry Register 2
Event Queue 0 Entry Register 3
Event Queue 0 Entry Register 4
Event Queue 0 Entry Register 5
Event Queue 0 Entry Register 6
Event Queue 0 Entry Register 7
Event Queue 0 Entry Register 8
Event Queue 0 Entry Register 9
Event Queue 0 Entry Register 10
Event Queue 0 Entry Register 11
Event Queue 0 Entry Register 12
Event Queue 0 Entry Register 13
Event Queue 0 Entry Register 14
Event Queue 0 Entry Register 15
Event Queue 1 Entry Register 0
Event Queue 1 Entry Register 1
Event Queue 1 Entry Register 2
Event Queue 1 Entry Register 3
Event Queue 1 Entry Register 4
Event Queue 1 Entry Register 5
Event Queue 1 Entry Register 6
Event Queue 1 Entry Register 7
Event Queue 1 Entry Register 8
Event Queue 1 Entry Register 9
Event Queue 1 Entry Register 10
Event Queue 1 Entry Register 11
Event Queue 1 Entry Register 12
Event Queue 1 Entry Register 13
Event Queue 1 Entry Register 14
Event Queue 1 Entry Register 15
Event Queue 2 Entry Register 0
Event Queue 2 Entry Register 1
Event Queue 2 Entry Register 2
Event Queue 2 Entry Register 3
Event Queue 2 Entry Register 4
Event Queue 2 Entry Register 5
Event Queue 2 Entry Register 6
Event Queue 2 Entry Register 7
Event Queue 2 Entry Register 8
Event Queue 2 Entry Register 9
Q0E1
Q0E2
Q0E3
Q0E4
Q0E5
Q0E6
Q0E7
Q0E8
Q0E9
Q0E10
Q0E11
Q0E12
Q0E13
Q0E14
Q0E15
Q1E0
Q1E1
Q1E2
Q1E3
Q1E4
Q1E5
Q1E6
Q1E7
Q1E8
Q1E9
Q1E10
Q1E11
Q1E12
Q1E13
Q1E14
Q1E15
Q2E0
Q2E1
Q2E2
Q2E3
Q2E4
Q2E5
Q2E6
Q2E7
Q2E8
Q2E9
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Table 6-14. EDMA Channel Controller Registers (continued)
HEX ADDRESS
0x02A0 04A8
ACRONYM
Q2E10
Q2E11
Q2E12
Q2E13
Q2E14
Q2E15
Q3E0
Q3E1
Q3E2
Q3E3
Q3E4
Q3E5
Q3E6
Q3E7
Q3E8
Q3E9
Q3E10
Q3E11
Q3E12
Q3E13
Q3E14
Q3E15
-
REGISTER NAME
Event Queue 2 Entry Register 10
0x02A0 04AC
Event Queue 2 Entry Register 11
Event Queue 2 Entry Register 12
Event Queue 2 Entry Register 13
Event Queue 2 Entry Register 14
Event Queue 2 Entry Register 15
Event Queue 3 Entry Register 0
Event Queue 3 Entry Register 1
Event Queue 3 Entry Register 2
Event Queue 3 Entry Register 3
Event Queue 3 Entry Register 4
Event Queue 3 Entry Register 5
Event Queue 3 Entry Register 6
Event Queue 3 Entry Register 7
Event Queue 3 Entry Register 8
Event Queue 3 Entry Register 9
Event Queue 3 Entry Register 10
Event Queue 3 Entry Register 11
Event Queue 3 Entry Register 12
Event Queue 3 Entry Register 13
Event Queue 3 Entry Register 14
Event Queue 3 Entry Register 15
Reserved
0x02A0 04B0
0x02A0 04B4
0x02A0 04B8
0x02A0 04BC
0x02A0 04C0
0x02A0 04C4
0x02A0 04C8
0x02A0 04CC
0x02A0 04D0
0x02A0 04D4
0x02A0 04D8
0x02A0 04DC
0x02A0 04E0
0x02A0 04E4
0x02A0 04E8
0x02A0 04EC
0x02A0 04F0
0x02A0 04F4
0x02A0 04F8
0x02A0 04FC
0x02A0 0500 - 0x02A0 051C
0x02A0 0520 - 0x02A0 05FC
0x02A0 0600
-
Reserved
QSTAT0
QSTAT1
QSTAT2
QSTAT3
-
Queue 0 Status Register
0x02A0 0604
Queue 1 Status Register
0x02A0 0608
Queue Status Register 2
0x02A0 060C
Queue Status Register 3
0x02A0 0610 - 0x02A0 061C
0x02A0 0620
Reserved
QWMTHRA
-
Queue Watermark Threshold A Register for Q[3:0]
Reserved
0x02A0 0624
0x02A0 0640
CCSTAT
-
EDMA3CC Status Register
0x02A0 0644 - 0x02A0 06FC
0x02A0 0700 - 0x02A0 07FC
0x02A0 0800
Reserved
-
Reserved
MPFAR
MPFSR
MPFCR
MPPA0
MPPA1
MPPA2
MPPA3
MPPA4
MPPA5
MPPA6
MPPA7
-
Memory Protection Fault Address Register
Memory Protection Fault Status Register
Memory Protection Fault Command Register
Memory Protection Page Attribute Register 0
Memory Protection Page Attribute Register 1
Memory Protection Page Attribute Register 2
Memory Protection Page Attribute Register 3
Memory Protection Page Attribute Register 4
Memory Protection Page Attribute Register 5
Memory Protection Page Attribute Register 6
Memory Protection Page Attribute Register 7
Reserved
0x02A0 0804
0x02A0 0808
0x02A0 080C
0x02A0 0810
0x02A0 0814
0x02A0 0818
0x02A0 081C
0x02A0 0820
0x02A0 0824
0x02A0 0828
0x02A0 082C - 0x02A0 0FFC
0x02A0 1000
ER
Event Register
76
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Table 6-14. EDMA Channel Controller Registers (continued)
HEX ADDRESS
0x02A0 1004
0x02A0 1008
0x02A0 100C
0x02A0 1010
0x02A0 1014
0x02A0 1018
0x02A0 101C
0x02A0 1020
0x02A0 1024
0x02A0 1028
0x02A0 102C
0x02A0 1030
0x02A0 1034
0x02A0 1038
0x02A0 103C
0x02A0 1040
0x02A0 1044
ACRONYM
ERH
REGISTER NAME
Event Register High
ECR
Event Clear Register
Event Clear Register High
Event Set Register
ECRH
ESR
ESRH
CER
Event Set Register High
Chained Event Register
CERH
EER
Chained Event Register High
Event Enable Register
EERH
EECR
EECRH
EESR
EESRH
SER
Event Enable Register High
Event Enable Clear Register
Event Enable Clear Register High
Event Enable Set Register
Event Enable Set Register High
Secondary Event Register
Secondary Event Register High
Secondary Event Clear Register
Secondary Event Clear Register High
Reserved
SERH
SECR
SECRH
0x02A0 1048 - 0x02A0 104C
0x02A0 1050
IER
Interrupt Enable Register
Interrupt Enable Register High
Interrupt Enable Clear Register
Interrupt Enable Clear Register High
Interrupt Enable Set Register
Interrupt Enable Set Register High
Interrupt Pending Register
Interrupt Pending Register High
Interrupt Clear Register
0x02A0 1054
IERH
0x02A0 1058
IECR
0x02A0 105C
IECRH
0x02A0 1060
IESR
0x02A0 1064
IESRH
0x02A0 1068
IPR
0x02A0 106C
IPRH
0x02A0 1070
ICR
0x02A0 1074
ICRH
Interrupt Clear Register High
Interrupt Evaluate Register
Reserved
0x02A0 1078
IEVAL
0x02A0 107C
-
0x02A0 1080
QER
QDMA Event Register
0x02A0 1084
QEER
QDMA Event Enable Register
QDMA Event Enable Clear Register
QDMA Event Enable Set Register
QDMA Secondary Event Register
QDMA Secondary Event Clear Register
Reserved
0x02A0 1088
QEECR
0x02A0 108C
QEESR
0x02A0 1090
QSER
0x02A0 1094
QSECR
0x02A0 1098 - 0x02A0 1FFF
0x02A0 2000- 0x02A0 2097
0x02A0 2098 - 0x02A0 21FF
0x02A0 2200 - 0x02A0 2297
0x02A0 2298 - 0x02A0 23FF
0x02A0 2400 - 0x02A0 2497
0x02A0 2498 - 0x02A0 25FF
0x02A0 2600 - 0x02A0 2697
0x02A0 2698 - 0x02A0 27FF
0x02A0 2800 - 0x02A0 2897
0x02A0 2898 - 0x02A0 29FF
-
-
-
-
-
-
-
-
-
-
-
Shadow Region 0 Channel Registers
Reserved
Shadow Region 1 Channel Registers
Reserved
Shadow Region 2 Channel Registers
Reserved
Shadow Region 3 Channel Registers
Reserved
Shadow Region 4 Channel Registers
Reserved
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Table 6-14. EDMA Channel Controller Registers (continued)
HEX ADDRESS
ACRONYM
REGISTER NAME
Shadow Region 5 Channel Registers
0x02A0 2A00 - 0x02A0 2A97
0x02A0 2A98 - 0x02A0 2BFF
0x02A0 2C00 - 0x02A0 2C97
0x02A0 2C98 - 0x02A0 2DFF
0x02A0 2E00 - 0x02A0 2E97
0x02A0 2E98 - 0x02A0 2FFF
-
-
-
-
-
-
Reserved
Shadow Region 6 Channel Registers
Reserved
Shadow Region 7 Channel Registers
Reserved
Table 6-15 shows an abbreviation of the set of registers that make up the parameter set for each of 128
EDMA events. Each of the parameter register sets consist of eight 32-bit word entries. Table 6-16 shows
the parameter set entry registers with relative memory address locations within each of the parameter
sets.
Table 6-15. EDMA Parameter Set RAM
HEX ADDRESS RANGE
0x02A0 4000 - 0x02A0 401F
0x02A0 4020 - 0x02A0 403F
0x02A0 4040 - 0x02A0 405F
0x02A0 4060 - 0x02A0 407F
0x02A0 4080 - 0x02A0 409F
0x02A0 40A0 - 0x02A0 40BF
...
DESCRIPTION
Parameters Set 0 (8 32-bit words)
Parameters Set 1 (8 32-bit words)
Parameters Set 2 (8 32-bit words)
Parameters Set 3 (8 32-bit words)
Parameters Set 4 (8 32-bit words)
Parameters Set 5 (8 32-bit words)
...
0x02A0 4FC0 - 0x02A0 4FDF
0x02A0 4FE0 - 0x02A0 4FFF
...
Parameters Set 126 (8 32-bit words)
Parameters Set 127 (8 32-bit words)
...
0x02A0 5FC0 - 0x02A0 5FDF
0x02A0 5FE0 - 0x02A0 5FFF
...
Parameters Set 254 (8 32-bit words)
Parameters Set 255 (8 32-bit words)
...
0x02A0 7FC0 - 0x02A0 7FDF
0x02A0 7FE0 - 0x02A0 7FFF
Parameters Set 510 (8 32-bit words)
Parameters Set 511 (8 32-bit words)
Table 6-16. Parameter Set Entries
HEX OFFSET ADDRESS
WITHIN THE PARAMETER SET
ACRONYM
PARAMETER ENTRY
0x0000
0x0004
0x0008
0x000C
0x0010
0x0014
0x0018
0x001C
OPT
SRC
Option
Source Address
A_B_CNT
DST
A Count, B Count
Destination Address
SRC_DST_BIDX
LINK_BCNTRLD
SRC_DST_CIDX
CCNT
Source B Index, Destination B Index
Link Address, B Count Reload
Source C Index, Destination C Index
C Count
Table 6-17. EDMA3 Transfer Controller 0 Registers
HEX ADDRESS RANGE
02A2 0000
ACRONYM
REGISTER NAME
PID
TCCFG
-
Peripheral Identification Register
EDMA3TC Configuration Register
Reserved
02A2 0004
02A2 0008 - 02A2 00FC
78
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Table 6-17. EDMA3 Transfer Controller 0 Registers (continued)
HEX ADDRESS RANGE
ACRONYM
TCSTAT
-
REGISTER NAME
02A2 0100
02A2 0104 - 02A2 011C
02A2 0120
EDMA3TC Channel Status Register
Reserved
ERRSTAT
ERREN
ERRCLR
ERRDET
ERRCMD
-
Error Register
02A2 0124
Error Enable Register
02A2 0128
Error Clear Register
02A2 012C
Error Details Register
02A2 0130
Error Interrupt Command Register
Reserved
02A2 0134 - 02A2 013C
02A2 0140
RDRATE
-
Read Rate Register
02A2 0144 - 02A2 023C
02A2 0240
Reserved
SAOPT
Source Active Options Register
02A2 0244
SASRC
SACNT
Source Active Source Address Register
Source Active Count Register
02A2 0248
02A2 024C
SADST
Source Active Destination Address Register
Source Active Source B-Index Register
Source Active Memory Protection Proxy Register
Source Active Count Reload Register
Source Active Source Address B-Reference Register
Source Active Destination Address B-Reference Register
Reserved
02A2 0250
SABIDX
SAMPPRXY
SACNTRLD
SASRCBREF
SADSTBREF
-
02A2 0254
02A2 0258
02A2 025C
02A2 0260
02A2 0264 - 02A2 027C
02A2 0280
DFCNTRLD
DFSRCBREF
DFDSTBREF
-
Destination FIFO Set Count Reload
Destination FIFO Set Destination Address B Reference Register
Destination FIFO Set Destination Address B Reference Register
Reserved
02A2 0284
02A2 0288
02A2 028C - 02A2 02FC
02A2 0300
DFOPT0
DFSRC0
DFCNT0
DFDST0
DFBIDX0
DFMPPRXY0
-
Destination FIFO Options Register 0
Destination FIFO Source Address Register 0
Destination FIFO Count Register 0
Destination FIFO Destination Address Register 0
Destination FIFO BIDX Register 0
Destination FIFO Memory Protection Proxy Register 0
Reserved
02A2 0304
02A2 0308
02A2 030C
02A2 0310
02A2 0314
02A2 0318 - 02A2 033C
02A2 0340
DFOPT1
DFSRC1
DFCNT1
DFDST1
DFBIDX1
DFMPPRXY1
-
Destination FIFO Options Register 1
Destination FIFO Source Address Register 1
Destination FIFO Count Register 1
Destination FIFO Destination Address Register 1
Destination FIFO BIDX Register 1
Destination FIFO Memory Protection Proxy Register 1
Reserved
02A2 0344
02A2 0348
02A2 034C
02A2 0350
02A2 0354
02A2 0358 - 02A2 037C
02A2 0380
DFOPT2
DFSRC2
DFCNT2
DFDST2
DFBIDX2
DFMPPRXY2
-
Destination FIFO Options Register 2
Destination FIFO Source Address Register 2
Destination FIFO Count Register 2
Destination FIFO Destination Address Register 2
Destination FIFO BIDX Register 2
Destination FIFO Memory Protection Proxy Register 2
Reserved
02A2 0384
02A2 0388
02A2 038C
02A2 0390
02A2 0394
02A2 0398 - 02A2 03BC
02A2 03C0
DFOPT3
DFSRC3
Destination FIFO Options Register 3
Destination FIFO Source Address Register 3
02A2 03C4
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Table 6-17. EDMA3 Transfer Controller 0 Registers (continued)
HEX ADDRESS RANGE
02A2 03C8
ACRONYM
DFCNT3
DFDST3
DFBIDX3
DFMPPRXY3
-
REGISTER NAME
Destination FIFO Count Register 3
Destination FIFO Destination Address Register 3
Destination FIFO BIDX Register 3
Destination FIFO Memory Protection Proxy Register 3
Reserved
02A2 03CC
02A2 03D0
02A2 03D4
02A2 03D8 - 02A2 7FFF
Table 6-18. EDMA3 Transfer Controller 1 Registers
HEX ADDRESS RANGE
02A2 8000
ACRONYM
PID
REGISTER NAME
Peripheral Identification Register
EDMA3TC Configuration Register
Reserved
02A2 8004
TCCFG
-
02A2 8008 - 02A2 80FC
02A2 8100
TCSTAT
-
EDMA3TC Channel Status Register
Reserved
02A2 8104 - 02A2 811C
02A2 8120
ERRSTAT
ERREN
ERRCLR
ERRDET
ERRCMD
-
Error Register
02A2 8124
Error Enable Register
02A2 8128
Error Clear Register
02A2 812C
Error Details Register
02A2 8130
Error Interrupt Command Register
Reserved
02A2 8134 - 02A2 813C
02A2 8140
RDRATE
-
Read Rate Register
02A2 8144 - 02A2 823C
02A2 8240
Reserved
SAOPT
SASRC
SACNT
SADST
SABIDX
SAMPPRXY
SACNTRLD
SASRCBREF
SADSTBREF
-
Source Active Options Register
Source Active Source Address Register
Source Active Count Register
02A2 8244
02A2 8248
02A2 824C
Source Active Destination Address Register
Source Active Source B-Index Register
Source Active Memory Protection Proxy Register
Source Active Count Reload Register
Source Active Source Address B-Reference Register
Source Active Destination Address B-Reference Register
Reserved
02A2 8250
02A2 8254
02A2 8258
02A2 825C
02A2 8260
02A2 8264 - 02A2 827C
02A2 8280
DFCNTRLD
DFSRCBREF
DFDSTBREF
-
Destination FIFO Set Count Reload
Destination FIFO Set Destination Address B Reference Register
Destination FIFO Set Destination Address B Reference Register
Reserved
02A2 8284
02A2 8288
02A2 828C - 02A2 82FC
02A2 8300
DFOPT0
DFSRC0
DFCNT0
DFDST0
DFBIDX0
DFMPPRXY0
-
Destination FIFO Options Register 0
Destination FIFO Source Address Register 0
Destination FIFO Count Register 0
Destination FIFO Destination Address Register 0
Destination FIFO BIDX Register 0
Destination FIFO Memory Protection Proxy Register 0
Reserved
02A2 8304
02A2 8308
02A2 830C
02A2 8310
02A2 8314
02A2 8318 - 02A2 833C
02A2 8340
DFOPT1
DFSRC1
DFCNT1
DFDST1
DFBIDX1
Destination FIFO Options Register 1
Destination FIFO Source Address Register 1
Destination FIFO Count Register 1
Destination FIFO Destination Address Register 1
Destination FIFO BIDX Register 1
02A2 8344
02A2 8348
02A2 834C
02A2 8350
80
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Table 6-18. EDMA3 Transfer Controller 1 Registers (continued)
HEX ADDRESS RANGE
ACRONYM
DFMPPRXY1
-
REGISTER NAME
02A2 8354
02A2 8358 - 02A2 837C
02A2 8380
Destination FIFO Memory Protection Proxy Register 1
Reserved
DFOPT2
DFSRC2
DFCNT2
DFDST2
DFBIDX2
DFMPPRXY2
-
Destination FIFO Options Register 2
Destination FIFO Source Address Register 2
Destination FIFO Count Register 2
Destination FIFO Destination Address Register 2
Destination FIFO BIDX Register 2
Destination FIFO Memory Protection Proxy Register 2
Reserved
02A2 8384
02A2 8388
02A2 838C
02A2 8390
02A2 8394
02A2 8398 - 02A2 83BC
02A2 83C0
DFOPT3
DFSRC3
DFCNT3
DFDST3
DFBIDX3
DFMPPRXY3
-
Destination FIFO Options Register 3
Destination FIFO Source Address Register 3
Destination FIFO Count Register 3
Destination FIFO Destination Address Register 3
Destination FIFO BIDX Register 3
Destination FIFO Memory Protection Proxy Register 3
Reserved
02A2 83C4
02A2 83C8
02A2 83CC
02A2 83D0
02A2 83D4
02A2 83D8 - 02A2 FFFF
Table 6-19. EDMA3 Transfer Controller 2 Registers
HEX ADDRESS RANGE
02A3 0000
ACRONYM
PID
REGISTER NAME
Peripheral Identification Register
EDMA3TC Configuration Register
Reserved
02A3 0004
TCCFG
-
02A3 0008 - 02A3 00FC
02A3 0100
TCSTAT
-
EDMA3TC Channel Status Register
Reserved
02A3 0104 - 02A3 011C
02A3 0120
ERRSTAT
ERREN
ERRCLR
ERRDET
ERRCMD
-
Error Register
02A3 0124
Error Enable Register
02A3 0128
Error Clear Register
02A3 012C
Error Details Register
02A3 0130
Error Interrupt Command Register
Reserved
02A3 0134 - 02A3 013C
02A3 0140
RDRATE
-
Read Rate Register
02A3 0144 - 02A3 023C
02A3 0240
Reserved
SAOPT
SASRC
SACNT
SADST
SABIDX
SAMPPRXY
SACNTRLD
SASRCBREF
SADSTBREF
-
Source Active Options Register
Source Active Source Address Register
Source Active Count Register
Source Active Destination Address Register
Source Active Source B-Index Register
Source Active Memory Protection Proxy Register
Source Active Count Reload Register
Source Active Source Address B-Reference Register
Source Active Destination Address B-Reference Register
Reserved
02A3 0244
02A3 0248
02A3 024C
02A3 0250
02A3 0254
02A3 0258
02A3 025C
02A3 0260
02A3 0264 - 02A3 027C
02A3 0280
DFCNTRLD
DFSRCBREF
DFDSTBREF
-
Destination FIFO Set Count Reload
Destination FIFO Set Destination Address B Reference Register
Destination FIFO Set Destination Address B Reference Register
Reserved
02A3 0284
02A3 0288
02A3 028C - 02A3 02FC
02A3 0300
DFOPT0
Destination FIFO Options Register 0
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Table 6-19. EDMA3 Transfer Controller 2 Registers (continued)
HEX ADDRESS RANGE
02A3 0304
ACRONYM
DFSRC0
DFCNT0
DFDST0
DFBIDX0
DFMPPRXY0
-
REGISTER NAME
Destination FIFO Source Address Register 0
Destination FIFO Count Register 0
Destination FIFO Destination Address Register 0
Destination FIFO BIDX Register 0
Destination FIFO Memory Protection Proxy Register 0
Reserved
02A3 0308
02A3 030C
02A3 0310
02A3 0314
02A3 0318 - 02A3 033C
02A3 0340
DFOPT1
DFSRC1
DFCNT1
DFDST1
DFBIDX1
DFMPPRXY1
-
Destination FIFO Options Register 1
Destination FIFO Source Address Register 1
Destination FIFO Count Register 1
Destination FIFO Destination Address Register 1
Destination FIFO BIDX Register 1
Destination FIFO Memory Protection Proxy Register 1
Reserved
02A3 0344
02A3 0348
02A3 034C
02A3 0350
02A3 0354
02A3 0358 - 02A3 037C
02A3 0380
DFOPT2
DFSRC2
DFCNT2
DFDST2
DFBIDX2
DFMPPRXY2
-
Destination FIFO Options Register 2
Destination FIFO Source Address Register 2
Destination FIFO Count Register 2
Destination FIFO Destination Address Register 2
Destination FIFO BIDX Register 2
Destination FIFO Memory Protection Proxy Register 2
Reserved
02A3 0384
02A3 0388
02A3 038C
02A3 0390
02A3 0394
02A3 0398 - 02A3 03BC
02A3 03C0
DFOPT3
DFSRC3
DFCNT3
DFDST3
DFBIDX3
DFMPPRXY3
-
Destination FIFO Options Register 3
Destination FIFO Source Address Register 3
Destination FIFO Count Register 3
Destination FIFO Destination Address Register 3
Destination FIFO BIDX Register 3
Destination FIFO Memory Protection Proxy Register 3
Reserved
02A3 03C4
02A3 03C8
02A3 03CC
02A3 03D0
02A3 03D4
02A3 03D8 - 02A3 7FFF
Table 6-20. EDMA3 Transfer Controller 3 Registers
HEX ADDRESS RANGE
02A3 8000
ACRONYM
PID
REGISTER NAME
Peripheral Identification Register
EDMA3TC Configuration Register
Reserved
02A3 8004
TCCFG
-
02A3 8008 - 02A3 80FC
02A3 8100
TCSTAT
-
EDMA3TC Channel Status Register
Reserved
02A3 8104 - 02A3 811C
02A3 8120
ERRSTAT
ERREN
ERRCLR
ERRDET
ERRCMD
-
Error Register
02A3 8124
Error Enable Register
02A3 8128
Error Clear Register
02A3 812C
Error Details Register
02A3 8130
Error Interrupt Command Register
Reserved
02A3 8134 - 02A3 813C
02A3 8140
RDRATE
-
Read Rate Register
02A3 8144 - 02A3 823C
02A3 8240
Reserved
SAOPT
SASRC
SACNT
SADST
Source Active Options Register
Source Active Source Address Register
Source Active Count Register
Source Active Destination Address Register
02A3 8244
02A3 8248
02A3 824C
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Table 6-20. EDMA3 Transfer Controller 3 Registers (continued)
HEX ADDRESS RANGE
ACRONYM
SABIDX
SAMPPRXY
SACNTRLD
SASRCBREF
SADSTBREF
-
REGISTER NAME
02A3 8250
02A3 8254
Source Active Source B-Index Register
Source Active Memory Protection Proxy Register
Source Active Count Reload Register
Source Active Source Address B-Reference Register
Source Active Destination Address B-Reference Register
Reserved
02A3 8258
02A3 825C
02A3 8260
02A3 8264 - 02A3 827C
02A3 8280
DFCNTRLD
DFSRCBREF
DFDSTBREF
-
Destination FIFO Set Count Reload
Destination FIFO Set Destination Address B Reference Register
Destination FIFO Set Destination Address B Reference Register
Reserved
02A3 8284
02A3 8288
02A3 828C - 02A3 82FC
02A3 8300
DFOPT0
DFSRC0
DFCNT0
DFDST0
DFBIDX0
DFMPPRXY0
-
Destination FIFO Options Register 0
Destination FIFO Source Address Register 0
Destination FIFO Count Register 0
02A3 8304
02A3 8308
02A3 830C
Destination FIFO Destination Address Register 0
Destination FIFO BIDX Register 0
02A3 8310
02A3 8314
Destination FIFO Memory Protection Proxy Register 0
Reserved
02A3 8318 - 02A3 833C
02A3 8340
DFOPT1
DFSRC1
DFCNT1
DFDST1
DFBIDX1
DFMPPRXY1
-
Destination FIFO Options Register 1
Destination FIFO Source Address Register 1
Destination FIFO Count Register 1
02A3 8344
02A3 8348
02A3 834C
Destination FIFO Destination Address Register 1
Destination FIFO BIDX Register 1
02A3 8350
02A3 8354
Destination FIFO Memory Protection Proxy Register 1
Reserved
02A3 8358 - 02A3 837C
02A3 8380
DFOPT2
DFSRC2
DFCNT2
DFDST2
DFBIDX2
DFMPPRXY2
-
Destination FIFO Options Register 2
Destination FIFO Source Address Register 2
Destination FIFO Count Register 2
02A3 8384
02A3 8388
02A3 838C
Destination FIFO Destination Address Register 2
Destination FIFO BIDX Register 2
02A3 8390
02A3 8394
Destination FIFO Memory Protection Proxy Register 2
Reserved
02A3 8398 - 02A3 83BC
02A3 83C0
DFOPT3
DFSRC3
DFCNT3
DFDST3
DFBIDX3
DFMPPRXY3
-
Destination FIFO Options Register 3
Destination FIFO Source Address Register 3
Destination FIFO Count Register 3
02A3 83C4
02A3 83C8
02A3 83CC
Destination FIFO Destination Address Register 3
Destination FIFO BIDX Register 3
02A3 83D0
02A3 83D4
Destination FIFO Memory Protection Proxy Register 3
Reserved
02A3 83D8 - 02A3 FFFF
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6.7 Reset Controller
The reset controller detects the different types of resets supported on the device and manages the
distribution of those resets throughout the device.
The device has several types of resets: power-on reset, warm reset, max reset and system reset.
Table 6-21 explains further the types of reset, the reset initiator, and the effects of each reset on the chip.
See Section 6.7.8 for more information on the effects of each reset on the PLL controllers and their clocks.
Table 6-21. Device-Level Reset Types
TYPE
INITIATOR
EFFECT(s)
Power-on Reset
POR pin
Resets the entire chip including the test and emulation logic
Resets everything except for the test and emulation logic and the
Ethernet Subsystem
Warm Reset
Max Reset
RESET pin
Emulator
Same as a warm reset
A system reset maintains memory contents and does not reset the
test and emulation circuit and the Ethernet Subsystem. The device
configuration pins are also not re-latched and system reset does not
affect the state of the peripherals (enable/disable).
System Reset
PCI via the PRST pin
In addition to device-level global resets, the PSC provides the capability to cause local resets to
peripherals and/or the CPU.
6.7.1 Power-on Reset (POR Pin)
Power-on reset (POR) is initiated by the POR pin and is used to reset the entire chip, including the test
and emulation logic. Power-on reset is also referred to as a cold reset since the device usually goes
through a power-up cycle. During power-up, the POR pin must be asserted (driven low) until the power
supplies have reached their normal operating conditions. Note that a device power-up cycle is not required
to initiate a power-on reset.
The following sequence must be followed during a power-on reset:
1. Wait for all power supplies to reach normal operating conditions while keeping the POR pin asserted
(driven low). While POR is asserted, all pins will be in high-impedance mode. After the POR pin is
deasserted (driven high), all Z-group pins, low-group pins, and high-group pins are set to their reset
state and will remain at their reset state until configured by their respective peripheral. The clock and
reset of each peripheral is determined by the default settings of the power and sleep controller (PSC).
2. Once all the power supplies are within valid operating conditions, the POR pin must remain asserted
(low) for a minimum number of 256 CLKIN2 cycles. The PLL1 controller input clock, CLKIN1, and the
PCI input clock, PCLK, must be valid during this time. PCLK is needed only if the PCI module is being
used. If the DDR2 memory controller and the Ethernet Subsystem are not needed, CLKIN2 can be tied
low and REFCLKP/REFCLKN can be connected to VSS and CVDD respectively. In this case, the POR
pin must remain asserted (low) for a minimum of 256 CLKIN1 cycles after all power supplies have
reached valid operating conditions. Within the low period of the POR pin, the following occurs:
(a) The reset signals flow to the entire chip (including the test and emulation logic), resetting modules
that use reset asynchronously.
(b) The PLL1 controller clocks are started at the frequency of the system reference clock. The clocks
are propagated throughout the chip to reset modules that use reset synchronously. By default,
PLL1 is in reset and unlocked.
(c) The PLL2 controller clocks are started at the frequency of the system reference clock. PLL2 is held
in reset. Since the PLL2 controller always operates in PLL mode, the system reference clock and
all the system clocks are invalid at this point.
(d) The RESETSTAT pin stays asserted (low), indicating the device is in reset.
3. The POR pin may now be deasserted (driven high). When the POR pin is deasserted, the
configuration pin values are latched, and the PLL controllers change their system clocks to their default
divide-down values. PLL2 is taken out of reset and automatically starts its locking sequence. Other
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device initialization is also started.
4. After device initialization is complete, the RESETSTAT pin is deasserted (driven high). By this time,
PLL2 has already completed its locking sequence and is outputting a valid clock. The system clocks of
both PLL controllers are allowed to finish their current cycles and then paused for 10 cycles of their
respective system reference clocks. After the pause, the system clocks are restarted at their default
divide-by settings.
The device is now out of reset; device execution begins as dictated by the selected boot mode.
6.7.2 Warm Reset (RESET Pin)
A warm reset has the same effect as a power-on reset, except that in this case, the test and emulation
logic are not reset.
The following sequence must be followed during a warm reset:
1. Hold the RESET pin low for a minimum of 24 CLKIN1 cycles. Within the low period of the RESET pin,
the following occurs:
(a) The Z-group pins, low-group pins, and the high-group pins are set to their reset state
(b) The reset signals flow to the entire chip (excluding the test and emulation logic), resetting modules
that use reset asynchronously
(c) The PLL Controllers are reset. PLL1 switches back to PLL bypass mode, resetting all their
registers to default values. Both PLL1 and PLL2 are placed in reset and lose lock. The PLL1
controller clocks start running at the frequency of the system reference clock. The clocks are
propagated throughout the chip to reset modules that use reset synchronously.
(d) The RESETSTAT pin becomes active (low), indicating the device is in reset.
2. The RESET pin may now be released (driven inactive high). When the RESET pin is released, the
configuration pin values are latched and the PLL controllers immediately change their system clocks to
their default divide-down values. Other device initialization is also started.
After device initialization is complete, the RESETSTAT pin goes inactive (high). All system clocks are
allowed to finish their current cycles and then paused for 10 cycles of their respective system reference
clocks. After the pause the system clocks are restarted at their default divide-by settings.
The clock and reset of each peripheral is determined by the default settings of the PSC.
The device is now out of reset, device execution begins as dictated by the selected boot mode.
6.7.3 Maximum Reset
A maximum (max) reset is initiated by the emulator. The effects are the same as a warm reset, except the
device boot and configuration pins are not re-latched. The emulator initiates a maximum reset via the
ICEPICK module. This ICEPICK initiated reset is nonmaskable.
The max reset sequence is as follows:
1. Max reset is initiated by the emulator. During this time, the following happens:
(a) The reset signals flow to the entire chip, resetting all the modules on chip except the test and
emulation logic.
(b) The PLL controllers are reset, PLL1 switches back to PLL bypass mode, resetting all their registers
to default values. Both PLL1 and PLL2 are placed in reset and lose lock.
(c) The RESETSTAT pin becomes asserted (low), indicating the device is in reset.
2. After device initialization is complete, the PLL Controllers pause the system clocks for 10 cycles. At the
end of these 10 cycles, the RESETSTAT pin is deasserted (driven high). At this point, the following
occurs:
(a) The I/O pins are controlled by the default peripherals (default peripherals are determined by
PINMUX register).
(b) The clock and reset of each peripheral is determined by the default settings of the power and sleep
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controller (PSC).
(c) The C64x+ begins executing from DSPBOOTADDR (determined by bootmode selection).
After the reset sequence, the boot sequence begins. Since the boot and configuration pins are not
latched with a max reset, the previous values (as shown in the BOOTCFG register) are used to
select the bootmode. For more details on the boot sequence, see the Using the
TMS320DM647/DM648 Bootloader Application Report (literature number SPRAAJ1). After the boot
sequence, follow the software initialization sequence.
6.7.4 System Reset
A system reset maintains memory contents and does not reset the clock logic or the test and emulation
circuitry. The device configuration pins are also not re-latched and the state of the peripherals
(enabled/disabled) is also not affected. A system reset is initiated by the PRST pin of PCI peripheral.
During a system reset, the following happens:
1. The RESETSTAT pin goes low to indicate an internal reset is being generated. The reset is allowed to
propagate through the system. Internal system clocks are not affected.
2. After the internal reset signal has propagated, the PLL controllers pause and restart their system
clocks for about 10 cycles of their system reference clocks, but retain their configuration. The PLLs
also remain locked.
3. The boot sequence is started after the system clocks are restarted. Since the configuration pins
(including the BOOTMODE[3:0] pins) are not latched with a system reset, the previous values, as
shown in the BOOTCFG register, are used to select the boot mode.
6.7.5 Peripheral Local Reset
The user can configure the local reset and clock state of a peripheral through programming the PSC.
Table 6-2 identifies the LPSC numbers and the peripherals capable of being locally reset by the PSC. For
more detailed information on the programming of these peripherals by the PSC, see the
TMS320DM647/TMS320DM648 DSP Subsystem Reference Guide (literature number SPRUEU6).
6.7.6 Reset Priority
If any of the above reset sources occur simultaneously, the PLLCTRL processes only the highest priority
reset request. The reset request priorities are as follows (high to low):
•
•
•
•
Power-on Reset
Maximum Reset
Warm Reset
System Reset
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6.7.7 Reset Controller Register
The reset type status (RSTYPE) register is the only register for the reset controller.
The RSTYPE register latches the cause of the last reset. If multiple reset sources occur simultaneously,
this register latches the highest priority reset source. The reset type status register is shown in Figure 6-9
and described in Table 6-22.
Figure 6-9. Reset Type Status Register (RSTYPE)
31
15
16
Reserved
R-0
4
3
2
1
0
Reserved
R-0
SRST MRST WRST POR
R-0 R-0 R-0 R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 6-22. Reset Type Status Register (RSTYPE) Field Descriptions
Bit
31:4
3
Field
Value Description
Reserved
SRST
Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.
System reset
0
1
System Reset was not the last reset to occur.
System Reset was the last reset to occur.
Max reset
2
1
0
MRST
WRST
POR
0
1
Max Reset was not the last reset to occur.
Max Reset was the last reset to occur.
Warm reset
0
1
Warm Reset was not the last reset to occur.
Warm Reset was the last reset to occur.
Power-on reset
0
1
Power-on Reset was not the last reset to occur.
Power-on Reset was the last reset to occur.
6.7.8 Reset Electrical Data/Timing
NOTE
If a configuration pin must be routed out from the device, the internal pullup/pulldown
(IPU/IPD) resistor should not be relied upon; TI recommends the use of an external
pullup/pulldown resistor.
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UNIT
Table 6-23. Timing Requirements for Reset(1) (2) (see Figure 6-10)
720, 800, 900, 1100
NO.
MIN
256D
24C
MAX
5
6
tw(POR)
Pulse duration, POR low(3)
ns
ns
tw(RESET)
Pulse duration, RESET low
Setup time, boot mode and configuration pins valid before POR high or
RESET high
7
8
tsu(boot)
th(boot)
6P
6P
ns
ns
(4)
Hold time, boot mode and configuration pins valid after POR high or RESET
(4)
high
(1) C = 1/CLKIN1 clock frequency in ns
(2) D = 1/CLKIN2 clock frequency in ns
(3) If CLKIN2 is not used, tw(POR) must be measured in terms of CLKIN1 cycles; otherwise, use the slower of the CLKIN1,CLKIN2 cycles.
(4) P = 1/CPU clock frequency in nanoseconds
Table 6-24. Switching Characteristics Over Recommended Operating Conditions During Reset(1)
(see Figure 6-10)
720, 800, 900, 1100
NO.
PARAMETER
UNIT
MIN
MAX
9
td(PORH-RSTATH)
Delay time, POR high AND RESET high to RESETSTAT high
1500C
ns
(1) C = 1/CLKIN1 clock frequency in ns.
•
Z group consists of: all I/O/Z and O/Z pins, except for Low and High group pins. Pins become high
impedance as soon as their respective power supply has reached normal operating conditions. Pins
remain in high impedance until configured otherwise by their respective peripherals.
•
•
•
•
Low group consists of pins that become low as soon as their respective power supply has reached
normal operating conditions. Pins remain low until configured otherwise by their respective peripheral.
High group consists of pins that become high as soon as their respective power supply has reached
normal operating conditions. Pins remain high until configured otherwise by their respective peripheral.
All peripherals must be enabled through software following a power-on reset; for more details, see
Section 6.7.1, Power-on Reset.
For power-supply sequence requirements, see Section 6.3.1.
A. RESET should be used only after the device has been powered up. For more details on the use of the RESET pin,
see Section 6.7, Reset Controller.
B. A reset signal is generated internally during a Warm Reset. This internal reset signal has the same effect as the
RESET pin during a Warm Reset.
C. Boot and Device Configuration Inputs (during reset) include AEA[22:11], and UHPIEN.
Figure 6-10. Warm Reset and Max Reset Timing
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6.8 Interrupts
The C64x+ DSP interrupt controller combines device events into 12 prioritized interrupts. The source for
each of the 12 CPU interrupts is user programmable. Also, the interrupt controller controls the generation
of the CPU exception, NMI, and emulation interrupts and the generation of AEG events. Table 6-26
summarizes the C64x+ interrupt controller registers and memory locations. For more details on DSP
interrupt control, see TMS320DM647/TMS320DM648 DSP Subsystem Reference Guide (literature
number SPRUEU6).
Table 6-25. DSP Interrupt Events
DSP
EVENT
INTERRUPT SOURCE
INTERRUPT
NUMBER
0
EVT0
EVT1
EVT2
EVT33
Output of event combiner 0, for events 1 – 31
Output of event combiner 1, for events 32 – 63
Output of event combiner 2, for events 64 – 95
Output of event combiner 3, for events 96 – 127
Reserved
1
2
3
4-8
9
EMU_DTDMA
ECM interrupt for:
•
•
•
Host scan access event
DTDMA transfer complete event
AET interrupt event
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30 -31
32
33
34
35
36
37
38
39
Reserved
Reserved
EMU_RTDXRX
EMU_RTDXTX
IDMA0 EMC
IDMA1 EMC
HINT
RTDX receive complete event
RTDX transmit complete event
C64x+ EMC 0 event
C64x+ EMC 1 event
Host (PCI/HPI) to DSP interrupt event
I2C interrupt event
I2CINT
Reserved
Reserved
AEASYNCERR event
TINT2L
EMIFA Error Interrupt event
Timer interrupt low event
Timer interrupt high event
Timer interrupt low event
Timer interrupt high event
PSC-ALLINT event
TINT2H
TINT3L
TINT3H
PSCINT
TPCC_GINT
SPIINT0
EDMA3 channel global completion interrupt event
SPI Interrupt
SPIINT1
SPI Interrupt
DSQINT
VICP – Sqr (DSP int)
IMXINT
VICP – IMX
VLCDINT
VICP - VLCD
Reserved
Reserved
RX_PULSE
RX_THRESH_PULSE
TX_PULSE
MISC_PULSE
UART_INT
VP0_INT
Ethernet Subsystem RX pulse interrupt event
Ethernet Subsystem RX threshold interrupt event
Ethernet Subsystem TX pulse interrupt event
Ethernet Subsystem MISC pulse interrupt event
UART Interrupt
VP0 Interrupt
VP1_INT
VP1 Interrupt
VP2_INT
VP2 Interrupt
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Table 6-25. DSP Interrupt Events (continued)
DSP
EVENT
INTERRUPT SOURCE
INTERRUPT
NUMBER
40
41
42
43
44
45-49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
VP3_INT
VP4_INT
GPIO_BNK1_INT
AXINT
VP3 Interrupt
VP4 Interrupt
(GPIO16:31) GPIO Bank 1 Interrupt event
TX Interrupt McASP
ARINT
RX Interrupt McASP
Reserved
VINT
VLYNQ Pulse Interrupt event
GPIO Interrupt event
GPINT0
GPINT1
GPIO Interrupt event
GPINT2
GPIO Interrupt event
GPINT3
GPIO Interrupt event
GPINT4
GPIO Interrupt event
GPINT5
GPIO Interrupt event
GPINT6
GPIO Interrupt event
GPINT7
GPIO Interrupt event
GPINT8
GPIO Interrupt event
GPINT9
GPIO Interrupt event
GPINT10
GPIO Interrupt event
GPINT11
GPIO Interrupt event
GPINT12
GPIO Interrupt
GPINT13
GPIO Interrupt
GPINT14
GPIO Interrupt event
GPINT15
GPIO Interrupt event
TINT0L
Timer interrupt low event
Timer interrupt high event
Timer interrupt low event
Timer interrupt high event
EDMA3CC Completion Interrupt - Mask0 event
EDMA3CC Completion Interrupt – Mask1 event
EDMA3CC Completion Interrupt – Mask2 event
EDMA3CC Completion Interrupt – Mask3 event
EDMA3CC Completion Interrupt – Mask4 event
EDMA3CC Completion Interrupt – Mask5 event
EDMA3CC Completion Interrupt – Mask6 event
EDMA3CC Completion Interrupt – Mask7 event
EDMA3CC Error Interrupt event
EDMA3CC Memory Protection Interrupt event
EDMA3TC0 Error Interrupt event
EDMA3TC1 Error Interrupt event
EDMA3TC2 Error Interrupt event
EDMA3TC3 Error Interrupt event
Reserved
TINT0H
TINT1L
TINT1H
EDMA3CC_INT0
EDMA3CC_INT1
EDMA3CC_INT2
EDMA3CC_INT3
EDMA3CC_INT4
EDMA3CC_INT5
EDMA3CC_INT6
EDMA3CC_INT7
EDMA3CC_ERRINT
EDMA3CC_MPINT
EDMA3TC0_ERRINT
EDMA3TC1_ERRINT
EDMA3TC2_ERRINT
EDMA3TC3_ERRINT
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
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Table 6-25. DSP Interrupt Events (continued)
DSP
EVENT
INTERRUPT SOURCE
INTERRUPT
NUMBER
90
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
INTERR
Reserved
91
Reserved
92
Reserved
93
Reserved
94
Reserved
95
Reserved
96
C64x+ Interrupt Controller Dropped CPU Interrupt Event
C64x+ EMC Invalid IDMA Parameters event
Reserved
97
EMC_IDMAERR
Reserved
Reserved
EFIINTA
98
99
Reserved
100
101
102 - 112
113
114-115
116
117
118
119
120
121
122
123
124
125
126
127
EFI Interrupt from side A event
EFI Interrupt from side B event
Reserved
EFIINTB
Reserved
L1P_ED
L1P Single bit error detected during DMA read event
Reserved
Reserved
L2_ED1
L2 single bit error detected event
L2 two bit error detected event
Power Down sleep interrupt event
Reserved
L2_ED2
PDC_INT
Reserved
L1P_CMPA
L1P_DMPA
L1D_CMPA
L1D_DMPA
L2_CMPA
L2_DMPA
IDMA_CMPA
IDMA_BUSERR
L1P CPU memory protection fault event
L1P DMA memory protection fault event
L1D CPU memory protection fault event
L1D DMA memory protection fault event
L2 CPU memory protection fault event
L2 DMA memory protection fault event
IDMA CPU memory protection fault event
IDMA bus error interrupt event
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Table 6-26. C64x+ Interrupt Controller Registers
HEX ADDRESS
0x0180 0000
0x0180 0004
0x0180 0008
0x0180 000C
0x0180 0020
0x0180 0024
0x0180 0028
0x0180 002C
0x0180 0040
0x0180 0044
0x0180 0048
0x0180 004C
0x0180 0080
0x0180 0084
0x0180 0088
0x0180 008C
0x0180 00A0
0x0180 00A4
0x0180 00A8
0x0180 00AC
0x0180 00C0
0x0180 00C4
0x0180 00C8
0x0180 00CC
0x0180 00E0
0x0180 00E4
0x0180 00E8
0x0180 00EC
0x0180 0104
0x0180 0108
0x0180 010C
0x0180 0140
0x0180 0144
0x0180 0180
0x0180 0184
0x0180 0188
0x0180 01C0
ACRONYM
EVTFLAG0
EVTFLAG1
EVTFLAG2
EVTFLAG3
EVTSET0
REGISTER DESCRIPTION
Event flag register 0
Event flag register 1
Event flag register 2
Event flag register 3
Event set register 0
EVTSET1
Event set register 1
EVTSET2
Event set register 2
EVTSET3
Event set register 3
EVTCLR0
Event clear register 0
EVTCLR1
Event clear register 1
EVTCLR2
Event clear register 2
EVTCLR3
Event clear register 3
EVTMASK0
EVTMASK1
EVTMASK2
EVTMASK3
MEVTFLAG0
MEVTFLAG1
MEVTFLAG2
MEVTFLAG3
EXPMASK0
EXPMASK1
EXPMASK2
EXPMASK3
MEXPFLAG0
MEXPFLAG1
MEXPFLAG2
MEXPFLAG3
INTMUX1
Event mask register 0
Event mask register 1
Event mask register 2
Event mask register 3
Masked event flag register 0
Masked event flag register 1
Masked event flag register 2
Masked event flag register 3
Exception mask register 0
Exception mask register 1
Exception mask register 2
Exception mask register 3
Masked exception flag register 0
Masked exception flag register 1
Masked exception flag register 2
Masked exception flag register 3
Interrupt mux register 1
Interrupt mux register 2
Interrupt mux register 3
Advanced event generator mux register 0
Advanced event generator mux register 1
Interrupt exception status
Interrupt exception clear
Dropped interrupt mask register
Event assert register
INTMUX2
INTMUX3
AEGMUX0
AEGMUX1
INTXSTAT
INTXCLR
INTDMASK
EVTASRT
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6.9 DDR2 Memory Controller
The 32-bit DDR2 memory controller bus of the device is used to interface to JESD79D-2A
standard-compliant DDR2 SDRAM devices. The DDR2 external bus interfaces only to DDR2 SDRAM
devices; it does not share the bus with any other types of peripherals. The decoupling of DDR2 memories
from other devices simplifies board design and provides I/O concurrency from a second external memory
interface, EMIFA.
The internal data bus clock frequency and DDR2 bus clock frequency directly affect the maximum
throughput of the DDR2 bus. The data rate of the DDR2 bus is equal to the CLKIN2 frequency multiplied
by 20. The internal data bus clock frequency of the DDR2 memory controller is fixed at a divide-by-three
ratio of the CPU frequency. The maximum DDR2 throughput is determined by the smaller of the two bus
frequencies. For example, if the internal data bus frequency is 300 MHz (CPU frequency is 900 MHz) and
the DDR2 data rate is 533 MHz (266 MHz clock rate as CLKIN2 frequency is 26.6 MHz), the maximum
data rate achievable by the DDR2 memory controller is 2.13 Gbytes/sec.
6.9.1 DDR2 Memory Controller Device-Specific Information
The approach to specifying interface timing for the DDR2 memory bus is different than on other interfaces
such as EMIF and HPI. For these other interfaces, the device timing was specified in terms of data
manual specifications and I/O buffer information specification (IBIS) models.
For the DDR2 memory bus, the approach is to specify compatible DDR2 devices and provide the printed
circuit board (PCB) solution and guidelines directly to the user. Texas Instruments (TI) has performed the
simulation and system characterization to be sure all DDR2 interface timings in this solution are met.
The ODT[1:0] pins of the memory controller must be left unconnected. The ODT pins on the DDR2
memory device(s) must be connected to ground.
The DDR2 memory controller on the device supports the following memory topologies:
•
•
A 32-bit wide configuration interfacing to two 16-bit wide DDR2 SDRAM devices.
A 16-bit wide configuration interfacing to a single 16-bit wide DDR2 SDRAM device.
A race condition may exist when certain masters write data to the DDR2 memory controller. For example,
if master A passes a software message via a buffer in external memory and does not wait for indication
that the write completes, when master B attempts to read the software message, then the master B read
may bypass the master A write and, thus, master B may read stale data and, therefore, receive an
incorrect message.
Some master peripherals (e.g., EDMA3 transfer controllers) will always wait for the write to complete
before signaling an interrupt to the system, thus avoiding this race condition. For masters that do not have
hardware specification of write-read ordering, it may be necessary to specify data ordering via software.
If master A does not wait for indication that a write is complete, it must perform the following workaround:
1. Perform the required write.
2. Perform a dummy write to the DDR2 memory controller module ID and revision register.
3. Perform a dummy read to the DDR2 memory controller module ID and revision register.
4. Indicate to master B that the data is ready to be read after completion of the read in step 3. The
completion of the read in step 3 ensures that the previous write was done.
The master peripherals that need to implement this workaround are HPI, PCI, and VLYNQ.
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6.9.2 DDR2 Memory Controller Peripheral Registers
Table 6-27. DDR2 Memory Controller Registers(1)
HEX ADDRESS RANGE
0x7800 0000
ACRONYM
REGISTER NAME
MIDR
DDR2 Memory Controller Module and Revision Register
0x7800 0004
DMCSTAT
DDR2 Memory Controller Status Register
0x7800 0008
SDCFG
DDR2 Memory Controller SDRAM Configuration Register
0x7800 000C
SDRFC
DDR2 Memory Controller SDRAM Refresh Control Register
0x7800 0010
SDTIM1
DDR2 Memory Controller SDRAM Timing 1 Register
0x7800 0014
SDTIM2
DDR2 Memory Controller SDRAM Timing 2 Register
0x7800 0018
-
Reserved
0x7800 0020
BPRIO
DDR2 Memory Controller Burst Priority Register
0x7800 0024 - 0x7800 004C
0x7800 0050 - 0x7800 0078
0x7800 007C - 0x7800 00BC
0x7800 00C0 - 0x7800 00E0
0x7800 00E4
-
Reserved
-
Reserved
-
Reserved
-
Reserved
DMCCTL
DDR2 Memory Controller Control Register
0x7800 00E8 - 0x7800 00FC
0x7800 0100 - 0x7FFF FFFF
-
-
Reserved
Reserved
(1) For details about the DDR2 registers and their modes, see the TMS320DM647/DM648 DSP DDR2 Memory Controller (DDR2) User's
Guide (literature number SPRUEK5).
6.9.3 DDR2 Interface
This section provides the timing information for the DDR2 interface as a PCB design and manufacturing
specification. The design rules constrain PCB trace length, PCB trace skew, signal integrity, cross-talk,
and signal timing. These rules, when followed, result in a reliable DDR2 memory system without the need
for a complex timing closure process. For more information regarding guidelines for using this DDR2
specification, Understanding TI's PCB Routing Rule-Based DDR2 Timing Specification (SPRAAV0).
6.9.3.1 DDR2 Interface Schematic
Figure 6-11 shows the DDR2 interface schematic for a x32 DDR2 memory system. The x16 DDR2 system
schematic shown in Figure 6-12 is identical except that the high word DDR2 device is deleted.
6.9.3.2 Compatible JEDEC DDR2 Devices
Table 6-28 shows the parameters of the JEDEC DDR2 devices that are compatible with this interface.
Generally, the DDR2 interface is compatible with x16 DDR2-533 speed grade DDR2 devices.
Table 6-28. Compatible JEDEC DDR2 Devices
NO.
1
PARAMETER
MIN
MAX
UNIT
JEDEC DDR2 Device Speed Grade(1)
JEDEC DDR2 Device Bit Width
JEDEC DDR2 Device Count(2)
JEDEC DDR2 Device Ball Count(3)
DDR2-533
2
x16
1
x16
2
Bits
Devices
Balls
3
4
84
92
(1) Higher DDR2 speed grades are supported due to inherent JEDEC DDR2 backwards compatibility.
(2) One DDR2 device is used for 16-bit DDR2 memory system. Two DDR2 devices are used for 32-bit DDR2 memory system.
(3) 92 ball devices retained for legacy support. New designs will migrate to 84 ball DDR2 devices. Electrically, the 92 and 84 ball DDR2
devices are the same.
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DM647/DM648
DDR2
ODT
DDR_ODT0
DDR_D00
NC
BED0
T
T
DDR_D7
BED7
LDM
LDQS
DDR_DQM0
DDR_DQS0
T
T
DDR_DQS0
DDR_D08
T
T
LDQS
BED8
DDR_D15
DDR_DQM1
DDR_DQS1
BED15
UDM
T
T
T
UDQS
DDR_DQS1
T
UDQS
T
DDR_DQGATE0
DDR_DQGATE1
DDR_DQGATE2
DDR_DQGATE3
T
DDR2
ODT
DDR_ODT1
DDR_D16
NC
BED0
T
DDR_D23
DDR_DQM2
DDR_DQS2
BED0
LDM
LDQS
T
T
T
DDR_DQS2
DDR_D24
LDQS
BED7
T
T
DDR_D31
DDR_DQM3
DDR_DQS3
DDR_DQS3
BED15
UDM
T
T
T
T
UDQS
UDQS
DDR_BA0
T
BA0
BA0
DDR_BA2
DDR_A00
T
T
BA2
A0
BA2
A0
DDR_A13
DDR_CS0
DDR_CAS
DDR_RAS
T
T
T
T
T
T
A13
CS
A13
CS
CAS
RAS
CAS
RAS
Vio 1.8(A)
BSDWE
DDR_CKE
DDR_CLK
WE
CKE
CK
WE
CKE
CK
T
T
0.1 µF
1 kΩ 1%
CK
CK
DDR_CLK
DDR_VREF
VREF VREF
VREF VREF
VREF
(B)
(B)
(B)
0.1 µF
0.1 µF
1 kΩ 1%
0.1 µF
0.1 µF
T
Terminator, if desired. See terminator comments.
A. DM648 is shown in this figure as an example of the device and represents the entire set of devices that include:
DM647/DM648.
B. Vio 1.8 is the power supply for the DDR2 memory interface.
C. One of these capacitors can be eliminated if the divider and its capacitors are placed near a device VREF pin.
Figure 6-11. 32-Bit DDR2 High-Level Schematic
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DM647/DM648
DDR2
ODT
DDR_ODT0
DDR_D00
NC
BED0
T
T
DDR_D7
BED7
LDM
LDQS
DDR_DQM0
DDR_DQS0
T
T
DDR_DQS0
DDR_D08
T
T
LDQS
BED8
DDR_D15
DDR_DQM1
DDR_DQS1
BED15
UDM
T
T
T
UDQS
DDR_DQS1
T
UDQS
T
DDR_DQGATE0
DDR_DQGATE1
DDR_DQGATE2
DDR_DQGATE3
NC
1 kΩ
DDR_ODT1
DDR_D16
NC
NC
Vio 1.8(A)
DDR_D23
DDR_DQM2
NC
NC 1 kΩ
DDR_DQS2
DDR_DQS2
NC
DDR_D24
1 kΩ
Vio 1.8(A)
DDR_D31
DDR_DQM3
DDR_DQS3
DDR_DQS3
NC
NC
1 kΩ
1 kΩ
DDR_BA0
T
BA0
DDR_BA2
DDR_A00
T
T
BA2
A0
DDR_A13
DDR_CS0
DDR_CAS
DDR_RAS
T
T
T
T
T
T
A13
CS
CAS
RAS
Vio 1.8(A)
BSDWE
DDR_CKE
DDR_CLK
WE
CKE
CK
T
T
0.1 µF
1 kΩ 1%
CK
DDR_CLK
DDR_VREF
VREF VREF
VREF
(B)
(B)
0.1 µF
1 kΩ 1%
0.1 µF
0.1 µF
T
Terminator, if desired. See terminator comments.
A. DM648 is shown in this figure as an example of the device and represents the entire set of devices that include:
DM647/DM648.
B. Vio 1.8 is the power supply for the DDR2 memory interface.
C. One of these capacitors can be eliminated if the divider and its capacitors are placed near a device VREF pin.
Figure 6-12. 16-Bit DDR2 High-Level Schematic
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6.9.3.3 PCB Stackup
The minimum stackup required for routing the device is a six-layer stack as shown in Table 6-29.
Additional layers may be added to the PCB stack up to accommodate other circuity or to reduce the size
of the PCB footprint.
Table 6-29. Minimum PCB Stack Up
LAYER
TYPE
Signal
Plane
Plane
Signal
Plane
Signal
DESCRIPTION
Top routing mostly horizontal
Ground
1
2
3
4
5
6
Power
Internal routing
Ground
Bottom routing mostly vertical
Complete stack up specifications are provided in Table 6-30.
Table 6-30. PCB Stack Up Specifications
NO.
1
PARAMETER
MIN
6
TYP
MAX UNIT
PCB Routing/Plane Layers
2
Signal Routing Layers
3
3
Full ground layers under DDR2 routing Region
Number of ground plane cuts allowed within DDR routing region
Number of ground reference planes required for each DDR2 routing layer
Number of layers between DDR2 routing layer and reference ground plane
PCB Routing Feature Size
2
4
0
5
1
6
0
7
4
4
Mils
Mils
Mils
Mils
8
PCB Trace Width w
8
PCB BGA escape via pad size
18
8
9
PCB BGA escape via hole size
10
11
12
13
DSP Device BGA pad size(1)
DDR2 Device BGA pad size(2)
Single Ended Impedance, Zo
Impedance Control(3)
50
75
Ω
Ω
Z-5
Z
Z+5
(1) See the Flip Chip Ball Grid Array Package Reference Guide (SPRU811) for DSP device BGA pad size.
(2) See the DDR2 device manufacturer documenation for the DDR2 device BGA pad size.
(3) Z is the nominal singled ended impedance selected for the PCB specified by item 12.
6.9.3.4 Placement
Figure 6-13 shows the required placement for the device as well as the DDR2 devices. The dimensions
for Figure 6-13 are defined in Table 6-31. The placement does not restrict the side of the PCB where the
devices are mounted. The purpose of the placement is to limit the maximum trace lengths and allow for
proper routing space. For 16-bit DDR memory systems, the high word DDR2 device is omitted from the
placement.
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X
A1
Y
OFFSET
DDR2
Device
Y
DM648
Y
OFFSET
A1
Recommended DDR2 Device
Orientation
A. DM648 is shown in this figure as an example of the device and represents the entire set of devices that include:
DM647/DM648.
Figure 6-13. DDR2 Device Placement
Table 6-31. Placement Specifications
NO.
1
PARAMETER
X(1) (2)
Y(1) (2)
Y Offset(1) (2) (3)
MIN
MAX
1660
1280
650
UNIT
Mils
Mils
Mils
2
3
4
DDR2 Keepout Region(4)
5
Clearance from non-DDR2 signal to DDR2 Keepout Region(5)
4
w
(1) See Figure 6-11 for dimension defintions.
(2) Measurements from center of DSP device to center of DDR2 device.
(3) For 16-bit memory systems, it is recommended that Y Offset be as small as possible.
(4) DDR2 Keepout region to encompass entire DDR2 routing area
(5) Non-DDR2 signals allowed within DDR2 keepout region provided they are separated from DDR2 routing layers by a ground plane.
6.9.3.5 DDR2 Keep Out Region
The region of the PCB used for the DDR2 circuitry must be isolated from other signals. The DDR2 keep
out region is defined for this purpose and is shown in Figure 6-14. The size of this region varies with the
placement and DDR routing. Additional clearances required for the keep out region are shown in
Table 6-31.
A1
DDR2 Device
A1
Figure 6-14. DDR2 Keepout Region
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NOTE
The region (see Figure 6-14) should encompass all DDR2 circuitry and varies depending
on placement. Non-DDR2 signals should not be routed on the DDR signal layers within
the DDR2 keep out region. Non-DDR2 signals may be routed in the region provided they
are routed on layers separated from DDR2 signal layers by a ground layer. No breaks
should be allowed in the reference ground layers in this region. In addition, the 1.8-V
power plane should cover the entire keep out region.
6.9.3.6 Bulk Bypass Capacitors
Bulk bypass capacitors are required for moderate speed bypassing of the DDR2 and other circuitry.
Table 6-32 contains the minimum numbers and capacitance required for the bulk bypass capacitors. This
table covers only the bypass needs of the DSP and DDR2 interfaces. Additional bulk bypass capacitance
may be needed for other circuitry.
Table 6-32. Bulk Bypass Capacitors
NO. PARAMETER
MIN
3
MAX
UNIT
Devices
mF
1
2
3
4
5
6
DVDD18 Bulk Bypass Capacitor Count(1)
DVDD18 Bulk Bypass Total Capacitance
DDR#1 Bulk Bypass Capacitor Count(1)
DDR#1 Bulk Bypass Total Capacitance
DDR#2 Bulk Bypass Capacitor Count(1) (2)
DDR#2 Bulk Bypass Total Capacitance(2)
30
1
Devices
mF
10
1
Devices
mF
10
(1) These devices should be placed near the device they are bypassing, but preference should be given to the placement of the high-speed
(HS) bypass caps.
(2) Only used on 32-bit wide DDR2 memory systems
6.9.3.7 High-Speed Bypass Capacitors
High-Speed (HS) bypass capacitors are critical for proper DDR2 interface operation. It is particularly
important to minimize the parasitic series inductance of the HS bypass cap, DSP/DDR power, and
DSP/DDR ground connections. Table 6-33 contains the specification for the HS bypass capacitors as well
as for the power connections on the PCB.
6.9.3.8 Net Classes
Table 6-34 lists the clock net classes for the DDR2 interface. Table 6-35 lists the signal net classes, and
associated clock net classes, for the signals in the DDR2 interface. These net classes are used for the
termination and routing rules that follow.
Table 6-33. High-Speed Bypass Capacitors
NO. PARAMETER
MIN
MAX
0402
250
UNIT
10 Mils
Mils
1
2
3
4
5
6
7
8
9
HS Bypass Capacitor Package Size(1)
Distance from HS bypass capacitor to device being bypassed
Number of connection vias for each HS bypass capacitor(2)
Trace length from bypass capacitor contact to connection via
Number of connection vias for each DDR2 device power or ground balls
Trace length from DDR2 device power ball to connection via
DVDD18 HS Bypass Capacitor Count(3)
2
1
1
Vias
30
35
Mils
Vias
Mils
20
1.2
8
Devices
mF
DVDD18 HS Bypass Capacitor Total Capacitance
DDR#1 HS Bypass Capacitor Count(3)
Devices
(1) L × W, 10 mil units ( i.e., a 0402 is a 40 × 20 mil surface mount capacitor)
(2) An additional HS bypass capacitor can share the connection vias only if it is mounted on the opposite side of the board.
(3) These devices should be placed as close as possible to the device being bypassed.
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Table 6-33. High-Speed Bypass Capacitors (continued)
NO. PARAMETER
MIN
0.4
8
MAX
UNIT
mF
10 DDR#1 HS Bypass Capacitor Total Capacitance
11 DDR#2 HS Bypass Capacitor Count(3) (4)
12 DDR#2 HS Bypass Capacitor Total Capacitance(4)
Devices
mF
0.4
(4) Only used on 32-bit wide DDR2 memory systems
Table 6-34. Clock Net Class Definitions
CLOCK NET CLASS
DSP PIN NAMES
CK
DDR_CLK/DDR_CLK
DQS0
DDR_DQS0/DDR_DQS0
DDR_DQS1/DDR_DQS1
DDR_DQS2/DDR_DQS2
DDR_DQS3/DDR_DQS3
DQS1
DQS2(1)
DQS3(1)
(1) Only used on 32-bit wide DDR2 memory systems.
Table 6-35. Signal Net Class Definitions
CLOCK NET CLASS
ASSOCIATED CLOCK NET CLASS
DSP PIN NAMES
ADDR_CTRL
CK
DDR_BA[2:0], DDR_A[13:0], DDR_CS, DDR_CAS, DDR_RAS,
DDR_WE, DDR_CKE
DQ0
DQ1
DQS0
DDR_D[7:0], DDR_DQM0
DQS1
DDR_D[15:8], DDR_DQM1
DQ2(1)
DQ3(1)
DQS2
DDR_D[23:16], DDR_DQM2
DDR_D[31:24], DDR_DQM3
DDR_DQGATE0, DDR_DQGATE1
DDR_DQGATE2, DDR_DQGATE3
DQS3
DQGATEL
DQGATEH(1)
CK, DQS0, DQS1
CK, DQS2, DQS3
(1) Only used on 32-bit wide DDR2 memory systems.
6.9.3.9 DDR2 Signal Termination
No terminations of any kind are required in order to meet signal integrity and overshoot requirements.
Serial terminators are permitted, if desired, to reduce EMI risk; however, serial terminations are the only
type permitted. Table 6-36 shows the specifications for the series terminators.
Table 6-36. DDR2 Signal Terminations
NO.
1
PARAMETER
CK Net Class(1)
ADDR_CTRL Net Class(1) (2) (3)
Data Byte Net Classes (DQS0-DQS3, DQ0-DQ3)(1) (2) (3) (4)
DQGATE Net Classes (DQGATEL, DQGATEH)(1) (2) (3)
MIN
0
TYP
MAX UNIT
10
Zo
Zo
Zo
Ω
Ω
Ω
Ω
2
0
22
22
10
3
0
4
0
(1) Only series termination is permitted, parallel or SST specifically disallowed.
(2) Terminator values larger than typical only recommended to address EMI issues.
(3) Termination value should be uniform across net class.
(4) When no termination is used on data lines (0 Ωs), the DDR2 devices must be programmed to operate in 60% strength mode.
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6.9.3.10 VREF Routing
VREF is used as a reference by the input buffers of the DDR2 memories as well as the device’s. VREF is
intended to be 1/2 the DDR2 power supply voltage and should be created using a resistive divider as
shown in Figure 6-11. Other methods of creating VREF are not recommended. Figure 6-15 shows the
layout guidelines for VREF.
VREF Bypass Capacitor
DDR2 Device
A1
VREF Nominal Minimum
Trace Width is 20 Mils
DM648
Device
A1
Neck down to minimum in BGA escape regions
is acceptable. Narrowing to accommodate via
congestion for short distances is also acceptable.
Best performance is obtained if the width of
VREF is maximized.
A. DM648 is shown in this figure as an example of the device and represents the entire set of devices that include:
DM647/DM648.
Figure 6-15. VREF Routing and Topology
6.9.3.11 DDR2 CK and ADDR_CTRL Routing
Figure 6-16 shows the topology of the routing for the CK and ADDR_CTRL net classes. The route is a
balanced T as it is intended that the length of segments B and C be equal. In addition, the length of A
should be maximized.
A1
T
A
DM648
A1
A. DM648 is shown in this figure as an example of the device and represents the entire set of devices that include:
DM647/DM648.
Figure 6-16. CK and ADDR_CTRL Routing and Topology
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UNIT
Table 6-37. CK and ADDR_CTRL Routing Specification(1)
NO
1
PARAMETER
MIN
TYP
MAX
2w
Center to center CK-CK spacing
2
CK A to B/A to C Skew Length Mismatch(1)
25
Mils
Mils
3
CK B to C Skew Length Mismatch
25
4
Center to center CK to other DDR2 trace spacing(2)
CK/ADDR_CTRL nominal trace length(3)
4w
5
CACLM-50
CACLM
CACLM+50
100
Mils
Mils
Mils
6
ADDR_CTRL to CK Skew Length Mismatch
ADDR_CTRL to ADDR_CTRL Skew Length Mismatch
Center to center ADDR_CTRL to other DDR2 trace spacing(2)
Center to center ADDR_CTRL to other ADDR_CTRL trace spacing(2)
ADDR_CTRL A to B/A to C Skew Length Mismatch(1)
ADDR_CTRL B to C Skew Length Mismatch
7
100
8
4w
3w
9
10
11
100
100
Mils
Mils
(1) Series terminator, if used, should be located closest to DSP.
(2) Center to center spacing is allowed to fall to minimum (w) for up to 500 mils of routed length to accommodate BGA escape and routing
congestion.
(3) CACLM is the longest Manhattan distance of the CK and ADDR_CTRL net classes.
Figure 6-17 shows the topology and routing for the DQS and DQ net classes; the routes are point to point.
Skew matching across bytes is not needed nor recommended.
T
E0
A1
T
E1
DM648
T
E2
A1
T
E3
A. DM648 is shown in this figure as an example of the device and represents the entire set of devices that include:
DM647/DM648.
Figure 6-17. DQS and DQ Routing and Toplogy
(1)
Table 6-38. DQS and DQ Routing Specification
NO.
1
PARAMETER
MIN
TYP
MAX
2 w
25
UNIT
Center to center DQS-DQS spacing
DQS E Skew Length Mismatch
2
Mils
3
Center to center DQS to other DDR2 trace spacing(2)
DQS/DQ nominal trace length(1) (3) (4) (5)
DQ to DQS Skew Length Mismatch(3) (4) (5)
DQ to DQ Skew Length Mismatch(3) (4) (5)
4 w
4
DQLM-50
DQLM
DQLM+50
100
Mils
Mils
Mils
5
6
100
(1) Series terminator, if used, should be located closest to DDR.
(2) Center to center spacing is allowed to fall to minimum (w) for up to 500 mils of routed length to accommodate BGA escape and routing
congestion.
(3) A 16-bit DDR memory system has two sets of data net classes, one for data byte 0, and one for data byte 1, each with an associated
DQS (2 DQSs).
(4) A 32-bit DDR memory system will have four sets of data net classes, one each for data bytes 0 through 3, and each associated with a
DQS (4 DQSs).
(5) There is no need and it is not recommended to skew match across data bytes, i.e., from DQS0 and data byte 0 to DQS1 and data byte
1.
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(1)
Table 6-38. DQS and DQ Routing Specification
(continued)
NO.
7
PARAMETER
MIN
TYP
MAX
UNIT
Center to center DQ to other DDR2 trace spacing(2) (6)
Center to Center DQ to other DQ trace spacing(7) (2)
DQ/DQS E Skew Length Mismatch(3) (4) (5)
4 w
3w
8
9
100
Mils
(6) DQs from other DQS domains are considered other DDR2 trace.
(7) DQLM is the longest Manhattan distance of each of the DQS and DQ net classes.
Figure 6-18 shows the routing for the DQGATE net classes. Table 6-39 contains the routing specification.
A1
T
T
DM648
A1
A. DM648 is shown in this figure as an example of the device and represents the entire set of devices that include:
DM647/DM648.
Figure 6-18. DQGATE Routing
Table 6-39. DQGATE Routing Specification
NO.
1
PARAMETER
DQGATEL Length F(1)
DQGATEH Length F(2) (3)
MIN
TYP
MAX
UNIT
CKB0B1
CKB2B3
2
3
Center to center DQGATE to any other trace spacing
DQS/DQ nominal trace length
4 w
4
DQLM - 50
DQLM
DQLM +
50
Mils
5
6
DQGATEL Skew(4)
DQGATEH Skew(5) (3)
100
100
Mils
Mils
(1) CKB0B1 is the sum of the length of the CK net plus the average length of the DQS0 and DQS1 nets.
(2) CKB2B3 is the sum of the length of the CK net plus the average length of the DQS2 and DQS3 nets.
(3) Only used on 32-bit-wide DDR2 memory systems.
(4) Skew from CKB0B1
(5) Skew from CKB2B3
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6.10 External Memory Interface A (EMIFA)
The EMIFA can interface to a variety of external devices or ASICs, including:
•
•
•
•
Pipelined and flow-through synchronous-burst SRAM (SBSRAM)
ZBT (zero bus turnaround) SRAM and late write SRAM
Synchronous FIFOs
Asynchronous memory, including SRAM, ROM, and Flash
6.10.1 EMIFA Device-Specific Information
Timing analysis must be done to verify all ac timing requirements are met. TI recommends utilizing I/O
buffer information specification (IBIS) to analyze all ac timing.
To properly use IBIS models to attain accurate timing analysis for a given system, see the Using IBIS
Models for Timing Analysis Application Report (literature number SPRA839).
To maintain signal integrity, serial termination resistors should be inserted into all EMIFA output signal
lines.
A race condition may exist when certain masters write data to the EMIFA. For example, if master A
passes a software message via a buffer in external memory and does not wait for indication that the write
completes, when master B attempts to read the software message, then the master B read may bypass
the master A write and, thus, master B may read stale data and, therefore, receive an incorrect message.
Some master peripherals (e.g., EDMA3 transfer controllers) will always wait for the write to complete
before signaling an interrupt to the system, thus avoiding this race condition. For masters that do not have
hardware specification of write-read ordering, it may be necessary to specify data ordering via software.
If master A does not wait for indication that a write is complete, it must perform the following workaround:
1. Perform the required write.
2. Perform a dummy write to the EMIFA module ID and revision register.
3. Perform a dummy read to the EMIFA module ID and revision register.
4. Indicate to master B that the data is ready to be read after completion of the read in step 3. The
completion of the read in step 3 ensures that the previous write was done.
6.10.2 EMIFA Peripheral Register Description(s)
For more information on the EMIF registers shown in Table 6-40, see TMS320DM647/DM648 DSP
External Memory Interface (EMIF) User's Guide (literature number SPRUEK6).
Table 6-40. EMIFA Registers
HEX ADDRESS RANGE
0x7000 0000
ACRONYM
REGISTER NAME
Module ID and Revision Register
MIDR
0x7000 0004
STAT
Status Register
0x7000 0008
-
Reserved
0x7000 000C - 0x7000 001C
0x7000 0020
-
Reserved
BPRIO
Burst Priority Register
0x7000 0024 - 0x7000 004C
0x7000 0050 - 0x7000 007C
0x7000 0080
-
Reserved
-
Reserved
CE2CFG
EMIFA CE2 Configuration Register
EMIFA CE3 Configuration Register
Reserved
0x7000 0084
CE3CFG
0x7000 0088
-
0x7000 008C
-
Reserved
0x7000 0090 - 0x7000 009C
0x7000 00A0
-
Reserved
AWCC
EMIFA Async Wait Cycle Configuration Register
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Table 6-40. EMIFA Registers (continued)
HEX ADDRESS RANGE
ACRONYM
REGISTER NAME
0x7000 00A4 - 0x7000 00BC
0x7000 00C0
-
INTRAW
INTMSK
INTMSKSET
INTMSKCLR
-
Reserved
EMIFA Interrupt RAW Register
0x7000 00C4
EMIFA Interrupt Masked Register
EMIFA Interrupt Mask Set Register
EMIFA Interrupt Mask Clear Register
Reserved
0x7000 00C8
0x7000 00CC
0x7000 00D0 - 0x7000 00DC
0x7000 00E0 - 0x77FF FFFF
-
Reserved
6.10.3 EMIFA Electrical Data/Timing
Table 6-41. Timing Requirements for AECLKIN for EMIFA(1) (2) (see Figure 6-19)
720, 800, 900, 1100
NO.
UNIT
MIN
6(3)
2.7
MAX
16P(4)
1
2
3
4
5
tc(EKI)
tw(EKIH)
tw(EKIL)
tt(EKI)
Cycle time, AECLKIN
ns
ns
ns
ns
ns
Pulse duration, AECLKIN high
Pulse duration, AECLKIN low
Transition time, AECLKIN
Period Jitter, AECLKIN
2.7
2
tJ(EKI)
0.02E(5)
(1) The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN.
(2) E = the EMIF input clock (AECLKIN or SYSCLK4/2) period in ns for EMIFA.
(3) Minimum AECLKIN cycle times must be met, even when AECLKIN is generated by an internal clock source. Minimum AECLKIN times
are based on internal logic speed; the maximum useable speed of the EMIF may be lower due to AC timing requirements.
(4) P is P = 1/CPU clock frequency in ns.
(5) This timing applies only when AECLKIN is used for EMIFA.
1
5
4
2
AECLKIN
3
4
Figure 6-19. AECLKIN Timing for EMIFA
Table 6-42. Switching Characteristics Over Recommended Operating Conditions for AECLKOUT for the
EMIFA Module(1) (2) (3) (see Figure 6-20)
720, 800, 900, 1100
NO.
PARAMETER
UNIT
MIN
E - 0.7
MAX
1
2
3
4
5
6
tc(EKO)
Cycle time, AECLKOUT
E + 0.7
ns
ns
ns
ns
ns
ns
tw(EKOH)
tw(EKOL)
Pulse duration, AECLKOUT high
EH - 0.7
EL - 0.7
EH + 0.7
Pulse duration, AECLKOUT low
EL + 0.7
tt(EKO)
Transition time, AECLKOUT
1
8
8
td(EKIH-EKOH)
td(EKIL-EKOL)
Delay time, AECLKIN high to AECLKOUT high
Delay time, AECLKIN low to AECLKOUT low
1
1
(1) E = the EMIF input clock (AECLKIN or SYSCLK4/2) period in ns for EMIFA.
(2) The reference points for the rise and fall transitions are measured at VOL MAX and VOH MIN.
(3) EH is the high period of E (EMIF input clock period) in ns and EL is the low period of E (EMIF input clock period) in ns for EMIFA.
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AECLKIN
5
2
3
3
1
4
AECLKOUT
A. E = the EMIF input clock (AECLKIN or SYSCLK4/2) period in ns for EMIFA.
B. The reference points for the rise and fall transitions are measured at VOL MAX and VOH MIN.
C. EH is the high period of E (EMIF input clock period) in ns and EL is the low period of E (EMIF input clock period) in ns
for EMIFA.
Figure 6-20. AECLKOUT Timing for the EMIFA Module
6.10.3.1 Asynchronous Memory Timing
Table 6-43. Timing Requirements for Asynchronous Memory Cycles for EMIFA Module(1) (2) (3)
(see Figure 6-21 and Figure 6-22)
720, 800, 900, 1100
NO.
UNIT
MIN
MAX
3
4
5
6
7
tsu(EDV-A OEH)
th(AOEH-EDV)
tsu(ARDY-EKOH)
th(EKOH-ARDY)
tw(ARDY )
Setup time, AEDx valid before AAOE/ASOE high
Hold time, AEDx valid after AAOE/ASOE high
Setup time, AARDY valid before AECLKOUT low
Hold time, AARDY valid after AECLKOUT low
Pulse width, AARDY assertion and deassertion
6.5
ns
ns
ns
ns
ns
3
1
2
2E + 5
Delay time, from AARDY sampled deasserted on AECLKOUT falling
to beginning of programmed hold period
8
td(ARDY-HOLD)
4E
ns
Setup time, before end of programmed strobe period by which
AARDY should be asserted in order to insert extended strobe wait
states.
9
tsu(ARDY-HOLD)
2E
ns
(1) E = AECLKOUT period in ns for EMIFA
(2) To specify data setup time, simply program the strobe width wide enough.
(3) AARDY is internally synchronized. To use AARDY as an asynchronous input, the pulse width of the AARDY signal should be at least 2E
to specify setup and hold time is met.
Table 6-44. Switching Characteristics Over Recommended Operating Conditions for Asynchronous
Memory Cycles for EMIFA Module(1) (2) (3) (see Figure 6-21 and Figure 6-22)
720, 800, 900, 1100
NO.
PARAMETER
UNIT
MIN
RS × E - 1.5
RS × E - 1.9
1
MAX
7.28
7.1
1
tosu(SELV-AOEL)
toh(AOEH-SELIV)
td(EKOH-AOEV)
tosu(SELV-AWEL)
toh(AWEH-SELIV)
td(EKOH-AWEV)
Output setup time, select signals valid to AAOE/ASOE low
Output hold time, AAOE/ASOE high to select signals invalid
Delay time, AECLKOUT high to AAOE/ASOE valid
ns
ns
ns
ns
ns
ns
2
10
11
12
13
Output setup time, select signals valid to AAWE/ASWE low
Output hold time, AAWE/ASWE high to select signals invalid
Delay time, AECLKOUT high to AAWE/ASWE valid
WS × E - 1.7
WH × E - 1.8
1.3
(1) E = AECLKOUT period in ns for EMIFA
(2) RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold. These parameters
are programmed via the EMIFA CE Configuration registers (CEnCFG).
(3) Select signals for EMIFA include: ACEx, ABE[1:0], AEA[23:0], ABA[1:0]; and for EMIFA writes, also include AR/W, AED[15:0].
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Strobe = 4
Setup = 1
Hold = 1
AECLKOUT
2
2
1
1
ACEx
Byte Enables
Address
ABE[1:0]
2
1
AEA[23:0]/
ABA[1:0]
3
Read Data
4
AED[15:0]
10
10
AAOE/ASOE
AAWE/ASWE
AR/W
AARDY
DEASSERTED
A. AAOE/ASOE and AAWE/ASWE operate as AAOE/ASOE (identified under select signals) and AAWE/ASWE,
respectively, during asynchronous memory accesses.
B. Polarity of the AARDY signal is programmable through the AP field of the EMIFA Async Wait Cycle Configuration
register (AWCC).
Figure 6-21. Asynchronous Memory Read Timing for EMIFA
Strobe = 4
Hold = 1
Setup = 1
AECLKOUT
12
12
12
11
11
ACEx
ABE[1:0]
Byte Enables
Address
11
11
AEA[23:0]/
ABA[1:0]
12
Write Data
AED[15:0]
(A)
AAOE/ASOE
13
13
(A)
AAWE/ASWE
11
12
AR/W
(B)
AARDY
DEASSERTED
A. AAOE/ASOE and AAWE/ASWE operate as AAOE/ASOE and AAWE/ASWE (identified under select signals) during
asynchronous memory accesses.
B. Polarity of the AARDY signal is programmable through the AP field of the EMIFA Async Wait Cycle Configuration
register (AWCC).
Figure 6-22. Asynchronous Memory Write Timing for EMIFA
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Strobe
Strobe
Hold = 2
Setup = 2
Extended Strobe
8
9
AECLKOUT
6
5
7
7
(A)
ASSERTED
DEASSERTED
AARDY
A. Polarity of the AARDY signal is programmable through the AP field of the EMIFA Async Wait Cycle Configuration
register (AWCC).
Figure 6-23. AARDY Timing
6.10.3.2 Programmable Synchronous Interface Timing
Table 6-45. Timing Requirements for Programmable Synchronous Interface Cycles for EMIFA Module
(see Figure 6-24)
720, 800, 900, 1100
NO.
UNIT
MIN
2
MAX
6
7
tsu(EDV-EKOH)
th(EKOH-EDV)
Setup time, read AEDx valid before AECLKOUT high
Hold time, read AEDx valid after AECLKOUT high
ns
ns
1.5
Table 6-46. Switching Characteristics Over Recommended Operating Conditions for Programmable
Synchronous Interface Cycles for EMIFA Module(1) (see Figure 6-24-Figure 6-26)
720, 800, 900, 1100
NO.
PARAMETER
UNIT
MIN
MAX
4.9
1
2
td(EKOH-CEV)
td(EKOH-BEV)
td(EKOH-BEIV)
td(EKOH-EAV)
td(EKOH-EAIV)
td(EKOH-ADSV)
td(EKOH-OEV)
td(EKOH-EDV)
td(EKOH-EDIV)
td(EKOH-WEV)
Delay time, AECLKOUT high to ACEx valid
Delay time, AECLKOUT high to ABEx valid
Delay time, AECLKOUT high to ABEx invalid
Delay time, AECLKOUT high to AEAx valid
Delay time, AECLKOUT high to AEAx invalid
Delay time, AECLKOUT high to ASADS/ASRE valid
Delay time, AECLKOUT high to AAOE/ASOE valid
Delay time, AECLKOUT high to AEDx valid
Delay time, AECLKOUT high to AEDx invalid
Delay time, AECLKOUT high to AAWE/ASWE valid
1.3
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4.9
3
1.3
4
4.9
5
1.3
1.3
1.3
8
4.9
4.9
4.9
9
10
11
12
1.3
1.3
4.9
(1) The following parameters are programmable via the EMIFA CE Configuration registers (CEnCFG):
•
•
•
Read latency (R_LTNCY): 0-, 1-, 2-, or 3-cycle read latency
Write latency (W_LTNCY): 0-, 1-, 2-, or 3-cycle write latency
ACEx assertion length (CE_EXT): For standard SBSRAM or ZBT SRAM interface, ACEx goes inactive after the final command has
been issued (CE_EXT = 0). For synchronous FIFO interface with glue, ACEx is active when AAOE/ASOE is active (CE_EXT = 1).
Function of ASADS/ASRE (R_ENABLE): For standard SBSRAM or ZBT SRAM interface, ASADS/ASRE has deselect cycles
(R_ENABLE = 0). For FIFO interface, ASADS/ASRE has NO deselect cycles (R_ENABLE = 1).
•
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Strobe = 4
Setup = 1
Hold = 1
AECLKOUT
2
2
1
1
ACEx
Byte Enables
Address
ABE[1:0]
2
1
AEA[23:0]/
ABA[1:0]
3
Read Data
4
AED[15:0]
10
10
AAOE/ASOE
AAWE/ASWE
AR/W
AARDY
DEASSERTED
Figure 6-24. Programmable Synchronous Interface Read Timing for EMIFA (With Read Latency = 2)
NOTE
This information applies to Figure 6-25 and Figure 6-26.
The following parameters are programmable via the EMIF Chip Select n Configuration
Register (CESECn):
•
•
•
Read latency (R_LTNCY): 1-, 2-, or 3-cycle read latency
Write latency (W_LTNCY): 0-, 1-, 2-, or 3-cycle write latency
ACEx assertion length (CE_EXT): For standard SBSRAM or ZBT SRAM interface,
ACEx goes inactive after the final command has been issued (CE_EXT = 0). For
synchronous FIFO interface, ACEx is active when AAOE/ASOE is active (CE_EXT =
1).
•
Function of ASADS/ASRE (R_ENABLE): For standard SBSRAM or ZBT SRAM
interface, ASADS/ASRE has deselect cycles (R_ENABLE = 0). For FIFO interface,
ASADS/ASRE has NO deselect cycles (R_ENABLE = 1).
AECLKOUT
ACEx
1
2
1
3
ABE[1:0]
BE1
BE2
EA2
Q2
BE3
EA3
Q3
BE4
EA4
Q4
5
4
AEA[23:0]/ABA[1:0]
EA1
10
10
Q1
11
AED[15:0]
ASADS/ASRE
AAOE/ASOE
8
8
12
12
AAWE/ASWE
A. In this figure, W_LTNCY = 0, CE_EXT = 0, R_ENABLE = 0, and SSEL = 1.
Figure 6-25. Programmable Synchronous Interface Write Timing for EMIFA (With Write Latency = 0)
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Write
Latency = 1
AECLKOUT
1
1
3
ACEx
ABE[1:0]
2
BE1
BE2
BE3
EA3
Q2
BE4
EA4
Q3
5
4
AEA[23:0]/ABA[1:0]
AED[15:0]
EA1
10
EA2
10
11
8
Q1
Q4
8
ASADS/ASRE
AAOE/ASOE
12
12
AAWE/ASWE
Figure 6-26. Programmable Synchronous Interface Write Timing for EMIFA (With Write Latency = 1)
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6.11 Video Port
Each video port is capable of sending and receiving digital video data. The video ports are also capable of
capturing/displaying RAW data. The video port peripherals follow video standards such as BT.656 and
SMPTE296.
6.11.1 Video Port Device-Specific Information
The devices have five video port peripherals.
The video port peripheral can operate as a video capture port, video display port, or as a transport
channel interface (TCI) capture port.
The port consists of two channels: A and B. A 5120-byte capture/display buffer is splittable between the
two channels. The entire port (both channels) is always configured for either video capture or display only.
Separate data pipelines control the parsing and formatting of video capture or display data for each of the
BT.656, Y/C, raw video, and TCI modes.
For video capture operation, the video port may operate as two 8-bit channels of BT.656 or raw video
capture; or as a single channel of 8-bit BT.656, 8-bit raw video, 8-bit Y/C video, 16-bit raw video, or 8-bit
TCI.
For video display operation, the video port may operate as a single channel of 8-bit BT.656; or as a single
channel of 8-bit BT.656, 8-bit raw video, 8-bit Y/C video, or 16-bit raw video. It may also operate in a two
channel 8-bit raw mode in which the two channels are locked to the same timing. Channel B is not used
during single channel operation.
For more detailed information on the video port peripherals, see the TMS320DM647/DM648 Video Port
User's Guide (literature number SPRUEM1).
6.11.2 Video Port Peripheral Register Description(s)
Table 6-47. Video Port 0, 1, 2, 3, and 4 (VP0, VP1, VP2, VP3, and VP4) Control Registers
HEX ADDRESS RANGE
ACRONYM
DESCRIPTION
VP0
VP1
VP2
VP3
VP4
Video Port Peripheral Identification
Register
0x02C0 0000
0x02C0 4000
0x02C0 8000
0x02C0 C000
0x02C1 0000
VPPID
0x02C0 0004
0x02C0 0008
0x02C0 000C
0x02C0 0020
0x02C0 0024
0x02C0 0028
0x02C0 002C
0x02C0 0030
0x02C0 0034
0x02C0 0038
0x02C0 003C
0x02C0 0040
0x02C0 0044
0x02C0 00C0
0x02C0 00C4
0x02C0 00C8
0x02C0 00CC
0x02C0 0100
0x02C0 4004
0x02C0 4008
0x02C0 400C
0x02C0 4020
0x02C0 4024
0x02C0 4028
0x02C0 402C
0x02C0 4030
0x02C0 4034
0x02C0 4038
0x02C0 403C
0x02C0 4040
0x02C0 4044
0x02C0 40C0
0x02C0 40C4
0x02C0 40C8
0x02C0 40CC
0x02C0 4100
0x02C0 8004
0x02C0 8008
0x02C0 800C
0x02C0 8020
0x02C0 8024
0x02C0 8028
0x02C0 802C
0x02C0 8030
0x02C0 8034
0x02C0 8038
0x02C0 803C
0x02C0 8040
0x02C0 8044
0x02C0 80C0
0x02C0 80C4
0x02C0 80C8
0x02C0 80CC
0x02C0 8100
0x02C0 C004
0x02C0 C008
0x02C0 C00C
0x02C0 C020
0x02C0 C024
0x02C0 C028
0x02C0 C02C
0x02C0 C030
0x02C0 C034
0x02C0 C038
0x02C0 C03C
0x02C0 C040
0x02C0 C044
0x02C0 C0C0
0x02C0 C0C4
0x02C0 C0C8
0x02C0 C0CC
0x02C0 C100
0x02C1 0004
0x02C1 0008
0x02C1 000C
0x02C1 0020
0x02C1 0024
0x02C1 0028
0x02C1 002C
0x02C1 0030
0x02C1 0034
0x02C1 0038
0x02C1 003C
0x02C1 0040
0x02C1 0044
0x02C1 00C0
0x02C1 00C4
0x02C1 00C8
0x02C1 00CC
0x02C1 0100
PCR
-
Video Port Peripheral Control Register
Reserved
-
Reserved
PFUNC
PDIR
Video Port Pin Function Register
Video Port Pin Direction Register
Video Port Pin Data Input Register
Video Port Pin Data Output Register
Video Port Pin Data Set Register
Video Port Pin Data Clear Register
Video Port Pin Interrupt Enable Register
Video Port Pin Interrupt Polarity Register
Video Port Pin Interrupt Status Register
Video Port Pin Interrupt Clear Register
Video Port Control Register
PDIN
PDOUT
PDSET
PDCLR
PIEN
PIPOL
PISTAT
PICLR
VPCTL
VPSTAT
VPIE
Video Port Status Register
Video Port Interrupt Enable Register
Video Port interrupt Status Register
Video Capture Channel A Status Register
VPIS
VCASTAT
Video Capture Channel A Control
Register
0x02C0 0104
0x02C0 4104
0x02C0 8104
0x02C0 C104
0x02C1 0104
VCACTL
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Table 6-47. Video Port 0, 1, 2, 3, and 4 (VP0, VP1, VP2, VP3, and VP4) Control Registers (continued)
HEX ADDRESS RANGE
ACRONYM
DESCRIPTION
VP0
VP1
VP2
VP3
VP4
Video Capture Channel A Field 1 Start
Register
0x02C0 0108
0x02C0 4108
0x02C0 8108
0x02C0 C108
0x02C1 0108
VCASTRT1
VCASTOP1
VCASTRT2
VCASTOP2
VCAVINT
Video Capture Channel A Field 1 Stop
Register
0x02C0 010C
0x02C0 0110
0x02C0 0114
0x02C0 0118
0x02C0 011C
0x02C0 410C
0x02C0 4110
0x02C0 4114
0x02C0 4118
0x02C0 411C
0x02C0 810C
0x02C0 8110
0x02C0 8114
0x02C0 8118
0x02C0 811C
0x02C0 C10C
0x02C0 C110
0x02C0 C114
0x02C0 C118
0x02C0 C11C
0x02C1 010C
0x02C1 0110
0x02C1 0114
0x02C1 0118
0x02C1 011C
Video Capture Channel A Field 2 Start
Register
Video Capture Channel A Field 2 Stop
Register
Video Capture Channel A Vertical
Interrupt Register
Video Capture Channel A Threshold
Register
VCATHRLD
Video Capture Channel A Event Count
Register
0x02C0 0120
0x02C0 0140
0x02C0 0144
0x02C0 4120
0x02C0 4140
0x02C0 4144
0x02C0 8120
0x02C0 8140
0x02C0 8144
0x02C0 C120
0x02C0 C140
0x02C0 C144
0x02C1 0120
0x02C1 0140
0x02C1 0144
VCAEVTCT
VCBSTAT
VCBCTL
Video Capture Channel B Status Register
Video Capture Channel B Control
Register
Video Capture Channel B Field 1 Start
Register
0x02C0 0148
0x02C0 014C
0x02C0 0150
0x02C0 0154
0x02C0 0158
0x02C0 015C
0x02C0 0160
0x02C0 4148
0x02C0 414C
0x02C0 4150
0x02C0 4154
0x02C0 4158
0x02C0 415C
0x02C0 4160
0x02C0 8148
0x02C0 814C
0x02C0 8150
0x02C0 8154
0x02C0 8158
0x02C0 815C
0x02C0 8160
0x02C0 C148
0x02C0 C14C
0x02C0 C150
0x02C0 C154
0x02C0 C158
0x02C0 C15C
0x02C0 C160
0x02C1 0148
0x02C1 014C
0x02C1 0150
0x02C1 0154
0x02C1 0158
0x02C1 015C
0x02C1 0160
VCBSTRT1
VCBSTOP1
VCBSTRT2
VCBSTOP2
VCBVINT
Video Capture Channel B Field 1 Stop
Register
Video Capture Channel B Field 2 Start
Register
Video Capture Channel B Field 2 Stop
Register
Video Capture Channel B Vertical
Interrupt Register
Video Capture Channel B Threshold
Register
VCBTHRLD
VCBEVTCT
Video Capture Channel B Event Count
Register
0x02C0 0180
0x02C0 0184
0x02C0 0188
0x02C0 018C
0x02C0 0190
0x02C0 4180
0x02C0 4184
0x02C0 4188
0x02C0 418C
0x02C0 4190
0x02C0 8180
0x02C0 8184
0x02C0 8188
0x02C0 818C
0x02C0 8190
0x02C0 C180
0x02C0 C184
0x02C0 C188
0x02C0 C18C
0x02C0 C190
0x02C1 0180
0x02C1 0184
0x02C1 0188
0x02C1 018C
0x02C1 0190
TCICTL
TCI Capture Control Register
TCICLKINITL
TCICLKINITM
TCISTCLKL
TCISTCLKM
TCI Clock Initialization LSB Register
TCI Clock Initialization MSB Register
TCI System Time Clock LSB Register
TCI System Time Clock MSB Register
TCI System Time Clock Compare LSB
Register
0x02C0 0194
0x02C0 0198
0x02C0 019C
0x02C0 01A0
0x02C0 01A4
0x02C0 4194
0x02C0 4198
0x02C0 419C
0x02C0 41A0
0x02C0 41A4
0x02C0 8194
0x02C0 8198
0x02C0 819C
0x02C0 81A0
0x02C0 81A4
0x02C0 C194
0x02C0 C198
0x02C0 C19C
0x02C0 C1A0
0x02C0 C1A4
0x02C1 0194
0x02C1 0198
0x02C1 019C
0x02C1 01A0
0x02C1 01A4
TCISTCMPL
TCISTCMPM
TCISTMSKL
TCISTMSKM
TCITICKS
TCI System Time Clock Compare MSB
Register
TCI System Time Clock Compare Mask
LSB Register
TCI System Time Clock Compare Mask
MSB Register
TCI System Time Clock Ticks Interrupt
Register
0x02C0 0200
0x02C0 0204
0x02C0 0208
0x02C0 4200
0x02C0 4204
0x02C0 4208
0x02C0 8200
0x02C0 8204
0x02C0 8208
0x02C0 C200
0x02C0 C204
0x02C0 C208
0x02C1 0200
0x02C1 0204
0x02C1 0208
VDSTAT
VDCTL
Video Display Status Register
Video Display Control Register
Video Display Frame Size Register
VDFRMSZ
Video Display Horizontal Blanking
Register
0x02C0 020C
0x02C0 0210
0x02C0 0214
0x02C0 0218
0x02C0 021C
0x02C0 420C
0x02C0 4210
0x02C0 4214
0x02C0 4218
0x02C0 421C
0x02C0 820C
0x02C0 8210
0x02C0 8214
0x02C0 8218
0x02C0 821C
0x02C0 C20C
0x02C0 C210
0x02C0 C214
0x02C0 C218
0x02C0 C21C
0x02C1 020C
0x02C1 0210
0x02C1 0214
0x02C1 0218
0x02C1 021C
VDHBLNK
VDVBLKS1
VDVBLKE1
VDVBLKS2
VDVBLKE2
Video Display Field 1 Vertical Blanking
Start Register
Video Display Field 1 Vertical Blanking
End Register
Video Display Field 2 Vertical Blanking
Start Register
Video Display Field 2 Vertical Blanking
End Register
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Table 6-47. Video Port 0, 1, 2, 3, and 4 (VP0, VP1, VP2, VP3, and VP4) Control Registers (continued)
HEX ADDRESS RANGE
ACRONYM
DESCRIPTION
VP0
VP1
VP2
VP3
VP4
Video Display Field 1 Image Offset
Register
0x02C0 0220
0x02C0 4220
0x02C0 8220
0x02C0 C220
0x02C1 0220
VDIMGOFF1
VDIMGSZ1
VDIMGOFF2
VDIMGSZ2
Video Display Field 1 Image Size
Register
0x02C0 0224
0x02C0 0228
0x02C0 022C
0x02C0 4224
0x02C0 4228
0x02C0 422C
0x02C0 8224
0x02C0 8228
0x02C0 822C
0x02C0 C224
0x02C0 C228
0x02C0 C22C
0x02C1 0224
0x02C1 0228
0x02C1 022C
Video Display Field 2 Image Offset
Register
Video Display Field 2 Image Size
Register
0x02C0 0230
0x02C0 0234
0x02C0 0238
0x02C0 4230
0x02C0 4234
0x02C0 4238
0x02C0 8230
0x02C0 8234
0x02C0 8238
0x02C0 C230
0x02C0 C234
0x02C0 C238
0x02C1 0230
0x02C1 0234
0x02C1 0238
VDFLDT1
VDFLDT2
VDTHRLD
Video Display Field 1 Timing Register
Video Display Field 2 Timing Register
Video Display Threshold Register
Video Display Horizontal Synchronization
Register
0x02C0 023C
0x02C0 0240
0x02C0 0244
0x02C0 0248
0x02C0 024C
0x02C0 423C
0x02C0 4240
0x02C0 4244
0x02C0 4248
0x02C0 424C
0x02C0 823C
0x02C0 8240
0x02C0 8244
0x02C0 8248
0x02C0 824C
0x02C0 C23C
0x02C0 C240
0x02C0 C244
0x02C0 C248
0x02C0 C24C
0x02C1 023C
0x02C1 0240
0x02C1 0244
0x02C1 0248
0x02C1 024C
VDHSYNC
VDVSYNS1
VDVSYNE1
VDVSYNS2
VDVSYNE2
Video Display Field 1 Vertical
Synchronization Start Register
Video Display Field 1 Vertical
Synchronization End Register
Video Display Field 2 Vertical
Synchronization Start Register
Video Display Field 2 Vertical
Synchronization End Register
0x02C0 0250
0x02C0 0254
0x02C0 0258
0x02C0 4250
0x02C0 4254
0x02C0 4258
0x02C0 8250
0x02C0 8254
0x02C0 8258
0x02C0 C250
0x02C0 C254
0x02C0 C258
0x02C1 0250
0x02C1 0254
0x02C1 0258
VDRELOAD
VDDISPEVT
VDCLIP
Video Display Counter Reload Register
Video Display Event Register
Video Display Clipping Register
Video Display Default Display Value
Register
0x02C0 025C
0x02C0 425C
0x02C0 825C
0x02C0 C25C
0x02C1 025C
VDDEFVAL
0x02C0 0260
0x02C0 0264
0x02C0 4260
0x02C0 4264
0x02C0 8260
0x02C0 8264
0x02C0 C260
0x02C0 C264
0x02C1 0260
0x02C1 0264
VDVINT
VDFBIT
Video Display Vertical Interrupt Register
Video Display Field Bit Register
Video Display Field 1Vertical Blanking Bit
Register
0x02C0 0268
0x02C0 026C
0x02C0 4268
0x02C0 426C
0x02C0 8268
0x02C0 826C
0x02C0 C268
0x02C0 C26C
0x02C1 0268
0x02C1 026C
VDVBIT1
VDVBIT2
Video Display Field 2Vertical Blanking Bit
Register
0x5000 0000
0x5000 0020
0x5000 0040
0x5000 0080
0x5000 00A0
0x5000 00C0
0x5200 0000
0x5200 0020
0x5200 0040
0x5200 0080
0x5400 0000
0x5400 0020
0x5400 0040
0x5400 0080
0x5400 00A0
0x5400 00C0
0x5600 0000
0x5600 0020
0x5600 0040
0x5600 0080
0x5800 0000
0x5800 0020
0x5800 0040
0x5800 0080
0x5800 00A0
0x5800 00C0
0x5A00 0000
0x5A00 0020
0x5A00 0040
0x5A00 0080
0x6000 0000
0x6000 0020
0x6000 0040
0x6000 0080
0x6000 00A0
0x6000 00C0
0x6200 0000
0x6200 0020
0x6200 0040
0x6200 0080
0x6400 0000
0x6400 0020
0x6400 0040
0x6400 0080
0x6400 00A0
0x6400 00C0
0x6600 0000
0x6600 0020
0x6600 0040
0x6600 0080
YSRCA
CBSRCA
CRSRCA
YDSTA
Y FIFO Source Register A
CB FIFO Source Register A
CR FIFO Source Register A
Y FIFO Destination Register A
CB FIFO Destination Register
CR FIFO Destination Register
Y FIFO Source Register B
CB FIFO Source Register B
CR FIFO Source Register B
Y FIFO Destination Register B
CBDST
CRDST
YSRCB
CBSRCB
CRSRCB
YDSTB
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6.11.3 Video Port (VP0, VP1, VP2, VP3, VP4) Electrical Data/Timing
6.11.3.1 VCLKIN Timing (Video Capture Mode)
Table 6-48. Timing Requirements for Video Capture Mode for VPxCLKINx(1)
(see Figure 6-27)
-720
-800
-900
NO.
UNIT
-1100
MIN MAX
1
2
3
4
tc(VKI)
Cycle time, VPxCLKINx
9.259
5.4
ns
ns
ns
ns
tw(VKIH)
tw(VKIL)
tt(VKI)
Pulse duration, VPxCLKINx high
Pulse duration, VPxCLKINx low
Transition time, VPxCLKINx
5.4
3
(1) The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN.
4
1
2
3
VPxCLKINx
4
Figure 6-27. Video Port Capture VPxCLKINx TIming
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6.11.3.2 Video Data and Control Timing (Video Capture Mode)
Table 6-49. Timing Requirements in Video Capture Mode for Video Data and Control Inputs
(see Figure 6-28)
-720
-800
-900
-1100
NO.
UNIT
MIN
2.4
0.5
2.4
0.5
MAX
1
2
3
4
tsu(VDATV-VKIH) Setup time, VPxDx valid before VPxCLKINx high
ns
ns
ns
ns
th(VDATV-VKIH)
tsu(VCTLV-VKIH)
th(VCTLV-VKIH)
Hold time, VPxDx valid after VPxCLKINx high
Setup time, VPxCTLx valid before VPxCLKINx high
Hold time, VPxCTLx valid after VPxCLKINx high
VPxCLKINx
1
3
2
VPxD[19:0] (Input)
VPxCTLx (Input)
4
Figure 6-28. Video Port Capture Data and Control Input Timing
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6.11.3.3 VCLKIN Timing (Video Display Mode)
Table 6-50. Timing Requirements for Video Display Mode for VPxCLKINx(1) (see Figure 6-29)
-720
-800
-900
-1100
NO.
UNIT
MIN
9
MAX
1
2
3
4
tc(VKI)
Cycle time, VPxCLKINx
ns
ns
ns
ns
tw(VKIH)
tw(VKIL)
tt(VKI)
Pulse duration, VPxCLKINx high
Pulse duration, VPxCLKINx low
Transition time, VPxCLKINx
4.1
4.1
3
(1) The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN.
4
1
2
3
VPxCLKINx
4
Figure 6-29. Video Port Display VPxCLKINx Timing
6.11.3.4 Video Control Input/Output and Video Display Data Output Timing With Respect to VPxCLKINx
and VPxCLKOUTx (Video Display Mode)
Table 6-51. Timing Requirements in Video Display Mode for Video Control Input Shown With Respect to
VPxCLKINx and VPxCLKOUTx (see Figure 6-30)
-720
-800
-900
-1100
NO.
UNIT
MIN
MAX
13 tsu(VCTLV-VKIH)
14 th(VCTLV-VKIH)
15 tsu(VCTLV-VKOH)
16 th(VCTLV-VKOH)
Setup time, VPxCTLx valid before VPxCLKINx high
Hold time, VPxCTLx valid after VPxCLKINx high
Setup time, VPxCTLx valid before VPxCLKOUTx high(1)
Hold time, VPxCTLx valid after VPxCLKOUTx high(1)
2.4
0.5
ns
ns
ns
ns
7.4
-0.9
(1) Assuming non-inverted VPxCLKOUTx signal.
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Table 6-52. Switching Characteristics Over Recommended Operating Conditions in Video Display Mode
for Video Data and Control Output Shown With Respect to VPxCLKINx and VPxCLKOUTx(1) (2)
(see Figure 6-30)
-720
-800
-900
-1100
NO.
PARAMETER
UNIT
MIN
V - 0.7
MAX
1
2
3
4
5
6
7
8
9
tc(VKO)
Cycle time, VPxCLKOUTx
V + 0.7
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tw(VKOH)
Pulse duration, VPxCLKOUTx high
VH - 0.7 VH + 0.7
tw(VKOL)
Pulse duration, VPxCLKOUTx low
VL - 0.7 VL + 0.7
tt(VKO)
Transition time, VPxCLKOUTx
1.8
td(VKIH-VKOH)
td(VKIL-VKOL)
td(VKIH-VKOL)
td(VKIL-VKOH)
td(VKIH-VPOUTV)
Delay time, VPxCLKINx high to VPxCLKOUTx high(3)
Delay time, VPxCLKINx low to VPxCLKOUTx low(3)
Delay time, VPxCLKINx high to VPxCLKOUTx low
Delay time, VPxCLKINx low to VPxCLKOUTx high
Delay time, VPxCLKINx high to VPxOUT valid(4)
Delay time, VPxCLKINx high to VPxOUT invalid(4)
Delay time, VPxCLKOUTx high to VPxOUT valid(1) (4)
Delay time, VPxCLKOUTx high to VPxOUT invalid(1) (4)
5
5
5
5
7
10 td(VKIH-VPOUTIV)
11 td(VKOH-VPOUTV)
12 td(VKOH-VPOUTIV)
1.7
4.7
0.7
(1) V = the video input clock (VPxCLKINx) period in ns.
(2) VH is the high period of V (video input clock period) in ns and VL is the low period of V (video input clock period) in ns.
(3) Assuming non-inverted VPxCLKOUTx signal.
(4) VPxOUT consists of VPxCTLx and VPxD[19:0]
VPxCLKINx
5
7
2
1
6
8
3
VPxCLKOUTx
[VCLK2P = 0]
4
4
VPxCLKOUTx
(Inverted)
[VCLK2P = 1]
12
10
11
9
VPxCTLx,V
PxD[19:0]
(Outputs)
15
16
14
13
VPxCTLx
(Input)
Figure 6-30. Video Port Display Data Output Timing and Control Input/Output Timing With Respect to
VPxCLKINx and VPxCLKOUTx
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6.11.3.5 Video Dual-Display Sync Mode Timing (With Respect to VPxCLKINx)
Table 6-53. Timing Requirements for Dual-Display Sync Mode for VPxCLKINx (see Figure 6-31)
-720<br
Placement="li
ne"/>-800<br
Placement="li
ne"/>-900
NO.
UNIT
-1100
MIN
MAX
1
tskr(VKI)
Skew rate, VPxCLKINx before VPyCLKINy
±500
ps
VPxCLKINx
1
VPyCLKINy
Figure 6-31. Video Port Dual-Display Sync Timing
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6.12 VCXO Interpolated Control (VIC)
The VIC can be used in conjunction with the video ports (VPs) to maintain synchronization of a video
stream. The VIC can also be used to control a VCXO to adjust the pixel clock rate to a video port.
6.12.1 VIC Device-Specific Information
The VCXO interpolated control (VIC) port provides digital-to-analog conversation with resolution from
9-bits to up to 16-bits. The output of the VIC is a single bit interpolated D/A output (VDAC pin).
Typical D/A converters provide a discrete output level for every value of the digital word that is being
converted. This is a problem for digital words that are long. This is avoided in a Sigma Delta type D/A
converter by choosing a few widely spaced output levels and interpolating values between them. The
interpolating mechanism causes the output to oscillate rapidly between the levels in such a manner that
the average output represents the value of input code.
In the VIC, two output levels are chosen (0 and 1), and Sigma Delta interpolation scheme is implemented
to interpolate between these levels with a rapidly changing signal. The frequency of interpolation is
dependent on the resolution needed.
When the video port is used in transport channel interface (TCI) mode, the VIC port is used to control the
system clock, VCXO, for MPEG transport stream.
The VIC supports the following features:
•
•
•
Single interpolation for D/A conversion
Programmable precision from 9-to-16 bits
Interface for register accesses
For more detailed information on the VCXO interpolated control (VIC) peripheral, see the
TMS320DM647/DM648 Video Port User's Guide (literature number SPRUEM1).
6.12.2 VIC Peripheral Register Description(s)
Table 6-54. VCXO Interpolated Control (VIC) Port Registers
HEX ADDRESS RANGE
0x0204 7400
ACRONYM
VICCTL
VICIN
REGISTER NAME
VIC control register
0x0204 7404
VIC input register
VIC clock divider register
Reserved
0x0204 7408
VPDIV
-
0x0204 740C - 0x0204 77FF
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6.12.3 VIC Electrical Data/Timing
6.12.3.1 STCLK Timing
Table 6-55. Timing Requirements for STCLK(1) (see Figure 6-32)
-720
-800
-900
-1100
NO.
UNIT
MIN MAX
1
2
3
4
tc(STCLK)
tw(STCLKH)
tw(STCLKL)
tt(STCLK)
Cycle time, STCLK
33.3
16
16
3
ns
ns
ns
ns
Pulse duration, STCLK high
Pulse duration, STCLK low
Transition time, STCLK
(1) The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN.
4
1
2
3
STCLK
4
Figure 6-32. STCLK Timing
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6.13 Universal Asynchronous Receiver/Transmitter (UART)
The device has a UART peripheral. The UART has the following features:
•
•
•
•
•
•
•
16-byte storage space for both the transmitter and receiver FIFOs
1, 4, 8, or 14 byte selectable receiver FIFO trigger level for autoflow control and DMA
DMA signaling capability for both received and transmitted data
Programmable auto-rts and auto-cts for autoflow control
Frequency pre-scale values from 1 to 65, 535 to generate appropriate baud rates
Prioritized interrupts
Programmable serial data formats
–
–
–
5, 6, 7, or 8-bit characters
Even, odd, or no parity bit generation and detection
1, 1.5, or 2 stop bit generation
•
•
•
False start bit detection
Line break generation and detection
Internal diagnostic capabilities
–
–
Loopback controls for communications link fault isolation
Break, parity, overrun, and framing error simulation
•
Modem control functions (CTS, RTS).
The UART registers are listed in Table 6-56 .
6.13.1 UART Peripheral Register Description(s)
Table 6-56. UART Register Descriptions
HEX ADDRESS RANGE
0x0204 7000
ACRONYM
RBR
THR
IER
REGISTER NAME
UART Receiver Buffer Register (Read Only)
UART Transmitter Holding Register (Write Only)
UART Interrupt Enable Register
UART Interrupt Identification Register (Read Only)
UART FIFO Control Register (Write Only)
UART Line Control Register
UART Modem Control Register
UART Line Status Register
Reserved
0x0204 7000
0x0204 7004
0x0204 7008
IIR
0x0204 7008
FCR
LCR
MCR
LSR
-
0x0204 700C
0x0204 7010
0x0204 7014
0x0204 7018
0x0204 701C
0x0204 7020
-
Reserved
DLL
DLH
PID
UART Divisor Latch (LSB)
0x0204 7024
UART Divisor Latch (MSB)
Peripheral Identification Register
Reserved
0x0204 7028
0x0204 702C
0x0204 7030
PWREMU_MGMT
UART Power and Emulation Management Register
Mode Definition Register
0x0204 7034
MDR
-
0x0204 7038 - 0x0204 73FF
Reserved
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6.13.2 UART Electrical Data/Timing
Table 6-57. Timing Requirements for UARTx Receive(1) (see Figure 6-33)
720, 800, 900, 1100
NO.
UNIT
MIN
0.96U
0.96U
MAX
1.05U
1.05U
4
5
tw(URXDB)
tw(URXSB)
Pulse duration, receive data bit (RXDn) [15/30/100 pF]
Pulse duration, receive start bit [15/30/100 pF]
ns
ns
(1) U = UART baud time = 1/programmed baud rate.
Table 6-58. Switching Characteristics Over Recommended Operating Conditions for UARTx Transmit(1)
(see Figure 6-33)
720, 800, 900, 1100
NO.
PARAMETER
UNIT
MIN
MAX
1
2
3
f(baud)
Maximum programmable baud rate
5
MHz
ns
tw(UTXDB)
tw(UTXSB)
Pulse duration, transmit data bit (TXDn) [15/30/100 pF]
Pulse duration, transmit start bit [15/30/100 pF]
U - 2
U - 2
U + 2
U + 2
ns
(1) U = UART baud time = 1/programmed baud rate.
3
2
Start
Bit
UART_TXDn
Data Bits
5
4
Start
Bit
UART_RXDn
Data Bits
Figure 6-33. UART Transmit/Receive Timing
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6.14 Serial Peripheral Interface Port (SPI)
6.14.1 SPI Device-Specific Information
Figure 6-34 is a block diagram of the SPI module, which is a simple shift register and buffer plus control
logic. Data is written to the shift register before transmission occurs and is read from the buffer at the end
of transmission. The SPI can operate only as a master, in which case, it initiates a transfer and drives the
SPICLK pin. Four clock phase and polarity options are supported as well as many data formatting options.
SPIDO
SPIDI
Peripheral
Configuration Bus
16-Bit Shift Register
State
Machine
GPIO
Control
(all pins)
SPICSx
SPICLK
Interrupt and
16-Bit Buffer
Clock
Control
DMA Requests
16-Bit Emulation Buffer
Figure 6-34. Block Diagram of SPI Module
The SPI supports 3- and 4-pin operation with three basic pins (SPICLK, SPIDO, and SPIDI) and two
optional pins (SPICSx).
The optional SPICSx (Slave Chip Select) pin is most useful to enable in master mode when there are
more than one slave devices on the same SPI port. The device only shifts data and drives the SPIDI pin
when SPICSx is held low.
Optional − Slave Chip Select
SPICSx
SPICSx
SPICLK
SPIDI
SPICLK
SPIDI
SPIDO
SPIDO
MASTER SPI
SLAVE SPI
Figure 6-35. Illustration of SPI Master-to-SPI Slave Connection
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6.14.2 SPI Peripheral Register Descriptions
Table 6-59 is a list of the SPI registers.
Table 6-59. SPI Configuration Registers
SPI0
BYTE ADDRESS
REGISTER NAME
SPIGCR0
DESCRIPTION
0x0204 7800
0x0204 7804
0x0204 7808
0x0204 780C
0x0204 7810
0x0204 7814
0x0204 7818
0x0204 781C
0x0204 783C
0x0204 7840
0x0204 7844
0x0204 7848
0x0204 784C
0x0204 7850
0x0204 7854
0x0204 7858
0x0204 785C
0x0204 7860
0x0204 7864
Global Control Register 0
Global Control Register 1
Interrupt Register
SPIGCR1
SPIINT0
SPILVL
Interrupt Level Register
Flag Register
SPIFLG
SPIPC0
Pin Control Register 0 (Pin Function)
Pin Control Register 1 (Pin Direction)
Pin Control Register 2 (Pin Data In)
Shift Register 1 (with format select)
Buffer Register
SPIPC1
SPIPC2
SPIDAT1
SPIBUF
SPIEMU
SPIDELAY
SPIDEF
Emulation Register
Delay Register
Default Chip Select Register
Format Register 0
SPIFMT0
SPIFMT1
SPIFMT2
SPIFMT3
TGINTVECT0
TGINTVECT1
Format Register 1
Format Register 2
Format Register 3
Interrupt Vector for SPI INT0
Interrupt Vector for SPI INT1
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6.14.3 SPI Electrical Data/Timing
6.14.3.1 Serial Peripheral Interface (SPI) Timing
Table 6-60 assumes testing over recommended operating conditions (see Figure 6-36).
Table 6-60. General Timing Requirements for SPIx Master Modes(1)
NO.
MIN
MAX UNIT
greater of 8P or
1
tc(SPC)M
Cycle Time, SPICLK, All Master Modes
256P ns
100 ns
greater of 4P or 45 ns
greater of 4P or 45 ns
2
3
tw(SPCH)M
tw(SPCL)M
Pulse Width High, SPICLK, All Master Modes
Pulse Width Low, SPICLK, All Master Modes
ns
ns
Polarity = 0, Phase = 0,
to SPICLK rising
4P
0.5tc(SPC)M + 4P
4P
Polarity = 0, Phase = 1,
to SPICLK rising
Delay, initial data bit valid
on SPIDO to initial edge on
SPICLK(2)
4
5
6
7
8
td(SIMO_SPC)M
td(SPC_SIMO)M
toh(SPC_SIMO)M
tsu(SOMI_SPC)M
tih(SPC_SOMI)M
ns
Polarity = 1, Phase = 0,
to SPICLK falling
Polarity = 1, Phase = 1,
to SPICLK falling
0.5tc(SPC)M + 4P
Polarity = 0, Phase = 0,
from SPICLK rising
15
Polarity = 0, Phase = 1,
from SPICLK falling
15
ns
15
Delay, subsequent bits
valid on SPIDO after
transmit edge of SPICLK
Polarity = 1, Phase = 0,
from SPICLK falling
Polarity = 1, Phase = 1,
from SPICLK rising
15
Polarity = 0, Phase = 0,
from SPICLK falling
0.5tc(SPC)M - 10
0.5tc(SPC)M - 10
0.5tc(SPC)M - 10
0.5tc(SPC)M - 10
0.5P + 15
Polarity = 0, Phase = 1,
from SPICLK rising
Output hold time, SPIDO
valid after
ns
receive edge of SPICLK,
Polarity = 1, Phase = 0,
from SPICLK rising
except for final bit(3)
Polarity = 1, Phase = 1,
from SPICLK falling
Polarity = 0, Phase = 0,
to SPICLK falling
Polarity = 0, Phase = 1,
to SPICLK rising
0.5P + 15
Input Setup Time, SPIDI
valid before
receive edge of SPICLK
ns
Polarity = 1, Phase = 0,
to SPICLK rising
0.5P + 15
Polarity = 1, Phase = 1,
to SPICLK falling
0.5P + 15
Polarity = 0, Phase = 0,
from SPICLK falling
0.5P + 5
Polarity = 0, Phase = 1,
from SPICLK rising
0.5P + 5
Input Hold Time, SPIDI
valid after
receive edge of SPICLK
ns
Polarity = 1, Phase = 0,
from SPICLK rising
0.5P + 5
Polarity = 1, Phase = 1,
from SPICLK falling
0.5P + 5
(1) P = SYSCLK3 period
(2) First bit may be MSB or LSB depending upon SPI configuration. MO(0) refers to first bit and MO(n) refers to last bit output on SPIDO.
MI(0) refers to the first bit input and MI(n) refers to the last bit input on SPIDI.
(3) The final data bit will be held on the SPIDO pin until the SPIDAT1 register is written with new data.
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1
Master Mode
Polarity = 0 Phase = 0
2
3
SPICLK
SPIDO
SPIDI
5
4
6
MO(0)
7
MO(1)
MO(n−1)
MO(n)
MI(n)
8
MI(0)
MI(1)
MI(n−1)
Master Mode
Polarity = 0 Phase = 1
4
SPICLK
6
5
SPIDO
SPIDI
MO(0)
7
MO(1)
MI(1)
MO(n−1)
MI(n−1)
MO(n)
MI(n)
8
MI(0)
4
Master Mode
Polarity = 1 Phase = 0
SPICLK
SPIDO
SPIDI
5
6
MO(0)
7
MO(1)
MI(1)
MO(n−1)
MO(n)
MI(n)
8
MI(0)
MI(n−1)
Master Mode
Polarity = 1 Phase = 1
SPICLK
SPIDO
SPIDI
5
4
6
MO(0)
7
MO(1)
MI(1)
MO(n−1)
MI(n−1)
MO(n)
MI(n)
8
MI(0)
Figure 6-36. SPI Timings—Master Mode
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6.15 Inter-Integrated Circuit (I2C)
The inter-integrated circuit (I2C) module provides an interface between the DM647/DM648 device and
other devices compliant with Philips Semiconductors Inter-IC bus (I2C-bus™) specification version 2.1.
External components attached to this 2-wire serial bus can transmit/receive up to 8-bit data to/from the
DSP through the I2C module. The I2C port does not support CBUS-compatible devices.
The I2C port supports:
•
•
•
•
•
•
•
Compatible with Philips I2C Specification Revision 2.1 (January 2000)
Fast Mode up to 400 Kbps (no fail-safe I/O buffers)
Noise Filter to Remove Noise 50 ns or less
Seven- and Ten-Bit Device Addressing Modes
Master (Transmit/Receive) and Slave (Transmit/Receive) Functionality
Events: DMA, Interrupt, or Polling
Slew-Rate Limited Open-Drain Output Buffers
I2C Module
Clock
Prescale
Peripheral Clock
(DSP/6)
I2CPSC
Control
Bit Clock
Generator
Own
Address
I2COAR
I2CSAR
I2CMDR
I2CCNT
I2CEMDR
SCL
Noise
Filter
I2C Clock
Slave
Address
I2CCLKH
I2CCLKL
Mode
Data
Count
Transmit
I2CXSR
Transmit
Shift
Extended
Mode
Transmit
Buffer
I2CDXR
SDA
Interrupt/DMA
I2CIMR
Noise
Filter
I2C Data
Interrupt
Mask/Status
Receive
I2CDRR
Receive
Buffer
Interrupt
Status
I2CSTR
I2CIVR
Interrupt
Vector
Receive
Shift
I2CRSR
Shading denotes control/status registers.
Figure 6-37. I2C Module Block Diagram
For more detailed information on the I2C peripheral, see the TMS320DM647/DM648 DSP Inter-Integrated
Circuit (I2C) Module User's Guide (literature number SPRUEK8).
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6.15.1 I2C Peripheral Register Description(s)
Table 6-61. I2C Registers
HEX ADDRESS RANGE
0x0204 7C00
0x0204 7C04
0x0204 7C08
0x0204 7C0C
0x0204 7C10
0x0204 7C14
0x0204 7C18
0x0204 7C1C
0x0204 7C20
0x0204 7C24
0x0204 7C28
0x0204 7C2C
0x0204 7C30
0x0204 7C34
ACRONYM
ICOAR
ICIMR
REGISTER NAME
I2C Own Address Register
I2C Interrupt Mask Register
I2C Interrupt Status Register
ICSTR
ICCLKL
ICCLKH
ICCNT
I2C Clock Divider Low Register
I2C Clock Divider High Register
I2C Data Count Register
I2C Data Receive Register
I2C Slave Address Register
I2C Data Transmit Register
I2C Mode Register
ICDRR
ICSAR
ICDXR
ICMDR
ICIVR
I2C Interrupt Vector Register
I2C Extended Mode Register
I2C Prescaler Register
ICEMDR
ICPSC
ICDMAC
I2C DMA Control Register
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6.15.2 I2C Electrical Data/Timing
6.15.2.1 Inter-Integrated Circuits (I2C) Timing
Table 6-62. Timing Requirements for I2C Timings(1) (see Figure 6-38)
720, 800, 900, 1100
STANDARD
NO.
FAST MODE
UNIT
MODE
MIN MAX
10
MIN MAX
1
2
tc(SCL)
Cycle time, SCL
2.5
µs
µs
Setup time, SCL high before SDA low (for a repeated START
condition)
tsu(SCLH-SDAL)
4.7
4
0.6
Hold time, SCL low after SDA low (for a START and a repeated
START condition)
3
th(SCLL-SDAL)
0.6
µs
4
5
tw(SCLL)
Pulse duration, SCL low
4.7
4
1.3
0.6
100(2)
µs
µs
ns
tw(SCLH)
tsu(SDAV-SCLH)
th(SDA-SCLL)
tw(SDAH)
tr(SDA)
Pulse duration, SCL high
6
Setup time, SDA valid before SCL high
Hold time, SDA valid after SCL low
Pulse duration, SDA high between STOP and START conditions
Rise time, SDA
250
0(3)
4.7
7
0(3) 0.9(4) µs
8
1.3
µs
300 ns
300 ns
300 ns
300 ns
µs
(5)
9
1000 20 + 0.1Cb
(5)
(5)
(5)
10
11
12
13
14
15
tr(SCL)
Rise time, SCL
1000 20 + 0.1Cb
tf(SDA)
Fall time, SDA
300 20 + 0.1Cb
300 20 + 0.1Cb
tf(SCL)
Fall time, SCL
tsu(SCLH-SDAH)
tw(SP)
Setup time, SCL high before SDA high (for STOP condition)
Pulse duration, spike (must be suppressed)
Capacitive load for each bus line
4
0.6
0
50 ns
400 pF
(5)
Cb
400
(1) The I2C pins SDA and SCL do not feature fail-safe I/O buffers. These pins could potentially draw current when the device is powered
down.
(2) A Fast-mode I2C-bus™ device can be used in a standard-mode I2C-bus system, but the requirement tsu(SDA-SCLH)≥ 250 ns must then be
met. This will be the case automatically if the device does not stretch the LOW period of the SCL signal. If such a device does stretch
the LOW period of the SCL signal, it must output the next data bit to the SDA line tr max + tsu(SDA-SCLH)= 1000 + 250 = 1250 ns
(according to the Standard-mode I2C-Bus Specification) before the SCL line is released.
(3) A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCL signal) to bridge the
undefined region of the falling edge of SCL.
(4) The maximum th(SDA-SCLL) has to be met only if the device does not stretch the low period [tw(SCLL)] of the SCL signal.
(5) Cb = total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed.
11
9
SDA
6
8
14
4
13
5
10
SCL
1
12
3
2
7
3
Stop
Start
Repeated
Start
Stop
Figure 6-38. I2C Receive Timings
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Table 6-63. Switching Characteristics for I2C Timings(1) (see Figure 6-39)
720, 800, 900, 1100
STANDARD
NO.
PARAMETER
FAST MODE
UNIT
MODE
MIN
10
MAX
MIN MAX
16
17
tc(SCL)
Cycle time, SCL
2.5
µs
µs
Delay time, SCL high to SDA low (for a repeated START
condition)
td(SCLH-SDAL)
4.7
4
0.6
Delay time, SDA low to SCL low (for a START and a
repeated START condition)
18
td(SDAL-SCLL)
0.6
µs
19
20
21
22
tw(SCLL)
Pulse duration, SCL low
4.7
4
1.3
0.6
100
0
µs
µs
ns
µs
tw(SCLH)
Pulse duration, SCL high
td(SDAV-SCLH)
tv(SCLL-SDAV)
Delay time, SDA valid to SCL high
Valid time, SDA valid after SCL low
250
0
0.9
Pulse duration, SDA high between STOP and START
conditions
23
24
25
26
27
tw(SDAH)
tr(SDA)
tr(SCL)
tf(SDA)
tf(SCL)
4.7
1.3
µs
ns
ns
ns
ns
20 + 0.1Cb
Rise time, SDA
Rise time, SCL
Fall time, SDA
Fall time, SCL
1000
1000
300
300
300
300
300
(1)
20 + 0.1Cb
(1)
20 + 0.1Cb
(1)
20 + 0.1Cb
300
(1)
28
29
td(SCLH-SDAH)
Cp
Delay time, SCL high to SDA high (for STOP condition)
Capacitance for each I2C pin
4
0.6
µs
pF
10
10
(1) Cb = total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed.
26
24
SDA
21
23
19
28
20
25
SCL
16
27
18
17
22
18
Stop
Start
Repeated
Start
Stop
Figure 6-39. I2C Transmit Timings
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6.16 Host-Port Interface (HPI) Peripheral
6.16.1 HPI Device-Specific Information
The device includes a user-configurable 16-bit or 32-bit host-port interface (HPI16/HPI32). The AEA14 pin
controls the HPI_WIDTH, allowing the user to configure the HPI as a 16-bit or 32-bit peripheral.
Software handshaking via the HRDY bit of the Host Port Control Register (HPIC) is not supported.
An HPI boot is terminated using a DSP interrupt. The DSP interrupt is registered in bit 0 (channel 0) of the
EDMA Event Register (ER). This event must be cleared by software before triggering transfers on DMA
channel 0.
6.16.2 HPI Peripheral Register Description(s)
Table 6-64. HPI Control Registers
HEX ADDRESS RANGE
ACRONYM
REGISTER NAME
COMMENTS
0x0200 0000
PID
Peripheral Identification Register
HPI power and emulation management
register
PWREMU_MGMT has both host/CPU
read/write access.
0x0200 0004
PWREMU_MGMT
0x0200 0008 - 0x0200 0024
0x0200 0028
-
-
-
Reserved
Reserved
Reserved
0x0200 002C
The host and the CPU have read/write
access to the HPIC register.(1)
0x0200 0030
0x0200 0034
HPIC
HPI control register
HPIA
HPI address register
(Write)
(HPIAW)(2)
The host has read/write access to the
HPIA registers. The CPU has read
access only to the HPIA registers.
HPIA
HPI address register
(Read)
0x0200 0038
(HPIAR)(2)
0x0200 003C - 0x0200 007F
-
Reserved
(1) The CPU can write 1 to the HINT bit to generate an interrupt to the host and it can write 1 to the DSPINT bit to clear/acknowledge an
interrupt from the host.
(2) There are two 32-bit HPIA registers: HPIAR for read operations and HPIAW for write operations. The HPI can be configured such that
HPIAR and HPIAW act as a single 32-bit HPIA (single-HPIA mode) or as two separate 32-bit HPIAs (dual-HPIA mode) from the
perspective of the host. The CPU can access HPIAW and HPIAR independently. For details about the HPIA registers and their modes,
see the TMS320DM647/DM648 DSP Host Port Interface (HPI) User's Guide (literature number SPRUEL5).
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6.16.3 HPI Electrical Data/Timing
Table 6-65. Timing Requirements for Host-Port Interface Cycles(1) (2) (see Figure 6-40 through
Figure 6-47)
720, 800, 900, 1100
NO.
UNIT
MIN
5
MAX
9
tsu(HASL-HSTBL)
th(HSTBL-HASL)
tsu(SELV-HASL)
th(HASL-SELV)
tw(HSTBL)
Setup time, HAS low before HSTROBE low
Hold time, HAS low after HSTROBE low
Setup time, select signals(3) valid before HAS low
Hold time, select signals(3) valid after HAS low
Pulse duration, HSTROBE low
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
10
11
12
13
14
15
16
17
18
37
2
5
5
2M
2M
5
tw(HSTBH)
Pulse duration, HSTROBE high between consecutive accesses
Setup time, select signals(3) valid before HSTROBE low
Hold time, select signals(3) valid after HSTROBE low
Setup time, host data valid before HSTROBE high
Hold time, host data valid after HSTROBE high
Setup time, HCS low before HSTROBE low
tsu(SELV-HSTBL)
th(HSTBL-SELV)
tsu(HDV-HSTBH)
th(HSTBH-HDV)
tsu(HCSL-HSTBL)
5
5
1
0
Hold time, HSTROBE low after HRDY low. HSTROBE should not be
inactivated until HRDY is active (low); otherwise, HPI writes will not
complete properly.
38
th(HRDYL-HSTBL)
1.1
ns
(1) HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT (HDS1 XOR HDS2)] OR HCS.
(2) M = SYSCLK3 period = 6/CPU clock frequency in ns.
(3) Select signals include: HCNTL[1:0] and HR/W. For HPI16 mode only, select signals also include HHWIL.
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Table 6-66. Switching Characteristics for Host-Port Interface Cycles(1) (2)
(see Figure 6-40 through Figure 6-47)
720, 800, 900, 1100
NO.
PARAMETER
UNIT
MIN
MAX
Case 1. HPIC or HPIA read
5
15
Case 2. HPID read with no
auto-increment(3)
9 × M + 20
9 × M + 20
Delay time, HSTROBE low to
DSP data valid
Case 3. HPID read with auto-increment
and read FIFO initially empty(3)
1
td(HSTBL-HDV)
ns
Case 4. HPID read with auto-increment
and data previously prefetched into the
read FIFO
5
15
2
3
4
5
tdis(HSTBH-HDV)
ten(HSTBL-HD)
td(HSTBL-HRDYH)
td(HSTBH-HRDYH)
Disable time, HD high-impedance from HSTROBE high
Enable time, HD driven from HSTROBE low
Delay time, HSTROBE low to HRDY high
Delay time, HSTROBE high to HRDY high
Case 1. HPID read with no
1
3
4
15
12
12
ns
ns
ns
ns
10 × M + 20
10 × M + 20
auto-increment(3)
Delay time, HSTROBE low to
6
td(HSTBL-HRDYL)
ns
HRDY low
Case 2. HPID read with auto-increment
and read FIFO initially empty(3)
7
td(HDV-HRDYL)
td(DSH-HRDYL)
Delay time, HD valid to HRDY low
0
ns
ns
Case 1. HPIA write(3)
5 × M + 20
5 × M + 20
Delay time, HSTROBE high to
HRDY low
34
Case 2. HPID write with no
auto-increment(3)
Delay time, HSTROBE low to HRDY low for HPIA write and FIFO not
empty(3)
35
36
td(HSTBL-HRDYL)
td(HASL-HRDYH)
40 × M + 20
12
ns
ns
Delay time, HAS low to HRDY high
(1) M = SYSCLK3 period = 6/CPU clock frequency in ns.
(2) HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
(3) Assumes the HPI is accessing L2/L1 memory and no other master is accessing the same memory location.
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HCS
HAS
HCNTL[1:0]
HR/W
HHWIL
13
16
13
16
15
15
37
37
14
HSTROBE
3
3
1
1
2
2
HD[15:0]
38
4
7
6
HRDY
A. HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
B. Depending on the type of write or read operation (HPID without auto-incrementing; HPIA, HPIC, or HPID with
auto-incrementing) and the state of the FIFO, transitions on HRDY may or may not occur. For more detailed
information on the HPI peripheral, see the TMS320DM647/DM648 DSP Host Port Interface (HPI) User's Guide
(literature number SPRUEL5).
Figure 6-40. HPI16 Read Timing (HAS Not Used, Tied High)
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HCS
HAS
12
11
12
11
HCNTL[1:0]
12
11
12
11
HR/W
12
11
12
11
HHWIL
10
9
13
10
9
37
13
37
14
(A)
HSTROBE
1
3
1
2
3
2
HD[15:0]
7
38
36
6
(B)
HRDY
A. HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
B. Depending on the type of write or read operation (HPID without auto-incrementing; HPIA, HPIC, or HPID with
auto-incrementing) and the state of the FIFO, transitions on HRDY may or may not occur. For more detailed
information on the HPI peripheral, see the TMS320DM647/DM648 DSP Host Port Interface (HPI) User's Guide
(literature number SPRUEL5).
Figure 6-41. HPI16 Read Timing (HAS Used)
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HCS
HAS
HCNTL[1:0]
HR/W
HHWIL
16
16
13
15
15
13
37
14
37
(A)
HSTROBE
18
18
17
17
HD[15:0]
34
38
4
34
5
35
5
(B)
HRDY
A. HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
B. Depending on the type of write or read operation (HPID without auto-incrementing; HPIA, HPIC, or HPID with
auto-incrementing) and the state of the FIFO, transitions on HRDY may or may not occur. For more detailed
information on the HPI peripheral, see the TMS320DM647/DM648 DSP Host Port Interface (HPI) User's Guide
(literature number SPRUEL5).
Figure 6-42. HPI16 Write Timing (HAS Not Used, Tied High)
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HCS
HAS
12
11
12
11
HCNTL[1:0]
12
11
12
11
HR/W
12
11
12
11
HHWIL
10
9
13
10
9
37
13
37
14
(A)
HSTROBE
1
3
1
2
3
2
HD[15:0]
7
38
36
6
(B)
HRDY
A. HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
B. Depending on the type of write or read operation (HPID without auto-incrementing; HPIA, HPIC, or HPID with
auto-incrementing) and the state of the FIFO, transitions on HRDY may or may not occur. For more detailed
information on the HPI peripheral, see the TMS320DM647/DM648 DSP Host Port Interface (HPI) User's Guide
(literature number SPRUEL5).
Figure 6-43. HPI16 Write Timing (HAS Used)
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HAS (input)
15
16
HCNTL[1:0] (input)
HR/W (input)
13
(A)
HSTROBE (input)
37
HCS (input)
1
2
3
HD[31:0] (output)
38
7
6
4
(B)
HRDY (output)
A. HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT (HDS1 XOR HDS2)] OR HCS.
B. Depending on the type of write or read operation (HPID without auto-incrementing; HPIA, HPIC, or HPID with
auto-incrementing) and the state of the FIFO, transitions on HRDY may or may not occur. For more detailed
information on the HPI peripheral, see the TMS320DM647/DM648 DSP Host Port Interface (HPI) User's Guide
(literature number SPRUEL5)
Figure 6-44. HPI32 Read Timing (HAS Not Used, Tied High)
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10
HAS (input)
12
11
HCNTL[1:0] (input)
HR/W (input)
9
13
(A)
HSTROBE
(input)
37
HCS (input)
1
2
3
HD[31:0] (output)
7
38
6
36
(B)
HRDY
(output)
A. HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT (HDS1 XOR HDS2)] OR HCS.
B. Depending on the type of write or read operation (HPID without auto-incrementing; HPIA, HPIC, or HPID with
auto-incrementing) and the state of the FIFO, transitions on HRDY may or may not occur. For more detailed
information on the HPI peripheral, see the TMS320DM647/DM648 DSP Host Port Interface (HPI) User's Guide
(literature number SPRUEL5)
Figure 6-45. HPI32 Read Timing (HAS Used)
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HAS (input)
16
15
HCNTL[1:0]
(input)
HR/W (input)
13
(A)
HSTROBE
(input)
37
HCS (input)
18
17
HD[31:0] (input)
38
34
35
5
4
(B)
HRDY (output)
A. HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT (HDS1 XOR HDS2)] OR HCS.
B. Depending on the type of write or read operation (HPID without auto-incrementing; HPIA, HPIC, or HPID with
auto-incrementing) and the state of the FIFO, transitions on HRDY may or may not occur. For more detailed
information on the HPI peripheral, see the TMS320DM647/DM648 DSP Host Port Interface (HPI) User's Guide
(literature number SPRUEL5)
Figure 6-46. HPI32 Write Timing (HAS Not Used, Tied High)
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10
HAS (input)
12
11
HCNTL[1:0]
(input)
HR/W (input)
9
13
(A)
HSTROBE
(input)
37
HCS (input)
18
17
HD[31:0] (input)
35
34
5
38
36
(B)
HRDY (output)
A. HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
B. Depending on the type of write or read operation (HPID without auto-incrementing; HPIA, HPIC, or HPID with
auto-incrementing) and the state of the FIFO, transitions on HRDY may or may not occur. For more detailed
information on the HPI peripheral, see the TMS320DM647/DM648 DSP Host Port Interface (HPI) User's Guide
(literature number SPRUEL5)
Figure 6-47. HPI32 Write Timing (HAS Used)
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6.17 Peripheral Component Interconnect (PCI)
The device supports connections to a PCI backplane via the integrated PCI master/slave bus interface.
The PCI port interfaces to DSP internal resources via the data switched central resource. .
For more detailed information on the PCI port peripheral module, see the TMS320DM647/DM648
Peripheral Component Interconnect (PCI) User's Guide (literature number SPRUEL4).
6.17.1 PCI Device-Specific Information
The PCI peripheral conforms to the PCI Local Bus Specification (version 2.3). The PCI peripheral can act
both as a PCI bus master and as a target. It supports PCI bus operation of speeds up to 66 MHz and uses
a 32-bit data/address bus.
The pins of the PCI peripheral are multiplexed with the pins of the HPI, and GPIO peripherals. PCI
functionality for these pins is controlled (enabled/disabled) by the UHPIEN pin (H2). The maximum speed
of the PCI, 33 MHz or 66 MHz, is controlled through the PCI66 pin (G5). For more detailed information on
the peripheral control, see Section 3.
The device provides an initialization mechanism through which the default values for some of the PCI
configuration registers can be read from an I2C EEPROM. Table 6-67 shows the registers which can be
initialized through the PCI auto-initialization. Also shown is the default value of these registers when PCI
auto-initialization is not used. PCI auto-initialization is enabled by selecting PCI boot with
auto-initialization. For more information on this feature, see the TMS320DM647/DM648 Peripheral
Component Interconnect (PCI) User's Guide (literature number SPRUEL4) and the Using the
TMS320DM647/DM648 Bootloader Application Report (literature number SPRAAJ1).
Table 6-67. Default Values for PCI Configuration
Registers
DEFAULT
REGISTER
VALUE
Vendor ID/Device ID Register (PCIVENDEV)
Class Code/Revision ID Register (PCICLREV)
104C B003h
0000 0001h
0000 0000h
Subsystem Vendor ID/Subsystem ID Register
(PCISUBID)
Max Latency/Min Grant/Interrupt Pin/Interrupt Line
Register (PCILGINT)
0000 0100h
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6.17.2 PCI Peripheral Register Description(s)
Table 6-68. PCI Configuration Registers
PCI HOST ACCESS
HEX ADDRESS OFFSET
ACRONYM
PCI HOST ACCESS REGISTER NAME
0x00
0x04
PCIVENDEV
PCICSR
PCICLREV
PCICLINE
PCIBAR0
PCIBAR1
PCIBAR2
PCIBAR3
PCIBAR4
PCIBAR5
-
Vendor ID/Device ID
Command/Status
0x08
Class Code/Revision ID
BIST/Header Type/Latency Timer/Cacheline Size
Base Address 0
0x0C
0x10
0x14
Base Address 1
0x18
Base Address 2
0x1C
Base Address 3
0x20
Base Address 4
0x24
Base Address 5
0x28 - 0x2B
0x2C
Reserved
PCISUBID
-
Subsystem Vendor ID/Subsystem ID
Reserved
0x30
0x34
PCICPBPTR
-
Capabilities Pointer
Reserved
0x38 - 0x3B
0x3C
PCILGINT
-
Max Latency/Min Grant/Interrupt Pin/Interrupt Line
Reserved
0x40 - 0x7F
Table 6-69. PCI Back End Configuration Registers
DSP ACCESS
HEX ADDRESS RANGE
ACRONYM
DSP ACCESS REGISTER NAME
0x0204 8400 - 0x0204 840F
0x0204 8410
-
Reserved
PCISTATSET
PCISTATCLR
-
PCI Status Set Register
0x0204 8414
PCI Status Clear Register
0x0204 8418 - 0x0204 841F
0x0204 8420
Reserved
PCIHINTSET
PCIHINTCLR
-
PCI Host Interrupt Enable Set Register
PCI Host Interrupt Enable Clear Register
Reserved
0x0204 8424
0x0204 8428 - 0x0204 842F
0x0204 8430
PCIBINTSET
PCIBINTCLR
PCIBCLKMGT
-
PCI Back End Application Interrupt Enable Set Register
PCI Back End Application Interrupt Enable Clear Register
PCI Back End Application Clock Management Register
Reserved
0x0204 8434
0x0204 8438
0x0204 843C - 0x0204 84FF
0x0204 8500
PCIVENDEVMIR PCI Vendor ID/Device ID Mirror Register
PCICSRMIR PCI Command/Status Mirror Register
PCICLREVMIR PCI Class Code/Revision ID Mirror Register
0x0204 8504
0x0204 8508
0x0204 850C
PCICLINEMIR
PCIBAR0MSK
PCIBAR1MSK
PCIBAR2MSK
PCIBAR3MSK
PCIBAR4MSK
PCIBAR5MSK
-
PCI BIST/Header Type/Latency Timer/Cacheline Size Mirror Register
0x0204 8510
PCI Base Address Mask Register 0
PCI Base Address Mask Register 1
PCI Base Address Mask Register 2
PCI Base Address Mask Register 3
PCI Base Address Mask Register 4
PCI Base Address Mask Register 5
Reserved
0x0204 8514
0x0204 8518
0x0204 851C
0x0204 8520
0x0204 8524
0x0204 8528 - 0x0204 852B
0x0204 852C
PCISUBIDMIR
PCI Subsystem Vendor ID/Subsystem ID Mirror Register
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Table 6-69. PCI Back End Configuration Registers (continued)
DSP ACCESS
HEX ADDRESS RANGE
ACRONYM
DSP ACCESS REGISTER NAME
0x0204 8530
0x0204 8534
-
Reserved
PCICPBPTRMIR PCI Capabilities Pointer Mirror Register
0x0204 8538 - 0x0204 853B
0x0204 853C
-
Reserved
PCILGINTMIR
-
PCI Max Latency/Min Grant/Interrupt Pin/Interrupt Line Mirror Register
Reserved
0x0204 8540 - 0x0204 857F
0x0204 8580
PCISLVCNTL
-
PCI Slave Control Register
0x0204 8584 - 0x0204 85BF
0x0204 85C0
Reserved
PCIBAR0TRL
PCIBAR1TRL
PCIBAR2TRL
PCIBAR3TRL
PCIBAR4TRL
PCIBAR5TRL
-
PCI Slave Base Address 0 Translation Register
PCI Slave Base Address 1 Translation Register
PCI Slave Base Address 2 Translation Register
PCI Slave Base Address 3 Translation Register
PCI Slave Base Address 4 Translation Register
PCI Slave Base Address 5 Translation Register
Reserved
0x0204 85C4
0x0204 85C8
0x0204 85CC
0x0204 85D0
0x0204 85D4
0x0204 85D8 - 0x0204 85DF
0x0204 85E0
PCIBAR0MIR
PCIBAR1MIR
PCIBAR2MIR
PCIBAR3MIR
PCIBAR4MIR
PCIBAR5MIR
-
PCI Base Address Register 0 Mirror Register
PCI Base Address Register 1 Mirror Register
PCI Base Address Register 2 Mirror Register
PCI Base Address Register 3 Mirror Register
PCI Base Address Register 4 Mirror Register
PCI Base Address Register 5 Mirror Register
Reserved
0x0204 85E4
0x0204 85E8
0x0204 85EC
0x0204 85F0
0x0204 85F4
0x0204 85F8 - 0x0204 86FF
0x0204 8700
PCIMCFGDAT PCI Master Configuration/IO Access Data Register
PCIMCFGADR PCI Master Configuration/IO Access Address Register
PCIMCFGCMD PCI Master Configuration/IO Access Command Register
0x0204 8704
0x0204 8708
0x0204 870C - 0x0204 870F
0x0204 8710
-
Reserved
PCIMSTCFG
PCI Master Configuration Register
Table 6-70. PCI Hook Configuration Registers
DSP ACCESS
HEX ADDRESS RANGE
ACRONYM
DSP ACCESS REGISTER NAME
0x0204 8794
0x0204 8798
0x0204 879C
0x0204 87A0
0x0204 87A4
0x0204 87A8
0x0204 87AC
0x0204 87B0
0x0204 87B4
0x0204 87B8
0x0204 87BC
0x0204 87C0
0x0204 87C4
0x0204 87C8
0x0204 87CC
0x0204 87D0
PCIVENDEVPRG PCI Vendor ID and Device ID Program Register
PCICMDSTATPRG PCI Command and Status Program Register
PCICLREVPRG
PCISUBIDPRG
PCI Class Code and Revision ID Program Register
PCI Subsystem Vendor ID and Subsystem ID Program Register
PCIMAXLGPRG PCI Max Latency and Min Grant Program Register
PCILRSTREG
PCICFGDONE
PCI LRESET Register
PCI Configuration Done Register
PCIBAR0MPRG PCI Base Address Mask Register 0 Program Register
PCIBAR1MPRG PCI Base Address Mask Register 1 Program Register
PCIBAR2MPRG PCI Base Address Mask Register 2 Program Register
PCIBAR3MPRG PCI Base Address Mask Register 3 Program Register
PCIBAR4MPRG PCI Base Address Mask Register 4 Program Register
PCIBAR5MPRG PCI Base Address Mask Register 5 Program Register
PCIBAR0PRG
PCIBAR1PRG
PCIBAR2PRG
PCI Base Address Register 0 Program Register
PCI Base Address Register 1 Program Register
PCI Base Address Register 2 Program Register
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Table 6-70. PCI Hook Configuration Registers (continued)
DSP ACCESS
HEX ADDRESS RANGE
ACRONYM
DSP ACCESS REGISTER NAME
0x0204 87D4
PCIBAR3PRG
PCIBAR4PRG
PCIBAR5PRG
PCI Base Address Register 3 Program Register
0x0204 87D8
PCI Base Address Register 4 Program Register
PCI Base Address Register 5 Program Register
0x0204 87DC
0x0204 87E0
PCIBAR0TRLPRG PCI Base Address Translation Register 0 Program Register
PCIBAR1TRLPRG PCI Base Address Translation Register 1 Program Register
PCIBAR2TRLPRG PCI Base Address Translation Register 2 Program Register
PCIBAR3TRLPRG PCI Base Address Translation Register 3 Program Register
PCIBAR4TRLPRG PCI Base Address Translation Register 4 Program Register
PCIBAR5TRLPRG PCI Base Address Translation Register 5 Program Register
PCIBASENPRG PCI Base En Prog Register
0x0204 87E4
0x0204 87E8
0x0204 87EC
0x0204 87F0
0x0204 87F4
0x0204 87F8
0x0204 87FC - 0x0204 87FF
-
Reserved
Table 6-71. PCI External Memory Space
HEX ADDRESS OFFSET
0x4000 0000 - 0x407F FFFF
0x4080 0000 - 0x40FF FFFF
0x4100 0000 - 0x417F FFFF
0x4180 0000 - 0x41FF FFFF
0x4200 0000 - 0x427F FFFF
0x4280 0000 - 0x42FF FFFF
0x4300 0000 - 0x437F FFFF
0x4380 0000 - 0x43FF FFFF
0x4400 0000 - 0x447F FFFF
0x4480 0000 - 0x44FF FFFF
0x4500 0000 - 0x457F FFFF
0x4580 0000 - 0x45FF FFFF
0x4600 0000 - 0x467F FFFF
0x4680 0000 - 0x46FF FFFF
0x4700 0000 - 0x477F FFFF
0x4780 0000 - 0x47FF FFFF
0x4800 0000 - 0x487F FFFF
0x4880 0000 - 0x48FF FFFF
0x4900 0000 - 0x497F FFFF
0x4980 0000 - 0x49FF FFFF
0x4A00 0000 - 0x4A7F FFFF
0x4A80 0000 - 0x4AFF FFFF
0x4B00 0000 - 0x4B7F FFFF
0x4B80 0000 - 0x4BFF FFFF
0x4C00 0000 - 0x4C7F FFFF
0x4C80 0000 - 0x4CFF FFFF
0x4D00 0000 - 0x4D7F FFFF
0x4D80 0000 - 0x4DFF FFFF
0x4E00 0000 - 0x4E7F FFFF
0x4E80 0000 - 0x4EFF FFFF
0x4F00 0000 - 0x4F7F FFFF
0x4F80 0000 - 0x4FFF FFFF
ACRONYM
REGISTER NAME
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PCI Master Window 0
PCI Master Window 1
PCI Master Window 2
PCI Master Window 3
PCI Master Window 4
PCI Master Window 5
PCI Master Window 6
PCI Master Window 7
PCI Master Window 8
PCI Master Window 9
PCI Master Window 10
PCI Master Window 11
PCI Master Window 12
PCI Master Window 13
PCI Master Window 14
PCI Master Window 15
PCI Master Window 16
PCI Master Window 17
PCI Master Window 18
PCI Master Window 19
PCI Master Window 20
PCI Master Window 21
PCI Master Window 22
PCI Master Window 23
PCI Master Window 24
PCI Master Window 25
PCI Master Window 26
PCI Master Window 27
PCI Master Window 28
PCI Master Window 29
PCI Master Window 30
PCI Master Window 31
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6.17.3 PCI Electrical Data/Timing
Texas Instruments (TI) has performed the simulation and system characterization to be sure that the PCI
peripheral meets all ac timing specifications as required by the PCI Local Bus Specification (version 2.3).
The ac timing specifications are not reproduced here. For more information on the ac timing specifications,
see Section 4.2.3, Timing Specification (33 MHz timing), and Section 7.6.4, Timing Specification (66 MHz
timing), of the PCI Local Bus Specification (version 2.3). Note that the PCI peripheral only supports 3.3-V
signaling.
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6.18 Multichannel Audio Serial Port (McASP)
The McASP functions as a general-purpose audio serial port optimized for the needs of multichannel
audio applications. The McASP is useful for time-division multiplexed (TDM) stream, Inter-Integrated
Sound (I2S) protocols, and intercomponent digital audio interface transmission (DIT).
6.18.1 McASP Device-Specific Information
The device includes one multichannel audio serial port (McASP) interface peripheral. The McASP is a
serial port optimized for the needs of multichannel audio applications.
The McASP consists of a transmit and receive section. These sections can operate completely
independently with different data formats, separate master clocks, bit clocks, and frame syncs or
alternatively, the transmit and receive sections may be synchronized. The McASP module also includes a
pool of 16 shift registers that may be configured to operate as either transmit data or receive data.
The transmit section of the McASP can transmit data in either a time-division-multiplexed (TDM)
synchronous serial format or in a digital audio interface (DIT) format where the bit stream is encoded for
S/PDIF, AES-3, IEC-60958, CP-430 transmission. The receive section of the McASP supports the TDM
synchronous serial format.
The McASP can support one transmit data format (either a TDM format or DIT format) and one receive
format at a time. All transmit shift registers use the same format and all receive shift registers use the
same format. However, the transmit and receive formats need not be the same.
Both the transmit and receive sections of the McASP also support burst mode which is useful for
non-audio data (for example, passing control information between two DSPs).
The McASP peripheral has additional capability for flexible clock generation, and error detection/handling,
as well as error management.
For more detailed information on and the functionality of the McASP peripheral, see the
TMS320DM647/DM648 Multichannel Audio Serial Port (McASP) User's Guide (literature number
SPRUEL1).
6.18.1.1 McASP Block Diagram
Figure 6-48 illustrates the major blocks along with external signals of the McASP peripheral; and shows
the 10 serial data [AXR] pins.
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McASP
Transmit
Frame Sync
Generator
DIT
RAM
AFSX
T
ransmit
Transmit
Clock
Generator
AHCLKX
ACLKX
Clock Check
(High-
Frequency)
AMUTE
Error
Detect
AMUTEIN
Receive
Clock Check
(High-
Receive
Clock
Generator
AHCLKR
ACLKR
Frequency)
Transmit
Data
Formatter
Receive
Frame Sync
Generator
AFSR
Serializer 0
AXR0[0]
AXR0[1]
AXR0[2]
AXR0[3]
Serializer 1
Serializer 2
Serializer 3
Serializer 9
AXR0[9]
Receive
Data
Formatter
GPIO
Control
Figure 6-48. McASP Configuration
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6.18.1.2 McASP Peripheral Register Description(s)
Table 6-72. McASP Control Registers
HEX ADDRESS RANGE
0x0204 0000
ACRONYM
REGISTER NAME
Peripheral Identification register [Register value: 0x0010 0101]
Power down and emulation management register
Reserved
PID
PWRDEMU
-
0x0204 0004
0x0204 0008
0x0204 000C
0x0204 0010
-
Reserved
PFUNC
PDIR
Pin function register
0x0204 0014
Pin direction register
0x0204 0018
PDOUT
Pin data out register
Pin data in/data set register
Read returns: PDIN
0x0204 001C
PDIN/PDSET
Writes affect: PDSET
0x0204 0020
0x0204 0024 - 0x0204 0040
0x0204 0044
PDCLR
-
Pin data clear register
Reserved
GBLCTL
AMUTE
DLBCTL
DITCTL
Global control register
Mute control register
Digital Loop-back control register
DIT mode control register
0x0204 0048
0x0204 004C
0x0204 0050
0x0204 0054 - 0x0204
005C
-
Reserved
Alias of GBLCTL containing only Receiver Reset bits, allows transmit to be reset
independently from receive.
0x0204 0060
RGBLCTL
0x0204 0064
0x0204 0068
0x0204 006C
0x0204 0070
0x0204 0074
0x0204 0078
0x0204 007C
0x0204 0080
0x0204 0084
0x0204 0088
RMASK
RFMT
Receiver format UNIT bit mask register
Receive bit stream format register
Receive frame sync control register
Receive clock control register
AFSRCTL
ACLKRCTL
AHCLKRCTL
RTDM
High-frequency receive clock control register
Receive TDM slot 0-31 register
Receiver interrupt control register
Status register - Receiver
RINTCTL
RSTAT
RSLOT
Current receive TDM slot register
Receiver clock check control register
RCLKCHK
0x0204 008C - 0x0204
009C
-
Reserved
Alias of GBLCTL containing only Transmitter Reset bits, allows transmit to be reset
independently from receive.
0x0204 00A0
XGBLCTL
0x0204 00A4
0x0204 00A8
0x0204 00AC
0x0204 00B0
0x0204 00B4
0x0204 00B8
0x0204 00BC
0x0204 00C0
0x0204 00C4
0x0204 00C8
XMASK
XFMT
Transmit format UNIT bit mask register
Transmit bit stream format register
Transmit frame sync control register
Transmit clock control register
AFSXCTL
ACLKXCTL
AHCLKXCTL
XTDM
High-frequency Transmit clock control register
Transmit TDM slot 0-31 register
Transmit interrupt control register
Status register - Transmitter
XINTCTL
XSTAT
XSLOT
Current transmit TDM slot
XCLKCHK
Transmit clock check control register
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Table 6-72. McASP Control Registers (continued)
HEX ADDRESS RANGE
ACRONYM
REGISTER NAME
0x0204 00CC - 0x0204
00FC
-
Reserved
0x0204 0100
0x0204 0104
0x0204 0108
0x0204 010C
0x0204 0110
0x0204 0114
0x0204 0118
0x0204 011C
0x0204 0120
0x0204 0124
0x0204 0128
0x0204 012C
0x0204 0130
0x0204 0134
0x0204 0138
0x0204 013C
0x0204 0140
0x0204 0144
0x0204 0148
0x0204 014C
0x0204 0150
0x0204 0154
0x0204 0158
0x0204 015C
DITCSRA0
DITCSRA1
DITCSRA2
DITCSRA3
DITCSRA4
DITCSRA5
DITCSRB0
DITCSRB1
DITCSRB2
DITCSRB3
DITCSRB4
DITCSRB5
DITUDRA0
DITUDRA1
DITUDRA2
DITUDRA3
DITUDRA4
DITUDRA5
DITUDRB0
DITUDRB1
DITUDRB2
DITUDRB3
DITUDRB4
DITUDRB5
Left (even TDM slot) channel status register file
Left (even TDM slot) channel status register file
Left (even TDM slot) channel status register file
Left (even TDM slot) channel status register file
Left (even TDM slot) channel status register file
Left (even TDM slot) channel status register file
Right (odd TDM slot) channel status register file
Right (odd TDM slot) channel status register file
Right (odd TDM slot) channel status register file
Right (odd TDM slot) channel status register file
Right (odd TDM slot) channel status register file
Right (odd TDM slot) channel status register file
Left (even TDM slot) user data register file
Left (even TDM slot) user data register file
Left (even TDM slot) user data register file
Left (even TDM slot) user data register file
Left (even TDM slot) user data register file
Left (even TDM slot) user data register file
Right (odd TDM slot) user data register file
Right (odd TDM slot) user data register file
Right (odd TDM slot) user data register file
Right (odd TDM slot) user data register file
Right (odd TDM slot) user data register file
Right (odd TDM slot) user data register file
0x0204 0160 - 0x0204
017C
-
Reserved
0x0204 0180
0x0204 0184
0x0204 0188
0x0204 018C
0x0204 0190
0x0204 0194
0x0204 0198
0x0204 019C
0x0204 01A0
0x0204 01A4
SRCTL0
SRCTL1
SRCTL2
SRCTL3
SRCTL4
SRCTL5
SRCTL6
SRCTL7
SRCTL8
SRCTL9
Serializer 0 control register
Serializer 1 control register
Serializer 2 control register
Serializer 3 control register
Serializer 4 control register
Serializer 5 control register
Serializer 6 control register
Serializer 7 control register
Serializer 8 control register
Serializer 9 control register
0x0204 01A8 - 0x0204
01FC
-
Reserved
0x0204 0200
0x0204 0204
0x0204 0208
0x0204 020C
0x0204 0210
0x0204 0214
0x0204 0218
0x0204 021C
XBUF0
XBUF1
XBUF2
XBUF3
XBUF4
XBUF5
XBUF6
XBUF7
Transmit Buffer for Serializer 0
Transmit Buffer for Serializer 1
Transmit Buffer for Serializer 2
Transmit Buffer for Serializer 3
Transmit Buffer for Serializer 4
Transmit Buffer for Serializer 5
Transmit Buffer for Serializer 6
Transmit Buffer for Serializer 7
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Table 6-72. McASP Control Registers (continued)
HEX ADDRESS RANGE
0x0204 021A
ACRONYM
XBUF8
XBUF9
-
REGISTER NAME
Transmit Buffer for Serializer 8
Transmit Buffer for Serializer 9
Reserved
0x0204 0220
0x0204 0224-0x0204 027C
0x0204 0280
RBUF0
RBUF1
RBUF2
RBUF3
RBUF4
RBUF5
RBUF6
RBUF7
RBUF8
RBUF9
-
Receive Buffer for Serializer 0
Receive Buffer for Serializer 1
Receive Buffer for Serializer 2
Receive Buffer for Serializer 3
Receive Buffer for Serializer 4
Receive Buffer for Serializer 5
Receive Buffer for Serializer 6
Receive Buffer for Serializer 7
Receive Buffer for Serializer 8
Receive Buffer for Serializer 9
Reserved
0x0204 0284
0x0204 0288
0x0204 028C
0x0204 0290
0x0204 0294
0x0204 0298
0x0204 029C
0x0204 02A0
0x0204 02A4
0x0204 02A8-0x0204 3FFF
Table 6-73. McASP Data Registers
HEX ADDRESS RANGE
ACRONYM
REGISTER NAME
COMMENTS
(Used when RSEL or XSEL bits = 0
[these bits are located in the RFMT or
XFMT registers, respectively].)
McASP receive buffers or McASP transmit
buffers via the Peripheral Data Bus.
0204 4000 - 0204 43FF
RBUF/XBUF
6.18.1.3 McASP Electrical Data/Timing
6.18.1.3.1 Multichannel Audio Serial Port (McASP) Timing
Table 6-74. Timing Requirements for McASP (see Figure 6-49 and Figure 6-50)(1)
720, 800, 900,
1100
NO.
UNIT
MIN
MAX
1
2
3
4
tc(AHCKRX)
tw(AHCKRX)
tc(CKRX)
Cycle time, AHCLKR/X
20
10
33
16.5
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Pulse duration, AHCLKR/X high or low
Cycle time, ACLKR/X
ACLKR/X ext
ACLKR/X ext
ACLKR/X int
ACLKR/X ext
ACLKR/X int
ACLKR/X ext
ACLKR/X int
ACLKR/X ext
ACLKR/X int
ACLKR/X ext
tw(CKRX)
Pulse duration, ACLKR/X high or low
5
6
7
8
tsu(FRX-CKRX)
th(CKRX-FRX)
tsu(AXR-CKRX)
th(CKRX-AXR)
Setup time, AFSR/X input valid before ACLKR/X latches data
Hold time, AFSR/X input valid after ACLKR/X latches data
Setup time, AXR input valid before ACLKR/X latches data
Hold time, AXR input valid after ACLKR/X latches data
5
5
12.08
5
5
5
7.35
(1) ACLKX internal: ACLKXCTL.CLKXM=1, PDIR.ACLKX = 1
ACLKX external input: ACLKXCTL.CLKXM=0, PDIR.ACLKX=0
ACLKX external output: ACLKXCTL.CLKXM=0, PDIR.ACLKX=1
ACLKR internal: ACLKRCTL.CLKRM=1, PDIR.ACLKR = 1
ACLKR external input: ACLKRCTL.CLKRM=0, PDIR.ACLKR=0
ACLKR external output: ACLKRCTL.CLKRM=0, PDIR.ACLKR=1
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Table 6-75. Switching Characteristics Over Recommended Operating Conditions for McASP
(see Figure 6-49 and Figure 6-50)(1)
720, 800, 900,
1100
NO.
PARAMETER
UNIT
MIN
MAX
9
tc(AHCKRX)
tw(AHCKRX)
tc(CKRX)
Cycle time, AHCLKR/X
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
10
11
12
Pulse duration, AHCLKR/X high or low
Cycle time, ACLKR/X
10
33
ACLKR/X int
ACLKR/X int
ACLKR/X int
ACLKR/X ext
ACLKX int
tw(CKRX)
Pulse duration, ACLKR/X high or low
16.5
5
13
14
15
td(CKRX-FRX)
Delay time, ACLKR/X transmit edge to AFSX/R output valid
Delay time, ACLKX transmit edge to AXR output valid
14.28
10
td(CKX-AXRV)
ACLKX ext
12.5
10
ACLKR/X int
ACLKR/X ext
Disable time, AXR high impedance following last data bit from
ACLKR/X transmit edge
tdis(CKRX-AXRHZ)
12.5
(1) ACLKX internal: ACLKXCTL.CLKXM=1, PDIR.ACLKX = 1
ACLKX external input: ACLKXCTL.CLKXM=0, PDIR.ACLKX=0
ACLKX external output: ACLKXCTL.CLKXM=0, PDIR.ACLKX=1
ACLKR internal: ACLKRCTL.CLKRM=1, PDIR.ACLKR = 1
ACLKR external input: ACLKRCTL.CLKRM=0, PDIR.ACLKR=0
ACLKR external output: ACLKRCTL.CLKRM=0, PDIR.ACLKR=1
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2
1
2
AHCLKR/X (Falling Edge Polarity)
AHCLKR/X (Rising Edge Polarity)
4
3
4
(A)
ACLKR/X (CLKRP = CLKXP = 0)
(B)
ACLKR/X (CLKRP = CLKXP = 1)
6
5
AFSR/X (Bit Width, 0 Bit Delay)
AFSR/X (Bit Width, 1 Bit Delay)
AFSR/X (Bit Width, 2 Bit Delay)
AFSR/X (Slot Width, 0 Bit Delay)
AFSR/X (Slot Width, 1 Bit Delay)
AFSR/X (Slot Width, 2 Bit Delay)
8
7
AXR[n] (Data In/Receive)
A0 A1
A30 A31 B0 B1
B30 B31 C0 C1 C2 C3
C31
A. For CLKRP = CLKXP = 0, the McASP transmitter is configured for rising edge (to shift data out) and the McASP
receiver is configured for falling edge (to shift data in).
B. For CLKRP = CLKXP = 1, the McASP transmitter is configured for falling edge (to shift data out) and the McASP
receiver is configured for rising edge (to shift data in).
Figure 6-49. McASP Input Timing
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10
10
9
AHCLKR/X (Falling Edge Polarity)
AHCLKR/X (Rising Edge Polarity)
12
11
12
(A)
ACLKR/X (CLKRP = CLKXP = 1)
(B)
ACLKR/X (CLKRP = CLKXP = 0)
13
13
13
13
AFSR/X (Bit Width, 0 Bit Delay)
AFSR/X (Bit Width, 1 Bit Delay)
AFSR/X (Bit Width, 2 Bit Delay)
AFSR/X (Slot Width, 0 Bit Delay)
AFSR/X (Slot Width, 1 Bit Delay)
AFSR/X (Slot Width, 2 Bit Delay)
AXR[n] (Data Out/Transmit)
13
13
13
14
15
A0 A1
A30 A31 B0 B1
B30 B31 C0 C1 C2 C3
C31
A. For CLKRP = CLKXP = 1, the McASP transmitter is configured for falling edge (to shift data out) and the McASP
receiver is configured for rising edge (to shift data in).
B. For CLKRP = CLKXP = 0, the McASP transmitter is configured for rising edge (to shift data out) and the McASP
receiver is configured for falling edge (to shift data in).
Figure 6-50. McASP Output Timing
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6.19 3-Port Ethernet Switch Subsystem (3PSW)
The Ethernet module controls the flow of packet data between the device and two external Ethernet PHYs
(DM648 only) or one external Ethernet PHY (DM647 only), with hardware flow control and
quality-of-service (QOS) support. See Figure 6-51 for a block diagram of the Ethernet module. The
Ethernet Subsystem contains a 3-port gigabit switch, where one port is internally connected to the C64x+
DSP (via the switched central resource) and the other two ports are brought out externally. Each of the
external Ethernet ports support the modes shown in Table 6-76.
The Ethernet module controls the flow of packet data between the device and two external Ethernet PHYs
, with hardware flow control and quality-of-service (QOS) support. See Figure 6-51 for a block diagram of
the Ethernet module. The Ethernet Subsystem contains a 3-port gigabit switch, where one port is
internally connected to the C64x+ DSP (via the switched central resource) and the other two ports are
brought out externally. Each of the external Ethernet ports support the modes shown in Table 6-76.
Table 6-76. Ethernet Operating Modes
DESCRIPTION
10Base-T
DATA RATE
OPERATING MODE
half- or full-duplex
half- or full-duplex
full-duplex
10 Mbits/second (Mbps)
100 Mbits/second (Mbps)
1000 Mbits/second (Mbps)
100Base-T
1000Base-T
The Ethernet Subsystem provides these functions:
•
Ethernet communication/routing by way of two dedicated 10/100/1000 ports with SGMII interfaces
–
–
–
–
Wire-rate switching (802.1d), non-blocking switch fabric
Four priority levels of QoS TX support (802.1p) in hardware
Programmable interrupt pacing on RX/TX plus interrupt threshold on RX
Supports forwarding frame sizes of 64-2020 bytes
•
Address Lookup
–
–
–
–
–
–
–
–
–
–
–
1024 total address lookup engine (ALE) entries of VLANs and/or MAC addresses
L2 address lock and L2 filtering support
Multicast/broadcast filtering and forwarding state control
Receive-based or destination-based multicast and broadcast rate limits
MAC address blocking
Source port locking
OUI (Vendor ID) host accept/deny feature
Host controlled time-based aging
MAC authentication (802.1x)
Remapping of priority level of VLAN or ports
Multiple spanning tree support (spanning tree per VLAN)
•
VLAN support
–
802.1Q compliant
•
•
Auto add port VLAN for untagged frames on ingress
Auto VLAN removal on egress and auto pad to minimum frame size
–
–
Flow control (IEEE 802.3x)
Programmable priority escalation to specify delivery of lower priority level packets in the event of
over-subscribed TX high priority traffic
–
–
Host pass CRC mode (enables CRC protection through host)
Write-protect option for Ethernet module registers (3PGSW, CPPI RAM, MDIO, SGMII0, SGMII1,
control)
–
Ethernet statistics:
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•
•
EtherStats and 802.3 Stats RMON statistics gathering (shared)
Programmable statistics interrupt mask when a statistic is above one half its 32-bit value
–
–
MDIO module for PHY management
SGMII gigabit current mode logic (CML) differential SERializer/DESerializer (SerDes) I/O
receiver/transmitters
•
Adaptive active equalization for superior data dependent jitter tolerance in the presence of a
lossy channel
•
•
•
Loss of signal detector with programmable threshold levels in receive channels
Integrated receiver and transmitter termination
IEEE 802.3 gigabit Ethernet conformant
6.19.1 Ethernet Subsystem Functions
2
2
Configuration
Registers
Configuration
Bus
Gigabit
MAC 0
SGMII
Port 0
GMII port 0
SGMII 0
3-port
Gigabit
Switch
Host DMA
Controller
2
Peripheral
Bus
Addr Lookup
Engine
REFCLK
2
2
Buffer
Descriptor
Memory
Gigabit
MAC 1
SGMII
Port 1
SGMII 1(A)
GMII port 1
DSP
Interrupt
Controller
MII
Configuration
Bus
MDIO
Serial
Mgmt
A. SGMII port 1 is not available on DM647.
Figure 6-51. Ethernet Subsystem Block Diagram
The Ethernet Subsystem conforms to the IEEE 802.3-2002 standard. Deviating from this standard, the
GMAC module does not use the transmit coding error signal MTXER. Instead of driving the error pin when
an underflow condition occurs on a transmitted frame, the GMAC generates an incorrect checksum by
inverting the frame CRC, so that the transmitted frame will be detected as an error by the network.
In networking systems, packet transmission and reception are critical tasks. The communications port
programming interface (CPPI) protocol maximizes the efficiency of interaction between the host software
and communications modules. The CPPI block contains 2048 words of 32-bit buffer descriptor memory
that holds up to 512 buffer descriptors.
After reset, initialization, configuration, and auto-negotiation, the host C64x+ DSP may initiate Ethernet
transmit and receive operations.
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•
Transmit operations are initiated by C64x+ DSP writes to the appropriate transmit channel head
descriptor pointer contained in the CPDMA block. The CPDMA TX controller then fetches the first
packet in the packet chain from memory in accordance with the CPPI protocol for the GMAC to
process before sending to the SGMII.
•
Receive operations are initiated by C64x+ DSP writes to the appropriate receive channel head
descriptor pointer. The CPDMA RX controller then writes packets to memory in accordance with the
CPPI protocol.
DSP writes may be write-protected to the Ethernet Subsystem configuration registers from addresses
0x02D0 0000 - 0x02D0 4FFF (3PGSW, MDIO, SGMII0, SGMII1, control), and the CPPI RAM. The
Ethernet Subsystem setting in the PSC is also write-protected. A specific 32-bit lock code (0x4C6F436B)
and a 32-bit unlock code (0x6F50654E) written to ESS_LOCK register will activate or clear this option,
respectively. See Section 3.2.5 and Section 3.2.7
The 3-port gigabit switch block contains the following functions:
•
•
•
3-port gigabit switch: performs packet forwarding and routing functions, one port is internally connected
to the C64x+ DSP and two ports are brought out externally
CPDMA: performs high-speed DMA transfers with RX and TX CPPI buffers in local memory, including
channel setup and channel teardown
GMAC (Gigabit Ethernet MAC):
–
–
–
–
Uses Rx packet FIFO, and a TX packet FIFO to improve data transfer efficiency
Handles processing of Ethernet packet data, frames, and headers
Includes flow control
Provides statistics collection and reporting
•
The address lookup engine (ALE) processes all received packets to determine where (that is, which
packet location) to forward the packet. The ALE uses the incoming packet received port number,
destination address, source address, length/type, and VLAN information to determine how the packet
should be forwarded. The ALE outputs the port mask to the switch fabric that indicates to which port(s)
the packet should be forwarded.
6.19.2 Interrupt Controller and Pacing Interrupts
The interrupt control block selects the interrupts from the 3-port gigabit switch and MDIO modules for
output to the C64x+ DSP. The miscellaneous interrupt is an immediate (non-paced) interrupt selected
from the miscellaneous interrupts (host error level, statistics level, MDIO User [2], MDIO link [2]).
The eight RX interrupts and eight TX interrupts can be paced. The 8 RX threshold interrupts and the
miscellaneous interrupts are not paced. The interrupt pacing feature limits the number of interrupts that
occur during a given period of time. For heavily loaded systems in which interrupts can occur at a very
high rate, the performance benefit is significant due to minimizing the overhead associated with servicing
each interrupt. Interrupt pacing increases the C64x+ DSP cache hit ratio by minimizing the number of
times that large interrupt service routines are moved to and from the DSP instruction cache.
MDIO
The MDIO module manages the PHY configuration and monitors status. For a list of supported registers
and register fields, see Table 6-78. In 10/100 mode, the GMII_MTXD(7:0) data bus uses only the lower
nibble.
SGMII
The SGMII/SerDes module contains:
•
•
•
•
Gigabit differential current mode logic (CML) receiver/transmitters
An integrated RX/TX PLL to provide the required high-quality/high-speed internal clocks
Phase-interpolator-based clock/data recovery
A bandgap reference for transmitter swing settings
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•
•
•
•
•
Parallel-to-serial converter
Serial-to-parallel converter
Integrated receiver and transmitter termination
Configuration logic
802.3 auto-negotiation functionality (as defined in Clause 37 of the IEEE Specification 802.3)
The SGMII receive interface converts the encoded receive signals from the differential receive input
terminals (SGMII0RXN: SGMII0RXP, SGMII1RXN: SGMII1RXP) into the required GMAC GMII signals.
The SGMII transmit interface converts the GMAC GMII data into the required encoded differential transmit
output terminals (SGMII0TXN: SGMII0TXP, SGMII1TXN: SGMII1TXP). The GMAC does not source the
transmit error signal. Any transmit frame from the GMAC with an error (ie., underrun) will be indicated as
an error by an error CRC.
NOTE
SGMII1 is pinned out only in the DM648 device. The DM647 device has only one SGMII
port (SGMII0).
6.19.3 Peripheral Register Description(s)
Table 6-77 through Table 6-80 list the registers.
Table 6-77. Ethernet Switch Registers
HEX ADDRESS RANGE
0x02D0 3000
0x02D0 3004
0x02D0 3008
0x02D0 300C
0x02D0 3010
0x02D0 3014
0x02D0 3018
0x02D0 301C
0x02D0 3020
0x02D0 3024
0x02D0 3028
0x02D0 302C
0x02D0 3030
0x02D0 3034
0x02D0 3038
0x02D0 303C
0x02D0 3040
0x02D0 3044
REGISTER ACRONYM
CPSW_ID_VER
DESCRIPTION
CPSW Identification and Version Register
CPSW Switch Control Register
CPSW_CONTROL
CPSW_SOFT_RESET
CPSW_STAT_PORT_EN
CPSW_PTYPE
CPSW Soft Reset Register
CPSW Statistics Port Enable Register
CPSW Transmit Priority Type Register
CPSW Port 0 Maximum FIFO blocks Register
CPSW Port 0 FIFO Block Usage Count Register (read only)
CPSW Port 0 Flow Control Threshold Register
CPSW Port 0 VLAN Register
P0_MAX_BLKS
P0_BLK_CNT
P0_FLOW_THRESH
P0_PORT_VLAN
P0_TX_PRI_MAP
GMAC0_GAP_THRESH
GMAC0_SA_LO
CPSW Port 0 Tx Header Pri to Switch Pri Mapping Register
CPSW GMAC0 Short Gap Threshold Register
CPSW GMAC0 Source Address Low Register
CPSW GMAC0 Source Address High Register
CPSW Port 1 Maximum FIFO blocks Register
CPSW Port 1 FIFO Block Usage Count Register (read only)
CPSW Port 1 Flow Control Threshold Register
CPSW Port 1 VLAN Register
GMAC0_SA_HI
P1_MAX_BLKS
P1_BLK_CNT
P1_FLOW_THRESH
P1_PORT_VLAN
P1_TX_PRI_MAP
CPSW Port 1 Tx Header Priority to Switch Pri Mapping
Register
0x02D0 3048
0x02D0 304C
0x02D0 3050
0x02D0 3054
0x02D0 3058
0x02D0 305C
0x02D0 3060
0x02D0 3064
GMAC1_GAP_THRESH
GMAC1_SA_LO
GMAC1_SA_HI
CPSW GMAC1 Short Gap Threshold Register
CPSW GMAC1 Source Address Low Register
CPSW GMAC1 Source Address High Register
CPSW Port 2 Maximum FIFO blocks Register
CPSW Port 2 FIFO Block Usage Count Register (read only)
CPSW Port 2 Flow Control Threshold Register
CPSW Port 2 VLAN Register
P2_MAX_BLKS
P2_BLK_CNT
P2_FLOW_THRESH
P2_PORT_VLAN
P2_TX_PRI_MAP
CPSW Port 2 Tx (CPDMA Rx) Header Priority to Switch Pri
Mapping Register
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Table 6-77. Ethernet Switch Registers (continued)
HEX ADDRESS RANGE
REGISTER ACRONYM
DESCRIPTION
0x02D0 3068
CPDMA_TX_PRI_MAP
CPSW CPDMA Tx (Port 2 Rx) Pkt Priority to Header Priority
Mapping Register
0x02D0 306C
CPDMA_RX_CH_MAP
CPSW CPDMA Rx (Port 2 Tx) Switch Priority to DMA
channel Mapping Register
0x02D0 3070 - 0x02D0 307C
0x02D0 3080
reserved
GMAC0_IDVER
GMAC0_MACCONTROL
GMAC0_MACSTATUS
GMAC0_SOFT_RESET
GMAC0_RX_MAXLEN
GMAC0_BOFFTEST
reserved
GMAC0 Identification and Version Register
GMAC0 Mac Control Register
0x02D0 3084
0x02D0 3088
GMAC0 Mac Status Register
0x02D0 308C
GMAC0 Soft Reset Register
0x02D0 3090
GMAC0 RX Maximum Length Register
GMAC0 Backoff Test Register
0x02D0 3094
0x02D0 3098
0x02D0 309C
reserved
0x02D0 30A0
GMAC0_EMCONTROL
GMAC0_RX_PRI_MAP
reserved
GMAC0 Emulation Control Register
0x02D0 30A4
GMAC0 Rx Pkt Priority to Header Priority Mapping Register
0x02D0 30A8 - 0x02D0 30BC
0x02D0 30C0
GMAC1_IDVER
GMAC1_MACCONTROL
GMAC1_MACSTATUS
GMAC1_SOFT_RESET
GMAC1_RX_MAXLEN
GMAC1_BOFFTEST
reserved
GMAC1 Identification and Version Register
GMAC1 Mac Control Register
0x02D0 30C4
0x02D0 30C8
GMAC1 Mac Status Register
0x02D0 30CC
0x02D0 30D0
GMAC1 Soft Reset Register
GMAC1 RX Maximum Length Register
GMAC1 Backoff Test Register
0x02D0 30D4
0x02D0 30D8
0x02D0 30DC
0x02D0 30E0
reserved
GMAC1_EMCONTROL
GMAC1_RX_PRI_MAP
reserved
GMAC1 Emulation Control Register
0x02D0 30E4
GMAC1 Rx Pkt Priority to Header Priority Mapping Register
0x02D0 30E8 - 0x02D0 30FC
0x02D0 3100
TX_IDVER
CPDMA Tx Identification and Version Register
CPDMA Tx Control Register
0x02D0 3104
TX_CONTROL
0x02D0 3108
TX_TEARDOWN
reserved
CPDMA Tx Teardown Register
0x02D0 310C
0x02D0 3110
RX_IDVER
CPDMA Rx Identification and Version Register
CPDMA Rx Control Register
0x02D0 3114
RX_CONTROL
0x02D0 3118
RX_TEARDOWN
SOFT_RESET
CPDMA Rx Teardown Register
CPDMA Soft Reset Register
0x02D0 311C
0x02D0 3120
DMACONTROL
CPDMA Control Register
0x02D0 3124
DMASTATUS
CPDMA Status Register
0x02D0 3128
RX_BUFFER_OFFSET
EMCONTROL
CPDMA Rx Buffer Offset Register
CPDMA Emulation Control Register
0x02D0 312C
0x02D0 3130 - 0x02D0 317C
0x02D0 3180
reserved
TX_INTSTAT_RAW
TX_INTSTAT_MASKED
TX_INTMASK_SET
TX_INTMASK_CLEAR
CPDMA_IN_VECTOR
CPDMA_EOI_VECTOR
reserved
CPDMA Tx interrupt Status Register (raw value)
CPDMA Tx Interrupt Status Register (masked value)
CPDMA Tx Interrupt Mask Set Register
0x02D0 3184
0x02D0 3188
0x02D0 318C
CPDMA Tx Interrupt Mask Clear Register
CPDMA Input Vector Register (read only)
CPDMA End Of Interrupt Vector Register
0x02D0 3190
0x02D0 3194
0x02D0 3198 - 0x02D0 319C
0x02D0 31A0
RX_INTSTAT_RAW
CPDMA Rx Interrupt Status Register (raw value)
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Table 6-77. Ethernet Switch Registers (continued)
HEX ADDRESS RANGE
0x02D0 31A4
0x02D0 31A8
0x02D0 31AC
0x02D0 31B0
0x02D0 31B4
0x02D0 31B8
0x02D0 31BC
0x02D0 31C0
0x02D0 31C4
0x02D0 31C8
0x02D0 31CC
0x02D0 31D0
0x02D0 31D4
0x02D0 31D8
0x02D0 31DC
0x02D0 31E0
0x02D0 31E4
0x02D0 31E8
0x02D0 31EC
0x02D0 31F0
0x02D0 31F4
0x02D0 31F8
0x02D0 31FC
0x02D0 3200
0x02D0 3204
0x02D0 3208
0x02D0 320C
0x02D0 3210
0x02D0 3214
0x02D0 3218
0x02D0 321C
0x02D0 3220
0x02D0 3224
0x02D0 3228
0x02D0 322C
0x02D0 3230
0x02D0 3234
0x02D0 3238
0x02D0 323C
0x02D0 3240
0x02D0 3244
0x02D0 3248
0x02D0 324C
0x02D0 3250
0x02D0 3254
0x02D0 3258
0x02D0 325C
REGISTER ACRONYM
RX_INTSTAT_MASKED
RX_INTMASK_SET
RX_INTMASK_CLEAR
DMA_INTSTAT_RAW
DMA_INTSTAT_MASKED
DMA_INTMASK_SET
DMA_INTMASK_CLEAR
RX0_PENDTHRESH
RX1_PENDTHRESH
RX2_PENDTHRESH
RX3_PENDTHRESH
RX4_PENDTHRESH
RX5_PENDTHRESH
RX6_PENDTHRESH
RX7_PENDTHRESH
RX0_FREEBUFFER
RX1_FREEBUFFER
RX2_FREEBUFFER
RX3_FREEBUFFER
RX4_FREEBUFFER
RX5_FREEBUFFER
RX6_FREEBUFFER
RX7_FREEBUFFER
TX0_HDP
DESCRIPTION
CPDMA Rx Interrupt Status Register (masked value)
CPDMA Rx Interrupt Mask Set Register
CPDMA Rx Interrupt Mask Clear Register
CPDMA DMA Interrupt Status Register (raw value)
CPDMA DMA Interrupt Status Register (masked value)
CPDMA DMA Interrupt Mask Set Register
CPDMA DMA Interrupt Mask Clear Register
CPDMA Rx Threshold Pending Register Channel 0
CPDMA Rx Threshold Pending Register Channel 1
CPDMA Rx Threshold Pending Register Channel 2
CPDMA Rx Threshold Pending Register Channel 3
CPDMA Rx Threshold Pending Register Channel 4
CPDMA Rx Threshold Pending Register Channel 5
CPDMA Rx Threshold Pending Register Channel 6
CPDMA Rx Threshold Pending Register Channel 7
CPDMA Rx Free Buffer Register Channel 0
CPDMA Rx Free Buffer Register Channel 1
CPDMA Rx Free Buffer Register Channel 2
CPDMA Rx Free Buffer Register Channel 3
CPDMA Rx Free Buffer Register Channel 4
CPDMA Rx Free Buffer Register Channel 5
CPDMA Rx Free Buffer Register Channel 6
CPDMA Rx Free Buffer Register Channel 7
CPDMA Tx Channel 0 Head Desc Pointer
TX1_HDP
CPDMA Tx Channel 1 Head Desc Pointer
TX2_HDP
CPDMA Tx Channel 2 Head Desc Pointer
TX3_HDP
CPDMA Tx Channel 3 Head Desc Pointer
TX4_HDP
CPDMA Tx Channel 4 Head Desc Pointer
TX5_HDP
CPDMA Tx Channel 5 Head Desc Pointer
TX6_HDP
CPDMA Tx Channel 6 Head Desc Pointer
TX7_HDP
CPDMA Tx Channel 7 Head Desc Pointer
RX0_HDP
CPDMA Rx 0 Channel 0 Head Desc Pointer
CPDMA Rx 1 Channel 1 Head Desc Pointer
CPDMA Rx 2 Channel 2 Head Desc Pointer
CPDMA Rx 3 Channel 3 Head Desc Pointer
CPDMA Rx 4 Channel 4 Head Desc Pointer
CPDMA Rx 5 Channel 5 Head Desc Pointer
CPDMA Rx 6 Channel 6 Head Desc Pointer
CPDMA Rx 7 Channel 7 Head Desc Pointer
CPDMA Tx Channel 0 Completion Pointer Register
CPDMA Tx Channel 1 Completion Pointer Register
CPDMA Tx Channel 2 Completion Pointer Register
CPDMA Tx Channel 3 Completion Pointer Register
CPDMA Tx Channel 4 Completion Pointer Register
CPDMA Tx Channel 5 Completion Pointer Register
CPDMA Tx Channel 6 Completion Pointer Register
CPDMA Tx Channel 7 Completion Pointer Register
RX1_HDP
RX2_HDP
RX3_HDP
RX4_HDP
RX5_HDP
RX6_HDP
RX7_HDP
TX0_CP
TX1_CP
TX2_CP
TX3_CP
TX4_CP
TX5_CP
TX6_CP
TX7_CP
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Table 6-77. Ethernet Switch Registers (continued)
HEX ADDRESS RANGE
REGISTER ACRONYM
RX0_CP
DESCRIPTION
0x02D0 3260
0x02D0 3264
CPDMA Rx Channel 0 Completion Pointer Register
CPDMA Rx Channel 1 Completion Pointer Register
CPDMA Rx Channel 2 Completion Pointer Register
CPDMA Rx Channel 3 Completion Pointer Register
CPDMA Rx Channel 4 Completion Pointer Register
CPDMA Rx Channel 5 Completion Pointer Register
CPDMA Rx Channel 6 Completion Pointer Register
CPDMA Rx Channel 7 Completion Pointer Register
RX1_CP
0x02D0 3268
RX2_CP
0x02D0 326C
RX3_CP
0x02D0 3270
RX4_CP
0x02D0 3274
RX5_CP
0x02D0 3278
RX6_CP
0x02D0 327C
RX7_CP
0x02D0 3280 - 0x02D0 32BF
0x02D0 32C0 - 0x02D0 32FC
0x02D0 3300 - 0x02D0 337C
0x02D0 3380 - 0x02D0 33FC
0x02D0 3400
reserved
reserved
reserved
reserved
RXGOODFRAMES
RXBROADCASTFRAMES
CPSW_STATS Total number of good frames received
0x02D0 3404
CPSW_STATS Total number of good broadcast frames
received
0x02D0 3408
RXMULTICASTFRAMES
CPSW_STATS Total number of good multicast frames
received
0x02D0 340C
0x02D0 3410
0x02D0 3414
RXPAUSEFRAMES
RXCRCERRORS
CPSW_STATS PauseRxFrames
CPSW_STATS Total number of CRC errors frames received
RXALIGNCODEERRORS
CPSW_STATS Total number of alignment/code errors
received
0x02D0 3418
0x02D0 341C
0x02D0 3420
0x02D0 3424
0x02D0 3428
0x02D0 342C
0x02D0 3430
RXOVERSIZEDFRAMES
RXJABBERFRAMES
RXUNDERSIZEDFRAMES
RXFRAGMENTS
reserved
CPSW_STATS Total number of oversized frames received
CPSW_STATS Total number of jabber frames received
CPSW_STATS Total number of undersized frames received
CPSW_STATS RxFragments received
reserved
RXOCTETS
CPSW_STATS Total number of received bytes in good
frames
0x02D0 3434
0x02D0 3438
0x02D0 343C
0x02D0 3440
0x02D0 3444
0x02D0 3448
0x02D0 344C
0x02D0 3450
0x02D0 3454
0x02D0 3458
0x02D0 345C
0x02D0 3460
0x02D0 3464
0x02D0 3468
0x02D0 346C
0x02D0 3470
0x02D0 3474
0x02D0 3478
0x02D0 347C
TXGOODFRAMES
TXBROADCASTFRAMES
TXMULTICASTFRAMES
TXPAUSEFRAMES
CPSW_STATS GoodTxFrames
CPSW_STATS BroadcastTxFrames
CPSW_STATS MulticastTxFrames
CPSW_STATS PauseTxFrames
CPSW_STATS Deferred Frames
CPSW_STATS Collisions
TXDEFERREDFRAMES
TXCOLLISIONFRAMES
TXSINGLECOLLFRAMES
TXMULTCOLLFRAMES
TXEXCESSIVECOLLISIONS
TXLATECOLLISIONS
TXUNDERRUN
CPSW_STATS SingleCollisionTxFrames
CPSW_STATS MultipleCollisionTxFrames
CPSW_STATS ExcessiveCollisions
CPSW_STATS LateCollisions
CPSW_STATS Transmit Underrun Error
CPSW_STATS CarrierSenseErrors
CPSW_STATS TxOctets
TXCARRIERSENSEERRORS
TXOCTETS
OCTETFRAMES64
CPSW_STATS 64octetFrames
OCTETFRAMES65T127
OCTETFRAMES128T255
OCTETFRAMES256T511
OCTETFRAMES512T1023
OCTETFRAMES1024TUP
CPSW_STATS 65-127octetFrames
CPSW_STATS 128-255octetFrames
CPSW_STATS 256-511octetFrames
CPSW_STATS 512-1023octetFrames
CPSW_STATS 1023-1518octetFrames
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Table 6-77. Ethernet Switch Registers (continued)
HEX ADDRESS RANGE
0x02D0 3480
REGISTER ACRONYM
NETOCTETS
DESCRIPTION
CPSW_STATS NetOctets
0x02D0 3484
RXSOFOVERRUNS
CPSW_STATS Receive FIFO or DMA Start of Frame
Overruns
0x02D0 3488
0x02D0 348C
RXMOFOVERRUNS
RXDMAOVERRUNS
CPSW_STATS Receive FIFO or DMA Mid of Frame
Overruns
CPSW_STATS Receive DMA Start of Frame and Middle of
Frame Overruns
0x02D0 3490 - 0x02D0 34FC
0x02D0 3500
reserved
ALE_IDVER
reserved
ALE Identification and Version Register
ALE Control Register
0x02D0 3504
0x02D0 3508
ALE_CONTROL
reserved
0x02D0 350C
0x02D0 3510
ALE_PRESCALE
reserved
ALE Prescale Register
0x02D0 3514
0x02D0 3518
ALE_UNKNOWN_VLAN
reserved
ALE Unknown VLAN Register
ALE Table Control Register
0x02D0 351C
0x02D0 3520
ALE_TBLCTL
reserved
0x02D0 3524 - 0x02D0 3530
0x02D0 3534
ALE_TBLW2
ALE_TBLW1
ALE_TBLW0
ALE_PORTCTL0
ALE_PORTCTL1
ALE_PORTCTL2
reserved
ALE Table Word 2 Register
ALE Table Word 1 Register
ALE Table Word 0 Register
ALE Port 0 Control Register
ALE Port 1 Control Register
ALE Port 2 Control Register
0x02D0 3538
0x02D0 353C
0x02D0 3540
0x02D0 3544
0x02D0 3548
0x02D0 354C - 0x02D0 37FF
Table 6-78. Ethernet Subsystem Registers
HEX ADDRESS RANGE
0x02D0 2000
0x02D0 2004
0x02D0 2008
0x02D0 200C
0x02D0 2010
0x02D0 2014
0x02D0 2018
0x02D0 201C
0x02D0 2020
0x02D0 2024
0x02D0 2028
0x02D0 202C
0x02D0 2030
0x02D0 2034
REGISTER ACRONYM
IDVER
DESCRIPTION
Identification and Version Register
Soft Reset Register
SOFT_RESET
EM_CONTROL
INT_CONTROL
RX_THRESH_EN
RX_EN
Emulation Control Register
Interrupt Control Register
Receive Threshold Interrupt Enable Register
Receive Interrupt Enable Register
Transmit Interrupt Enable Register
Misc Interrupt Enable Register
TX_EN
MISC_EN
RX_THRESH_STAT
RX_STAT
Receive Threshold Masked Interrupt Status Register
Receive Interrupt Masked Interrupt Status Register
Transmit Interrupt Masked Interrupt Status Register
Misc Interrupt Masked Interrupt Status Register
Receive Interrupts Per Millisecond
Transmit Interrupts Per Millisecond
TX_STAT
MISC_STAT
RX_IMAX
TX_IMAX
Table 6-79. SGMII0 Registers
HEX ADDRESS RANGE
0x02D0 4800
REGISTER NAME
IDVER
DESCRIPTION
Identification and Version Register
Soft Reset Register
0x02D0 4804
SOFT_RESET
162
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Table 6-79. SGMII0 Registers (continued)
HEX ADDRESS RANGE
REGISTER NAME
Reserved
DESCRIPTION
0x02D0 4808 - 0x02D0 480C
0x02D0 4810
Reserved
CONTROL
Control Register
0x02D0 4814
STATUS
Status Register (read only)
Advertised Ability Register
Transmit Next Page Register
Link Partner Advertised Ability (read only)
Link Partner Receive Next Page Register (read only)
Reserved
0x02D0 4818
MR_ADV_ABILITY
MR_NP_TX
MR_LP_ADV_ABILITY
MR_NP_RX
Reserved
0x02D0 481C
0x02D0 4820
0x02D0 4824
0x02D0 4828 - 0x02D0 482C
0x02D0 4830
Reserved
Reserved
0x02D0 4834
Reserved
Reserved
0x02D0 4838
Reserved
Reserved
0x02D0 483C
Reserved
Reserved
0x02D0 4840
DIAG_CLEAR
DIAG_CONTROL
DIAG_STATUS
Reserved
Diagnostics Clear Register
Diagnostics Control Register
Diagnostics Status Register (read only)
Reserved
0x02D0 4844
0x02D0 4848
0x02D0 484C - 0x02D0 487F
Table 6-80. SGMII1 Registers
HEX ADDRESS RANGE
0x02D0 4C00
REGISTER NAME
IDVER
DESCRIPTION
Identification and Version Register
Soft Reset Register
0x02D0 4C04
SOFT_RESET
Reserved
0x02D0 4C08 - 0x02D0 4C0C
0x02D0 4C10
Reserved
CONTROL
Control Register
0x02D0 4C14
STATUS
Status Register (read only)
Advertised Ability Register
Transmit Next Page Register
Link Partner Advertised Ability (read only)
Link Partner Receive Next Page Register (read only)
Reserved
0x02D0 4C18
MR_ADV_ABILITY
MR_NP_TX
MR_LP_ADV_ABILITY
MR_NP_RX
Reserved
0x02D0 4C1C
0x02D0 4C20
0x02D0 4C24
0x02D0 4C28 - 0x02D0 4C2C
0x02D0 4C30
Reserved
Reserved
0x02D0 4C34
Reserved
Reserved
0x02D0 4C38
Reserved
Reserved
0x02D0 4C3C
Reserved
Reserved
0x02D0 4C40
DIAG_CLEAR
DIAG_CONTROL
DIAG_STATUS
Reserved
Diagnostics Clear Register
Diagnostics Control Register
Diagnostics Status Register (read only)
Reserved
0x02D0 4C44
0x02D0 4C48
0x02D0 4C4C - 0x02D0 4C7F
6.19.4 Ethernet Subsystem Timing
Table 6-81. Ethernet Subsystem Timing Requirements
PARAMETER(1)
MIN
NOM
MAX
UNITS
t01
REFCLKP/N period, mode
x 10 mode
x 20 mode
x 25 mode
8
ns
ns
ns
16
20
(1) C = REFCLKP/N period in ms.
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Table 6-81. Ethernet Subsystem Timing Requirements (continued)
PARAMETER(1)
MIN
NOM
MAX
UNITS
%
t02
t03
t04
t05
REFCLKP/N duty cycle
REFCLKP/N rise/fall
PLL Clock Period, x n Mode
PLL power up
40
60
700
ps
t01 / n
ns
1 + 200 * C
ms
REFCLKP/N Jitter and PLL Loop Bandwidth
Jitter on the reference clock will degrade both the transmit eye and receiver jitter tolerance thereby
impairing system performance. A good quality, low jitter reference clock is necessary to achieve
compliance with most if not all physical layer standards (see Table 6-82).
Table 6-82. REFCLKP/N Jitter Requirements for Standards Compliance
Standard
Gigabit Ethernet
Line Rate (Gbps)
Total REFCLKP/N Jitter (within PLL bandwidth)
1.25
50 ps pk-pk
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6.20 Management Data Input/Output (MDIO)
The management data input/output (MDIO) module continuously polls all 32 MDIO addresses to
enumerate all PHY devices in the system. It contains two user access registers to control and monitor up
to two PHYs simultaneously.
The MDIO module implements the 802.3 serial management interface to interrogate and control two
Ethernet PHYs simultaneously using a shared two-wire bus.
6.20.1 MII Management Interface
Host software uses the MDIO module to configure the auto-negotiation parameters of each PHY attached
to the Ethernet Switch Subsystem, retrieve the negotiation results, and configure required parameters in
the Ethernet Switch Subsystem module for correct operation. The module is designed to allow almost
transparent operation of the MDIO interface, with very little maintenance from the core processor. Only a
maximum of two PHYs may be connected at any given time.
For more detailed information on the Ethernet Switch Subsystem, see the TMS320DM647/DM648 DSP
Ethernet Subsystem User's Guide Reference Guide (literature number SPRUF57). For a list of supported
registers and register fields, see Table 6-83.
6.20.2 MDIO Register Descriptions
Table 6-83. MDIO Registers
HEX ADDRESS RANGE
0x02D0 4000
REGISTER ACRONYM
MDIOVER
DESCRIPTION
Module version register
Module control register
PHY acknowledge status register
PHY link status register
0x02D0 4004
MDIOCONTROL
MDIOALIVE
0x02D0 4008
0x02D0 400C
MDIOLINK
0x02D0 4010
MDIOLINKINTRAW
Link status change interrupt register (raw
value)
0x02D0 4014
MDIOLINKINTMASKED
Link status change interrupt register (masked
value)
0x02D0 4018 - 0x02D0 401C
0x02D0 4020
reserved
MDIOUSERINTRAW
User command complete interrupt register
(raw value)
0x02D0 4024
MDIOUSERINTMASKED
User command complete interrupt register
(masked value)
0x02D0 4028
0x02D0 402C
MDIOUSERINTMASKSET
MDIOUSERINTMASKCLR
reserved
User interrupt mask set register
User interrupt mask clear register
0x02D0 4030 - 0x02D0 407C
0x02D0 4080
MDIOUSERACCESS0
MDIOUSERPHYSEL0
MDIOUSERACCESS1
MDIOUSERPHYSEL1
reserved
User access register0
User PHY select register0
User access register1
User PHY select register1
0x02D0 4084
0x02D0 4088
0x02D0 408C
0x02D0 4090 - 0x02D0 40FF
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6.21 Timers
The device has four 64-bit general-purpose timers of which only Timer 0 and Timer 1 have external
input/output. The timers can be used to: time events, count events, generate pulses, interrupt the CPU,
and send synchronization events to the EDMA3 channel controller.
6.21.1 General-Purpose Timers
Each timer can be programmed as a 64-bit timer or as two separate 32-bit timers. Each timer is made up
of two 32-bit counters: a high counter and a low counter. The timer pins, TINPLx and TOUTLx are
connected to the low counter. The high counter does not have any external device pins.
For more detailed information, see the TMS320DM647DM648 DSP 64-Bit Timer User's Guide (literature
number SPRUEL0).
6.21.2 Timer Peripheral Register Descriptions
Table 6-84. Timer 0 Registers
HEX ADDRESS RANGE
0x0204 4400
ACRONYM
DESCRIPTION
Peripheral Identification Register
PID12
0x0204 4404
EMUMGT_CLKSPD
Timer 0 Emulation Management/Clock Speed Register
Timer 0 Counter Register 12
Timer 0 Counter Register 34
Timer 0 Period Register 12
Timer 0 Period Register 34
Timer 0 Control Register
0x0204 4410
TIM12
TIM34
PRD12
PRD34
TCR
0x0204 4414
0x0204 4418
0x0204 441C
0x0204 4420
0x0204 4424
TGCR
-
Timer 0 Global Control Register
Reserved
0x0x0204 4428 - 0x0204 44FF
Table 6-85. Timer 1 Registers
HEX ADDRESS RANGE
0x0204 4800
ACRONYM
DESCRIPTION
PID12
Peripheral Identification Register
0x0204 4804
EMUMGT_CLKSPD
Timer 1 Emulation Management/Clock Speed Register
Timer 1 Counter Register 12
Timer 1 Counter Register 34
Timer 1 Period Register 12
Timer 1 Period Register 34
Timer 1 Control Register
0x0204 4810
TIM12
TIM34
PRD12
PRD34
TCR
0x0204 4814
0x0204 4818
0x0204 481C
0x0204 4820
0x0204 4824
TGCR
-
Timer 1 Global Control Register
Reserved
0x0204 4828 - 0x0204 48FF
Table 6-86. Timer 2 Registers
HEX ADDRESS RANGE
0x0204 4C00
0x0204 4C04
0x0204 4C10
0x0204 4C14
0x0204 4C18
0x0204 4C1C
0x0204 4C20
0x0204 4C24
ACRONYM
DESCRIPTION
PID12
EMUMGT_CLKSPD
TIM12
Peripheral Identification Register
Timer 2 Emulation Management/Clock Speed Register
Timer 2 Counter Register 12
TIM34
Timer 2 Counter Register 34
PRD12
Timer 2 Period Register 12
PRD34
Timer 2 Period Register 34
TCR
Timer 2 Control Register
TGCR
Timer 2 Global Control Register
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Table 6-86. Timer 2 Registers (continued)
HEX ADDRESS RANGE
ACRONYM
DESCRIPTION
0x0204 4C28 - 0x0204 4CFF
-
Reserved
Table 6-87. Timer 3 Registers
HEX ADDRESS RANGE
0x0204 5000
ACRONYM
DESCRIPTION
PID12
Peripheral Identification Register
0x0204 5004
EMUMGT_CLKSPD
Timer 3 Emulation Management/Clock Speed Register
Timer 3 Counter Register 12
Timer 3 Counter Register 34
Timer 3 Period Register 12
Timer 3 Period Register 34
Timer 3 Control Register
0x0204 5010
TIM12
TIM34
PRD12
PRD34
TCR
0x0204 5014
0x0204 5018
0x0204 501C
0x0204 5020
0x0204 5024
TGCR
-
Timer 3 Global Control Register
Reserved
0x0204 5028 - 0x0204 50FF
6.21.3 Timer Electrical Data/Timing
Table 6-88. Timing Requirements for Timer Input(1) (see Figure 6-52)
720, 800, 900,
1100
NO.
UNIT
MIN
MAX
1
2
tw(TIMIxH)
tw(TIMIxL)
Pulse duration, TIMIxH high
Pulse duration, TIMIxL low
12P(1)
ns
ns
12P
(1) P = 1/CPU clock frequency in ns.
Table 6-89. Switching Characteristics for Timer Output
over operating free-air temperature range (unless otherwise noted)
720, 800, 900, 1100
NO.
PARAMETER
UNIT
MIN
12P(1)
12P
TYP
MAX
3
4
tw(TIMOxH)
tw(TIMOxL)
Pulse duration, TIMOxH high
Pulse duration, TIMOxL low
(1) P = 1/CPU clock frequency in ns.
2
1
TINPLx
4
3
TOUTLx
Figure 6-52. Timer Timing
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6.22 VLYNQ Peripheral
6.22.1 VLYNQ Device-Specific Information
The VLYNQ peripheral conforms to the VLYNQ Module Specification (revision 2.x). By default, the VLYNQ
peripheral is initialized with a device ID of 0x22.
6.22.2 VLYNQ Peripheral Register Descriptions
Table 6-90. VLYNQ Registers
HEX ADDRESS RANGE
0x3800 0000
0x3800 0004
0x3800 0008
0x3800 000C
0x3800 0010
0x3800 0014
0x3800 0018
0x3800 001C
0x3800 0020
0x3800 0024
0x3800 0028
0x3800 002C
0x3800 0030
0x3800 0034
0x3800 0038
0x3800 003C
0x3800 0040
0x3800 0044
0x3800 0048
0x3800 004C
0x3800 0050 - 0x3800 005C
0x3800 0060
0x3800 0064
0x3800 0068 - 0x3800 007C
0x3800 0080
0x3800 0084
0x3800 0088
0x3800 008C
0x3800 0090
0x3800 0094
0x3800 0098
0x3800 009C
0x3800 00A0
0x3800 00A4
0x3800 00A8
0x3800 00AC
0x3800 00B0
0x3800 00B4
0x3800 00B8
ACRONYM
-
REGISTER NAME
Reserved
CTRL
VLYNQ Local Control Register
VLYNQ Local Status Register
STAT
INTPRI
INTSTATCLR
INTPENDSET
INTPTR
XAM
VLYNQ Local Interrupt Priority Vector Status/Clear Register
VLYNQ Local Interrupt Status/Clear Register
VLYNQ Local Interrupt Pending/Set Register
VLYNQ Local Interrupt Pointer Register
VLYNQ Local Transmit Address Map
RAMS1
RAMO1
RAMS2
RAMO2
RAMS3
RAMO3
RAMS4
RAMO4
CHIPVER
AUTNGO
MANNGO
NGOSTAT
-
VLYNQ Local Receive Address Map Size 1
VLYNQ Local Receive Address Map Offset 1
VLYNQ Local Receive Address Map Size 2
VLYNQ Local Receive Address Map Offset 2
VLYNQ Local Receive Address Map Size 3
VLYNQ Local Receive Address Map Offset 3
VLYNQ Local Receive Address Map Size 4
VLYNQ Local Receive Address Map Offset 4
VLYNQ Local Chip Version Register
VLYNQ Local Auto Negotiation Register
VLYNQ Local Manual Negotiation Register
VLYNQ Local Negotiation Status Register
Reserved
INTVEC0
INTVEC1
-
VLYNQ Local Interrupt Vector 3 - 0
VLYNQ Local Interrupt Vector 7 - 4
Reserved for future use [Local Interrupt Vectors 8 - 31]
VLYNQ Remote Revision Register
RREVID
RCTRL
RSTAT
RINTPRI
VLYNQ Remote Control Register
VLYNQ Remote Status Register
VLYNQ Remote Interrupt Priority Vector Status/Clear Register
RINTSTATCLR VLYNQ Remote Interrupt Status/Clear Register
RINTPENDSET VLYNQ Remote Interrupt Pending/Set Register
RINTPTR
RXAM
VLYNQ Remote Interrupt Pointer Register
VLYNQ Remote Transmit Address Map
RRAMS1
RRAMO1
RRAMS2
RRAMO2
RRAMS3
RRAMO3
RRAMS4
VLYNQ Remote Receive Address Map Size 1
VLYNQ Remote Receive Address Map Offset 1
VLYNQ Remote Receive Address Map Size 2
VLYNQ Remote Receive Address Map Offset 2
VLYNQ Remote Receive Address Map Size 3
VLYNQ Remote Receive Address Map Offset 3
VLYNQ Remote Receive Address Map Size 4
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Table 6-90. VLYNQ Registers (continued)
HEX ADDRESS RANGE
ACRONYM
RRAMO4
RCHIPVER
RAUTNGO
RMANNGO
RNGOSTAT
-
REGISTER NAME
VLYNQ Remote Receive Address Map Offset 4
VLYNQ Remote Chip Version Register
VLYNQ Remote Auto Negotiation Register
VLYNQ Remote Manual Negotiation Register
VLYNQ Remote Negotiation Status Register
Reserved
0x3800 00BC
0x3800 00C0
0x3800 00C4
0x3800 00C8
0x3800 00CC
0x3800 00D0 - 0x3800 00DC
0x3800 00E0
RINTVEC0
RINTVEC1
-
VLYNQ Remote Interrupt Vector 3 - 0
VYLNQ Remote Interrupt Vector 7 - 4
Reserved for future use [Remote Interrupt Vectors 8 - 31]
0x3800 00E4
0x3800 00E8 - 0x3800 00FC
6.22.3 VLYNQ Electrical Data/Timing
Table 6-91. Timing Requirements for VCLK for VLYNQ (see Figure 6-53)
720, 800, 900, 1100
NO.
1
UNIT
MIN
MAX
tc(VCLK)
Cycle time, VCLK
8
ns
ns
ns
ns
ns
ns
Pulse duration, VCLK high, VCLK Input
Pulse duration, VCLK high, VCLK Output
Pulse duration, VCLK low, VCLK Input
Pulse duration, VCLK low, VCLK Output
Transition time, VCLK
2
3
2
3
2
tw(VCLKH)
3
4
tw(VCLKL)
tt(VCLK)
1
4
2
VCLK
4
3
Figure 6-53. VCLK Timing for VLYNQ
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Table 6-92. Switching Characteristics
Over Recommended Operating Conditions for Transmit Data for the VLYNQ Module (see Figure 6-54)
720, 800, 900, 1100
NO.
PARAMETER
UNIT
MIN
2.25
0.86
MAX
1
1
2
td(VCLKH-TXDI)
td(VCLKH-TXDI)
td(VCLKH-TXDV)
Delay time, VCLK high to VTXD[3:0] invalid [SLOW Mode]
Delay time, VCLK high to VTXD[3:0] invalid [FAST Mode]
Delay time, VCLK to VTXD[3:0] valid
ns
ns
6.85
ns
Table 6-93. Timing Requirements for Receive Data for the VLYNQ Module (see Figure 6-54)
720, 800, 900, 1100
NO.
UNIT
MIN
0.2
MAX
RTM disabled
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
RTM enabled, RXD Flop = 0
RTM enabled, RXD Flop = 1
RTM enabled, RXD Flop = 2
RTM enabled, RXD Flop = 3
RTM enabled, RXD Flop = 4
RTM enabled, RXD Flop = 5
RTM enabled, RXD Flop = 6
RTM enabled, RXD Flop = 7
RTM disabled
1.25
0.91
0.64
0.36
0.09
-0.18
-0.44
-0.69
2
Setup time, VRXD[3:0] valid before VCLK
high
3
tsu(RXDV-VCLKH)
RTM enabled, RXD Flop = 0
RTM enabled, RXD Flop = 1
RTM enabled, RXD Flop = 2
0.95
1.33
1.72
2.15
2.58
3.03
3.46
3.89
4
th(VCLKH-RXDV)
Hold time, VRXD[3:0] valid after VCLK high RTM enabled, RXD Flop = 3
RTM enabled, RXD Flop = 4
RTM enabled, RXD Flop = 5
RTM enabled, RXD Flop = 6
RTM enabled, RXD Flop = 7
1
VCLK
2
VTXD[3:0]
VRXD[3:0]
Data
4
3
Data
Figure 6-54. VLYNQ Transmit/Receive Timing
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6.23 General-Purpose Input/Output (GPIO)
The GPIO peripheral provides general-purpose pins that can be configured as either inputs or outputs.
When configured as an output, a write to an internal register can control the state driven on the output pin.
When configured as an input, the state of the input is detectable by reading the state of an internal
register. In addition, the GPIO peripheral can produce CPU interrupts and EDMA events in different
interrupt/event generation modes. The GPIO peripheral provides generic connections to external devices.
The GPIO pins are grouped into banks of 16 pins per bank (i.e., bank 0 consists of GPIO [0:15]).
The GPIO peripheral supports the following:
•
•
Up to 3.3-V GPIO pins
Interrupts:
–
–
–
Up to 16 unique GPIO[0:15] interrupts from Bank 0
One GPIO bank (aggregated) interrupt signal from the GPIOs in Bank 1
Interrupts can be triggered by rising and/or falling edge, specified for each interrupt capable GPIO
signal
•
•
DMA events:
–
Up to 10 unique GPIO DMA events from Bank 0
Set/clear functionality: Firmware writes 1 to corresponding bit position(s) to set or to clear GPIO
signal(s). This allows multiple firmware processes to toggle GPIO output signals without critical section
protection (disable interrupts, program GPIO, re-enable interrupts, to prevent context switching to
anther process during GPIO programming).
•
•
Separate Input/Output registers
Output register in addition to set/clear so that, if preferred by firmware, some GPIO output signals can
be toggled by direct write to the output register(s).
•
Output register, when read, reflects output drive status. This, in addition to the input register reflecting
pin status and open-drain I/O cell, allows wired logic be implemented.
The memory map for the GPIO registers is shown in Table 6-94.
For more detailed information on GPIOs, see the TMS320DM647/DM648 DSP General-Purpose
Input/Output (GPIO) User's Guide (literature number SPRUEK7).
6.23.1 GPIO Peripheral Register Descriptions
Table 6-94. GPIO Registers
HEX ADDRESS RANGE
0x0204 8000
ACRONYM
REGISTER NAME
Peripheral Identification Register
PID
-
0x0204 8004
Reserved
0x0204 8008
BINTEN
GPIO interrupt per-bank enable
GPIO Banks 0 and 1
0x0204 800C
0x0204 8010
0x0204 8014
0x0204 8018
0x0204 801C
0x0204 8020
0x0204 8024
0x0204 8028
0x0204 802C
0x0204 8030
0x0204 8034
-
Reserved
DIR
GPIO Banks 0 and 1 Direction Register (GPIO[0:31])
GPIO Banks 0 and 1 Output Data Register (GPIO[0:31])
GPIO Banks 0 and 1 Set Data Register (GPIO[0:31])
GPIO Banks 0 and 1 Clear data for banks 0 and 1 (GPIO[0:31])
GPIO Banks 0 and 1 Input Data Register (GPIO[0:31])
GPIO Banks 0 and 1 Set Rising Edge Interrupt Register (GPIO[0:31])
GPIO Banks 0 and 1 Clear Rising Edge Interrupt Register (GPIO[0:31])
GPIO Banks 0 and 1 Set Falling Edge Interrupt Register (GPIO[0:31])
GPIO Banks 0 and 1 Clear Falling Edge Interrupt Register (GPIO[0:31])
GPIO Banks 0 and 1 Interrupt Status Register (GPIO[0:31])
OUT_DATA
SET_DATA
CLR_DATA
IN_DATA
SET_RIS_TRIG
CLR_RIS_TRIG
SET_FAL_TRIG
CLR_FAL_TRIG
INSTAT
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6.23.2 GPIO Peripheral Input/Output Electrical Data/Timing
Table 6-95. Timing Requirements for GPIO Inputs(1) (see Figure 6-55)
720, 800, 900,
1100
NO.
UNIT
MIN
MAX
1
2
tw(GPIH)
tw(GPIL)
Pulse duration, GPIx high
Pulse duration, GPIx low
12P
12P
ns
ns
(1) The pulse width given is sufficient to generate a CPU interrupt or an EDMA event. However, if a user wants to have the device
recognize the GPIx changes through software polling of the GPIO register, the GPIx duration must be extended to allow the device
enough time to access the GPIO register through the internal bus. P = 1/CPU clock frequency in ns.
Table 6-96. Switching Characteristics Over Recommended Operating Conditions for GPIO Outputs
(see Figure 6-55)
720, 800, 900, 1100
NO.
PARAMETER
UNIT
MIN
6P(1)
6P(1)
MAX
3
4
tw(GPOH)
tw(GPOL)
Pulse duration, GPOx high
Pulse duration, GPOx low
ns
ns
(1) This parameter value should not be used as a maximum performance specification. Actual performance of back-to-back accesses of the
GPIO is dependent upon internal bus activity. P = 1/CPU clock frequency in ns.
2
1
GPIx
4
3
GPOx
Figure 6-55. GPIO Port Timing
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6.24 Emulation Features and Capability
6.24.1 Advanced Event Triggering (AET)
The device supports Advanced Event Triggering (AET). This capability can be used to debug complex
problems as well as understand performance characteristics of user applications. AET provides the
following capabilities:
•
Hardware Program Breakpoints: specify addresses or address ranges that can generate events such
as halting the processor or triggering the trace capture.
•
Data Watchpoints: specify data variable addresses, address ranges, or data values that can generate
events such as halting the processor or triggering the trace capture.
•
•
Counters: count the occurrence of an event or cycles for performance monitoring.
State Sequencing: allows combinations of hardware program breakpoints and data watchpoints to
precisely generate events for complex sequences.
For more information on AET, see the following documents:
•
Using Advanced Event Triggering to Find and Fix Intermittent Real-Time Bugs Application Report
(literature number SPRA753)
•
Using Advanced Event Triggering to Debug Real-Time Problems in High Speed Embedded
Microprocessor Systems Application Report (literature number SPRA387)
6.24.2 Trace
The device supports Trace. Trace is a debug technology that provides a detailed, historical account of
application code execution, timing, and data accesses. Trace collects, compresses, and exports debug
information for analysis. Trace works in real-time and does not impact the execution of the system.
For more information on board design guidelines for Trace Advanced Emulation, see the Emulation and
Trace Headers Technical Reference Manual (literature number SPRU655).
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6.25 IEEE 1149.1 JTAG
The JTAG(2) interface is used for BSDL testing and emulation of the device.
TRST needs to be released only when it is necessary to use a JTAG controller to debug the device or
exercise the device's boundary scan functionality. Note: TRST is synchronous and must be clocked by
TCK; otherwise, the boundary scan logic may not respond as expected after TRST is asserted.
For maximum reliability, the device includes an internal pulldown (IPD) on the TRST pin to make certain
that TRST will always be asserted upon power up and the device's internal emulation logic will always be
properly initialized.
JTAG controllers from Texas Instruments actively drive TRST high. However, some third-party JTAG
controllers may not drive TRST high but expect the use of a pullup resistor on TRST.
When using this type of JTAG controller, assert TRST to initialize the device after powerup and externally
drive TRST high before attempting any emulation or boundary scan operations.
6.25.1 JTAG Peripheral Register Description(s) - JTAG ID Register
Table 6-97. JTAG ID Register
HEX ADDRESS RANGE
ACRONYM
REGISTER NAME
JTAG Identification Register
COMMENTS
Read-only. Provides 32-bit
JTAG ID of the device.
0x0204 9018
JTAGID
(2) IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
The JTAG ID register is a read-only register that identifies to the customer the JTAG/Device ID. The JTAG
ID register resides at address location 0x0204 9018. The register hex value is: 0x0B77 A02F . For the
actual register bit names and their associated bit field descriptions, see Figure 6-56 and Table 6-98.
Figure 6-56. JTAGID Register (0x0204 9018)
31-28
VERSION
R-0001
27-12
11-1
0
PART NUMBER (16-Bit)
R-1011 0111 0111 1010
MANUFACTURER (11-Bit)
R-0000 0010 111
LSB
R-1
LEGEND: R = Read, W = Write, n = value at reset
Table 6-98. JTAGID Register Selection Bit Descriptions
BIT
31:28
27:12
11-1
0
NAME
DESCRIPTION
VERSION
Silicon version value: 0001.
Part Number (16-Bit) value: 1011 0111 0111 1010.
PART NUMBER
MANUFACTURER Manufacturer (11-Bit) value: 0000 0010 111.
LSB LSB. This bit is read as a 1.
6.25.2 JTAG Electrical Data/Timing
Table 6-99. Timing Requirements for JTAG Test Port (see Figure 6-57)
720, 800, 900, 1100
NO.
UNIT
MIN
35
2
MAX
1
3
4
tc(TCK)
Cycle time, TCK
ns
ns
ns
tsu(TDIV-TCKH)
th(TCKH-TDIV)
Setup time, TDI/TMS/TRST valid before TCK high
Hold time, TDI/TMS/TRST valid after TCK high
0
174
Peripheral Information and Electrical Specifications
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TMS320DM647
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SPRS372F–JANUARY 2010–REVISED SEPTEMBER 2009
Table 6-100. Switching Characteristics Over Recommended Operating Conditions for JTAG Test Port
(see Figure 6-57)
720, 800, 900, 1100
NO.
PARAMETER
UNIT
MIN
MAX
2
td(TCKL-TDOV)
Delay time, TCK low to TDO valid
0
0.25 × tc(TCK)
ns
1
TCK
TDO
2
2
4
3
TDI/TMS/TRST
Figure 6-57. JTAG Test-Port Timing
Copyright © 2010–2009, Texas Instruments Incorporated
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TMS320DM647
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7 Mechanical Data
The following table(s) show the thermal resistance characteristics for the ZUT mechanical package.
7.1 Thermal Data for ZUT
Table 7-1. Thermal Resistance Characteristics (PBGA Package) [ZUT]
°C/W(1)
1.7
AIR FLOW (m/s)(2)
RΘJC
RΘJB
RΘJA
RΘJC Junction-to-case
RΘJB Junction-to-board
RΘJA Junction-to-free air
N/A
N/A
0.0
1.0
2.0
3.0
0.0
1.0
2.0
3.0
0.0
1.0
2.0
3.0
8.6
17.2
13.7
12.4
11.5
0.6
yJT
yJT Junction-to-package top
yJB Junction-to-board
0.6
0.6
0.7
yiJB
8.4
7.4
7.0
6.7
(1) The junction-to-case measurement was conducted in a JEDEC defined 1S0P system. Other measurements were conducted in a JEDEC
defined 1S2P system and will change based on environment as well as application.
For more information, see these three EIA/JEDEC standards:
•
•
•
EIA/JESD51-2, Integrated Circuits Thermal Test Method Environment Conditions - Natural Convection (Still Air)
EIA/JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements
(2) m/s = meters per second
176
Mechanical Data
Copyright © 2010–2009, Texas Instruments Incorporated
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TMS320DM647
TMS320DM648
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7.2 Packaging Information
The following packaging information reflects the most current data available for the designated device(s).
This data is subject to change without notice and without revision of this document.
Package
Type
Package
Drawing
Package
Qty
Eco
Lead/Ball
Finish
Orderable Device
TMS320DM647ZUT1
TMS320DM647ZUT7
TMS320DM647ZUT9
TMS320DM647ZUTA8
Status(1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Pins
529
529
529
529
MSL Peak Temp(3)
Level-4-245C-72HR
Level-4-245C-72HR
Level-4-245C-72HR
Level-4-245C-72HR
Plan(2)
Pb-Free
(RoHS)
FCBGA
FCBGA
FCBGA
FCBGA
ZUT
ZUT
ZUT
ZUT
84
84
84
84
Call TI
SNAGCU
SNAGCU
Call TI
Pb-Free
(RoHS)
Pb-Free
(RoHS)
Pb-Free
(RoHS)
TMS320DM647ZUTD7
TMS320DM647ZUTD9
ACTIVE
ACTIVE
FCBGA
FCBGA
ZUT
ZUT
529
529
TBD
TBD
Call TI
Call TI
Call TI
Call TI
Pb-Free
(RoHS)
TMS320DM648ZUT1
TMS320DM648ZUT7
TMS320DM648ZUT9
TMS320DM648ZUTA8
TMS320DM648ZUTD7
TMS320DM648ZUTD9
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
FCBGA
FCBGA
FCBGA
FCBGA
FCBGA
FCBGA
ZUT
ZUT
ZUT
ZUT
ZUT
ZUT
529
529
529
529
529
529
84
84
84
1
Call TI
SNAGCU
SNAGCU
Call TI
Level-4-245C-72HR
Level-4-245C-72HR
Level-4-245C-72HR
Level-4-245C-72HR
Level-4-245C-72HR
Level-4-245C-72HR
Pb-Free
(RoHS)
Pb-Free
(RoHS)
Pb-Free
(RoHS)
Pb-Free
(RoHS)
84
84
Call TI
Pb-Free
(RoHS)
Call TI
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this
part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please
check http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS
requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where
designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die
and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free
(RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based
flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material).
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer: The information provided on this page represents TI's knowledge
and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by
third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are
underway to better integrate information from third parties. TI has taken and continues to take reasonable
steps to provide representative and accurate information but may not have conducted destructive testing
or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information
to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI
part(s) at issue in this document sold by TI to Customer on an annual basis.
Copyright © 2010–2009, Texas Instruments Incorporated
Mechanical Data
177
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PACKAGE OPTION ADDENDUM
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16-Apr-2010
PACKAGING INFORMATION
Orderable Device
TMS320DM647ZUT1
TMS320DM647ZUT7
TMS320DM647ZUT9
TMS320DM647ZUTA8
TMS320DM647ZUTD7
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
FCBGA
ZUT
529
529
529
529
529
84 Pb-Free (RoHS
Exempt)
Call TI
Level-4-245C-72HR
Level-4-245C-72HR
Level-4-245C-72HR
Level-4-245C-72HR
Level-4-245C-72HR
FCBGA
FCBGA
FCBGA
FCBGA
ZUT
ZUT
ZUT
ZUT
84 Pb-Free (RoHS
Exempt)
Call TI
84 Pb-Free (RoHS
Exempt)
SNAGCU
Call TI
84 Pb-Free (RoHS
Exempt)
84 Pb-Free (RoHS
Exempt)
Call TI
TMS320DM647ZUTD9
TMS320DM648ZUT1
ACTIVE
ACTIVE
FCBGA
FCBGA
ZUT
ZUT
529
529
TBD
Call TI
Call TI
Call TI
84 Pb-Free (RoHS
Exempt)
Level-4-245C-72HR
TMS320DM648ZUT7
TMS320DM648ZUT9
TMS320DM648ZUTA8
TMS320DM648ZUTD7
TMS320DM648ZUTD9
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
FCBGA
FCBGA
FCBGA
FCBGA
FCBGA
ZUT
ZUT
ZUT
ZUT
ZUT
529
529
529
529
529
84 Pb-Free (RoHS
Exempt)
Call TI
Call TI
Call TI
Call TI
Call TI
Level-4-245C-72HR
Level-4-245C-72HR
Level-4-245C-72HR
Level-4-245C-72HR
Level-4-245C-72HR
84 Pb-Free (RoHS
Exempt)
84 Pb-Free (RoHS
Exempt)
84 Pb-Free (RoHS
Exempt)
1
Pb-Free (RoHS
Exempt)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
16-Apr-2010
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
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