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TMS320F28027, TMS320F28026, TMS320F28023, TMS320F28022

TMS320F28021, TMS320F28020, TMS320F280200

SPRS523M –NOVEMBER 2008–REVISED JANUARY 2019

TMS320F2802x Piccolo™ Microcontrollers

1 Device Overview

1.1 Features

1

• High-Efficiency 32-Bit CPU (TMS320C28x)

– 60 MHz (16.67-ns Cycle Time)

– 50 MHz (20-ns Cycle Time)

– 40 MHz (25-ns Cycle Time)

– 16 × 16 and 32 × 32 MAC Operations

– 16 × 16 Dual MAC

• On-Chip Memory

– Flash, SARAM, OTP, Boot ROM Available

• Code-Security Module

• 128-Bit Security Key and Lock

– Protects Secure Memory Blocks

– Prevents Firmware Reverse Engineering

• Serial Port Peripherals

– Harvard Bus Architecture

– Atomic Operations

– One Serial Communications Interface (SCI)

Universal Asynchronous Receiver/Transmitter

(UART) Module

– Fast Interrupt Response and Processing

– Unified Memory Programming Model

– Code-Efficient (in C/C++ and Assembly)

• Endianness: Little Endian

• Low Cost for Both Device and System:

– Single 3.3-V Supply

– One Serial Peripheral Interface (SPI) Module

– One Inter-Integrated-Circuit (I2C) Module

• Enhanced Control Peripherals

– ePWM

– High-Resolution PWM (HRPWM)

– Enhanced Capture (eCAP) Module

– Analog-to-Digital Converter (ADC)

– On-Chip Temperature Sensor

– Comparator

– No Power Sequencing Requirement

– Integrated Power-on and Brown-out Resets

– Small Packaging, as Low as 38-Pin Available

– Low Power

– No Analog Support Pins

• Advanced Emulation Features

– Analysis and Breakpoint Functions

– Real-Time Debug Through Hardware

• Package Options

• Clocking:

– Two Internal Zero-Pin Oscillators

– On-Chip Crystal Oscillator and External Clock

Input

– 38-Pin DA Thin Shrink Small-Outline Package

(TSSOP)

– 48-Pin PT Low-Profile Quad Flatpack (LQFP)

• Temperature Options

– Watchdog Timer Module

– Missing Clock Detection Circuitry

• Up to 22 Individually Programmable, Multiplexed

GPIO Pins With Input Filtering

– T: –40°C to 105°C

– S: –40°C to 125°C

• Peripheral Interrupt Expansion (PIE) Block That

Supports All Peripheral Interrupts

• Three 32-Bit CPU Timers

• Independent 16-Bit Timer in Each Enhanced Pulse

Width Modulator (ePWM)

– Q: –40°C to 125°C

(AEC Q100 Qualification for Automotive

Applications)

1.2 Applications

•

Appliances

•

Grid Infrastructure

Building Automation

Medical, Healthcare and Fitness

Motor Drives

Electric Vehicle/Hybrid Electric Vehicle (EV/HEV)

Powertrain

Power Delivery

•

Factory Automation

Telecom Infrastructure

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

TMS320F28027, TMS320F28026, TMS320F28023, TMS320F28022

TMS320F28021, TMS320F28020, TMS320F280200

SPRS523M –NOVEMBER 2008–REVISED JANUARY 2019

www.ti.com

1.3 Description

C2000™ 32-bit microcontrollers are optimized for processing, sensing, and actuation to improve closed-

loop performance in real-time control applications such as industrial motor drives; solar inverters and

digital power; electrical vehicles and transportation; motor control; and sensing and signal processing. The

C2000 line includes the Delfino™ Premium Performance family and the Piccolo™ Entry Performance

family.

The F2802x Piccolo™ family of microcontrollers provides the power of the C28x core coupled with highly

integrated control peripherals in low pin-count devices. This family is code-compatible with previous C28x-

based code, and also provides a high level of analog integration.

An internal voltage regulator allows for single-rail operation. Enhancements have been made to the

HRPWM to allow for dual-edge control (frequency modulation). Analog comparators with internal 10-bit

references have been added and can be routed directly to control the PWM outputs. The ADC converts

from 0 to 3.3-V fixed full-scale range and supports ratio-metric V_REFHI/V_REFLOreferences. The ADC

interface has been optimized for low overhead and latency.

To learn more about the C2000 MCUs, visit the C2000 Overview at www.ti.com/c2000.

Device Information⁽¹⁾

PART NUMBER

TMS320F28027PT

PACKAGE

LQFP (48)

TSSOP (38)

BODY SIZE

7.0 mm × 7.0 mm

12.5 mm × 6.2 mm

TMS320F28026PT

TMS320F28023PT

TMS320F28022PT

TMS320F28021PT

TMS320F28020PT

TMS320F280200PT

TMS320F28027DA

TMS320F28026DA

TMS320F28023DA

TMS320F28022DA

TMS320F28021DA

TMS320F28020DA

TMS320F280200DA

(1) For more information on these devices, see Mechanical, Packaging, and Orderable Information.

2

Device Overview

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TMS320F28020 TMS320F280200

TMS320F28027, TMS320F28026, TMS320F28023, TMS320F28022

TMS320F28021, TMS320F28020, TMS320F280200

www.ti.com

SPRS523M –NOVEMBER 2008–REVISED JANUARY 2019

1.4 Functional Block Diagram

Functional Block Diagram shows the functional block diagram for the device.

OTP 1K × 16

Secure

M0

SARAM 1K × 16

(0-wait)

SARAM

M1

SARAM 1K × 16

(0-wait)

1K/3K/4K × 16

Code

Security

Module

FLASH

8K/16K/32K × 16

Secure

(0-wait)

Secure

Boot-ROM

8K × 16

(0-wait)

OTP/Flash

Wrapper

PSWD

Memory Bus

TRST

TCK

TDI

TMS

TDO

COMP1OUT

GPIO

MUX

C28x

32-Bit CPU

COMP2OUT

GPIO

Mux

COMP1A

COMP1B

COMP2A

COMP2B

COMP

3 External Interrupts

XCLKIN

PIE

OSC1,

OSC2,

Ext,

CPU Timer 0

X1

X2

AIO

CPU Timer 1

CPU Timer 2

Memory Bus

MUX

PLL,

LPM,

WD

LPM Wakeup

XRS

ADC

A7:0

B7:0

POR/

BOR

VREG

32-Bit Peripheral Bus

16-Bit Peripheral Bus

32-Bit Peripheral Bus

ePWM

SCI

(4L FIFO)

SPI

(4L FIFO)

I2C

eCAP

(4L FIFO)

HRPWM

From

COMP1OUT,

COMP2OUT

GPIO MUX

A. Not all peripheral pins are available at the same time due to multiplexing.

Figure 1-1. Functional Block Diagram

Device Overview

3

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TMS320F28020 TMS320F280200

TMS320F28027, TMS320F28026, TMS320F28023, TMS320F28022

TMS320F28021, TMS320F28020, TMS320F280200

SPRS523M –NOVEMBER 2008–REVISED JANUARY 2019

www.ti.com

Table of Contents

1

Device Overview ......................................... 1

1.1 Features .............................................. 1

1.2 Applications........................................... 1

1.3 Description............................................ 2

1.4 Functional Block Diagram ........................... 3

Revision History ......................................... 5

Device Comparison ..................................... 6

3.1 Related Products ..................................... 8

Terminal Configuration and Functions.............. 9

4.1 Pin Diagrams ......................................... 9

4.2 Signal Descriptions.................................. 11

Specifications ........................................... 16

5.1 Absolute Maximum Ratings ........................ 16

5.2 ESD Ratings – Automotive.......................... 16

5.3 ESD Ratings – Commercial......................... 17

5.4 Recommended Operating Conditions............... 17

5.5 Power Consumption Summary...................... 18

5.6 Electrical Characteristics............................ 23

5.7 Thermal Resistance Characteristics ................ 24

5.8 Thermal Design Considerations .................... 25

5.14 Flash Timing ........................................ 34

Detailed Description ................................... 37

6.1 Overview ............................................ 37

6.2 Memory Maps ...................................... 45

6.3 Register Maps....................................... 53

6.4 Device Emulation Registers......................... 54

6.5 VREG/BOR/POR.................................... 55

6.6 System Control ...................................... 57

6.7 Low-power Modes Block ............................ 65

6.8 Interrupts ............................................ 66

6.9 Peripherals .......................................... 71

Applications, Implementation, and Layout ...... 122

7.1 TI Design or Reference Design.................... 122

Device and Documentation Support.............. 123

8.1 Getting Started..................................... 123

6

2

3

4

5

7

8

8.2

Device and Development Support Tool

Nomenclature ...................................... 123

8.3 Tools and Software ................................ 124

8.4 Documentation Support............................ 126

8.5 Related Links ...................................... 127

8.6 Community Resources............................. 127

8.7 Trademarks ........................................ 127

8.8 Electrostatic Discharge Caution ................... 127

8.9 Glossary............................................ 127

5.9

Emulator Connection Without Signal Buffering for

the MCU............................................. 25

5.10 Parameter Information .............................. 26

5.11 Test Load Circuit ................................... 26

5.12 Power Sequencing .................................. 27

5.13 Clock Specifications................................. 30

9

Mechanical, Packaging, and Orderable

Information............................................. 128

9.1 Packaging Information ............................. 128

4

Table of Contents

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Product Folder Links: TMS320F28027 TMS320F28026 TMS320F28023 TMS320F28022 TMS320F28021

TMS320F28020 TMS320F280200

TMS320F28027, TMS320F28026, TMS320F28023, TMS320F28022

TMS320F28021, TMS320F28020, TMS320F280200

www.ti.com

SPRS523M –NOVEMBER 2008–REVISED JANUARY 2019

2 Revision History

Changes from December 15, 2017 to January 8, 2019 (from L Revision (December 2017) to M Revision)

Page

•

Global: Replaced individual peripheral guides with the TMS320F2802x,TMS320F2802xx Piccolo Technical

Reference Manual. ................................................................................................................... 1

Section 1.3 (Description): Updated section. ...................................................................................... 2

Section 3.1 (Related Products): Updated section. ............................................................................... 8

Table 4-1 (Signal Descriptions): Updated DESCRIPTION of XRS. .......................................................... 11

Table 5-11 (Internal Zero-Pin Oscillator (INTOSC1/INTOSC2) Characteristics): Updated "Oscillator frequency

will vary over temperature ..." footnote: Replaced the controlSUITE example with C2000Ware. ........................ 32

Section 6.1.8 (Boot ROM): Updated "The Boot ROM is factory-programmed ..." paragraph. ............................ 39

Figure 6-13 (External and PIE Interrupt Sources): Updated figure. .......................................................... 66

Section 8.3 (Tools and Software): Added "C2000Ware for C2000 MCUs" and "UniFlash Standalone Flash Tool".. 124

Section 8.4 (Documentation Support): Replaced individual peripheral guides with the

•

TMS320F2802x,TMS320F2802xx Piccolo Technical Reference Manual. Updated section. ............................ 126

Revision History

5

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TMS320F28020 TMS320F280200

TMS320F28027, TMS320F28026, TMS320F28023, TMS320F28022

TMS320F28021, TMS320F28020, TMS320F280200

SPRS523M –NOVEMBER 2008–REVISED JANUARY 2019

www.ti.com

3.1 Related Products

For information about other devices in the Piccolo family of products, see the following links:

Original Piccolo™ series:

TMS320F2802x Piccolo™ Microcontrollers

The F2802x series is the original Piccolo and offers the lowest pin-count and Flash memory size options.

InstaSPIN-FOC™ versions are available.

TMS320F2803x Piccolo™ Microcontrollers

The F2803x series increases the pin-count and memory size options. The F2803x series also introduces

the parallel control law accelerator (CLA) option.

TMS320F2805x Piccolo™ Microcontrollers

The F2805x series is similar to the F2803x series but adds on-chip programmable gain amplifiers (PGAs).

InstaSPIN-FOC and InstaSPIN-MOTION™ versions are available.

TMS320F2806x Piccolo™ Microcontrollers

The F2806x series is the first to include a floating-point unit (FPU). The F2806x series also increases the

pin-count, memory size options, and the quantity of peripherals. InstaSPIN-FOC™ and InstaSPIN-

MOTION™ versions are available.

Newest Piccolo™ series:

TMS320F2807x Piccolo™ Microcontrollers

The F2807x series is the highest-end Piccolo with the most performance, largest pin counts, flash memory

sizes, and peripheral options. The F2807x series includes the latest generation of accelerators, ePWM

peripherals, and analog technology.

TMS320F28004x Piccolo™ Microcontrollers

The F28004x series is a reduced version of the F2807x series with the latest generational enhancements.

The F28004x series is the best roadmap option for those using the F2806x series. InstaSPIN-FOC and

configurable logic block (CLB) versions are available.

8

Device Comparison

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TMS320F28020 TMS320F280200

TMS320F28027, TMS320F28026, TMS320F28023, TMS320F28022

TMS320F28021, TMS320F28020, TMS320F280200

www.ti.com

SPRS523M –NOVEMBER 2008–REVISED JANUARY 2019

4 Terminal Configuration and Functions

4.1 Pin Diagrams

Figure 4-1 shows the 48-pin PT low-profile quad flatpack (LQFP) pin assignments. Figure 4-2 shows the

38-pin DA thin shrink small-outline package (TSSOP) pin assignments.

GPIO2/EPWM2A 37

GPIO3/EPWM2B/COMP2OUT 38

GPIO4/EPWM3A 39

24 GPIO18/SPICLKA/SCITXDA/XCLKOUT

23 GPIO38/XCLKIN (TCK)

22 GPIO37 (TDO)

GPIO5/EPWM3B/ECAP1 40

21 GPIO36 (TMS)

GPIO6/EPWM4A/EPWMSYNCI/EPWMSYNCO 41

GPIO7/EPWM4B/SCIRXDA 42

20 GPIO35 (TDI)

19 GPIO34/COMP2OUT

18 ADCINB7

V_DD

V_SS

43

44

17 ADCINB6/AIO14

16 ADCINB4/COMP2B/AIO12

15 ADCINB3

X1 45

X2 46

GPIO12/TZ1/SCITXDA 47

GPIO28/SCIRXDA/SDAA/TZ2 48

14 ADCINB2/COMP1B/AIO10

13 ADCINB1

Figure 4-1. 2802x 48-Pin PT LQFP (Top View)

Terminal Configuration and Functions

9

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TMS320F28020 TMS320F280200

TMS320F28027, TMS320F28026, TMS320F28023, TMS320F28022

TMS320F28021, TMS320F28020, TMS320F280200

SPRS523M –NOVEMBER 2008–REVISED JANUARY 2019

www.ti.com

V_DD

V_SS

1

38 TEST

2

37 GPIO0/EPWM1A

VREGENZ

V_DDIO

3

36 GPIO1/EPWM1B/COMP1OUT

35 GPIO16/SPISIMOA/TZ2

34 GPIO17/SPISOMIA/TZ3

4

GPIO2/EPWM2A

GPIO3/EPWM2B

5

6

33 GPIO19/XCLKIN/SPISTEA/SCIRXDA/ECAP1

32 GPIO18/SPICLKA/SCITXDA/XCLKOUT

31 GPIO38/XCLKIN (TCK)

30 GPIO37 (TDO)

GPIO4/EPWM3A

7

GPIO5/EPWM3B/ECAP1

GPIO6/EPWM4A/EPWMSYNCI/EPWMSYNCO

GPIO7/EPWM4B/SCIRXDA

V_DD

8

9

10

11

12

13

14

15

16

17

18

19

29 GPIO36 (TMS)

28 GPIO35 (TDI)

V_SS

27 GPIO34

GPIO12/TZ1/SCITXDA

GPIO28/SCIRXDA/SDAA/TZ2

GPIO29/SCITXDA/SCLA/TZ3

26 ADCINB6/AIO14

25 ADCINB4/AIO12

24 ADCINB2/COMP1B/AIO10

/V_REFLO

23 V_SSA

22 V_DDA

TRST

XRS

ADCINA6/AIO6

ADCINA4/AIO4

21 ADCINA0/V_REFHI

20 ADCINA2/COMP1A/AIO2

Figure 4-2. 2802x 38-Pin DA TSSOP (Top View)

10

Terminal Configuration and Functions

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TMS320F28020 TMS320F280200

TMS320F28027, TMS320F28026, TMS320F28023, TMS320F28022

TMS320F28021, TMS320F28020, TMS320F280200

www.ti.com

SPRS523M –NOVEMBER 2008–REVISED JANUARY 2019

4.2 Signal Descriptions

Table 4-1 describes the signals. With the exception of the JTAG pins, the GPIO function is the default at

reset, unless otherwise mentioned. The peripheral signals that are listed under them are alternate

functions. Some peripheral functions may not be available in all devices. See Table 3-1 for details. Inputs

are not 5-V tolerant. All GPIO pins are I/O/Z and have an internal pullup, which can be selectively

enabled/disabled on a per-pin basis. This feature only applies to the GPIO pins. The pullups on the PWM

pins are not enabled at reset. The pullups on other GPIO pins are enabled upon reset. The AIO pins do

not have an internal pullup.

NOTE

When the on-chip VREG is used, the GPIO19, GPIO34, GPIO35, GPIO36, GPIO37, and

GPIO38 pins could glitch during power up. This potential glitch will finish before the boot

mode pins are read and will not affect boot behavior. If glitching is unacceptable in an

application, 1.8 V could be supplied externally. Alternatively, adding a current-limiting resistor

(for example, 470 Ω) in series with these pins and any external driver could be considered to

limit the potential for degradation to the pin and/or external circuitry. There is no power-

sequencing requirement when using an external 1.8-V supply. However, if the 3.3-V

transistors in the level-shifting output buffers of the I/O pins are powered before the 1.8-V

transistors, it is possible for the output buffers to turn on, causing a glitch to occur on the pin

during power up. To avoid this behavior, power the V_DDpins before or with the V_DDIOpins,

ensuring that the V_DDpins have reached 0.7 V before the V_DDIOpins reach 0.7 V.

Table 4-1. Signal Descriptions⁽¹⁾

TERMINAL

I/O/Z

DESCRIPTION

PT

PIN NO.

DA

PIN NO.

NAME

JTAG

JTAG test reset with internal pulldown. TRST, when driven high, gives the scan

system control of the operations of the device. If this signal is not connected or

driven low, the device operates in its functional mode, and the test reset signals

are ignored.

NOTE: TRST is an active high test pin and must be maintained low at all times

during normal device operation. An external pulldown resistor is required on this

pin. The value of this resistor should be based on drive strength of the debugger

pods applicable to the design. A 2.2-kΩ resistor generally offers adequate

protection. Because this is application-specific, TI recommends validating each

target board for proper operation of the debugger and the application. (↓)

TRST

2

16

I

TCK

TMS

See GPIO38

I

See GPIO38. JTAG test clock with internal pullup (↑)

See GPIO36. JTAG test-mode select (TMS) with internal pullup. This serial control

input is clocked into the TAP controller on the rising edge of TCK. (↑)

See GPIO36

See GPIO35

See GPIO35. JTAG test data input (TDI) with internal pullup. TDI is clocked into

the selected register (instruction or data) on a rising edge of TCK. (↑)

TDI

I

See GPIO37. JTAG scan out, test data output (TDO). The contents of the

selected register (instruction or data) are shifted out of TDO on the falling edge of

TCK.

TDO

See GPIO37

O/Z

(8-mA drive)

FLASH

TEST

30

38

I/O

Test Pin. Reserved for TI. Must be left unconnected.

(1) I = Input, O = Output, Z = High Impedance, OD = Open Drain, ↑ = Pullup, ↓ = Pulldown

Terminal Configuration and Functions

11

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TMS320F28021, TMS320F28020, TMS320F280200

SPRS523M –NOVEMBER 2008–REVISED JANUARY 2019

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Table 4-1. Signal Descriptions⁽¹⁾(continued)

TERMINAL

I/O/Z

DESCRIPTION

PT

PIN NO.

DA

PIN NO.

NAME

CLOCK

See GPIO18. Output clock derived from SYSCLKOUT. XCLKOUT is either the

same frequency, one-half the frequency, or one-fourth the frequency of

SYSCLKOUT. This is controlled by bits 1:0 (XCLKOUTDIV) in the XCLK register.

At reset, XCLKOUT = SYSCLKOUT/4. The XCLKOUT signal can be turned off by

setting XCLKOUTDIV to 3. The mux control for GPIO18 must also be set to

XCLKOUT for this signal to propogate to the pin.

XCLKOUT

See GPIO18

O/Z

See GPIO19 and GPIO38. External oscillator input. Pin source for the clock is

controlled by the XCLKINSEL bit in the XCLK register, GPIO38 is the default

selection. This pin feeds a clock from an external 3.3-V oscillator. In this case, the

X1 pin, if available, must be tied to GND and the on-chip crystal oscillator must be

disabled through bit 14 in the CLKCTL register. If a crystal/resonator is used, the

XCLKIN path must be disabled by bit 13 in the CLKCTL register.

XCLKIN

See GPIO19 and GPIO38

I

NOTE: Designs that use the GPIO38/TCK/XCLKIN pin to supply an external clock

for normal device operation may need to incorporate some hooks to disable this

path during debug using the JTAG connector. This is to prevent contention with

the TCK signal, which is active during JTAG debug sessions. The zero-pin internal

oscillators may be used during this time to clock the device.

On-chip 1.8-V crystal-oscillator input. To use this oscillator, a quartz crystal or a

ceramic resonator must be connected across X1 and X2. In this case, the XCLKIN

path must be disabled by bit 13 in the CLKCTL register. If this pin is not used, it

must be tied to GND. (I)

X1

X2

45

46

–

I

On-chip crystal-oscillator output. A quartz crystal or a ceramic resonator must be

connected across X1 and X2. If X2 is not used, it must be left unconnected. (O)

O

RESET

Device Reset (in) and Watchdog Reset (out). Piccolo devices have a built-in

power-on reset (POR) and brown-out reset (BOR) circuitry. During a power-on or

brown-out condition, this pin is driven low by the device. An external circuit may

also drive this pin to assert a device reset. This pin is also driven low by the MCU

when a watchdog reset occurs. During watchdog reset, the XRS pin is driven low

for the watchdog reset duration of 512 OSCCLK cycles. A resistor with a value

from 2.2 kΩ to 10 kΩ should be placed between XRS and V_DDIO. If a capacitor is

placed between XRS and V_SSfor noise filtering, it should be 100 nF or smaller.

These values will allow the watchdog to properly drive the XRS pin to V_OLwithin

512 OSCCLK cycles when the watchdog reset is asserted. Regardless of the

source, a device reset causes the device to terminate execution. The program

counter points to the address contained at the location 0x3F FFC0. When reset is

deactivated, execution begins at the location designated by the program counter.

The output buffer of this pin is an open-drain device with an internal pullup. (↑) If

this pin is driven by an external device, it should be done using an open-drain

device.

XRS

3

17

I/OD

ADC, COMPARATOR, ANALOG I/O

ADC Group A, Channel 7 input

ADC Group A, Channel 6 input

ADCINA7

ADCINA6

AIO6

6

4

–

I

18

I/O

Digital AIO 6

ADCINA4

COMP2A

AIO4

I

ADC Group A, Channel 4 input

Comparator Input 2A (available in 48-pin device only)

Digital AIO 4

5

7

9

19

–

I

I/O

ADCINA3

ADCINA2

COMP1A

AIO2

I

ADC Group A, Channel 3 input

ADC Group A, Channel 2 input

Comparator Input 1A

I

20

I

I/O

Digital AIO 2

ADCINA1

ADCINA0

V_REFHI

8

–

21

–

I

ADC Group A, Channel 1 input

ADC Group A, Channel 0 input

10

18

ADC External Reference High – only used when in ADC external reference mode.

See Section 6.9.1.1, ADC.

ADCINB7

I

ADC Group B, Channel 7 input

12

Terminal Configuration and Functions

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TMS320F28021, TMS320F28020, TMS320F280200

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SPRS523M –NOVEMBER 2008–REVISED JANUARY 2019

Table 4-1. Signal Descriptions⁽¹⁾(continued)

TERMINAL

I/O/Z

DESCRIPTION

PT

PIN NO.

DA

PIN NO.

NAME

ADCINB6

AIO14

I

ADC Group B, Channel 6 input

Digital AIO 14

17

26

I/O

ADCINB4

COMP2B

AIO12

I

ADC Group B, Channel 4 input

16

15

14

13

25

–

I

Comparator Input 2B (available in 48-pin device only)

Digital AIO12

I/O

ADCINB3

ADCINB2

COMP1B

AIO10

I

ADC Group B, Channel 3 input

ADC Group B, Channel 2 input

Comparator Input 1B

I

24

–

I/O

I

Digital AIO 10

ADCINB1

ADC Group B, Channel 1 input

CPU AND I/O POWER

V_DDA

11

12

22

23

Analog Power Pin. Tie with a 2.2-µF capacitor (typical) close to the pin.

Analog Ground Pin

V_SSA

V_REFLO

I

ADC External Reference Low (always tied to ground)

32

43

1

CPU and Logic Digital Power Pins. When using internal VREG, place one 1.2-µF

capacitor between each V_DDpin and ground. Higher value capacitors may be

used.

V_DD

11

Digital I/O Buffers and Flash Memory Power Pin. Single supply source when

VREG is enabled. Place a decoupling capacitor on this pin. The exact value

should be determined by the system voltage regulation solution.

V_DDIO

35

4

33

44

2

V_SS

Digital Ground Pins

12

VOLTAGE REGULATOR CONTROL SIGNAL

Internal VREG Enable/Disable. Pull low to enable the internal voltage regulator

(VREG), pull high to disable VREG.

GPIO AND PERIPHERAL SIGNALS⁽²⁾

VREGENZ

34

29

3

I

GPIO0

I/O/Z

O

General-purpose input/output 0

EPWM1A

Enhanced PWM1 Output A and HRPWM channel

37

–

GPIO1

EPWM1B

–

I/O/Z

O

General-purpose input/output 1

Enhanced PWM1 Output B

28

37

38

36

5

–

COMP1OUT

GPIO2

EPWM2A

–

O

Direct output of Comparator 1

I/O/Z

O

General-purpose input/output 2

Enhanced PWM2 Output A and HRPWM channel

–

GPIO3

EPWM2B

–

I/O/Z

O

General-purpose input/output 3

Enhanced PWM2 Output B

6

–

COMP2OUT

O

Direct output of Comparator 2 (available in 48-pin device only)

(2) The GPIO function (shown in bold italics) is the default at reset. The peripheral signals that are listed under them are alternate functions.

For JTAG pins that have the GPIO functionality multiplexed, the input path to the GPIO block is always valid. The output path from the

GPIO block and the path to the JTAG block from a pin is enabled/disabled based on the condition of the TRST signal. See the System

Control chapter in the TMS320F2802x,TMS320F2802xx Piccolo Technical Reference Manual for details.

Terminal Configuration and Functions

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Table 4-1. Signal Descriptions⁽¹⁾(continued)

TERMINAL

I/O/Z

DESCRIPTION

PT

PIN NO.

DA

PIN NO.

NAME

GPIO4

I/O/Z

O

General-purpose input/output 4

EPWM3A

–

Enhanced PWM3 output A and HRPWM channel

–

39

40

41

42

47

27

26

7

8

–

GPIO5

EPWM3B

–

I/O/Z

O

General-purpose input/output 5

Enhanced PWM3 output B

–

ECAP1

GPIO6

EPWM4A

EPWMSYNCI

EPWMSYNCO

GPIO7

EPWM4B

SCIRXDA

–

I/O

Enhanced Capture input/output 1

General-purpose input/output 6

Enhanced PWM4 output A and HRPWM channel

External ePWM sync pulse input

External ePWM sync pulse output

General-purpose input/output 7

Enhanced PWM4 output B

SCI-A receive data

I/O/Z

O

9

I

O

I/O/Z

O

10

13

35

34

I

–

GPIO12

TZ1

I/O/Z

General-purpose input/output 12

Trip Zone input 1

I

SCITXDA

–

O

SCI-A transmit data

–

GPIO16

SPISIMOA

–

I/O/Z

I/O

General-purpose input/output 16

SPI slave in, master out

–

TZ2

I

Trip Zone input 2

GPIO17

SPISOMIA

–

I/O/Z

I/O

General-purpose input/output 17

SPI-A slave out, master in

–

TZ3

I

Trip zone input 3

GPIO18

SPICLKA

SCITXDA

XCLKOUT

I/O/Z

I/O

O

General-purpose input/output 18

SPI-A clock input/output

SCI-A transmit

O/Z

Output clock derived from SYSCLKOUT. XCLKOUT is either the same frequency,

one-half the frequency, or one-fourth the frequency of SYSCLKOUT. This is

controlled by bits 1:0 (XCLKOUTDIV) in the XCLK register. At reset, XCLKOUT =

SYSCLKOUT/4. The XCLKOUT signal can be turned off by setting XCLKOUTDIV

to 3. The mux control for GPIO18 must also be set to XCLKOUT for this signal to

propogate to the pin.

24

32

GPIO19

I/O/Z

I

General-purpose input/output 19

XCLKIN

External Oscillator Input. The path from this pin to the clock block is not gated by

the mux function of this pin. Care must be taken not to enable this path for

clocking if it is being used for the other periperhal functions

25

48

33

14

SPISTEA

SCIRXDA

ECAP1

GPIO28

SCIRXDA

SDAA

I/O

SPI-A slave transmit enable input/output

SCI-A receive

I

I/O

I/O/Z

I

Enhanced Capture input/output 1

General-purpose input/output 28

SCI receive data

I/OD

I

I2C data open-drain bidirectional port

Trip zone input 2

TZ2

14

Terminal Configuration and Functions

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SPRS523M –NOVEMBER 2008–REVISED JANUARY 2019

Table 4-1. Signal Descriptions⁽¹⁾(continued)

TERMINAL

I/O/Z

DESCRIPTION

PT

PIN NO.

DA

PIN NO.

NAME

GPIO29

I/O/Z

O

General-purpose input/output 29.

SCI transmit data

SCITXDA

SCLA

1

15

–

I/OD

I

I2C clock open-drain bidirectional port

Trip zone input 3

TZ3

GPIO32

I/O/Z

I/OD

I

General-purpose input/output 32

I2C data open-drain bidirectional port

Enhanced PWM external sync pulse input

ADC start-of-conversion A

SDAA

31

36

EPWMSYNCI

ADCSOCAO

GPIO33

O

I/O/Z

I/OD

O

General-Purpose Input/Output 33

I2C clock open-drain bidirectional port

Enhanced PWM external synch pulse output

ADC start-of-conversion B

SCLA

–

EPWMSYNCO

ADCSOCBO

GPIO34

O

I/O/Z

General-Purpose Input/Output 34

Direct output of Comparator 2. COMP2OUT signal is not available in the DA

package.

COMP2OUT

O

19

27

–

GPIO35

TDI

I/O/Z

I

General-Purpose Input/Output 35

20

21

22

28

29

30

JTAG test data input (TDI) with internal pullup. TDI is clocked into the selected

register (instruction or data) on a rising edge of TCK

GPIO36

TMS

I/O/Z

I

General-Purpose Input/Output 36

JTAG test-mode select (TMS) with internal pullup. This serial control input is

clocked into the TAP controller on the rising edge of TCK.

GPIO37

TDO

I/O/Z

O/Z

General-Purpose Input/Output 37

JTAG scan out, test data output (TDO). The contents of the selected register

(instruction or data) are shifted out of TDO on the falling edge of TCK (8 mA drive)

GPIO38

TCK

I/O/Z

General-Purpose Input/Output 38

JTAG test clock with internal pullup

I

23

31

XCLKIN

External Oscillator Input. The path from this pin to the clock block is not gated by

the mux function of this pin. Care must be taken to not enable this path for

clocking if it is being used for the other functions.

Terminal Configuration and Functions

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5 Specifications

5.1 Absolute Maximum Ratings⁽¹⁾⁽²⁾

over operating free-air temperature range (unless otherwise noted)

MIN

–0.3

–20

MAX

4.6

2.5

4.6

2.5

4.6

20

UNIT

V_DDIO(I/O and Flash) with respect to V_SS

Supply voltage

V

V_DDwith respect to V_SS

Analog voltage

Input voltage

Output voltage

V_DDAwith respect to V_SSA

V_IN(3.3 V)

V_IN(X1)

V_O

(3)

Digital input (per pin), I_IK(V_IN< V_SSor V_IN> V_DDIO

)

Analog input (per pin), I_IKANALOG

–20

20

Input clamp current

(V_IN< V_SSAor V_IN> V_DDA

)

mA

Total for all inputs, I_IKTOTAL

(V_IN< V_SS/V_SSAor V_IN> V_DDIO/V_DDA

)

Output clamp current

Junction temperature⁽⁴⁾

Storage temperature⁽⁴⁾

I_OK(V_O< 0 or V_O> V_DDIO

)

–20

–40

–65

20

150

mA

°C

T_J

T_stg

°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under Section 5.4 is not implied.

Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltage values are with respect to V_SS, unless otherwise noted.

(3) Continuous clamp current per pin is ±2 mA.

(4) Long-term high-temperature storage or extended use at maximum temperature conditions may result in a reduction of overall device life.

For additional information, see Semiconductor and IC Package Thermal Metrics.

5.2 ESD Ratings – Automotive

VALUE

UNIT

TMS320F28027, TMS320F28027F, TMS320F28026, TMS320F28026F, TMS320F28023, TMS320F28022 in 48-pin PT package

Human body model (HBM), per AEC Q100-002⁽¹⁾

All pins

±2000

All pins except corner

pins

±500

Electrostatic

discharge

V_(ESD)

V

Charged device model (CDM), per AEC Q100-011

Corner pins on 48-pin PT:

1, 12, 13, 24, 25, 36, 37,

48

±750

TMS320F28027, TMS320F28027F, TMS320F28026, TMS320F28026F, TMS320F28023, TMS320F28022 in 38-pin DA package

Human body model (HBM), per AEC Q100-002⁽¹⁾

All pins

±2000

All pins except corner

pins

Electrostatic

discharge

±500

V_(ESD)

V

Charged device model (CDM), per AEC Q100-011

Corner pins on 38-pin DA:

1, 19, 20, 38

±750

(1) AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

16

Specifications

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5.3 ESD Ratings – Commercial

TMS320F28021, TMS320F28020, TMS320F280200 in 48-pin PT package

VALUE

UNIT

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

±2000

±500

V_(ESD)

Electrostatic discharge

V

Charged-device model (CDM), per JEDEC specification JESD22-

C101⁽²⁾

TMS320F28021, TMS320F28020, TMS320F280200 in 38-pin DA package

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

±2000

±500

V_(ESD)

Electrostatic discharge

V

Charged-device model (CDM), per JEDEC specification JESD22-

C101⁽²⁾

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

5.4 Recommended Operating Conditions

MIN

NOM

MAX

UNIT

(1)

Device supply voltage, I/O, V_DDIO

2.97

3.3

3.63

V

Device supply voltage CPU, V_DD(When internal VREG is

disabled and 1.8 V is supplied externally)

1.71

1.8

1.995

V

Supply ground, V_SS

0

3.3

0

V

Analog supply voltage, V_DDA

Analog ground, V_SSA

2.97

3.63

28020, 28021, 280200

28022, 28023

2

40

Device clock frequency (system clock)

2

50

MHz

28026, 28027

2

60

High-level input voltage, V_IH(3.3 V)

Low-level input voltage, V_IL(3.3 V)

V_DDIO+ 0.3

V

V_SS– 0.3

0.8

–4

–8

4

V

All GPIO/AIO pins

Group 2⁽²⁾

mA

High-level output source current, V_OH= V_OH(MIN), I_OH

Low-level output sink current, V_OL= V_OL(MAX), I_OL

All GPIO/AIO pins

Group 2⁽²⁾

8

T version

–40

105

125

S version

(3)

Junction temperature, T_J

°C

Q version

(AEC Q100

Qualification)

–40

125

(1) A tolerance of ±10% may be used for V_DDIOif the BOR is not used. See the TMS320F2802x, TMS320F2802xx Piccolo™ MCUs Silicon

Errata for more information. V_DDIOtolerance is ±5% if the BOR is enabled.

(2) Group 2 pins are as follows: GPIO16, GPIO17, GPIO18, GPIO19, GPIO28, GPIO29, GPIO36, GPIO37

(3) T_A(Ambient temperature) is product- and application-dependent and can go up to the specified T_Jmax of the device. See Section 5.8,

Thermal Design Considerations.

Specifications

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TMS320F28021, TMS320F28020, TMS320F280200

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5.5 Power Consumption Summary

Table 5-1. TMS320F2802x/F280200⁽¹⁾Current Consumption at 40-MHz SYSCLKOUT

VREG ENABLED

VREG DISABLED

(2)

(3)

(2)

(3)

MODE

TEST CONDITIONS

I_DDIO

TYP⁽⁴⁾

I_DDA

TYP⁽⁴⁾

I_DD

I_DDIO

TYP⁽⁴⁾

I_DDA

TYP⁽⁴⁾

MAX

TYP⁽⁴⁾

MAX

The following peripheral clocks are

enabled:

•

ePWM1/2/3/4

eCAP1

SCI-A

SPI-A

ADC

Operational

(Flash)

70 mA 80 mA 13 mA 18 mA

62 mA

70 mA

15 mA

18 mA 13 mA

18 mA

I2C

COMP1/2

CPU Timer0/1/2

All PWM pins are toggled at 40 kHz.

All I/O pins are left unconnected.⁽⁵⁾

Code is running out of flash with 1 wait-

state.

XCLKOUT is turned off.

Flash is powered down.

XCLKOUT is turned off.

All peripheral clocks are off.

IDLE

13 mA 16 mA

53 μA

10 μA

58 μA

15 μA

15 mA

3 mA

17 mA

6 mA

120 μA

25 μA

400 μA 53 μA

400 μA 10 μA

10 μA

58 μA

15 μA

Flash is powered down.

Peripheral clocks are off.

STANDBY

HALT

3 mA

6 mA

Flash is powered down.

Peripheral clocks are off.

Input clock is disabled.⁽⁶⁾

50 μA

15 μA

(1) For the TMS320F280200 device, subtract the I_DDcurrent number for eCAP (see Table 5-4) from I_DD(VREG disabled)/I_DDIO(VREG

enabled) current numbers shown in Table 5-1 for operational mode.

(2) I_DDIOcurrent is dependent on the electrical loading on the I/O pins.

(3) To realize the I_DDAcurrents shown for IDLE, STANDBY, and HALT, clock to the ADC module must be turned off explicitly by writing to

the PCLKCR0 register.

(4) The TYP numbers are applicable over room temperature and nominal voltage.

(5) The following is done in a loop:

•

Data is continuously transmitted out of SPI-A and SCI-A ports.

The hardware multiplier is exercised.

Watchdog is reset.

ADC is performing continuous conversion.

COMP1/2 are continuously switching voltages.

GPIO17 is toggled.

(6) If a quartz crystal or ceramic resonator is used as the clock source, the HALT mode shuts down the on-chip crystal oscillator.

18

Specifications

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TMS320F28021, TMS320F28020, TMS320F280200

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SPRS523M –NOVEMBER 2008–REVISED JANUARY 2019

Table 5-2. TMS320F2802x Current Consumption at 50-MHz SYSCLKOUT

VREG ENABLED

VREG DISABLED

(1)

(2)

(1)

(2)

MODE

TEST CONDITIONS

I_DDIO

TYP⁽³⁾

I_DDA

TYP⁽³⁾

I_DD

I_DDIO

TYP⁽³⁾

I_DDA

TYP⁽³⁾

MAX

TYP⁽³⁾

MAX

The following peripheral clocks are

enabled:

•

ePWM1/2/3/4

eCAP1

SCI-A

SPI-A

ADC

Operational

(Flash)

80 mA 90 mA 13 mA 18 mA

71 mA

80 mA

15 mA

18 mA 13 mA

18 mA

I2C

COMP1/2

CPU Timer0/1/2

All PWM pins are toggled at 40 kHz.

All I/O pins are left unconnected.⁽⁴⁾

Code is running out of flash with 1 wait-

state.

XCLKOUT is turned off.

Flash is powered down.

XCLKOUT is turned off.

All peripheral clocks are off.

IDLE

16 mA 19 mA

64 μA

10 μA

69 μA

15 μA

17 mA

4 mA

20 mA

7 mA

120 μA

25 μA

400 μA 64 μA

400 μA 10 μA

10 μA

69 μA

15 μA

Flash is powered down.

Peripheral clocks are off.

STANDBY

HALT

4 mA

7 mA

Flash is powered down.

Peripheral clocks are off.

Input clock is disabled.⁽⁵⁾

50 μA

15 μA

(1) I_DDIOcurrent is dependent on the electrical loading on the I/O pins.

(2) To realize the I_DDAcurrents shown for IDLE, STANDBY, and HALT, clock to the ADC module must be turned off explicitly by writing to

the PCLKCR0 register.

(3) The TYP numbers are applicable over room temperature and nominal voltage.

(4) The following is done in a loop:

•

Data is continuously transmitted out of SPI-A and SCI-A ports.

The hardware multiplier is exercised.

Watchdog is reset.

ADC is performing continuous conversion.

COMP1/2 are continuously switching voltages.

GPIO17 is toggled.

(5) If a quartz crystal or ceramic resonator is used as the clock source, the HALT mode shuts down the on-chip crystal oscillator.

Specifications

19

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TMS320F28021, TMS320F28020, TMS320F280200

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Table 5-3. TMS320F2802x Current Consumption at 60-MHz SYSCLKOUT

VREG ENABLED

VREG DISABLED

(1)

(2)

(1)

(2)

MODE

TEST CONDITIONS

I_DDIO

TYP⁽³⁾

I_DDA

TYP⁽³⁾

I_DD

I_DDIO

TYP⁽³⁾

I_DDA

TYP⁽³⁾

MAX

TYP⁽³⁾

MAX

The following peripheral clocks

are enabled:

•

ePWM1/2/3/4

eCAP1

SCI-A

SPI-A

ADC

Operational

(Flash)

I2C

90 mA

100 mA

13 mA

18 mA

80 mA

90 mA

15 mA

18 mA 13 mA

18 mA

COMP1/2

CPU-TIMER0/1/2

All PWM pins are toggled at

60 kHz.

All I/O pins are left

unconnected.⁽⁴⁾

Code is running out of flash

with 2 wait states.

XCLKOUT is turned off.

Flash is powered down.

XCLKOUT is turned off.

All peripheral clocks are turned

off.

IDLE

18 mA

23 mA

7 mA

75 μA

80 μA

19 mA

24 mA

7 mA

120 μA 400 μA

75 μA

80 μA

Flash is powered down.

Peripheral clocks are off.

STANDBY

HALT

4 mA

10 μA

15 μA

4 mA

120 μA 400 μA

25 μA

10 μA

15 μA

Flash is powered down.

Peripheral clocks are off.

Input clock is disabled.⁽⁵⁾

50 μA

15 μA

(1) I_DDIOcurrent is dependent on the electrical loading on the I/O pins.

(2) To realize the I_DDAcurrents shown for IDLE, STANDBY, and HALT, clock to the ADC module must be turned off explicitly by writing to

the PCLKCR0 register.

(3) The TYP numbers are applicable over room temperature and nominal voltage.

(4) The following is done in a loop:

•

Data is continuously transmitted out of SPI-A and SCI-A ports.

The hardware multiplier is exercised.

Watchdog is reset.

ADC is performing continuous conversion.

COMP1/2 are continuously switching voltages.

GPIO17 is toggled.

(5) If a quartz crystal or ceramic resonator is used as the clock source, the HALT mode shuts down the on-chip crystal oscillator.

NOTE

The peripheral - I/O multiplexing implemented in the device prevents all available peripherals

from being used at the same time. This is because more than one peripheral function may

share an I/O pin. It is, however, possible to turn on the clocks to all the peripherals at the

same time, although such a configuration is not useful. If this is done, the current drawn by

the device will be more than the numbers specified in the current consumption tables.

20

Specifications

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SPRS523M –NOVEMBER 2008–REVISED JANUARY 2019

5.5.1 Reducing Current Consumption

The 2802x/280200 devices incorporate a method to reduce the device current consumption. Because

each peripheral unit has an individual clock-enable bit, significant reduction in current consumption can be

achieved by turning off the clock to any peripheral module that is not used in a given application.

Furthermore, any one of the three low-power modes could be taken advantage of to reduce the current

consumption even further. Table 5-4 indicates the typical reduction in current consumption achieved by

turning off the clocks.

Table 5-4. Typical Current Consumption by Various

Peripherals (at 60 MHz)⁽¹⁾

PERIPHERAL

MODULE⁽²⁾

I_DDCURRENT

REDUCTION (mA)

ADC

2⁽³⁾

I2C

ePWM

3

2

eCAP

2

SCI

2

SPI

2

COMP/DAC

HRPWM

1

3

CPU-TIMER

Internal zero-pin oscillator

1

0.5

(1) All peripheral clocks (except CPU Timer clocks) are disabled upon

reset. Writing to/reading from peripheral registers is possible only

after the peripheral clocks are turned on.

(2) For peripherals with multiple instances, the current quoted is per

module. For example, the 2 mA value quoted for ePWM is for one

ePWM module.

(3) This number represents the current drawn by the digital portion of

the ADC module. Turning off the clock to the ADC module results in

the elimination of the current drawn by the analog portion of the ADC

(I_DDA) as well.

NOTE

I_DDIOcurrent consumption is reduced by 15 mA (typical) when XCLKOUT is turned off.

NOTE

The baseline I_DDcurrent (current when the core is executing a dummy loop with no

peripherals enabled) is 45 mA, typical. To arrive at the I_DDcurrent for a given application, the

current-drawn by the peripherals (enabled by that application) must be added to the baseline

I_DDcurrent.

Following are other methods to reduce power consumption further:

•

The flash module may be powered down if code is run off SARAM. This results in a current reduction

of 18 mA (typical) in the V_DDrail and 13 mA (typical) in the V_DDIOrail.

•

Savings in I_DDIOmay be realized by disabling the pullups on pins that assume an output function.

Specifications

21

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5.5.2 Current Consumption Graphs (VREG Enabled)

Operational Current vs Frequency

100

90

80

70

60

50

40

30

20

10

0

10

15

20

25

30

35

40

45

50

55

60

SYSCLKOUT (MHz)

IDDIO (mA)

IDDA

Figure 5-1. Typical Operational Current Versus Frequency (F2802x/F280200)

Operational Power vs Frequency

450

400

350

300

250

200

10

15

20

25

30

35

40

45

50

55

60

SYSCLKOUT (MHz)

Figure 5-2. Typical Operational Power Versus Frequency (F2802x/F280200)

22

Specifications

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5.6 Electrical Characteristics⁽¹⁾

over recommended operating conditions (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

2.4

TYP

MAX UNIT

I_OH= I_OHMAX

I_OH= 50 μA

V_OH

V_OL

High-level output voltage

Low-level output voltage

V

V_DDIO– 0.2

I_OL= I_OLMAX

0.4

–205

–360

V

All GPIO

XRS pin

–80

–140

–290

Pin with pullup

V_DDIO= 3.3 V, V_IN= 0 V

enabled

Input current

(low level)

–225

I_IL

μA

Pin with pulldown

enabled

V_DDIO= 3.3 V, V_IN= 0 V

V_DDIO= 3.3 V, V_IN= V_DDIO

V_O= V_DDIOor 0 V

±2

80

Pin with pullup

enabled

Input current

(high level)

I_IH

μA

Pin with pulldown

enabled

28

50

Output current, pullup or

pulldown disabled

I_OZ

C_I

±2 μA

Input capacitance

2

2.65

35

pF

V_DDIOBOR trip point

V_DDIOBOR hysteresis

Falling V_DDIO

2.42

400

3.135

V

mV

Supervisor reset release delay

time

Time after BOR/POR/OVR event is removed to XRS

release

800 μs

VREG V_DDoutput

Internal VREG on

1.9

V

(1) When the on-chip VREG is used, its output is monitored by the POR/BOR circuit, which will reset the device should the core voltage

(V_DD) go out of range.

Specifications

23

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5.7 Thermal Resistance Characteristics

5.7.1 PT Package

°C/W⁽¹⁾

13.6

30.6

64

AIR FLOW (lfm)⁽²⁾

RΘ_JC

RΘ_JB

Junction-to-case thermal resistance

Junction-to-board thermal resistance

N/A

0

50.4

48.2

45

150

250

500

0

RΘ_JA

(High k PCB)

Junction-to-free air thermal resistance

Junction-to-package top

0.56

0.94

1.1

150

250

500

0

Psi_JT

1.38

30.1

28.7

28.4

28

150

250

500

Psi_JB

Junction-to-board

(1) These values are based on a JEDEC defined 2S2P system (with the exception of the Theta JC [RΘ_JC] value, which is based on a

JEDEC defined 1S0P system) and will change based on environment as well as application. For more information, see these

EIA/JEDEC standards:

•

JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air)

JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages

JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages

JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements

(2) lfm = linear feet per minute

5.7.2 DA Package

°C/W⁽¹⁾

12.8

33

AIR FLOW (lfm)⁽²⁾

RΘ_JC

RΘ_JB

Junction-to-case thermal resistance

N/A

0

Junction-to-board thermal resistance

Junction-to-free air thermal resistance

70.1

56.4

53.9

50.2

0.34

0.61

0.74

0.98

32.5

32.1

31.7

31.1

150

250

500

0

RΘ_JA

(High k PCB)

150

250

500

0

Psi_JT

Junction-to-package top

Junction-to-board

150

250

500

Psi_JB

(1) These values are based on a JEDEC defined 2S2P system (with the exception of the Theta JC [RΘ_JC] value, which is based on a

JEDEC defined 1S0P system) and will change based on environment as well as application. For more information, see these

EIA/JEDEC standards:

•

JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air)

JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages

JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages

JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements

(2) lfm = linear feet per minute

24

Specifications

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5.8 Thermal Design Considerations

Based on the end application design and operational profile, the I_DDand I_DDIOcurrents could vary.

Systems that exceed the recommended maximum power dissipation in the end product may require

additional thermal enhancements. Ambient temperature (T_A) varies with the end application and product

design. The critical factor that affects reliability and functionality is T_J, the junction temperature, not the

ambient temperature. Hence, care should be taken to keep T_Jwithin the specified limits. T_caseshould be

measured to estimate the operating junction temperature T_J. T_caseis normally measured at the center of

the package top-side surface. The thermal application report Semiconductor and IC Package Thermal

Metrics helps to understand the thermal metrics and definitions.

5.9 Emulator Connection Without Signal Buffering for the MCU

Figure 5-3 shows the connection between the MCU and JTAG header for a single-processor configuration.

If the distance between the JTAG header and the MCU is greater than 6 inches, the emulation signals

must be buffered. If the distance is less than 6 inches, buffering is typically not needed. Figure 5-3 shows

the simpler, no-buffering situation. For the pullup/pulldown resistor values, see Section 4.2, Signal

Descriptions.

6 inches or less

V_DDIO

13

14

2

5

EMU0

EMU1

TRST

TMS

PD

4

6

8

TRST

TMS

TDI

GND

1

GND

3

TDI

7

10

12

TDO

TCK

TDO

11

9

TCK

TCK_RET

MCU

JTAG Header

A. See Figure 6-39 for JTAG/GPIO multiplexing.

Figure 5-3. Emulator Connection Without Signal Buffering for the MCU

NOTE

The 2802x devices do not have EMU0/EMU1 pins. For designs that have a JTAG Header

onboard, the EMU0/EMU1 pins on the header must be tied to V_DDIOthrough a 4.7-kΩ

(typical) resistor.

Specifications

25

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5.10 Parameter Information

5.10.1 Timing Parameter Symbology

Timing parameter symbols used are created in accordance with JEDEC Standard 100. To shorten the

symbols, some of the pin names and other related terminology have been abbreviated as follows:

Lowercase subscripts and their

meanings:

Letters and symbols and their

meanings:

a

c

d

access time

H

L

High

Low

cycle time (period)

delay time

V

Valid

Unknown, changing, or don't care

level

f

fall time

X

Z

h

r

hold time

High impedance

rise time

su

t

setup time

transition time

valid time

v

w

pulse duration (width)

5.10.2 General Notes on Timing Parameters

All output signals from the 28x devices (including XCLKOUT) are derived from an internal clock such that

all output transitions for a given half-cycle occur with a minimum of skewing relative to each other.

The signal combinations shown in the following timing diagrams may not necessarily represent actual

cycles. For actual cycle examples, see the appropriate cycle description section of this document.

5.11 Test Load Circuit

This test load circuit is used to measure all switching characteristics provided in this document.

Tester Pin Electronics

Data Sheet Timing Reference Point

W

3.5 nH

Output

Under

Test

42

Transmission Line

(A)

Z0 = 50 W

Device Pin^(B)

4.0 pF

1.85 pF

A. Input requirements in this data sheet are tested with an input slew rate of < 4 Volts per nanosecond (4 V/ns) at the

device pin.

B. The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its

transmission line effects must be taken into account. A transmission line with a delay of 2 ns or longer can be used to

produce the desired transmission line effect. The transmission line is intended as a load only. It is not necessary to

add or subtract the transmission line delay (2 ns or longer) from the data sheet timing.

Figure 5-4. 3.3-V Test Load Circuit

26

Specifications

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5.12 Power Sequencing

There is no power sequencing requirement needed to ensure the device is in the proper state after reset

or to prevent the I/Os from glitching during power up/down (GPIO19, GPIO34–38 do not have glitch-free

I/Os). No voltage larger than a diode drop (0.7 V) above V_DDIOshould be applied to any digital pin (for

analog pins, this value is 0.7 V above V_DDA) before powering up the device. Voltages applied to pins on an

unpowered device can bias internal p-n junctions in unintended ways and produce unpredictable results.

V_DDIO, V_DDA

(3.3 V)

V_DD(1.8 V)

INTOSC1

t_INTOSCST

X1/X2

t_OSCST

(B)

(A)

XCLKOUT

User-code dependent

t

w(RSL1)

XRS^(D)

Address/data valid, internal boot-ROM code execution phase

Address/Data/

Control

(Internal)

User-code execution phase

User-code dependent

t

d(EX)

(C)

h(boot-mode)

t

Boot-Mode

Pins

GPIO pins as input

Peripheral/GPIO function

Boot-ROM execution starts

(E)

Based on boot code

GPIO pins as input (state depends on internal PU/PD)

I/O Pins

User-code dependent

A. Upon power up, SYSCLKOUT is OSCCLK/4. Because the XCLKOUTDIV bits in the XCLK register come up with a

reset state of 0, SYSCLKOUT is further divided by 4 before it appears at XCLKOUT. XCLKOUT = OSCCLK/16 during

this phase.

B. Boot ROM configures the DIVSEL bits for /1 operation. XCLKOUT = OSCCLK/4 during this phase. XCLKOUT will not

be visible at the pin until explicitly configured by user code.

C. After reset, the boot ROM code samples Boot Mode pins. Based on the status of the Boot Mode pin, the boot code

branches to destination memory or boot code function. If boot ROM code executes after power-on conditions (in

debugger environment), the boot code execution time is based on the current SYSCLKOUT speed. The SYSCLKOUT

will be based on user environment and could be with or without PLL enabled.

D. Using the XRS pin is optional due to the on-chip power-on reset (POR) circuitry.

E. The internal pullup/pulldown will take effect when BOR is driven high.

Figure 5-5. Power-on Reset

Specifications

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Table 5-5. Reset (XRS) Timing Requirements

MIN

1000t_c(SCO)

32t_c(OSCCLK)

MAX

UNIT

cycles

t_h(boot-mode)

t_w(RSL2)

Hold time for boot-mode pins

Pulse duration, XRS low on warm reset

Table 5-6. Reset (XRS) Switching Characteristics

over recommended operating conditions (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

UNIT

t_w(RSL1)

Pulse duration, XRS driven by device

600

μs

Pulse duration, reset pulse generated by

watchdog

t_w(WDRS)

512t_c(OSCCLK)

cycles

t_d(EX)

Delay time, address/data valid after XRS high

Start-up time, internal zero-pin oscillator

On-chip crystal-oscillator start-up time

32t_c(OSCCLK)

cycles

μs

t_INTOSCST

3

(1)

t_OSCST

1

10

ms

(1) Dependent on crystal/resonator and board design.

INTOSC1

X1/X2

XCLKOUT

User-Code Dependent

t

w(RSL2)

XRS

User-Code Execution Phase

t

d(EX)

Address/Data/

User-Code Execution

Control

(Internal)

(A)

t

Boot-ROM Execution Starts

GPIO Pins as Input

h(boot-mode)

Boot-Mode

Pins

Peripheral/GPIO Function

User-Code Dependent

Peripheral/GPIO Function

User-Code Execution Starts

I/O Pins

GPIO Pins as Input (State Depends on Internal PU/PD)

User-Code Dependent

A. After reset, the Boot ROM code samples BOOT Mode pins. Based on the status of the Boot Mode pin, the boot code

branches to destination memory or boot code function. If Boot ROM code executes after power-on conditions (in

debugger environment), the Boot code execution time is based on the current SYSCLKOUT speed. The

SYSCLKOUT will be based on user environment and could be with or without PLL enabled.

Figure 5-6. Warm Reset

28

Specifications

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Figure 5-7 shows an example for the effect of writing into PLLCR register. In the first phase, PLLCR =

0x0004 and SYSCLKOUT = OSCCLK x 2. The PLLCR is then written with 0x0008. Right after the PLLCR

register is written, the PLL lock-up phase begins. During this phase, SYSCLKOUT = OSCCLK/2. After the

PLL lock-up is complete, SYSCLKOUT reflects the new operating frequency, OSCCLK x 4.

OSCCLK

Write to PLLCR

SYSCLKOUT

OSCCLK * 2

OSCCLK/2

OSCCLK * 4

(CPU frequency while PLL is stabilizing

with the desired frequency. This period

(PLL lock-up time t_p) is 1 ms long.)

(Current CPU

Frequency)

(Changed CPU frequency)

Figure 5-7. Example of Effect of Writing Into PLLCR Register

Specifications

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5.13 Clock Specifications

5.13.1 Device Clock Table

This section provides the timing requirements and switching characteristics for the various clock options

available on the 2802x MCUs. Table 5-7, Table 5-8, and Table 5-9 list the cycle times of various clocks.

Table 5-7. 2802x Clock Table and Nomenclature (40-MHz Devices)

MIN

25

2

NOM

MAX UNIT

t_c(SCO), Cycle time

Frequency

500

40

ns

MHz

ns

SYSCLKOUT

LSPCLK⁽¹⁾

ADC clock

t_c(LCO), Cycle time

Frequency

25

100⁽²⁾

10⁽²⁾

40

MHz

ns

t_c(ADCCLK), Cycle time

Frequency

25

MHz

(1) Lower LSPCLK will reduce device power consumption.

(2) This is the default reset value if SYSCLKOUT = 40 MHz.

Table 5-8. 2802x Clock Table and Nomenclature (50-MHz Devices)

MIN

20

2

NOM

MAX UNIT

t_c(SCO), Cycle time

Frequency

500

50

ns

MHz

ns

SYSCLKOUT

LSPCLK⁽¹⁾

ADC clock

t_c(LCO), Cycle time

Frequency

20

80⁽²⁾

12.5⁽²⁾

50

MHz

ns

t_c(ADCCLK), Cycle time

Frequency

20

MHz

(1) Lower LSPCLK will reduce device power consumption.

(2) This is the default reset value if SYSCLKOUT = 50 MHz.

Table 5-9. 2802x Clock Table and Nomenclature (60-MHz Devices)

MIN

16.67

2

NOM

MAX UNIT

t_c(SCO), Cycle time

Frequency

500

60

ns

MHz

ns

SYSCLKOUT

LSPCLK⁽¹⁾

ADC clock

t_c(LCO), Cycle time

Frequency

16.67

66.67⁽²⁾

15⁽²⁾

60

MHz

ns

t_c(ADCCLK), Cycle time

Frequency

16.67

MHz

(1) Lower LSPCLK will reduce device power consumption.

(2) This is the default reset value if SYSCLKOUT = 60 MHz.

30

Specifications

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Table 5-10. Device Clocking Requirements/Characteristics

MIN

50

NOM

MAX UNIT

t_c(OSC), Cycle time

Frequency

200

20

ns

MHz

ns

On-chip oscillator (X1/X2 pins)

(Crystal/Resonator)

5

33.3

5

t_c(CI), Cycle time (C8)

Frequency

200

30

External oscillator/clock source

(XCLKIN pin) — PLL Enabled

MHz

ns

t_c(CI), Cycle time (C8)

Frequency

33.33

4

250

30

External oscillator/clock source

(XCLKIN pin) — PLL Disabled

MHz

Limp mode SYSCLKOUT

(with /2 enabled)

Frequency range

1 to 5

MHz

t_c(XCO), Cycle time (C1)

66.67

0.5

2000

15

ns

MHz

ms

XCLKOUT

Frequency

t_p

PLL lock time⁽¹⁾

1

(1) The PLLLOCKPRD register must be updated based on the number of OSCCLK cycles. If the zero-pin internal oscillators (10 MHz) are

used as the clock source, then the PLLLOCKPRD register must be written with a value of 10,000 (minimum).

Specifications

31

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Table 5-11. Internal Zero-Pin Oscillator (INTOSC1/INTOSC2) Characteristics

PARAMETER

Internal zero-pin oscillator 1 (INTOSC1)⁽¹⁾⁽²⁾

Internal zero-pin oscillator 2 (INTOSC2)⁽¹⁾⁽²⁾

MIN

TYP

10

MAX

UNIT

MHz

kHz

Frequency

10

Step size (coarse trim)

55

Step size (fine trim)

14

kHz

Temperature drift⁽³⁾

Voltage (V_DD) drift⁽³⁾

3.03

175

4.85 kHz/°C

Hz/mV

(1) Oscillator frequency will vary over temperature, see Figure 5-8. To compensate for oscillator temperature drift, see the Oscillator

Compensation Guide and C2000Ware.

(2) Frequency range ensured only when VREG is enabled, VREGENZ = V_SS

.

(3) Output frequency of the internal oscillators follows the direction of both the temperature gradient and voltage (V_DD) gradient. For

example:

•

Increase in temperature will cause the output frequency to increase per the temperature coefficient.

Decrease in voltage (V_DD) will cause the output frequency to decrease per the voltage coefficient.

Zero-Pin Oscillator Frequency Movement With Temperature

10.6

10.5

10.4

10.3

10.2

10.1

10

9.9

9.8

9.7

9.6

–40

–30

–20

–10

0

10

20

30

40

50

60

70

80

90

100

110

120

Typical

Max

Temperature (°C)

Figure 5-8. Zero-Pin Oscillator Frequency Movement With Temperature

32

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5.13.2 Clock Requirements and Characteristics

Table 5-12. XCLKIN Timing Requirements – PLL Enabled

NO.

C9

MIN

MAX

6

UNIT

ns

t_f(CI)

Fall time, XCLKIN

C10

C11

C12

t_r(CI)

Rise time, XCLKIN

6

ns

t_w(CIL)

t_w(CIH)

Pulse duration, XCLKIN low as a percentage of t_c(OSCCLK)

Pulse duration, XCLKIN high as a percentage of t_c(OSCCLK)

45%

55%

Table 5-13. XCLKIN Timing Requirements – PLL Disabled

NO.

MIN

MAX

UNIT

Up to 20 MHz

6

2

6

2

C9

t_f(Cl)

Fall time, XCLKIN

20 MHz to 30 MHz

ns

Up to 20 MHz

C10

t_r(CI)

Rise time, XCLKIN

20 MHz to 30 MHz

ns

Pulse duration, XCLKIN low as a percentage of

t_c(OSCCLK)

C11

C12

t_w(CIL)

t_w(CIH)

45%

55%

Pulse duration, XCLKIN high as a percentage of

t_c(OSCCLK)

The possible configuration modes are shown in Table 6-16.

Table 5-14. XCLKOUT Switching Characteristics (PLL Bypassed or Enabled)^{(1) (2)}

over recommended operating conditions (unless otherwise noted)

NO.

C3

C4

C5

C6

PARAMETER

MIN

MAX

11

UNIT

ns

t_f(XCO)

Fall time, XCLKOUT

Rise time, XCLKOUT

t_r(XCO)

11

ns

t_w(XCOL)

t_w(XCOH)

Pulse duration, XCLKOUT low

Pulse duration, XCLKOUT high

H – 2

H + 2

ns

(1) A load of 40 pF is assumed for these parameters.

(2) H = 0.5t_c(XCO)

C10

C9

C8

(A)

XCLKIN

C6

C3

C1

C4

C5

(B)

XCLKOUT

A. The relationship of XCLKIN to XCLKOUT depends on the divide factor chosen. The waveform relationship shown is

intended to illustrate the timing parameters only and may differ based on actual configuration.

B. XCLKOUT configured to reflect SYSCLKOUT.

Figure 5-9. Clock Timing

Specifications

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5.14 Flash Timing

Table 5-15. Flash/OTP Endurance for T Temperature Material⁽¹⁾

ERASE/PROGRAM

TEMPERATURE

MIN

TYP

MAX

UNIT

N_f

Flash endurance for the array (write/erase cycles)

OTP endurance for the array (write cycles)

0°C to 105°C (ambient)

0°C to 30°C (ambient)

20000

50000

cycles

write

N_OTP

1

(1) Write/erase operations outside of the temperature ranges indicated are not specified and may affect the endurance numbers.

Table 5-16. Flash/OTP Endurance for S Temperature Material⁽¹⁾

ERASE/PROGRAM

MIN

TYP

MAX

UNIT

TEMPERATURE

0°C to 125°C (ambient)

0°C to 30°C (ambient)

N_f

Flash endurance for the array (write/erase cycles)

OTP endurance for the array (write cycles)

20000

50000

cycles

write

N_OTP

1

(1) Write/erase operations outside of the temperature ranges indicated are not specified and may affect the endurance numbers.

Table 5-17. Flash/OTP Endurance for Q Temperature Material⁽¹⁾

ERASE/PROGRAM

TEMPERATURE

MIN

TYP

MAX

UNIT

N_f

Flash endurance for the array (write/erase cycles)

OTP endurance for the array (write cycles)

–40°C to 125°C (ambient)

–40°C to 30°C (ambient)

20000

50000

cycles

write

N_OTP

1

(1) Write/erase operations outside of the temperature ranges indicated are not specified and may affect the endurance numbers.

Table 5-18. Flash Parameters at 60-MHz SYSCLKOUT

TEST

CONDITIONS

PARAMETER

MIN

TYP

MAX UNIT

(1)

I_DDP

I_DDIOP

V_DDcurrent consumption during Erase/Program cycle

V_DDIOcurrent consumption during Erase/Program cycle

VREG disabled

80

60

mA

(1)

I_DDIOP

VREG enabled

120

(1) Typical parameters as seen at room temperature including function call overhead, with all peripherals off. It is important to maintain a

stable power supply during the entire flash programming process. It is conceivable that device current consumption during flash

programming could be higher than normal operating conditions. The power supply used should ensure V_MINon the supply rails at all

times, as specified in the Recommended Operating Conditions of the data sheet. Any brown-out or interruption to power during

erasing/programming could potentially corrupt the password locations and lock the device permanently. Powering a target board (during

flash programming) through the USB port is not recommended, as the port may be unable to respond to the power demands placed

during the programming process.

Table 5-19. Flash Parameters at 50-MHz SYSCLKOUT

TEST

CONDITIONS

PARAMETER

MIN

TYP

MAX UNIT

(1)

I_DDP

I_DDIOP

V_DDcurrent consumption during Erase/Program cycle

V_DDIOcurrent consumption during Erase/Program cycle

VREG disabled

70

60

mA

(1)

I_DDIOP

VREG enabled

110

(1) Typical parameters as seen at room temperature including function call overhead, with all peripherals off. It is important to maintain a

stable power supply during the entire flash programming process. It is conceivable that device current consumption during flash

programming could be higher than normal operating conditions. The power supply used should ensure V_MINon the supply rails at all

times, as specified in the Recommended Operating Conditions of the data sheet. Any brown-out or interruption to power during

erasing/programming could potentially corrupt the password locations and lock the device permanently. Powering a target board (during

flash programming) through the USB port is not recommended, as the port may be unable to respond to the power demands placed

during the programming process.

34

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Table 5-20. Flash Parameters at 40-MHz SYSCLKOUT

TEST

CONDITIONS

PARAMETER

MIN

TYP

MAX UNIT

(1)

I_DDP

V_DDcurrent consumption during Erase/Program cycle

V_DDIOcurrent consumption during Erase/Program cycle

VREG disabled

60

mA

(1)

I_DDIOP

(1)

I_DDIOP

VREG enabled

100

(1) Typical parameters as seen at room temperature including function call overhead, with all peripherals off. It is important to maintain a

stable power supply during the entire flash programming process. It is conceivable that device current consumption during flash

programming could be higher than normal operating conditions. The power supply used should ensure V_MINon the supply rails at all

times, as specified in the Recommended Operating Conditions of the data sheet. Any brown-out or interruption to power during

erasing/programming could potentially corrupt the password locations and lock the device permanently. Powering a target board (during

flash programming) through the USB port is not recommended, as the port may be unable to respond to the power demands placed

during the programming process.

Table 5-21. Flash Program/Erase Time

TEST

CONDITIONS

PARAMETER

MIN

TYP

MAX UNIT

Program Time

Erase Time⁽¹⁾

8K Sector

4K Sector

16-Bit Word

8K Sector

4K Sector

250

125

50

2

ms

μs

s

2

s

(1) The on-chip flash memory is in an erased state when the device is shipped from TI. As such, erasing the flash memory is not required

prior to programming, when programming the device for the first time. However, the erase operation is needed on all subsequent

programming operations.

Table 5-22. Flash/OTP Access Timing

PARAMETER

MIN

40

MAX UNIT

t_a(fp)

Paged Flash access time

Random Flash access time

OTP access time

ns

t_a(fr)

40

t_a(OTP)

60

Table 5-23. Flash Data Retention Duration

PARAMETER

Data retention duration

TEST CONDITIONS

T_J= 55°C

MIN

15

MAX UNIT

t_retention

years

Specifications

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Table 5-24. Minimum Required Flash/OTP Wait States at Different Frequencies

SYSCLKOUT

(MHz)

SYSCLKOUT

(ns)

PAGE

RANDOM

OTP

WAIT STATE

WAIT STATE⁽¹⁾

60

55

50

45

40

35

30

25

16.67

18.18

20

2

1

0

2

1

3

2

1

22.22

25

28.57

33.33

40

(1) Random wait state must be ≥ 1.

The equations to compute the Flash page wait state and random wait state in Table 5-24 are as follows:

é

ê

ë

ù

æ

ç

è

ö

÷

ø

t_{a(f ·p)}

Flash Page Wait State =

-1 round up to the next highest integer

ú

t_c(SCO)

ê

ú

û

é

ê

ë

ù

æ

ç

è

ö

÷

ø

t_{a(f ×r)}

Flash Random Wait State =

-1 round up to the next highest integer, or 1, whichever is larger

ú

t_c(SCO)

ê

ú

û

The equation to compute the OTP wait state in Table 5-24 is as follows:

é

ê

ë

ù

æ

ç

è

ö

÷

ø

t_a(OTP)

OTP Wait State =

-1 round up to the next highest integer, or 1, whichever is larger

ú

t_c(SCO)

ê

ú

û

36

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6 Detailed Description

6.1 Overview

6.1.1 CPU

The 2802x (C28x) family is a member of the TMS320C2000™ microcontroller (MCU) platform. The C28x-

based controllers have the same 32-bit fixed-point architecture as existing C28x MCUs. It is a very

efficient C/C++ engine, enabling users to develop not only their system control software in a high-level

language, but also enabling development of math algorithms using C/C++. The device is as efficient at

MCU math tasks as it is at system control tasks that typically are handled by microcontroller devices. This

efficiency removes the need for a second processor in many systems. The 32 × 32-bit MAC 64-bit

processing capabilities enable the controller to handle higher numerical resolution problems efficiently.

Add to this the fast interrupt response with automatic context save of critical registers, resulting in a device

that is capable of servicing many asynchronous events with minimal latency. The device has an 8-level-

deep protected pipeline with pipelined memory accesses. This pipelining enables it to execute at high

speeds without resorting to expensive high-speed memories. Special branch-look-ahead hardware

minimizes the latency for conditional discontinuities. Special store conditional operations further improve

performance.

6.1.2 Memory Bus (Harvard Bus Architecture)

As with many MCU-type devices, multiple buses are used to move data between the memories and

peripherals and the CPU. The memory bus architecture contains a program read bus, data read bus, and

data write bus. The program read bus consists of 22 address lines and 32 data lines. The data read and

write buses consist of 32 address lines and 32 data lines each. The 32-bit-wide data buses enable single

cycle 32-bit operations. The multiple bus architecture, commonly termed Harvard Bus, enables the C28x

to fetch an instruction, read a data value and write a data value in a single cycle. All peripherals and

memories attached to the memory bus prioritize memory accesses. Generally, the priority of memory bus

accesses can be summarized as follows:

Highest:

Data Writes

(Simultaneous data and program writes cannot occur on the

memory bus.)

Program Writes

(Simultaneous data and program writes cannot occur on the

memory bus.)

Data Reads

Program Reads

(Simultaneous program reads and fetches cannot occur on the

memory bus.)

Lowest:

Fetches

(Simultaneous program reads and fetches cannot occur on the

memory bus.)

6.1.3 Peripheral Bus

To enable migration of peripherals between various Texas Instruments (TI) MCU family of devices, the

devices adopt a peripheral bus standard for peripheral interconnect. The peripheral bus bridge multiplexes

the various buses that make up the processor Memory Bus into a single bus consisting of 16 address

lines and 16 or 32 data lines and associated control signals. Three versions of the peripheral bus are

supported. One version supports only 16-bit accesses (called peripheral frame 2). Another version

supports both 16- and 32-bit accesses (called peripheral frame 1).

Detailed Description

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6.1.4 Real-Time JTAG and Analysis

(1)

The devices implement the standard IEEE 1149.1 JTAG

interface for in-circuit based debug.

Additionally, the devices support real-time mode of operation allowing modification of the contents of

memory, peripheral, and register locations while the processor is running and executing code and

servicing interrupts. The user can also single step through non-time-critical code while enabling time-

critical interrupts to be serviced without interference. The device implements the real-time mode in

hardware within the CPU. This is a feature unique to the 28x family of devices, requiring no software

monitor. Additionally, special analysis hardware is provided that allows setting of hardware breakpoint or

data/address watch-points and generating various user-selectable break events when a match occurs.

These devices do not support boundary scan; however, IDCODE and BYPASS features are available if

the following considerations are taken into account. The IDCODE does not come by default. The user

must go through a sequence of SHIFT IR and SHIFT DR state of JTAG to get the IDCODE. For BYPASS

instruction, the first shifted DR value would be 1.

6.1.5 Flash

The F280200 device contains 8K × 16 of embedded flash memory, segregated into two 4K × 16 sectors.

The F28021/23/27 devices contain 32K × 16 of embedded flash memory, segregated into four 8K × 16

sectors. The F28020/22/26 devices contain 16K × 16 of embedded flash memory, segregated into four

4K × 16 sectors. All devices also contain a single 1K × 16 of OTP memory at address range 0x3D 7800 to

0x3D 7BFF. The user can individually erase, program, and validate a flash sector while leaving other

sectors untouched. However, it is not possible to use one sector of the flash or the OTP to execute flash

algorithms that erase/program other sectors. Special memory pipelining is provided to enable the flash

module to achieve higher performance. The flash/OTP is mapped to both program and data space;

therefore, it can be used to execute code or store data information. Addresses 0x3F 7FF0 to 0x3F 7FF5

are reserved for data variables and should not contain program code.

NOTE

The Flash and OTP wait states can be configured by the application. This allows applications

running at slower frequencies to configure the flash to use fewer wait states.

Flash effective performance can be improved by enabling the flash pipeline mode in the

Flash options register. With this mode enabled, effective performance of linear code

execution will be much faster than the raw performance indicated by the wait-state

configuration alone. The exact performance gain when using the Flash pipeline mode is

application-dependent.

For more information on the Flash options, Flash wait state, and OTP wait-state registers,

see the System Control chapter in the TMS320F2802x,TMS320F2802xx Piccolo Technical

Reference Manual.

6.1.6 M0, M1 SARAMs

All devices contain these two blocks of single access memory, each 1K × 16 in size. The stack pointer

points to the beginning of block M1 on reset. The M0 and M1 blocks, like all other memory blocks on C28x

devices, are mapped to both program and data space. Hence, the user can use M0 and M1 to execute

code or for data variables. The partitioning is performed within the linker. The C28x device presents a

unified memory map to the programmer. This makes for easier programming in high-level languages.

6.1.7 L0 SARAM

The device contains up to 4K × 16 of single-access RAM. Refer to the device-specific memory map

figures in Section 6.2 to ascertain the exact size for a given device. This block is mapped to both program

and data space.

(1) IEEE Standard 1149.1-1990 Standard Test Access Port and Boundary Scan Architecture

38

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6.1.8 Boot ROM

The Boot ROM is factory-programmed with bootloader software. The Boot ROM uses the boot-mode-

select GPIO pins to determine what boot mode to use upon power up. The user can select to boot

normally to application code, to download new software from an external connection, or to select boot

software that is programmed in the internal Flash/ROM. The Boot ROM also contains standard tables,

such as SIN/COS waveforms, for use in math-related algorithms. The boot-ROM content, and hence the

checksum value, may vary for different silicon revisions. For details, see the Boot ROM chapter in the

TMS320F2802x,TMS320F2802xx Piccolo Technical Reference Manual.

Table 6-1. Boot Mode Selection

MODE

GPIO37/TDO

GPIO34/COMP2OUT

TRST

MODE

3

2

1

0

x

1

0

1

0

x

0

1

GetMode

Wait (see Section 6.1.9 for description)

1

SCI

0

Parallel IO

Emulation Boot

EMU

6.1.8.1 Emulation Boot

When the emulator is connected, the GPIO37/TDO pin cannot be used for boot mode selection. In this

case, the boot ROM detects that an emulator is connected and uses the contents of two reserved SARAM

locations in the PIE vector table to determine the boot mode. If the content of either location is invalid,

then the Wait boot option is used. All boot mode options can be accessed in emulation boot.

6.1.8.2 GetMode

The default behavior of the GetMode option is to boot to flash. This behavior can be changed to another

boot option by programming two locations in the OTP. If the content of either OTP location is invalid, then

boot to flash is used. One of the following loaders can be specified: SCI, SPI, I2C, or OTP.

6.1.8.3 Peripheral Pins Used by the Bootloader

Table 6-2 shows which GPIO pins are used by each peripheral bootloader. Refer to the GPIO mux table

to see if these conflict with any of the peripherals you would like to use in your application.

Table 6-2. Peripheral Bootload Pins

BOOTLOADER

PERIPHERAL LOADER PINS

SCIRXDA (GPIO28)

SCI

SCITXDA (GPIO29)

Parallel Boot

SPI

Data (GPIO[7:0])

28x Control (GPIO16)

Host Control (GPIO12)

SPISIMOA (GPIO16)

SPISOMIA (GPIO17)

SPICLKA (GPIO18)

SPISTEA (GPIO19)

I2C

SDAA (GPIO32)⁽¹⁾

SCLA (GPIO33)⁽¹⁾

(1) GPIO pins 32 and 33 may not be available on your device package. On these devices, this bootload

option is unavailable.

Detailed Description

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6.1.9 Security

The devices support high levels of security to protect the user firmware from being reverse engineered.

The security features a 128-bit password (hardcoded for 16 wait states), which the user programs into the

flash. One code security module (CSM) is used to protect the flash/OTP and the L0/L1 SARAM blocks.

The security feature prevents unauthorized users from examining the memory contents through the JTAG

port, executing code from external memory or trying to boot-load some undesirable software that would

export the secure memory contents. To enable access to the secure blocks, the user must write the

correct 128-bit KEY value that matches the value stored in the password locations within the Flash.

In addition to the CSM, the emulation code security logic (ECSL) has been implemented to prevent

unauthorized users from stepping through secure code. Any code or data access to flash, user OTP, or L0

memory while the emulator is connected will trip the ECSL and break the emulation connection. To allow

emulation of secure code, while maintaining the CSM protection against secure memory reads, the user

must write the correct value into the lower 64 bits of the KEY register, which matches the value stored in

the lower 64 bits of the password locations within the flash. Dummy reads of all 128 bits of the password

in the flash must still be performed. If the lower 64 bits of the password locations are all ones

(unprogrammed), then the KEY value does not need to match.

When initially debugging a device with the password locations in flash programmed (that is, secured), the

CPU will start running and may execute an instruction that performs an access to a protected ECSL area.

If this happens, the ECSL will trip and cause the emulator connection to be cut.

The solution is to use the Wait boot option. This will sit in a loop around a software breakpoint to allow an

emulator to be connected without tripping security. The user can then exit this mode once the emulator is

connected by using one of the emulation boot options as described in the Boot ROM chapter in the

TMS320F2802x,TMS320F2802xx Piccolo Technical Reference Manual. Piccolo devices do not support a

hardware wait-in-reset mode.

NOTE

•

When the code-security passwords are programmed, all addresses from 0x3F7F80 to

0x3F7FF5 cannot be used as program code or data. These locations must be

programmed to 0x0000.

If the code security feature is not used, addresses 0x3F7F80 to 0x3F7FEF may be used

for code or data. Addresses 0x3F7FF0 to 0x3F7FF5 are reserved for data and should not

contain program code.

The 128-bit password (at 0x3F 7FF8 to 0x3F 7FFF) must not be programmed to zeros.

Doing so would permanently lock the device.

40

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Disclaimer

Code Security Module Disclaimer

THE CODE SECURITY MODULE (CSM) INCLUDED ON THIS DEVICE WAS DESIGNED

TO PASSWORD PROTECT THE DATA STORED IN THE ASSOCIATED MEMORY

(EITHER ROM OR FLASH) AND IS WARRANTED BY TEXAS INSTRUMENTS (TI), IN

ACCORDANCE WITH ITS STANDARD TERMS AND CONDITIONS, TO CONFORM TO

TI'S PUBLISHED SPECIFICATIONS FOR THE WARRANTY PERIOD APPLICABLE FOR

THIS DEVICE.

TI DOES NOT, HOWEVER, WARRANT OR REPRESENT THAT THE CSM CANNOT BE

COMPROMISED OR BREACHED OR THAT THE DATA STORED IN THE ASSOCIATED

MEMORY CANNOT BE ACCESSED THROUGH OTHER MEANS. MOREOVER, EXCEPT

AS SET FORTH ABOVE, TI MAKES NO WARRANTIES OR REPRESENTATIONS

CONCERNING THE CSM OR OPERATION OF THIS DEVICE, INCLUDING ANY IMPLIED

WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.

IN NO EVENT SHALL TI BE LIABLE FOR ANY CONSEQUENTIAL, SPECIAL, INDIRECT,

INCIDENTAL, OR PUNITIVE DAMAGES, HOWEVER CAUSED, ARISING IN ANY WAY

OUT OF YOUR USE OF THE CSM OR THIS DEVICE, WHETHER OR NOT TI HAS BEEN

ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. EXCLUDED DAMAGES INCLUDE,

BUT ARE NOT LIMITED TO LOSS OF DATA, LOSS OF GOODWILL, LOSS OF USE OR

INTERRUPTION OF BUSINESS OR OTHER ECONOMIC LOSS.

6.1.10 Peripheral Interrupt Expansion (PIE) Block

The PIE block serves to multiplex numerous interrupt sources into a smaller set of interrupt inputs. The

PIE block can support up to 96 peripheral interrupts. On the F2802x, 33 of the possible 96 interrupts are

used by peripherals. The 96 interrupts are grouped into blocks of 8 and each group is fed into 1 of

12 CPU interrupt lines (INT1 to INT12). Each of the 96 interrupts is supported by its own vector stored in a

dedicated RAM block that can be overwritten by the user. The vector is automatically fetched by the CPU

on servicing the interrupt. It takes 8 CPU clock cycles to fetch the vector and save critical CPU registers.

Hence the CPU can quickly respond to interrupt events. Prioritization of interrupts is controlled in

hardware and software. Each individual interrupt can be enabled/disabled within the PIE block.

6.1.11 External Interrupts (XINT1–XINT3)

The devices support three masked external interrupts (XINT1–XINT3). Each of the interrupts can be

selected for negative, positive, or both negative and positive edge triggering and can also be

enabled/disabled. These interrupts also contain a 16-bit free running up counter, which is reset to zero

when a valid interrupt edge is detected. This counter can be used to accurately time stamp the interrupt.

There are no dedicated pins for the external interrupts. XINT1, XINT2, and XINT3 interrupts can accept

inputs from GPIO0–GPIO31 pins.

6.1.12 Internal Zero Pin Oscillators, Oscillator, and PLL

The device can be clocked by either of the two internal zero-pin oscillators, an external oscillator, or by a

crystal attached to the on-chip oscillator circuit (48-pin devices only). A PLL is provided supporting up to

12 input-clock-scaling ratios. The PLL ratios can be changed on-the-fly in software, enabling the user to

scale back on operating frequency if lower power operation is desired. Refer to Section 5, Electrical

Specifications, for timing details. The PLL block can be set in bypass mode.

6.1.13 Watchdog

Each device contains two watchdogs: CPU-Watchdog that monitors the core and NMI-Watchdog that is a

missing clock-detect circuit. The user software must regularly reset the CPU-watchdog counter within a

certain time frame; otherwise, the CPU-watchdog generates a reset to the processor. The CPU-watchdog

can be disabled if necessary. The NMI-Watchdog engages only in case of a clock failure and can either

generate an interrupt or a device reset.

Detailed Description

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6.1.14 Peripheral Clocking

The clocks to each individual peripheral can be enabled/disabled to reduce power consumption when a

peripheral is not in use. Additionally, the system clock to the serial ports (except I2C) can be scaled

relative to the CPU clock.

6.1.15 Low-power Modes

The devices are full static CMOS devices. Three low-power modes are provided:

IDLE:

Place CPU in low-power mode. Peripheral clocks may be turned off selectively and

only those peripherals that must function during IDLE are left operating. An enabled

interrupt from an active peripheral or the watchdog timer will wake the processor from

IDLE mode.

STANDBY: Turns off clock to CPU and peripherals. This mode leaves the oscillator and PLL

functional. An external interrupt event will wake the processor and the peripherals.

Execution begins on the next valid cycle after detection of the interrupt event

HALT:

This mode basically shuts down the device and places it in the lowest possible power

consumption mode. If the internal zero-pin oscillators are used as the clock source,

the HALT mode turns them off, by default. To keep these oscillators from shutting

down, the INTOSCnHALTI bits in CLKCTL register may be used. The zero-pin

oscillators may thus be used to clock the CPU-watchdog in this mode. If the on-chip

crystal oscillator is used as the clock source, it is shut down in this mode. A reset or

an external signal (through a GPIO pin) or the CPU-watchdog can wake the device

from this mode.

The CPU clock (OSCCLK) and WDCLK should be from the same clock source before attempting to put

the device into HALT or STANDBY.

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6.1.16 Peripheral Frames 0, 1, 2 (PFn)

The device segregates peripherals into three sections. The mapping of peripherals is as follows:

PF0: PIE:

Flash:

PIE Interrupt Enable and Control Registers Plus PIE Vector Table

Flash Waitstate Registers

Timers:

CSM:

CPU-Timers 0, 1, 2 Registers

Code Security Module KEY Registers

ADC Result Registers

ADC:

PF1: GPIO:

ePWM:

GPIO MUX Configuration and Control Registers

Enhanced Pulse Width Modulator Module and Registers

Enhanced Capture Module and Registers

eCAP:

Comparators: Comparator Modules

PF2: SYS:

SCI:

System Control Registers

Serial Communications Interface (SCI) Control and RX/TX Registers

Serial Port Interface (SPI) Control and RX/TX Registers

ADC Status, Control, and Configuration Registers

Inter-Integrated Circuit Module and Registers

External Interrupt Registers

SPI:

ADC:

I2C:

XINT:

6.1.17 General-Purpose Input/Output (GPIO) Multiplexer

Most of the peripheral signals are multiplexed with general-purpose input/output (GPIO) signals. This

enables the user to use a pin as GPIO if the peripheral signal or function is not used. On reset, GPIO pins

are configured as inputs. The user can individually program each pin for GPIO mode or peripheral signal

mode. For specific inputs, the user can also select the number of input qualification cycles. This is to filter

unwanted noise glitches. The GPIO signals can also be used to bring the device out of specific low-power

modes.

6.1.18 32-Bit CPU-Timers (0, 1, 2)

CPU-Timers 0, 1, and 2 are identical 32-bit timers with presettable periods and with 16-bit clock

prescaling. The timers have a 32-bit count-down register, which generates an interrupt when the counter

reaches zero. The counter is decremented at the CPU clock speed divided by the prescale value setting.

When the counter reaches zero, it is automatically reloaded with a 32-bit period value.

CPU-Timer 0 is for general use and is connected to the PIE block. CPU-Timer 1 is also for general use

and can be connected to INT13 of the CPU. CPU-Timer 2 is reserved for DSP/BIOS. It is connected to

INT14 of the CPU. If DSP/BIOS is not being used, CPU-Timer 2 is available for general use.

CPU-Timer 2 can be clocked by any one of the following:

•

SYSCLKOUT (default)

Internal zero-pin oscillator 1 (INTOSC1)

Internal zero-pin oscillator 2 (INTOSC2)

External clock source

Detailed Description

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6.1.19 Control Peripherals

The devices support the following peripherals that are used for embedded control and communication:

ePWM:

The enhanced PWM peripheral supports independent/complementary PWM

generation, adjustable dead-band generation for leading/trailing edges,

latched/cycle-by-cycle trip mechanism. Some of the PWM pins support the

HRPWM high resolution duty and period features. The type 1 module found on

2802x devices also supports increased dead-band resolution, enhanced SOC and

interrupt generation, and advanced triggering including trip functions based on

comparator outputs.

eCAP:

ADC:

The enhanced capture peripheral uses a 32-bit time base and registers up to four

programmable events in continuous/one-shot capture modes.

This peripheral can also be configured to generate an auxiliary PWM signal.

The ADC block is a 12-bit converter. It has up to 13 single-ended channels pinned

out, depending on the device. It contains two sample-and-hold units for

simultaneous sampling.

Comparator: Each comparator block consists of one analog comparator along with an internal

10-bit reference for supplying one input of the comparator.

6.1.20 Serial Port Peripherals

The devices support the following serial communication peripherals:

SPI:

The SPI is a high-speed, synchronous serial I/O port that allows a serial bit stream

of programmed length (1 to 16 bits) to be shifted into and out of the device at a

programmable bit-transfer rate. Normally, the SPI is used for communications

between the MCU and external peripherals or another processor. Typical

applications include external I/O or peripheral expansion through devices such as

shift registers, display drivers, and ADCs. Multidevice communications are

supported by the master/slave operation of the SPI. The SPI contains a 4-level

receive and transmit FIFO for reducing interrupt servicing overhead.

SCI:

I2C:

The serial communications interface is a two-wire asynchronous serial port,

commonly known as UART. The SCI contains a 4-level receive and transmit FIFO

for reducing interrupt servicing overhead.

The inter-integrated circuit (I2C) module provides an interface between an MCU

and other devices compliant with Philips Semiconductors Inter-IC bus ( I²C-bus^®)

specification version 2.1 and connected by way of an I²C-bus. External

components attached to this 2-wire serial bus can transmit/receive up to 8-bit data

to/from the MCU through the I2C module. The I2C contains a 4-level receive and

transmit FIFO for reducing interrupt servicing overhead.

44

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6.2 Memory Maps

In Figure 6-1, Figure 6-2, Figure 6-3, Figure 6-4, and Figure 6-5, the following apply:

•

Memory blocks are not to scale.

Peripheral Frame 0, Peripheral Frame 1 and Peripheral Frame 2 memory maps are restricted to data

memory only. A user program cannot access these memory maps in program space.

•

Protected means the order of Write-followed-by-Read operations is preserved rather than the pipeline

order.

•

Certain memory ranges are EALLOW protected against spurious writes after configuration.

Locations 0x3D7C80 to 0x3D7CC0 contain the internal oscillator and ADC calibration routines. These

locations are not programmable by the user.

Detailed Description

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Data Space

0x00 0000

Prog Space

M0 Vector RAM (Enabled if VMAP = 0)

M0 SARAM (1K ´ 16, 0-Wait)

0x00 0040

0x00 0400

0x00 0800

0x00 0D00

M1 SARAM (1K ´ 16, 0-Wait)

Peripheral Frame 0

PIE Vector - RAM

(256 ´ 16)

(Enabled if

VMAP = 1,

ENPIE = 1)

Reserved

0x00 0E00

0x00 2000

0x00 6000

Peripheral Frame 0

Reserved

Peripheral Frame 1

(4K ´ 16, Protected)

Reserved

0x00 7000

0x00 8000

Peripheral Frame 2

(4K ´ 16, Protected)

L0 SARAM (4K ´ 16)

(0-Wait, Secure Zone + ECSL, Dual Mapped)

0x00 9000

0x3D 7800

0x3D 7C00

Reserved

User OTP (1K ´ 16, Secure Zone + ECSL)

Reserved

0x3D 7C80

0x3D 7CC0

0x3D 7CE0

0x3D 7E80

Calibration Data

Get_mode function

Reserved

Calibration Data

Reserved

0x3D 7EB0

0x3D 7FFF

PARTID

0x3D 8000

0x3F 0000

Reserved

FLASH

(32K ´ 16, 4 Sectors, Secure Zone + ECSL)

0x3F 7FF8

0x3F 8000

128-Bit Password

L0 SARAM (4K ´ 16)

(0-Wait, Secure Zone + ECSL, Dual Mapped)

0x3F 9000

0x3F E000

0x3F FFC0

Reserved

Boot ROM (8K ´ 16, 0-Wait)

Vector (32 Vectors, Enabled if VMAP = 1)

A. Memory locations 0x3D 7E80–0x3D 7EAF are reserved in TMX/TMP silicon.

Figure 6-1. 28023/28027 Memory Map

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Data Space

Prog Space

0x00 0000

0x00 0040

0x00 0400

0x00 0800

0x00 0D00

M0 Vector RAM (Enabled if VMAP = 0)

M0 SARAM (1K ´ 16, 0-Wait)

M1 SARAM (1K ´ 16, 0-Wait)

Peripheral Frame 0

PIE Vector - RAM

(256 ´ 16)

(Enabled if

VMAP = 1,

ENPIE = 1)

Reserved

0x00 0E00

0x00 2000

0x00 6000

Peripheral Frame 0

Reserved

Peripheral Frame 1

(4K ´ 16, Protected)

Reserved

0x00 7000

0x00 8000

Peripheral Frame 2

(4K ´ 16, Protected)

L0 SARAM (4K ´ 16)

(0-Wait, Secure Zone + ECSL, Dual Mapped)

0x00 9000

0x3D 7800

0x3D 7C00

Reserved

User OTP (1K ´ 16, Secure Zone + ECSL)

Reserved

0x3D 7C80

0x3D 7CC0

Calibration Data

Get_mode function

Reserved

0x3D 7CE0

0x3D 7E80

Calibration Data

Reserved

0x3D 7EB0

0x3D 7FFF

PARTID

0x3D 8000

0x3F 4000

Reserved

FLASH

(16K ´ 16, 4 Sectors, Secure Zone + ECSL)

0x3F 7FF8

0x3F 8000

128-Bit Password

L0 SARAM (4K ´ 16)

(0-Wait, Secure Zone + ECSL, Dual Mapped)

0x3F 9000

0x3F E000

0x3F FFC0

Reserved

Boot ROM (8K ´ 16, 0-Wait)

Vector (32 Vectors, Enabled if VMAP = 1)

A. Memory locations 0x3D 7E80–0x3D 7EAF are reserved in TMX/TMP silicon.

Figure 6-2. 28022/28026 Memory Map

Detailed Description

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Data Space

0x00 0000

Prog Space

M0 Vector RAM (Enabled if VMAP = 0)

M0 SARAM (1K ´ 16, 0-Wait)

0x00 0040

0x00 0400

0x00 0800

0x00 0D00

M1 SARAM (1K ´ 16, 0-Wait)

Peripheral Frame 0

PIE Vector - RAM

(256 ´ 16)

(Enabled if

VMAP = 1,

ENPIE = 1)

Reserved

0x00 0E00

0x00 2000

0x00 6000

Peripheral Frame 0

Reserved

Peripheral Frame 1

(4K ´ 16, Protected)

Reserved

0x00 7000

0x00 8000

Peripheral Frame 2

(4K ´ 16, Protected)

L0 SARAM (3K ´ 16)

(0-Wait, Secure Zone + ECSL, Dual Mapped)

0x00 8C00

0x3D 7800

0x3D 7C00

Reserved

User OTP (1K ´ 16, Secure Zone + ECSL)

Reserved

0x3D 7C80

0x3D 7CC0

Calibration Data

Get_mode function

Reserved

0x3D 7CE0

0x3D 7E80

Calibration Data

Reserved

0x3D 7EB0

0x3D 7FFF

PARTID

0x3D 8000

0x3F 0000

Reserved

FLASH

(32K ´ 16, 4 Sectors, Secure Zone + ECSL)

0x3F 7FF8

0x3F 8000

128-Bit Password

L0 SARAM (3K ´ 16)

(0-Wait, Secure Zone + ECSL, Dual Mapped)

0x3F 8C00

0x3F E000

0x3F FFC0

Reserved

Boot ROM (8K ´ 16, 0-Wait)

Vector (32 Vectors, Enabled if VMAP = 1)

A. Memory locations 0x3D 7E80–0x3D 7EAF are reserved in TMX/TMP silicon.

Figure 6-3. 28021 Memory Map

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Data Space

Prog Space

0x00 0000

0x00 0040

0x00 0400

0x00 0800

0x00 0D00

M0 Vector RAM (Enabled if VMAP = 0)

M0 SARAM (1K ´ 16, 0-Wait)

M1 SARAM (1K ´ 16, 0-Wait)

Peripheral Frame 0

PIE Vector - RAM

(256 ´ 16)

(Enabled if

VMAP = 1,

ENPIE = 1)

Reserved

0x00 0E00

0x00 2000

0x00 6000

Peripheral Frame 0

Reserved

Peripheral Frame 1

(4K ´ 16, Protected)

Reserved

0x00 7000

0x00 8000

Peripheral Frame 2

(4K ´ 16, Protected)

L0 SARAM (1K ´ 16)

(0-Wait, Secure Zone + ECSL, Dual Mapped)

0x00 8400

0x3D 7800

0x3D 7C00

Reserved

User OTP (1K ´ 16, Secure Zone + ECSL)

Reserved

0x3D 7C80

0x3D 7CC0

0x3D 7CE0

0x3D 7E80

Calibration Data

Get_mode function

Reserved

Calibration Data

Reserved

0x3D 7EB0

0x3D 7FFF

PARTID

0x3D 8000

0x3F 4000

Reserved

FLASH

(16K ´ 16, 4 Sectors, Secure Zone + ECSL)

0x3F 7FF8

0x3F 8000

128-Bit Password

L0 SARAM (1K ´ 16)

(0-Wait, Secure Zone + ECSL, Dual Mapped)

0x3F 8400

0x3F E000

0x3F FFC0

Reserved

Boot ROM (8K ´ 16, 0-Wait)

Vector (32 Vectors, Enabled if VMAP = 1)

A. Memory locations 0x3D 7E80–0x3D 7EAF are reserved in TMX/TMP silicon.

Figure 6-4. 28020 Memory Map

Detailed Description

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Data Space

0x00 0000

Prog Space

M0 Vector RAM (Enabled if VMAP = 0)

M0 SARAM (1K ´ 16, 0-Wait)

0x00 0040

0x00 0400

0x00 0800

0x00 0D00

M1 SARAM (1K ´ 16, 0-Wait)

Peripheral Frame 0

PIE Vector - RAM

(256 ´ 16)

(Enabled if

VMAP = 1,

ENPIE = 1)

Reserved

0x00 0E00

0x00 2000

0x00 6000

Peripheral Frame 0

Reserved

Peripheral Frame 1

(4K ´ 16, Protected)

Reserved

0x00 7000

0x00 8000

Peripheral Frame 2

(4K ´ 16, Protected)

L0 SARAM (1K ´ 16)

(0-Wait, Secure Zone + ECSL, Dual Mapped)

0x00 8400

0x3D 7800

0x3D 7C00

Reserved

User OTP (1K ´ 16, Secure Zone + ECSL)

Reserved

0x3D 7C80

0x3D 7CC0

Calibration Data

Get_mode function

Reserved

0x3D 7CE0

0x3D 7E80

Calibration Data

Reserved

0x3D 7EB0

0x3D 7FFF

PARTID

0x3D 8000

0x3F 6000

Reserved

FLASH

(8K ´ 16, 2 Sectors, Secure Zone + ECSL)

0x3F 7FF8

0x3F 8000

128-Bit Password

L0 SARAM (1K ´ 16)

(0-Wait, Secure Zone + ECSL, Dual Mapped)

0x3F 8400

0x3F E000

0x3F FFC0

Reserved

Boot ROM (8K ´ 16, 0-Wait)

Vector (32 Vectors, Enabled if VMAP = 1)

A. Memory locations 0x3D 7E80–0x3D 7EAF are reserved in TMX/TMP silicon.

Figure 6-5. 280200 Memory Map

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Table 6-3. Addresses of Flash Sectors in F28021/28023/28027

ADDRESS RANGE

0x3F 0000 to 0x3F 1FFF

0x3F 2000 to 0x3F 3FFF

0x3F 4000 to 0x3F 5FFF

0x3F 6000 to 0x3F 7F7F

PROGRAM AND DATA SPACE

Sector D (8K × 16)

Sector C (8K × 16)

Sector B (8K × 16)

Sector A (8K × 16)

Program to 0x0000 when using the

Code Security Module

0x3F 7F80 to 0x3F 7FF5

0x3F 7FF6 to 0x3F 7FF7

0x3F 7FF8 to 0x3F 7FFF

Boot-to-Flash Entry Point

(program branch instruction here)

Security Password (128-Bit)

(Do not program to all zeros)

Table 6-4. Addresses of Flash Sectors in F28020/28022/28026

ADDRESS RANGE

0x3F 4000 to 0x3F 4FFF

0x3F 5000 to 0x3F 5FFF

0x3F 6000 to 0x3F 6FFF

0x3F 7000 to 0x3F 7F7F

PROGRAM AND DATA SPACE

Sector D (4K × 16)

Sector C (4K × 16)

Sector B (4K × 16)

Sector A (4K × 16)

Program to 0x0000 when using the

Code Security Module

0x3F 7F80 to 0x3F 7FF5

0x3F 7FF6 to 0x3F 7FF7

0x3F 7FF8 to 0x3F 7FFF

Boot-to-Flash Entry Point

(program branch instruction here)

Security Password (128-Bit)

(Do not program to all zeros)

Table 6-5. Addresses of Flash Sectors in F280200

ADDRESS RANGE

0x3F 6000 to 0x3F 6FFF

0x3F 7000 to 0x3F 7F7F

PROGRAM AND DATA SPACE

Sector B (4K × 16)

Sector A (4K × 16)

Program to 0x0000 when using the

Code Security Module

0x3F 7F80 to 0x3F 7FF5

0x3F 7FF6 to 0x3F 7FF7

0x3F 7FF8 to 0x3F 7FFF

Boot-to-Flash Entry Point

(program branch instruction here)

Security Password (128-Bit)

(Do not program to all zeros)

NOTE

•

When the code-security passwords are programmed, all addresses from 0x3F 7F80 to

0x3F 7FF5 cannot be used as program code or data. These locations must be

programmed to 0x0000.

If the code security feature is not used, addresses 0x3F 7F80 to 0x3F 7FEF may be

used for code or data. Addresses 0x3F 7FF0 to 0x3F 7FF5 are reserved for data and

should not contain program code.

Table 6-6 shows how to handle these memory locations.

Detailed Description

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Table 6-6. Impact of Using the Code Security Module

FLASH

ADDRESS

CODE SECURITY ENABLED

CODE SECURITY DISABLED

0x3F 7F80 to 0x3F 7FEF

0x3F 7FF0 to 0x3F 7FF5

Application code and data

Reserved for data only

Fill with 0x0000

Peripheral Frame 1 and Peripheral Frame 2 are grouped together to enable these blocks to be write/read

peripheral block protected. The protected mode makes sure that all accesses to these blocks happen as

written. Because of the pipeline, a write immediately followed by a read to different memory locations, will

appear in reverse order on the memory bus of the CPU. This can cause problems in certain peripheral

applications where the user expected the write to occur first (as written). The CPU supports a block

protection mode where a region of memory can be protected so that operations occur as written (the

penalty is extra cycles are added to align the operations). This mode is programmable and by default, it

protects the selected zones.

The wait states for the various spaces in the memory map area are listed in Table 6-7.

Table 6-7. Wait States

AREA

M0 and M1 SARAMs

Peripheral Frame 0

Peripheral Frame 1

WAIT STATES (CPU)

0-wait

COMMENTS

Fixed

0-wait

0-wait (writes)

2-wait (reads)

Cycles can be extended by peripheral generated ready.

Back-to-back write operations to Peripheral Frame 1 registers will incur

a 1-cycle stall (1-cycle delay).

Peripheral Frame 2

0-wait (writes)

2-wait (reads)

Fixed. Cycles cannot be extended by the peripheral.

L0 SARAM

OTP

0-wait data and program

Programmable

Assumes no CPU conflicts

Programmed through the Flash registers.

1-wait is minimum number of wait states allowed.

Programmed through the Flash registers.

1-wait minimum

Programmable

FLASH

0-wait Paged min

1-wait Random min

Random ≥ Paged

FLASH Password

Boot-ROM

16-wait fixed

0-wait

Wait states of password locations are fixed.

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6.3 Register Maps

The devices contain three peripheral register spaces. The spaces are categorized as follows:

Peripheral Frame 0: These are peripherals that are mapped directly to the CPU memory bus.

See Table 6-8.

Peripheral Frame 1: These are peripherals that are mapped to the 32-bit peripheral bus. See

Table 6-9.

Peripheral Frame 2: These are peripherals that are mapped to the 16-bit peripheral bus. See

Table 6-10.

Table 6-8. Peripheral Frame 0 Registers⁽¹⁾

NAME

Device Emulation Registers

System Power Control Registers

FLASH Registers⁽³⁾

ADDRESS RANGE

0x00 0880 to 0x00 0984

0x00 0985 to 0x00 0987

0x00 0A80 to 0x00 0ADF

0x00 0AE0 to 0x00 0AEF

0x00 0B00 to 0x00 0B0F

0x00 0C00 to 0x00 0C3F

0x00 0CE0 to 0x00 0CFF

0x00 0D00 to 0x00 0DFF

SIZE (×16)

EALLOW PROTECTED⁽²⁾

261

3

Yes

No

96

16

64

32

256

Code Security Module Registers

ADC registers (0 wait read only)

CPU–TIMER0/1/2 Registers

PIE Registers

No

PIE Vector Table

No

(1) Registers in Frame 0 support 16-bit and 32-bit accesses.

(2) If registers are EALLOW protected, then writes cannot be performed until the EALLOW instruction is executed. The EDIS instruction

disables writes to prevent stray code or pointers from corrupting register contents.

(3) The Flash Registers are also protected by the Code Security Module (CSM).

Table 6-9. Peripheral Frame 1 Registers

NAME

Comparator 1 registers

ADDRESS RANGE

0x00 6400 to 0x00 641F

0x00 6420 to 0x00 643F

0x00 6800 to 0x00 683F

0x00 6840 to 0x00 687F

0x00 6880 to 0x00 68BF

0x00 68C0 to 0x00 68FF

0x00 6A00 to 0x00 6A1F

0x00 6F80 to 0x00 6FFF

SIZE (×16)

EALLOW PROTECTED

(1)

32

64

32

128

(1)

Comparator 2 registers

ePWM1 + HRPWM1 registers

ePWM2 + HRPWM2 registers

ePWM3 + HRPWM3 registers

ePWM4 + HRPWM4 registers

eCAP1 registers

No

(1)

GPIO registers

(1) Some registers are EALLOW protected. For more information, see the TMS320F2802x,TMS320F2802xx Piccolo Technical Reference

Manual.

Table 6-10. Peripheral Frame 2 Registers

NAME

System Control Registers

ADDRESS RANGE

0x00 7010 to 0x00 702F

0x00 7040 to 0x00 704F

0x00 7050 to 0x00 705F

0x00 7060 to 0x00 706F

0x00 7070 to 0x00 707F

0x00 7100 to 0x00 717F

0x00 7900 to 0x00 793F

SIZE (×16)

EALLOW PROTECTED

32

16

Yes

No

SPI-A Registers

SCI-A Registers

16

No

NMI Watchdog Interrupt Registers

External Interrupt Registers

ADC Registers

16

Yes

16

Yes

(1)

128

64

(1)

I2C-A Registers

(1) Some registers are EALLOW protected. For more information, see the TMS320F2802x,TMS320F2802xx Piccolo Technical Reference

Manual.

Detailed Description

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6.4 Device Emulation Registers

These registers are used to control the protection mode of the C28x CPU and to monitor some critical

device signals. The registers are defined in Table 6-11 .

Table 6-11. Device Emulation Registers

ADDRESS

RANGE

EALLOW

PROTECTED

NAME

SIZE (x16)

DESCRIPTION

Device Configuration Register

Part ID Register

0x0880

0x0881

DEVICECNF

PARTID

2

1

Yes

0x3D 7FFF

TMS320F280200PT

TMS320F280200DA

TMS320F28027PT

TMS320F28027DA

TMS320F28027FPT

TMS320F28027FDA

TMS320F28026PT

TMS320F28026DA

TMS320F28026FPT

TMS320F28026FDA

TMS320F28023PT

TMS320F28023DA

TMS320F28022PT

TMS320F28022DA

TMS320F28021PT

TMS320F28021DA

TMS320F28020PT

TMS320F28020DA

TMS320F280200PT/DA

TMS320F28027PT/DA

TMS320F28027FPT/DA

TMS320F28026PT/DA

TMS320F28026FPT/DA

TMS320F28023PT/DA

TMS320F28022PT/DA

TMS320F28021PT/DA

TMS320F28020PT/DA

0x00C1

0x00C0

0x00CF

0x00CE

0x00CF

0x00CE

0x00C7

0x00C6

0x00C7

0x00C6

0x00CD

0x00CC

0x00C5

0x00C4

0x00CB

0x00CA

0x00C3

0x00C2

0x00C7

0x00CF

0x00C7

0x00CF

0x00C7

0x00CF

0x00C7

No

CLASSID

0x0882

1

Class ID Register

No

REVID

0x0883

1

Revision ID

Register

0x0000 - Silicon Rev. 0 - TMS

0x0001 - Silicon Rev. A - TMS

0x0002 - Silicon Rev. B - TMS

54

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6.5 VREG/BOR/POR

Although the core and I/O circuitry operate on two different voltages, these devices have an on-chip

voltage regulator (VREG) to generate the V_DDvoltage from the V_DDIOsupply. This eliminates the cost and

space of a second external regulator on an application board. Additionally, internal power-on reset (POR)

and brown-out reset (BOR) circuits monitor both the V_DDand V_DDIOrails during power-up and run mode.

6.5.1 On-chip Voltage Regulator (VREG)

A linear regulator generates the core voltage (V_DD) from the V_DDIOsupply. Therefore, although capacitors

are required on each V_DDpin to stabilize the generated voltage, power need not be supplied to these pins

to operate the device. Conversely, the VREG can be disabled, should power or redundancy be the

primary concern of the application.

6.5.1.1 Using the On-chip VREG

To use the on-chip VREG, the VREGENZ pin should be tied low and the appropriate recommended

operating voltage should be supplied to the V_DDIOand V_DDApins. In this case, the V_DDvoltage needed by

the core logic will be generated by the VREG. Each V_DDpin requires on the order of 1.2 μF (minimum)

capacitance for proper regulation of the VREG. These capacitors should be located as close as possible

to the V_DDpins. Driving an external load with the internal VREG is not supported.

6.5.1.2 Disabling the On-chip VREG

To conserve power, it is also possible to disable the on-chip VREG and supply the core logic voltage to

the V_DDpins with a more efficient external regulator. To enable this option, the VREGENZ pin must be tied

high.

Detailed Description

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6.5.2 On-chip Power-On Reset (POR) and Brown-Out Reset (BOR) Circuit

Two on-chip supervisory circuits, the power-on reset (POR) and the brown-out reset (BOR) remove the

burden of monitoring the V_DDand V_DDIOsupply rails from the application board. The purpose of the POR is

to create a clean reset throughout the device during the entire power-up procedure. The trip point is a

looser, lower trip point than the BOR, which watches for dips in the V_DDor V_DDIOrail during device

operation. The POR function is present on both V_DDand V_DDIOrails at all times. After initial device power-

up, the BOR function is present on V_DDIOat all times, and on V_DDwhen the internal VREG is enabled

(VREGENZ pin is tied low). Both functions tie the XRS pin low when one of the voltages is below their

respective trip point. V_DDBOR and overvoltage trip points are outside of the recommended operating

voltages. Proper device operation cannot be ensured. If overvoltage or undervoltage conditions affecting

the system is a concern for an application, an external voltage supervisor should be added. Figure 6-6

shows the VREG, POR, and BOR. To disable both the V_DDand V_DDIOBOR functions, a bit is provided in

the

BORCFG

register.

For

details,

see

the

System

Control

chapter

in

the

TMS320F2802x,TMS320F2802xx Piccolo Technical Reference Manual.

In

I/O Pin

Out

(Force Hi-Z When High)

DIR (0 = Input, 1 = Output)

Internal

Weak PU

SYSRS

SYSCLKOUT

Sync

Deglitch

Filter

RS

WDRST

C28

Core

MCLKRS

JTAG

TCK

PLL

+

Clocking

Logic

Detect

Logic

XRS

VREGHALT

WDRST^(A)

PBRS^(B)

POR/BOR

Generating

Module

On-Chip

Voltage

Regulator

(VREG)

VREGENZ

A. WDRST is the reset signal from the CPU-watchdog.

B. PBRS is the reset signal from the POR/BOR module.

Figure 6-6. VREG + POR + BOR + Reset Signal Connectivity

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6.6 System Control

This section describes the oscillator and clocking mechanisms, the watchdog function and the low-power

modes.

Table 6-12. PLL, Clocking, Watchdog, and Low-Power Mode Registers

NAME

BORCFG

ADDRESS

0x00 0985

0x00 7010

0x00 7011

0x00 7012

0x00 7013

0x00 7014

0x00 7016

0x00 701B

0x00 701C

0x00 701D

0x00 701E

0x00 7020

0x00 7021

0x00 7022

0x00 7023

0x00 7025

0x00 7029

SIZE (x16)

DESCRIPTION⁽¹⁾

BOR Configuration Register

1

XCLK

XCLKOUT Control

PLLSTS

PLL Status Register

CLKCTL

Clock Control Register

PLLLOCKPRD

INTOSC1TRIM

INTOSC2TRIM

LOSPCP

PCLKCR0

PCLKCR1

LPMCR0

PCLKCR3

PLLCR

PLL Lock Period

Internal Oscillator 1 Trim Register

Internal Oscillator 2 Trim Register

Low-Speed Peripheral Clock Prescaler Register

Peripheral Clock Control Register 0

Peripheral Clock Control Register 1

Low-Power Mode Control Register 0

Peripheral Clock Control Register 3

PLL Control Register

SCSR

System Control and Status Register

Watchdog Counter Register

Watchdog Reset Key Register

Watchdog Control Register

WDCNTR

WDKEY

WDCR

(1) All registers in this table are EALLOW protected.

Detailed Description

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Figure 6-7 shows the various clock domains that are discussed. Figure 6-8 shows the various clock

sources (both internal and external) that can provide a clock for device operation.

SYSCLKOUT

PCLKCR0/1/3

(System Ctrl Regs)

LOSPCP

(System Ctrl Regs)

C28x Core

CLKIN

Clock Enables

LSPCLK

Peripheral

Registers

SPI-A, SCI-A

I/O

PF2

Clock Enables

eCAP1

Peripheral

Registers

PF1

PF2

GPIO

Mux

Clock Enables

ePWM1/.../4

Clock Enables

I2C-A

Peripheral

Registers

Peripheral

Registers

Clock Enables

ADC

Registers

PF2

PF0

16 Ch

12-Bit ADC

Analog

GPIO

Mux

Clock Enables

COMP1/2

COMP

Registers

6

PF1

A. CLKIN is the clock into the CPU. It is passed out of the CPU as SYSCLKOUT (that is, CLKIN is the same frequency

as SYSCLKOUT).

Figure 6-7. Clock and Reset Domains

58

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CLKCTL[WDCLKSRCSEL]

Internal

OSC 1

(10 MHz)

0

OSC1CLK

OSCCLKSRC1

INTOSC1TRIM Reg^(A)

WDCLK

CPU-watchdog

(OSC1CLK on XRS reset)

OSCE

1

CLKCTL[INTOSC1OFF]

1 = Turn OSC Off

CLKCTL[OSCCLKSRCSEL]

CLKCTL[INTOSC1HALT]

1 = Ignore HALT

WAKEOSC

OSC2CLK

0

1

Internal

OSC 2

(10 MHz)

INTOSC2TRIM Reg^(A)

OSCCLK

PLL

Missing-Clock-Detect Circuit^(B)

(OSC1CLK on XRS reset)

OSCE

CLKCTL[TRM2CLKPRESCALE]

CLKCTL[TMR2CLKSRCSEL]

1 = Turn OSC Off

10

11

CLKCTL[INTOSC2OFF]

Prescale

/1, /2, /4,

/8, /16

SYNC

Edge

Detect

01, 10, 11

CPUTMR2CLK

1 = Ignore HALT

01

1

0

00

CLKCTL[INTOSC2HALT]

SYSCLKOUT

OSCCLKSRC2

CLKCTL[OSCCLKSRC2SEL]

0 = GPIO38

1 = GPIO19

XCLK[XCLKINSEL]

CLKCTL[XCLKINOFF]

0

1

0

GPIO19

or

XCLKIN

GPIO38

XCLKIN

X1

X2

EXTCLK

(Crystal)

OSC

XTAL

WAKEOSC

(Oscillators enabled when this signal is high)

0 = OSC on (default on reset)

1 = Turn OSC off

CLKCTL[XTALOSCOFF]

A. Register loaded from TI OTP-based calibration function.

B. See Section 6.6.4 for details on missing clock detection.

Figure 6-8. Clock Tree

Detailed Description

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6.6.1 Internal Zero Pin Oscillators

The F2802x devices contain two independent internal zero pin oscillators. By default both oscillators are

turned on at power up, and internal oscillator 1 is the default clock source at this time. For power savings,

unused oscillators may be powered down by the user. The center frequency of these oscillators is

determined by their respective oscillator trim registers, written to in the calibration routine as part of the

boot ROM execution. See Section 5, Electrical Specifications, for more information on these oscillators.

6.6.2 Crystal Oscillator Option

The on-chip crystal oscillator X1 and X2 pins are 1.8-V level signals and must never have 3.3-V level

signals applied to them. If a system 3.3-V external oscillator is to be used as a clock source, it should be

connected to the XCLKIN pin only. The X1 pin is not intended to be used as a single-ended clock input, it

should be used with X2 and a crystal.

The typical specifications for the external quartz crystal (fundamental mode, parallel resonant) are listed in

Table 6-13. Furthermore, ESR range = 30 to 150 Ω.

Table 6-13. Typical Specifications for External Quartz Crystal⁽¹⁾

FREQUENCY (MHz)

R_d(Ω)

2200

470

0

C_L1(pF)

18

C_L2(pF)

18

5

10

15

20

15

0

12

(1) C_shuntshould be less than or equal to 5 pF.

XCLKIN/GPIO19/38

X1

X2

R_d

Turn off

XCLKIN path

in CLKCTL

register

C_L1

Crystal

C_L2

A. X1/X2 pins are available in 48-pin package only.

Figure 6-9. Using the On-chip Crystal Oscillator

NOTE

1. C_L1and C_L2are the total capacitance of the circuit board and components excluding the

IC and crystal. The value is usually approximately twice the value of the crystal's load

capacitance.

2. The load capacitance of the crystal is described in the crystal specifications of the

manufacturers.

3. TI recommends that customers have the resonator/crystal vendor characterize the

operation of their device with the MCU chip. The resonator/crystal vendor has the

equipment and expertise to tune the tank circuit. The vendor can also advise the

customer regarding the proper tank component values that will produce proper start-up

and stability over the entire operating range.

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XCLKIN/GPIO19/38

X1

X2

NC

External Clock Signal

(Toggling 0−V

)

DDIO

Figure 6-10. Using a 3.3-V External Oscillator

6.6.3 PLL-Based Clock Module

The devices have an on-chip, PLL-based clock module. This module provides all the necessary clocking

signals for the device, as well as control for low-power mode entry. The PLL has a 4-bit ratio control

PLLCR[DIV] to select different CPU clock rates. The watchdog module should be disabled before writing

to the PLLCR register. It can be re-enabled (if need be) after the PLL module has stabilized, which takes

1 ms. The input clock and PLLCR[DIV] bits should be chosen in such a way that the output frequency of

the PLL (VCOCLK) is at least 50 MHz.

Table 6-14. PLL Settings

SYSCLKOUT (CLKIN)

PLLCR[DIV] VALUE^{(1) (2)}

PLLSTS[DIVSEL] = 0 or 1⁽³⁾

OSCCLK/4 (Default)⁽¹⁾

(OSCCLK * 1)/4

PLLSTS[DIVSEL] = 2

OSCCLK/2

PLLSTS[DIVSEL] = 3

OSCCLK

0000 (PLL bypass)

0001

(OSCCLK * 1)/2

(OSCCLK * 2)/2

(OSCCLK * 3)/2

(OSCCLK * 4)/2

(OSCCLK * 5)/2

(OSCCLK * 6)/2

(OSCCLK * 7)/2

(OSCCLK * 8)/2

(OSCCLK * 9)/2

(OSCCLK * 10)/2

(OSCCLK * 11)/2

(OSCCLK * 12)/2

(OSCCLK * 1)/1

(OSCCLK * 2)/1

(OSCCLK * 3)/1

(OSCCLK * 4)/1

(OSCCLK * 5)/1

(OSCCLK * 6)/1

(OSCCLK * 7)/1

(OSCCLK * 8)/1

(OSCCLK * 9)/1

(OSCCLK * 10)/1

(OSCCLK * 11)/1

(OSCCLK * 12)/1

0010

(OSCCLK * 2)/4

0011

(OSCCLK * 3)/4

0100

(OSCCLK * 4)/4

0101

(OSCCLK * 5)/4

0110

(OSCCLK * 6)/4

0111

(OSCCLK * 7)/4

1000

(OSCCLK * 8)/4

1001

(OSCCLK * 9)/4

1010

(OSCCLK * 10)/4

(OSCCLK * 11)/4

(OSCCLK * 12)/4

1011

1100

(1) The PLL control register (PLLCR) and PLL Status Register (PLLSTS) are reset to their default state by the XRS signal or a watchdog

reset only. A reset issued by the debugger or the missing clock detect logic has no effect.

(2) This register is EALLOW protected. See the System Control chapter in the TMS320F2802x,TMS320F2802xx Piccolo Technical

Reference Manual for more information.

(3) By default, PLLSTS[DIVSEL] is configured for /4. (The boot ROM changes this to /1.) PLLSTS[DIVSEL] must be 0 before writing to the

PLLCR and should be changed only after PLLSTS[PLLLOCKS] = 1.

Table 6-15. CLKIN Divide Options

PLLSTS [DIVSEL]

CLKIN DIVIDE

0

1

2

3

/4

/2

/1

Detailed Description

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The PLL-based clock module provides four modes of operation:

•

INTOSC1 (Internal Zero-pin Oscillator 1): This is the on-chip internal oscillator 1. This can provide

the clock for the Watchdog block, core and CPU-Timer 2

•

INTOSC2 (Internal Zero-pin Oscillator 2): This is the on-chip internal oscillator 2. This can provide

the clock for the Watchdog block, core and CPU-Timer 2. Both INTOSC1 and INTOSC2 can be

independently chosen for the Watchdog block, core and CPU-Timer 2.

•

Crystal/Resonator Operation: The on-chip (crystal) oscillator enables the use of an external

crystal/resonator attached to the device to provide the time base. The crystal/resonator is connected to

the X1/X2 pins. Some devices may not have the X1/X2 pins. See Table 4-1 for details.

External Clock Source Operation: If the on-chip (crystal) oscillator is not used, this mode allows it to

be bypassed. The device clocks are generated from an external clock source input on the XCLKIN pin.

The XCLKIN is multiplexed with GPIO19 or GPIO38 pin. The XCLKIN input can be selected as

GPIO19 or GPIO38 through the XCLKINSEL bit in XCLK register. The CLKCTL[XCLKINOFF] bit

disables this clock input (forced low). If the clock source is not used or the respective pins are used as

GPIOs, the user should disable at boot time.

Before changing clock sources, ensure that the target clock is present. If a clock is not present, then that

clock source must be disabled (using the CLKCTL register) before switching clocks.

Table 6-16. Possible PLL Configuration Modes

CLKIN AND

SYSCLKOUT

PLL MODE

REMARKS

PLLSTS[DIVSEL]

Invoked by the user setting the PLLOFF bit in the PLLSTS register. The PLL block

is disabled in this mode. This can be useful to reduce system noise and for low-

power operation. The PLLCR register must first be set to 0x0000 (PLL Bypass)

before entering this mode. The CPU clock (CLKIN) is derived directly from the

input clock on either X1/X2, X1 or XCLKIN.

0, 1

2

3

OSCCLK/4

OSCCLK/2

OSCCLK/1

PLL Off

PLL Bypass is the default PLL configuration upon power-up or after an external

reset (XRS). This mode is selected when the PLLCR register is set to 0x0000 or

while the PLL locks to a new frequency after the PLLCR register has been

modified. In this mode, the PLL is bypassed but the PLL is not turned off.

0, 1

2

3

OSCCLK/4

OSCCLK/2

OSCCLK/1

PLL Bypass

PLL Enable

0, 1

2

3

OSCCLK * n/4

OSCCLK * n/2

OSCCLK * n/1

Achieved by writing a nonzero value n into the PLLCR register. Upon writing to the

PLLCR the device will switch to PLL Bypass mode until the PLL locks.

6.6.4 Loss of Input Clock (NMI Watchdog Function)

The 2802x devices may be clocked from either one of the internal zero-pin oscillators

(INTOSC1/INTOSC2), the on-chip crystal oscillator, or from an external clock input. Regardless of the

clock source, in PLL-enabled and PLL-bypass mode, if the input clock to the PLL vanishes, the PLL will

issue a limp-mode clock at its output. This limp-mode clock continues to clock the CPU and peripherals at

a typical frequency of 1–5 MHz.

When the limp mode is activated, a CLOCKFAIL signal is generated that is latched as an NMI interrupt.

Depending on how the NMIRESETSEL bit has been configured, a reset to the device can be fired

immediately or the NMI watchdog counter can issue a reset when it overflows. In addition to this, the

Missing Clock Status (MCLKSTS) bit is set. The NMI interrupt could be used by the application to detect

the input clock failure and initiate necessary corrective action such as switching over to an alternative

clock source (if available) or initiate a shut-down procedure for the system.

If the software does not respond to the clock-fail condition, the NMI watchdog triggers a reset after a

preprogrammed time interval. Figure 6-11 shows the interrupt mechanisms involved.

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NMIFLG[NMINT]

NMIFLGCLR[NMINT]

Clear

Latch

Set

Clear

XRS

Generate

Interrupt

Pulse

When

Input = 1

NMIFLG[CLOCKFAIL]

0

1

0

Clear

NMIFLGCLR[CLOCKFAIL]

CLOCKFAIL

NMINT

Latch

SYNC?

Set

Clear

XRS

SYSCLKOUT

NMICFG[CLOCKFAIL]

NMIFLGFRC[CLOCKFAIL]

SYSCLKOUT

SYSRS

NMIWDPRD[15:0]

NMIWDCNT[15:0]

See System

Control Section

NMI-watchdog

NMIRS

Figure 6-11. NMI-watchdog

6.6.5 CPU-Watchdog Module

The CPU-watchdog module on the 2802x device is similar to the one used on the 281x/280x/283xx

devices. This module generates an output pulse, 512 oscillator clocks wide (OSCCLK), whenever the 8-bit

watchdog up counter has reached its maximum value. To prevent this, the user must disable the counter

or the software must periodically write a 0x55 + 0xAA sequence into the watchdog key register that resets

the watchdog counter. Figure 6-12 shows the various functional blocks within the watchdog module.

Normally, when the input clocks are present, the CPU-watchdog counter decrements to initiate a CPU-

watchdog reset or WDINT interrupt. However, when the external input clock fails, the CPU-watchdog

counter stops decrementing (that is, the watchdog counter does not change with the limp-mode clock).

NOTE

The CPU-watchdog is different from the NMI watchdog. It is the legacy watchdog that is

present in all 28x devices.

NOTE

Applications in which the correct CPU operating frequency is absolutely critical should

implement a mechanism by which the MCU will be held in reset, should the input clocks ever

fail. For example, an R-C circuit may be used to trigger the XRS pin of the MCU, should the

capacitor ever get fully charged. An I/O pin may be used to discharge the capacitor on a

periodic basis to prevent it from getting fully charged. Such a circuit would also help in

detecting failure of the flash memory.

Detailed Description

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WDCR (WDPS[2:0])

WDCR (WDDIS)

WDCNTR(7:0)

WDCLK

8-Bit

Watchdog

Counter

CLR

Watchdog

Prescaler

/512

Clear Counter

Internal

Pullup

WDKEY(7:0)

WDRST

WDINT

Generate

Watchdog

55 + AA

Key Detector

Output Pulse

(512 OSCCLKs)

Good K ey

XRS

Bad

WDCHK

Key

Core-reset

SCSR (WDENINT)

WDCR (WDCHK[2:0])

1

0

1

(A)

WDRST

A. The WDRST signal is driven low for 512 OSCCLK cycles.

Figure 6-12. CPU-watchdog Module

The WDINT signal enables the watchdog to be used as a wakeup from IDLE/STANDBY mode.

In STANDBY mode, all peripherals are turned off on the device. The only peripheral that remains

functional is the CPU-watchdog. This module will run off OSCCLK. The WDINT signal is fed to the LPM

block so that it can wake the device from STANDBY (if enabled). See Section 6.7, Low-power Modes

Block, for more details.

In IDLE mode, the WDINT signal can generate an interrupt to the CPU, through the PIE, to take the CPU

out of IDLE mode.

In HALT mode, the CPU-watchdog can be used to wake up the device through a device reset.

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6.7 Low-power Modes Block

Table 6-17 summarizes the various modes.

Table 6-17. Low-power Modes

MODE

LPMCR0(1:0)

OSCCLK

CLKIN

SYSCLKOUT

EXIT⁽¹⁾

XRS, CPU-watchdog interrupt, any

enabled interrupt

IDLE

00

On

XRS, CPU-watchdog interrupt, GPIO

Port A signal, debugger⁽²⁾

STANDBY

HALT⁽³⁾

01

Off

(CPU-watchdog still running)

Off

(on-chip crystal oscillator and

PLL turned off, zero-pin oscillator

and CPU-watchdog state

dependent on user code.)

XRS, GPIO Port A signal, debugger⁽²⁾

CPU-watchdog

,

1X

Off

(1) The EXIT column lists which signals or under what conditions the low-power mode is exited. A low signal, on any of the signals, exits

the low-power condition. This signal must be kept low long enough for an interrupt to be recognized by the device. Otherwise, the low-

power mode will not be exited and the device will go back into the indicated low-power mode.

(2) The JTAG port can still function even if the CPU clock (CLKIN) is turned off.

(3) The WDCLK must be active for the device to go into HALT mode.

The various low-power modes operate as follows:

IDLE Mode:

This mode is exited by any enabled interrupt that is recognized by the

processor. The LPM block performs no tasks during this mode as long as

the LPMCR0(LPM) bits are set to 0,0.

STANDBY Mode:

Any GPIO port A signal (GPIO[31:0]) can wake the device from STANDBY

mode. The user must select which signal(s) will wake the device in the

GPIOLPMSEL register. The selected signal(s) are also qualified by the

OSCCLK before waking the device. The number of OSCCLKs is specified in

the LPMCR0 register.

HALT Mode:

CPU-watchdog, XRS, and any GPIO port A signal (GPIO[31:0]) can wake

the device from HALT mode. The user selects the signal in the

GPIOLPMSEL register.

NOTE

The low-power modes do not affect the state of the output pins (PWM pins included). They

will be in whatever state the code left them in when the IDLE instruction was executed. See

the System Control chapter in the TMS320F2802x,TMS320F2802xx Piccolo Technical

Reference Manual for more details.

Detailed Description

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6.8 Interrupts

Figure 6-13 shows how the various interrupt sources are multiplexed.

Peripherals

(SPI, SCI, ePWM, I²C, HRPWM, eCAP, ADC)

WDINT

Watchdog

WAKEINT

Sync

LPMINT

Low-Power Modes

SYSCLKOUT

Interrupt Control

XINT1CR(15:0)

XINT1CTR(15:0)

XINT1

GPIOXINT1SEL(4:0)

XINT2SOC

ADC

INT1

to

INT12

XINT2

Interrupt Control

XINT2CR(15:0)

XINT2CTR(15:0)

C28

Core

GPIOXINT2SEL(4:0)

GPIO0.int

XINT3

TINT0

XINT3

GPIO

MUX

Interrupt Control

XINT3CR(15:0)

XINT3CTR(15:0)

GPIO31.int

GPIOXINT3SEL(4:0)

CPU TIMER 0

CPU TIMER 1

CPU TIMER 2

TINT1

TINT2

INT13

INT14

CPUTMR2CLK

CLOCKFAIL

NMIRS

System Control

(See the System

Control section.)

NMI interrupt with watchdog function

(See the NMI Watchdog section.)

NMI

Figure 6-13. External and PIE Interrupt Sources

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Eight PIE block interrupts are grouped into one CPU interrupt. In total, 12 CPU interrupt groups, with

8 interrupts per group equals 96 possible interrupts. Table 6-18 shows the interrupts used by 2802x

devices.

The TRAP #VectorNumber instruction transfers program control to the interrupt service routine

corresponding to the vector specified. The TRAP #0 instruction attempts to transfer program control to the

address pointed to by the reset vector. The PIE vector table does not, however, include a reset vector.

Therefore, the TRAP #0 instruction should not be used when the PIE is enabled. Doing so will result in

undefined behavior.

When the PIE is enabled, the TRAP #1 to TRAP #12 instructions will transfer program control to the

interrupt service routine corresponding to the first vector within the PIE group. For example: the TRAP #1

instruction fetches the vector from INT1.1, the TRAP #2 instruction fetches the vector from INT2.1, and so

forth.

IFR[12:1]

IER[12:1]

INTM

INT1

INT2

1

CPU

MUX

0

INT11

INT12

Global

Enable

(Flag)

(Enable)

INTx.1

INTx.2

INTx.3

INTx.4

INTx.5

From

Peripherals

or

External

Interrupts

INTx

MUX

INTx.6

INTx.7

INTx.8

PIEACKx

(Enable/Flag)

(Enable)

(Flag)

PIEIERx[8:1]

PIEIFRx[8:1]

Figure 6-14. Multiplexing of Interrupts Using the PIE Block

Detailed Description

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Table 6-18. PIE MUXed Peripheral Interrupt Vector Table⁽¹⁾

INTx.8

WAKEINT

(LPM/WD)

0xD4E

Reserved

–

INTx.7

TINT0

(TIMER 0)

0xD4C

Reserved

–

INTx.6

ADCINT9

(ADC)

0xD4A

Reserved

–

INTx.5

XINT2

Ext. int. 2

0xD48

Reserved

–

INTx.4

XINT1

Ext. int. 1

0xD46

EPWM4_TZINT

(ePWM4)

0xD56

EPWM4_INT

(ePWM4)

0xD66

Reserved

–

INTx.3

Reserved

–

INTx.2

ADCINT2

(ADC)

INTx.1

ADCINT1

(ADC)

INT1.y

INT2.y

INT3.y

INT4.y

INT5.y

INT6.y

INT7.y

INT8.y

INT9.y

INT10.y

INT11.y

INT12.y

0xD44

EPWM3_TZINT

(ePWM3)

0xD54

EPWM3_INT

(ePWM3)

0xD64

Reserved

–

0xD42

0xD40

EPWM2_TZINT

(ePWM2)

0xD52

EPWM1_TZINT

(ePWM1)

0xD50

0xD5E

Reserved

–

0xD5C

Reserved

–

0xD5A

Reserved

–

0xD58

Reserved

–

EPWM2_INT

(ePWM2)

0xD62

EPWM1_INT

(ePWM1)

0xD60

0xD6E

Reserved

–

0xD6C

Reserved

–

0xD6A

Reserved

–

0xD68

Reserved

–

Reserved

–

ECAP1_INT

(eCAP1)

0xD70

0xD7E

Reserved

–

0xD7C

Reserved

–

0xD7A

Reserved

–

0xD78

Reserved

–

0xD76

Reserved

–

0xD74

Reserved

–

0xD72

Reserved

–

Reserved

–

0xD8E

Reserved

–

0xD8C

Reserved

–

0xD8A

Reserved

–

0xD88

Reserved

–

0xD86

Reserved

–

0xD84

Reserved

–

0xD82

0xD80

SPITXINTA

(SPI-A)

0xD92

SPIRXINTA

(SPI-A)

0xD90

0xD9E

Reserved

–

0xD9C

Reserved

–

0xD9A

Reserved

–

0xD98

Reserved

–

0xD96

Reserved

–

0xD94

Reserved

–

Reserved

–

Reserved

–

0xDAE

Reserved

–

0xDAC

Reserved

–

0xDAA

Reserved

–

0xDA8

Reserved

–

0xDA6

Reserved

–

0xDA4

Reserved

–

0xDA2

0xDA0

I2CINT2A

(I2C-A)

0xDB2

I2CINT1A

(I2C-A)

0xDBE

Reserved

–

0xDBC

Reserved

–

0xDBA

Reserved

–

0xDB8

Reserved

–

0xDB6

Reserved

–

0xDB4

Reserved

–

0xDB0

SCITXINTA

(SCI-A)

0xDC2

SCIRXINTA

(SCI-A)

0xDC0

0xDCE

ADCINT8

(ADC)

0xDDE

Reserved

–

0xDCC

ADCINT7

(ADC)

0xDDC

Reserved

–

0xDCA

ADCINT6

(ADC)

0xDDA

Reserved

–

0xDC8

ADCINT5

(ADC)

0xDD8

Reserved

–

0xDC6

ADCINT4

(ADC)

0xDC4

ADCINT3

(ADC)

0xDD4

Reserved

–

ADCINT2

(ADC)

ADCINT1

(ADC)

0xDD6

Reserved

–

0xDD2

0xDD0

Reserved

–

Reserved

–

0xDEE

Reserved

–

0xDEC

Reserved

–

0xDEA

Reserved

–

0xDE8

Reserved

–

0xDE6

Reserved

–

0xDE4

Reserved

–

0xDE2

0xDE0

Reserved

–

XINT3

Ext. Int. 3

0xDF0

0xDFE

0xDFC

0xDFA

0xDF8

0xDF6

0xDF4

0xDF2

(1) Out of 96 possible interrupts, some interrupts are not used. These interrupts are reserved for future devices. These interrupts can be

used as software interrupts if they are enabled at the PIEIFRx level, provided none of the interrupts within the group is being used by a

peripheral. Otherwise, interrupts coming in from peripherals may be lost by accidentally clearing their flag while modifying the PIEIFR.

To summarize, there are two safe cases when the reserved interrupts could be used as software interrupts:

•

No peripheral within the group is asserting interrupts.

No peripheral interrupts are assigned to the group (for example, PIE groups 5, 7, or 11) .

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Table 6-19. PIE Configuration and Control Registers

NAME

PIECTRL

PIEACK

PIEIER1

PIEIFR1

PIEIER2

PIEIFR2

PIEIER3

PIEIFR3

PIEIER4

PIEIFR4

PIEIER5

PIEIFR5

PIEIER6

PIEIFR6

PIEIER7

PIEIFR7

PIEIER8

PIEIFR8

PIEIER9

PIEIFR9

PIEIER10

PIEIFR10

PIEIER11

PIEIFR11

PIEIER12

PIEIFR12

Reserved

ADDRESS

0x0CE0

0x0CE1

0x0CE2

0x0CE3

0x0CE4

0x0CE5

0x0CE6

0x0CE7

0x0CE8

0x0CE9

0x0CEA

0x0CEB

0x0CEC

0x0CED

0x0CEE

0x0CEF

0x0CF0

0x0CF1

0x0CF2

0x0CF3

0x0CF4

0x0CF5

0x0CF6

0x0CF7

0x0CF8

0x0CF9

SIZE (x16)

DESCRIPTION⁽¹⁾

PIE, Control Register

1

6

PIE, Acknowledge Register

PIE, INT1 Group Enable Register

PIE, INT1 Group Flag Register

PIE, INT2 Group Enable Register

PIE, INT2 Group Flag Register

PIE, INT3 Group Enable Register

PIE, INT3 Group Flag Register

PIE, INT4 Group Enable Register

PIE, INT4 Group Flag Register

PIE, INT5 Group Enable Register

PIE, INT5 Group Flag Register

PIE, INT6 Group Enable Register

PIE, INT6 Group Flag Register

PIE, INT7 Group Enable Register

PIE, INT7 Group Flag Register

PIE, INT8 Group Enable Register

PIE, INT8 Group Flag Register

PIE, INT9 Group Enable Register

PIE, INT9 Group Flag Register

PIE, INT10 Group Enable Register

PIE, INT10 Group Flag Register

PIE, INT11 Group Enable Register

PIE, INT11 Group Flag Register

PIE, INT12 Group Enable Register

PIE, INT12 Group Flag Register

Reserved

0x0CFA –

0x0CFF

(1) The PIE configuration and control registers are not protected by EALLOW mode. The PIE vector table

is protected.

Detailed Description

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6.8.1 External Interrupts

Table 6-20. External Interrupt Registers

NAME

XINT1CR

XINT2CR

XINT3CR

XINT1CTR

XINT2CTR

XINT3CTR

ADDRESS

0x00 7070

0x00 7071

0x00 7072

0x00 7078

0x00 7079

0x00 707A

SIZE (x16)

DESCRIPTION

XINT1 configuration register

XINT2 configuration register

XINT3 configuration register

XINT1 counter register

1

XINT2 counter register

XINT3 counter register

Each external interrupt can be enabled/disabled or qualified using positive, negative, or both positive and

negative edge. For more information, see the System Control chapter in the

TMS320F2802x,TMS320F2802xx Piccolo Technical Reference Manual.

6.8.1.1 External Interrupt Electrical Data/Timing

Table 6-21. External Interrupt Timing Requirements⁽¹⁾

MIN

1t_c(SCO)

MAX

UNIT

Synchronous

cycles

(2)

t_w(INT)

Pulse duration, INT input low/high

With qualifier

1t_c(SCO)+ t_w(IQSW)

(1) For an explanation of the input qualifier parameters, see Table 6-55.

(2) This timing is applicable to any GPIO pin configured for ADCSOC functionality.

Table 6-22. External Interrupt Switching Characteristics⁽¹⁾

over recommended operating conditions (unless otherwise noted)

PARAMETER

MIN

MAX

t_w(IQSW)+ 12t_c(SCO)

UNIT

t_d(INT)

Delay time, INT low/high to interrupt-vector fetch

cycles

(1) For an explanation of the input qualifier parameters, see Table 6-55.

t

w(INT)

XINT1, XINT2, XINT3

t

d(INT)

Address bus

(internal)

Interrupt Vector

Figure 6-15. External Interrupt Timing

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6.9 Peripherals

6.9.1 Analog Block

A 12-bit ADC core is implemented that has different timings than the 12-bit ADC used on F280x/F2833x.

The ADC wrapper is modified to incorporate the new timings and also other enhancements to improve the

timing control of start of conversions. Figure 6-16 shows the interaction of the analog module with the rest

of the F2802x system.

For more information on the ADC, see the Analog-to-Digital Converter and Comparator chapter in the

TMS320F2802x,TMS320F2802xx Piccolo Technical Reference Manual.

(3.3 V) VDDA

(Agnd) VSSA

VREFLO

38-Pin

VDDA

48-Pin

VDDA

VREFLO VREFLO

Tied To Tied To

Interface Reference

Diff

VSSA

VREFHI VREFHI

Tied To Tied To

VREFHI

A0

B0

A0

A2

A4

A6

A0

A1

A2

A3

A4

A1

B1

COMP1OUT

A2

AIO2

AIO10

10-Bit

DAC

Comp1

Comp2

B2

A6

A7

A3

B3

ADC

COMP2OUT

(See Note A)

A4

B4

B1

B2

B3

B4

AIO4

AIO12

10-Bit

DAC

B2

B4

B6

B5

B6

B7

Temperature Sensor

A5

A6

Signal Pinout

AIO6

AIO14

B6

A7

B7

A. Comparator 2 is available only on the 48-pin PT package.

Figure 6-16. Analog Pin Configurations

Detailed Description

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6.9.1.1 Analog-to-Digital Converter (ADC)

6.9.1.1.1 Features

The core of the ADC contains a single 12-bit converter fed by two sample-and-hold circuits. The sample-

and-hold circuits can be sampled simultaneously or sequentially. These, in turn, are fed by a total of up to

13 analog input channels. The converter can be configured to run with an internal band-gap reference to

create true-voltage based conversions or with a pair of external voltage references (V_REFHI/V_REFLO) to

create ratiometric-based conversions.

Contrary to previous ADC types, this ADC is not sequencer-based. It is easy for the user to create a

series of conversions from a single trigger. However, the basic principle of operation is centered around

the configurations of individual conversions, called SOCs, or Start-Of-Conversions.

Functions of the ADC module include:

•

12-bit ADC core with built-in dual sample-and-hold (S/H)

Simultaneous sampling or sequential sampling modes

Full range analog input: 0 V to 3.3 V fixed, or V_REFHI/V_REFLOratiometric. The digital value of the input

analog voltage is derived by:

–

Internal Reference (V_REFLO= V_SSA. V_REFHImust not exceed V_DDAwhen using either internal or

external reference modes.)

Digital Value = 0,

when input £ 0 V

Input Analog Voltage -

V_REFLO

Digital Value = 4096 ´

when 0 V < input < 3.3 V

3.3

Digital Value = 4095,

when input ³ 3.3 V

–

External Reference (V_REFHI/V_REFLOconnected to external references. V_REFHImust not exceed V_DDA

when using either internal or external reference modes.)

Digital Value = 0,

when input £ 0 V

Input Analog Voltage -

V_REFLO

Digital Value = 4096 ´

when 0 V < input <

V_REFHI

-

V_REFHIV_REFLO

Digital Value = 4095,

when input ³

V_REFHI

•

Up to 16-channel, multiplexed inputs

16 SOCs, configurable for trigger, sample window, and channel

16 result registers (individually addressable) to store conversion values

Multiple trigger sources

–

S/W – software immediate start

ePWM 1–4

GPIO XINT2

CPU Timers 0/1/2

ADCINT1/2

•

9 flexible PIE interrupts, can configure interrupt request after any conversion

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Table 6-23. ADC Configuration and Control Registers

SIZE

(x16)

EALLOW

PROTECTED

REGISTER NAME

ADDRESS

DESCRIPTION

ADCCTL1

0x7100

0x7101

0x7104

0x7105

0x7106

0x7107

0x7108

0x7109

0x710A

0x710B

0x710C

0x7110

0x7112

0x7114

0x7115

0x7118

0x711A

0x711C

0x711E

1

Yes

No

Control 1 Register

Control 2 Register

Interrupt Flag Register

ADCCTL2

ADCINTFLG

ADCINTFLGCLR

ADCINTOVF

No

Interrupt Flag Clear Register

No

Interrupt Overflow Register

ADCINTOVFCLR

INTSEL1N2

No

Interrupt Overflow Clear Register

Yes

No

Interrupt 1 and 2 Selection Register

INTSEL3N4

Interrupt 3 and 4 Selection Register

INTSEL5N6

Interrupt 5 and 6 Selection Register

INTSEL7N8

Interrupt 7 and 8 Selection Register

INTSEL9N10

Interrupt 9 Selection Register (reserved Interrupt 10 Selection)

SOC Priority Control Register

SOCPRICTL

ADCSAMPLEMODE

ADCINTSOCSEL1

ADCINTSOCSEL2

ADCSOCFLG1

ADCSOCFRC1

ADCSOCOVF1

ADCSOCOVFCLR1

Sampling Mode Register

Interrupt SOC Selection 1 Register (for 8 channels)

Interrupt SOC Selection 2 Register (for 8 channels)

SOC Flag 1 Register (for 16 channels)

SOC Force 1 Register (for 16 channels)

SOC Overflow 1 Register (for 16 channels)

SOC Overflow Clear 1 Register (for 16 channels)

SOC0 Control Register to SOC15 Control Register

No

ADCSOC0CTL to

ADCSOC15CTL

0x7120 –

0x712F

Yes

ADCREFTRIM

ADCOFFTRIM

COMPHYSTCTL

ADCREV

0x7140

0x7141

0x714C

0x714F

1

Yes

No

Reference Trim Register

Offset Trim Register

Comparator Hysteresis Control Register

Revision Register

Table 6-24. ADC Result Registers (Mapped to PF0)

SIZE

(x16)

EALLOW

PROTECTED

REGISTER NAME

ADCRESULT0 to ADCRESULT15

ADDRESS

DESCRIPTION

0xB00 to 0xB0F

1

No

ADC Result 0 Register to ADC Result 15

Register

Detailed Description

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0-Wait

Result

Registers

PF0 (CPU)

PF2 (CPU)

SYSCLKOUT

ADCENCLK

ADCINT 1

PIE

ADCINT 9

TINT 0

TINT 1

TINT 2

ADC

Core

12-Bit

CPUTIMER 0

CPUTIMER 1

CPUTIMER 2

AIO

MUX

ADC

Channels

ADCTRIG 1

ADCTRIG 2

ADCTRIG 3

XINT 2SOC

XINT 2

ePWM 1

ePWM 2

ePWM 3

ePWM 4

ADCTRIG 4

SOCA 1

SOCB 1

SOCA 2

SOCB 2

SOCA 3

SOCB 3

SOCA 4

SOCB 4

ADCTRIG 5

ADCTRIG 6

ADCTRIG 7

ADCTRIG 8

ADCTRIG 9

ADCTRIG 10

ADCTRIG 11

ADCTRIG 12

Figure 6-17. ADC Connections

ADC Connections if the ADC is Not Used

TI recommends keeping the connections for the analog power pins, even if the ADC is not used. Following

is a summary of how the ADC pins should be connected, if the ADC is not used in an application:

•

V_DDA– Connect to V_DDIO

V_SSA– Connect to V_SS

V_REFLO– Connect to V_SS

ADCINAn, ADCINBn, V_REFHI– Connect to V_SSA

When the ADC module is used in an application, unused ADC input pins should be connected to analog

ground (V_SSA).

NOTE

Unused ADCIN pins that are multiplexed with AIO function should not be directly connected

to analog ground. They should be grounded through a 1-kΩ resistor. This is to prevent an

errant code from configuring these pins as AIO outputs and driving grounded pins to a logic-

high state.

When the ADC is not used, be sure that the clock to the ADC module is not turned on to realize power

savings.

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6.9.1.1.2 ADC Start-of-Conversion Electrical Data/Timing

Table 6-25. External ADC Start-of-Conversion Switching Characteristics

over recommended operating conditions (unless otherwise noted)

PARAMETER

MIN

MAX

UNIT

t_w(ADCSOCL)

Pulse duration, ADCSOCxO low

32t_c(HCO)

cycles

t_w(ADCSOCL)

ADCSOCAO

or

ADCSOCBO

Figure 6-18. ADCSOCAO or ADCSOCBO Timing

Detailed Description

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6.9.1.1.3 On-Chip Analog-to-Digital Converter (ADC) Electrical Data/Timing

Table 6-26. ADC Electrical Characteristics

PARAMETER

MIN

TYP

MAX

UNIT

DC SPECIFICATIONS

Resolution

12

0.001

7

Bits

ADC clock

60-MHz device

28027/26/23/22

28021/20/200

60

64

MHz

Sample Window

ADC

Clocks

14

ACCURACY

INL (Integral nonlinearity) at ADC Clock ≤ 30 MHz⁽¹⁾

–4

–1

4

1

LSB

DNL (Differential nonlinearity) at ADC Clock ≤ 30 MHz,

no missing codes

(2)

Offset error

Executing Device_Cal

function

–20

–4

0

20

4

LSB

Executing periodic self-

recalibration⁽³⁾

Overall gain error with internal reference

Overall gain error with external reference

Channel-to-channel offset variation

Channel-to-channel gain variation

ADC temperature coefficient with internal reference

ADC temperature coefficient with external reference

V_REFLO

–60

–40

–4

60

40

4

LSB

–4

4

LSB

–50

–20

ppm/°C

µA

–100

100

V_REFHI

µA

ANALOG INPUT

Analog input voltage with internal reference

Analog input voltage with external reference

V_REFLOinput voltage⁽⁴⁾

0

V_REFLO

V_SSA

3.3

V_REFHI

V_SSA

V

V_REFHIinput voltage⁽⁵⁾

with V_REFLO= V_SSA

1.98

V_DDA

V

Input capacitance

5

pF

μA

Input leakage current

±5

(1) INL will degrade when the ADC input voltage goes above V_DDA

.

(2) 1 LSB has the weighted value of full-scale range (FSR)/4096. FSR is 3.3 V with internal reference and V_REFHI- V_REFLOfor external

reference.

(3) Periodic self-recalibration will remove system-level and temperature dependencies on the ADC zero offset error. This can be performed

as needed in the application without sacrificing an ADC channel by using the procedure listed in the "ADC Zero Offset Calibration"

section of the Analog-to-Digital Converter and Comparator chapter in the TMS320F2802x,TMS320F2802xx Piccolo Technical Reference

Manual.

(4) V_REFLOis always connected to V_SSA

.

(5) V_REFHImust not exceed V_DDAwhen using either internal or external reference modes. Because V_REFHIis tied to ADCINA0, the input

signal on ADCINA0 must not exceed V_DDA

.

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Table 6-27. ADC Power Modes

ADC OPERATING MODE

CONDITIONS

I_DDA

UNITS

ADC Clock Enabled

Band gap On (ADCBGPWD = 1)

Reference On (ADCREFPWD = 1)

ADC Powered Up (ADCPWDN = 1)

Mode A – Operating Mode

13

mA

ADC Clock Enabled

Band gap On (ADCBGPWD = 1)

Reference On (ADCREFPWD = 1)

ADC Powered Up (ADCPWDN = 0)

Mode B – Quick Wake Mode

4

mA

ADC Clock Enabled

Band gap On (ADCBGPWD = 1)

Reference On (ADCREFPWD = 0)

ADC Powered Up (ADCPWDN = 0)

Mode C – Comparator-Only Mode

Mode D – Off Mode

1.5

ADC Clock Enabled

Band gap On (ADCBGPWD = 0)

Reference On (ADCREFPWD = 0)

ADC Powered Up (ADCPWDN = 0)

0.075

6.9.1.1.3.1 Internal Temperature Sensor

Table 6-28. Temperature Sensor Coefficient

PARAMETER⁽¹⁾

MIN

TYP

0.18⁽²⁾⁽³⁾

1750

MAX

UNIT

°C/LSB

LSB

T_SLOPE

Degrees C of temperature movement per measured ADC LSB change

of the temperature sensor

T_OFFSET

ADC output at 0°C of the temperature sensor

(1) The temperature sensor slope and offset are given in terms of ADC LSBs using the internal reference of the ADC. Values must be

adjusted accordingly in external reference mode to the external reference voltage.

(2) ADC temperature coeffieicient is accounted for in this specification

(3) Output of the temperature sensor (in terms of LSBs) is sign-consistent with the direction of the temperature movement. Increasing

temperatures will give increasing ADC values relative to an initial value; decreasing temperatures will give decreasing ADC values

relative to an initial value.

6.9.1.1.3.2 ADC Power-Up Control Bit Timing

Table 6-29. ADC Power-Up Delays

PARAMETER⁽¹⁾

MIN

MAX

UNIT

t_d(PWD)

Delay time for the ADC to be stable after power up

1

ms

(1) Timings maintain compatibility to the ADC module. The 2802x ADC supports driving all 3 bits at the same time t_d(PWD)ms before first

conversion.

ADCPWDN/

ADCBGPWD/

ADCREFPWD/

ADCENABLE

t_d(PWD)

Request for ADC

Conversion

Figure 6-19. ADC Conversion Timing

Detailed Description

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R_on

3.4 kW

Switch

R_s

ADCIN

C_p

C_h

Source

Signal

ac

5 pF

1.6 pF

28x DSP

Typical Values of the Input Circuit Components:

Switch Resistance (R_on): 3.4 kW

Sampling Capacitor (C_h): 1.6 pF

Parasitic Capacitance (C_p): 5 pF

Source Resistance (R_s): 50 W

Figure 6-20. ADC Input Impedance Model

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6.9.1.1.3.3 ADC Sequential and Simultaneous Timings

Analog Input

SOC0 Sample

Window

SOC1 Sample

Window

SOC2 Sample

Window

0

2

9

15

22 24

37

ADCCLK

ADCCTL 1.INTPULSEPOS

ADCSOCFLG 1.SOC0

ADCSOCFLG 1.SOC1

ADCSOCFLG 1.SOC2

S/H Window Pulse to Core

ADCRESULT 0

SOC0

SOC1

SOC2

Result 0 Latched

2 ADCCLKs

ADCRESULT 1

EOC0 Pulse

EOC1 Pulse

ADCINTFLG.ADCINTx

Minimum

7 ADCCLKs

Conversion 0

13 ADC Clocks

1 ADCCLK

6

Minimum

ADCCLKs 7 ADCCLKs

Conversion 1

13 ADC Clocks

Figure 6-21. Timing Example for Sequential Mode / Late Interrupt Pulse

Detailed Description

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Analog Input

SOC0 Sample

Window

SOC1 Sample

Window

SOC2 Sample

Window

0

2

9

15

22 24

37

ADCCLK

ADCCTL1.INTPULSEPOS

ADCSOCFLG 1.SOC0

ADCSOCFLG 1.SOC1

ADCSOCFLG 1.SOC2

S/H Window Pulse to Core

ADCRESULT 0

SOC0

SOC1

SOC2

Result 0 Latched

ADCRESULT 1

EOC0 Pulse

EOC1 Pulse

EOC2 Pulse

ADCINTFLG.ADCINTx

Minimum

7 ADCCLKs

Conversion 0

13 ADC Clocks

2 ADCCLKs

6

Minimum

ADCCLKs 7 ADCCLKs

Conversion 1

13 ADC Clocks

Figure 6-22. Timing Example for Sequential Mode / Early Interrupt Pulse

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Analog Input A

Analog Input B

SOC0 Sample

A Window

SOC2 Sample

A Window

SOC0 Sample

B Window

SOC2 Sample

B Window

0

2

9

22 24

37

50

ADCCLK

ADCCTL1.INTPULSEPOS

ADCSOCFLG 1.SOC0

ADCSOCFLG 1.SOC1

ADCSOCFLG 1.SOC2

S/H Window Pulse to Core

ADCRESULT 0

SOC0 (A/B)

SOC2 (A/B)

Result 0 (A) Latched

2 ADCCLKs

ADCRESULT 1

Result 0 (B) Latched

ADCRESULT 2

EOC0 Pulse

EOC1 Pulse

1 ADCCLK

EOC2 Pulse

ADCINTFLG .ADCINTx

Minimum

7 ADCCLKs

Conversion 0 (A)

13 ADC Clocks

Conversion 0 (B)

13 ADC Clocks

2 ADCCLKs

19

ADCCLKs

Minimum

7 ADCCLKs

Conversion 1 (A)

13 ADC Clocks

Figure 6-23. Timing Example for Simultaneous Mode / Late Interrupt Pulse

Detailed Description

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Analog Input A

SOC0 Sample

A Window

SOC2 Sample

A Window

Analog Input B

SOC0 Sample

B Window

SOC2 Sample

B Window

0

2

9

22 24

37

50

ADCCLK

ADCCTL1.INTPULSEPOS

ADCSOCFLG1.SOC0

ADCSOCFLG1.SOC1

ADCSOCFLG1.SOC2

S/H Window Pulse to Core

ADCRESULT 0

SOC0 (A/B)

SOC2 (A/B)

Result 0 (A) Latched

2 ADCCLKs

Result 0 (B) Latched

ADCRESULT 1

ADCRESULT 2

EOC0 Pulse

EOC1 Pulse

EOC2 Pulse

ADCINTFLG.ADCINTx

Conversion 0 (A)

13 ADC Clocks

Conversion 0 (B)

13 ADC Clocks

Minimum

2 ADCCLKs

7 ADCCLKs

19

Minimum

7 ADCCLKs

Conversion 1 (A)

13 ADC Clocks

ADCCLKs

Figure 6-24. Timing Example for Simultaneous Mode / Early Interrupt Pulse

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6.9.1.2 ADC MUX

To COMPy A or B input

To ADC Channel X

Logic implemented in GPIO MUX block

AIOx Pin

SYSCLK

AIOxIN

1

AIOxINE

AIODAT Reg

(Read)

SYNC

0

AIODAT Reg

(Latch)

AIOMUX 1 Reg

AIOSET,

AIOCLEAR,

AIOTOGGLE

Regs

AIODIR Reg

(Latch)

1

(0 = Input, 1 = Output)

0

Figure 6-25. AIOx Pin Multiplexing

The ADC channel and Comparator functions are always available. The digital I/O function is available only

when the respective bit in the AIOMUX1 register is 0. In this mode, reading the AIODAT register reflects

the actual pin state.

The digital I/O function is disabled when the respective bit in the AIOMUX1 register is 1. In this mode,

reading the AIODAT register reflects the output latch of the AIODAT register and the input digital I/O buffer

is disabled to prevent analog signals from generating noise.

On reset, the digital function is disabled. If the pin is used as an analog input, users should keep the AIO

function disabled for that pin.

Detailed Description

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6.9.1.3 Comparator Block

Figure 6-26 shows the interaction of the Comparator modules with the rest of the system.

COMP x A

+

COMP x B

COMP

TZ1/2/3

-

GPIO

MUX

COMP x

+

DAC x

Wrapper

ePWM

AIO

MUX

COMPxOUT

DAC

Core

10-Bit

Figure 6-26. Comparator Block Diagram

Table 6-30. Comparator Control Registers

COMP1

ADDRESS

COMP2

SIZE

(x16)

EALLOW

PROTECTED

REGISTER NAME

COMPCTL

DESCRIPTION

ADDRESS⁽¹⁾

0x6400

0x6402

0x6404

0x6406

0x6420

0x6422

0x6424

0x6426

1

Yes

No

Comparator Control Register

Comparator Status Register

DAC Control Register

COMPSTS

DACCTL

DACVAL

Yes

No

DAC Value Register

RAMPMAXREF_ACTIVE

RAMPMAXREF_SHDW

RAMPDECVAL_ACTIVE

RAMPDECVAL_SHDW

RAMPSTS

Ramp Generator Maximum

Reference (Active) Register

0x6408

0x640A

0x640C

0x6428

0x642A

0x642C

1

No

Ramp Generator Maximum

Reference (Shadow) Register

Ramp Generator Decrement Value

(Active) Register

Ramp Generator Decrement Value

(Shadow) Register

0x640E

0x6410

0x642E

0x6430

1

No

Ramp Generator Status Register

(1) Comparator 2 is available only on the 48-pin PT package.

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6.9.1.3.1 On-Chip Comparator/DAC Electrical Data/Timing

Table 6-31. Electrical Characteristics of the Comparator/DAC

PARAMETER

MIN

TYP

MAX

UNITS

Comparator

Comparator Input Range

V_SSA– V_DDA

V

Comparator response time to PWM Trip Zone (Async)

30

±5

35

ns

Input Offset

Input Hysteresis⁽¹⁾

mV

DAC

DAC Output Range

DAC resolution

DAC settling time

DAC Gain

V_SSA– V_DDA

V

10

bits

See Figure 6-27

–1.5%

10

DAC Offset

Monotonic

mV

Yes

±3

INL

LSB

(1) Hysteresis on the comparator inputs is achieved with a Schmidt trigger configuration. This results in an effective 100-kΩ feedback

resistance between the output of the comparator and the noninverting input of the comparator. There is an option to disable the

hysteresis and, with it, the feedback resistance; see the Analog-to-Digital Converter and Comparator chapter in the

TMS320F2802x,TMS320F2802xx Piccolo Technical Reference Manual for more information on this option if needed in your system.

1100

1000

900

800

700

600

500

400

300

200

100

0

50

100

150

200

250

300

350

400

450

500

DAC Step Size (Codes)

DAC Accuracy

15 Codes

7 Codes

3 Codes

1 Code

Figure 6-27. DAC Settling Time

Detailed Description

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6.9.2 Detailed Descriptions

Integral Nonlinearity

Integral nonlinearity refers to the deviation of each individual code from a line drawn from zero to full

scale. The point used as zero occurs one-half LSB before the first code transition. The full-scale point is

defined as level one-half LSB beyond the last code transition. The deviation is measured from the center

of each particular code to the true straight line between these two points.

Differential Nonlinearity

An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal

value. A differential nonlinearity error of less than ±1 LSB ensures no missing codes.

Zero Offset

The major carry transition should occur when the analog input is at zero volts. Zero error is defined as the

deviation of the actual transition from that point.

Gain Error

The first code transition should occur at an analog value one-half LSB above negative full scale. The last

transition should occur at an analog value one and one-half LSB below the nominal full scale. Gain error is

the deviation of the actual difference between first and last code transitions and the ideal difference

between first and last code transitions.

Signal-to-Noise Ratio + Distortion (SINAD)

SINAD is the ratio of the rms value of the measured input signal to the rms sum of all other spectral

components below the Nyquist frequency, including harmonics but excluding dc. The value for SINAD is

expressed in decibels.

Effective Number of Bits (ENOB)

For a sine wave, SINAD can be expressed in terms of the number of bits. Using the following formula,

(SINAD -1.76)

N =

6.02

it is possible to get a measure of performance expressed as N, the effective number of

bits. Thus, effective number of bits for a device for sine wave inputs at a given input frequency can be

calculated directly from its measured SINAD.

Total Harmonic Distortion (THD)

THD is the ratio of the rms sum of the first nine harmonic components to the rms value of the measured

input signal and is expressed as a percentage or in decibels.

Spurious Free Dynamic Range (SFDR)

SFDR is the difference in dB between the rms amplitude of the input signal and the peak spurious signal.

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6.9.3 Serial Peripheral Interface (SPI) Module

The device includes the four-pin serial peripheral interface (SPI) module. One SPI module (SPI-A) is

available. The SPI is a high-speed, synchronous serial I/O port that allows a serial bit stream of

programmed length (1 to 16 bits) to be shifted into and out of the device at a programmable bit-transfer

rate. Normally, the SPI is used for communications between the MCU and external peripherals or another

processor. Typical applications include external I/O or peripheral expansion through devices such as shift

registers, display drivers, and ADCs. Multidevice communications are supported by the master/slave

operation of the SPI.

The SPI module features include:

•

Four external pins:

–

SPISOMI: SPI slave-output/master-input pin

SPISIMO: SPI slave-input/master-output pin

SPISTE: SPI slave transmit-enable pin

SPICLK: SPI serial-clock pin

NOTE

All four pins can be used as GPIO if the SPI module is not used.

•

Two operational modes: master and slave

Baud rate: 125 different programmable rates.

LSPCLK

Baud rate =

when SPIBRR = 3 to127

when SPIBRR = 0,1, 2

(SPIBRR + 1)

LSPCLK

Baud rate =

4

•

Data word length: 1 to 16 data bits

Four clocking schemes (controlled by clock polarity and clock phase bits) include:

–

Falling edge without phase delay: SPICLK active-high. SPI transmits data on the falling edge of the

SPICLK signal and receives data on the rising edge of the SPICLK signal.

Falling edge with phase delay: SPICLK active-high. SPI transmits data one half-cycle ahead of the

falling edge of the SPICLK signal and receives data on the falling edge of the SPICLK signal.

Rising edge without phase delay: SPICLK inactive-low. SPI transmits data on the rising edge of the

SPICLK signal and receives data on the falling edge of the SPICLK signal.

Rising edge with phase delay: SPICLK inactive-low. SPI transmits data one half-cycle ahead of the

rising edge of the SPICLK signal and receives data on the rising edge of the SPICLK signal.

•

Simultaneous receive and transmit operation (transmit function can be disabled in software)

Transmitter and receiver operations are accomplished through either interrupt-driven or polled

algorithms.

•

Nine SPI module control registers: In control register frame beginning at address 7040h.

NOTE

All registers in this module are 16-bit registers that are connected to Peripheral Frame 2.

When a register is accessed, the register data is in the lower byte (7–0), and the upper byte

(15–8) is read as zeros. Writing to the upper byte has no effect.

Detailed Description

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Enhanced feature:

•

4-level transmit/receive FIFO

Delayed transmit control

Bidirectional 3 wire SPI mode support

The SPI port operation is configured and controlled by the registers listed in Table 6-32.

Table 6-32. SPI-A Registers

NAME

SPICCR

ADDRESS

0x7040

0x7041

0x7042

0x7044

0x7046

0x7047

0x7048

0x7049

0x704A

0x704B

0x704C

0x704F

SIZE (x16) EALLOW PROTECTED

DESCRIPTION⁽¹⁾

SPI-A Configuration Control Register

SPI-A Operation Control Register

SPI-A Status Register

1

No

SPICTL

SPISTS

SPIBRR

SPI-A Baud Rate Register

SPIRXEMU

SPIRXBUF

SPITXBUF

SPIDAT

SPI-A Receive Emulation Buffer Register

SPI-A Serial Input Buffer Register

SPI-A Serial Output Buffer Register

SPI-A Serial Data Register

SPIFFTX

SPIFFRX

SPIFFCT

SPIPRI

SPI-A FIFO Transmit Register

SPI-A FIFO Receive Register

SPI-A FIFO Control Register

SPI-A Priority Control Register

(1) Registers in this table are mapped to Peripheral Frame 2. This space only allows 16-bit accesses. 32-bit accesses produce undefined

results.

For more information on the SPI, see the Serial Peripheral Interface (SPI) chapter in the

TMS320F2802x,TMS320F2802xx Piccolo Technical Reference Manual.

88

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Figure 6-28 is a block diagram of the SPI in slave mode.

SPIFFENA

Overrun

INT ENA

Receiver

Overrun Flag

SPIFFTX.14

SPISTS.7

RX FIFO Registers

SPICTL.4

SPIRXBUF

RX FIFO _0

RX FIFO _1

-----

SPIINT

RX FIFO Interrupt

RX Interrupt

Logic

RX FIFO _3

16

SPIRXBUF

Buffer Register

SPIFFOVF

FLAG

SPIFFRX.15

To CPU

TX FIFO Registers

SPITXBUF

TX FIFO _3

TX Interrupt

Logic

TX FIFO Interrupt

-----

TX FIFO _1

SPITX

TX FIFO _0

16

SPI INT

ENA

16

SPI INT FLAG

SPITXBUF

Buffer Register

SPISTS.6

SPICTL.0

TRIWIRE

SPIPRI.0

16

M

S

M

SPIDAT

Data Register

TW

S

SW1

SW2

SPISIMO

M

S

TW

SPIDAT.15 - 0

M

TW

S

SPISOMI

SPISTE

Talk

SPICTL.1

State Control

Master/Slave

SPICTL.2

SPI Char

LSPCLK

SPICCR.3 - 0

S

SW3

3

2

1

0

Clock

Polarity

Clock

Phase

M

S

SPI Bit Rate

SPIBRR.6 - 0

SPICCR.6

SPICTL.3

SPICLK

M

6

5

4

3

2

1

0

A. SPISTE is driven low by the master for a slave device.

Figure 6-28. SPI Module Block Diagram (Slave Mode)

Detailed Description

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6.9.3.1 SPI Master Mode Electrical Data/Timing

Table 6-33 lists the master mode timing (clock phase = 0) and Table 6-34 lists the master mode timing

(clock phase = 1). Figure 6-29 and Figure 6-30 show the timing waveforms.

Table 6-33. SPI Master Mode External Timing (Clock Phase = 0)^{(1)(2)(3)(4)(5)}

BRR EVEN

MIN

BRR ODD

MIN

NO.

PARAMETER

UNIT

MAX

1

2

t_c(SPC)M

Cycle time, SPICLK

4t_c(LSPCLK)

128t_c(LSPCLK)

5t_c(LSPCLK)

0.5t_c(SPC)M

127t_c(LSPCLK)

ns

Pulse duration, SPICLK first

pulse

+

0.5t_c(SPC)M

+

t_w(SPC1)M

0.5t_c(SPC)M– 10

0.5t_c(SPC)M+ 10

10

0.5t_c(LSPCLK)– 10

0.5t_c(LSPCLK)+ 10

Pulse duration, SPICLK second

pulse

0.5t_c(SPC)M

–

0.5t_c(SPC)M

–

3

4

t_w(SPC2)M

t_d(SIMO)M

t_v(SIMO)M

t_su(SOMI)M

t_h(SOMI)M

t_d(SPC)M

t_d(STE)M

0.5t_c(SPC)M– 10

ns

0.5t_c(LSPCLK)– 10

0.5t_c(LSPCLK)+ 10

Delay time, SPICLK to

SPISIMO valid

10

Valid time, SPISIMO valid after

SPICLK

0.5t_c(SPC)M

–

5

0.5t_c(SPC)M– 10

0.5t_c(LSPCLK)– 10

Setup time, SPISOMI before

SPICLK

8

26

0

26

Hold time, SPISOMI valid after

SPICLK

9

0

Delay time, SPISTE active to

SPICLK

0.5t_c(SPC)M

–

23

24

t_c(SPC)M– 10

0.5t_c(SPC)M– 10

0.5t_c(LSPCLK)– 10

Delay time, SPICLK to SPISTE

inactive

0.5t_c(SPC)M

–

0.5t_c(LSPCLK)– 10

(1) The MASTER / SLAVE bit (SPICTL.2) is set and the CLOCK PHASE bit (SPICTL.3) is cleared.

(2) t_c(SPC)= SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR +1)

(3) t_c(LCO)= LSPCLK cycle time

(4) Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate:

Master mode transmit 25-MHz MAX, master mode receive 12.5-MHz MAX

Slave mode transmit 12.5-MAX, slave mode receive 12.5-MHz MAX.

(5) The active edge of the SPICLK signal referenced is controlled by the clock polarity bit (SPICCR.6).

1

SPICLK

(clock polarity = 0)

2

3

SPICLK

(clock polarity = 1)

4

5

SPISIMO

Master Out Data Is Valid

8

9

Master In Data

Must Be Valid

SPISOMI

SPISTE

24

23

Figure 6-29. SPI Master Mode External Timing (Clock Phase = 0)

90

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Table 6-34. SPI Master Mode External Timing (Clock Phase = 1)^{(1)(2)(3)(4)(5)}

BRR EVEN

BRR ODD

NO.

PARAMETER

UNIT

MIN

MAX

MIN

MAX

1

2

t_c(SPC)M

Cycle time, SPICLK

4t_c(LSPCLK)

128t_c(LSPCLK)

5t_c(LSPCLK)

127t_c(LSPCLK)

ns

Pulse duration, SPICLK first

pulse

0.5t_c(SPC)M

–

0.5t_c(SPC)M

–

t_w(SPC1)M

t_w(SPC2)M

t_d(SIMO)M

t_v(SIMO)M

t_su(SOMI)M

t_h(SOMI)M

t_d(SPC)M

0.5t_c(SPC)M– 10

26

0.5t_c(SPC)M+ 10

0.5t_c(LSPCLK)– 10

0.5t_c(LSPCLK)+ 10

Pulse duration, SPICLK second

pulse

0.5t_c(SPC)M

+

0.5t_c(SPC)M

+

3

6

ns

0.5t_c(LSPCLK)– 10

0.5t_c(LSPCLK)+ 10

Delay time, SPISIMO valid to

SPICLK

0.5t_c(SPC)M

+

0.5t_c(LSPCLK)– 10

Valid time, SPISIMO valid after

SPICLK

0.5t_c(SPC)M

–

7

0.5t_c(LSPCLK)– 10

Setup time, SPISOMI before

SPICLK

10

11

23

24

26

Hold time, SPISOMI valid after

SPICLK

0

Delay time, SPISTE active to

SPICLK

t_c(SPC)– 10

0.5t_c(SPC)– 10

t_c(SPC)– 10

Delay time, SPICLK to SPISTE

inactive

0.5t_c(SPC)

–

t_d(STE)M

0.5t_c(LSPCLK)– 10

(1) The MASTER/SLAVE bit (SPICTL.2) is set and the CLOCK PHASE bit (SPICTL.3) is set.

(2) t_c(SPC)= SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR + 1)

(3) Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate:

Master mode transmit 25 MHz MAX, master mode receive 12.5 MHz MAX

Slave mode transmit 12.5 MHz MAX, slave mode receive 12.5 MHz MAX.

(4) t_c(LCO)= LSPCLK cycle time

(5) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).

1

SPICLK

(clock polarity = 0)

2

3

SPICLK

(clock polarity = 1)

6

7

SPISIMO

Master Out Data Is Valid

10

11

Master In Data Must

Be Valid

SPISOMI

SPISTE

24

23

Figure 6-30. SPI Master Mode External Timing (Clock Phase = 1)

Detailed Description

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6.9.3.2 SPI Slave Mode Electrical Data/Timing

Table 6-35 lists the slave mode timing (clock phase = 0) and Table 6-36 lists the slave mode timing (clock

phase = 1). Figure 6-31 and Figure 6-32 show the timing waveforms.

Table 6-35. SPI Slave Mode External Timing (Clock Phase = 0)^{(1)(2)(3)(4)(5)}

NO.

PARAMETER

Cycle time, SPICLK

MIN

4t_c(SYSCLK)

MAX UNIT

12 t_c(SPC)S

13 t_w(SPC1)S

14 t_w(SPC2)S

15 t_d(SOMI)S

16 t_v(SOMI)S

19 t_su(SIMO)S

20 t_h(SIMO)S

25 t_su(STE)S

26 t_h(STE)S

ns

Pulse duration, SPICLK first pulse

2t_c(SYSCLK)– 1

Pulse duration, SPICLK second pulse

Delay time, SPICLK to SPISOMI valid

Valid time, SPISOMI data valid after SPICLK

Setup time, SPISIMO valid before SPICLK

Hold time, SPISIMO data valid after SPICLK

Setup time, SPISTE active before SPICLK

Hold time, SPISTE inactive after SPICLK

21

ns

0

1.5t_c(SYSCLK)

(1) The MASTER / SLAVE bit (SPICTL.2) is cleared and the CLOCK PHASE bit (SPICTL.3) is cleared.

(2) t_c(SPC)= SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR + 1)

(3) Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate:

Master mode transmit 25-MHz MAX, master mode receive 12.5-MHz MAX

Slave mode transmit 12.5-MHz MAX, slave mode receive 12.5-MHz MAX.

(4) t_c(LCO)= LSPCLK cycle time

(5) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).

12

SPICLK

(clock polarity = 0)

13

14

SPICLK

(clock polarity = 1)

15

16

SPISOMI

SPISOMI Data Is Valid

19

20

SPISIMO Data

Must Be Valid

SPISIMO

SPISTE

25

26

Figure 6-31. SPI Slave Mode External Timing (Clock Phase = 0)

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Table 6-36. SPI Slave Mode External Timing (Clock Phase = 1)^(1)(2)(3)(4)

NO.

PARAMETER

Cycle time, SPICLK

MIN

4t_c(SYSCLK)

MAX UNIT

12 t_c(SPC)S

13 t_w(SPC1)S

14 t_w(SPC2)S

17 t_d(SOMI)S

18 t_v(SOMI)S

21 t_su(SIMO)S

22 t_h(SIMO)S

25 t_su(STE)S

26 t_h(STE)S

ns

Pulse duration, SPICLK first pulse

2t_c(SYSCLK)– 1

Pulse duration, SPICLK second pulse

Delay time, SPICLK to SPISOMI valid

Valid time, SPISOMI data valid after SPICLK

Setup time, SPISIMO valid before SPICLK

Hold time, SPISIMO data valid after SPICLK

Setup time, SPISTE active before SPICLK

Hold time, SPISTE inactive after SPICLK

21

ns

0

1.5t_c(SYSCLK)

(1) The MASTER / SLAVE bit (SPICTL.2) is cleared and the CLOCK PHASE bit (SPICTL.3) is cleared.

(2) t_c(SPC)= SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR + 1)

(3) Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate:

Master mode transmit 25-MHz MAX, master mode receive 12.5-MHz MAX

Slave mode transmit 12.5-MHz MAX, slave mode receive 12.5-MHz MAX.

(4) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).

12

SPICLK

(clock polarity = 0)

13

14

SPICLK

(clock polarity = 1)

17

SPISOMI

SPISOMI Data Is Valid

Data Valid

18

21

22

SPISIMO Data

Must Be Valid

SPISIMO

SPISTE

26

25

Figure 6-32. SPI Slave Mode External Timing (Clock Phase = 1)

Detailed Description

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6.9.4 Serial Communications Interface (SCI) Module

The devices include one serial communications interface (SCI) module (SCI-A). The SCI module supports

digital communications between the CPU and other asynchronous peripherals that use the standard

nonreturn-to-zero (NRZ) format. The SCI receiver and transmitter are double-buffered, and each has its

own separate enable and interrupt bits. Both can be operated independently or simultaneously in the full-

duplex mode. To ensure data integrity, the SCI checks received data for break detection, parity, overrun,

and framing errors. The bit rate is programmable to over 65000 different speeds through a 16-bit baud-

select register.

Features of each SCI module include:

•

Two external pins:

–

SCITXD: SCI transmit-output pin

SCIRXD: SCI receive-input pin

NOTE

Both pins can be used as GPIO if not used for SCI.

–

Baud rate programmable to 64K different rates:

LSPCLK

Baud rate =

when BRR ¹ 0

when BRR = 0

(BRR + 1) * 8

LSPCLK

Baud rate =

16

•

Data-word format

–

One start bit

Data-word length programmable from 1 to 8 bits

Optional even/odd/no parity bit

One or 2 stop bits

•

Four error-detection flags: parity, overrun, framing, and break detection

Two wake-up multiprocessor modes: idle-line and address bit

Half- or full-duplex operation

Double-buffered receive and transmit functions

Transmitter and receiver operations can be accomplished through interrupt-driven or polled algorithms

with status flags.

–

Transmitter: TXRDY flag (transmitter-buffer register is ready to receive another character) and TX

EMPTY flag (transmitter-shift register is empty)

–

Receiver: RXRDY flag (receiver-buffer register is ready to receive another character), BRKDT flag

(break condition occurred), and RX ERROR flag (monitoring four interrupt conditions)

•

Separate enable bits for transmitter and receiver interrupts (except BRKDT)

NRZ (nonreturn-to-zero) format

NOTE

All registers in this module are 8-bit registers that are connected to Peripheral Frame 2.

When a register is accessed, the register data is in the lower byte (7–0), and the upper byte

(15–8) is read as zeros. Writing to the upper byte has no effect.

Enhanced features:

•

Auto baud-detect hardware logic

4-level transmit/receive FIFO

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The SCI port operation is configured and controlled by the registers listed in Table 6-37.

Table 6-37. SCI-A Registers⁽¹⁾

EALLOW

SIZE (x16)

NAME

ADDRESS

DESCRIPTION

PROTECTED

SCICCRA

0x7050

0x7051

0x7052

0x7053

0x7054

0x7055

0x7056

0x7057

0x7059

0x705A

0x705B

0x705C

0x705F

1

No

SCI-A Communications Control Register

SCI-A Control Register 1

SCICTL1A

SCIHBAUDA

SCILBAUDA

SCICTL2A

SCI-A Baud Register, High Bits

SCI-A Baud Register, Low Bits

SCI-A Control Register 2

SCIRXSTA

SCIRXEMUA

SCIRXBUFA

SCITXBUFA

SCIFFTXA⁽²⁾

SCIFFRXA⁽²⁾

SCIFFCTA⁽²⁾

SCIPRIA

SCI-A Receive Status Register

SCI-A Receive Emulation Data Buffer Register

SCI-A Receive Data Buffer Register

SCI-A Transmit Data Buffer Register

SCI-A FIFO Transmit Register

SCI-A FIFO Receive Register

SCI-A FIFO Control Register

SCI-A Priority Control Register

(1) Registers in this table are mapped to Peripheral Frame 2 space. This space only allows 16-bit accesses. 32-bit accesses produce

undefined results.

(2) These registers are new registers for the FIFO mode.

Detailed Description

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For more information on the SCI, see the Serial Communications Interface (SCI) chapter in the

TMS320F2802x,TMS320F2802xx Piccolo Technical Reference Manual.

Figure 6-33 shows the SCI module block diagram.

SCICTL1.1

SCITXD

Frame Format and Mode

SCITXD

TXSHF

Register

TXENA

Parity

Even/Odd Enable

TX EMPTY

SCICTL2.6

8

SCICCR.6 SCICCR.5

TXRDY

TX INT ENA

SCICTL2.0

Transmitter-Data

Buffer Register

SCICTL2.7

TXWAKE

SCICTL1.3

1

8

TX FIFO _0

TX FIFO

Interrupts

TXINT

TX Interrupt

Logic

TX FIFO _1

-----

To CPU

TX FIFO _3

SCI TX Interrupt select logic

SCITXBUF.7-0

WUT

TX FIFO registers

SCIFFENA

AutoBaud Detect logic

SCIFFTX.14

SCIHBAUD. 15 - 8

SCIRXD

RXSHF

Register

Baud Rate

MSbyte

Register

SCIRXD

RXWAKE

LSPCLK

SCIRXST.1

SCILBAUD. 7 - 0

RXENA

SCICTL1.0

8

Baud Rate

LSbyte

Register

SCICTL2.1

Receive Data

Buffer register

SCIRXBUF.7-0

RXRDY

RX/BK INT ENA

SCIRXST.6

8

RX FIFO _3

BRKDT

SCIRXST.5

-----

RX FIFO

Interrupts

RX FIFO_1

RX FIFO _0

RXINT

RX Interrupt

Logic

SCIRXBUF.7-0

RX FIFO registers

To CPU

RXFFOVF

SCIRXST.7 SCIRXST.4 - 2

SCIFFRX.15

RX Error

FE OE PE

RX Error

RX ERR INT ENA

SCICTL1.6

SCI RX Interrupt select logic

Figure 6-33. Serial Communications Interface (SCI) Module Block Diagram

96

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6.9.5 Inter-Integrated Circuit (I2C)

The device contains one I2C Serial Port. Figure 6-34 shows how the I2C peripheral module interfaces

within the device.

The I2C module has the following features:

•

Compliance with the Philips Semiconductors I²C-bus specification (version 2.1):

–

Support for 1-bit to 8-bit format transfers

7-bit and 10-bit addressing modes

General call

START byte mode

Support for multiple master-transmitters and slave-receivers

Support for multiple slave-transmitters and master-receivers

Combined master transmit/receive and receive/transmit mode

Data transfer rate of from 10 kbps up to 400 kbps (I2C Fast-mode rate)

•

One 4-word receive FIFO and one 4-word transmit FIFO

One interrupt that can be used by the CPU. This interrupt can be generated as a result of one of the

following conditions:

–

Transmit-data ready

Receive-data ready

Register-access ready

No-acknowledgment received

Arbitration lost

Stop condition detected

Addressed as slave

•

An additional interrupt that can be used by the CPU when in FIFO mode

Module enable/disable capability

Free data format mode

For more information on the I2C, see the Inter-Integrated Circuit Module (I2C) chapter in the

TMS320F2802x,TMS320F2802xx Piccolo Technical Reference Manual.

Detailed Description

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I2C Module

I2CXSR

I2CDXR

TX FIFO

RX FIFO

FIFO Interrupt to

CPU/PIE

SDA

Peripheral Bus

I2CRSR

I2CDRR

Control/Status

Registers

CPU

Clock

Synchronizer

SCL

Prescaler

Noise Filters

Arbitrator

Interrupt to

CPU/PIE

I2C INT

A. The I2C registers are accessed at the SYSCLKOUT rate. The internal timing and signal waveforms of the I2C port are

also at the SYSCLKOUT rate.

B. The clock enable bit (I2CAENCLK) in the PCLKCRO register turns off the clock to the I2C port for low-power

operation. Upon reset, I2CAENCLK is clear, which indicates the peripheral internal clocks are off.

Figure 6-34. I2C Peripheral Module Interfaces

The registers in Table 6-38 configure and control the I2C port operation.

Table 6-38. I2C-A Registers

EALLOW

PROTECTED

NAME

ADDRESS

DESCRIPTION

I2C own address register

I2COAR

I2CIER

0x7900

0x7901

0x7902

0x7903

0x7904

0x7905

0x7906

0x7907

0x7908

0x7909

0x790A

0x790C

0x7920

0x7921

–

No

I2C interrupt enable register

I2C status register

I2CSTR

I2CCLKL

I2CCLKH

I2CCNT

I2CDRR

I2CSAR

I2CDXR

I2CMDR

I2CISRC

I2CPSC

I2CFFTX

I2CFFRX

I2CRSR

I2CXSR

I2C clock low-time divider register

I2C clock high-time divider register

I2C data count register

I2C data receive register

I2C slave address register

I2C data transmit register

I2C mode register

I2C interrupt source register

I2C prescaler register

I2C FIFO transmit register

I2C FIFO receive register

I2C receive shift register (not accessible to the CPU)

I2C transmit shift register (not accessible to the CPU)

–

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6.9.5.1 I2C Electrical Data/Timing

Table 6-39 shows the I2C timing requirements. Table 6-40 shows the I2C switching characteristics.

Table 6-39. I2C Timing Requirements

MIN

MAX

UNIT

Hold time, START condition, SCL fall delay

after SDA fall

t_{h(SDA-SCL)START}

t_{su(SCL-SDA)START}

0.6

µs

Setup time, Repeated START, SCL rise before

SDA fall delay

0.6

µs

t_h(SCL-DAT)

t_su(DAT-SCL)

t_r(SDA)

Hold time, data after SCL fall

Setup time, data before SCL rise

Rise time, SDA

0

100

20

µs

ns

Input tolerance

300

t_r(SCL)

Rise time, SCL

20

t_f(SDA)

Fall time, SDA

11.4

t_f(SCL)

Fall time, SCL

Setup time, STOP condition, SCL rise before

SDA rise delay

t_{su(SCL-SDA)STOP}

0.6

µs

Table 6-40. I2C Switching Characteristics

over recommended operating conditions (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

MAX

400

UNIT

I2C clock module frequency is from 7 MHz to

12 MHz and I2C prescaler and clock divider

registers are configured appropriately.

f_SCL

SCL clock frequency

kHz

V_il

Low level input voltage

High level input voltage

Input hysteresis

0.3 V_DDIO

V

V_ih

V_hys

V_ol

0.7 V_DDIO

0.05 V_DDIO

0

Low level output voltage

3-mA sink current

0.4

I2C clock module frequency is from 7 MHz to

12 MHz and I2C prescaler and clock divider

registers are configured appropriately.

t_LOW

Low period of SCL clock

High period of SCL clock

1.3

μs

I2C clock module frequency is from 7 MHz to

12 MHz and I2C prescaler and clock divider

registers are configured appropriately.

t_HIGH

0.6

μs

Input current with an input voltage from

0.1 V_DDIOto 0.9 V_DDIOMAX

l_I

–10

10

μA

Detailed Description

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6.9.6 Enhanced PWM Modules (ePWM1/2/3/4)

The devices contain up to four enhanced PWM Modules (ePWM). Figure 6-35 shows a block diagram of

multiple ePWM modules. Figure 6-36 shows the signal interconnections with the ePWM. For more details,

see the Enhanced Pulse Width Modulator (ePWM) chapter in the TMS320F2802x,TMS320F2802xx

Piccolo Technical Reference Manual.

Table 6-41 shows the complete ePWM register set per module.

100

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EPWMSYNCI

EPWM1SYNCI

EPWM1B

EPWM1TZINT

EPWM1INT

ePWM1

Module

TZ1 to TZ3

EPWM2TZINT

EPWM2INT

PIE

CLOCKFAIL

TZ5

EMUSTOP

EPWMxTZINT

EPWMxINT

TZ6

EPWM1ENCLK

TBCLKSYNC

eCAPI

EPWM1SYNCO

EPWM2SYNCI

TZ1 to TZ3

COMPOUT1

COMPOUT2

EPWM2B

ePWM2

Module

COMP

CLOCKFAIL

EPWM1A

EPWM2A

TZ5

TZ6

EMUSTOP

H

R

P

W

M

EPWM2ENCLK

TBCLKSYNC

EPWMxA

G

P

I

EPWM2SYNCO

O

M

U

X

SOCA1

SOCB1

SOCA2

SOCB2

SOCAx

SOCBx

ADC

EPWMxSYNCI

EPWMxB

TZ1 to TZ3

ePWMx

Module

CLOCKFAIL

EMUSTOP

TZ5

TZ6

EPWMxENCLK

TBCLKSYNC

System Control

C28x CPU

SOCA1

SOCA2

SPCAx

ADCSOCAO

Pulse Stretch

(32 SYSCLKOUT Cycles, Active-Low Output)

SOCB1

SOCB2

SPCBx

ADCSOCBO

Pulse Stretch

(32 SYSCLKOUT Cycles, Active-Low Output)

Figure 6-35. ePWM

Detailed Description

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Time-Base (TB)

CTR=ZERO

Sync

In/Out

Select

Mux

TBPRD Shadow (24)

CTR=CMPB

TBPRDHR (8)

EPWMxSYNCO

Disabled

TBPRD Active (24)

8

CTR=PRD

TBCTL[SYNCOSEL]

TBCTL[PHSEN]

EPWMxSYNCI

DCAEVT1.sync

DCBEVT1.sync

Counter

Up/Down

(16 Bit)

TBCTL[SWFSYNC]

(Software Forced

Sync)

CTR=ZERO

CTR_Dir

TCBNT

Active (16)

CTR=PRD

CTR=ZERO

TBPHSHR (8)

EPWMxINT

CTR=PRD or ZERO

CTR=CMPA

Event

Trigger

and

Interrupt

(ET)

16

8

EPWMxSOCA

Phase

Control

CTR=CMPB

CTR_Dir

(A)

DCAEVT1.soc

(A)

TBPHS Active (24)

EPWMxSOCB

EPWMxSOCA

ADC

DCBEVT1.soc

EPWMxSOCB

Action

Qualifier

(AQ)

CTR=CMPA

CMPAHR (8)

16

High-resolution PWM (HRPWM)

CMPA Active (24)

CMPA Shadow (24)

EPWMxA

EPWMA

PWM

Chopper

(PC)

Trip

Zone

(TZ)

Dead

Band

(DB)

CTR=CMPB

16

CMPB Active (16)

EPWMB

EPWMxB

EPWMxTZINT

TZ1 to TZ3

CMPB Shadow (16)

EMUSTOP

CTR=ZERO

CLOCKFAIL

DCAEVT1.inter

DCBEVT1.inter

(A)

DCAEVT1.force

DCAEVT2.force

DCBEVT1.force

DCBEVT2.force

DCAEVT2.inter

DCBEVT2.inter

A. These events are generated by the Type 1 ePWM digital compare (DC) submodule based on the levels of

the COMPxOUT and TZ signals.

Figure 6-36. ePWM Submodules Showing Critical Internal Signal Interconnections

104

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6.9.6.1 ePWM Electrical Data/Timing

PWM refers to PWM outputs on ePWM1–4. Table 6-42 shows the PWM timing requirements and Table 6-

43, switching characteristics.

Table 6-42. ePWM Timing Requirements⁽¹⁾

MIN

2t_c(SCO)

MAX

UNIT

cycles

Asynchronous

Synchronous

t_w(SYCIN)

Sync input pulse width

2t_c(SCO)

With input qualifier

1t_c(SCO)+ t_w(IQSW)

(1) For an explanation of the input qualifier parameters, see Table 6-55.

Table 6-43. ePWM Switching Characteristics

over recommended operating conditions (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

33.33

MAX

UNIT

ns

t_w(PWM)

Pulse duration, PWMx output high/low

Sync output pulse width

t_w(SYNCOUT)

8t_c(SCO)

cycles

Delay time, trip input active to PWM forced high

Delay time, trip input active to PWM forced low

t_d(PWM)tza

no pin load

25

20

ns

t_d(TZ-PWM)HZ

Delay time, trip input active to PWM Hi-Z

6.9.6.2 Trip-Zone Input Timing

Table 6-44. Trip-Zone Input Timing Requirements⁽¹⁾

MIN

2t_c(TBCLK)

MAX UNIT

cycles

Asynchronous

t_w(TZ)

Pulse duration, TZx input low

Synchronous

2t_c(TBCLK)

cycles

With input qualifier

2t_c(TBCLK)+ t_w(IQSW)

cycles

(1) For an explanation of the input qualifier parameters, see Table 6-55.

SYSCLK

t_w(TZ)

TZ^(A)

t_d(TZ-PWM)HZ

PWM^(B)

A. TZ - TZ1, TZ2, TZ3

B. PWM refers to all the PWM pins in the device. The state of the PWM pins after TZ is taken high depends on the PWM

recovery software.

Figure 6-37. PWM Hi-Z Characteristics

Detailed Description

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6.9.7 High-Resolution PWM (HRPWM)

This module combines multiple delay lines in a single module and a simplified calibration system by using

a dedicated calibration delay line. For each ePWM module there is one HR delay line.

The HRPWM module offers PWM resolution (time granularity) that is significantly better than what can be

achieved using conventionally derived digital PWM methods. The key points for the HRPWM module are:

•

Significantly extends the time resolution capabilities of conventionally derived digital PWM

This capability can be used in both single edge (duty cycle and phase-shift control) as well as dual

edge control for frequency/period modulation.

•

Finer time granularity control or edge positioning is controlled through extensions to the Compare A

and Phase registers of the ePWM module.

HRPWM capabilities, when available on a particular device, are offered only on the A signal path of an

ePWM module (that is, on the EPWMxA output). EPWMxB output has conventional PWM capabilities.

NOTE

The minimum SYSCLKOUT frequency allowed for HRPWM is 50 MHz.

NOTE

When dual-edge high-resolution is enabled (high-resolution period mode), the PWMxB output

is not available for use.

6.9.7.1 HRPWM Electrical Data/Timing

Table 6-45 shows the high-resolution PWM switching characteristics.

Table 6-45. High-Resolution PWM Characteristics at SYSCLKOUT = 50 MHz⁽¹⁾–60 MHz

PARAMETER

MIN

TYP

MAX UNIT

310 ps

Micro Edge Positioning (MEP) step size⁽²⁾

150

(1) The HRPWM operates at a minimum SYSCLKOUT frequency of 50 MHz. Below 50 MHz, with device process variation, the MEP step

size may decrease under cold temperature and high core voltage conditions to such a point that 255 MEP steps will not span an entire

SYSCLKOUT cycle.

(2) The MEP step size will be largest at high temperature and minimum voltage on V_DD. MEP step size will increase with higher

temperature and lower voltage and decrease with lower temperature and higher voltage.

Applications that use the HRPWM feature should use MEP Scale Factor Optimizer (SFO) estimation software functions. See the TI

software libraries for details of using SFO function in end applications. SFO functions help to estimate the number of MEP steps per

SYSCLKOUT period dynamically while the HRPWM is in operation.

106

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6.9.8 Enhanced Capture Module (eCAP1)

The device contains an enhanced capture (eCAP) module. Figure 6-38 shows a functional block diagram

of a module.

CTRPHS

(phase register−32 bit)

APWM mode

SYNCIn

CTR_OVF

OVF

CTR [0−31]

PRD [0−31]

CMP [0−31]

TSCTR

(counter−32 bit)

SYNCOut

PWM

compare

logic

Delta−mode

RST

32

CTR=PRD

CTR=CMP

CTR [0−31]

PRD [0−31]

32

eCAPx

32

LD1

CAP1

(APRD active)

Polarity

select

LD

APRD

shadow

32

CMP [0−31]

32

LD2

CAP2

(ACMP active)

Polarity

select

LD

Event

qualifier

Event

Prescale

32

ACMP

shadow

Polarity

select

32

LD3

LD4

CAP3

(APRD shadow)

LD

CAP4

(ACMP shadow)

Polarity

select

LD

4

Capture events

CEVT[1:4]

4

Interrupt

Trigger

and

Flag

control

Continuous /

Oneshot

Capture Control

to PIE

CTR_OVF

CTR=PRD

CTR=CMP

Figure 6-38. eCAP Functional Block Diagram

The eCAP module is clocked at the SYSCLKOUT rate.

The clock enable bits (ECAP1 ENCLK) in the PCLKCR1 register turn off the eCAP module individually (for

low-power operation). Upon reset, ECAP1ENCLK is set to low, indicating that the peripheral clock is off.

Detailed Description

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Table 6-46. eCAP Control and Status Registers

NAME

TSCTR

eCAP1

0x6A00

SIZE (x16) EALLOW PROTECTED

DESCRIPTION

Time-Stamp Counter

2

8

1

6

CTRPHS

CAP1

0x6A02

Counter Phase Offset Value Register

Capture 1 Register

0x6A04

CAP2

0x6A06

Capture 2 Register

CAP3

0x6A08

Capture 3 Register

CAP4

0x6A0A

Capture 4 Register

Reserved

ECCTL1

ECCTL2

ECEINT

ECFLG

ECCLR

ECFRC

Reserved

0x6A0C to 0x6A12

0x6A14

Reserved

Capture Control Register 1

Capture Control Register 2

Capture Interrupt Enable Register

Capture Interrupt Flag Register

Capture Interrupt Clear Register

Capture Interrupt Force Register

Reserved

0x6A15

0x6A16

0x6A17

0x6A18

0x6A19

0x6A1A to 0x6A1F

For more information on the eCAP, see the Enhanced Capture (eCAP) Module chapter in the

TMS320F2802x,TMS320F2802xx Piccolo Technical Reference Manual.

6.9.8.1 eCAP Electrical Data/Timing

Table 6-47 shows the eCAP timing requirement and Table 6-48 shows the eCAP switching characteristics.

Table 6-47. Enhanced Capture (eCAP) Timing Requirement⁽¹⁾

MIN

2t_c(SCO)

MAX UNIT

cycles

Asynchronous

Synchronous

t_w(CAP)

Capture input pulse width

2t_c(SCO)

cycles

With input qualifier

1t_c(SCO)+ t_w(IQSW)

cycles

(1) For an explanation of the input qualifier parameters, see Table 6-55.

Table 6-48. eCAP Switching Characteristics

over recommended operating conditions (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

MAX

UNIT

t_w(APWM)

Pulse duration, APWMx output high/low

20

ns

108

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6.9.9 JTAG Port

On the 2802x device, the JTAG port is reduced to 5 pins (TRST, TCK, TDI, TMS, TDO). TCK, TDI, TMS

and TDO pins are also GPIO pins. The TRST signal selects either JTAG or GPIO operating mode for the

pins in Figure 6-39. During emulation/debug, the GPIO function of these pins are not available. If the

GPIO38/TCK/XCLKIN pin is used to provide an external clock, an alternate clock source should be used

to clock the device during emulation/debug because this pin will be needed for the TCK function.

NOTE

In 2802x devices, the JTAG pins may also be used as GPIO pins. Care should be taken in

the board design to ensure that the circuitry connected to these pins do not affect the

emulation capabilities of the JTAG pin function. Any circuitry connected to these pins should

not prevent the emulator from driving (or being driven by) the JTAG pins for successful

debug.

TRST = 0: JTAG Disabled (GPIO Mode)

TRST = 1: JTAG Mode

TRST

XCLKIN

GPIO38_in

TCK

TCK/GPIO38

GPIO38_out

C28x

Core

GPIO37_in

TDO

TDO/GPIO37

1

0

GPIO37_out

GPIO36_in

1

0

TMS

TMS/GPIO36

TDI/GPIO35

1

GPIO36_out

GPIO35_in

1

0

TDI

1

GPIO35_out

Figure 6-39. JTAG/GPIO Multiplexing

Detailed Description

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6.9.10 General-Purpose Input/Output (GPIO) MUX

The GPIO MUX can multiplex up to three independent peripheral signals on a single GPIO pin in addition

to providing individual pin bit-banging I/O capability.

The device supports 22 GPIO pins. The GPIO control and data registers are mapped to Peripheral

Frame 1 to enable 32-bit operations on the registers (along with 16-bit operations). Table 6-49 shows the

GPIO register mapping.

Table 6-49. GPIO Registers

NAME

ADDRESS

GPIO CONTROL REGISTERS (EALLOW PROTECTED)

0x6F80 GPIO A Control Register (GPIO0 to 31)

SIZE (x16)

DESCRIPTION

GPACTRL

2

GPAQSEL1

GPAQSEL2

GPAMUX1

GPAMUX2

GPADIR

0x6F82

0x6F84

0x6F86

0x6F88

0x6F8A

0x6F8C

0x6F90

0x6F92

0x6F96

0x6F9A

0x6F9C

0x6FB6

0x6FBA

GPIO A Qualifier Select 1 Register (GPIO0 to 15)

GPIO A Qualifier Select 2 Register (GPIO16 to 31)

GPIO A MUX 1 Register (GPIO0 to 15)

GPIO A MUX 2 Register (GPIO16 to 31)

GPIO A Direction Register (GPIO0 to 31)

GPIO A Pullup Disable Register (GPIO0 to 31)

GPIO B Control Register (GPIO32 to 38)

GPIO B Qualifier Select 1 Register (GPIO32 to 38)

GPIO B MUX 1 Register (GPIO32 to 38)

GPAPUD

GPBCTRL

GPBQSEL1

GPBMUX1

GPBDIR

GPIO B Direction Register (GPIO32 to 38)

GPIO B Pullup Disable Register (GPIO32 to 38)

Analog, I/O mux 1 register (AIO0 to AIO15)

Analog, I/O Direction Register (AIO0 to AIO15)

GPBPUD

AIOMUX1

AIODIR

GPIO DATA REGISTERS (NOT EALLOW PROTECTED)

GPADAT

0x6FC0

0x6FC2

0x6FC4

0x6FC6

0x6FC8

0x6FCA

0x6FCC

0x6FCE

0x6FD8

0x6FDA

0x6FDC

0x6FDE

2

GPIO A Data Register (GPIO0 to 31)

GPASET

GPIO A Data Set Register (GPIO0 to 31)

GPIO A Data Clear Register (GPIO0 to 31)

GPIO A Data Toggle Register (GPIO0 to 31)

GPIO B Data Register (GPIO32 to 38)

GPACLEAR

GPATOGGLE

GPBDAT

GPBSET

GPIO B Data Set Register (GPIO32 to 38)

GPIO B Data Clear Register (GPIO32 to 38)

GPIO B Data Toggle Register (GPIO32 to 38)

Analog I/O Data Register (AIO0 to AIO15)

Analog I/O Data Set Register (AIO0 to AIO15)

Analog I/O Data Clear Register (AIO0 to AIO15)

Analog I/O Data Toggle Register (AIO0 to AIO15)

GPBCLEAR

GPBTOGGLE

AIODAT

AIOSET

AIOCLEAR

AIOTOGGLE

GPIO INTERRUPT AND LOW-POWER MODES SELECT REGISTERS (EALLOW PROTECTED)

GPIOXINT1SEL

GPIOXINT2SEL

GPIOXINT3SEL

GPIOLPMSEL

0x6FE0

0x6FE1

0x6FE2

0x6FE8

1

2

XINT1 GPIO Input Select Register (GPIO0 to 31)

XINT2 GPIO Input Select Register (GPIO0 to 31)

XINT3 GPIO Input Select Register (GPIO0 to 31)

LPM GPIO Select Register (GPIO0 to 31)

NOTE

There is a two-SYSCLKOUT cycle delay from when the write to the GPxMUXn/AIOMUXn

and GPxQSELn registers occurs to when the action is valid.

110

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Table 6-50. GPIOA MUX⁽¹⁾⁽²⁾

DEFAULT AT RESET

PRIMARY I/O

PERIPHERAL

SELECTION 1

PERIPHERAL

SELECTION 2

PERIPHERAL

SELECTION 3

FUNCTION

GPAMUX1 REGISTER

BITS

(GPAMUX1 BITS = 00) (GPAMUX1 BITS = 01)

(GPAMUX1 BITS = 10)

(GPAMUX1 BITS = 11)

1-0

GPIO0

GPIO1

EPWM1A (O)

EPWM1B (O)

EPWM2A (O)

EPWM2B (O)

EPWM3A (O)

EPWM3B (O)

EPWM4A (O)

EPWM4B (O)

Reserved

COMP1OUT (O)

Reserved

3-2

5-4

GPIO2

Reserved

7-6

GPIO3

Reserved

COMP2OUT⁽³⁾(O)

9-8

GPIO4

Reserved

11-10

13-12

15-14

17-16

19-18

21-20

23-22

25-24

27-26

29-28

31-30

GPIO5

Reserved

ECAP1 (I/O)

EPWMSYNCO (O)

Reserved

GPIO6

EPWMSYNCI (I)

SCIRXDA (I)

Reserved

GPIO7

Reserved

GPIO12

Reserved

TZ1 (I)

SCITXDA (O)

Reserved

GPAMUX2 REGISTER

BITS

(GPAMUX2 BITS = 00) (GPAMUX2 BITS = 01)

(GPAMUX2 BITS = 10)

(GPAMUX2 BITS = 11)

1-0

GPIO16

GPIO17

SPISIMOA (I/O)

SPISOMIA (I/O)

SPICLKA (I/O)

SPISTEA (I/O)

Reserved

TZ2 (I)

TZ3 (I)

3-2

5-4

GPIO18

SCITXDA (O)

SCIRXDA (I)

Reserved

XCLKOUT (O)

ECAP1 (I/O)

Reserved

TZ2 (I)

7-6

GPIO19/XCLKIN

Reserved

GPIO28

9-8

11-10

13-12

15-14

17-16

19-18

21-20

23-22

25-24

27-26

29-28

31-30

Reserved

SCIRXDA (I)

SCITXDA (O)

Reserved

SDAA (I/OD)

SCLA (I/OD)

Reserved

GPIO29

TZ3 (I)

Reserved

(1) The word reserved means that there is no peripheral assigned to this GPxMUX1/2 register setting. Should it be selected, the state of the

pin will be undefined and the pin may be driven. This selection is a reserved configuration for future expansion.

(2) I = Input, O = Output, OD = Open Drain

(3) These functions are not available in the 38-pin package.

Detailed Description

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Table 6-51. GPIOB MUX⁽¹⁾

DEFAULT AT RESET

PRIMARY I/O FUNCTION

PERIPHERAL

SELECTION 1

PERIPHERAL

SELECTION 2

PERIPHERAL

SELECTION 3

GPBMUX1 REGISTER

BITS

(GPBMUX1 BITS = 00)

(GPBMUX1 BITS = 01)

(GPBMUX1 BITS = 10)

(GPBMUX1 BITS = 11)

1-0

GPIO32⁽²⁾

GPIO33⁽²⁾

SDAA⁽²⁾(I/OD)

SCLA⁽²⁾(I/OD)

COMP2OUT (O)

Reserved

EPWMSYNCI⁽²⁾(I)

EPWMSYNCO⁽²⁾(O)

Reserved

ADCSOCAO ⁽²⁾(O)

ADCSOCBO ⁽²⁾(O)

Reserved

3-2

5-4

GPIO34

7-6

GPIO35 (TDI)

GPIO36 (TMS)

GPIO37 (TDO)

GPIO38/XCLKIN (TCK)

Reserved

9-8

Reserved

11-10

13-12

15-14

17-16

19-18

21-20

23-22

25-24

27-26

29-28

31-30

Reserved

(1) I = Input, O = Output, OD = Open Drain

(2) These pins are not available in the 38-pin package.

Table 6-52. Analog MUX for 48-Pin PT Package⁽¹⁾

DEFAULT AT RESET

PERIPHERAL SELECTION 2 AND

PERIPHERAL SELECTION 3

AIOx AND PERIPHERAL SELECTION 1

AIOMUX1 REGISTER BITS

AIOMUX1 BITS = 0,x

ADCINA0 (I), V_REFHI(I)

ADCINA1 (I)

AIO2 (I/O)

ADCINA3 (I)

AIO4 (I/O)

–

AIOMUX1 BITS = 1,x

ADCINA0 (I), V_REFHI(I)

ADCINA1 (I)

1-0

3-2

5-4

ADCINA2 (I), COMP1A (I)

ADCINA3 (I)

7-6

9-8

ADCINA4 (I), COMP2A (I)

–

11-10

13-12

15-14

17-16

19-18

21-20

23-22

25-24

27-26

29-28

31-30

AIO6 (I/O)

ADCINA7 (I)

–

ADCINA6 (I)

ADCINA7 (I)

–

ADCINB1 (I)

AIO10 (I/O)

ADCINB3 (I)

AIO12 (I/O)

–

ADCINB1 (I)

ADCINB2 (I), COMP1B (I)

ADCINB3 (I)

ADCINB4 (I), COMP2B (I)

–

AIO14 (I/O)

ADCINB7 (I)

ADCINB6 (I)

ADCINB7 (I)

(1) I = Input, O = Output

112

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Table 6-53. Analog MUX for 38-Pin DA Package⁽¹⁾

DEFAULT AT RESET

PERIPHERAL SELECTION 2 AND

PERIPHERAL SELECTION 3

AIOx AND PERIPHERAL SELECTION 1

AIOMUX1 REGISTER BITS

AIOMUX1 BITS = 0,x

AIOMUX1 BITS = 1,x

1-0

ADCINA0 (I), V_REFHI(I)

3-2

–

5-4

AIO2 (I/O)

ADCINA2 (I), COMP1A (I)

7-6

–

9-8

AIO4 (I/O)

ADCINA4 (I)

11-10

13-12

15-14

17-16

19-18

21-20

23-22

25-24

27-26

29-28

31-30

–

AIO6 (I/O)

ADCINA6 (I)

–

AIO10 (I/O)

ADCINB2 (I), COMP1B (I)

–

AIO12 (I/O)

ADCINB4 (I)

–

AIO14 (I/O)

–

ADCINB6 (I)

–

(1) I = Input, O = Output

The user can select the type of input qualification for each GPIO pin through the GPxQSEL1/2 registers

from four choices:

•

Synchronization To SYSCLKOUT Only (GPxQSEL1/2 = 0, 0): This is the default mode of all GPIO pins

at reset and it simply synchronizes the input signal to the system clock (SYSCLKOUT).

•

Qualification Using Sampling Window (GPxQSEL1/2 = 0, 1 and 1, 0): In this mode the input signal,

after synchronization to the system clock (SYSCLKOUT), is qualified by a specified number of cycles

before the input is allowed to change.

•

The sampling period is specified by the QUALPRD bits in the GPxCTRL register and is configurable in

groups of 8 signals. It specifies a multiple of SYSCLKOUT cycles for sampling the input signal. The

sampling window is either 3-samples or 6-samples wide and the output is only changed when ALL

samples are the same (all 0s or all 1s) as shown in Figure 6-42 (for 6 sample mode).

No Synchronization (GPxQSEL1/2 = 1,1): This mode is used for peripherals where synchronization is

not required (synchronization is performed within the peripheral).

Due to the multilevel multiplexing that is required on the device, there may be cases where a peripheral

input signal can be mapped to more then one GPIO pin. Also, when an input signal is not selected, the

input signal will default to either a 0 or 1 state, depending on the peripheral.

Detailed Description

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GPIOXINT1SEL

GPIOXINT2SEL

GPIOXINT3SEL

GPIOLMPSEL

LPMCR0

External Interrupt

MUX

Low-Power

Modes Block

PIE

Asynchronous

path

GPxDAT (read)

GPxQSEL1/2

GPxCTRL

GPxPUD

N/C

00

01

Peripheral 1 Input

Peripheral 2 Input

Input

Internal

Qualification

10

11

Pullup

Peripheral 3 Input

GPxTOGGLE

Asynchronous path

GPIOx pin

GPxCLEAR

GPxSET

00

01

GPxDAT (latch)

Peripheral 1 Output

10

11

Peripheral 2 Output

Peripheral 3 Output

High Impedance

Output Control

GPxDIR (latch)

00

01

Peripheral 1 Output Enable

Peripheral 2 Output Enable

0 = Input, 1 = Output

XRS

10

11

Peripheral 3 Output Enable

= Default at Reset

GPxMUX1/2

A. x stands for the port, either A or B. For example, GPxDIR refers to either the GPADIR and GPBDIR register

depending on the particular GPIO pin selected.

B. GPxDAT latch/read are accessed at the same memory location.

C. This is a generic GPIO MUX block diagram. Not all options may be applicable for all GPIO pins. For pin-specific

variations, see the System Control chapter in the TMS320F2802x,TMS320F2802xx Piccolo Technical Reference

Manual.

Figure 6-40. GPIO Multiplexing

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6.9.10.1 GPIO Electrical Data/Timing

6.9.10.1.1 GPIO - Output Timing

Table 6-54. General-Purpose Output Switching Characteristics

over recommended operating conditions (unless otherwise noted)

PARAMETER

MIN

MAX

13⁽¹⁾

15

UNIT

ns

t_r(GPO)

t_f(GPO)

t_fGPO

Rise time, GPIO switching low to high

Fall time, GPIO switching high to low

Toggling frequency

All GPIOs

ns

MHz

(1) Rise time and fall time vary with electrical loading on I/O pins. Values given in Table 6-54 are applicable for a 40-pF load on I/O pins.

GPIO

t

r(GPO)

t

f(GPO)

Figure 6-41. General-Purpose Output Timing

Detailed Description

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6.9.10.1.2 GPIO - Input Timing

Table 6-55. General-Purpose Input Timing Requirements

MIN

1t_c(SCO)

MAX

UNIT

cycles

QUALPRD = 0

t_w(SP)

Sampling period

QUALPRD ≠ 0

2t_c(SCO)* QUALPRD

t_w(SP)* (n⁽¹⁾– 1)

2t_c(SCO)

t_w(IQSW)

Input qualifier sampling window

Pulse duration, GPIO low/high

Synchronous mode

With input qualifier

(2)

t_w(GPI)

t_w(IQSW)+ t_w(SP)+ 1t_c(SCO)

(1) "n" represents the number of qualification samples as defined by GPxQSELn register.

(2) For t_w(GPI), pulse width is measured from V_ILto V_ILfor an active low signal and V_IHto V_IHfor an active high signal.

(A)

GPIO Signal

GPxQSELn = 1,0 (6 samples)

1

0

1

0

1

t_w(SP)

Sampling Period determined

by GPxCTRL[QUALPRD]^(B)

t_w(IQSW)

[(SYSCLKOUT cycle * 2 * QUALPRD) * 5^(C)

]

Sampling Window

SYSCLKOUT

QUALPRD = 1

(SYSCLKOUT/2)

(D)

Output From

Qualifier

A. This glitch will be ignored by the input qualifier. The QUALPRD bit field specifies the qualification sampling period. It

can vary from 00 to 0xFF. If QUALPRD = 00, then the sampling period is 1 SYSCLKOUT cycle. For any other value

"n", the qualification sampling period in 2n SYSCLKOUT cycles (that is, at every 2n SYSCLKOUT cycles, the GPIO

pin will be sampled).

B. The qualification period selected through the GPxCTRL register applies to groups of 8 GPIO pins.

C. The qualification block can take either three or six samples. The GPxQSELn Register selects which sample mode is

used.

D. In the example shown, for the qualifier to detect the change, the input should be stable for 10 SYSCLKOUT cycles or

greater. In other words, the inputs should be stable for (5 x QUALPRD x 2) SYSCLKOUT cycles. This would ensure

5 sampling periods for detection to occur. Because external signals are driven asynchronously, an 13-SYSCLKOUT-

wide pulse ensures reliable recognition.

Figure 6-42. Sampling Mode

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6.9.10.1.3 Sampling Window Width for Input Signals

The following section summarizes the sampling window width for input signals for various input qualifier

configurations.

Sampling frequency denotes how often a signal is sampled with respect to SYSCLKOUT.

Sampling frequency = SYSCLKOUT/(2 × QUALPRD), if QUALPRD ≠ 0

Sampling frequency = SYSCLKOUT, if QUALPRD = 0

Sampling period = SYSCLKOUT cycle × 2 × QUALPRD, if QUALPRD ≠ 0

In the above equations, SYSCLKOUT cycle indicates the time period of SYSCLKOUT.

Sampling period = SYSCLKOUT cycle, if QUALPRD = 0

In a given sampling window, either 3 or 6 samples of the input signal are taken to determine the validity of

the signal. This is determined by the value written to GPxQSELn register.

Case 1:

Qualification using 3 samples

Sampling window width = (SYSCLKOUT cycle × 2 × QUALPRD) × 2, if QUALPRD ≠ 0

Sampling window width = (SYSCLKOUT cycle) × 2, if QUALPRD = 0

Case 2:

Qualification using 6 samples

Sampling window width = (SYSCLKOUT cycle × 2 × QUALPRD) × 5, if QUALPRD ≠ 0

Sampling window width = (SYSCLKOUT cycle) × 5, if QUALPRD = 0

SYSCLK

GPIOxn

t_w(GPI)

Figure 6-43. General-Purpose Input Timing

V_DDIO

> 1 MS

2 pF

V_SS

Figure 6-44. Input Resistance Model for a GPIO Pin With an Internal Pullup

Detailed Description

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6.9.10.1.4 Low-Power Mode Wakeup Timing

Table 6-56 shows the timing requirements, Table 6-57 shows the switching characteristics, and Figure 6-

45 shows the timing diagram for IDLE mode.

Table 6-56. IDLE Mode Timing Requirements⁽¹⁾

MIN

2t_c(SCO)

MAX

UNIT

Without input qualifier

With input qualifier

t_w(WAKE-INT)

Pulse duration, external wake-up signal

cycles

5t_c(SCO)+ t_w(IQSW)

(1) For an explanation of the input qualifier parameters, see Table 6-55.

Table 6-57. IDLE Mode Switching Characteristics⁽¹⁾

over recommended operating conditions (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

MAX

UNIT

(2)

Delay time, external wake signal to program execution resume

cycles

Without input qualifier

With input qualifier

Without input qualifier

With input qualifier

Without input qualifier

With input qualifier

20t_c(SCO)

•

Wake up from Flash

Flash module in active state

cycles

–

20t_c(SCO)+ t_w(IQSW)

1050t_c(SCO)

t_d(WAKE-IDLE)

•

Wake up from Flash

Flash module in sleep state

–

1050t_c(SCO)+ t_w(IQSW)

20t_c(SCO)

•

Wake up from SARAM

20t_c(SCO)+ t_w(IQSW)

(1) For an explanation of the input qualifier parameters, see Table 6-55.

(2) This is the time taken to begin execution of the instruction that immediately follows the IDLE instruction. Execution of an ISR (triggered

by the wake-up signal) involves additional latency.

t

d(WAKE−IDLE)

Address/Data

(internal)

XCLKOUT

t

w(WAKE−INT)

WAKE INT^(A)(B)

A. WAKE INT can be any enabled interrupt, WDINT or XRS.

B. From the time the IDLE instruction is executed to place the device into low-power mode (LPM), wakeup should not be

initiated until at least 4 OSCCLK cycles have elapsed.

Figure 6-45. IDLE Entry and Exit Timing

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Table 6-58. STANDBY Mode Timing Requirements

MIN

3t_c(OSCCLK)

MAX

UNIT

Without input qualification

With input qualification⁽¹⁾

Pulse duration, external

wake-up signal

t_w(WAKE-INT)

cycles

(2 + QUALSTDBY) * t_c(OSCCLK)

(1) QUALSTDBY is a 6-bit field in the LPMCR0 register.

Table 6-59. STANDBY Mode Switching Characteristics

over recommended operating conditions (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

MAX

UNIT

Delay time, IDLE instruction

executed to XCLKOUT low

t_d(IDLE-XCOL)

32t_c(SCO)

45t_c(SCO)

cycles

Delay time, external wake signal to program execution

resume⁽¹⁾

cycles

Without input qualifier

100t_c(SCO)

•

Wake up from flash

–

Flash module in active state With input qualifier

100t_c(SCO)+ t_w(WAKE-INT)

1125t_c(SCO)

t_d(WAKE-STBY)

Without input qualifier

•

Wake up from flash

cycles

–

Flash module in sleep state With input qualifier

1125t_c(SCO)+ t_w(WAKE-INT)

100t_c(SCO)

Without input qualifier

•

Wake up from SARAM

With input qualifier

100t_c(SCO)+ t_w(WAKE-INT)

(1) This is the time taken to begin execution of the instruction that immediately follows the IDLE instruction. Execution of an ISR (triggered

by the wake-up signal) involves additional latency.

Detailed Description

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(C)

(F)

(A)

(B)

(D)(E)

(G)

Normal Execution

Device

Status

STANDBY

Flushing Pipeline

Wake-up

Signal^(H)

t

w(WAKE-INT)

t

d(WAKE-STBY)

X1/X2 or

XCLKIN

XCLKOUT

t

d(IDLE−XCOL)

A. IDLE instruction is executed to put the device into STANDBY mode.

B. The PLL block responds to the STANDBY signal. SYSCLKOUT is held for the number of cycles indicated below

before being turned off:

•

16 cycles, when DIVSEL = 00 or 01

32 cycles, when DIVSEL = 10

64 cycles, when DIVSEL = 11

This delay enables the CPU pipeline and any other pending operations to flush properly.

C. Clock to the peripherals are turned off. However, the PLL and watchdog are not shut down. The device is now in

STANDBY mode.

D. The external wake-up signal is driven active.

E. The wake-up signal fed to a GPIO pin to wake up the device must meet the minimum pulse width requirement.

Furthermore, this signal must be free of glitches. If a noisy signal is fed to a GPIO pin, the wake-up behavior of the

device will not be deterministic and the device may not exit low-power mode for subsequent wake-up pulses.

F. After a latency period, the STANDBY mode is exited.

G. Normal execution resumes. The device will respond to the interrupt (if enabled).

H. From the time the IDLE instruction is executed to place the device into low-power mode (LPM), wakeup should not be

initiated until at least 4 OSCCLK cycles have elapsed.

Figure 6-46. STANDBY Entry and Exit Timing Diagram

Table 6-60. HALT Mode Timing Requirements

MIN

t_oscst+ 2t_c(OSCCLK)

t_oscst+ 8t_c(OSCCLK)

MAX

UNIT

cycles

t_w(WAKE-GPIO)

t_w(WAKE-XRS)

Pulse duration, GPIO wake-up signal

Pulse duration, XRS wake-up signal

Table 6-61. HALT Mode Switching Characteristics

over recommended operating conditions (unless otherwise noted)

PARAMETER

MIN

MAX

UNIT

t_d(IDLE-XCOL)

t_p

Delay time, IDLE instruction executed to XCLKOUT low

PLL lock-up time

32t_c(SCO)

45t_c(SCO)

1

cycles

ms

Delay time, PLL lock to program execution resume

1125t_c(SCO)

35t_c(SCO)

cycles

•

Wake up from flash

Flash module in sleep state

t_d(WAKE-HALT)

–

Wake up from SARAM

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(C)

(F)

(A)

(H)

(B)

(G)

(D)(E)

Device

Status

HALT

Flushing Pipeline

PLL Lock-up Time

Normal

Execution

Wake-up Latency

GPIOn^(I)

t

)

d(WAKE−HALT

t

w(WAKE-GPIO)

t_p

X1/X2 or

XCLKIN

Oscillator Start-up Time

XCLKOUT

t

d(IDLE−XCOL)

A. IDLE instruction is executed to put the device into HALT mode.

B. The PLL block responds to the HALT signal. SYSCLKOUT is held for the number of cycles indicated below before

oscillator is turned off and the CLKIN to the core is stopped:

•

16 cycles, when DIVSEL = 00 or 01

32 cycles, when DIVSEL = 10

64 cycles, when DIVSEL = 11

This delay enables the CPU pipeline and any other pending operations to flush properly.

C. Clocks to the peripherals are turned off and the PLL is shut down. If a quartz crystal or ceramic resonator is used as

the clock source, the internal oscillator is shut down as well. The device is now in HALT mode and consumes

absolute minimum power. It is possible to keep the zero-pin internal oscillators (INTOSC1 and INTOSC2) and the

watchdog alive in HALT mode. This is done by writing to the appropriate bits in the CLKCTL register.

D. When the GPIOn pin (used to bring the device out of HALT) is driven low, the oscillator is turned on and the oscillator

wake-up sequence is initiated. The GPIO pin should be driven high only after the oscillator has stabilized. This

enables the provision of a clean clock signal during the PLL lock sequence. Because the falling edge of the GPIO pin

asynchronously begins the wake-up procedure, care should be taken to maintain a low noise environment prior to

entering and during HALT mode.

E. The wake-up signal fed to a GPIO pin to wake up the device must meet the minimum pulse width requirement.

Furthermore, this signal must be free of glitches. If a noisy signal is fed to a GPIO pin, the wake-up behavior of the

device will not be deterministic and the device may not exit low-power mode for subsequent wake-up pulses.

F. Once the oscillator has stabilized, the PLL lock sequence is initiated, which takes 1 ms.

G. When CLKIN to the core is enabled, the device will respond to the interrupt (if enabled), after a latency. The HALT

mode is now exited.

H. Normal operation resumes.

I.

From the time the IDLE instruction is executed to place the device into low-power mode (LPM), wakeup should not be

initiated until at least 4 OSCCLK cycles have elapsed.

Figure 6-47. HALT Mode Wakeup Using GPIOn

Detailed Description

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7 Applications, Implementation, and Layout

NOTE

www.ti.com

Information in the following sections is not part of the TI component specification, and TI

does not warrant its accuracy or completeness. TI’s customers are responsible for

determining suitability of components for their purposes. Customers should validate and test

their design implementation to confirm system functionality.

7.1 TI Design or Reference Design

The TI Designs Reference Design Library is a robust reference design library spanning analog, embedded

processor, and connectivity. Created by TI experts to help you jump start your system design, all TI

Designs include schematic or block diagrams, BOMs, and design files to speed your time to market.

Search and download designs at ti.com/tidesigns.

36V/1kW Brushless DC Motor Drive with Stall Current Limit of <1us Response Time Reference Design

This reference design is a power stage for brushless motors in battery-powered garden and power tools

rated up to 1 kW, operating from a 10-cell lithium-ion battery with a voltage range from 36 V to 42 V. The

design uses 60-V, N-channel NexFET™ technology featuring a very low drain-to-source resistance

(RDS_ON) of 1.8 mΩ in a SON5x6 SMD package, which results in a very small PCB form factor of

57 mm × 59 mm. The 3-phase gate-driver is used to drive a 3-phase MOSFET bridge, which can operate

from 6 V to 60 V and supports programmable gate current with a maximum setting of 2.3-A sink/1.7-A

source. The C2000™ Piccolo LaunchPad™ Development Kit (LAUNCHXL-F28027) is used with this

power stage, and 120-degree trapezoidal control of BLDC motor with Hall sensors is implemented in

software. The cycle-by-cycle current limit feature in the gate-driver protects the board from excessive

current that is caused during motor stalls, by limiting the maximum current allowed in the power stage to a

safe level.

Single-Ended Signal Conditioning Circuit for Current and Voltage Measurement Using Fluxgate Sensors

This design provides a 4-channel signal conditioning solution for single-ended SAR ADCs integrated into a

microcontroller measuring motor current using fluxgate sensors. Also provided is an alternative

measurement circuit with external SAR ADCs as well as circuits for high-speed overcurrent and earth fault

detection. Proper signal conditioning improves noise immunity on critical current measurements in motor

drives. This reference design can help increase the effective resolution of the analog-to-digital conversion,

improving motor drive efficiency.

122

Applications, Implementation, and Layout

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8 Device and Documentation Support

8.1 Getting Started

Key links include:

1. Getting Started with C2000 Real-time Control MCUs

2. Motor drive and control

3. Digital power

4. Tools & software for Performance MCUs

8.2 Device and Development Support Tool Nomenclature

To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all

TMS320™ MCU devices and support tools. Each TMS320 MCU commercial family member has one of

three prefixes: TMX, TMP, or TMS (for example, TMS320F28023). Texas Instruments recommends two of

three possible prefix designators for its support tools: TMDX and TMDS. These prefixes represent

evolutionary stages of product development from engineering prototypes (TMX/TMDX) through fully

qualified production devices/tools (TMS/TMDS).

Device development evolutionary flow:

TMX

TMP

TMS

Experimental device that is not necessarily representative of the final device's electrical

specifications

Final silicon die that conforms to the device's electrical specifications but has not

completed quality and reliability verification

Fully qualified production device

Support tool development evolutionary flow:

TMDX Development-support product that has not yet completed Texas Instruments internal

qualification testing

TMDS Fully qualified development-support product

TMX and TMP devices and TMDX development-support tools are shipped against the following

disclaimer:

"Developmental product is intended for internal evaluation purposes."

TMS devices and TMDS development-support tools have been characterized fully, and the quality and

reliability of the device have been demonstrated fully. TI's standard warranty applies.

Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard

production devices. Texas Instruments recommends that these devices not be used in any production

system because their expected end-use failure rate still is undefined. Only qualified production devices are

to be used.

TI device nomenclature also includes a suffix with the device family name. This suffix indicates the

package type (for example, PT) and temperature range (for example, S). Figure 8-1 provides a legend for

reading the complete device name for any family member.

For device part numbers and further ordering information, see the TI website (www.ti.com) or contact your

TI sales representative.

For additional description of the device nomenclature markings on the die, see the TMS320F2802x,

TMS320F2802xx Piccolo™ MCUs Silicon Errata.

Device and Documentation Support

123

Submit Documentation Feedback

Product Folder Links: TMS320F28027 TMS320F28026 TMS320F28023 TMS320F28022 TMS320F28021

TMS320F28020 TMS320F280200

TMS320F28027, TMS320F28026, TMS320F28023, TMS320F28022

TMS320F28021, TMS320F28020, TMS320F280200

SPRS523M –NOVEMBER 2008–REVISED JANUARY 2019

www.ti.com

TMS 320

F

28023

PT

S

PREFIX

TEMPERATURE RANGE

experimental device

prototype device

qualified device

TMX =

TMP =

TMS =

T

S

Q

−40°C to 105°C

−40°C to 125°C

=

(Q refers to AEC Q100 qualification for automotive applications.)

DEVICE FAMILY

PACKAGE TYPE

320 = TMS320 MCU Family

48-Pin PT Low-Profile Quad Flatpack (LQFP)

38-Pin DA Thin Shrink Small-Outline Package (TSSOP)

DEVICE

28027

28026

28023

28022

28021

28020

280200

28027F

28026F

TECHNOLOGY

F = Flash

A. For more information on peripheral, temperature, and package availability for a specific device, see Table 3-1.

Figure 8-1. Device Nomenclature

8.3 Tools and Software

TI offers an extensive line of development tools. Some of the tools and software to evaluate the

performance of the device, generate code, and develop solutions are listed below. To view all available

tools and software for C2000™ real-time control MCUs, visit the Tools & software for C2000™ real-time

control MCUs page.

Development Tools

Code Composer Studio (CCS) Integrated Development Environment (IDE) for C2000 Microcontrollers

Code Composer Studio is an integrated development environment (IDE) that supports TI's Microcontroller

and Embedded Processors portfolio. CCS comprises a suite of tools used to develop and debug

embedded applications. It includes an optimizing C/C++ compiler, source code editor, project build

environment, debugger, profiler, and many other features. The intuitive IDE provides a single user

interface taking you through each step of the application development flow. Familiar tools and interfaces

allow users to get started faster than ever before. CCS combines the advantages of the Eclipse software

framework with advanced embedded debug capabilities from TI resulting in a compelling feature-rich

development environment for embedded developers.

C2000 Piccolo LaunchPad

The C2000 Piccolo LaunchPad is an inexpensive, modular, and fun evaluation platform, enabling you to

dive into real-time, closed-loop control development with Texas Instruments’ C2000 32-bit microcontroller

family. This platform provides a great starting point for development of many common power electronics

applications, including motor control, digital power supplies, solar inverters, digital LED lighting, precision

sensing, and more.

To view all available C2000 LaunchPad development kits and BoosterPack™ plug-in modules, visit the

C2000 LaunchPad site.

Software Tools

powerSUITE - Digital Power Supply Design Software Tools for C2000™ MCUs

powerSUITE is a suite of digital power supply design software tools for Texas Instruments' C2000 real-

time microcontroller (MCU) family. powerSUITE helps power supply engineers drastically reduce

development time as they design digitally-controlled power supplies based on C2000 real-time control

MCUs.

124

Device and Documentation Support

Submit Documentation Feedback

Product Folder Links: TMS320F28027 TMS320F28026 TMS320F28023 TMS320F28022 TMS320F28021

TMS320F28020 TMS320F280200

TMS320F28027, TMS320F28026, TMS320F28023, TMS320F28022

TMS320F28021, TMS320F28020, TMS320F280200

www.ti.com

SPRS523M –NOVEMBER 2008–REVISED JANUARY 2019

C2000Ware for C2000 MCUs

C2000Ware for C2000™ microcontrollers is a cohesive set of development software and documentation

designed to minimize software development time. From device-specific drivers and libraries to device

peripheral examples, C2000Ware provides a solid foundation to begin development and evaluation of your

product.

UniFlash Standalone Flash Tool

UniFlash is a standalone tool used to program on-chip flash memory through a GUI, command line, or

scripting interface.

Models

Various models are available for download from the product Tools & Software pages. These include I/O

Buffer Information Specification (IBIS) Models and Boundary-Scan Description Language (BSDL) Models.

To view all available models, visit the Models section of the Tools & Software page for each device, which

can be found in Table 8-1.

Training

InstaSPIN-FOC LaunchPad and BoosterPack

This 6-part series provides information about the C2000 InstaSPIN-FOC Motor Control LaunchPad

Development Kit and BoosterPack Plug-in Module.

The InstaSPIN-FOC enabled C2000 Piccolo LaunchPad is an inexpensive evaluation platform designed to

help you leap right into the world of sensorless motor control using the InstaSPIN-FOC solution.

•

Part 1: Introduction and Overview

Part 2: Identifying Your Motor

Part 3: Zero Speed, Low Speed, & Tuning

Part 4: Accelerations & Speed Reversals with Texas Instruments

Part 5: High, Higher, Highest Speeds with Texas Instruments

BOOSTXL-DRV8301 BoosterPack with Texas Instruments

C2000™ Architecture and Peripherals

The C2000 family of microcontrollers contains a unique mix of innovative and cutting-edge peripherals

along with a very capable C28x core. This video describes the core architecture and every peripheral

offered on C2000 devices.

Device and Documentation Support

125

Submit Documentation Feedback

Product Folder Links: TMS320F28027 TMS320F28026 TMS320F28023 TMS320F28022 TMS320F28021

TMS320F28020 TMS320F280200

TMS320F28027, TMS320F28026, TMS320F28023, TMS320F28022

TMS320F28021, TMS320F28020, TMS320F280200

SPRS523M –NOVEMBER 2008–REVISED JANUARY 2019

www.ti.com

8.4 Documentation Support

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the

upper right corner, click on Alert me to register and receive a weekly digest of any product information that

has changed. For change details, review the revision history included in any revised document.

The current documentation that describes the processor, related peripherals, and other technical collateral

is listed below.

Errata

TMS320F2802x, TMS320F2802xx Piccolo™ MCUs Silicon Errata describes known advisories on silicon

and provides workarounds.

Technical Reference Manual

TMS320F2802x,TMS320F2802xx Piccolo Technical Reference Manual details the integration, the

environment, the functional description, and the programming models for each peripheral and subsystem

in the device.

InstaSPIN Technical Reference Manuals

InstaSPIN-FOC™ and InstaSPIN-MOTION™ User's Guide describes the InstaSPIN-FOC and InstaSPIN-

MOTION devices.

TMS320F28026F, TMS320F28027F InstaSPIN™-FOC Software Technical Reference Manual describes

the TMS320F28026F and TMS320F28027F InstaSPIN-FOC software.

CPU User's Guides

TMS320C28x CPU and Instruction Set Reference Guide describes the central processing unit (CPU) and

the assembly language instructions of the TMS320C28x fixed-point digital signal processors (DSPs). This

reference guide also describes emulation features available on these DSPs.

Peripheral Guides

C2000 Real-Time Control Peripherals Reference Guide describes the peripheral reference guides of the

28x digital signal processors (DSPs).

Tools Guides

TMS320C28x Assembly Language Tools v18.9.0.STS User's Guide describes the assembly language

tools (assembler and other tools used to develop assembly language code), assembler directives, macros,

common object file format, and symbolic debugging directives for the TMS320C28x device.

TMS320C28x Optimizing C/C++ Compiler v18.9.0.STS User's Guide describes the TMS320C28x C/C++

compiler. This compiler accepts ANSI standard C/C++ source code and produces TMS320 DSP assembly

language source code for the TMS320C28x device.

Application Reports

Semiconductor Packing Methodology describes the packing methodologies employed to prepare

semiconductor devices for shipment to end users.

Calculating Useful Lifetimes of Embedded Processors provides a methodology for calculating the useful

lifetime of TI embedded processors (EPs) under power when used in electronic systems. It is aimed at

general engineers who wish to determine if the reliability of the TI EP meets the end system reliability

requirement.

Semiconductor and IC Package Thermal Metrics describes traditional and new thermal metrics and puts

their application in perspective with respect to system-level junction temperature estimation.

Oscillator Compensation Guide describes a factory supplied method for compensating the Piccolo internal

oscillators for frequency drift caused by temperature.

126

Device and Documentation Support

Submit Documentation Feedback

Product Folder Links: TMS320F28027 TMS320F28026 TMS320F28023 TMS320F28022 TMS320F28021

TMS320F28020 TMS320F280200

TMS320F28027, TMS320F28026, TMS320F28023, TMS320F28022

TMS320F28021, TMS320F28020, TMS320F280200

www.ti.com

SPRS523M –NOVEMBER 2008–REVISED JANUARY 2019

An Introduction to IBIS (I/O Buffer Information Specification) Modeling discusses various aspects of IBIS

including its history, advantages, compatibility, model generation flow, data requirements in modeling the

input/output structures and future trends.

Serial Flash Programming of C2000™ Microcontrollers discusses using a flash kernel and ROM loaders

for serial programming a device.

8.5 Related Links

The table below lists quick access links. Categories include technical documents, support and community

resources, tools and software, and quick access to sample or buy.

Table 8-1. Related Links

TECHNICAL

DOCUMENTS

TOOLS &

SOFTWARE

SUPPORT &

COMMUNITY

PARTS

PRODUCT FOLDER

SAMPLE & BUY

TMS320F28027

TMS320F28026

TMS320F28023

TMS320F28022

TMS320F28021

TMS320F28020

TMS320F280200

Click here

8.6 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the

respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views;

see TI's Terms of Use.

TI E2E™ Online Community The TI engineer-to-engineer (E2E) community was created to foster

collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge,

explore ideas and help solve problems with fellow engineers.

TI Embedded Processors Wiki Established to help developers get started with Embedded Processors

from Texas Instruments and to foster innovation and growth of general knowledge about the

hardware and software surrounding these devices.

8.7 Trademarks

Piccolo, InstaSPIN-FOC, TMS320C2000, NexFET, C2000, LaunchPad, TMS320, BoosterPack,

InstaSPIN-MOTION, E2E are trademarks of Texas Instruments.

I²C-bus is a registered trademark of NXP B.V. Corporation.

All other trademarks are the property of their respective owners.

8.8 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

8.9 Glossary

TI Glossary This glossary lists and explains terms, acronyms, and definitions.

Device and Documentation Support

127

Submit Documentation Feedback

Product Folder Links: TMS320F28027 TMS320F28026 TMS320F28023 TMS320F28022 TMS320F28021

TMS320F28020 TMS320F280200

TMS320F28027, TMS320F28026, TMS320F28023, TMS320F28022

TMS320F28021, TMS320F28020, TMS320F280200

SPRS523M –NOVEMBER 2008–REVISED JANUARY 2019

www.ti.com

9 Mechanical, Packaging, and Orderable Information

9.1 Packaging Information

The following pages include mechanical, packaging, and orderable information. This information is the

most current data available for the designated devices. This data is subject to change without notice and

revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

128

Mechanical, Packaging, and Orderable Information

Submit Documentation Feedback

Product Folder Links: TMS320F28027 TMS320F28026 TMS320F28023 TMS320F28022 TMS320F28021

TMS320F28020 TMS320F280200

PACKAGE MATERIALS INFORMATION

www.ti.com

15-Feb-2019

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

TMS320F28022DAQR

TMS320F28027DASR

TMS320F28027DATR

TSSOP

DA

38

2000

330.0

24.4

8.6

13.0

1.8

12.0

24.0

Q1

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

15-Feb-2019

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

TMS320F28022DAQR

TMS320F28027DASR

TMS320F28027DATR

TSSOP

DA

38

2000

350.0

43.0

Pack Materials-Page 2

MECHANICAL DATA

MTQF003A – OCTOBER 1994 – REVISED DECEMBER 1996

PT (S-PQFP-G48)

PLASTIC QUAD FLATPACK

0,27

0,17

M

0,08

0,50

36

25

37

24

48

13

0,13 NOM

1

12

5,50 TYP

7,20

SQ

6,80

Gage Plane

9,20

SQ

8,80

0,25

0,05 MIN

0°–7°

1,45

1,35

0,75

0,45

Seating Plane

0,10

1,60 MAX

4040052/C 11/96

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Falls within JEDEC MS-026

D. This may also be a thermally enhanced plastic package with leads conected to the die pads.

1

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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD

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These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate

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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	TMS320F28022PTSCA
厂家：	TEXAS INSTRUMENTS
描述：	Piccolo Microcontroller 48-LQFP -40 to 125 时钟微控制器外围集成电路
文件：	总138页 (文件大小：2202K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TMS320F28022PTSCA [TI]

相关型号：

TMS320F28022PTT

TMS320F28023

TMS320F28023-Q1

TMS320F280230

TMS320F280230DAS

TMS320F280230DAT

TMS320F280230PTS

TMS320F280230PTT

TMS320F2802338A

TMS320F2802338S

TMS320F2802348A

TMS320F2802348S