TMS320F28053PNQ_技术文档

TMS320F28055, TMS320F28054, TMS320F28053

TMS320F28052, TMS320F28051, TMS320F28050

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SPRS797 –NOVEMBER 2012

Piccolo Microcontrollers

Check for Samples: TMS320F28055, TMS320F28054, TMS320F28053, TMS320F28052, TMS320F28051, TMS320F28050

1 TMS320F2805x ( Piccolo™) MCUs

1.1 Features

123

• Highlights

• Programmable Control Law Accelerator (CLA)

– 32-Bit Floating-Point Math Accelerator

– High-Efficiency 32-Bit CPU ( TMS320C28x™)

– 60-MHz Device

– Single 3.3-V Supply

– Executes Code Independently of the Main

CPU

• Low Device and System Cost:

– Single 3.3-V Supply

– Integrated Power-on and Brown-out Resets

– Two Internal Zero-pin Oscillators

– Up to 42 Multiplexed GPIO Pins

– Three 32-Bit CPU Timers

– On-Chip Flash, SARAM, Message RAM, OTP,

CLA Data ROM, Boot ROM, Secure ROM

Memory

– No Power Sequencing Requirement

– Integrated Power-on Reset and Brown-out

Reset

– Low Power

– No Analog Support Pins

• Clocking:

– Dual-Zone Security Module

– Serial Port Peripherals (SCI/SPI/I2C/eCAN)

– Enhanced Control Peripherals

– Two Internal Zero-pin Oscillators

– On-Chip Crystal Oscillator/External Clock

Input

– Dynamic PLL Ratio Changes Supported

– Watchdog Timer Module

– Missing Clock Detection Circuitry

•

Enhanced Pulse Width Modulator (ePWM)

Enhanced Capture (eCAP)

Enhanced Quadrature Encoder Pulse

(eQEP)

– Analog Peripherals

• Up to 42 Individually Programmable,

Multiplexed GPIO Pins With Input Filtering

•

One 12-Bit Analog-to-Digital Converter

(ADC)

• Peripheral Interrupt Expansion (PIE) Block That

Supports All Peripheral Interrupts

•

One On-Chip Temperature Sensor

• Three 32-Bit CPU Timers

• Independent 16-Bit Timer in Each ePWM

Module

Up to Seven Comparators With up to

Three Integrated Digital-to-Analog

Converters (DACs)

•

One Buffered Reference DAC

Up to Four Programmable Gain

Amplifiers (PGAs)

• On-Chip Memory

– Flash, SARAM, Message RAM, OTP, CLA

Data ROM, Boot ROM, Secure ROM Available

•

Up to Four Digital Filters

• 128-Bit Security Key and Lock

– Protects Secure Memory Blocks

– Prevents Firmware Reverse Engineering

• Serial Port Peripherals

– 80-Pin Package

• High-Efficiency 32-Bit CPU ( TMS320C28x™)

– 60 MHz (16.67-ns Cycle Time)

– 16 x 16 and 32 x 32 MAC Operations

– 16 x 16 Dual MAC

– Three SCI (UART) Modules

– One SPI Module

– Harvard Bus Architecture

– One Inter-Integrated-Circuit (I2C) Bus

– Atomic Operations

– One Enhanced Controller Area Network

(eCAN) Bus

• Advanced Emulation Features

– Fast Interrupt Response and Processing

– Unified Memory Programming Model

– Code-Efficient (in C/C++ and Assembly)

• Endianness: Little Endian

– Analysis and Breakpoint Functions

– Real-Time Debug via Hardware

• 80-Pin PN Low-Profile Quad Flatpack (LQFP)

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Piccolo, TMS320C28x, C28x, TMS320C2000, Code Composer Studio, XDS510, XDS560 are trademarks of Texas

2

Instruments.

All other trademarks are the property of their respective owners.

3

ADVANCE INFORMATION concerns new products in the sampling or preproduction

phase of development. Characteristic data and other specifications are subject to change

without notice.

TMS320F28055, TMS320F28054, TMS320F28053

TMS320F28052, TMS320F28051, TMS320F28050

SPRS797 –NOVEMBER 2012

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1.2 Description

The F2805x Piccolo™ family of microcontrollers provides the power of the C28x™ core and Control Law

Accelerator (CLA) coupled with highly integrated control peripherals in low pin-count devices. This family

is code-compatible with previous C28x-based code, as well as providing a high level of analog integration.

An internal voltage regulator allows for single rail operation. Analog comparators with internal 6-bit

references have been added and can be routed directly to control the PWM outputs. The ADC converts

from 0 to 3.3-V fixed full scale range and supports ratio-metric V_REFHI/V_REFLOreferences. The ADC

interface has been optimized for low overhead/latency.

The Analog Front End (AFE) contains up to seven comparators with up to three integrated Digital-to-

Analog Converters (DACs), one VREFOUT-buffered DAC, up to four Programmable Gain Amplifiers

(PGAs), and up to four digital filters. The Programmable Gain Amplifiers (PGAs) are capable of amplifying

the input signal in three discrete gain modes. The actual gain itself depends on the resistors defined by

the user at the bipolar input end. The actual number of AFE peripherals will depend upon the 2805x

device number. See Table 2-1 for more details.

2

TMS320F2805x ( Piccolo™) MCUs

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TMS320F28050

TMS320F28055, TMS320F28054, TMS320F28053

TMS320F28052, TMS320F28051, TMS320F28050

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SPRS797 –NOVEMBER 2012

1.3 Functional Block Diagram

Z1/Z2 User OTP

Secure

M0

SARAM 1Kx16

(0-wait)

L0 SARAM (2Kx16)

(0-wait, Secure)

CLA Data RAM2

FLASH

M1

SARAM 1Kx16

(0-wait)

L1 DPSARAM (1Kx16)

(0-wait, Secure)

CLA Data RAM0

28055, 28054: 64K x 16, 10 Sectors

Dual-

Zone

Security

Module

+

ECSL

28053, 28052, 28051: 32K x 16, 5 Sectors

L2 DPSARAM (1Kx16)

(0-wait, Secure)

CLA Data RAM1

28050: 16K x 16, 3 Sectors

Boot ROM

12Kx16

Secure

L3 DPSARAM (4Kx16)

(0-wait, Secure)

CLA Program RAM

(0-wait)

Non-Secure

PUMP

Secure ROM^(A)

2Kx16

OTP/Flash Wrapper

PSWD

CLA Data ROM

(4Kx16)

(0-wait)

Secure

Memory Bus

TRST

TCK

CLA +

Message RAMs

C28x CPU

(60 MHz)

TDI

TMS

TDO

GPIO

Mux

GPIO

CTRIPnOUT

MUX

X1

X2

COMP

+

CPU Timer 0

OSC1,

OSC2,

Ext,

XRS

Digital

Filter

COMPAn

COMPBn

CPU Timer 1

POR/

BOR

PLL,

LPM,

WD

VREG

Program-

mable

Gain

CPU Timer 2

PIE

(up to 96 interrupts)

XCLKIN

Amps

ADC

0-wait

Result

Regs

LPM Wakeup

GPIO

Mux

3 External Interrupts

ADC

3.75

MSPS

Memory Bus

32-bit Peripheral Bus

(CLA-accessible)

32-bit Peripheral Bus

(CLA-accessible)

32-Bit

Peripheral Bus

16-bit Peripheral Bus

SCI-A,

SCI-B, SCI-C

(4L FIFO)

eCAN-A

SPI-A

I2C-A

eCAP

eQEP

ePWM1–ePWM7

(4L FIFO)

(32-mbox)

GPIO MUX

A. Stores Secure Copy Code Functions on all devices.

B. Not all peripheral pins are available at the same time due to multiplexing.

Figure 1-1. Functional Block Diagram

TMS320F2805x ( Piccolo™) MCUs

3

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TMS320F28052, TMS320F28051, TMS320F28050

SPRS797 –NOVEMBER 2012

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1

2

TMS320F2805x ( Piccolo™) MCUs .................. 1

1.1 Features ............................................. 1

1.2 Description ........................................... 2

1.3 Functional Block Diagram ........................... 3

Device Overview ........................................ 5

2.1 Device Characteristics ............................... 5

2.2 Memory Maps ........................................ 8

2.3 Brief Descriptions ................................... 15

2.4 Register Map ....................................... 26

2.5 Device Emulation Registers ........................ 28

2.6 VREG, BOR, POR .................................. 30

2.7 System Control ..................................... 32

2.8 Low-power Modes Block ........................... 40

2.9 Thermal Design Considerations .................... 40

Device Pins ............................................. 41

3.1 Pin Assignments .................................... 41

3.2 Terminal Functions ................................. 42

Device Operating Conditions ....................... 50

4.1 Absolute Maximum Ratings ........................ 50

4.2 Recommended Operating Conditions .............. 50

5.1 Power Sequencing ................................. 58

5.2 Clocking ............................................ 60

5.3 Interrupts ............................................ 63

Peripheral Information and Timings ............... 68

6.1 Parameter Information .............................. 68

6.2 Control Law Accelerator (CLA) ..................... 69

6.3 Analog Block ........................................ 72

6.4 Serial Peripheral Interface (SPI) .................... 91

6

6.5

Serial Communications Interface (SCI) ........... 100

Enhanced Controller Area Network (eCAN) ...... 103

6.6

6.7 Inter-Integrated Circuit (I2C) ...................... 107

Enhanced Pulse Width Modulator (ePWM) ....... 110

6.8

6.9 Enhanced Capture Module (eCAP) ............... 118

6.10 Enhanced Quadrature Encoder Pulse (eQEP) .... 120

6.11 JTAG Port ......................................... 123

6.12 General-Purpose Input/Output (GPIO) ............ 125

Device and Documentation Support ............. 136

7.1 Device Support .................................... 136

7.2 Documentation Support ........................... 138

7.3 Community Resources ............................ 138

Mechanical Packaging and Orderable

Information ............................................ 139

8.1 Thermal Data for Package ........................ 139

8.2 Packaging Information ............................ 139

3

4

7

8

4.3

Electrical Characteristics Over Recommended

Operating Conditions (Unless Otherwise Noted) ... 51

4.4 Current Consumption ............................... 52

4.5 Flash Timing ........................................ 56

Power, Reset, Clocking, and Interrupts ........... 58

5

4

Contents

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TMS320F28050

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TMS320F28052, TMS320F28051, TMS320F28050

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SPRS797 –NOVEMBER 2012

2 Device Overview

2.1 Device Characteristics

Table 2-1 lists the features of the TMS320F2805x devices.

Device Overview

5

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SPRS797 –NOVEMBER 2012

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2.2 Memory Maps

In Figure 2-1, Figure 2-2, Figure 2-3, and Figure 2-4, the following apply:

•

Memory blocks are not to scale.

Peripheral Frame 0, Peripheral Frame 1, Peripheral Frame 2, and Peripheral Frame 3 memory maps

are restricted to data memory only. A user program cannot access these memory maps in program

space.

•

Protected means the order of Write-followed-by-Read operations is preserved rather than the pipeline

order.

Certain memory ranges are EALLOW protected against spurious writes after configuration.

8

Device Overview

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TMS320F28050

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TMS320F28052, TMS320F28051, TMS320F28050

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SPRS797 –NOVEMBER 2012

Data Space

Prog Space

0x00 0000

0x00 0040

0x00 0400

0x00 0800

0x00 0D00

M0 Vector RAM (Enabled if VMAP = 0)

M0 SARAM (1K x 16, 0-Wait)

M1 SARAM (1K x 16, 0-Wait)

Peripheral Frame 0

PIE Vector - RAM

(256 x 16)

(Enabled if

VMAP = 1,

ENPIE = 1)

Reserved

0x00 0E00

0x00 1400

Peripheral Frame 0

CLA Registers

0x00 1480

0x00 1500

0x00 1580

0x00 2000

0x00 6000

CLA-to-CPU Message RAM

CPU-to-CLA Message RAM

Peripheral Frame 0

Reserved

Peripheral Frame 1

(1K x 16, Protected)

0x00 6400

0x00 6A00

0x00 7000

0x00 8000

0x00 8800

0x00 8C00

0x00 9000

Peripheral Frame 3

(1.5K x 16, Protected)

Reserved

Peripheral Frame 1

(1.5K x 16, Protected)

Peripheral Frame 2

(4K x 16, Protected)

L0 DPSARAM (2K x 16)

(0-Wait, Z1 or Z2 Secure Zone + ECSL, CLA Data RAM 2)

L1 DPSARAM (1K x 16)

(0-Wait, Z1 or Z2 Secure Zone + ECSL, CLA Data RAM 0)

L2 DPSARAM (1K x 16)

(0-Wait, Z1 or Z2 Secure Zone + ECSL, CLA Data RAM 1)

L3 DPSARAM (4K x 16)

(0-Wait, Z1 or Z2 Secure Zone + ECSL, CLA Prog RAM)

0x00 A000

0x00 F000

0x01 0000

Reserved

CLA Data ROM (4K x 16)

Reserved

0x3D 7800

0x3D 7A00

0x3D 7C00

User OTP, Zone 2 Passwords (512 x 16)

User OTP, Zone 1 Passwords (512 x 16)

Reserved

0x3D 7E00

0x3D 7FCB

Calibration Data

Configuration Data

Reserved

0x3D 7FF0

0x3E 8000

FLASH

(64K x 16, 10 Sectors, Dual Secure Zone + ECSL)

(Z1/Z2 User-Selectable Security Zone Per Sector)

0x3F 7FFF

0x3F 8000

Zone 1 Secure Copy Code ROM

(1K x 16)

0x3F 8400

Zone 2 Secure Copy Code ROM

(1K x 16)

0x3F 8800

0x3F D000

0x3F FFC0

Reserved

Boot ROM (12K x 16, 0-Wait)

Vector (32 Vectors, Enabled if VMAP = 1)

A. CLA-specific registers and RAM apply to the 28055 device only.

Figure 2-1. 28055 and 28054 Memory Map

Device Overview

9

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TMS320F28052, TMS320F28051, TMS320F28050

SPRS797 –NOVEMBER 2012

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Data Space

0x00 0000

Prog Space

M0 Vector RAM (Enabled if VMAP = 0)

M0 SARAM (1K x 16, 0-Wait)

0x00 0040

0x00 0400

0x00 0800

0x00 0D00

M1 SARAM (1K x 16, 0-Wait)

Peripheral Frame 0

PIE Vector - RAM

(256 x 16)

(Enabled if

VMAP = 1,

ENPIE = 1)

Reserved

0x00 0E00

0x00 1400

Peripheral Frame 0

CLA Registers

0x00 1480

0x00 1500

0x00 1580

0x00 2000

0x00 6000

CLA-to-CPU Message RAM

CPU-to-CLA Message RAM

Peripheral Frame 0

Reserved

Peripheral Frame 1

(1K x 16, Protected)

0x00 6400

0x00 6A00

0x00 7000

0x00 8000

0x00 8800

0x00 8C00

0x00 9000

Peripheral Frame 3

(1.5K x 16, Protected)

Reserved

Peripheral Frame 1

(1.5K x 16, Protected)

Peripheral Frame 2

(4K x 16, Protected)

L0 DPSARAM (2K x 16)

(0-Wait, Z1 or Z2 Secure Zone + ECSL, CLA Data RAM 2)

L1 DPSARAM (1K x 16)

(0-Wait, Z1 or Z2 Secure Zone + ECSL, CLA Data RAM 0)

L2 DPSARAM (1K x 16)

(0-Wait, Z1 or Z2 Secure Zone + ECSL, CLA Data RAM 1)

L3 DPSARAM (4K x 16)

(0-Wait, Z1 or Z2 Secure Zone + ECSL, CLA Prog RAM)

0x00 A000

0x00 F000

0x01 0000

Reserved

CLA Data ROM (4K x 16)

Reserved

0x3D 7800

0x3D 7A00

0x3D 7C00

User OTP, Zone 2 Passwords (512 x 16)

User OTP, Zone 1 Passwords (512 x 16)

Reserved

0x3D 7E00

0x3D 7FCB

Calibration Data

Configuration Data

Reserved

0x3D 7FF0

0x3F 0000

FLASH

(32K x 16, 5 Sectors, Dual Secure Zone + ECSL)

(Z1/Z2 User-Selectable Security Zone Per Sector)

0x3F 7FFF

0x3F 8000

Zone 1 Secure Copy Code ROM

(1K x 16)

0x3F 8400

Zone 2 Secure Copy Code ROM

(1K x 16)

0x3F 8800

0x3F D000

0x3F FFC0

Reserved

Boot ROM (12K x 16, 0-Wait)

Vector (32 Vectors, Enabled if VMAP = 1)

A. CLA-specific registers and RAM apply to the 28053 device only.

Figure 2-2. 28053 and 28052 Memory Map

10

Device Overview

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SPRS797 –NOVEMBER 2012

Data Space

Prog Space

0x00 0000

0x00 0040

0x00 0400

0x00 0800

0x00 0D00

M0 Vector RAM (Enabled if VMAP = 0)

M0 SARAM (1K x 16, 0-Wait)

M1 SARAM (1K x 16, 0-Wait)

Peripheral Frame 0

PIE Vector - RAM

(256 x 16)

(Enabled if

VMAP = 1,

ENPIE = 1)

Reserved

0x00 0E00

0x00 1400

Peripheral Frame 0

CLA Registers

0x00 1480

0x00 1500

0x00 1580

0x00 2000

0x00 6000

CLA-to-CPU Message RAM

CPU-to-CLA Message RAM

Peripheral Frame 0

Reserved

Peripheral Frame 1

(1K x 16, Protected)

0x00 6400

0x00 6A00

0x00 7000

0x00 8000

0x00 8800

0x00 8C00

0x00 9000

Peripheral Frame 3

(1.5K x 16, Protected)

Reserved

Peripheral Frame 1

(1.5K x 16, Protected)

Peripheral Frame 2

(4K x 16, Protected)

Reserved

L1 DPSARAM (1K x 16)

(0-Wait, Z1 or Z2 Secure Zone + ECSL, CLA Data RAM 0)

L2 DPSARAM (1K x 16)

(0-Wait, Z1 or Z2 Secure Zone + ECSL, CLA Data RAM 1)

L3 DPSARAM (4K x 16)

(0-Wait, Z1 or Z2 Secure Zone + ECSL, CLA Prog RAM)

0x00 A000

0x00 F000

0x01 0000

Reserved

CLA Data ROM (4K x 16)

Reserved

0x3D 7800

0x3D 7A00

0x3D 7C00

User OTP, Zone 2 Passwords (512 x 16)

User OTP, Zone 1 Passwords (512 x 16)

Reserved

0x3D 7E00

0x3D 7FCB

Calibration Data

Configuration Data

Reserved

0x3D 7FF0

0x3F 0000

FLASH

(32K x 16, 5 Sectors, Dual Secure Zone + ECSL)

(Z1/Z2 User-Selectable Security Zone Per Sector)

0x3F 7FFF

0x3F 8000

Zone 1 Secure Copy Code ROM

(1K x 16)

0x3F 8400

Zone 2 Secure Copy Code ROM

(1K x 16)

0x3F 8800

0x3F D000

0x3F FFC0

Reserved

Boot ROM (12K x 16, 0-Wait)

Vector (32 Vectors, Enabled if VMAP = 1)

Figure 2-3. 28051 Memory Map

Device Overview

11

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Data Space

0x00 0000

Prog Space

M0 Vector RAM (Enabled if VMAP = 0)

M0 SARAM (1K x 16, 0-Wait)

0x00 0040

0x00 0400

0x00 0800

0x00 0D00

M1 SARAM (1K x 16, 0-Wait)

Peripheral Frame 0

PIE Vector - RAM

(256 x 16)

(Enabled if

VMAP = 1,

ENPIE = 1)

Reserved

0x00 0E00

0x00 1400

Peripheral Frame 0

Reserved

0x00 1580

0x00 2000

0x00 6000

Peripheral Frame 0

Reserved

Peripheral Frame 1

(1K x 16, Protected)

0x00 6400

0x00 6A00

0x00 7000

0x00 8000

0x00 8800

0x00 8C00

0x00 9000

Peripheral Frame 3

(1.5K x 16, Protected)

Reserved

Peripheral Frame 1

(1.5K x 16, Protected)

Peripheral Frame 2

(4K x 16, Protected)

L0 DPSARAM (2K x 16)

(0-Wait, Z1 or Z2 Secure Zone + ECSL)

L1 DPSARAM (1K x 16)

(0-Wait, Z1 or Z2 Secure Zone + ECSL)

L2 DPSARAM (1K x 16)

(0-Wait, Z1 or Z2 Secure Zone + ECSL)

Reserved

0x00 A000

0x00 F000

0x01 0000

Reserved

0x3D 7800

0x3D 7A00

0x3D 7C00

User OTP, Zone 2 Passwords (512 x 16)

User OTP, Zone 1 Passwords (512 x 16)

Reserved

0x3D 7E00

0x3D 7FCB

Calibration Data

Configuration Data

Reserved

0x3D 7FF0

0x3F 4000

FLASH

(16K x 16, 3 Sectors, Dual Secure Zone + ECSL)

(Z1/Z2 User-Selectable Security Zone Per Sector)

0x3F 7FFF

0x3F 8000

Zone 1 Secure Copy Code ROM

(1K x 16)

0x3F 8400

Zone 2 Secure Copy Code ROM

(1K x 16)

0x3F 8800

0x3F D000

0x3F FFC0

Reserved

Boot ROM (12K x 16, 0-Wait)

Vector (32 Vectors, Enabled if VMAP = 1)

Figure 2-4. 28050 Memory Map

12

Device Overview

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SPRS797 –NOVEMBER 2012

Table 2-2. Addresses of Flash Sectors in F28055 and F28054

ADDRESS RANGE

0x3E 8000 – 0x3E 8FFF

0x3E 9000 – 0x3E 9FFF

0x3E A000 – 0x3E BFFF

0x3E C000 – 0x3E DFFF

0x3E E000 – 0x3E FFFF

0x3F 0000 – 0x3F 1FFF

0x3F 2000 – 0x3F 3FFF

0x3F 4000 – 0x3F 5FFF

0x3F 6000 – 0x3F 6FFF

0x3F 7000 – 0x3F 7FFF

PROGRAM AND DATA SPACE

Sector J (4K x 16)

Sector I (4K x 16)

Sector H (8K x 16)

Sector G (8K x 16)

Sector F (8K x 16)

Sector E (8K x 16)

Sector D (8K x 16)

Sector C (8K x 16)

Sector B (4K x 16)

Sector A (4K x 16)

Table 2-3. Addresses of Flash Sectors in F28053, F28052, and F28051

ADDRESS RANGE

0x3F 0000 – 0x3F 1FFF

0x3F 2000 – 0x3F 3FFF

0x3F 4000 – 0x3F 5FFF

0x3F 6000 – 0x3F 6FFF

0x3F 7000 – 0x3F 7FFF

PROGRAM AND DATA SPACE

Sector E (8K x 16)

Sector D (8K x 16)

Sector C (8K x 16)

Sector B (4K x 16)

Sector A (4K x 16)

Table 2-4. Addresses of Flash Sectors in F28050

ADDRESS RANGE

0x3F 4000 – 0x3F 5FFF

0x3F 6000 – 0x3F 6FFF

0x3F 7000 – 0x3F 7FFF

PROGRAM AND DATA SPACE

Sector C (8K x 16)

Sector B (4K x 16)

Sector A (4K x 16)

Device Overview

13

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Peripheral Frame 1, Peripheral Frame 2, and Peripheral Frame 3 are grouped together to enable these

blocks to be write/read peripheral block protected. The protected mode makes sure that all accesses to

these blocks happen as written. Because of the pipeline, a write immediately followed by a read to

different memory locations will appear in reverse order on the memory bus of the CPU. This action can

cause problems in certain peripheral applications where the user expected the write to occur first (as

written). The CPU supports a block protection mode where a region of memory can be protected so that

operations occur as written (the penalty is extra cycles are added to align the operations). This mode is

programmable, and by default, it protects the selected zones.

The wait-states for the various spaces in the memory map area are listed in Table 2-5.

Table 2-5. Wait-States

AREA

WAIT-STATES (CPU)

0-wait

COMMENTS

M0 and M1 SARAMs

Peripheral Frame 0

Peripheral Frame 1

Fixed

0-wait

0-wait (writes)

2-wait (reads)

Cycles can be extended by peripheral generated ready.

Back-to-back write operations to Peripheral Frame 1 registers will incur

a 1-cycle stall (1-cycle delay).

Peripheral Frame 2

Peripheral Frame 3

0-wait (writes)

2-wait (reads)

Fixed. Cycles cannot be extended by the peripheral.

0-wait (writes)

Assumes no conflict between CPU and CLA.

Cycles can be extended by peripheral-generated ready.

Assumes no CPU conflicts

2-wait (reads)

L0 SARAM

L1 SARAM

L2 SARAM

L3 SARAM

OTP

0-wait data and program

Programmable

Assumes no CPU conflicts

Programmed via the Flash registers.

1-wait is minimum number of wait states allowed.

Programmed via the Flash registers.

1-wait minimum

FLASH

Programmable

0-wait Paged min

1-wait Random min

Random ≥ Paged

FLASH Password

Boot-ROM

16-wait fixed

0-wait

Wait states of password locations are fixed.

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2.3 Brief Descriptions

2.3.1 CPU

The 2805x (C28x) family is a member of the TMS320C2000™ microcontroller (MCU) platform. The C28x-

based controllers have the same 32-bit fixed-point architecture as existing C28x MCUs. Each C28x-based

controller, including the 2805x device, is a very efficient C/C++ engine, enabling users to develop not only

their system control software in a high-level language, but also enabling development of math algorithms

using C/C++. The device is as efficient at MCU math tasks as it is at system control tasks. This efficiency

removes the need for a second processor in many systems. The 32 x 32-bit MAC 64-bit processing

capabilities enable the controller to handle higher numerical resolution problems efficiently. Add to this

feature the fast interrupt response with automatic context save of critical registers, resulting in a device

that is capable of servicing many asynchronous events with minimal latency. The device has an 8-level-

deep protected pipeline with pipelined memory accesses. This pipelining enables the device to execute at

high speeds without resorting to expensive high-speed memories. Special branch-look-ahead hardware

minimizes the latency for conditional discontinuities. Special store conditional operations further improve

performance.

2.3.2 Control Law Accelerator (CLA)

The C28x control law accelerator is a single-precision (32-bit) floating-point unit that extends the

capabilities of the C28x CPU by adding parallel processing. The CLA is an independent processor with its

own bus structure, fetch mechanism, and pipeline. Eight individual CLA tasks, or routines, can be

specified. Each task is started by software or a peripheral such as the ADC, ePWM, eCAP, eQEP, or CPU

Timer 0. The CLA executes one task at a time to completion. When a task completes the main CPU is

notified by an interrupt to the PIE and the CLA automatically begins the next highest-priority pending task.

The CLA can directly access the ADC Result registers, ePWM, eCAP, eQEP, and the Comparator and

DAC registers. Dedicated message RAMs provide a method to pass additional data between the main

CPU and the CLA.

2.3.3 Memory Bus (Harvard Bus Architecture)

As with many MCU-type devices, multiple busses are used to move data between the memories and

peripherals and the CPU. The memory bus architecture contains a program read bus, data read bus, and

data write bus. The program read bus consists of 22 address lines and 32 data lines. The data read and

write busses consist of 32 address lines and 32 data lines each. The 32-bit-wide data busses enable

single cycle 32-bit operations. The multiple bus architecture, commonly termed Harvard Bus, enables the

C28x to fetch an instruction, read a data value and write a data value in a single cycle. All peripherals and

memories attached to the memory bus prioritize memory accesses. Generally, the priority of memory bus

accesses can be summarized as follows:

Highest:

Data Writes

(Simultaneous data and program writes cannot occur on the

memory bus.)

Program Writes

(Simultaneous data and program writes cannot occur on the

memory bus.)

Data Reads

Program Reads

(Simultaneous program reads and fetches cannot occur on the

memory bus.)

Lowest:

Fetches

(Simultaneous program reads and fetches cannot occur on the

memory bus.)

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2.3.4 Peripheral Bus

To enable migration of peripherals between various Texas Instruments (TI) MCU family of devices, the

devices adopt a peripheral bus standard for peripheral interconnect. The peripheral bus bridge multiplexes

the various busses that make up the processor Memory Bus into a single bus consisting of 16 address

lines and 16 or 32 data lines and associated control signals. Three versions of the peripheral bus are

supported. One version supports only 16-bit accesses (called peripheral frame 2). Another version

supports both 16- and 32-bit accesses (called peripheral frame 1). The third version supports CLA access

and both 16- and 32-bit accesses (called peripheral frame 3).

2.3.5 Real-Time JTAG and Analysis

(1)

The devices implement the standard IEEE 1149.1 JTAG

interface for in-circuit based debug.

Additionally, the devices support real-time mode of operation allowing modification of the contents of

memory, peripheral, and register locations while the processor is running and executing code and

servicing interrupts. The user can also single step through non-time-critical code while enabling time-

critical interrupts to be serviced without interference. The device implements the real-time mode in

hardware within the CPU. This feature is unique to the 28x family of devices, and requires no software

monitor. Additionally, special analysis hardware is provided that allows setting of hardware breakpoint or

data/address watch-points and generating various user-selectable break events when a match occurs.

These devices do not support boundary scan; however, IDCODE and BYPASS features are available if

the following considerations are taken into account. The IDCODE does not come by default. The user

needs to go through a sequence of SHIFT IR and SHIFT DR state of JTAG to get the IDCODE. For

BYPASS instruction, the first shifted DR value would be 1.

2.3.6 Flash

The F28055 and F28054 devices contain 64K x 16 of embedded flash memory, segregated into six

8K x 16 sectors and four 4K x 16 sectors. The F28053, F28052, and F28051 devices contain 32K x 16 of

embedded flash memory, segregated into three 8K x 16 sectors and two 4K x 16 sectors. The F28050

device contains 16K x 16 of embedded flash memory, segregated into one 8K x 16 sector and two 4K x

16 sectors. The devices also contain a single 1K x 16 of OTP memory at address range 0x3D 7800 –

0x3D 7BFF. The user can individually erase, program, and validate a flash sector while leaving other

sectors untouched. However, it is not possible to use one sector of the flash or the OTP to execute flash

algorithms that erase or program other sectors. Special memory pipelining is provided to enable the flash

module to achieve higher performance. The flash/OTP is mapped to both program and data space;

therefore, the flash/OTP can be used to execute code or store data information.

NOTE

The Flash and OTP wait-states can be configured by the application. This feature allows

applications running at slower frequencies to configure the flash to use fewer wait-states.

Flash effective performance can be improved by enabling the flash pipeline mode in the

Flash options register. With this mode enabled, effective performance of linear code

execution will be much faster than the raw performance indicated by the wait-state

configuration alone. The exact performance gain when using the Flash pipeline mode is

application-dependent.

For more information on the Flash options, Flash wait-state, and OTP wait-state registers,

see the System Control and Interrupts chapter of the TMS320x2805x Piccolo Technical

Reference Manual (literature number SPRUHE5).

(1) IEEE Standard 1149.1-1990 Standard Test Access Port and Boundary Scan Architecture

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2.3.7 M0, M1 SARAMs

All devices contain these two blocks of single access memory, each 1K x 16 in size. The stack pointer

points to the beginning of block M1 on reset. The M0 and M1 blocks, like all other memory blocks on C28x

devices, are mapped to both program and data space. Hence, the user can use M0 and M1 to execute

code or for data variables. The partitioning is performed within the linker. The C28x device presents a

unified memory map to the programmer, which makes for easier programming in high-level languages.

2.3.8 L0 SARAM, and L1, L2, and L3 DPSARAMs

The device contains up to 8K x 16 of single-access RAM. To ascertain the exact size for a given device,

see the device-specific memory map figures in Section 2.2. This block is mapped to both program and

data space. Block L0 is 2K in size and is dual mapped to both program and data space. Blocks L1 and L2

are both 1K in size, and together with L0, are shared with the CLA which can ultilize these blocks for its

data space. Block L3 is 4K in size and is shared with the CLA which can ultilize this block for its program

space. DPSARAM refers to the dual-port configuration of these blocks.

2.3.9 Boot ROM

The Boot ROM is factory-programmed with boot-loading software. Boot-mode signals are provided to tell

the bootloader software what boot mode to use on power up. The user can select to boot normally or to

download new software from an external connection or to select boot software that is programmed in the

internal Flash/ROM. The Boot ROM also contains standard tables, such as SIN/COS waveforms, for use

in math-related algorithms.

Table 2-6. Boot Mode Selection

GPIO34/COMP2OUT/

MODE

GPIO37/TDO

TRST

MODE

COMP3OUT

3

2

1

0

x

1

0

1

0

x

0

1

GetMode

Wait (see Section 2.3.10 for description)

1

SCI

0

Parallel IO

Emulation Boot

EMU

2.3.9.1 Emulation Boot

When the emulator is connected, the GPIO37/TDO pin cannot be used for boot mode selection. In this

case, the boot ROM detects that an emulator is connected and uses the contents of two reserved SARAM

locations in the PIE vector table to determine the boot mode. If the content of either location is invalid,

then the Wait boot option is used. All boot mode options can be accessed in emulation boot.

2.3.9.2 GetMode

The default behavior of the GetMode option is to boot to flash. This behavior can be changed to another

boot option by programming two locations in the OTP. If the content of either OTP location is invalid, then

boot to flash is used. One of the following loaders can be specified: SCI, SPI, I2C, CAN, or OTP.

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2.3.9.3 Peripheral Pins Used by the Bootloader

Table 2-7 shows which GPIO pins are used by each peripheral bootloader. Refer to the GPIO mux table

to see if these conflict with any of the peripherals you would like to use in your application.

Table 2-7. Peripheral Bootload Pins

BOOTLOADER

PERIPHERAL LOADER PINS

SCIRXDA (GPIO28)

SCI

SCITXDA (GPIO29)

Parallel Boot

SPI

Data (GPIO31,30,5:0)

28x Control (GPIO26)

Host Control (GPIO27)

SPISIMOA (GPIO16)

SPISOMIA (GPIO17)

SPICLKA (GPIO18)

SPISTEA (GPIO19)

I2C

SDAA (GPIO28)

SCLA (GPIO29)

CAN

CANRXA (GPIO30)

CANTXA (GPIO31)

2.3.10 Security

The TMS320F2805x device supports high levels of security with a dual-zone (Z1/Z2) feature to protect

user's firmware from being reverse-engineered. The dual-zone feature enables the user to co-develop

application software with a third-party or sub-contractor by preventing visibility into each other's software

IP. The security features a 128-bit password (hardcoded for 16 wait states) for each zone, which the user

programs into the USER-OTP. Each zone has its own dedicated USER-OTP, which needs to be

programmed by the user with the required security settings, including the 128-bit password. Since OTP

cannot be erased, in order to provide the user with the flexibility of changing security-related settings and

passwords multiple times, a 32-bit link pointer is stored at the beginning of each USER-OTP. Considering

the fact that user can only flip a ‘1’ in USER-OTP to ‘0’, the most significant bit position in the link pointer,

programmed as 0, defines the USER-OTP region (zone-select) for each zone in which security-related

settings and passwords are stored.

Table 2-8. Location of Zone-Select Block Based on Link Pointer

Zx LINK POINTER VALUE

ADDRESS OFFSET FOR ZONE-SELECT

32’bxx111111111111111111111111111111

32’bxx111111111111111111111111111110

32’bxx11111111111111111111111111110x

32’bxx1111111111111111111111111110xx

32’bxx111111111111111111111111110xxx

32’bxx11111111111111111111111110xxxx

32’bxx1111111111111111111111110xxxxx

32’bxx111111111111111111111110xxxxxx

32’bxx11111111111111111111110xxxxxxx

32’bxx1111111111111111111110xxxxxxxx

32’bxx111111111111111111110xxxxxxxxx

32’bxx11111111111111111110xxxxxxxxxx

32’bxx1111111111111111110xxxxxxxxxxx

32’bxx111111111111111110xxxxxxxxxxxx

32’bxx11111111111111110xxxxxxxxxxxxx

0x10

0x20

0x30

0x40

0x50

0x60

0x70

0x80

0x90

0xa0

0xb0

0xc0

0xd0

0xe0

0xf0

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Table 2-8. Location of Zone-Select Block Based on Link Pointer (continued)

Zx LINK POINTER VALUE

ADDRESS OFFSET FOR ZONE-SELECT

32’bxx1111111111111110xxxxxxxxxxxxxx

32’bxx111111111111110xxxxxxxxxxxxxxx

32’bxx11111111111110xxxxxxxxxxxxxxxx

32’bxx1111111111110xxxxxxxxxxxxxxxxx

32’bxx111111111110xxxxxxxxxxxxxxxxxx

32’bxx11111111110xxxxxxxxxxxxxxxxxxx

32’bxx1111111110xxxxxxxxxxxxxxxxxxxx

32’bxx111111110xxxxxxxxxxxxxxxxxxxxx

32’bxx11111110xxxxxxxxxxxxxxxxxxxxxx

32’bxx1111110xxxxxxxxxxxxxxxxxxxxxxx

32’bxx111110xxxxxxxxxxxxxxxxxxxxxxxx

32’bxx11110xxxxxxxxxxxxxxxxxxxxxxxxx

32’bxx1110xxxxxxxxxxxxxxxxxxxxxxxxxx

32’bxx110xxxxxxxxxxxxxxxxxxxxxxxxxxx

32’bxx10xxxxxxxxxxxxxxxxxxxxxxxxxxxx

32’bxx0xxxxxxxxxxxxxxxxxxxxxxxxxxxxx

0x100

0x110

0x120

0x130

0x140

0x150

0x160

0x170

0x180

0x190

0x1a0

0x1b0

0x1c0

0x1d0

0x1e0

0x1f0

Table 2-9. Zone-Select Block Organization in USER-OTP

16-BIT ADDRESS OFFSET

(WITH RESPECT TO OFFSET OF ZONE-SELECT)

CONTENT

0x0

0x1

0x2

0x3

0x4

0x5

0x6

0x7

0x8

0x9

0xa

0xb

0xc

0xd

0xe

0xf

Zx-EXEONLYRAM

Zx-EXEONLYSECT

Zx-GRABRAM

Zx-GRABSECT

Zx-CSMPSWD0

Zx-CSMPSWD1

Zx-CSMPSWD2

Zx-CSMPSWD3

The Dual Code Security Module (DCSM) is used to protect the Flash/OTP/Lx SARAM blocks/CLA/Secure

ROM content. Individual flash sectors and SARAM blocks can be attached to any of the secure zone at

start-up time. Secure ROM and the CLA are always attached to Z1. Resources attached to (owned by)

one zone do not have any access to code running in the other zone when it is secured. Individual flash

sectors, as well as SARAM blocks, can be further protected by enabling the EXEONLY protection.

EXEONLY flash sectors or SARAM blocks do not have READ/WRITE access. Only code execution is

allowed from such memory blocks.

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The security feature prevents unauthorized users from examining memory contents via the JTAG port,

executing code from external memory, or trying to boot load an undesirable software that would export the

secure memory contents. To enable access to the secure blocks of a particular zone, the user must write

a 128-bit value in the zone’s CSMKEY registers that matches the values stored in the password locations

in USER-OTP. If the 128 bits of the password locations in USER-OTP of a particular zone are all ones

(un-programmed), then the security for that zone gets UNLOCKED as soon as a dummy read is done to

the password locations in USER-OTP (the value in the CSMKEY register becomes "Don’t care" in this

case).

In addition to the DCSM, the Emulation Code Security Logic (ECSL) has been implemented for each zone

to prevent unauthorized users from stepping through secure code. A halt inside secure code will trip the

ECSL and break the emulation connection. To allow emulation of secure code while maintaining DCSM

protection against secure memory reads, the user must write the lower 64 bits of the USER-OTP

password into the zone's CSMKEY register to disable the ECSL. Note that dummy reads of all 128 bits of

the password for that particular zone in USER-OTP must still be performed. If the lower 64 bits of the

password locations of a particular zone are all zeros, then the ECSL for that zone gets disabled as soon

as a dummy read is done to the password locations in USER-OTP (the value in the CSMKEY register

becomes "Don’t care" in this case).

When initially debugging a device with the password locations in OTP (that is, secured), the CPU will start

running and may execute an instruction that performs an access to ECSL-protected area. If the CPU

execution is halted when the program counter belongs to the secure code region, the ECSL will trip and

cause the emulator connection to be cut. The solution is to use the Wait boot option. The Wait boot option

will sit in a loop around a software breakpoint to allow an emulator to be connected without tripping

security. The user can then exit this mode once the emulator is connected by using one of the emulation

boot options as described in the Boot ROM chapter of the TMS320x2805x Piccolo Technical Reference

Manual (literature number SPRUHE5). 2805x devices do not support hardware wait-in-reset mode.

To prevent reverse-engineering of the code in secure zone, unauthorized users are prevented from

looking at the CPU registers in the CCS Expressions Window. The values in the Expressions Window for

all of these registers, except for PC and some status bits, display false values when code is running from

a secure zone. This feature gets disabled if the zone is unlocked.

NOTE

•

The USER-OTP contains security-related settings for their respective zone. Execution is

not allowed from the USER-OTP; therefore, the user should not keep any code/data in

this region.

•

The 128-bit password must not be programmed to zeros. Doing so would permanently

lock the device.

The user must try not to write into the CPU registers through the debugger watch window

when code is running/halted from/inside secure zone. This may corrupt the execution of

the actual program.

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Disclaimer

Dual Code Security Module Disclaimer

THE DUAL CODE SECURITY MODULE (DCSM) INCLUDED ON THIS DEVICE WAS

DESIGNED TO PASSWORD PROTECT THE DATA STORED IN THE ASSOCIATED

MEMORY (EITHER ROM OR FLASH) AND IS WARRANTED BY TEXAS INSTRUMENTS

(TI), IN ACCORDANCE WITH ITS STANDARD TERMS AND CONDITIONS, TO CONFORM

TO TI'S PUBLISHED SPECIFICATIONS FOR THE WARRANTY PERIOD APPLICABLE

FOR THIS DEVICE.

TI DOES NOT, HOWEVER, WARRANT OR REPRESENT THAT THE DCSM CANNOT BE

COMPROMISED OR BREACHED OR THAT THE DATA STORED IN THE ASSOCIATED

MEMORY CANNOT BE ACCESSED THROUGH OTHER MEANS. MOREOVER, EXCEPT

AS SET FORTH ABOVE, TI MAKES NO WARRANTIES OR REPRESENTATIONS

CONCERNING THE DCSM OR OPERATION OF THIS DEVICE, INCLUDING ANY IMPLIED

WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.

IN NO EVENT SHALL TI BE LIABLE FOR ANY CONSEQUENTIAL, SPECIAL, INDIRECT,

INCIDENTAL, OR PUNITIVE DAMAGES, HOWEVER CAUSED, ARISING IN ANY WAY

OUT OF YOUR USE OF THE DCSM OR THIS DEVICE, WHETHER OR NOT TI HAS BEEN

ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. EXCLUDED DAMAGES INCLUDE,

BUT ARE NOT LIMITED TO LOSS OF DATA, LOSS OF GOODWILL, LOSS OF USE OR

INTERRUPTION OF BUSINESS OR OTHER ECONOMIC LOSS.

2.3.11 Peripheral Interrupt Expansion (PIE) Block

The PIE block serves to multiplex numerous interrupt sources into a smaller set of interrupt inputs. The

PIE block can support up to 96 peripheral interrupts. On the F2805x devices, 54 of the possible 96

interrupts are used by peripherals. The 96 interrupts are grouped into blocks of 8 and each group is fed

into 1 of 12 CPU interrupt lines (INT1 to INT12). Each of the 96 interrupts is supported by its own vector

stored in a dedicated RAM block that can be overwritten by the user. The vector is automatically fetched

by the CPU on servicing the interrupt. Eight CPU clock cycles are needed to fetch the vector and save

critical CPU registers. Hence the CPU can quickly respond to interrupt events. Prioritization of interrupts is

controlled in hardware and software. Each individual interrupt can be enabled or disabled within the PIE

block.

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2.3.12 External Interrupts (XINT1–XINT3)

The devices support three masked external interrupts (XINT1–XINT3). Each of the interrupts can be

selected for negative, positive, or both negative and positive edge triggering and can also be enabled or

disabled. These interrupts also contain a 16-bit free running up counter, which is reset to zero when a

valid interrupt edge is detected. This counter can be used to accurately time stamp the interrupt. There are

no dedicated pins for the external interrupts. XINT1, XINT2, and XINT3 interrupts can accept inputs from

GPIO0–GPIO31 pins.

2.3.13 Internal Zero-Pin Oscillators, Oscillator, and PLL

The device can be clocked by either of the two internal zero-pin oscillators, an external oscillator, or by a

crystal attached to the on-chip oscillator circuit. A PLL is provided supporting up to 12 input-clock-scaling

ratios. The PLL ratios can be changed on-the-fly in software, enabling the user to scale back on operating

frequency if lower power operation is desired. Refer to Section 5.2 for timing details. The PLL block can

be set in bypass mode.

2.3.14 Watchdog

Each device contains two watchdogs: CPU-Watchdog that monitors the core and NMI-Watchdog that is a

missing clock-detect circuit. The user software must regularly reset the CPU-watchdog counter within a

certain time frame; otherwise, the CPU-watchdog generates a reset to the processor. The CPU-watchdog

can be disabled if necessary. The NMI-Watchdog engages only in case of a clock failure and can either

generate an interrupt or a device reset.

2.3.15 Peripheral Clocking

The clocks to each individual peripheral can be enabled or disabled to reduce power consumption when a

peripheral is not in use. Additionally, the system clock to the serial ports (except I2C) can be scaled

relative to the CPU clock.

2.3.16 Low-power Modes

The devices are full-static CMOS devices. Three low-power modes are provided:

IDLE:

Place CPU in low-power mode. Peripheral clocks may be turned off selectively and

only those peripherals that need to function during IDLE are left operating. An

enabled interrupt from an active peripheral or the watchdog timer will wake the

processor from IDLE mode.

STANDBY: Turns off clock to CPU and peripherals. This mode leaves the oscillator and PLL

functional. An external interrupt event will wake the processor and the peripherals.

Execution begins on the next valid cycle after detection of the interrupt event

HALT:

This mode basically shuts down the device and places the device in the lowest

possible power consumption mode. If the internal zero-pin oscillators are used as the

clock source, the HALT mode turns them off, by default. To keep these oscillators

from shutting down, the INTOSCnHALTI bits in CLKCTL register may be used. The

zero-pin oscillators may thus be used to clock the CPU-watchdog in this mode. If the

on-chip crystal oscillator is used as the clock source, the crystal oscillator is shut

down in this mode. A reset or an external signal (through a GPIO pin) or the CPU-

watchdog can wake the device from this mode.

The CPU clock (OSCCLK) and WDCLK should be from the same clock source before attempting to put

the device into HALT or STANDBY.

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2.3.17 Peripheral Frames 0, 1, 2, 3 (PFn)

The device segregates peripherals into four sections. The mapping of peripherals is as follows:

PF0:

PIE:

PIE Interrupt Enable and Control Registers Plus PIE Vector Table

Flash Waitstate Registers

Flash:

Timers:

DCSM:

ADC:

CLA

CPU-Timers 0, 1, 2 Registers

Dual Zone Security Module Registers

ADC Result Registers

Control Law Accelrator Registers and Message RAMs

GPIO MUX Configuration and Control Registers

Enhanced Control Area Network Configuration and Control Registers

Enhanced Capture Module and Registers

PF1:

PF2:

GPIO:

eCAN:

eCAP:

eQEP:

SYS:

Enhanced Quadrature Encoder Pulse Module and Registers

System Control Registers

SCI:

Serial Communications Interface (SCI) Control and RX/TX Registers

Serial Port Interface (SPI) Control and RX/TX Registers

ADC Status, Control, and Configuration Registers

Inter-Integrated Circuit Module and Registers

External Interrupt Registers

SPI:

ADC:

I2C:

XINT:

ePWM:

PF3:

Enhanced Pulse Width Modulator Module and Registers

Comparators and Comparator Modules

Digital Filters:

eCAP:

eQEP:

ADC:

DAC:

Enhanced Capture Module and Registers

Enhanced Quadrature Encoder Pulse Module and Registers

ADC Status, Control, and Configuration Registers

ADC Result Registers

DAC Control Registers

2.3.18 General-Purpose Input/Output (GPIO) Multiplexer

Most of the peripheral signals are multiplexed with general-purpose input/output (GPIO) signals. This

muxing enables the user to use a pin as GPIO if the peripheral signal or function is not used. On reset,

GPIO pins are configured as inputs. The user can individually program each pin for GPIO mode or

peripheral signal mode. For specific inputs, the user can also select the number of input qualification

cycles. This selection is to filter unwanted noise glitches. The GPIO signals can also be used to bring the

device out of specific low-power modes.

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2.3.19 32-Bit CPU-Timers (0, 1, 2)

CPU-Timers 0, 1, and 2 are identical 32-bit timers with presettable periods and with 16-bit clock

prescaling. The timers have a 32-bit count-down register, which generates an interrupt when the counter

reaches zero. The counter is decremented at the CPU clock speed divided by the prescale value setting.

When the counter reaches zero, the counter is automatically reloaded with a 32-bit period value.

CPU-Timer 0 is for general use and is connected to the PIE block. CPU-Timer 1 is also for general use

and can be connected to INT13 of the CPU. CPU-Timer 2 is reserved for DSP/BIOS. CPU-Timer 2 is

connected to INT14 of the CPU. If DSP/BIOS is not being used, CPU-Timer 2 is available for general use.

CPU-Timer 2 can be clocked by any one of the following:

•

SYSCLKOUT (default)

Internal zero-pin oscillator 1 (INTOSC1)

Internal zero-pin oscillator 2 (INTSOC2)

External clock source

2.3.20 Control Peripherals

The devices support the following peripherals that are used for embedded control and communication:

ePWM:

The enhanced PWM peripheral supports independent/complementary

PWM generation, adjustable dead-band generation for leading/trailing

edges, latched/cycle-by-cycle trip mechanism. The type 1 module found on

2805x devices also supports increased dead-band resolution, enhanced

SOC and interrupt generation, and advanced triggering including trip

functions based on comparator outputs.

eCAP:

eQEP:

The enhanced capture peripheral uses a 32-bit time base and registers up

to four programmable events in continuous/one-shot capture modes.

This peripheral can also be configured to generate an auxiliary PWM

signal.

The enhanced QEP peripheral uses a 32-bit position counter, supports

low-speed measurement using capture unit and high-speed measurement

using a 32-bit unit timer. This peripheral has a watchdog timer to detect

motor stall and input error detection logic to identify simultaneous edge

transition in QEP signals.

ADC:

The ADC block is a 12-bit converter. The ADC has up to 16 single-ended

channels pinned out, depending on the device. The ADC also contains two

sample-and-hold units for simultaneous sampling.

Comparator and

Digital Filter

Subsystems:

Each comparator block consists of one analog comparator along with an

internal 6-bit reference for supplying one input of the comparator. The

comparator output signal filtering is achieved using the Digital Filter

present on each input line and qualifies the output of the COMP/DAC

subsystem. The filtered or unfiltered output of the COMP/DAC subsystem

can be configured to be an input to the Digital Compare submodule of the

ePWM peripheral. There is also a configurable option to bring the output of

the COMP/DAC subsystem onto the GPIO’s.

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2.3.21 Serial Port Peripherals

The devices support the following serial communication peripherals:

SPI:

The SPI is a high-speed, synchronous serial I/O port that allows a serial bit stream

of programmed length (one to sixteen bits) to be shifted into and out of the device

at a programmable bit-transfer rate. Normally, the SPI is used for communications

between the MCU and external peripherals or another processor. Typical

applications include external I/O or peripheral expansion through devices such as

shift registers, display drivers, and ADCs. Multi-device communications are

supported by the master/slave operation of the SPI. The SPI contains a 4-level

receive and transmit FIFO for reducing interrupt servicing overhead.

SCI:

I2C:

The serial communications interface is a two-wire asynchronous serial port,

commonly known as UART. The SCI contains a 4-level receive and transmit FIFO

for reducing interrupt servicing overhead.

The inter-integrated circuit (I2C) module provides an interface between an MCU

and other devices compliant with Philips Semiconductors Inter-IC bus (I2C-bus)

specification version 2.1 and connected by way of an I2C-bus. External

components attached to this 2-wire serial bus can transmit and receive up to 8-bit

data to and from the MCU through the I2C module. The I2C contains a 4-level

receive and transmit FIFO for reducing interrupt servicing overhead.

eCAN:

The eCAN is the enhanced version of the CAN peripheral. The eCAN supports 32

mailboxes, time stamping of messages, and is CAN 2.0B-compliant.

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2.4 Register Map

The devices contain four peripheral register spaces. The spaces are categorized as follows:

Peripheral Frame 0: These are peripherals that are mapped directly to the CPU memory bus.

See Table 2-10.

Peripheral Frame 1: These are peripherals that are mapped to the 32-bit peripheral bus. See

Table 2-11.

Peripheral Frame 2: These are peripherals that are mapped to the 16-bit peripheral bus. See

Table 2-12.

Peripheral Frame 3: These are peripherals that are mapped to CLA in addition to their respective

Peripheral Frame. See Table 2-13.

Table 2-10. Peripheral Frame 0 Registers⁽¹⁾

NAME

Device Emulation Registers

System Power Control Registers

FLASH Registers⁽³⁾

ADDRESS RANGE

0x00 0880 – 0x00 0984

0x00 0985 – 0x00 0987

0x00 0A80 – 0x00 0ADF

0x00 0B00 – 0x00 0B0F

0x00 0B80 – 0x00 0BBF

0x00 0BC0 – 0x00 0BEF

0x00 0C00 – 0x00 0C3F

SIZE (×16)

EALLOW PROTECTED⁽²⁾

261

3

Yes

No

96

16

64

48

64

ADC registers (0 wait read only)

DCSM Zone 1 Registers

Yes

No

DCSM Zone 2 Registers

CPU-TIMER0, CPU-TIMER1, CPU-TIMER2

Registers

PIE Registers

0x00 0CE0 – 0x00 0CFF

0x00 0D00 – 0x00 0DFF

0x00 1400 – 0x00 147F

0x00 1480 – 0x00 14FF

0x00 1500 – 0x00 157F

32

No

PIE Vector Table

256

128

CLA Registers

Yes

NA

CLA to CPU Message RAM (CPU writes ignored)

CPU to CLA Message RAM (CLA writes ignored)

(1) Registers in Frame 0 support 16-bit and 32-bit accesses.

(2) If registers are EALLOW protected, then writes cannot be performed until the EALLOW instruction is executed. The EDIS instruction

disables writes to prevent stray code or pointers from corrupting register contents.

(3) The Flash Registers are also protected by the Dual Code Security Module (DCSM).

Table 2-11. Peripheral Frame 1 Registers

NAME

ADDRESS RANGE

0x00 6000 – 0x00 61FF

0x00 6A00 – 0x00 6A1F

0x00 6B00 – 0x00 6B3F

0x00 6F80 – 0x00 6FFF

SIZE (×16)

EALLOW PROTECTED

(1)

eCAN-A Registers

eCAP1 Registers

eQEP1 Registers

GPIO Registers

512

32

No

(1)

64

(1)

128

(1) Some registers are EALLOW protected. See the module reference guide for more information.

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Table 2-12. Peripheral Frame 2 Registers

NAME

ADDRESS RANGE

0x00 7010 – 0x00 702F

0x00 7040 – 0x00 704F

0x00 7050 – 0x00 705F

0x00 7060 – 0x00 706F

0x00 7070 – 0x00 707F

0x00 7100 – 0x00 717F

0x00 7900 – 0x00 793F

SIZE (×16)

EALLOW PROTECTED

System Control Registers

SPI-A Registers

32

16

Yes

No

SCI-A Registers

16

No

NMI Watchdog Interrupt Registers

External Interrupt Registers

ADC Registers

16

Yes

16

Yes

(1)

128

64

(1)

I2C-A Registers

(1) Some registers are EALLOW protected. See the module reference guide for more information.

Table 2-13. Peripheral Frame 3 Registers

NAME

ADDRESS RANGE

SIZE (×16)

EALLOW PROTECTED

ADC registers

0x00 0B00 – 0x00 0B0F

16

No

(0 wait read only)

DAC Control Registers

0x00 6400 – 0x00 640F

0x00 6410 – 0x00 641F

16

Yes

DAC, PGA, Comparator, and Filter Enable

Registers

SWITCH Registers

Digital Filter and Comparator Control Registers

LOCK Registers

0x00 6420 – 0x00 642F

0x00 6430 – 0x00 647F

0x00 64F0 – 0x00 64FF

0x00 6800 – 0x00 683F

0x00 6840 – 0x00 687F

0x00 6880 – 0x00 68BF

0x00 68C0 – 0x00 68FF

0x00 6900 – 0x00 693F

0x00 6940 – 0x00 697F

0x00 6980 – 0x00 69BF

0x00 6A00 – 0x00 6A1F

0x00 6B00 – 0x00 6B3F

16

80

16

64

32

64

Yes

(1)

ePWM1 registers

(1)

ePWM2 registers

ePWM3 registers

ePWM4 registers

ePWM5 registers

ePWM6 registers

ePWM7 registers

eCAP1 Registers

No

(1)

eQEP1 Registers

(1) Some registers are EALLOW protected. See the module reference guide for more information.

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2.5 Device Emulation Registers

These registers are used to control the protection mode of the C28x CPU and to monitor some critical

device signals. The registers are defined in Table 2-14.

Table 2-14. Device Emulation Registers

ADDRESS

RANGE

EALLOW

PROTECTED

NAME

SIZE (x16)

DESCRIPTION

Device Configuration Register

0x0880 –

0x0881

DEVICECNF

PARTID

2

1

Yes

0x0882

PARTID Register

TMS320F28055

TMS320F28054

TMS320F28053

TMS320F28052

TMS320F28051

TMS320F28050

0x0105

0x0104

0x0103

0x0102

0x0101

0x0100

No

REVID

DC1

0x0883

1

2

Revision ID

Register

0x0000 - Silicon Rev. 0 - TMX

No

0x0886 –

0x0887

Device Capability Register 1.

The Device Capability Register is predefined by the part and

can be used to verify features. If any bit is “zero” in this

register, the module is not present. See Table 2-15.

Yes

DC2

DC3

0x0888 –

0x0889

2

Device Capability Register 2.

The Device Capability Register is predefined by the part and

can be used to verify features. If any bit is “zero” in this

register, the module is not present. See Table 2-16.

Yes

0x088A –

0x088B

Device Capability Register 3.

The Device Capability Register is predefined by the part and

can be used to verify features. If any bit is “zero” in this

register, the module is not present. See Table 2-17.

Table 2-15. Device Capability Register 1 (DC1) Field Descriptions⁽¹⁾

BIT

FIELD

RSVD

TYPE

R = 0

R

DESCRIPTION

31–30

29–22

Reserved

PARTNO

These 8 bits set the PARTNO field value in the PARTID register for the device. They

are readable in the PARTID[7:0] register bits.

21–14

RSVD

CLA

RSVD

L3

R = 0

R

Reserved

13

12–7

6

CLA is present when this bit is set.

Reserved

R = 0

R

L3 is present when this bit is set.

L2 is present when this bit is set.

L1 is present when this bit is set.

L0 is present when this bit is set.

Reserved

5

L2

R

4

L1

R

3

L0

R

2

RSVD

R = 0

1–0

Reserved

(1) All reserved bits should not be written to but if any use case demands that they must be written to, then software must write the same

value that is read back from the reserved bits. These bits are reserved for future enhancements.

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Table 2-16. Device Capability Register 2 (DC2) Field Descriptions⁽¹⁾

BIT

31–28

27

FIELD

RSVD

TYPE

R = 0

R

DESCRIPTION

Reserved

eCAN-A

RSVD

EQEP-1

RSVD

ECAP-1

RSVD

I2C-A

eCAN-A is present when this bit is set.

Reserved

26–17

16

R = 0

R

eQEP-1 is present when this bit is set.

Reserved

15–13

12

R = 0

R

eCAP-1 is present when this bit is set.

Reserved

11–9

8

R = 0

R

I2C-A is present when this bit is set.

Reserved

7–5

4

RSVD

SPI-A

R = 0

R

SPI-A is present when this bit is set.

Reserved

3

RSVD

SCI-C

SCI-B

SCI-A

R = 0

R

2

SCI-C is present when this bit is set.

SCI-B is present when this bit is set.

SCI-A is present when this bit is set.

1

R

0

R

(1) All reserved bits should not be written to but if any use case demands that they must be written to, then software must write the same

value that is read back from the reserved bits. These bits are reserved for future enhancements.

Table 2-17. Device Capability Register 3 (DC3) Field Descriptions⁽¹⁾

BIT

31–20

19

18

17

16

15

14

13

12–8

7

FIELD

RSVD

TYPE

DESCRIPTION

R = 0

R

Reserved

CTRIPFIL7

CTRIPFIL6

CTRIPFIL5

CTRIPFIL4

CTRIPFIL3

CTRIPFIL2

CTRIPFIL1

RSVD

CTRIPFIL7(B7) is present when this bit is set.

CTRIPFIL6(B6) is present when this bit is set.

CTRIPFIL5(B4) is present when this bit is set.

CTRIPFIL4(A6) is present when this bit is set.

CTRIPFIL3(B1) is present when this bit is set.

CTRIPFIL2(A3) is present when this bit is set.

CTRIPFIL1(A1) is present when this bit is set.

Reserved

R

R = 0

R

RSVD

Reserved

6

ePWM7

ePWM7 is present when this bit is set.

ePWM6 is present when this bit is set.

ePWM5 is present when this bit is set.

ePWM4 is present when this bit is set.

ePWM3 is present when this bit is set.

ePWM2 is present when this bit is set.

ePWM1 is present when this bit is set.

5

ePWM6

R

4

ePWM5

R

3

ePWM4

R

2

ePWM3

R

1

ePWM2

R

0

ePWM1

R

(1) All reserved bits should not be written to but if any use case demands that they must be written to, then software must write the same

value that is read back from the reserved bits. These bits are reserved for future enhancements.

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2.6 VREG, BOR, POR

Although the core and I/O circuitry operate on two different voltages, these devices have an on-chip

voltage regulator (VREG) to generate the V_DDvoltage from the V_DDIOsupply. This feature eliminates the

cost and space of a second external regulator on an application board. Additionally, internal power-on

reset (POR) and brown-out reset (BOR) circuits monitor both the V_DDand V_DDIOrails during power-up and

run mode.

2.6.1 On-chip Voltage Regulator (VREG)

A linear regulator generates the core voltage (V_DD) from the V_DDIOsupply. Therefore, although capacitors

are required on each V_DDpin to stabilize the generated voltage, power need not be supplied to these pins

to operate the device. Conversely, the VREG can be disabled, should power or redundancy be the

primary concern of the application.

2.6.1.1 Using the On-chip VREG

To utilize the on-chip VREG, the VREGENZ pin should be tied low and the appropriate recommended

operating voltage should be supplied to the V_DDIOand V_DDApins. In this case, the V_DDvoltage needed by

the core logic will be generated by the VREG. Each V_DDpin requires on the order of 1.2 μF (minimum)

capacitance for proper regulation of the VREG. These capacitors should be located as close as possible

to the V_DDpins.

2.6.1.2 Disabling the On-chip VREG

To conserve power, it is also possible to disable the on-chip VREG and supply the core logic voltage to

the V_DDpins with a more efficient external regulator. To enable this option, the VREGENZ pin must be tied

high.

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2.6.2 On-chip Power-On Reset (POR) and Brown-Out Reset (BOR) Circuit

The purpose of the POR is to create a clean reset throughout the device during the entire power-up

procedure. The trip point is a looser, lower trip point than the BOR, which watches for dips in the V_DDor

V_DDIOrail during device operation. The POR function is present on both V_DDand V_DDIOrails at all times.

After initial device power-up, the BOR function is present on V_DDIOat all times, and on V_DDwhen the

internal VREG is enabled (VREGENZ pin is tied low). Both functions tie the XRS pin low when one of the

voltages is below their respective trip point. Additionally, when the internal voltage regulator is enabled, an

over-voltage protection circuit will tie XRS low if the V_DDrail rises above its trip point. See Section 4.3 for

the various trip points as well as the delay time for the device to release the XRS pin after the under-

voltage or over-voltage condition is removed. Figure 2-5 shows the VREG, POR, and BOR. To disable

both the V_DDand V_DDIOBOR functions, a bit is provided in the BORCFG register. See the System Control

and Interrupts chapter of the TMS320x2805x Piccolo Technical Reference Manual (literature number

SPRUHE5) for details.

In

I/O Pin

Out

(Force Hi-Z When High)

DIR (0 = Input, 1 = Output)

SYSRS

Internal

Weak PU

SYSCLKOUT

Deglitch

XRS

Filter

Sync

RS

C28x

Core

MCLKRS

PLL

JTAG

TCK

Detect

Logic

XRS

+

Clocking

Logic

VREGHALT

WDRST^(A)

PBRS^(B)

POR/BOR

Generating

Module

On-Chip

Voltage

Regulator

(VREG)

VREGENZ

A. WDRST is the reset signal from the CPU-watchdog.

B. PBRS is the reset signal from the POR/BOR module.

Figure 2-5. VREG + POR + BOR + Reset Signal Connectivity

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2.7 System Control

This section describes the oscillator and clocking mechanisms, the watchdog function and the low power

modes.

Table 2-18. PLL, Clocking, Watchdog, and Low-Power Mode Registers

NAME

BORCFG

ADDRESS

0x00 0985

0x00 7010

0x00 7011

0x00 7012

0x00 7013

0x00 7014

0x00 7016

0x00 701B

0x00 701C

0x00 701D

0x00 701E

0x00 7020

0x00 7021

0x00 7022

0x00 7023

0x00 7024

0x00 7025

0x00 7029

SIZE (x16)

DESCRIPTION⁽¹⁾

BOR Configuration Register

1

XCLK

XCLKOUT Control

PLLSTS

PLL Status Register

CLKCTL

Clock Control Register

PLLLOCKPRD

INTOSC1TRIM

INTOSC2TRIM

LOSPCP

PCLKCR0

PCLKCR1

LPMCR0

PCLKCR3

PLLCR

PLL Lock Period

Internal Oscillator 1 Trim Register

Internal Oscillator 2 Trim Register

Low-Speed Peripheral Clock Prescaler Register

Peripheral Clock Control Register 0

Peripheral Clock Control Register 1

Low Power Mode Control Register 0

Peripheral Clock Control Register 3

PLL Control Register

SCSR

System Control and Status Register

Watchdog Counter Register

Peripheral Clock Control Register 4

Watchdog Reset Key Register

Watchdog Control Register

WDCNTR

PCLKCR4

WDKEY

WDCR

(1) All registers in this table are EALLOW protected.

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Figure 2-6 shows the various clock domains that are discussed. Figure 2-7 shows the various clock

sources (both internal and external) that can provide a clock for device operation.

SYSCLKOUT

PCLKCR0/1/3/4

(System Ctrl Regs)

LOSPCP

(System Ctrl Regs)

C28x Core

CLKIN

Clock Enables

LSPCLK

Peripheral

Registers

SPI-A, SCI-A, SCI-B, SCI-C

Clock Enables

I/O

Peripheral

Registers

eCAP1, eQEP1

/2

Peripheral

Registers

GPIO

Mux

eCAN-A

Clock Enables

ePWM1, ePWM2,

ePWM3, ePWM4,

ePWM5, ePWM6, ePWM7

Peripheral

Registers

Clock Enables

I2C-A

Peripheral

Registers

Clock Enables

ADC

Registers

9 Ch

12-Bit ADC

Analog

Clock Enables

AFE

Registers

7 Ch

A. CLKIN is the clock into the CPU. CLKIN is passed out of the CPU as SYSCLKOUT (that is, CLKIN is the same

frequency as SYSCLKOUT).

Figure 2-6. Clock and Reset Domains

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CLKCTL[WDCLKSRCSEL]

Internal

0

OSC1CLK

INTOSC1TRIM Reg^(A)

OSC 1

OSCCLKSRC1

(10 MHz)

WDCLK

CPU-Watchdog

(OSC1CLK on XRS reset)

OSCE

1

CLKCTL[INTOSC1OFF]

1 = Turn OSC Off

CLKCTL[OSCCLKSRCSEL]

OSCCLK

CLKCTL[INTOSC1HALT]

WAKEOSC

1 = Ignore HALT

0

1

Internal

OSC 2

(10 MHz)

OSC2CLK

INTOSC2TRIM Reg^(A)

PLL

Missing-Clock-Detect Circuit^(B)

(OSC1CLK on XRS reset)

OSCE

CLKCTL[TRM2CLKPRESCALE]

CLKCTL[TMR2CLKSRCSEL]

1 = Turn OSC Off

10

11

CLKCTL[INTOSC2OFF]

Prescale

/1, /2, /4,

/8, /16

SYNC

Edge

Detect

01, 10, 11

CPUTMR2CLK

1 = Ignore HALT

01

1

0

00

CLKCTL[INTOSC2HALT]

SYSCLKOUT

OSCCLKSRC2

CLKCTL[OSCCLKSRC2SEL]

0 = GPIO38

1 = GPIO19

XCLK[XCLKINSEL]

CLKCTL[XCLKINOFF]

0

1

0

GPIO19

or

XCLKIN

GPIO38

XCLKIN

X1

X2

EXTCLK

(Crystal)

OSC

XTAL

WAKEOSC

(Oscillators enabled when this signal is high)

0 = OSC on (default on reset)

1 = Turn OSC off

CLKCTL[XTALOSCOFF]

A. Register loaded from TI OTP-based calibration function.

B. See Section 2.7.4 for details on missing clock detection.

Figure 2-7. Clock Tree

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2.7.1 Internal Zero-Pin Oscillators

The F2805x devices contain two independent internal zero-pin oscillators. By default both oscillators are

turned on at power up, and internal oscillator 1 is the default clock source at this time. For power savings,

unused oscillators may be powered down by the user. The center frequency of these oscillators is

determined by their respective oscillator trim registers, written to in the calibration routine as part of the

boot ROM execution. See Section 5.2.1 for more information on these oscillators.

2.7.2 Crystal Oscillator Option

The typical specifications for the external quartz crystal (fundamental mode, parallel resonant) are listed in

Table 2-19. Furthermore, ESR range = 30 to 150 Ω.

Table 2-19. Typical Specifications for External Quartz Crystal⁽¹⁾

FREQUENCY (MHz)

R_d(Ω)

2200

470

0

C_L1(pF)

18

C_L2(pF)

18

5

10

15

20

15

0

12

(1) C_shuntshould be less than or equal to 5 pF.

XCLKIN/GPIO19/38

X1

X2

R_d

Turn off

XCLKIN path

in CLKCTL

register

C_L1

Crystal

C_L2

Figure 2-8. Using the On-chip Crystal Oscillator

NOTE

1. C_L1and C_L2are the total capacitance of the circuit board and components excluding the

IC and crystal. The value is usually approximately twice the value of the crystal's load

capacitance.

2. The load capacitance of the crystal is described in the crystal specifications of the

manufacturers.

3. TI recommends that customers have the resonator/crystal vendor characterize the

operation of their device with the MCU chip. The resonator/crystal vendor has the

equipment and expertise to tune the tank circuit. The vendor can also advise the

customer regarding the proper tank component values that will produce proper start up

and stability over the entire operating range.

XCLKIN/GPIO19/38

X1

X2

NC

External Clock Signal

(Toggling 0−V

)

DDIO

Figure 2-9. Using a 3.3-V External Oscillator

Device Overview

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2.7.3 PLL-Based Clock Module

The devices have an on-chip, PLL-based clock module. This module provides all the necessary clocking

signals for the device, as well as control for low-power mode entry. The PLL has a 4-bit ratio control

PLLCR[DIV] to select different CPU clock rates. The watchdog module should be disabled before writing

to the PLLCR register. The watchdog module can be re-enabled (if need be) after the PLL module has

stabilized, which takes 1 ms. The input clock and PLLCR[DIV] bits should be chosen in such a way that

the output frequency of the PLL (VCOCLK) is at least 50 MHz.

Table 2-20. PLL Settings

SYSCLKOUT (CLKIN)

PLLCR[DIV] VALUE^{(1) (2)}

PLLSTS[DIVSEL] = 0 or 1⁽³⁾

OSCCLK/4 (Default)⁽¹⁾

(OSCCLK * 1)/4

PLLSTS[DIVSEL] = 2

OSCCLK/2

PLLSTS[DIVSEL] = 3

OSCCLK

0000 (PLL bypass)

0001

(OSCCLK * 1)/2

(OSCCLK * 2)/2

(OSCCLK * 3)/2

(OSCCLK * 4)/2

(OSCCLK * 5)/2

(OSCCLK * 6)/2

(OSCCLK * 7)/2

(OSCCLK * 8)/2

(OSCCLK * 9)/2

(OSCCLK * 10)/2

(OSCCLK * 11)/2

(OSCCLK * 12)/2

(OSCCLK * 1)/1

(OSCCLK * 2)/1

(OSCCLK * 3)/1

(OSCCLK * 4)/1

(OSCCLK * 5)/1

(OSCCLK * 6)/1

(OSCCLK * 7)/1

(OSCCLK * 8)/1

(OSCCLK * 9)/1

(OSCCLK * 10)/1

(OSCCLK * 11)/1

(OSCCLK * 12)/1

0010

(OSCCLK * 2)/4

0011

(OSCCLK * 3)/4

0100

(OSCCLK * 4)/4

0101

(OSCCLK * 5)/4

0110

(OSCCLK * 6)/4

0111

(OSCCLK * 7)/4

1000

(OSCCLK * 8)/4

1001

(OSCCLK * 9)/4

1010

(OSCCLK * 10)/4

(OSCCLK * 11)/4

(OSCCLK * 12)/4

1011

1100

(1) The PLL control register (PLLCR) and PLL Status Register (PLLSTS) are reset to their default state by the XRS signal or a watchdog

reset only. A reset issued by the debugger or the missing clock detect logic has no effect.

(2) This register is EALLOW protected. See the System Control and Interrupts chapter of the TMS320x2805x Piccolo Technical Reference

Manual (literature number SPRUHE5) for more information.

(3) By default, PLLSTS[DIVSEL] is configured for /4. (The boot ROM changes the PLLSTS[DIVSEL] configuration to /1.) PLLSTS[DIVSEL]

must be 0 before writing to the PLLCR and should be changed only after PLLSTS[PLLLOCKS] = 1.

Table 2-21. CLKIN Divide Options

PLLSTS [DIVSEL]

CLKIN DIVIDE

0

1

2

3

/4

/2

/1

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The PLL-based clock module provides four modes of operation:

•

INTOSC1 (Internal Zero-pin Oscillator 1): INTOSC1 is the on-chip internal oscillator 1. INTOSC1 can

provide the clock for the Watchdog block, core and CPU-Timer 2.

•

INTOSC2 (Internal Zero-pin Oscillator 2): INTOSC2 is the on-chip internal oscillator 2. INTOSC2 can

provide the clock for the Watchdog block, core and CPU-Timer 2. Both INTOSC1 and INTOSC2 can

be independently chosen for the Watchdog block, core and CPU-Timer 2.

•

Crystal/Resonator Operation: The on-chip (crystal) oscillator enables the use of an external

crystal/resonator attached to the device to provide the time base. The crystal/resonator is connected to

the X1/X2 pins. Some devices may not have the X1/X2 pins. See Table 3-1 for details.

External Clock Source Operation: If the on-chip (crystal) oscillator is not used, this mode allows the

on-chip (crystal) oscillator to be bypassed. The device clocks are generated from an external clock

source input on the XCLKIN pin. Note that the XCLKIN is multiplexed with GPIO19 or GPIO38 pin. The

XCLKIN input can be selected as GPIO19 or GPIO38 via the XCLKINSEL bit in XCLK register. The

CLKCTL[XCLKINOFF] bit disables this clock input (forced low). If the clock source is not used or the

respective pins are used as GPIOs, the user should disable at boot time.

Before changing clock sources, ensure that the target clock is present. If a clock is not present, then that

clock source must be disabled (using the CLKCTL register) before switching clocks.

Table 2-22. Possible PLL Configuration Modes

CLKIN AND

SYSCLKOUT

PLL MODE

REMARKS

PLLSTS[DIVSEL]

Invoked by the user setting the PLLOFF bit in the PLLSTS register. The PLL block

is disabled in this mode. The PLL block being disabled can be useful in reducing

system noise and for low-power operation. The PLLCR register must first be set to

0x0000 (PLL Bypass) before entering this mode. The CPU clock (CLKIN) is

derived directly from the input clock on either X1/X2, X1 or XCLKIN.

0, 1

2

3

OSCCLK/4

OSCCLK/2

OSCCLK/1

PLL Off

PLL Bypass is the default PLL configuration upon power-up or after an external

reset (XRS). This mode is selected when the PLLCR register is set to 0x0000 or

while the PLL locks to a new frequency after the PLLCR register has been

modified. In this mode, the PLL itself is bypassed but the PLL is not turned off.

0, 1

2

3

OSCCLK/4

OSCCLK/2

OSCCLK/1

PLL Bypass

PLL Enable

0, 1

2

3

OSCCLK * n/4

OSCCLK * n/2

OSCCLK * n/1

Achieved by writing a non-zero value n into the PLLCR register. Upon writing to the

PLLCR the device will switch to PLL Bypass mode until the PLL locks.

2.7.4 Loss of Input Clock (NMI Watchdog Function)

The 2805x devices may be clocked from either one of the internal zero-pin oscillators (INTOSC1 or

INTOSC2), the on-chip crystal oscillator, or from an external clock input. Regardless of the clock source,

in PLL-enabled and PLL-bypass mode, if the input clock to the PLL vanishes, the PLL will issue a limp-

mode clock at its output. This limp-mode clock continues to clock the CPU and peripherals at a typical

frequency of 1–5 MHz.

When the limp mode is activated, a CLOCKFAIL signal is generated that is latched as an NMI interrupt.

Depending on how the NMIRESETSEL bit has been configured, a reset to the device can be fired

immediately or the NMI watchdog counter can issue a reset when the counter overflows. In addition to this

action, the Missing Clock Status (MCLKSTS) bit is set. The NMI interrupt could be used by the application

to detect the input clock failure and initiate necessary corrective action such as switching over to an

alternative clock source (if available) or initiate a shut-down procedure for the system.

If the software does not respond to the clock-fail condition, the NMI watchdog triggers a reset after a

preprogrammed time interval. Figure 2-10 shows the interrupt mechanisms involved.

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NMIFLG[NMINT]

NMIFLGCLR[NMINT]

Clear

Latch

Set

Clear

XRS

Generate

Interrupt

Pulse

When

Input = 1

NMIFLG[CLOCKFAIL]

Clear

Latch

1

0

NMIFLGCLR[CLOCKFAIL]

CLOCKFAIL

NMINT

SYNC?

Set

Clear

SYSCLKOUT

NMICFG[CLOCKFAIL]

NMIFLGFRC[CLOCKFAIL]

XRS

SYSCLKOUT

SYSRS

NMIWDPRD[15:0]

NMIWDCNT[15:0]

See System

Control Section

NMI Watchdog

NMIRS

Figure 2-10. NMI-watchdog

2.7.5 CPU-Watchdog Module

The CPU-watchdog module on the 2805x device is similar to the one used on the 281x, 280x, and 283xx

devices. This module generates an output pulse, 512 oscillator clocks wide (OSCCLK), whenever the 8-bit

watchdog up counter has reached its maximum value. To prevent this occurrence, the user must disable

the counter or the software must periodically write a 0x55 + 0xAA sequence into the watchdog key register

that resets the watchdog counter. Figure 2-11 shows the various functional blocks within the watchdog

module.

Normally, when the input clocks are present, the CPU-watchdog counter decrements to initiate a CPU-

watchdog reset or WDINT interrupt. However, when the external input clock fails, the CPU-watchdog

counter stops decrementing (that is, the watchdog counter does not change with the limp-mode clock).

NOTE

The CPU-watchdog is different from the NMI watchdog. The CPU-watchdog is the legacy

watchdog that is present in all 28x devices.

NOTE

Applications in which the correct CPU operating frequency is absolutely critical should

implement a mechanism by which the MCU will be held in reset, should the input clocks ever

fail. For example, an R-C circuit may be used to trigger the XRS pin of the MCU, should the

capacitor ever get fully charged. An I/O pin may be used to discharge the capacitor on a

periodic basis to prevent the capacitor from getting fully charged. Such a circuit would also

help in detecting failure of the flash memory.

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WDCR (WDPS[2:0])

WDCR (WDDIS)

WDCNTR(7:0)

WDCLK

8-Bit

Watchdog

Counter

CLR

Watchdog

Prescaler

/512

Clear Counter

Internal

Pullup

WDKEY(7:0)

WDRST

WDINT

Generate

Watchdog

55 + AA

Key Detector

Output Pulse

(512 OSCCLKs)

Good Key

XRS

Bad

WDCHK

Key

Core-reset

SCSR (WDENINT)

WDCR (WDCHK[2:0])

1

0

1

(A)

WDRST

A. The WDRST signal is driven low for 512 OSCCLK cycles.

Figure 2-11. CPU-watchdog Module

The WDINT signal enables the watchdog to be used as a wakeup from IDLE/STANDBY mode.

In STANDBY mode, all peripherals are turned off on the device. The only peripheral that remains

functional is the CPU-watchdog. This module will run off OSCCLK. The WDINT signal is fed to the LPM

block so that the signal can wake the device from STANDBY (if enabled). See Section 2.8, Low-power

Modes Block, for more details.

In IDLE mode, the WDINT signal can generate an interrupt to the CPU, via the PIE, to take the CPU out of

IDLE mode.

In HALT mode, the CPU-watchdog can be used to wake up the device through a device reset.

Device Overview

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2.8 Low-power Modes Block

Table 2-23 summarizes the various modes.

Table 2-23. Low-power Modes

MODE

LPMCR0(1:0)

OSCCLK

CLKIN

SYSCLKOUT

EXIT⁽¹⁾

XRS, CPU-watchdog interrupt, any

enabled interrupt

IDLE

00

On

XRS, CPU-watchdog interrupt, GPIO

Port A signal, debugger⁽²⁾

STANDBY

HALT⁽³⁾

01

Off

(CPU-watchdog still running)

Off

(on-chip crystal oscillator and

PLL turned off, zero-pin oscillator

and CPU-watchdog state

dependent on user code.)

XRS, GPIO Port A signal, debugger⁽²⁾

CPU-watchdog

,

1X

Off

(1) The Exit column lists which signals or under what conditions the low power mode is exited. A low signal, on any of the signals, exits the

low power condition. This signal must be kept low long enough for an interrupt to be recognized by the device. Otherwise, the low-power

mode will not be exited and the device will go back into the indicated low power mode.

(2) The JTAG port can still function even if the CPU clock (CLKIN) is turned off.

(3) The WDCLK must be active for the device to go into HALT mode.

The various low-power modes operate as follows:

IDLE Mode:

This mode is exited by any enabled interrupt that is recognized by the

processor. The LPM block performs no tasks during this mode as long as

the LPMCR0(LPM) bits are set to 0,0.

STANDBY Mode:

Any GPIO port A signal (GPIO[31:0]) can wake the device from STANDBY

mode. The user must select which signals will wake the device in the

GPIOLPMSEL register. The selected signals are also qualified by the

OSCCLK before waking the device. The number of OSCCLKs is specified in

the LPMCR0 register.

HALT Mode:

CPU-watchdog, XRS, and any GPIO port A signal (GPIO[31:0]) can wake

the device from HALT mode. The user selects the signal in the

GPIOLPMSEL register.

NOTE

The low-power modes do not affect the state of the output pins (PWM pins included). They

will be in whatever state the code left them in when the IDLE instruction was executed. See

the System Control and Interrupts chapter of the TMS320x2805x Piccolo Technical

Reference Manual (literature number SPRUHE5) for more details.

2.9 Thermal Design Considerations

Based on the end application design and operational profile, the I_DDand I_DDIOcurrents could vary.

Systems that exceed the recommended maximum power dissipation in the end product may require

additional thermal enhancements. Ambient temperature (T_A) varies with the end application and product

design. The critical factor that affects reliability and functionality is T_J, the junction temperature, not the

ambient temperature. Hence, care should be taken to keep T_Jwithin the specified limits. T_caseshould be

measured to estimate the operating junction temperature T_J. T_caseis normally measured at the center of

the package top-side surface. The thermal application reports IC Package Thermal Metrics (literature

number SPRA953) and Reliability Data for TMS320LF24xx and TMS320F28xx Devices (literature number

SPRA963) help to understand the thermal metrics and definitions.

40

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3 Device Pins

3.1 Pin Assignments

Figure 3-1 shows the 80-pin PN Low-Profile Quad Flatpack (LQFP) pin assignments.

GPIO11/EPWM6B/SCIRXDB

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

GPIO26/SCIRXDC

TEST2

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

GPIO5/EPWM3B/SPISIMOA/ECAP1

GPIO4/EPWM3A

V

DDIO

V

GPIO40/EPWM7A

SS

GPIO10/EPWM6A/ADCSOCBO

GPIO3/EPWM2B/SPISOMIA/CTRIPM2OUT (COMP2OUT)

GPIO2/EPWM2A

GPIO9/EPWM5B/SCITXDB

GPIO30/CANRXA/SCIRXDB/EPWM7A

GPIO31/CANTXA/SCITXDB/EPWM7B

GPIO27/SCITXDC

PFCGND

GPIO1/EPWM1B/CTRIPM1OUT (COMP1OUT)

GPIO0/EPWM1A

V

ADCINB7 (op-amp)

ADCINB0

DDIO

VREGENZ

V

ADCINB6 (op-amp)

ADCINB5

SS

DD

GPIO34/CTRIPM2OUT (COMP2OUT)/CTRIPPFCOUT (COMP3OUT)

GPIO15/TZ1/CTRIPM1OUT/SCIRXDB

M2GND

ADCINB4 (op-amp)

ADCINB3

GPIO13/TZ2/CTRIPM2OUT

GPIO14/TZ3/CTRIPPFCOUT/SCITXDB

ADCINA7

GPIO20/EQEP1A/EPWM7A/CTRIPM1OUT (COMP1OUT)

GPIO21/EQEP1B/EPWM7B/CTRIPM2OUT (COMP2OUT)

GPIO23/EQEP1I/SCIRXDB

ADCINA6 (op-amp)

V

REFLO

SSA

Figure 3-1. 2805x 80-Pin PN LQFP (Top View)

Device Pins

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3.2 Terminal Functions

Table 3-1 describes the signals. With the exception of the JTAG pins, the GPIO function is the default at

reset, unless otherwise mentioned. The peripheral signals that are listed under them are alternate

functions. Some peripheral functions may not be available in all devices. See Table 2-1 for details. Inputs

are not 5-V tolerant. All GPIO pins are I/O/Z and have an internal pullup, which can be selectively enabled

or disabled on a per-pin basis. This feature only applies to the GPIO pins. The pullups on the PWM pins

are not enabled at reset. The pullups on other GPIO pins are enabled upon reset.

NOTE: When the on-chip VREG is used, the GPIO19, GPIO34, GPIO35, GPIO36, GPIO37, and GPIO38

pins could glitch during power up. If this behavior is unacceptable in an application, 1.8 V could be

supplied externally. There is no power-sequencing requirement when using an external 1.8-V supply.

However, if the 3.3-V transistors in the level-shifting output buffers of the I/O pins are powered prior to the

1.9-V transistors, it is possible for the output buffers to turn on, causing a glitch to occur on the pin during

power up. To avoid this behavior, power the V_DDpins prior to or simultaneously with the V_DDIOpins,

ensuring that the V_DDpins have reached 0.7 V before the V_DDIOpins reach 0.7 V.

Table 3-1. Terminal Functions⁽¹⁾

TERMINAL

I/O/Z

DESCRIPTION

PN

PIN NO.

NAME

JTAG

JTAG test reset with internal pulldown. TRST, when driven high, gives the scan system control

of the operations of the device. If this signal is not connected or driven low, the device

operates in its functional mode, and the test reset signals are ignored. NOTE: TRST is an

active high test pin and must be maintained low at all times during normal device operation.

An external pull-down resistor is required on this pin. The value of this resistor should be

based on drive strength of the debugger pods applicable to the design. A 2.2-kΩ resistor

generally offers adequate protection. Since the value of the resistor is application-specific, TI

recommends that each target board be validated for proper operation of the debugger and the

application. (↓)

TRST

9

I

See

GPIO38

TCK

TMS

TDI

I

See GPIO38. JTAG test clock with internal pullup. (↑)

See

GPIO36

See GPIO36. JTAG test-mode select (TMS) with internal pullup. This serial control input is

clocked into the TAP controller on the rising edge of TCK.. (↑)

I

See

GPIO35

See GPIO35. JTAG test data input (TDI) with internal pullup. TDI is clocked into the selected

register (instruction or data) on a rising edge of TCK. (↑)

See

GPIO37

See GPIO37. JTAG scan out, test data output (TDO). The contents of the selected register

(instruction or data) are shifted out of TDO on the falling edge of TCK. (8 mA drive)

TDO

O/Z

FLASH

TEST2

39

I/O

Test Pin. Reserved for TI. Must be left unconnected.

(1) I = Input, O = Output, Z = High Impedance, OD = Open Drain, ↑ = Pullup, ↓ = Pulldown

42

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Table 3-1. Terminal Functions⁽¹⁾(continued)

TERMINAL

NAME

I/O/Z

DESCRIPTION

PN

PIN NO.

CLOCK

See GPIO18. Output clock derived from SYSCLKOUT. XCLKOUT is either the same

frequency, one-half the frequency, or one-fourth the frequency of SYSCLKOUT. The value of

XCLKOUT is controlled by bits 1:0 (XCLKOUTDIV) in the XCLK register. At reset, XCLKOUT

= SYSCLKOUT/4. The XCLKOUT signal can be turned off by setting XCLKOUTDIV to 3. The

mux control for GPIO18 must also be set to XCLKOUT for this signal to propogate to the pin.

See

GPIO18

XCLKOUT

O/Z

See GPIO19 and GPIO38. External oscillator input. Pin source for the clock is controlled by

the XCLKINSEL bit in the XCLK register, GPIO38 is the default selection. This pin feeds a

clock from an external 3.3-V oscillator. In this case, the X1 pin, if available, must be tied to

GND and the on-chip crystal oscillator must be disabled via bit 14 in the CLKCTL register. If a

crystal/resonator is used, the XCLKIN path must be disabled by bit 13 in the CLKCTL register.

NOTE: Designs that use the GPIO38/TCK/XCLKIN pin to supply an external clock for normal

device operation may need to incorporate some hooks to disable this path during debug using

the JTAG connector. This action is to prevent contention with the TCK signal, which is active

during JTAG debug sessions. The zero-pin internal oscillators may be used during this time to

clock the device.

See

GPIO19

and

XCLKIN

I

GPIO38

On-chip crystal-oscillator input. To use this oscillator, a quartz crystal or a ceramic resonator

must be connected across X1 and X2. In this case, the XCLKIN path must be disabled by bit

13 in the CLKCTL register. If this pin is not used, this pin must be tied to GND. (I)

X1

X2

52

51

I

On-chip crystal-oscillator output. A quartz crystal or a ceramic resonator must be connected

across X1 and X2. If X2 is not used, X2 must be left unconnected. (O)

O

RESET

Device Reset (in) and Watchdog Reset (out). The device has a built-in power-on-reset (POR)

and brown-out-reset (BOR) circuitry. As such, no external circuitry is needed to generate a

reset pulse. During a power-on or brown-out condition, this pin is driven low by the device.

See Section 4.3, Electrical Characteristics, for thresholds of the POR/BOR block. This pin is

also driven low by the MCU when a watchdog reset occurs. During watchdog reset, the XRS

pin is driven low for the watchdog reset duration of 512 OSCCLK cycles. If need be, an

external circuitry may also drive this pin to assert a device reset. In this case, TI recommends

that this pin be driven by an open-drain device. An R-C circuit must be connected to this pin

for noise immunity reasons. Regardless of the source, a device reset causes the device to

terminate execution. The program counter points to the address contained at the location

0x3FFFC0. When reset is deactivated, execution begins at the location designated by the

program counter. The output buffer of this pin is an open-drain with an internal pullup. (I/OD)

XRS

8

I/O

Device Pins

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Table 3-1. Terminal Functions⁽¹⁾(continued)

TERMINAL

NAME

I/O/Z

DESCRIPTION

PN

PIN NO.

ADC, COMPARATOR, ANALOG I/O

ADCINA7

24

23

I

ADC Group A, Channel 7 input

ADC Group A, Channel 6 input

ADC Group A, Channel 5 input

ADCINA6

(op-amp)

ADCINA5

10

11

I

O

I

ADCBGOUT

ADCINA4

ADC Group A, Channel 4 input

ADC Group A, Channel 3 input

ADC Group A, Channel 2 input

ADC Group A, Channel 1 input

ADCINA3

(op-amp)

12

13

14

18

I

ADCINA2

ADCINA1

(op-amp)

ADCINA0

V_REFOUT

ADC Group A, Channel 0 input

Voltage Reference out from buffered DAC

ADC External Reference – used when in ADC external reference mode and used as V_REFOUT

reference

V_REFHI

19

31

I

ADCINB7

(op-amp)

ADC Group B, Channel 7 input

ADCINB6

(op-amp)

29

28

26

I

ADC Group B, Channel 6 input

ADC Group B, Channel 5 input

ADC Group B, Channel 4 input

ADCINB5

ADCINB4

(op-amp)

ADCINB3

ADCINB2

25

16

I

ADC Group B, Channel 3 input

ADC Group B, Channel 2 input

ADCINB1

(op-amp)

17

I

ADC Group B, Channel 1 input

ADCINB0

V_REFLO

30

22

I

ADC Group B, Channel 0 input

ADC Low Reference (always tied to ground)

44

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Table 3-1. Terminal Functions⁽¹⁾(continued)

TERMINAL

NAME

I/O/Z

DESCRIPTION

PN

PIN NO.

CPU AND I/O POWER

V_DDA

V_SSA

V_DD

20

21

6

Analog Power Pin. Tie with a 2.2-μF capacitor (typical) close to the pin.

Analog Ground Pin

CPU and Logic Digital Power Pins – no supply source needed when using internal VREG. Tie

with 1.2 µF (minimum) ceramic capacitor (10% tolerance) to ground when using internal

VREG. Higher value capacitors may be used, but could impact supply-rail ramp-up time.

V_DD

54

73

38

70

7

V_DD

V_DDIO

V_SS

Digital I/O and Flash Power Pin – Single Supply source when VREG is enabled

V_SS

37

53

72

15

27

32

Digital Ground Pins

V_SS

M1GND

M2GND

PFCGND

Ground pin for M1 channel

Ground pin for M2 channel

Ground pin for PFC channel

VOLTAGE REGULATOR CONTROL SIGNAL

Internal VREG Enable/Disable – pull low to enable VREG, pull high to disable VREG

VREGENZ

71

69

68

I

(1)

GPIO AND PERIPHERAL SIGNALS

GPIO0

I/O/Z

O

General-purpose input/output 0

Enhanced PWM1 Output A

General-purpose input/output 1

Enhanced PWM1 Output B

EPWM1A

GPIO1

I/O/Z

O

EPWM1B

CTRIPM1OUT

(COMP1OUT)

CTRIPM1 CTRIPxx output

(Direct output of Comparator 1)

O

GPIO2

67

66

I/O/Z

O

General-purpose input/output 2

Enhanced PWM2 Output A

General-purpose input/output 3

Enhanced PWM2 Output B

SPI-A slave out, master in

EPWM2A

GPIO3

I/O/Z

O

EPWM2B

SPISOMIA

I/O

CTRIPM2OUT

(COMP2OUT)

CTRIPM2 CTRIPxx output

(Direct output of Comparator 2)

O

GPIO4

63

62

I/O/Z

O

General-purpose input/output 4

Enhanced PWM3 output A

General-purpose input/output 5

Enhanced PWM3 output B

SPI-A slave in, master out

EPWM3A

GPIO5

I/O/Z

O

EPWM3B

SPISIMOA

ECAP1

I/O

Enhanced Capture input/output 1

(1) The GPIO function (shown in bold italics) is the default at reset. The peripheral signals that are listed under them are alternate functions.

For JTAG pins that have the GPIO functionality multiplexed, the input path to the GPIO block is always valid. The output path from the

GPIO block and the path to the JTAG block from a pin is enabled or disabled based on the condition of the TRST signal. See the

System Control and Interrupts chapter of the TMS320x2805x Piccolo Technical Reference Manual (literature number SPRUHE5) for

details.

Device Pins

45

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Table 3-1. Terminal Functions⁽¹⁾(continued)

TERMINAL

NAME

I/O/Z

DESCRIPTION

PN

PIN NO.

GPIO6

EPWM4A

50

I/O/Z

General-purpose input/output 6

Enhanced PWM4 output A

External ePWM sync pulse input

External ePWM sync pulse output

General-purpose input/output 7

Enhanced PWM4 output B

SCI-A receive data

O

EPWMSYNCI

EPWMSYNCO

GPIO7

I

O

49

45

36

65

61

48

I/O/Z

O

EPWM4B

SCIRXDA

GPIO8

I

I/O/Z

O

General-purpose input/output 8

Enhanced PWM5 output A

ADC start-of-conversion A

General-purpose input/output 9

Enhanced PWM5 output B

SCI-B transmit data

EPWM5A

ADCSOCAO

GPIO9

O

I/O/Z

O

EPWM5B

SCITXDB

GPIO10

O

I/O/Z

O

General-purpose input/output 10

Enhanced PWM6 output A

ADC start-of-conversion B

General-purpose input/output 11

Enhanced PWM6 output B

SCI-B receive data

EPWM6A

ADCSOCBO

GPIO11

O

I/O/Z

O

EPWM6B

SCIRXDB

GPIO12

I

I/O/Z

I

General-purpose input/output 12

Trip Zone input 1

TZ1

CTRIPM1OUT

SCITXDA

GPIO13

O

CTRIPM1 CTRIPxx output

SCI-A transmit data

O

76

77

I/O/Z

I

General-purpose input/output 13

Trip zone input 2

TZ2

CTRIPM2OUT

GPIO14

O

CTRIPM2 CTRIPxx output

General-purpose input/output 14

Trip zone input 3

I/O/Z

I

TZ3

CTRIPPFCOUT

SCITXDB

GPIO15

O

CTRIPPFC output

O

SCI-B transmit data

75

47

I/O/Z

I

General-purpose input/output 15

Trip zone input 1

TZ1

CTRIPM1OUT

SCIRXDB

GPIO16

O

CTRIPM1 CTRIPxx output

SCI-B receive data

I

I/O/Z

I/O

I

General-purpose input/output 16

SPI-A slave in, master out

Enhanced QEP1 strobe

Trip Zone input 2

SPISIMOA

EQEP1S

TZ2

CTRIPM2OUT

GPIO17

O

CTRIPM2 CTRIPxx output

General-purpose input/output 17

SPI-A slave out, master in

Enhanced QEP1 index

44

I/O/Z

I/O

I

SPISOMIA

EQEP1I

TZ3

Trip zone input 3

CTRIPPFCOUT

O

CTRIPPFC output

46

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Table 3-1. Terminal Functions⁽¹⁾(continued)

TERMINAL

NAME

GPIO18

I/O/Z

DESCRIPTION

PN

PIN NO.

43

I/O/Z

I/O

General-purpose input/output 18

SPI-A clock input/output

SCI-B transmit data

SPICLKA

SCITXDB

XCLKOUT

O

O/Z

Output clock derived from SYSCLKOUT. XCLKOUT is either the same frequency, one-half the

frequency, or one-fourth the frequency of SYSCLKOUT. The value of XCLKOUT is controlled

by bits 1:0 (XCLKOUTDIV) in the XCLK register. At reset, XCLKOUT = SYSCLKOUT/4. The

XCLKOUT signal can be turned off by setting XCLKOUTDIV to 3. The mux control for GPIO18

must also be set to XCLKOUT for this signal to propogate to the pin.

GPIO19

55

I/O/Z

I

General-purpose input/output 19

XCLKIN

External Oscillator Input. The path from this pin to the clock block is not gated by the mux

function of this pin. Care must be taken not to enable this path for clocking if this path is being

used for the other periperhal functions

SPISTEA

SCIRXDB

ECAP1

I/O

SPI-A slave transmit enable input/output

SCI-B receive data

I

I/O

I/O/Z

I

Enhanced Capture input/output 1

General-purpose input/output 20

Enhanced QEP1 input A

GPIO20

78

79

EQEP1A

EPWM7A

O

Enhanced PWM7 output A

CTRIPM1OUT

(COMP1OUT)

CTRIPM1 CTRIPxx output

(Direct output of Comparator 1)

O

GPIO21

I/O/Z

General-purpose input/output 21

Enhanced QEP1 input B

EQEP1B

EPWM7B

I

O

Enhanced PWM7 output B

CTRIPM2OUT

(COMP2OUT)

CTRIPM2 CTRIPxx output

(Direct output of Comparator 2)

O

GPIO22

EQEP1S

SCITXDB

GPIO23

EQEP1I

SCIRXDB

GPIO24

ECAP1

1

80

4

I/O/Z

I/O

O

General-purpose input/output 22

Enhanced QEP1 strobe

SCI-B transmit data

I/O/Z

I/O

I

General-purpose input/output 23

Enhanced QEP1 index

SCI-B receive data

I/O/Z

I/O

O

General-purpose input/output 24

Enhanced Capture input/output 1

Enhanced PWM7 output A

General-purpose input/output 25

General-purpose input/output 26

SCI-C receive data

EPWM7A

GPIO25

GPIO26

SCIRXDC

GPIO27

SCITXDC

GPIO28

SCIRXDA

SDAA

46

40

I/O/Z

I

33

42

I/O/Z

O

General-purpose input/output 27

SCI-C transmit data

I/O/Z

I

General-purpose input/output 28

SCI-A receive data

I/OD

I

I2C data open-drain bidirectional port

Trip zone input 2

TZ2

CTRIPM2OUT

O

CTRIPM2 CTRIPxx output

Device Pins

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Table 3-1. Terminal Functions⁽¹⁾(continued)

TERMINAL

NAME

GPIO29

I/O/Z

DESCRIPTION

PN

PIN NO.

41

I/O/Z

O

General-purpose input/output 29

SCI-A transmit data

SCITXDA

SCLA

I/OD

I

I2C clock open-drain bidirectional port

Trip zone input 3

TZ3

CTRIPPFCOUT

GPIO30

O

CTRIPPFC output

35

34

2

I/O/Z

I

General-purpose input/output 30

CAN receive

CANRXA

SCIRXDB

EPWM7A

GPIO31

I

SCI-B receive data

O

Enhanced PWM7 output A

General-purpose input/output 31

CAN transmit

I/O/Z

O

CANTXA

SCITXDB

EPWM7B

GPIO32

O

SCI-B transmit data

O

Enhanced PWM7 output B

General-purpose input/output 32

I2C data open-drain bidirectional port

I/O/Z

I/OD

I

SDAA

EPWMSYNCI

EQEP1S

GPIO33

Enhanced PWM external sync pulse input

Enhanced QEP1 strobe

I/O

I/O/Z

I/OD

O

3

General-Purpose Input/Output 33

I2C clock open-drain bidirectional port

Enhanced PWM external synch pulse output

Enhanced QEP1 index

SCLA

EPWMSYNCO

EQEP1I

I/O

I/O/Z

GPIO34

74

General-Purpose Input/Output 34

CTRIPM2OUT

(COMP2OUT)

CTRIPM2 CTRIPxx output

(Direct output of Comparator 2)

O

CTRIPPFCOUT

(COMP3OUT)

CTRIPPFC output

(Direct output of Comparator 3)

GPIO35

TDI

59

60

58

57

I/O/Z

I

General-Purpose Input/Output 35

JTAG test data input (TDI) with internal pullup. TDI is clocked into the selected register

(instruction or data) on a rising edge of TCK

GPIO36

TMS

I/O/Z

I

General-Purpose Input/Output 36

JTAG test-mode select (TMS) with internal pullup. This serial control input is clocked into the

TAP controller on the rising edge of TCK.

GPIO37

TDO

I/O/Z

O/Z

General-Purpose Input/Output 37

JTAG scan out, test data output (TDO). The contents of the selected register (instruction or

data) are shifted out of TDO on the falling edge of TCK (8 mA drive)

GPIO38

TCK

I/O/Z

General-Purpose Input/Output 38

JTAG test clock with internal pullup

I

XCLKIN

External Oscillator Input. The path from this pin to the clock block is not gated by the mux

function of this pin. Care must be taken to not enable this path for clocking if this path is being

used for the other functions.

48

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Table 3-1. Terminal Functions⁽¹⁾(continued)

TERMINAL

NAME

GPIO39

I/O/Z

DESCRIPTION

PN

PIN NO.

56

I/O/Z

I

General-Purpose Input/Output 39

SCI-C receive data

SCIRXDC

CTRIPPFCOUT

GPIO40

O

CTRIPPFC output

64

5

I/O/Z

O

General-Purpose Input/Output 40

Enhanced PWM7 output A

General-Purpose Input/Output 42

Enhanced PWM7 output B

SCI-C transmit data

EPWM7A

GPIO42

I/O/Z

O

EPWM7B

SCITXDC

O

CTRIPM1OUT

(COMP1OUT)

CTRIPM1 CTRIPxx output

(Direct output of Comparator 1)

O

Device Pins

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4 Device Operating Conditions

4.1 Absolute Maximum Ratings^{(1) (2)}

Supply voltage range, V_DDIO(I/O and Flash)

Supply voltage range, V_DD

with respect to V_SS

–0.3 V to 4.6 V

–0.3 V to 2.5 V

–0.3 V to 4.6 V

±20 mA

with respect to V_SS

with respect to V_SSA

Analog voltage range, V_DDA

Input voltage range, V_IN(3.3 V)

Output voltage range, V_O

(3)

Input clamp current, I_IK(V_IN< 0 or V_IN> V_DDIO

)

Output clamp current, I_OK(V_O< 0 or V_O> V_DDIO

)

±20 mA

(4)

Junction temperature range, T_J

–40°C to 150°C

–65°C to 150°C

(4)

Storage temperature range, T_stg

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under Section 4.2 is not implied.

Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltage values are with respect to V_SS, unless otherwise noted.

(3) Continuous clamp current per pin is ± 2 mA.

(4) Long-term high-temperature storage or extended use at maximum temperature conditions may result in a reduction of overall device life.

For additional information, see IC Package Thermal Metrics Application Report (literature number SPRA953) and Reliability Data for

TMS320LF24xx and TMS320F28xx Devices Application Report (literature number SPRA963).

4.2 Recommended Operating Conditions

MIN

2.97

1.71

NOM

3.3

MAX

3.63

UNIT

(1)

Device supply voltage, I/O, V_DDIO

V

Device supply voltage CPU, V_DD(When internal

VREG is disabled and 1.8 V is supplied externally)

1.8

1.995

V

Supply ground, V_SS

0

3.3

0

V

(1)

Analog supply voltage, V_DDA

2.97

3.63

Analog ground, V_SSA

V

Device clock frequency (system clock)

High-level input voltage, V_IH(3.3 V)

Low-level input voltage, V_IL(3.3 V)

High-level output source current, V_OH= V_OH(MIN), I_OHAll GPIO pins

Group 2⁽²⁾

2

60

MHz

V

V_DDIO+ 0.3

V_SS– 0.3

0.8

–4

–8

4

V

mA

Low-level output sink current, V_OL= V_OL(MAX), I_OL

All GPIO pins

Group 2⁽²⁾

T version

8

Junction temperature, T_J

–40

105

125

°C

S version

(1) V_DDIOand V_DDAshould be maintained within approximately 0.3 V of each other.

(2) Group 2 pins are as follows: GPIO16, GPIO17, GPIO18, GPIO28, GPIO29, GPIO30, GPIO31, GPIO36, GPIO37

50

Device Operating Conditions

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4.3 Electrical Characteristics Over Recommended Operating Conditions (Unless

Otherwise Noted)⁽¹⁾

PARAMETER

TEST CONDITIONS

MIN

2.4

TYP

MAX UNIT

I_OH= I_OHMAX

I_OH= 50 μA

V_OH

V_OL

High-level output voltage

Low-level output voltage

V

V_DDIO– 0.2

I_OL= I_OLMAX

0.4

–205

–375

V

All GPIO pins

XRS pin

–80

–140

–300

Pin with pullup

V_DDIO= 3.3 V, V_IN= 0 V

enabled

Input current

(low level)

–230

I_IL

μA

Pin with pulldown

enabled

V_DDIO= 3.3 V, V_IN= 0 V

V_DDIO= 3.3 V, V_IN= V_DDIO

V_O= V_DDIOor 0 V

±2

80

Pin with pullup

enabled

Input current

(high level)

I_IH

μA

Pin with pulldown

enabled

28

50

Output current, pullup or

pulldown disabled

I_OZ

C_I

±2 μA

Input capacitance

2

2.78

35

pF

V

V_DDIOBOR trip point

V_DDIOBOR hysteresis

Falling V_DDIO

mV

Supervisor reset release delay

time

Time after BOR/POR/OVR event is removed to XRS

release

400

800 μs

VREG V_DDoutput

Internal VREG on

1.9

V

(1) When the on-chip VREG is used, its output is monitored by the POR/BOR circuit, which will reset the device should the core voltage

(V_DD) go out of range.

Device Operating Conditions

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4.4 Current Consumption

Table 4-1. TMS320F2805x Current Consumption at 60-MHz SYSCLKOUT

VREG ENABLED

VREG DISABLED

(1)

(2)

(1)

(2)

MODE

TEST CONDITIONS

I_DDIO

I_DDA

TYP⁽³⁾

I_DD

I_DDIO

I_DDA

TYP⁽³⁾

MAX

TYP⁽³⁾

MAX

TYP⁽³⁾

MAX

TYP⁽³⁾

MAX

The following peripheral clocks are

enabled:

•

ePWM1, ePWM2, ePWM3,

ePWM4, ePWM5, ePWM6,

ePWM7

•

eCAP1

eQEP1

eCAN-A

CLA

SCI-A, SCI-B, SCI-C

SPI-A

Operational

(Flash)

100 mA⁽⁶⁾

40 mA

90 mA⁽⁶⁾

17 mA

40 mA

ADC

I2C-A

COMPA1, COMPA3,

COMPB1, COMPA6,

COMPB4, COMPB5,

COMPB7

•

CPU-TIMER0,

CPU-TIMER1,

CPU-TIMER2

All PWM pins are toggled at 60 kHz.

All I/O pins are left unconnected.⁽⁴⁾⁽⁵⁾

Code is running out of flash with

2 wait-states.

XCLKOUT is turned off.

Flash is powered down.

IDLE

XCLKOUT is turned off.

All peripheral clocks are turned off.

13 mA

4 mA

15 μA

13 mA

4 mA

300 μA

150 μA

15 μA

Flash is powered down.

Peripheral clocks are off.

STANDBY

HALT

Flash is powered down.

Peripheral clocks are off.

Input clock is disabled.⁽⁷⁾

30 μA

15 μA

(1) I_DDIOcurrent is dependent on the electrical loading on the I/O pins.

(2) In order to realize the I_DDAcurrents shown for IDLE, STANDBY, and HALT, clock to the ADC module must be turned off explicitly by

writing to the PCLKCR0 register.

(3) The TYP numbers are applicable over room temperature and nominal voltage.

(4) The following is done in a loop:

•

Data is continuously transmitted out of SPI-A, SCI-A, SCI-B, SCI-C, eCAN-A, and I2C-A ports.

The hardware multiplier is exercised.

Watchdog is reset.

ADC is performing continuous conversion.

GPIO17 is toggled.

(5) CLA is continuously performing polynomial calculations.

(6) For F2805x devices that do not have CLA, subtract the I_DDcurrent number for CLA (see Table 4-2) from the I_DD(VREG disabled)/I_DDIO

(VREG enabled) current numbers shown in Table 4-1 for operational mode.

(7) If a quartz crystal or ceramic resonator is used as the clock source, the HALT mode shuts down the on-chip crystal oscillator.

NOTE

The peripheral-I/O multiplexing implemented in the device prevents all available peripherals

from being used at the same time because more than one peripheral function may share an

I/O pin. It is, however, possible to turn on the clocks to all the peripherals at the same time,

although such a configuration is not useful. If the clocks to all the peripherals are turned on

at the same time, the current drawn by the device will be more than the numbers specified in

the current consumption tables.

52

Device Operating Conditions

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4.4.1 Reducing Current Consumption

The 2805x devices incorporate a method to reduce the device current consumption. Since each peripheral

unit has an individual clock-enable bit, significant reduction in current consumption can be achieved by

turning off the clock to any peripheral module that is not used in a given application. Furthermore, any one

of the three low-power modes could be taken advantage of to reduce the current consumption even

further. Table 4-2 indicates the typical reduction in current consumption achieved by turning off the clocks.

Table 4-2. Typical Current Consumption by Various

Peripherals (at 60 MHz)⁽¹⁾

PERIPHERAL

MODULE⁽²⁾

I_DDCURRENT

REDUCTION (mA)

ADC

2⁽³⁾

I2C

3

ePWM

2

eCAP

2

eQEP

2

SCI

2

SPI

COMP/DAC

PGA

2

1

2

CPU-TIMER

Internal zero-pin oscillator

CAN

1

0.5

2.5

20

CLA

(1) All peripheral clocks (except CPU Timer clock) are disabled upon

reset. Writing to or reading from peripheral registers is possible only

after the peripheral clocks are turned on.

(2) For peripherals with multiple instances, the current quoted is per

module. For example, the 2 mA value quoted for ePWM is for one

ePWM module.

(3) This number represents the current drawn by the digital portion of

the ADC module. Turning off the clock to the ADC module results in

the elimination of the current drawn by the analog portion of the ADC

(I_DDA) as well.

NOTE

I_DDIOcurrent consumption is reduced by 15 mA (typical) when XCLKOUT is turned off.

NOTE

The baseline I_DDcurrent (current when the core is executing a dummy loop with no

peripherals enabled) is 40 mA, typical. To arrive at the I_DDcurrent for a given application, the

current-drawn by the peripherals (enabled by that application) must be added to the baseline

I_DDcurrent.

Following are other methods to reduce power consumption further:

•

The flash module may be powered down if code is run off SARAM. This method results in a current

reduction of 18 mA (typical) in the V_DDrail and 13 mA (typical) in the V_DDIOrail.

•

Savings in I_DDIOmay be realized by disabling the pullups on pins that assume an output function.

Device Operating Conditions

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4.4.2 Current Consumption Graphs (VREG Enabled)

Operational Current vs Frequency

140

120

100

80

60

40

20

0

10

20

30

40

50

60

70

SYSCLKOUT (MHz)

IDDIO IDDA

Figure 4-1. Typical Operational Current Versus Frequency (F2805x)

Operational Power vs Frequency

500

450

400

350

300

250

200

0

10

20

30

40

50

60

70

SYSCLKOUT (MHz)

Figure 4-2. Typical Operational Power Versus Frequency (F2805x)

54

Device Operating Conditions

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Typical CLA operational current vs SYSCLKOUT

25

20

15

10

5

0

10

15

20

25

30

35

40

45

50

55

60

SYSCLKOUT (MHz)

Figure 4-3. Typical CLA Operational Current Versus SYSCLKOUT

Device Operating Conditions

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4.5 Flash Timing

Table 4-3. Flash/OTP Endurance for T Temperature Material⁽¹⁾

ERASE/PROGRAM

TEMPERATURE

MIN

TYP

MAX

UNIT

N_f

Flash endurance for the array (write/erase cycles)

OTP endurance for the array (write cycles)

0°C to 105°C (ambient)

0°C to 30°C (ambient)

20000

50000

cycles

write

N_OTP

1

(1) Write/erase operations outside of the temperature ranges indicated are not specified and may affect the endurance numbers.

Table 4-4. Flash/OTP Endurance for S Temperature Material⁽¹⁾

ERASE/PROGRAM

MIN

TYP

MAX

UNIT

TEMPERATURE

0°C to 125°C (ambient)

0°C to 30°C (ambient)

N_f

Flash endurance for the array (write/erase cycles)

OTP endurance for the array (write cycles)

20000

50000

cycles

write

N_OTP

1

(1) Write/erase operations outside of the temperature ranges indicated are not specified and may affect the endurance numbers.

Table 4-5. Flash Parameters at 60-MHz SYSCLKOUT

TEST

CONDITIONS

PARAMETER

MIN

TYP

MAX

UNIT

Program Time 16-Bit Word

8K Sector

50

250

125

2

μs

ms

s

4K Sector

Erase Time⁽¹⁾8K Sector

4K Sector

2

s

(2)

I_DDP

V_DDcurrent consumption during Erase/Program cycle

V_DDIOcurrent consumption during Erase/Program cycle

VREG disabled

VREG enabled

80

mA

(2)

I_DDIOP

60

120

mA

(1) The on-chip flash memory is in an erased state when the device is shipped from TI. As such, erasing the flash memory is not required

prior to programming, when programming the device for the first time. However, the erase operation is needed on all subsequent

programming operations.

(2) Typical parameters as seen at room temperature including function call overhead, with all peripherals off.

Table 4-6. Flash/OTP Access Timing

PARAMETER

MIN

40

MAX UNIT

t_a(fp)

Paged Flash access time

Random Flash access time

OTP access time

ns

t_a(fr)

40

t_a(OTP)

60

Table 4-7. Flash Data Retention Duration

PARAMETER

TEST CONDITIONS

T_J= 55°C

MIN

15

MAX UNIT

t_retention

Data retention duration

years

56

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Table 4-8. Minimum Required Flash/OTP Wait-States at Different Frequencies

SYSCLKOUT

(ns)

PAGE

RANDOM

OTP

WAIT-STATE

(MHz)

WAIT-STATE⁽¹⁾

60

16.67

18.18

20

2

1

2

1

3

2

1

55

50

45

22.22

25

40

35

28.57

33.33

30

(1) Page and random wait-state must be ≥ 1.

The equations to compute the Flash page wait-state and random wait-state in Table 4-8 are as follows:

é

ê

ë

ù

æ

ç

è

ö

÷

ø

t_{a(f ·p)}

Flash Page Wait State =

-1 round up to the next highest integer

ú

t_c(SCO)

ê

ú

û

é

ê

ë

ù

æ

ç

è

ö

÷

ø

t_{a(f ×r)}

Flash Random Wait State =

-1 round up to the next highest integer, or 1, whichever is larger

ú

t_c(SCO)

ê

ú

û

The equation to compute the OTP wait-state in Table 4-8 is as follows:

é

ê

ë

ù

æ

ç

è

ö

÷

ø

t_a(OTP)

OTP Wait State =

-1 round up to the next highest integer, or 1, whichever is larger

ú

t_c(SCO)

ê

ú

û

Device Operating Conditions

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5 Power, Reset, Clocking, and Interrupts

5.1 Power Sequencing

There is no power sequencing requirement needed to ensure the device is in the proper state after reset

or to prevent the I/Os from glitching during power up or power down (GPIO19, GPIO34–38 do not have

glitch-free I/Os). No voltage larger than a diode drop (0.7 V) above V_DDIOshould be applied to any digital

pin (for analog pins, this value is 0.7 V above V_DDA) prior to powering up the device. Voltages applied to

pins on an unpowered device can bias internal p-n junctions in unintended ways and produce

unpredictable results.

V_DDIO, V_DDA

(3.3 V)

V_DD(1.8 V)

INTOSC1

t_INTOSCST

X1/X2

t_OSCST

(B)

(A)

XCLKOUT

User-code dependent

t

w(RSL1)

XRS^(D)

Address/data valid, internal boot-ROM code execution phase

Address/Data/

Control

(Internal)

User-code execution phase

User-code dependent

t

d(EX)

(C)

h(boot-mode)

t

Boot-Mode

Pins

GPIO pins as input

Peripheral/GPIO function

Boot-ROM execution starts

(E)

Based on boot code

GPIO pins as input (state depends on internal PU/PD)

I/O Pins

User-code dependent

A. Upon power up, SYSCLKOUT is OSCCLK/4. Since the XCLKOUTDIV bits in the XCLK register come up with a reset

state of 0, SYSCLKOUT is further divided by 4 before SYSCLKOUT appears at XCLKOUT. XCLKOUT = OSCCLK/16

during this phase.

B. Boot ROM configures the DIVSEL bits for /1 operation. XCLKOUT = OSCCLK/4 during this phase. Note that

XCLKOUT will not be visible at the pin until explicitly configured by user code.

C. After reset, the boot ROM code samples Boot Mode pins. Based on the status of the Boot Mode pin, the boot code

branches to destination memory or boot code function. If boot ROM code executes after power-on conditions (in

debugger environment), the boot code execution time is based on the current SYSCLKOUT speed. The SYSCLKOUT

will be based on user environment and could be with or without PLL enabled.

D. Using the XRS pin is optional due to the on-chip power-on reset (POR) circuitry.

E. The internal pullup or pulldown will take effect when BOR is driven high.

Figure 5-1. Power-on Reset

58

Power, Reset, Clocking, and Interrupts

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Table 5-1. Reset (XRS) Timing Requirements

MIN

1000t_c(SCO)

32t_c(OSCCLK)

MAX

UNIT

cycles

t_h(boot-mode)

t_w(RSL2)

Hold time for boot-mode pins

Pulse duration, XRS low on warm reset

Table 5-2. Reset (XRS) Switching Characteristics

over recommended operating conditions (unless otherwise noted)

PARAMETER

MIN

TYP

MAX

UNIT

μs

t_w(RSL1)

t_w(WDRS)

t_d(EX)

Pulse duration, XRS driven by device

600

Pulse duration, reset pulse generated by watchdog

Delay time, address/data valid after XRS high

Start up time, internal zero-pin oscillator

On-chip crystal-oscillator start-up time

512t_c(OSCCLK)

cycles

μs

32t_c(OSCCLK)

t_INTOSCST

3

(1)

t_OSCST

1

10

ms

(1) Dependent on crystal/resonator and board design.

INTOSC1

X1/X2

XCLKOUT

User-Code Dependent

t

w(RSL2)

XRS

User-Code Execution Phase

t

d(EX)

Address/Data/

User-Code Execution

Control

(Internal)

(A)

t

Boot-ROM Execution Starts

GPIO Pins as Input

h(boot-mode)

Boot-Mode

Pins

Peripheral/GPIO Function

User-Code Dependent

Peripheral/GPIO Function

User-Code Execution Starts

I/O Pins

GPIO Pins as Input (State Depends on Internal PU/PD)

User-Code Dependent

A. After reset, the Boot ROM code samples BOOT Mode pins. Based on the status of the Boot Mode pin, the boot code

branches to destination memory or boot code function. If Boot ROM code executes after power-on conditions (in

debugger environment), the Boot code execution time is based on the current SYSCLKOUT speed. The

SYSCLKOUT will be based on user environment and could be with or without PLL enabled.

Figure 5-2. Warm Reset

Power, Reset, Clocking, and Interrupts

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Figure 5-3 shows an example for the effect of writing into PLLCR register. In the first phase, PLLCR =

0x0004 and SYSCLKOUT = OSCCLK x 2. The PLLCR is then written with 0x0008. Right after the PLLCR

register is written, the PLL lock-up phase begins. During this phase, SYSCLKOUT = OSCCLK/2. After the

PLL lock-up is complete, SYSCLKOUT reflects the new operating frequency, OSCCLK x 4.

OSCCLK

Write to PLLCR

SYSCLKOUT

OSCCLK * 2

OSCCLK/2

OSCCLK * 4

(CPU frequency while PLL is stabilizing

with the desired frequency. This period

(PLL lock-up time t_p) is 1 ms long.)

(Current CPU

Frequency)

(Changed CPU frequency)

Figure 5-3. Example of Effect of Writing Into PLLCR Register

5.2 Clocking

5.2.1 Device Clock Table

This section provides the timing requirements and switching characteristics for the various clock options

available on the 2805x MCUs. Table 5-3 lists the cycle times of various clocks.

Table 5-3. 2805x Clock Table and Nomenclature (60-MHz Devices)

MIN

16.67

2

NOM

MAX UNIT

t_c(SCO), Cycle time

Frequency

500

60

ns

MHz

ns

SYSCLKOUT

LSPCLK⁽¹⁾

ADC clock

t_c(LCO), Cycle time

Frequency

16.67

66.67⁽²⁾

15⁽²⁾

60

MHz

ns

t_c(ADCCLK), Cycle time

Frequency

16.67

MHz

(1) Lower LSPCLK will reduce device power consumption.

(2) This value is the default reset value if SYSCLKOUT = 60 MHz.

Table 5-4. Device Clocking Requirements/Characteristics

MIN

NOM

MAX UNIT

t_c(OSC), Cycle time

Frequency

50

5

200

20

ns

MHz

ns

On-chip oscillator (X1/X2 pins)

(Crystal/Resonator)

t_c(CI), Cycle time (C8)

Frequency

33.3

5

200

30

External oscillator/clock source

(XCLKIN pin) — PLL Enabled

MHz

ns

t_c(CI), Cycle time (C8)

Frequency

33.33

4

250

30

External oscillator/clock source

(XCLKIN pin) — PLL Disabled

MHz

Limp mode SYSCLKOUT

(with /2 enabled)

Frequency range

1 to 5

MHz

t_c(XCO), Cycle time (C1)

66.67

0.5

2000

15

ns

MHz

ms

XCLKOUT

Frequency

t_p

PLL lock time⁽¹⁾

1

(1) The PLLLOCKPRD register must be updated based on the number of OSCCLK cycles. If the zero-pin internal oscillators (10 MHz) are

used as the clock source, then the PLLLOCKPRD register must be written with a value of 10,000 (minimum).

60

Power, Reset, Clocking, and Interrupts

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Table 5-5. Internal Zero-Pin Oscillator (INTOSC1, INTOSC2) Characteristics

PARAMETER

MIN

TYP

10.000

55

MAX UNIT

MHz

Internal zero-pin oscillator 1 (INTOSC1) at 30°C⁽¹⁾⁽²⁾

Internal zero-pin oscillator 2 (INTOSC2) at 30°C⁽¹⁾⁽²⁾

Step size (coarse trim)

Frequency

MHz

kHz

Step size (fine trim)

14

kHz

Temperature drift⁽³⁾

Voltage (V_DD) drift⁽³⁾

3.03

4.85 kHz/°C

Hz/mV

175

(1) In order to achieve better oscillator accuracy (10 MHz ± 1% or better) than shown, see the Oscillator Compensation Guide Application

Report (literature number SPRAB84). Refer to Figure 5-4 for TYP and MAX values.

(2) Frequency range ensured only when VREG is enabled, VREGENZ = V_SS

.

(3) Output frequency of the internal oscillators follows the direction of both the temperature gradient and voltage (V_DD) gradient. For

example:

•

Increase in temperature will cause the output frequency to increase per the temperature coefficient.

Decrease in voltage (V_DD) will cause the output frequency to decrease per the voltage coefficient.

Zero-Pin Oscillator Frequency Movement With Temperature

10.6

10.5

10.4

10.3

10.2

10.1

10

9.9

9.8

9.7

9.6

–40

–30

–20

–10

0

10

20

30

40

50

60

70

80

90

100

110

120

Typical

Max

Temperature (°C)

Figure 5-4. Zero-Pin Oscillator Frequency Movement With Temperature

Power, Reset, Clocking, and Interrupts

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5.2.2 Clock Requirements and Characteristics

Table 5-6. XCLKIN Timing Requirements - PLL Enabled

NO.

MIN

MAX UNIT

C9

t_f(CI)

Fall time, XCLKIN

6

ns

%

C10 t_r(CI)

Rise time, XCLKIN

C11 t_w(CIL)

C12 t_w(CIH)

Pulse duration, XCLKIN low as a percentage of t_c(OSCCLK)

Pulse duration, XCLKIN high as a percentage of t_c(OSCCLK)

45

55

Table 5-7. XCLKIN Timing Requirements - PLL Disabled

NO.

MIN

MAX UNIT

C9

t_f(CI)

Fall time, XCLKIN

Rise time, XCLKIN

Up to 20 MHz

6

2

ns

20 MHz to 30 MHz

Up to 20 MHz

C10 t_r(CI)

6

ns

20 MHz to 30 MHz

2

C11 t_w(CIL)

C12 t_w(CIH)

Pulse duration, XCLKIN low as a percentage of t_c(OSCCLK)

Pulse duration, XCLKIN high as a percentage of t_c(OSCCLK)

45

55

%

The possible configuration modes are shown in Table 2-22.

Table 5-8. XCLKOUT Switching Characteristics (PLL Bypassed or Enabled)^{(1) (2)}

over recommended operating conditions (unless otherwise noted)

NO.

C3

C4

C5

C6

PARAMETER

MIN

MAX

5

UNIT

ns

t_f(XCO)

Fall time, XCLKOUT

Rise time, XCLKOUT

t_r(XCO)

5

ns

t_w(XCOL)

t_w(XCOH)

Pulse duration, XCLKOUT low

Pulse duration, XCLKOUT high

H – 2

H + 2

ns

(1) A load of 40 pF is assumed for these parameters.

(2) H = 0.5t_c(XCO)

C10

C9

C8

(A)

XCLKIN

C6

C3

C1

C4

C5

(B)

XCLKOUT

A. The relationship of XCLKIN to XCLKOUT depends on the divide factor chosen. The waveform relationship shown is

intended to illustrate the timing parameters only and may differ based on actual configuration.

B. XCLKOUT configured to reflect SYSCLKOUT.

Figure 5-5. Clock Timing

62

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5.3 Interrupts

Figure 5-6 shows how the various interrupt sources are multiplexed.

Peripherals

(SPI, SCI, ePWM, I2C,

eCAP, ADC, eQEP, CLA, eCAN)

WDINT

Watchdog

Low Power Modes

WAKEINT

Sync

LPMINT

XINT1

SYSCLKOUT

XINT1

Interrupt Control

XINT1CR(15:0)

XINT2CTR(15:0)

GPIOXINT1SEL(4:0)

XINT2SOC

ADC

INT1

to

INT12

XINT2

Interrupt Control

XINT2CR(15:0)

XINT3CTR(15:0)

C28

Core

GPIOXINT2SEL(4:0)

GPIO0.int

XINT3

TINT0

XINT3

GPIO

MUX

Interrupt Control

XINT3CR(15:0)

XINT3CTR(15:0)

GPIO31.int

GPIOXINT3SEL(4:0)

CPU TIMER 0

CPU TIMER 1

CPU TIMER 2

TINT1

TINT2

INT13

INT14

CPUTMR2CLK

CLOCKFAIL

NMIRS

System Control

(See the System

Control section.)

NMI interrupt with watchdog function

(See the NMI Watchdog section.)

NMI

Figure 5-6. External and PIE Interrupt Sources

Power, Reset, Clocking, and Interrupts

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Eight PIE block interrupts are grouped into one CPU interrupt. In total, 12 CPU interrupt groups, with

8 interrupts per group equals 96 possible interrupts. Table 5-9 shows the interrupts used by 2805x

devices.

The TRAP #VectorNumber instruction transfers program control to the interrupt service routine

corresponding to the vector specified. TRAP #0 attempts to transfer program control to the address

pointed to by the reset vector. The PIE vector table does not, however, include a reset vector. Therefore,

TRAP #0 should not be used when the PIE is enabled. Doing so will result in undefined behavior.

When the PIE is enabled, TRAP #1 through TRAP #12 will transfer program control to the interrupt service

routine corresponding to the first vector within the PIE group. For example: TRAP #1 fetches the vector

from INT1.1, TRAP #2 fetches the vector from INT2.1, and so forth.

IFR[12:1]

IER[12:1]

INTM

INT1

INT2

1

CPU

MUX

0

INT11

INT12

Global

Enable

(Flag)

(Enable)

INTx.1

INTx.2

INTx.3

INTx.4

INTx.5

From

Peripherals

or

External

Interrupts

INTx

MUX

INTx.6

INTx.7

INTx.8

PIEACKx

(Enable)

(Flag)

(Enable/Flag)

PIEIERx[8:1]

PIEIFRx[8:1]

Figure 5-7. Multiplexing of Interrupts Using the PIE Block

64

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Table 5-9. PIE MUXed Peripheral Interrupt Vector Table⁽¹⁾

INTx.8

WAKEINT

(LPM/WD)

0xD4E

Reserved

–

INTx.7

TINT0

INTx.6

ADCINT9

(ADC)

INTx.5

XINT2

INTx.4

XINT1

INTx.3

Reserved

–

INTx.2

ADCINT2

(ADC)

INTx.1

ADCINT1

(ADC)

INT1.y

INT2.y

INT3.y

INT4.y

INT5.y

INT6.y

INT7.y

INT8.y

INT9.y

INT10.y

(TIMER 0)

0xD4C

EPWM7_TZINT

(ePWM7)

0xD5C

EPWM7_INT

(ePWM7)

0xD6C

Reserved

–

Ext. int. 2

0xD48

Ext. int. 1

0xD46

0xD4A

0xD44

0xD42

0xD40

EPWM6_TZINT

(ePWM6)

0xD5A

EPWM5_TZINT

(ePWM5)

0xD58

EPWM4_TZINT

(ePWM4)

0xD56

EPWM3_TZINT

(ePWM3)

0xD54

EPWM2_TZINT

(ePWM2)

0xD52

EPWM1_TZINT

(ePWM1)

0xD50

0xD5E

Reserved

–

EPWM6_INT

(ePWM6)

0xD6A

EPWM5_INT

(ePWM5)

0xD68

EPWM4_INT

(ePWM4)

0xD66

EPWM3_INT

(ePWM3)

0xD64

EPWM2_INT

(ePWM2)

0xD62

EPWM1_INT

(ePWM1)

0xD60

0xD6E

Reserved

–

Reserved

–

Reserved

–

Reserved

–

Reserved

–

Reserved

–

ECAP1_INT

(eCAP1)

0xD70

0xD7E

Reserved

–

0xD7C

Reserved

–

0xD7A

0xD78

0xD76

0xD74

0xD72

Reserved

–

Reserved

–

Reserved

–

Reserved

–

Reserved

–

EQEP1_INT

(eQEP1)

0xD80

0xD8E

Reserved

–

0xD8C

Reserved

–

0xD8A

0xD88

0xD86

0xD84

0xD82

Reserved

–

Reserved

–

Reserved

–

Reserved

–

SPITXINTA

(SPI-A)

0xD92

SPIRXINTA

(SPI-A)

0xD9E

Reserved

–

0xD9C

Reserved

–

0xD9A

0xD98

0xD96

0xD94

0xD90

Reserved

–

Reserved

–

Reserved

–

Reserved

–

Reserved

–

Reserved

–

0xDAE

Reserved

–

0xDAC

Reserved

–

0xDAA

0xDA8

0xDA6

0xDA4

Reserved

–

0xDA2

0xDA0

SCITXINTC

(SCI-C)

0xDBA

SCIRXINTC

(SCI-C)

0xDB8

Reserved

–

I2CINT2A

(I2C-A)

0xDB2

I2CINT1A

(I2C-A)

0xDBE

Reserved

–

0xDBC

Reserved

–

0xDB6

0xDB4

SCIRXINTB

(SCI-B)

0xDC4

ADCINT3

(ADC)

0xDB0

ECAN1_INTA

(CAN-A)

0xDCA

ECAN0_INTA

(CAN-A)

0xDC8

SCITXINTB

(SCI-B)

0xDC6

ADCINT4

(ADC)

SCITXINTA

(SCI-A)

0xDC2

SCIRXINTA

(SCI-A)

0xDCE

ADCINT8

(ADC)

(ePWM16)

0xDDE

CLA1_INT8

(CLA)

0xDCC

ADCINT7

(ADC)

0xDC0

ADCINT6

(ADC)

ADCINT5

(ADC)

ADCINT2

(ADC)

ADCINT1

(ADC)

(ePWM15)

0xDDC

CLA1_INT7

(CLA)

(ePWM14)

0xDDA

(ePWM13)

0xDD8

(ePWM12)

0xDD6

CLA1_INT4

(CLA)

(ePWM11)

0xDD4

CLA1_INT3

(CLA)

(ePWM10)

0xDD2

(ePWM9)

0xDD0

INT11.y

INT12.y

CLA1_INT6

(CLA)

CLA1_INT5

(CLA)

CLA1_INT2

(CLA)

CLA1_INT1

(CLA)

(ePWM16)

0xDEE

LUF

(ePWM15)

0xDEC

LVF

(ePWM14)

0xDEA

(ePWM13)

0xDE8

(ePWM12)

0xDE6

(ePWM11)

0xDE4

Reserved

–

(ePWM10)

0xDE2

(ePWM9)

0xDE0

Reserved

–

Reserved

–

Reserved

–

Reserved

–

XINT3

(CLA)

Ext. Int. 3

0xDF0

0xDFE

0xDFC

0xDFA

0xDF8

0xDF6

0xDF4

0xDF2

(1) Out of 96 possible interrupts, some interrupts are not used. These interrupts are reserved for future devices. These interrupts can be

used as software interrupts if they are enabled at the PIEIFRx level, provided none of the interrupts within the group is being used by a

peripheral. Otherwise, interrupts coming in from peripherals may be lost by accidentally clearing their flag while modifying the PIEIFR.

To summarize, there are two safe cases when the reserved interrupts could be used as software interrupts:

•

No peripheral within the group is asserting interrupts.

No peripheral interrupts are assigned to the group (for example, PIE group 7).

Power, Reset, Clocking, and Interrupts

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Table 5-10. PIE Configuration and Control Registers

NAME

PIECTRL

PIEACK

PIEIER1

PIEIFR1

PIEIER2

PIEIFR2

PIEIER3

PIEIFR3

PIEIER4

PIEIFR4

PIEIER5

PIEIFR5

PIEIER6

PIEIFR6

PIEIER7

PIEIFR7

PIEIER8

PIEIFR8

PIEIER9

PIEIFR9

PIEIER10

PIEIFR10

PIEIER11

PIEIFR11

PIEIER12

PIEIFR12

Reserved

ADDRESS

0x0CE0

0x0CE1

0x0CE2

0x0CE3

0x0CE4

0x0CE5

0x0CE6

0x0CE7

0x0CE8

0x0CE9

0x0CEA

0x0CEB

0x0CEC

0x0CED

0x0CEE

0x0CEF

0x0CF0

0x0CF1

0x0CF2

0x0CF3

0x0CF4

0x0CF5

0x0CF6

0x0CF7

0x0CF8

0x0CF9

SIZE (x16)

DESCRIPTION⁽¹⁾

PIE, Control Register

1

6

PIE, Acknowledge Register

PIE, INT1 Group Enable Register

PIE, INT1 Group Flag Register

PIE, INT2 Group Enable Register

PIE, INT2 Group Flag Register

PIE, INT3 Group Enable Register

PIE, INT3 Group Flag Register

PIE, INT4 Group Enable Register

PIE, INT4 Group Flag Register

PIE, INT5 Group Enable Register

PIE, INT5 Group Flag Register

PIE, INT6 Group Enable Register

PIE, INT6 Group Flag Register

PIE, INT7 Group Enable Register

PIE, INT7 Group Flag Register

PIE, INT8 Group Enable Register

PIE, INT8 Group Flag Register

PIE, INT9 Group Enable Register

PIE, INT9 Group Flag Register

PIE, INT10 Group Enable Register

PIE, INT10 Group Flag Register

PIE, INT11 Group Enable Register

PIE, INT11 Group Flag Register

PIE, INT12 Group Enable Register

PIE, INT12 Group Flag Register

Reserved

0x0CFA –

0x0CFF

(1) The PIE configuration and control registers are not protected by EALLOW mode. The PIE vector table

is protected.

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5.3.1 External Interrupts

Table 5-11. External Interrupt Registers

NAME

XINT1CR

XINT2CR

XINT3CR

XINT1CTR

XINT2CTR

XINT3CTR

ADDRESS

0x00 7070

0x00 7071

0x00 7072

0x00 7078

0x00 7079

0x00 707A

SIZE (x16)

DESCRIPTION

XINT1 configuration register

XINT2 configuration register

XINT3 configuration register

XINT1 counter register

1

XINT2 counter register

XINT3 counter register

Each external interrupt can be enabled, disabled, or qualified using positive, negative, or both positive and

negative edge. For more information, see the System Control and Interrupts chapter of the

TMS320x2805x Piccolo Technical Reference Manual (literature number SPRUHE5).

5.3.1.1 External Interrupt Electrical Data/Timing

Table 5-12. External Interrupt Timing Requirements⁽¹⁾

TEST CONDITIONS

Synchronous

MIN

1t_c(SCO)

MAX

UNIT

cycles

(2)

t_w(INT)

Pulse duration, INT input low/high

With qualifier

1t_c(SCO)+ t_w(IQSW)

(1) For an explanation of the input qualifier parameters, see Table 6-45.

(2) This timing is applicable to any GPIO pin configured for ADCSOC functionality.

Table 5-13. External Interrupt Switching Characteristics⁽¹⁾

over recommended operating conditions (unless otherwise noted)

PARAMETER

MIN

MAX

t_w(IQSW)+ 12t_c(SCO)

UNIT

t_d(INT)

Delay time, INT low/high to interrupt-vector fetch

cycles

(1) For an explanation of the input qualifier parameters, see Table 6-45.

t

w(INT)

XINT1, XINT2, XINT3

t

d(INT)

Address bus

(internal)

Interrupt Vector

Figure 5-8. External Interrupt Timing

Power, Reset, Clocking, and Interrupts

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6 Peripheral Information and Timings

6.1 Parameter Information

6.1.1 Timing Parameter Symbology

Timing parameter symbols used are created in accordance with JEDEC Standard 100. To shorten the

symbols, some of the pin names and other related terminology have been abbreviated as follows:

Lowercase subscripts and their

meanings:

Letters and symbols and their

meanings:

a

c

d

access time

H

L

High

Low

cycle time (period)

delay time

V

Valid

Unknown, changing, or don't care

level

f

fall time

X

Z

h

r

hold time

High impedance

rise time

su

t

setup time

transition time

valid time

v

w

pulse duration (width)

6.1.1.1 General Notes on Timing Parameters

All output signals from the 28x devices (including XCLKOUT) are derived from an internal clock such that

all output transitions for a given half-cycle occur with a minimum of skewing relative to each other.

The signal combinations shown in the following timing diagrams may not necessarily represent actual

cycles. For actual cycle examples, see the appropriate cycle description section of this document.

6.1.2 Test Load Circuit

This test load circuit is used to measure all switching characteristics provided in this document.

Tester Pin Electronics

Data Sheet Timing Reference Point

W

3.5 nH

Output

Under

Test

42

Transmission Line

(A)

Z0 = 50 W

Device Pin^(B)

4.0 pF

1.85 pF

A. Input requirements in this data sheet are tested with an input slew rate of < 4 Volts per nanosecond (4 V/ns) at the

device pin.

B. The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its

transmission line effects must be taken into account. A transmission line with a delay of 2 ns or longer can be used to

produce the desired transmission line effect. The transmission line is intended as a load only. It is not necessary to

add or subtract the transmission line delay (2 ns or longer) from the data sheet timing.

Figure 6-1. 3.3-V Test Load Circuit

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6.2 Control Law Accelerator (CLA)

6.2.1 Control Law Accelerator Device-Specific Information

The control law accelerator extends the capabilities of the C28x CPU by adding parallel processing. Time-

critical control loops serviced by the CLA can achieve low ADC sample to output delay. Thus, the CLA

enables faster system response and higher frequency control loops. Utilizing the CLA for time-critical tasks

frees up the main CPU to perform other system and communication functions concurently. The following is

a list of major features of the CLA.

•

Clocked at the same rate as the main CPU (SYSCLKOUT).

An independent architecture allowing CLA algorithm execution independent of the main C28x CPU.

–

Complete bus architecture:

•

Program address bus and program data bus

Data address bus, data read bus, and data write bus

–

Independent eight-stage pipeline.

12-bit program counter (MPC)

Four 32-bit result registers (MR0–MR3)

Two 16-bit auxillary registers (MAR0, MAR1)

Status register (MSTF)

•

Instruction set includes:

–

IEEE single-precision (32-bit) floating-point math operations

Floating-point math with parallel load or store

Floating-point multiply with parallel add or subtract

1/X and 1/sqrt(X) estimations

Data type conversions.

Conditional branch and call

Data load and store operations

•

The CLA program code can consist of up to eight tasks or interrupt service routines.

–

The start address of each task is specified by the MVECT registers.

No limit on task size as long as the tasks fit within the CLA program memory space.

One task is serviced at a time through to completion. There is no nesting of tasks.

Upon task completion, a task-specific interrupt is flagged within the PIE.

When a task finishes, the next highest-priority pending task is automatically started.

Task trigger mechanisms:

–

C28x CPU via the IACK instruction

Task1 to Task7: the corresponding ADC, ePWM, eQEP, or eCAP module interrupt. For example:

•

Task1: ADCINT1 or EPWM1_INT

Task2: ADCINT2 or EPWM2_INT

Task4: ADCINT4 or EPWM4_INT or EQEPx_INT or ECAPx_INT

Task7: ADCINT7 or EPWM7_INT or EQEPx_INT or ECAPx_INT

–

Task8: ADCINT8 or by CPU Timer 0 or EQEPx_INT or ECAPx_INT

•

Memory and Shared Peripherals:

–

Two dedicated message RAMs for communication between the CLA and the main CPU.

The C28x CPU can map CLA program and data memory to the main CPU space or CLA space.

The CLA has direct access to the CLA Data ROM that stores the math tables required by the

routines in the CLA Math Library.

–

The CLA has direct access to the ADC Result registers, comparator and DAC registers, eCAP,

eQEP, and ePWM registers.

Peripheral Information and Timings

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Peripheral Interrupts

IACK

CLA Control

Registers

ADCINT1 to ADCINT8

EPWM1_INT to EPWM7_INT

ECAP1_INT

CLA_INT1 to CLA_INT8

MIFR

MIOVF

MICLR

MICLROVF

MIFRC

MIER

Main

28x

CPU

INT11

INT12

MPERINT1

to

MPERINT8

PIE

EQEP1_INT

LVF

LUF

CPU Timer 0

MIRUN

Main CPU Read/Write Data Bus

MPISRCSEL1

MVECT1

MVECT2

MVECT3

MVECT4

MVECT5

MVECT6

MVECT7

MVECT8

CLA Program Address Bus

CLA Program Data Bus

CLA

Program

Memory

CLA

Data

Memory

Map to CLA or

CPU Space

Map to CLA or

CPU Space

MMEMCFG

MCTL

SYSCLKOUT

CLAENCLK

SYSRS

CLA

Data

ROM

CLA

Shared

Message

RAMs

MEALLOW

CLA Execution

Registers

CLA Data Read Address Bus

ADC

Result

Registers

MPC(12)

MSTF(32)

MR0(32)

MR1(32)

MR2(32)

MR3(32)

CLA Data Read Data Bus

CLA Data Write Address Bus

CLA Data Write Data Bus

Main CPU Read Data Bus

eCAP

Registers

MAR0(32)

MAR1(32)

eQEP

Registers

ePWM

Registers

Comparator

+ DAC

Registers

Figure 6-2. CLA Block Diagram

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6.2.2 Control Law Accelerator Register Descriptions

Table 6-1. CLA Control Registers

CLA1

ADDRESS

EALLOW

PROTECTED

REGISTER NAME

SIZE (x16)

DESCRIPTION⁽¹⁾

MVECT1

MVECT2

MVECT3

MVECT4

MVECT5

MVECT6

MVECT7

MVECT8

MCTL

0x1400

0x1401

0x1402

0x1403

0x1404

0x1405

0x1406

0x1407

0x1410

0x1411

0x1414

0x1420

0x1421

0x1422

0x1423

0x1424

0x1425

0x1426

0x1428

0x142A

0x142B

0x142E

0x1430

0x1434

0x1438

0x143C

1

2

1

2

Yes

–

CLA Interrupt/Task 1 Start Address

CLA Interrupt/Task 2 Start Address

CLA Interrupt/Task 3 Start Address

CLA Interrupt/Task 4 Start Address

CLA Interrupt/Task 5 Start Address

CLA Interrupt/Task 6 Start Address

CLA Interrupt/Task 7 Start Address

CLA Interrupt/Task 8 Start Address

CLA Control Register

MMEMCFG

MPISRCSEL1

MIFR

CLA Memory Configure Register

Peripheral Interrupt Source Select Register 1

Interrupt Flag Register

MIOVF

Interrupt Overflow Register

Interrupt Force Register

MIFRC

MICLR

Interrupt Clear Register

MICLROVF

MIER

Interrupt Overflow Clear Register

Interrupt Enable Register

Interrupt RUN Register

MIRUN

MPC⁽²⁾

MAR0⁽²⁾

MAR1⁽²⁾

MSTF⁽²⁾

MR0⁽²⁾

MR1⁽²⁾

MR2⁽²⁾

MR3⁽²⁾

CLA Program Counter

–

CLA Aux Register 0

–

CLA Aux Register 1

–

CLA STF Register

–

CLA R0H Register

–

CLA R1H Register

–

CLA R2H Register

–

CLA R3H Register

(1) All registers in this table are DCSM protected

(2) The main C28x CPU has read only access to this register for debug purposes. The main CPU cannot perform CPU or debugger writes

to this register.

Table 6-2. CLA Message RAM

ADDRESS RANGE

0x1480 – 0x14FF

0x1500 – 0x157F

SIZE (x16)

128

DESCRIPTION

CLA to CPU Message RAM

CPU to CLA Message RAM

128

Peripheral Information and Timings

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6.3 Analog Block

6.3.1 Analog-to-Digital Converter (ADC)

6.3.1.1 Analog-to-Digital Converter Device-Specific Information

The core of the ADC contains a single 12-bit converter fed by two sample-and-hold circuits. The sample-

and-hold circuits can be sampled simultaneously or sequentially. These, in turn, are fed by a total of up to

16 analog input channels. The converter can be configured to run with an internal bandgap reference to

create true-voltage based conversions or with a pair of external voltage references (V_REFHI/V_REFLO) to

create ratiometric-based conversions.

Contrary to previous ADC types, this ADC is not sequencer-based. The user can easily create a series of

conversions from a single trigger. However, the basic principle of operation is centered around the

configurations of individual conversions, called SOCs, or Start-Of-Conversions.

Functions of the ADC module include:

•

12-bit ADC core with built-in dual sample-and-hold (S/H)

Simultaneous sampling or sequential sampling modes

Full range analog input: 0 V to 3.3 V fixed, or V_REFHI/V_REFLOratiometric. The digital value of the input

analog voltage is derived by:

–

Internal Reference (V_REFLO= V_SSA. V_REFHImust not exceed V_DDAwhen using either internal or

external reference modes.)

Digital Value = 0,

when input £ 0 V

Input Analog Voltage -

V_REFLO

Digital Value = 4096 ´

when 0 V < input < 3.3 V

3.3

Digital Value = 4095,

when input ³ 3.3 V

–

External Reference (V_REFHI/V_REFLOconnected to external references. V_REFHImust not exceed V_DDA

when using either internal or external reference modes.)

Digital Value = 0,

when input £ 0 V

Input Analog Voltage -

V_REFLO

Digital Value = 4096 ´

when 0 V < input <

V_REFHI

-

V_REFHIV_REFLO

Digital Value = 4095,

when input ³

V_REFHI

•

Runs at full system clock, no prescaling required

Up to 16-channel, multiplexed inputs

16 SOCs, configurable for trigger, sample window, and channel

16 result registers (individually addressable) to store conversion values

Multiple trigger sources

–

S/W – software immediate start

ePWM 1–7

GPIO XINT2

CPU Timer 0, CPU Timer 1, CPU Timer 2

ADCINT1, ADCINT2

•

9 flexible PIE interrupts, can configure interrupt request after any conversion

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Table 6-3. ADC Configuration and Control Registers

SIZE

(x16)

EALLOW

PROTECTED

REGISTER NAME

ADDRESS

DESCRIPTION

ADCCTL1

0x7100

0x7101

0x7104

0x7105

0x7106

0x7107

0x7108

0x7109

0x710A

0x710B

0x710C

0x7110

0x7112

0x7114

0x7115

0x7118

0x711A

0x711C

0x711E

1

Yes

No

Control 1 Register

ADCCTL2

Control 2 Register

ADCINTFLG

Interrupt Flag Register

ADCINTFLGCLR

ADCINTOVF

No

Interrupt Flag Clear Register

No

Interrupt Overflow Register

ADCINTOVFCLR

INTSEL1N2

No

Interrupt Overflow Clear Register

Yes

No

Interrupt 1 and 2 Selection Register

Interrupt 3 and 4 Selection Register

Interrupt 5 and 6 Selection Register

Interrupt 7 and 8 Selection Register

Interrupt 9 Selection Register (reserved Interrupt 10 Selection)

SOC Priority Control Register

INTSEL3N4

INTSEL5N6

INTSEL7N8

INTSEL9N10

SOCPRICTL

ADCSAMPLEMODE

ADCINTSOCSEL1

ADCINTSOCSEL2

ADCSOCFLG1

ADCSOCFRC1

ADCSOCOVF1

ADCSOCOVFCLR1

Sampling Mode Register

Interrupt SOC Selection 1 Register (for 8 channels)

Interrupt SOC Selection 2 Register (for 8 channels)

SOC Flag 1 Register (for 16 channels)

SOC Force 1 Register (for 16 channels)

SOC Overflow 1 Register (for 16 channels)

SOC Overflow Clear 1 Register (for 16 channels)

SOC0 Control Register to SOC15 Control Register

No

ADCSOC0CTL to

ADCSOC15CTL

0x7120 –

0x712F

Yes

ADCREFTRIM

ADCOFFTRIM

COMPHYSTCTL

ADCREV

0x7140

0x7141

0x714C

0x714F

1

Yes

No

Reference Trim Register

Offset Trim Register

Comparator Hysteresis Control Register

Revision Register

Table 6-4. ADC Result Registers (Mapped to PF0)

SIZE

(x16)

EALLOW

PROTECTED

REGISTER NAME

ADDRESS

DESCRIPTION

ADCRESULT0 to

ADCRESULT15

0xB00 –

0xB0F

1

No

ADC Result 0 Register to ADC Result 15 Register

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0-Wait

Result

Registers

PF0 (CPU)

PF2 (CPU)

SYSCLKOUT

ADCENCLK

ADCINT 1

ADCINT 9

PIE

TINT 0

TINT 1

TINT 2

CPUTIMER 0

CPUTIMER 1

CPUTIMER 2

ADCTRIG 1

ADCTRIG 2

ADCTRIG 3

ADC

Core

12-Bit

ADC

Channels

XINT 2SOC

XINT 2

EPWM 1

EPWM 2

EPWM 3

EPWM 4

EPWM 5

EPWM 6

EPWM 7

ADCTRIG 4

SOCA 1

SOCB 1

SOCA 2

SOCB 2

SOCA 3

SOCB 3

SOCA 4

SOCB 4

SOCA 5

SOCB 5

SOCA 6

SOCB 6

SOCA 7

SOCB 7

ADCTRIG 5

ADCTRIG 6

ADCTRIG 7

ADCTRIG 8

ADCTRIG 9

ADCTRIG 10

ADCTRIG 11

ADCTRIG 12

ADCTRIG 13

ADCTRIG 14

ADCTRIG 15

ADCTRIG 16

ADCTRIG 17

ADCTRIG 18

Figure 6-3. ADC Connections

ADC Connections if the ADC is Not Used

TI recommends that the connections for the analog power pins be kept, even if the ADC is not used.

Following is a summary of how the ADC pins should be connected, if the ADC is not used in an

application:

•

V_DDA– Connect to V_DDIO

V_SSA– Connect to V_SS

V_REFLO– Connect to V_SS

ADCINAn, ADCINBn, V_REFHI– Connect to V_SSA

When the ADC module is used in an application, unused ADC input pins should be connected to analog

ground (V_SSA).

When the ADC is not used, be sure that the clock to the ADC module is not turned on to realize power

savings.

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6.3.1.2 Analog-to-Digital Converter Electrical Data/Timing

Table 6-5. ADC Electrical Characteristics

PARAMETER

MIN

TYP

MAX

UNIT

DC SPECIFICATIONS

Resolution

12

0.5

10

Bits

ADC clock

60

63

MHz

Sample Window (see Table 6-6)

28055, 28054, 28053,

28052

ADC

Clocks

28051, 28050

24

63

ACCURACY

INL (Integral nonlinearity)⁽¹⁾

–4

–1

4

1.5

20

LSB

DNL (Differential nonlinearity), no missing codes

(2)

Offset error

Executing a single self-

recalibration⁽³⁾

–20

0

Executing periodic self-

recalibration⁽⁴⁾

–4

4

Overall gain error with internal reference

Overall gain error with external reference

Channel-to-channel offset variation

Channel-to-channel gain variation

ADC temperature coefficient with internal reference

ADC temperature coefficient with external reference

V_REFLO

–60

–40

–4

60

40

4

LSB

–4

4

LSB

–50

–20

ppm/°C

µA

–100

100

V_REFHI

µA

ANALOG INPUT

Analog input voltage with internal reference

Analog input voltage with external reference

V_REFLOinput voltage

0

V_REFLO

V_SSA

3.3

V_REFHI

0.66

V

V_REFHIinput voltage⁽⁵⁾

2.64

V_DDA

with V_REFLO= V_SSA

1.98

Input capacitance

5

pF

Input leakage current

±2

μA

(1) INL will degrade when the ADC input voltage goes above V_DDA

.

(2) 1 LSB has the weighted value of full-scale range (FSR)/4096. FSR is 3.3 V with internal reference and V_REFHI- V_REFLOfor external

reference.

(3) For more details, see the TMS320F28055, TMS320F28054, TMS320F28053, TMS320F28052, TMS320F28051, TMS320F28050

Piccolo MCU Silicon Errata (literature number SPRZ362).

(4) Periodic self-recalibration will remove system-level and temperature dependencies on the ADC zero offset error. This can be performed

as needed in the application without sacrificing an ADC channel by using the procedure listed in the "ADC Zero Offset Calibration"

section in the Analog-to-Digital Converter and Comparator chapter of the TMS320x2805x Piccolo Technical Reference Manual (literature

number SPRUHE5).

(5) V_REFHImust not exceed V_DDAwhen using either internal or external reference modes.

Table 6-6. ACQPS Values⁽¹⁾

OVERLAP MODE

{9, 10, 23, 36, 49, 62}

{23, 36, 49, 62}

NONOVERLAP MODE

{15, 16, 28, 29, 41, 42, 54, 55}

Non-PGA

PGA

(1) ACQPS = 6 can be used for the first sample if it is thrown away.

Peripheral Information and Timings

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Table 6-7. ADC Power Modes

ADC OPERATING MODE

Mode A – Operating Mode

CONDITIONS

I_DDA

UNITS

ADC Clock Enabled

13

mA

Bandgap On (ADCBGPWD = 1)

Reference On (ADCREFPWD = 1)

ADC Powered Up (ADCPWDN = 1)

Mode B – Quick Wake Mode

Mode C – Comparator-Only Mode

Mode D – Off Mode

ADC Clock Enabled

4

mA

Bandgap On (ADCBGPWD = 1)

Reference On (ADCREFPWD = 1)

ADC Powered Up (ADCPWDN = 0)

ADC Clock Enabled

1.5

Bandgap On (ADCBGPWD = 1)

Reference On (ADCREFPWD = 0)

ADC Powered Up (ADCPWDN = 0)

ADC Clock Enabled

0.075

Bandgap On (ADCBGPWD = 0)

Reference On (ADCREFPWD = 0)

ADC Powered Up (ADCPWDN = 0)

6.3.1.2.1 External ADC Start-of-Conversion Electrical Data/Timing

Table 6-8. External ADC Start-of-Conversion Switching Characteristics

over recommended operating conditions (unless otherwise noted)

PARAMETER

MIN

MAX

UNIT

t_w(ADCSOCL)

Pulse duration, ADCSOCxO low

32t_{c(HCO )}

cycles

t_w(ADCSOCL)

ADCSOCAO

or

ADCSOCBO

Figure 6-4. ADCSOCAO or ADCSOCBO Timing

6.3.1.2.2 Internal Temperature Sensor

Table 6-9. Temperature Sensor Coefficient⁽¹⁾

PARAMETER⁽²⁾

MIN

TYP

MAX

UNIT

T_SLOPE

Degrees C of temperature movement per measured ADC LSB change

of the temperature sensor

0.18⁽³⁾⁽⁴⁾

°C/LSB

T_OFFSET

ADC output at 0°C of the temperature sensor

1750

LSB

(1) The accuracy of the temperature sensor for sensing absolute temperature (temperature in degrees) is not specified. The primary use of

the temperature sensor should be to compensate the internal oscillator for temperature drift (this operation is assured as per Table 5-5).

(2) The temperature sensor slope and offset are given in terms of ADC LSBs using the internal reference of the ADC. Values must be

adjusted accordingly in external reference mode to the external reference voltage.

(3) ADC temperature coeffieicient is accounted for in this specification

(4) Output of the temperature sensor (in terms of LSBs) is sign-consistent with the direction of the temperature movement. Increasing

temperatures will give increasing ADC values relative to an initial value; decreasing temperatures will give decreasing ADC values

relative to an initial value.

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6.3.1.2.3 ADC Power-Up Control Bit Timing

Table 6-10. ADC Power-Up Delays

PARAMETER⁽¹⁾

MIN

MAX

UNIT

t_d(PWD)

Delay time for the ADC to be stable after power up

1

ms

(1) Timings maintain compatibility to the ADC module. The 2805x ADC supports driving all 3 bits at the same time t_d(PWD)ms before first

conversion.

ADCPWDN/

ADCBGPWD/

ADCREFPWD/

ADCENABLE

t_d(PWD)

Request for ADC

Conversion

Figure 6-5. ADC Conversion Timing

R_on

3.4 kW

Switch

R_s

ADCIN

C_p

C_h

Source

Signal

ac

5 pF

1.6 pF

28x DSP

Typical Values of the Input Circuit Components:

Switch Resistance (R_on): 3.4 kW

Sampling Capacitor (C_h): 1.6 pF

Parasitic Capacitance (C_p): 5 pF

Source Resistance (R_s): 50 W

Figure 6-6. ADC Input Impedance Model

Peripheral Information and Timings

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6.3.1.2.4 ADC Sequential and Simultaneous Timings

Analog Input

SOC0 Sample

Window

SOC1 Sample

Window

SOC2 Sample

Window

0

2

9

15

22 24

37

ADCCLK

ADCCTL 1.INTPULSEPOS

ADCSOCFLG 1.SOC0

ADCSOCFLG 1.SOC1

ADCSOCFLG 1.SOC2

S/H Window Pulse to Core

ADCRESULT 0

SOC0

SOC1

SOC2

Result 0 Latched

2 ADCCLKs

ADCRESULT 1

EOC0 Pulse

EOC1 Pulse

ADCINTFLG.ADCINTx

Minimum

7 ADCCLKs

Conversion 0

13 ADC Clocks

1 ADCCLK

6

Minimum

ADCCLKs 7 ADCCLKs

Conversion 1

13 ADC Clocks

A. This diagram uses ACQPS = 6 timings. These particular timings are not valid on this device (except for a throw-away

sample to meet the first sample issue in the device errata), but they correctly demonstrate the operation of the

converter.

Figure 6-7. Timing Example for Sequential Mode / Late Interrupt Pulse

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Analog Input

SOC0 Sample

Window

SOC1 Sample

Window

SOC2 Sample

Window

0

2

9

15

22 24

37

ADCCLK

ADCCTL1.INTPULSEPOS

ADCSOCFLG 1.SOC0

ADCSOCFLG 1.SOC1

ADCSOCFLG 1.SOC2

S/H Window Pulse to Core

ADCRESULT 0

SOC0

SOC1

SOC2

Result 0 Latched

ADCRESULT 1

EOC0 Pulse

EOC1 Pulse

EOC2 Pulse

ADCINTFLG.ADCINTx

Minimum

7 ADCCLKs

Conversion 0

13 ADC Clocks

2 ADCCLKs

6

Minimum

ADCCLKs 7 ADCCLKs

Conversion 1

13 ADC Clocks

A. This diagram uses ACQPS = 6 timings. These particular timings are not valid on this device (except for a throw-away

sample to meet the first sample issue in the device errata), but they correctly demonstrate the operation of the

converter.

Figure 6-8. Timing Example for Sequential Mode / Early Interrupt Pulse

Peripheral Information and Timings

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Analog Input A

SOC0 Sample

A Window

SOC2 Sample

A Window

Analog Input B

SOC0 Sample

B Window

SOC2 Sample

B Window

0

2

9

22 24

37

50

ADCCLK

ADCCTL1.INTPULSEPOS

ADCSOCFLG 1.SOC0

ADCSOCFLG 1.SOC1

ADCSOCFLG 1.SOC2

S/H Window Pulse to Core

ADCRESULT 0

SOC0 (A/B)

SOC2 (A/B)

2 ADCCLKs

Result 0 (A) Latched

ADCRESULT 1

Result 0 (B) Latched

ADCRESULT 2

EOC0 Pulse

EOC1 Pulse

1 ADCCLK

EOC2 Pulse

ADCINTFLG .ADCINTx

Minimum

7 ADCCLKs

Conversion 0 (A)

13 ADC Clocks

Conversion 0 (B)

13 ADC Clocks

2 ADCCLKs

19

ADCCLKs

Minimum

7 ADCCLKs

Conversion 1 (A)

13 ADC Clocks

A. This diagram uses ACQPS = 6 timings. These particular timings are not valid on this device (except for a throw-away

sample to meet the first sample issue in the device errata), but they correctly demonstrate the operation of the

converter.

Figure 6-9. Timing Example for Simultaneous Mode / Late Interrupt Pulse

80

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Analog Input A

Analog Input B

SOC0 Sample

A Window

SOC2 Sample

A Window

SOC0 Sample

B Window

SOC2 Sample

B Window

0

2

9

22 24

37

50

ADCCLK

ADCCTL1.INTPULSEPOS

ADCSOCFLG1.SOC0

ADCSOCFLG1.SOC1

ADCSOCFLG1.SOC2

S/H Window Pulse to Core

ADCRESULT 0

SOC0 (A/B)

SOC2 (A/B)

Result 0 (A) Latched

2 ADCCLKs

Result 0 (B) Latched

ADCRESULT 1

ADCRESULT 2

EOC0 Pulse

EOC1 Pulse

EOC2 Pulse

ADCINTFLG.ADCINTx

Conversion 0 (A)

13 ADC Clocks

Conversion 0 (B)

13 ADC Clocks

Minimum

2 ADCCLKs

7 ADCCLKs

19

Minimum

7 ADCCLKs

Conversion 1 (A)

13 ADC Clocks

ADCCLKs

A. This diagram uses ACQPS = 6 timings. These particular timings are not valid on this device (except for a throw-away

sample to meet the first sample issue in the device errata), but they correctly demonstrate the operation of the

converter.

Figure 6-10. Timing Example for Simultaneous Mode / Early Interrupt Pulse

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6.3.1.2.5 Detailed Descriptions

Integral Nonlinearity

Integral nonlinearity refers to the deviation of each individual code from a line drawn from zero through full

scale. The point used as zero occurs one-half LSB before the first code transition. The full-scale point is

defined as level one-half LSB beyond the last code transition. The deviation is measured from the center

of each particular code to the true straight line between these two points.

Differential Nonlinearity

An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal

value. A differential nonlinearity error of less than ±1 LSB ensures no missing codes.

Zero Offset

Zero error is the difference between the ideal input voltage and the actual input voltage that just causes a

transition from an output code of zero to an output code of one.

Gain Error

The first code transition should occur at an analog value one-half LSB above negative full scale. The last

transition should occur at an analog value one and one-half LSB below the nominal full scale. Gain error is

the deviation of the actual difference between first and last code transitions and the ideal difference

between first and last code transitions.

Signal-to-Noise Ratio + Distortion (SINAD)

SINAD is the ratio of the rms value of the measured input signal to the rms sum of all other spectral

components below the Nyquist frequency, including harmonics but excluding dc. The value for SINAD is

expressed in decibels.

Effective Number of Bits (ENOB)

For a sine wave, SINAD can be expressed in terms of the number of bits. Using the following formula,

(SINAD -1.76)

N =

6.02

it is possible to get a measure of performance expressed as N, the effective number of

bits. Thus, effective number of bits for a device for sine wave inputs at a given input frequency can be

calculated directly from its measured SINAD.

Total Harmonic Distortion (THD)

THD is the ratio of the rms sum of the first nine harmonic components to the rms value of the measured

input signal and is expressed as a percentage or in decibels.

Spurious Free Dynamic Range (SFDR)

SFDR is the difference in dB between the rms amplitude of the input signal and the peak spurious signal.

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6.3.2 Analog Front End (AFE)

6.3.2.1 Analog Front End Device-Specific Information

The Analog Front End (AFE) contains up to seven comparators with up to three integrated Digital-to-

Analog Converters (DACs), one VREFOUT-buffered DAC, up to four Programmable Gain Amplifiers

(PGAs), and up to four digital filters. Figure 6-11 and Figure 6-12 show the AFE.

The comparator output signal filtering is achieved using the Digital Filter present on selective input line

and qualifies the output of the COMP/DAC subsystem (see Figure 6-13). The filtered or unfiltered output

of the COMP/DAC subsystem can be configured to be an input to the Digital Compare submodule of the

ePWM peripheral. Note: The Analog inputs are brought in through the AFE subsystem rather than through

an AIO Mux, which is not present.

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V_REFHI

A0

V_REFOUT/A0

_

V_REFOUT

COMPB7

DFSS

Cmp1

+

Cmp1

+

Buffered

DAC Output

DAC6 6-bit

B7

PGA

G~ = 3, 6, 11

DAC5 6-bit

PFCGND

B0

A2

A4

B2

B0

A2

A4

B2

DAC1 6-bit

COMPA1H

_

COMPA1L

DFSS

Cmp2

Cmp3

+

ADCIN-

SWITCH

A1

DFSS

PGA

G~ = 3, 6, 11

A1

A3

M1GND

_

COMPA3H

DFSS

COMPA3L

DFSS

Cmp4

Cmp5

+

A3

B1

PGA

G~ = 3, 6, 11

_

M1GND

COMPB1H

DFSS

COMPB1L

DFSS

Cmp6

Cmp7

+

PGA

G~ = 3, 6, 11

B1

ADCIN-

SWITCH

ADC

DAC2 6-bit

Temp Sensor

A5

ADCCTL1.TEMPCONV

ADCCTL1.REFLOCONV

V_REFLO

B5

A7

B3

A7

B3

GAIN AMP

G~ = 3

A6

B4

B6

M2GND

GAIN AMP

G~ = 3

B4

GAIN AMP

G~ = 3

B6

Legend

Cmp - Comparator

DFSS - Comparator Trip/Digital Filter Subsystem Block

GAIN AMP - Fixed Gain Amplifier

PGA - Programmable Gain Amplifier

Figure 6-11. 28055, 28054, 28053, 28052, and 28051 Analog Front End (AFE)

84

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V_REFHI

A0

V_REFOUT/A0

_

V_REFOUT

Cmp1

+

Buffered

DAC Output

DAC6 6-bit

GAIN AMP

G~ = 3

B7

PFCGND

B0

A2

A4

B2

B0

A2

A4

B2

DAC1 6-bit

COMPA1H

_

COMPA1L

DFSS

Cmp2

Cmp3

+

ADCIN-

SWITCH

A1

DFSS

PGA

G~ = 3, 6, 11

A1

A3

M1GND

_

COMPA3H

DFSS

COMPA3L

DFSS

Cmp4

Cmp5

+

A3

B1

PGA

G~ = 3, 6, 11

_

M1GND

COMPB1H

DFSS

COMPB1L

DFSS

Cmp6

Cmp7

+

PGA

G~ = 3, 6, 11

B1

A5

ADCIN-

SWITCH

ADC

DAC2 6-bit

Temp Sensor

A5

ADCCTL1.TEMPCONV

ADCCTL1.REFLOCONV

V_REFLO

B5

A7

B3

A7

B3

GAIN AMP

G~ = 3

A6

B4

B6

M2GND

GAIN AMP

G~ = 3

B4

GAIN AMP

G~ = 3

B6

Legend

Cmp - Comparator

DFSS - Comparator Trip/Digital Filter Subsystem Block

GAIN AMP - Fixed Gain Amplifier

PGA - Programmable Gain Amplifier

Figure 6-12. 28050 Analog Front End (AFE)

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ePWM 1-7

DCAH

DCAL

COMPxINPEN

D

CTRIPxx0CTLREGISTER

CTRIPEN

C

T

R

I

P

S

E

L

ENABLES

COMPxxPOL

CTRIPFILCTRL

REGISTER

COMPxxH

1

0

1

Digital Filter

(to all ePWM modules)

DCBH

DCBL

COMPxxPOL

COMPxxL

CTRIPBYP

SYSCLK

0

CTRIPxxOUTEN

CTRIPOUTxxSTS

CTRIPOUTxxFLG

CTRIPOUTLATEN

1

0

CTRIPOUTBYP

1

0

1

GPIO

MUX

CTRIPOUTPOL

Figure 6-13. Comparator Trip/Digital Filter Subsystem

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6.3.2.2 Analog Front End Register Descriptions

Table 6-11. DAC Control Registers

SIZE

(x16)

EALLOW

PROTECTED

REGISTER NAME

DAC1CTL

ADDRESS

DESCRIPTION

0x6400

0x6401

0x6402

0x6403

0x6404

0x6405

1

Yes

DAC1 Control Register

DAC2 Control Register

DAC3 Control Register

DAC4 Control Register

DAC5 Control Register

VREFOUT DAC Control Register

DAC2CTL

DAC3CTL

DAC4CTL

DAC5CTL

VREFOUTCTL

Table 6-12. DAC, PGA, Comparator, and Filter Enable Registers

SIZE

(x16)

EALLOW

PROTECTED

REGISTER NAME

ADDRESS

DESCRIPTION

DACEN

0x6410

0x6411

0x6412

0x6413

0x6414

0x6415

0x6416

1

Yes

DAC Enables Register

VREFOUTEN

PGAEN

VREFOUT Enable Register

Programmable Gain Amplifier Enable Register

Comparator Enable Register

COMPEN

AMPM1_GAIN

AMPM2_GAIN

AMP_PFC_GAIN

Motor Unit 1 PGA Gain Controls Register

Motor Unit 2 PGA Gain Controls Register

PFC PGA Gain Controls Register

Table 6-13. SWITCH Registers

SIZE

(x16)

EALLOW

PROTECTED

REGISTER NAME

ADDRESS

DESCRIPTION

ADCINSWITCH

Reserved

0x6421

1

7

Yes

ADC Input-Select Switch Control Register

Reserved

0x6422 –

0x6428

COMPHYSTCTL

0x6429

1

Yes

Comparator Hysteresis Control Register

Table 6-14. Digital Filter and Comparator Control Registers

SIZE

(x16)

EALLOW

PROTECTED

REGISTER NAME

ADDRESS

DESCRIPTION

CTRIPA1ICTL

CTRIPA1FILCTL

CTRIPA1FILCLKCTL

Reserved

0x6430

0x6431

0x6432

0x6433

0x6434

0x6435

0x6436

0x6437

0x6438

0x6439

0x643A

0x643B

0x643C

0x643D

0x643E

0x643F

1

Yes

CTRIPA1 Filter Input and Function Control Register

CTRIPA1 Filter Parameters Register

CTRIPA1 Filter Sample Clock Control Register

Reserved

CTRIPA3ICTL

CTRIPA3FILCTL

CTRIPA3FILCLKCTL

Reserved

CTRIPA3 Filter Input and Function Control Register

CTRIPA3 Filter Parameters Register

CTRIPA3 Filter Sample Clock Control Register

Reserved

CTRIPB1ICTL

CTRIPB1FILCTL

CTRIPB1FILCLKCTL

Reserved

CTRIPB1 Filter Input and Function Control Register

CTRIPB1 Filter Parameters Register

CTRIPB1 Filter Sample Clock Control Register

Reserved

CTRIPM1OCTL

CTRIPM1STS

CTRIPM1FLGCLR

CTRIPM1 CTRIP Filter Output Control Register

CTRIPM1 CTRIPxx Outputs Status Register

CTRIPM1 CTRIPxx Flag Clear Register

Peripheral Information and Timings

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Table 6-14. Digital Filter and Comparator Control Registers (continued)

SIZE

(x16)

EALLOW

PROTECTED

REGISTER NAME

Reserved

ADDRESS

DESCRIPTION

0x6440 –

0x644F

16

Yes

Reserved

CTRIPA6ICTL

CTRIPA6FILCTL

CTRIPA6FILCLKCTL

Reserved

0x6450

0x6451

0x6452

0x6453

0x6454

0x6455

0x6456

0x6457

0x6458

0x6459

0x645A

0x645B

0x645C

0x645D

0x645E

0x645F

1

16

Yes

CTRIPA6 Filter Input and Function Control Register

CTRIPA6 Filter Parameters Register

CTRIPA6 Filter Sample Clock Control Register

Reserved

CTRIPB4ICTL

CTRIPB4FILCTL

CTRIPB4FILCLKCTL

Reserved

CTRIPB4 Filter Input and Function Control Register

CTRIPB4 Filter Parameters Register

CTRIPB4 Filter Sample Clock Control Register

Reserved

CTRIPB6ICTL

CTRIPB6FILCTL

CTRIPB6FILCLKCTL

Reserved

CTRIPB6 Filter Input and Function Control Register

CTRIPB6 Filter Parameters Register

CTRIPB6 Filter Sample Clock Control Register

Reserved

CTRIPM2OCTL

CTRIPM2STS

CTRIPM2FLGCLR

Reserved

CTRIPM2 CTRIP Filter Output Control Register

CTRIPM2 CTRIPxx Outputs Status Register

CTRIPM2 CTRIPxx Flag Clear Register

Reserved

0x6460 –

0x646F

CTRIPB7ICTL

CTRIPB7FILCTL

CTRIPB7FILCLKCTL

Reserved

0x6470

0x6471

0x6472

1

9

Yes

CTRIPB7 Filter Input and Function Control Register

CTRIPB7 Filter Parameters Register

CTRIPB7 Filter Sample Clock Control Register

Reserved

0x6473 –

0x647B

Reserved

0x647C

0x647D

0x647E

0x647F

1

Yes

Reserved

CTRIPPFCOCTL

CTRIPPFCSTS

CTRIPPFCFLGCLR

CTRIPPFC CTRIPxx Outputs Status Register

CTRIPPFC CTRIPxx Flag Clear Register

CTRIPPFC COMP Test Control Register

Table 6-15. LOCK Registers

SIZE

(x16)

EALLOW

PROTECTED

REGISTER NAME

ADDRESS

DESCRIPTION

LOCKCTRIP

Reserved

0x64F0

0x64F1

0x64F2

0x64F3

0x64F4

0x64F5

0x64F6

1

Yes

Lock Register for CTRIP Filters Register

Reserved

LOCKDAC

Lock Register for DACs Register

Reserved

LOCKAMPCOMP

Reserved

Lock Register for Amplifiers and Comparators Register

Reserved

LOCKSWITCH

Lock Register for Switches Register

88

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6.3.2.3 Programmable Gain Amplifier Electrical Data/Timing

Table 6-16. Op-Amp Linear Output and ADC Sampling Time Across Gain Settings

MINIMUM

EQUIVALENT GAIN FROM

INPUT TO OUTPUT

LINEAR OUTPUT RANGE

OF OP-AMP

ADC SAMPLING TIME

TO ACHIEVE SETTLING

ACCURACY

INTERNAL RESISTOR RATIO

10

5

11

6

0.6 V to V_DDA– 0.6 V

384 ns (ACQPS = 23)

2

3

Table 6-17. PGA Gain Stage: DC Accuracy Across Gain Settings

COMPENSATED

GAIN-ERROR DRIFT ACROSS

COMPENSATED INPUT

OFFSET-ERROR ACROSS

EQUIVALENT GAIN FROM

INPUT TO OUTPUT

INTERNAL RESISTOR RATIO

TEMPERATURE AND SUPPLY TEMPERATURE AND SUPPLY

VARIATIONS

VARIATIONS IN mV

10

5

11

6

< ±2.5%

< ±8 mV

< ±1.5%

< ±8 mV

2

3

< ±1.0%

< ±8 mV

6.3.2.4 Comparator Block Electrical Data/Timing

Table 6-18. Electrical Characteristics of the Comparator/DAC

PARAMETER

MIN

TYP

MAX

UNITS

Comparator

Comparator Input Range

Comparator response time to PWM Trip Zone (Async)

V_SSA– V_DDA

V

65

95

ns

Comparator large step response time to PWM Trip Zone (Async)

ns

Input Offset

Input Hysteresis⁽¹⁾

TBD

mV

DAC

DAC Output Range

DAC resolution

DAC Gain

V_DDA/ 2⁶– V_DDA

V

6

–1.5

10

bits

%

DAC Offset

Monotonic

mV

Yes

0.2

INL

LSB

(1) Hysteresis on the comparator inputs is achieved with a Schmidt trigger configuration, which results in an effective 100-kΩ feedback

resistance between the output of the comparator and the non-inverting input of the comparator. There is an option to disable the

hysteresis and, with it, the feedback resistance; see the Analog-to-Digital Converter and Comparator chapter of the TMS320x2805x

Piccolo Technical Reference Manual (literature number SPRUHE5) for more information on this option if needed in your system.

Peripheral Information and Timings

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6.3.2.5 V_REFOUTBuffered DAC Electrical Data

Table 6-19. Electrical Characteristics of V_REFOUTBuffered DAC

PARAMETER

MIN

TYP

MAX

UNITS

LSB

bits

V_REFOUTProgrammable Range

V_REFOUTresolution

V_REFOUTGain

V_REFOUTOffset

Monotonic

6

56

6

–1.5

10

%

mV

Yes

±0.2

INL

LSB

kΩ

Load

3

100

pF

90

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6.4 Serial Peripheral Interface (SPI)

6.4.1 Serial Peripheral Interface Device-Specific Information

The device includes the four-pin serial peripheral interface (SPI) module. The SPI is a high-speed,

synchronous serial I/O port that allows a serial bit stream of programmed length (one to sixteen bits) to be

shifted into and out of the device at a programmable bit-transfer rate. Normally, the SPI is used for

communications between the MCU and external peripherals or another processor. Typical applications

include external I/O or peripheral expansion through devices such as shift registers, display drivers, and

ADCs. Multidevice communications are supported by the master/slave operation of the SPI.

The SPI module features include:

•

Four external pins:

–

SPISOMI: SPI slave-output/master-input pin

SPISIMO: SPI slave-input/master-output pin

SPISTE: SPI slave transmit-enable pin

SPICLK: SPI serial-clock pin

NOTE: All four pins can be used as GPIO if the SPI module is not used.

•

Two operational modes: master and slave

Baud rate: 125 different programmable rates.

LSPCLK

Baud rate =

when SPIBRR = 3 to127

when SPIBRR = 0,1, 2

(SPIBRR + 1)

LSPCLK

Baud rate =

4

•

Data word length: one to sixteen data bits

Four clocking schemes (controlled by clock polarity and clock phase bits) include:

–

Falling edge without phase delay: SPICLK active-high. SPI transmits data on the falling edge of the

SPICLK signal and receives data on the rising edge of the SPICLK signal.

Falling edge with phase delay: SPICLK active-high. SPI transmits data one half-cycle ahead of the

falling edge of the SPICLK signal and receives data on the falling edge of the SPICLK signal.

Rising edge without phase delay: SPICLK inactive-low. SPI transmits data on the rising edge of the

SPICLK signal and receives data on the falling edge of the SPICLK signal.

Rising edge with phase delay: SPICLK inactive-low. SPI transmits data one half-cycle ahead of the

falling edge of the SPICLK signal and receives data on the rising edge of the SPICLK signal.

•

Simultaneous receive and transmit operation (transmit function can be disabled in software)

Transmitter and receiver operations are accomplished through either interrupt-driven or polled

algorithms.

•

Nine SPI module control registers: Located in control register frame beginning at address 7040h.

NOTE

All registers in this module are 16-bit registers that are connected to Peripheral Frame 2.

When a register is accessed, the register data is in the lower byte (7–0), and the upper byte

(15–8) is read as zeros. Writing to the upper byte has no effect.

Enhanced feature:

•

4-level transmit/receive FIFO

Delayed transmit control

Bi-directional 3-wire SPI mode support

Audio data receive support via SPISTE inversion

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Figure 6-14 is a block diagram of the SPI in slave mode.

SPIFFENA

Overrun

INT ENA

Receiver

Overrun Flag

SPIFFTX.14

RX FIFO Registers

SPIRXBUF

SPISTS.7

SPICTL.4

RX FIFO _0

RX FIFO _1

-----

SPIINT

RX FIFO Interrupt

RX Interrupt

Logic

RX FIFO _3

16

SPIRXBUF

Buffer Register

SPIFFOVF

FLAG

SPIFFRX.15

To CPU

TX FIFO Registers

SPITXBUF

TX FIFO _3

TX Interrupt

Logic

TX FIFO Interrupt

-----

TX FIFO _1

SPITX

TX FIFO _0

16

SPI INT

ENA

16

SPI INT FLAG

SPITXBUF

Buffer Register

SPISTS.6

SPICTL.0

TRIWIRE

SPIPRI.0

16

M

S

M

SPIDAT

Data Register

TW

S

SW1

SW2

SPISIMO

SPISOMI

M

S

TW

SPIDAT.15 - 0

M

S

TW

STEINV

SPIPRI.1

Talk

STEINV

SPICTL.1

SPISTE

State Control

Master/Slave

SPICTL.2

SPI Char

LSPCLK

SPICCR.3 - 0

S

SW3

3

2

1

0

Clock

Polarity

Clock

Phase

M

S

SPI Bit Rate

SPIBRR.6 - 0

SPICCR.6

SPICTL.3

SPICLK

M

6

5

4

3

2

1

0

A. SPISTE is driven low by the master for a slave device.

Figure 6-14. SPI Module Block Diagram (Slave Mode)

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6.4.2 Serial Peripheral Interface Register Descriptions

The SPI port operation is configured and controlled by the registers listed in Table 6-20.

Table 6-20. SPI-A Registers

NAME

SPICCR

SPICTL

ADDRESS

0x7040

0x7041

0x7042

0x7044

0x7046

0x7047

0x7048

0x7049

0x704A

0x704B

0x704C

0x704F

SIZE (x16) EALLOW PROTECTED

DESCRIPTION⁽¹⁾

SPI-A Configuration Control Register

SPI-A Operation Control Register

SPI-A Status Register

1

No

SPISTS

SPIBRR

SPIRXEMU

SPIRXBUF

SPITXBUF

SPIDAT

SPI-A Baud Rate Register

SPI-A Receive Emulation Buffer Register

SPI-A Serial Input Buffer Register

SPI-A Serial Output Buffer Register

SPI-A Serial Data Register

SPIFFTX

SPIFFRX

SPIFFCT

SPIPRI

SPI-A FIFO Transmit Register

SPI-A FIFO Receive Register

SPI-A FIFO Control Register

SPI-A Priority Control Register

(1) Registers in this table are mapped to Peripheral Frame 2. This space only allows 16-bit accesses. 32-bit accesses produce undefined

results.

6.4.3 Serial Peripheral Interface Master Mode Electrical Data/Timing

Table 6-21 lists the master mode timing (clock phase = 0) and Table 6-22 lists the timing (clock

phase = 1). Figure 6-15 and Figure 6-16 show the timing waveforms.

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6.4.4 Serial Peripheral Interface Slave Mode Electrical Data/Timing

Table 6-23 lists the slave mode external timing (clock phase = 0) and Table 6-24 (clock phase = 1).

Figure 6-17 and Figure 6-18 show the timing waveforms.

Table 6-23. SPI Slave Mode External Timing (Clock Phase = 0)^{(1)(2)(3)(4)(5)}

NO.

MIN

MAX UNIT

12 t_c(SPC)S

13 t_w(SPCH)S

t_w(SPCL)S

Cycle time, SPICLK

4t_c(LCO)

ns

Pulse duration, SPICLK high (clock polarity = 0)

0.5t_c(SPC)S– 10 0.5t_c(SPC)S

ns

Pulse duration, SPICLK low (clock polarity = 1)

0.5t_c(SPC)S– 10 0.5t_c(SPC)S

14 t_w(SPCL)S

t_w(SPCH)S

Pulse duration, SPICLK low (clock polarity = 0)

0.5t_c(SPC)S– 10 0.5t_c(SPC)S

Pulse duration, SPICLK high (clock polarity = 1)

0.5t_c(SPC)S– 10 0.5t_c(SPC)S

15 t_{d(SPCH-SOMI)S}

t_{d(SPCL-SOMI)S}

16 t_{v(SPCL-SOMI)S}

t_{v(SPCH-SOMI)S}

19 t_{su(SIMO-SPCL)S}

t_{su(SIMO-SPCH)S}

20 t_{v(SPCL-SIMO)S}

t_{v(SPCH-SIMO)S}

Delay time, SPICLK high to SPISOMI valid (clock polarity = 0)

Delay time, SPICLK low to SPISOMI valid (clock polarity = 1)

Valid time, SPISOMI data valid after SPICLK low (clock polarity = 0)

Valid time, SPISOMI data valid after SPICLK high (clock polarity = 1)

Setup time, SPISIMO before SPICLK low (clock polarity = 0)

Setup time, SPISIMO before SPICLK high (clock polarity = 1)

Valid time, SPISIMO data valid after SPICLK low (clock polarity = 0)

Valid time, SPISIMO data valid after SPICLK high (clock polarity = 1)

21

0.75t_c(SPC)S

26

0.5t_c(SPC)S– 10

(1) The MASTER / SLAVE bit (SPICTL.2) is cleared and the CLOCK PHASE bit (SPICTL.3) is cleared.

(2) t_c(SPC)= SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR + 1)

(3) Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate:

Master mode transmit 15-MHz MAX, master mode receive 10-MHz MAX

Slave mode transmit 10-MHz MAX, slave mode receive 10-MHz MAX.

(4) t_c(LCO)= LSPCLK cycle time

(5) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).

12

SPICLK

(clock polarity = 0)

13

14

SPICLK

(clock polarity = 1)

15

16

SPISOMI data Is valid

19

SPISOMI

SPISIMO

20

SPISIMO data

must be valid

(A)

SPISTE

A. In the slave mode, the SPISTE signal should be asserted low at least 0.5t_c(SPC)(minimum) before the valid SPI clock

edge and remain low for at least 0.5t_c(SPC)after the receiving edge (SPICLK) of the last data bit.

Figure 6-17. SPI Slave Mode External Timing (Clock Phase = 0)

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Table 6-24. SPI Slave Mode External Timing (Clock Phase = 1)^(1)(2)(3)(4)

NO.

MIN

8t_c(LCO)

MAX UNIT

12 t_c(SPC)S

13 t_w(SPCH)S

t_w(SPCL)S

Cycle time, SPICLK

ns

Pulse duration, SPICLK high (clock polarity = 0)

Pulse duration, SPICLK low (clock polarity = 1)

Pulse duration, SPICLK low (clock polarity = 0)

Pulse duration, SPICLK high (clock polarity = 1)

Setup time, SPISOMI before SPICLK high (clock polarity = 0)

Setup time, SPISOMI before SPICLK low (clock polarity = 1)

0.5t_c(SPC)S– 10

0.125t_c(SPC)S

0.5t_c(SPC)S

ns

0.5t_{c(SPC) S}

0.5t_c(SPC)S

14 t_w(SPCL)S

t_w(SPCH)S

17 t_{su(SOMI-SPCH)S}

t_{su(SOMI-SPCL)S}

18 t_{v(SPCL-SOMI)S}

0.125t_c(SPC)S

Valid time, SPISOMI data valid after SPICLK low

(clock polarity = 1)

0.75t_c(SPC)S

t_{v(SPCH-SOMI)S}

Valid time, SPISOMI data valid after SPICLK high

(clock polarity = 0)

0.75t_{c(SPC) S}

21 t_{su(SIMO-SPCH)S}

t_{su(SIMO-SPCL)S}

Setup time, SPISIMO before SPICLK high (clock polarity = 0)

Setup time, SPISIMO before SPICLK low (clock polarity = 1)

26

ns

22 t_{v(SPCH-SIMO)S}

Valid time, SPISIMO data valid after SPICLK high

(clock polarity = 0)

0.5t_c(SPC)S– 10

t_{v(SPCL-SIMO)S}

Valid time, SPISIMO data valid after SPICLK low

(clock polarity = 1)

0.5t_c(SPC)S– 10

(1) The MASTER / SLAVE bit (SPICTL.2) is cleared and the CLOCK PHASE bit (SPICTL.3) is cleared.

(2) t_c(SPC)= SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR + 1)

(3) Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate:

Master mode transmit 15-MHz MAX, master mode receive 10-MHz MAX

Slave mode transmit 10-MHz MAX, slave mode receive 10-MHz MAX.

(4) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).

12

SPICLK

(clock polarity = 0)

13

14

SPICLK

(clock polarity = 1)

17

18

SPISOMI data is valid

SPISOMI

SPISIMO

Data Valid

21

22

SPISIMO data

must be valid

(A)

SPISTE

A. In the slave mode, the SPISTE signal should be asserted low at least 0.5t_c(SPC)before the valid SPI clock edge and

remain low for at least 0.5t_c(SPC)after the receiving edge (SPICLK) of the last data bit.

Figure 6-18. SPI Slave Mode External Timing (Clock Phase = 1)

Peripheral Information and Timings

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6.5 Serial Communications Interface (SCI)

6.5.1 Serial Communications Interface Device-Specific Information

The 2805x devices include three serial communications interface (SCI) modules (SCI-A, SCI-B, SCI-C).

Each SCI module supports digital communications between the CPU and other asynchronous peripherals

that use the standard non-return-to-zero (NRZ) format. The SCI receiver and transmitter are double-

buffered, and each has its own separate enable and interrupt bits. Both can be operated independently or

simultaneously in the full-duplex mode. To ensure data integrity, the SCI checks received data for break

detection, parity, overrun, and framing errors. The bit rate is programmable to over 65000 different speeds

through a 16-bit baud-select register.

Features of each SCI module include:

•

Two external pins:

–

SCITXD: SCI transmit-output pin

SCIRXD: SCI receive-input pin

NOTE: Both pins can be used as GPIO if not used for SCI.

Baud rate programmable to 64K different rates:

–

LSPCLK

Baud rate =

when BRR ¹ 0

when BRR = 0

(BRR + 1) * 8

LSPCLK

16

•

Data-word format

–

One start bit

Data-word length programmable from one to eight bits

Optional even/odd/no parity bit

One or two stop bits

•

Four error-detection flags: parity, overrun, framing, and break detection

Two wake-up multiprocessor modes: idle-line and address bit

Half- or full-duplex operation

Double-buffered receive and transmit functions

Transmitter and receiver operations can be accomplished through interrupt-driven or polled algorithms

with status flags.

–

Transmitter: TXRDY flag (transmitter-buffer register is ready to receive another character) and TX

EMPTY flag (transmitter-shift register is empty)

–

Receiver: RXRDY flag (receiver-buffer register is ready to receive another character), BRKDT flag

(break condition occurred), and RX ERROR flag (monitoring four interrupt conditions)

•

Separate enable bits for transmitter and receiver interrupts (except BRKDT)

NRZ (non-return-to-zero) format

NOTE

All registers in this module are 8-bit registers that are connected to Peripheral Frame 2.

When a register is accessed, the register data is in the lower byte (7–0), and the upper byte

(15–8) is read as zeros. Writing to the upper byte has no effect.

Enhanced features:

•

Auto baud-detect hardware logic

4-level transmit/receive FIFO

100

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Figure 6-19 shows the SCI module block diagram.

SCICTL1.1

SCITXD

Frame Format and Mode

SCITXD

TXSHF

Register

TXENA

Parity

Even/Odd Enable

TX EMPTY

SCICTL2.6

8

SCICCR.6 SCICCR.5

TXRDY

TX INT ENA

SCICTL2.0

Transmitter-Data

Buffer Register

SCICTL2.7

TXWAKE

SCICTL1.3

1

8

TX FIFO _0

TX FIFO

Interrupts

TXINT

TX Interrupt

Logic

TX FIFO _1

-----

To CPU

TX FIFO _3

SCI TX Interrupt select logic

SCITXBUF.7-0

WUT

TX FIFO registers

SCIFFENA

AutoBaud Detect logic

SCIFFTX.14

SCIHBAUD. 15 - 8

SCIRXD

RXSHF

Register

Baud Rate

MSbyte

Register

SCIRXD

RXWAKE

LSPCLK

SCIRXST.1

SCILBAUD. 7 - 0

RXENA

SCICTL1.0

8

Baud Rate

LSbyte

Register

SCICTL2.1

Receive Data

Buffer register

SCIRXBUF.7-0

RXRDY

RX/BK INT ENA

SCIRXST.6

8

RX FIFO _3

BRKDT

SCIRXST.5

-----

RX FIFO

Interrupts

RX FIFO_1

RX FIFO _0

RXINT

RX Interrupt

Logic

SCIRXBUF.7-0

RX FIFO registers

To CPU

RXFFOVF

SCIRXST.7 SCIRXST.4 - 2

SCIFFRX.15

RX Error

FE OE PE

RX Error

RX ERR INT ENA

SCICTL1.6

SCI RX Interrupt select logic

Figure 6-19. Serial Communications Interface (SCI) Module Block Diagram

Peripheral Information and Timings

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6.5.2 Serial Communications Interface Register Descriptions

The SCI port operation is configured and controlled by the registers listed in Table 6-25.

Table 6-25. SCI-A Registers⁽¹⁾

EALLOW

PROTECTED

NAME

ADDRESS

SIZE (x16)

DESCRIPTION

SCICCRA

SCICTL1A

0x7050

0x7051

0x7052

0x7053

0x7054

0x7055

0x7056

0x7057

0x7059

0x705A

0x705B

0x705C

0x705F

1

No

SCI-A Communications Control Register

SCI-A Control Register 1

SCIHBAUDA

SCILBAUDA

SCICTL2A

SCI-A Baud Register, High Bits

SCI-A Baud Register, Low Bits

SCI-A Control Register 2

SCIRXSTA

SCIRXEMUA

SCIRXBUFA

SCITXBUFA

SCIFFTXA⁽²⁾

SCIFFRXA⁽²⁾

SCIFFCTA⁽²⁾

SCIPRIA

SCI-A Receive Status Register

SCI-A Receive Emulation Data Buffer Register

SCI-A Receive Data Buffer Register

SCI-A Transmit Data Buffer Register

SCI-A FIFO Transmit Register

SCI-A FIFO Receive Register

SCI-A FIFO Control Register

SCI-A Priority Control Register

(1) Registers in this table are mapped to Peripheral Frame 2 space. This space only allows 16-bit accesses. 32-bit accesses produce

undefined results.

(2) These registers are new registers for the FIFO mode.

102

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6.6 Enhanced Controller Area Network (eCAN)

6.6.1 Enhanced Controller Area Network Device-Specific Information

The CAN module (eCAN-A) has the following features:

•

Fully compliant with CAN protocol, version 2.0B

Supports data rates up to 1 Mbps

Thirty-two mailboxes, each with the following properties:

–

Configurable as receive or transmit

Configurable with standard or extended identifier

Has a programmable receive mask

Supports data and remote frame

Composed of 0 to 8 bytes of data

Uses a 32-bit time stamp on receive and transmit message

Protects against reception of new message

Holds the dynamically programmable priority of transmit message

Employs a programmable interrupt scheme with two interrupt levels

Employs a programmable alarm on transmission or reception time-out

•

Low-power mode

Programmable wake-up on bus activity

Automatic reply to a remote request message

Automatic retransmission of a frame in case of loss of arbitration or error

32-bit local network time counter synchronized by a specific message (communication in conjunction

with mailbox 16)

•

Self-test mode

–

Operates in a loopback mode receiving its own message. A "dummy" acknowledge is provided,

thereby eliminating the need for another node to provide the acknowledge bit.

NOTE

For a SYSCLKOUT of 60 MHz, the smallest bit rate possible is 4.6875 kbps.

The F2805x CAN has passed the conformance test per ISO/DIS 16845. Contact TI for test report and

exceptions.

Peripheral Information and Timings

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eCAN0INT

eCAN1INT

Controls Address

Data

32

Enhanced CAN Controller

Message Controller

Mailbox RAM

(512 Bytes)

Memory Management

Unit

eCAN Memory

(512 Bytes)

Registers and

CPU Interface,

Receive Control Unit,

Timer Management Unit

32-Message Mailbox

of 4 x 32-Bit Words

Message Objects Control

32

eCAN Protocol Kernel

Receive Buffer

Transmit Buffer

Control Buffer

Status Buffer

SN65HVD23x

3.3-V CAN Transceiver

CAN Bus

Figure 6-20. eCAN Block Diagram and Interface Circuit

Table 6-26. 3.3-V eCAN Transceivers

SUPPLY

VOLTAGE

LOW-POWER

MODE

SLOPE

CONTROL

PART NUMBER

VREF

OTHER

T_A

SN65HVD230

SN65HVD230Q

SN65HVD231

SN65HVD231Q

SN65HVD232

SN65HVD232Q

SN65HVD233

SN65HVD234

SN65HVD235

ISO1050

3.3 V

3–5.5 V

Standby

Sleep

Adjustable

None

Yes

–

–40°C to 85°C

–40°C to 125°C

–40°C to 85°C

–40°C to 125°C

–40°C to 85°C

–40°C to 125°C

–55°C to 105°C

–

Yes

–

Sleep

Yes

–

None

–

None

–

Standby

Standby and Sleep

Standby

None

Adjustable

None

Diagnostic Loopback

–

Autobaud Loopback

Built-in Isolation

Low Prop Delay

Thermal Shutdown

Failsafe Operation

Dominant Time-Out

104

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eCAN-A Control and Status Registers

Mailbox Enable - CANME

Mailbox Direction - CANMD

Transmission Request Set - CANTRS

Transmission Request Reset - CANTRR

Transmission Acknowledge - CANTA

Abort Acknowledge - CANAA

eCAN-A Memory (512 Bytes)

Control and Status Registers

6000h

Received Message Pending - CANRMP

Received Message Lost - CANRML

Remote Frame Pending - CANRFP

Global Acceptance Mask - CANGAM

603Fh

6040h

Local Acceptance Masks (LAM)

(32 x 32-Bit RAM)

607Fh

6080h

Master Control - CANMC

Message Object Time Stamps (MOTS)

(32 x 32-Bit RAM)

Bit-Timing Configuration - CANBTC

60BFh

60C0h

Error and Status - CANES

Message Object Time-Out (MOTO)

(32 x 32-Bit RAM)

Transmit Error Counter - CANTEC

Receive Error Counter - CANREC

Global Interrupt Flag 0 - CANGIF0

Global Interrupt Mask - CANGIM

Global Interrupt Flag 1 - CANGIF1

Mailbox Interrupt Mask - CANMIM

Mailbox Interrupt Level - CANMIL

60FFh

eCAN-A Memory RAM (512 Bytes)

6100h-6107h

6108h-610Fh

6110h-6117h

6118h-611Fh

6120h-6127h

Mailbox 0

Mailbox 1

Mailbox 2

Mailbox 3

Mailbox 4

Overwrite Protection Control - CANOPC

TX I/O Control - CANTIOC

RX I/O Control - CANRIOC

Time Stamp Counter - CANTSC

Time-Out Control - CANTOC

Time-Out Status - CANTOS

61E0h-61E7h

61E8h-61EFh

61F0h-61F7h

61F8h-61FFh

Mailbox 28

Mailbox 29

Mailbox 30

Mailbox 31

Reserved

Message Mailbox (16 Bytes)

Message Identifier - MSGID

Message Control - MSGCTRL

Message Data Low - MDL

Message Data High - MDH

61E8h-61E9h

61EAh-61EBh

61ECh-61EDh

61EEh-61EFh

Figure 6-21. eCAN-A Memory Map

NOTE

If the eCAN module is not used in an application, the RAM available (LAM, MOTS, MOTO,

and mailbox RAM) can be used as general-purpose RAM. The CAN module clock should be

enabled if the eCAN RAM (LAM, MOTS, MOTO, and mailbox RAM) is used as general-

purpose RAM.

Peripheral Information and Timings

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6.6.2 Enhanced Controller Area Network Register Descriptions

The CAN registers listed in Table 6-27 are used by the CPU to configure and control the CAN controller

and the message objects. eCAN control registers only support 32-bit read/write operations. Mailbox RAM

can be accessed as 16 bits or 32 bits. 32-bit accesses are aligned to an even boundary.

Table 6-27. CAN Register Map⁽¹⁾

eCAN-A

REGISTER NAME

SIZE (x32)

DESCRIPTION

ADDRESS

0x6000

0x6002

0x6004

0x6006

0x6008

0x600A

0x600C

0x600E

0x6010

0x6012

0x6014

0x6016

0x6018

0x601A

0x601C

0x601E

0x6020

0x6022

0x6024

0x6026

0x6028

0x602A

0x602C

0x602E

0x6030

0x6032

CANME

CANMD

1

Mailbox enable

Mailbox direction

CANTRS

CANTRR

CANTA

Transmit request set

Transmit request reset

Transmission acknowledge

Abort acknowledge

Receive message pending

Receive message lost

Remote frame pending

Global acceptance mask

Master control

CANAA

CANRMP

CANRML

CANRFP

CANGAM

CANMC

CANBTC

CANES

Bit-timing configuration

Error and status

CANTEC

CANREC

CANGIF0

CANGIM

CANGIF1

CANMIM

CANMIL

CANOPC

CANTIOC

CANRIOC

CANTSC

CANTOC

CANTOS

Transmit error counter

Receive error counter

Global interrupt flag 0

Global interrupt mask

Global interrupt flag 1

Mailbox interrupt mask

Mailbox interrupt level

Overwrite protection control

TX I/O control

RX I/O control

Time stamp counter (Reserved in SCC mode)

Time-out control (Reserved in SCC mode)

Time-out status (Reserved in SCC mode)

(1) These registers are mapped to Peripheral Frame 1.

106

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6.7 Inter-Integrated Circuit (I2C)

6.7.1 Inter-Integrated Circuit Device-Specific Information

The device contains one I2C Serial Port. Figure 6-22 shows how the I2C peripheral module interfaces

within the device.

The I2C module has the following features:

•

Compliance with the Philips Semiconductors I2C-bus specification (version 2.1):

–

Support for 1-bit to 8-bit format transfers

7-bit and 10-bit addressing modes

General call

START byte mode

Support for multiple master-transmitters and slave-receivers

Support for multiple slave-transmitters and master-receivers

Combined master transmit/receive and receive/transmit mode

Data transfer rate of from 10 kbps up to 400 kbps (I2C Fast-mode rate)

•

One 4-word receive FIFO and one 4-word transmit FIFO

One interrupt that can be used by the CPU. This interrupt can be generated as a result of one of the

following conditions:

–

Transmit-data ready

Receive-data ready

Register-access ready

No-acknowledgment received

Arbitration lost

Stop condition detected

Addressed as slave

•

An additional interrupt that can be used by the CPU when in FIFO mode

Module enable/disable capability

Free data format mode

Peripheral Information and Timings

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I2C Module

I2CXSR

I2CDXR

TX FIFO

RX FIFO

FIFO Interrupt to

CPU/PIE

SDA

Peripheral Bus

I2CRSR

I2CDRR

Control/Status

Registers

CPU

Clock

Synchronizer

SCL

Prescaler

Noise Filters

Arbitrator

Interrupt to

CPU/PIE

I2C INT

A. The I2C registers are accessed at the SYSCLKOUT rate. The internal timing and signal waveforms of the I2C port are

also at the SYSCLKOUT rate.

B. The clock enable bit (I2CAENCLK) in the PCLKCRO register turns off the clock to the I2C port for low power

operation. Upon reset, I2CAENCLK is clear, which indicates the peripheral internal clocks are off.

Figure 6-22. I2C Peripheral Module Interfaces

6.7.2 Inter-Integrated Circuit Register Descriptions

The registers in Table 6-28 configure and control the I2C port operation.

Table 6-28. I2C-A Registers

EALLOW

PROTECTED

NAME

ADDRESS

DESCRIPTION

I2C own address register

I2COAR

I2CIER

0x7900

0x7901

0x7902

0x7903

0x7904

0x7905

0x7906

0x7907

0x7908

0x7909

0x790A

0x790C

0x7920

0x7921

–

No

I2C interrupt enable register

I2C status register

I2CSTR

I2CCLKL

I2CCLKH

I2CCNT

I2CDRR

I2CSAR

I2CDXR

I2CMDR

I2CISRC

I2CPSC

I2CFFTX

I2CFFRX

I2CRSR

I2CXSR

I2C clock low-time divider register

I2C clock high-time divider register

I2C data count register

I2C data receive register

I2C slave address register

I2C data transmit register

I2C mode register

I2C interrupt source register

I2C prescaler register

I2C FIFO transmit register

I2C FIFO receive register

I2C receive shift register (not accessible to the CPU)

I2C transmit shift register (not accessible to the CPU)

–

108

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6.7.3 Inter-Integrated Circuit Electrical Data/Timing

Table 6-29. I2C Timing

TEST CONDITIONS

MIN

MAX

UNIT

f_SCL

SCL clock frequency

I2C clock module frequency is between

7 MHz and 12 MHz and I2C prescaler and

clock divider registers are configured

appropriately

400

kHz

v_il

Low level input voltage

High level input voltage

Input hysteresis

0.3 V_DDIO

V

V_ih

0.7 V_DDIO

V_hys

V_ol

0.05 V_DDIO

V

Low level output voltage

Low period of SCL clock

3 mA sink current

0

0.4

V

t_LOW

I2C clock module frequency is between

7 MHz and 12 MHz and I2C prescaler and

clock divider registers are configured

appropriately

1.3

μs

t_HIGH

High period of SCL clock

I2C clock module frequency is between

7 MHz and 12 MHz and I2C prescaler and

clock divider registers are configured

appropriately

0.6

μs

l_I

Input current with an input voltage

–10

10

μA

between 0.1 V_DDIOand 0.9 V_DDIOMAX

Peripheral Information and Timings

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6.8 Enhanced Pulse Width Modulator (ePWM)

6.8.1 Enhanced Pulse Width Modulator Device-Specific Information

The devices contain up to seven enhanced PWM Modules (ePWM1–ePWM7). Figure 6-23 shows a block

diagram of multiple ePWM modules. Figure 6-24 shows the signal interconnections with the ePWM. See

the Enhanced Pulse Width Modulator (ePWM) Module chapter of the TMS320x2805x Piccolo Technical

Reference Manual (literature number SPRUHE5) for more details.

110

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EPWMSYNCI

EPWM1SYNCI

EPWM1B

EPWM1TZINT

EPWM1INT

EPWM1

Module

TZ1 to TZ3

EPWM2TZINT

EPWM2INT

EQEP1ERR

CLOCKFAIL

EMUSTOP

TZ4

TZ5

TZ6

PIE

EPWMxTZINT

EPWMxINT

EPWM1ENCLK

TBCLKSYNC

eCAPI

EPWM1SYNCO

EPWM2SYNCI

EPWM1SYNCO

TZ1 to TZ3

EPWM2B

EPWM2

Module

CTRIP

Output

Subsystem

CTRIPxx

EQEP1ERR

CLOCKFAIL

EMUSTOP

EPWM1A

EPWM2A

TZ4

TZ5

TZ6

EPWM2ENCLK

TBCLKSYNC

EPWMxA

G

P

I

EPWM2SYNCO

O

M

U

X

SOCA1

SOCB1

SOCA2

SOCB2

SOCAx

SOCBx

ADC

EPWMxB

EPWMxSYNCI

TZ1 to TZ3

EPWMx

Module

EQEP1ERR

CLOCKFAIL

EMUSTOP

EQEP1ERR

TZ4

TZ5

TZ6

eQEP1

EPWMxENCLK

TBCLKSYNC

System Control

C28x CPU

SOCA1

SOCA2

SPCAx

ADCSOCAO

ADCSOCBO

Pulse Stretch

(32 SYSCLKOUT Cycles, Active-Low Output)

SOCB1

SOCB2

SPCBx

Pulse Stretch

(32 SYSCLKOUT Cycles, Active-Low Output)

Figure 6-23. ePWM

Peripheral Information and Timings

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Time-Base (TB)

CTR=ZERO

Sync

In/Out

Select

Mux

TBPRD Shadow (24)

TBPRD Active (24)

EPWMxSYNCO

CTR=CMPB

Disabled

CTR=PRD

TBCTL[SYNCOSEL]

TBCTL[PHSEN]

EPWMxSYNCI

DCAEVT1.sync

DCBEVT1.sync

Counter

Up/Down

(16 Bit)

TBCTL[SWFSYNC]

(Software Forced

Sync)

CTR=ZERO

TCBNT

Active (16)

CTR_Dir

CTR=PRD

CTR=ZERO

EPWMxINT

CTR=PRD or ZERO

CTR=CMPA

Event

Trigger

and

Interrupt

(ET)

16

EPWMxSOCA

Phase

TBPHS Active (24)

Control

CTR=CMPB

CTR_Dir

(A)

DCAEVT1.soc

(A)

EPWMxSOCB

EPWMxSOCA

ADC

DCBEVT1.soc

EPWMxSOCB

Action

Qualifier

CTR=CMPA

(AQ)

16

CMPA Active (24)

CMPA Shadow (24)

EPWMA

EPWMxA

PWM

Chopper

(PC)

Trip

Zone

(TZ)

Dead

CTR=CMPB

Band

(DB)

16

EPWMB

EPWMxB

EPWMxTZINT

TZ1 to TZ3

CMPB Active (16)

CMPB Shadow (16)

EMUSTOP

CLOCKFAIL

CTR=ZERO

EQEP1ERR

DCAEVT1.inter

DCBEVT1.inter

(A)

DCAEVT1.force

DCAEVT2.force

DCBEVT1.force

DCBEVT2.force

DCAEVT2.inter

DCBEVT2.inter

A. These events are generated by the Type 1 ePWM digital compare (DC) submodule based on the levels of the

COMPxOUT and TZ signals.

Figure 6-24. ePWM Sub-Modules Showing Critical Internal Signal Interconnections

112

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Table 6-31. ePWM5–ePWM7 Control and Status Registers

SIZE (x16) /

#SHADOW

NAME

ePWM5

ePWM6

ePWM7

DESCRIPTION

Time Base Control Register

TBCTL

0x6900

0x6901

0x6902

0x6903

0x6904

0x6905

0x6906

0x6907

0x6908

0x6909

0x690A

0x690B

0x690C

0x690D

0x690E

0x690F

0x6910

0x6940

0x6941

0x6942

0x6943

0x6944

0x6945

0x6946

0x6947

0x6948

0x6949

0x694A

0x694B

0x694C

0x694D

0x694E

0x694F

0x6950

0x6980

0x6981

0x6982

0x6983

0x6984

0x6985

0x6986

0x6987

0x6988

0x6989

0x698A

0x698B

0x698C

0x698D

0x698E

0x698F

0x6990

1 / 0

1 / 1

1 / 0

1 / 1

1 / 0

1 / 1

1 / 0

TBSTS

Time Base Status Register

Reserved

TBPHS

Reserved

Time Base Phase Register

TBCTR

Time Base Counter Register

Time Base Period Register Set

Reserved

TBPRD

Reserved

CMPCTL

Reserved

CMPA

Counter Compare Control Register

Reserved

Counter Compare A Register Set

Counter Compare B Register Set

Action Qualifier Control Register For Output A

Action Qualifier Control Register For Output B

Action Qualifier Software Force Register

Action Qualifier Continuous S/W Force Register Set

Dead-Band Generator Control Register

CMPB

AQCTLA

AQCTLB

AQSFRC

AQCSFRC

DBCTL

DBRED

Dead-Band Generator Rising Edge Delay Count

Register

DBFED

0x6911

0x6951

0x6991

1 / 0

Dead-Band Generator Falling Edge Delay Count

Register

TZSEL

0x6912

0x6913

0x6914

0x6915

0x6916

0x6917

0x6918

0x6919

0x691A

0x691B

0x691C

0x691D

0x691E

0x6920

-

0x6952

0x6953

0x6954

0x6955

0x6956

0x6957

0x6958

0x6959

0x695A

0x695B

0x695C

0x695D

0x695E

0x6960

-

0x6992

0x6993

0x6994

0x6995

0x6996

0x6997

0x6998

0x6999

0x699A

0x699B

0x699C

0x699D

0x699E

0x69A0

-

1 / 0

Trip Zone Select Register⁽¹⁾

TZDCSEL

TZCTL

Trip Zone Digital Compare Register

Trip Zone Control Register⁽¹⁾

Trip Zone Enable Interrupt Register⁽¹⁾

1 / 0

TZEINT

TZFLG

1 / 0

(1)

1 / 0

Trip Zone Flag Register

TZCLR

1 / 0

Trip Zone Clear Register⁽¹⁾

Trip Zone Force Register⁽¹⁾

Event Trigger Selection Register

Event Trigger Prescale Register

Event Trigger Flag Register

Event Trigger Clear Register

Event Trigger Force Register

PWM Chopper Control Register

Reserved

TZFRC

1 / 0

ETSEL

1 / 0

ETPS

1 / 0

ETFLG

1 / 0

ETCLR

1 / 0

ETFRC

1 / 0

PCCTL

1 / 0

Reserved

TBPRDM

Reserved

CMPAM

DCTRIPSEL

DCACTL

DCBCTL

DCFCTL

DCCAPCT

1 / 0

Reserved

-

1 / 0

Reserved

0x6928

0x692A

0x692B

0x692C

0x692D

0x6930

0x6931

0x6932

0x6933

0x6934

0x6968

0x696A

0x696B

0x696C

0x696D

0x6970

0x6971

0x6972

0x6973

0x6974

0x69A8

0x69AA

0x69AB

0x69AC

0x69AD

0x69B0

0x69B1

0x69B2

0x69B3

0x69B4

1 / 0

Reserved

1 / W⁽²⁾

1 / 0

Reserved

Time Base Period Register Mirror

Reserved

Compare A Register Mirror

(1)

Digital Compare Trip Select Register

1 / 0

Digital Compare A Control Register⁽¹⁾

Digital Compare B Control Register⁽¹⁾

Digital Compare Filter Control Register⁽¹⁾

Digital Compare Capture Control Register⁽¹⁾

1 / 0

(1) Registers that are EALLOW protected.

(2) W = Write to shadow register

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Table 6-31. ePWM5–ePWM7 Control and Status Registers (continued)

SIZE (x16) /

#SHADOW

NAME

ePWM5

ePWM6

ePWM7

DESCRIPTION

DCFOFFSET

DCFOFFSETCNT

DCFWINDOW

DCFWINDOWCNT

DCCAP

0x6935

0x6936

0x6937

0x6938

0x6939

0x6975

0x6976

0x6977

0x6978

0x6979

0x69B5

0x69B6

0x69B7

0x69B8

0x69B9

1 / 1

1 / 0

1 / 1

Digital Compare Filter Offset Register

Digital Compare Filter Offset Counter Register

Digital Compare Filter Window Register

Digital Compare Filter Window Counter Register

Digital Compare Counter Capture Register

6.8.3 Enhanced Pulse Width Modulator Electrical Data/Timing

PWM refers to PWM outputs on ePWM1–7. Table 6-32 shows the PWM timing requirements and Table 6-

33, switching characteristics.

Table 6-32. ePWM Timing Requirements⁽¹⁾

MIN

2t_c(SCO)

MAX

UNIT

cycles

t_w(SYCIN)

Sync input pulse width

Asynchronous

Synchronous

2t_c(SCO)

With input qualifier

1t_c(SCO)+ t_w(IQSW)

(1) For an explanation of the input qualifier parameters, see Table 6-45.

Table 6-33. ePWM Switching Characteristics

over recommended operating conditions (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

33.33

MAX

UNIT

ns

t_w(PWM)

Pulse duration, PWMx output high/low

Sync output pulse width

t_w(SYNCOUT)

t_d(PWM)tza

8t_c(SCO)

cycles

ns

Delay time, trip input active to PWM forced high

Delay time, trip input active to PWM forced low

no pin load

25

20

t_d(TZ-PWM)HZ

Delay time, trip input active to PWM Hi-Z

ns

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6.8.3.1 Trip-Zone Input Timing

Table 6-34. Trip-Zone Input Timing Requirements⁽¹⁾

MIN

2t_c(TBCLK)

MAX UNIT

cycles

t_w(TZ)

Pulse duration, TZx input low

Asynchronous

Synchronous

2t_c(TBCLK)

cycles

With input qualifier

2t_c(TBCLK)+ t_w(IQSW)

cycles

(1) For an explanation of the input qualifier parameters, see Table 6-45.

SYSCLK

t

w(TZ)

TZ^(A)

t

d(TZ-PWM)HZ

PWM^(B)

A. TZ - TZ1, TZ2, TZ3, TZ4, TZ5, TZ6

B. PWM refers to all the PWM pins in the device. The state of the PWM pins after TZ is taken high depends on the PWM

recovery software.

Figure 6-25. PWM Hi-Z Characteristics

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6.9 Enhanced Capture Module (eCAP)

6.9.1 Enhanced Capture Module Device-Specific Information

The device contains an enhanced capture module (eCAP1). Figure 6-26 shows a functional block diagram

of a module.

CTRPHS

(phase register−32 bit)

APWM mode

SYNCIn

CTR_OVF

OVF

CTR [0−31]

PRD [0−31]

CMP [0−31]

TSCTR

(counter−32 bit)

SYNCOut

PWM

compare

logic

Delta−mode

RST

32

CTR=PRD

CTR=CMP

CTR [0−31]

PRD [0−31]

32

eCAPx

32

LD1

CAP1

(APRD active)

Polarity

select

LD

APRD

shadow

32

CMP [0−31]

32

LD2

CAP2

(ACMP active)

Polarity

select

LD

Event

qualifier

Event

Pre-scale

32

ACMP

shadow

Polarity

select

32

LD3

LD4

CAP3

(APRD shadow)

LD

CAP4

(ACMP shadow)

Polarity

select

LD

4

Capture events

4

CEVT[1:4]

Interrupt

Trigger

and

Flag

control

Continuous /

Oneshot

Capture Control

to PIE

CTR_OVF

CTR=PRD

CTR=CMP

Figure 6-26. eCAP Functional Block Diagram

The eCAP module is clocked at the SYSCLKOUT rate.

The clock enable bits (ECAP1 ENCLK) in the PCLKCR1 register turn off the eCAP module individually (for

low power operation). Upon reset, ECAP1ENCLK is set to low, indicating that the peripheral clock is off.

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6.9.2 Enhanced Capture Module Register Descriptions

Table 6-35 shows the eCAP Control and Status Registers.

Table 6-35. eCAP Control and Status Registers

NAME

TSCTR

CTRPHS

CAP1

eCAP1

0x6A00

SIZE (x16) EALLOW PROTECTED

DESCRIPTION

Time-Stamp Counter

2

8

1

6

0x6A02

Counter Phase Offset Value Register

Capture 1 Register

0x6A04

CAP2

0x6A06

Capture 2 Register

CAP3

0x6A08

Capture 3 Register

CAP4

0x6A0A

Capture 4 Register

Reserved

ECCTL1

ECCTL2

ECEINT

ECFLG

ECCLR

ECFRC

Reserved

0x6A0C – 0x6A12

0x6A14

Reserved

Capture Control Register 1

Capture Control Register 2

Capture Interrupt Enable Register

Capture Interrupt Flag Register

Capture Interrupt Clear Register

Capture Interrupt Force Register

Reserved

0x6A15

0x6A16

0x6A17

0x6A18

0x6A19

0x6A1A – 0x6A1F

6.9.3 Enhanced Capture Module Electrical Data/Timing

Table 6-36 shows the eCAP timing requirement and Table 6-37 shows the eCAP switching characteristics.

Table 6-36. Enhanced Capture (eCAP) Timing Requirement⁽¹⁾

MIN

2t_c(SCO)

MAX UNIT

cycles

t_w(CAP)

Capture input pulse width

Asynchronous

Synchronous

2t_c(SCO)

cycles

With input qualifier

1t_c(SCO)+ t_w(IQSW)

cycles

(1) For an explanation of the input qualifier parameters, see Table 6-45.

Table 6-37. eCAP Switching Characteristics

over recommended operating conditions (unless otherwise noted)

PARAMETER

MIN

MAX

UNIT

t_w(APWM)

Pulse duration, APWMx output high/low

20

ns

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6.10 Enhanced Quadrature Encoder Pulse (eQEP)

6.10.1 Enhanced Quadrature Encoder Pulse Device-Specific Information

The device contains one enhanced quadrature encoder pulse (eQEP) module.

Figure 6-27 shows the eQEP functional block diagram.

System Control

Registers

To CPU

EQEPxENCLK

SYSCLKOUT

QCPRD

QCAPCTL

16

QCTMR

16

Quadrature

Capture

Unit

QCTMRLAT

QCPRDLAT

(QCAP)

QUTMR

QUPRD

QWDTMR

QWDPRD

Registers

Used by

Multiple Units

32

16

QEPCTL

QEPSTS

QFLG

UTOUT

QWDOG

UTIME

QDECCTL

16

WDTOUT

EQEPxAIN

EQEPxBIN

EQEPxIIN

EQEPxA/XCLK

EQEPxB/XDIR

EQEPxI

QCLK

QDIR

QI

EQEPxINT

16

PIE

Position Counter/

Control Unit

(PCCU)

EQEPxIOUT

EQEPxIOE

EQEPxSIN

EQEPxSOUT

EQEPxSOE

Quadrature

Decoder

(QDU)

QS

GPIO

MUX

QPOSLAT

QPOSSLAT

QPOSILAT

PHE

PCSOUT

EQEPxS

32

16

QPOSCNT

QPOSINIT

QPOSMAX

QEINT

QFRC

QPOSCMP

QCLR

QPOSCTL

Enhanced QEP (eQEP) Peripheral

Figure 6-27. eQEP Functional Block Diagram

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6.10.2 Enhanced Quadrature Encoder Pulse Register Descriptions

Table 6-38 shows the eQEP Control and Status Registers.

Table 6-38. eQEP Control and Status Registers

eQEP1

ADDRESS

NAME

QPOSCNT

SIZE(x16)/

#SHADOW

REGISTER DESCRIPTION

0x6B00

0x6B02

0x6B04

0x6B06

0x6B08

0x6B0A

0x6B0C

0x6B0E

0x6B10

0x6B12

0x6B13

0x6B14

0x6B15

0x6B16

0x6B17

0x6B18

0x6B19

0x6B1A

0x6B1B

0x6B1C

0x6B1D

0x6B1E

0x6B1F

0x6B20

2/0

2/1

2/0

1/0

31/0

eQEP Position Counter

QPOSINIT

QPOSMAX

QPOSCMP

QPOSILAT

QPOSSLAT

QPOSLAT

QUTMR

eQEP Initialization Position Count

eQEP Maximum Position Count

eQEP Position-compare

eQEP Index Position Latch

eQEP Strobe Position Latch

eQEP Position Latch

eQEP Unit Timer

QUPRD

eQEP Unit Period Register

eQEP Watchdog Timer

QWDTMR

QWDPRD

QDECCTL

QEPCTL

QCAPCTL

QPOSCTL

QEINT

eQEP Watchdog Period Register

eQEP Decoder Control Register

eQEP Control Register

eQEP Capture Control Register

eQEP Position-compare Control Register

eQEP Interrupt Enable Register

eQEP Interrupt Flag Register

eQEP Interrupt Clear Register

eQEP Interrupt Force Register

eQEP Status Register

QFLG

QCLR

QFRC

QEPSTS

QCTMR

eQEP Capture Timer

QCPRD

eQEP Capture Period Register

eQEP Capture Timer Latch

eQEP Capture Period Latch

QCTMRLAT

QCPRDLAT

Reserved

0x6B21 –

0x6B3F

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6.10.3 Enhanced Quadrature Encoder Pulse Electrical Data/Timing

Table 6-39 shows the eQEP timing requirement and Table 6-40 shows the eQEP switching

characteristics.

Table 6-39. Enhanced Quadrature Encoder Pulse (eQEP) Timing Requirements⁽¹⁾

TEST CONDITIONS

Synchronous

MIN

MAX

UNIT

cycles

t_w(QEPP)

QEP input period

2t_c(SCO)

With input qualifier

Synchronous

2[1t_c(SCO)+ t_w(IQSW)]

t_w(INDEXH)

t_w(INDEXL)

t_w(STROBH)

t_w(STROBL)

QEP Index Input High time

QEP Index Input Low time

QEP Strobe High time

QEP Strobe Input Low time

2t_c(SCO)

2t_c(SCO)+t_w(IQSW)

2t_c(SCO)

With input qualifier

Synchronous

With input qualifier

Synchronous

2t_c(SCO)+ t_w(IQSW)

2t_c(SCO)

2t_c(SCO)+ t_w(IQSW)

2t_c(SCO)

With input qualifier

Synchronous

With input qualifier

2t_c(SCO)+t_w(IQSW)

(1) For an explanation of the input qualifier parameters, see Table 6-45.

Table 6-40. eQEP Switching Characteristics

over recommended operating conditions (unless otherwise noted)

PARAMETER

MIN

MAX

UNIT

t_d(CNTR)xin

Delay time, external clock to counter increment

4t_c(SCO)

6t_c(SCO)

cycles

t_{d(PCS-OUT)QEP}

Delay time, QEP input edge to position compare sync output

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6.11 JTAG Port

6.11.1 JTAG Port Device-Specific Information

On the 2805x device, the JTAG port is reduced to 5 pins (TRST, TCK, TDI, TMS, TDO). TCK, TDI, TMS

and TDO pins are also GPIO pins. The TRST signal selects either JTAG or GPIO operating mode for the

pins in Figure 6-28. During emulation/debug, the GPIO function of these pins are not available. If the

GPIO38/TCK/XCLKIN pin is used to provide an external clock, an alternate clock source should be used

to clock the device during emulation/debug since this pin will be needed for the TCK function.

NOTE

In 2805x devices, the JTAG pins may also be used as GPIO pins. Care should be taken in

the board design to ensure that the circuitry connected to these pins do not affect the

emulation capabilities of the JTAG pin function. Any circuitry connected to these pins should

not prevent the emulator from driving (or being driven by) the JTAG pins for successful

debug.

TRST = 0: JTAG Disabled (GPIO Mode)

TRST = 1: JTAG Mode

TRST

XCLKIN

GPIO38_in

TCK

TCK/GPIO38

GPIO38_out

C28x

Core

GPIO37_in

TDO

TDO/GPIO37

1

0

GPIO37_out

GPIO36_in

1

0

TMS

TMS/GPIO36

TDI/GPIO35

1

GPIO36_out

GPIO35_in

1

0

TDI

1

GPIO35_out

Figure 6-28. JTAG/GPIO Multiplexing

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6.11.1.1 Emulator Connection Without Signal Buffering for the MCU

Figure 6-29 shows the connection between the MCU and JTAG header for a single-processor

configuration. If the distance between the JTAG header and the MCU is greater than 6 inches, the

emulation signals must be buffered. If the distance is less than 6 inches, buffering is typically not needed.

Figure 6-29 shows the simpler, no-buffering situation. For the pullup and pulldown resistor values, see

Section 3.2.

6 inches or less

V_DDIO

13

14

2

5

EMU0

EMU1

TRST

TMS

PD

4

6

8

TRST

TMS

TDI

GND

1

GND

3

TDI

7

10

12

TDO

TCK

TDO

11

9

TCK

TCK_RET

MCU

JTAG Header

A. See Figure 6-28 for JTAG/GPIO multiplexing.

Figure 6-29. Emulator Connection Without Signal Buffering for the MCU

NOTE

The 2805x devices do not have EMU0/EMU1 pins. For designs that have a JTAG Header

on-board, the EMU0/EMU1 pins on the header must be tied to V_DDIOthrough a 4.7-kΩ

(typical) resistor.

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6.12 General-Purpose Input/Output (GPIO)

6.12.1 General-Purpose Input/Output Device-Specific Information

The GPIO MUX can multiplex up to three independent peripheral signals on a single GPIO pin in addition

to providing individual pin bit-banging I/O capability.

Table 6-41. GPIOA MUX^{(1) (2)}

DEFAULT AT RESET

PERIPHERAL

SELECTION 1

PERIPHERAL

SELECTION 2

PERIPHERAL

SELECTION 3

PRIMARY I/O

FUNCTION

GPAMUX1 REGISTER

BITS

(GPAMUX1 BITS = 00) (GPAMUX1 BITS = 01)

(GPAMUX1 BITS = 10)

(GPAMUX1 BITS = 11)

1-0

GPIO0

GPIO1

GPIO2

GPIO3

GPIO4

GPIO5

GPIO6

GPIO7

GPIO8

GPIO9

GPIO10

GPIO11

GPIO12

GPIO13

GPIO14

GPIO15

EPWM1A (O)

EPWM1B (O)

EPWM2A (O)

EPWM2B (O)

EPWM3A (O)

EPWM3B (O)

EPWM4A (O)

EPWM4B (O)

EPWM5A (O)

EPWM5B (O)

EPWM6A (O)

EPWM6B (O)

TZ1 (I)

Reserved

COMP1OUT (O)

Reserved

3-2

5-4

Reserved

7-6

SPISOMIA (I/O)

Reserved

COMP2OUT (O)

Reserved

9-8

11-10

13-12

15-14

17-16

19-18

21-20

23-22

25-24

27-26

29-28

31-30

SPISIMOA (I/O)

EPWMSYNCI (I)

SCIRXDA (I)

Reserved

ECAP1 (I/O)

EPWMSYNCO (O)

Reserved

ADCSOCAO (O)

Reserved

ADCSOCBO (O)

Reserved

SCITXDA (O)

Reserved

TZ2 (I)

Reserved

TZ3 (I)

Reserved

TZ1 (I)

Reserved

GPAMUX2 REGISTER

BITS

(GPAMUX2 BITS = 00) (GPAMUX2 BITS = 01)

(GPAMUX2 BITS = 10)

(GPAMUX2 BITS = 11)

1-0

GPIO16

GPIO17

SPISIMOA (I/O)

SPISOMIA (I/O)

SPICLKA (I/O)

SPISTEA (I/O)

EQEP1A (I)

EQEP1B (I)

EQEP1S (I/O)

EQEP1I (I/O)

ECAP1 (I/O)

Reserved

SDAA (I/OD)

SCLA (I/OD)

Reserved

TZ2 (I)

TZ3 (I)

3-2

5-4

GPIO18

XCLKOUT (O)

ECAP1 (I/O)

COMP1OUT (O)

COMP2OUT (O)

Reserved

7-6

GPIO19/XCLKIN

GPIO20

9-8

11-10

13-12

15-14

17-16

19-18

21-20

23-22

25-24

27-26

29-28

31-30

GPIO21

GPIO22

GPIO23

Reserved

GPIO24

Reserved

GPIO25

Reserved

GPIO26

Reserved

GPIO27

Reserved

GPIO28

SCIRXDA (I)

SCITXDA (O)

CANRXA (I)

CANTXA (O)

TZ2 (I)

GPIO29

TZ3 (I)

GPIO30

Reserved

GPIO31

Reserved

(1) The word reserved means that there is no peripheral assigned to this GPxMUX1/2 register setting. Should the Reserved GPxMUX1/2

register setting be selected, the state of the pin will be undefined and the pin may be driven. This selection is a reserved configuration

for future expansion.

(2) I = Input, O = Output, OD = Open Drain

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Table 6-42. GPIOB MUX⁽¹⁾

DEFAULT AT RESET

PRIMARY I/O FUNCTION

PERIPHERAL

SELECTION 1

PERIPHERAL

SELECTION 2

PERIPHERAL

SELECTION 3

GPBMUX1 REGISTER

BITS

(GPBMUX1 BITS = 00)

(GPBMUX1 BITS = 01)

(GPBMUX1 BITS = 10)

(GPBMUX1 BITS = 11)

1-0

GPIO32

GPIO33

SDAA (I/OD)

SCLA (I/OD)

COMP2OUT (O)

Reserved

EPWMSYNCI (I)

EPWMSYNCO (O)

Reserved

ADCSOCAO (O)

ADCSOCBO (O)

COMP3OUT (O)

Reserved

3-2

5-4

GPIO34

7-6

GPIO35 (TDI)

GPIO36 (TMS)

GPIO37 (TDO)

GPIO38/XCLKIN (TCK)

GPIO39

Reserved

9-8

Reserved

11-10

13-12

15-14

17-16

19-18

21-20

23-22

25-24

27-26

29-28

31-30

Reserved

GPIO40

EPWM7A (O)

EPWM7B (O)

Reserved

GPIO41

Reserved

GPIO42

Reserved

COMP1OUT (O)

COMP2OUT (O)

Reserved

GPIO43

Reserved

GPIO44

Reserved

(1) I = Input, O = Output, OD = Open Drain

The user can select the type of input qualification for each GPIO pin via the GPxQSEL1/2 registers from

four choices:

•

Synchronization to SYSCLKOUT Only (GPxQSEL1/2 = 0, 0): This mode is the default mode of all

GPIO pins at reset and this mode simply synchronizes the input signal to the system clock

(SYSCLKOUT).

Qualification Using Sampling Window (GPxQSEL1/2 = 0, 1 and 1, 0): In this mode the input signal,

after synchronization to the system clock (SYSCLKOUT), is qualified by a specified number of cycles

before the input is allowed to change.

The sampling period is specified by the QUALPRD bits in the GPxCTRL register and is configurable in

groups of 8 signals. The sampling period specifies a multiple of SYSCLKOUT cycles for sampling the

input signal. The sampling window is either 3-samples or 6-samples wide and the output is only

changed when ALL samples are the same (all 0s or all 1s) as shown in Figure 6-32 (for 6 sample

mode).

•

No Synchronization (GPxQSEL1/2 = 1,1): This mode is used for peripherals where synchronization is

not required (synchronization is performed within the peripheral).

Due to the multi-level multiplexing that is required on the device, there may be cases where a peripheral

input signal can be mapped to more then one GPIO pin. Also, when an input signal is not selected, the

input signal will default to either a 0 or 1 state, depending on the peripheral.

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GPIOXINT1SEL

GPIOXINT2SEL

GPIOXINT3SEL

GPIOLMPSEL

LPMCR0

External Interrupt

PIE

MUX

Low Power

Modes Block

Asynchronous

path

GPxDAT (read)

GPxQSEL1/2

GPxCTRL

GPxPUD

N/C

00

01

Peripheral 1 Input

Input

Internal

Pullup

Qualification

Peripheral 2 Input

10

11

Peripheral 3 Input

GPxTOGGLE

Asynchronous path

GPIOx pin

GPxCLEAR

GPxSET

00

01

GPxDAT (latch)

Peripheral 1 Output

10

11

Peripheral 2 Output

Peripheral 3 Output

High Impedance

Output Control

GPxDIR (latch)

00

01

Peripheral 1 Output Enable

Peripheral 2 Output Enable

0 = Input, 1 = Output

XRS

10

11

Peripheral 3 Output Enable

= Default at Reset

GPxMUX1/2

A. x stands for the port, either A or B. For example, GPxDIR refers to either the GPADIR and GPBDIR register

depending on the particular GPIO pin selected.

B. GPxDAT latch/read are accessed at the same memory location.

C. This diagram is a generic GPIO MUX block diagram. Not all options may be applicable for all GPIO pins. See the

Systems Control and Interrupts chapter of the TMS320x2805x Piccolo Technical Reference Manual (literature number

SPRUHE5) for pin-specific variations.

Figure 6-30. GPIO Multiplexing

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6.12.2 General-Purpose Input/Output Register Descriptions

The device supports 42 GPIO pins. The GPIO control and data registers are mapped to Peripheral

Frame 1 to enable 32-bit operations on the registers (along with 16-bit operations). Table 6-43 shows the

GPIO register mapping.

Table 6-43. GPIO Registers

NAME

ADDRESS

GPIO CONTROL REGISTERS (EALLOW PROTECTED)

0x6F80 GPIO A Control Register (GPIO0 to 31)

SIZE (x16)

DESCRIPTION

GPACTRL

GPAQSEL1

GPAQSEL2

GPAMUX1

GPAMUX2

GPADIR

2

0x6F82

0x6F84

0x6F86

0x6F88

0x6F8A

0x6F8C

0x6F90

0x6F92

0x6F96

0x6F9A

0x6F9C

0x6FB6

0x6FBA

GPIO A Qualifier Select 1 Register (GPIO0 to 15)

GPIO A Qualifier Select 2 Register (GPIO16 to 31)

GPIO A MUX 1 Register (GPIO0 to 15)

GPIO A MUX 2 Register (GPIO16 to 31)

GPIO A Direction Register (GPIO0 to 31)

GPIO A Pull Up Disable Register (GPIO0 to 31)

GPIO B Control Register (GPIO32 to 44)

GPIO B Qualifier Select 1 Register (GPIO32 to 44)

GPIO B MUX 1 Register (GPIO32 to 44)

GPIO B Direction Register (GPIO32 to 44)

GPIO B Pull Up Disable Register (GPIO32 to 44)

Reserved

GPAPUD

GPBCTRL

GPBQSEL1

GPBMUX1

GPBDIR

GPBPUD

Reserved

GPIO DATA REGISTERS (NOT EALLOW PROTECTED)

GPADAT

GPASET

0x6FC0

0x6FC2

0x6FC4

0x6FC6

0x6FC8

0x6FCA

0x6FCC

0x6FCE

0x6FD8

0x6FDA

0x6FDC

0x6FDE

2

GPIO A Data Register (GPIO0 to 31)

GPIO A Data Set Register (GPIO0 to 31)

GPIO A Data Clear Register (GPIO0 to 31)

GPIO A Data Toggle Register (GPIO0 to 31)

GPIO B Data Register (GPIO32 to 44)

GPIO B Data Set Register (GPIO32 to 44)

GPIO B Data Clear Register (GPIO32 to 44)

GPIO B Data Toggle Register (GPIO32 to 44)

Reserved

GPACLEAR

GPATOGGLE

GPBDAT

GPBSET

GPBCLEAR

GPBTOGGLE

Reserved

GPIO INTERRUPT AND LOW POWER MODES SELECT REGISTERS (EALLOW PROTECTED)

GPIOXINT1SEL

GPIOXINT2SEL

GPIOXINT3SEL

GPIOLPMSEL

0x6FE0

0x6FE1

0x6FE2

0x6FE8

1

2

XINT1 GPIO Input Select Register (GPIO0 to 31)

XINT2 GPIO Input Select Register (GPIO0 to 31)

XINT3 GPIO Input Select Register (GPIO0 to 31)

LPM GPIO Select Register (GPIO0 to 31)

NOTE

There is a two-SYSCLKOUT cycle delay from when the write to the GPxMUXn and

GPxQSELn registers occurs to when the action is valid.

128

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6.12.3 General-Purpose Input/Output Electrical Data/Timing

6.12.3.1 GPIO - Output Timing

Table 6-44. General-Purpose Output Switching Characteristics

over recommended operating conditions (unless otherwise noted)

PARAMETER

MIN

MAX

13⁽¹⁾

15

UNIT

ns

t_r(GPO)

t_f(GPO)

t_fGPO

Rise time, GPIO switching low to high

Fall time, GPIO switching high to low

Toggling frequency

All GPIOs

ns

MHz

(1) Rise time and fall time vary with electrical loading on I/O pins. Values given in Table 6-44 are applicable for a 40-pF load on I/O pins.

GPIO

t

r(GPO)

t

f(GPO)

Figure 6-31. General-Purpose Output Timing

Peripheral Information and Timings

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6.12.3.2 GPIO - Input Timing

Table 6-45. General-Purpose Input Timing Requirements

MIN

1t_c(SCO)

MAX

UNIT

cycles

QUALPRD = 0

t_w(SP)

Sampling period

QUALPRD ≠ 0

2t_c(SCO)* QUALPRD

t_w(SP)* (n⁽¹⁾– 1)

2t_c(SCO)

t_w(IQSW)

Input qualifier sampling window

Pulse duration, GPIO low/high

Synchronous mode

With input qualifier

(2)

t_w(GPI)

t_w(IQSW)+ t_w(SP)+ 1t_c(SCO)

(1) "n" represents the number of qualification samples as defined by GPxQSELn register.

(2) For t_w(GPI), pulse width is measured from V_ILto V_ILfor an active low signal and V_IHto V_IHfor an active high signal.

(A)

GPIO Signal

GPxQSELn = 1,0 (6 samples)

1

0

1

0

1

t_w(SP)

Sampling Period determined

by GPxCTRL[QUALPRD]^(B)

t_w(IQSW)

[(SYSCLKOUT cycle * 2 * QUALPRD) * 5^(C)

]

Sampling Window

SYSCLKOUT

QUALPRD = 1

(SYSCLKOUT/2)

(D)

Output From

Qualifier

A. This glitch will be ignored by the input qualifier. The QUALPRD bit field specifies the qualification sampling period.

The QUALPRD bit field value can vary from 00 to 0xFF. If QUALPRD = 00, then the sampling period is 1

SYSCLKOUT cycle. For any other value "n", the qualification sampling period in 2n SYSCLKOUT cycles (that is, at

every 2n SYSCLKOUT cycles, the GPIO pin will be sampled).

B. The qualification period selected via the GPxCTRL register applies to groups of 8 GPIO pins.

C. The qualification block can take either three or six samples. The GPxQSELn Register selects which sample mode is

used.

D. In the example shown, for the qualifier to detect the change, the input should be stable for 10 SYSCLKOUT cycles or

greater. In other words, the inputs should be stable for (5 x QUALPRD x 2) SYSCLKOUT cycles. This condition would

ensure 5 sampling periods for detection to occur. Since external signals are driven asynchronously, an 13-

SYSCLKOUT-wide pulse ensures reliable recognition.

Figure 6-32. Sampling Mode

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6.12.3.3 Sampling Window Width for Input Signals

The following section summarizes the sampling window width for input signals for various input qualifier

configurations.

Sampling frequency denotes how often a signal is sampled with respect to SYSCLKOUT.

Sampling frequency = SYSCLKOUT/(2 * QUALPRD), if QUALPRD ≠ 0

Sampling frequency = SYSCLKOUT, if QUALPRD = 0

Sampling period = SYSCLKOUT cycle x 2 x QUALPRD, if QUALPRD ≠ 0

In the above equations, SYSCLKOUT cycle indicates the time period of SYSCLKOUT.

Sampling period = SYSCLKOUT cycle, if QUALPRD = 0

In a given sampling window, either 3 or 6 samples of the input signal are taken to determine the validity of

the signal. The number of samples is determined by the value written to GPxQSELn register.

Case 1:

Qualification using 3 samples

Sampling window width = (SYSCLKOUT cycle x 2 x QUALPRD) x 2, if QUALPRD ≠ 0

Sampling window width = (SYSCLKOUT cycle) x 2, if QUALPRD = 0

Case 2:

Qualification using 6 samples

Sampling window width = (SYSCLKOUT cycle x 2 x QUALPRD) x 5, if QUALPRD ≠ 0

Sampling window width = (SYSCLKOUT cycle) x 5, if QUALPRD = 0

SYSCLK

GPIOxn

t

w(GPI)

Figure 6-33. General-Purpose Input Timing

V_DDIO

> 1 MS

2 pF

V_SS

Figure 6-34. Input Resistance Model for a GPIO Pin With an Internal Pull-up

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6.12.3.4 Low-Power Mode Wakeup Timing

Table 6-46 shows the timing requirements, Table 6-47 shows the switching characteristics, and Figure 6-

35 shows the timing diagram for IDLE mode.

Table 6-46. IDLE Mode Timing Requirements⁽¹⁾

MIN

2t_c(SCO)

MAX

UNIT

Without input qualifier

With input qualifier

t_w(WAKE-INT)

Pulse duration, external wake-up signal

cycles

5t_c(SCO)+ t_w(IQSW)

(1) For an explanation of the input qualifier parameters, see Table 6-45.

Table 6-47. IDLE Mode Switching Characteristics⁽¹⁾

over recommended operating conditions (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

MAX

UNIT

cycles

(2)

Delay time, external wake signal to program execution resume

Without input qualifier

With input qualifier

Without input qualifier

With input qualifier

Without input qualifier

With input qualifier

20t_c(SCO)

•

Wake-up from Flash

Flash module in active state

–

20t_c(SCO)+ t_w(IQSW)

1050t_c(SCO)

t_d(WAKE-IDLE)

cycles

Wake-up from Flash

Flash module in sleep state

–

1050t_c(SCO)+ t_w(IQSW)

20t_c(SCO)

Wake-up from SARAM

20t_c(SCO)+ t_w(IQSW)

(1) For an explanation of the input qualifier parameters, see Table 6-45.

(2) This delay time is the time taken to begin execution of the instruction that immediately follows the IDLE instruction. execution of an ISR

(triggered by the wake-up) signal involves additional latency.

t

d(WAKE−IDLE)

Address/Data

(internal)

XCLKOUT

t

w(WAKE−INT)

WAKE INT^(A)(B)

A. WAKE INT can be any enabled interrupt, WDINT or XRS. After the IDLE instruction is executed, a delay of 5

OSCCLK cycles (minimum) is needed before the wake-up signal could be asserted.

B. From the time the IDLE instruction is executed to place the device into low-power mode (LPM), wakeup should not be

initiated until at least 4 OSCCLK cycles have elapsed.

Figure 6-35. IDLE Entry and Exit Timing

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Table 6-48. STANDBY Mode Timing Requirements

MIN

3t_c(OSCCLK)

MAX

UNIT

Without input qualification

With input qualification⁽¹⁾

Pulse duration, external

wake-up signal

t_w(WAKE-INT)

cycles

(2 + QUALSTDBY) * t_c(OSCCLK)

(1) QUALSTDBY is a 6-bit field in the LPMCR0 register.

Table 6-49. STANDBY Mode Switching Characteristics

over recommended operating conditions (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

MAX

UNIT

Delay time, IDLE instruction

executed to XCLKOUT low

t_d(IDLE-XCOL)

32t_c(SCO)

45t_c(SCO)

cycles

Delay time, external wake signal to program execution

resume⁽¹⁾

cycles

Without input qualifier

100t_c(SCO)

•

Wake up from flash

–

Flash module in active state With input qualifier

100t_c(SCO)+ t_w(WAKE-INT)

1125t_c(SCO)

t_d(WAKE-STBY)

Without input qualifier

•

Wake up from flash

cycles

–

Flash module in sleep state With input qualifier

1125t_c(SCO)+ t_w(WAKE-INT)

100t_c(SCO)

Without input qualifier

•

Wake up from SARAM

With input qualifier

100t_c(SCO)+ t_w(WAKE-INT)

(1) This delay time is the time taken to begin execution of the instruction that immediately follows the IDLE instruction. execution of an ISR

(triggered by the wake up signal) involves additional latency.

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(C)

(F)

(A)

(B)

(D)(E)

(G)

Normal Execution

Device

Status

STANDBY

Flushing Pipeline

Wake-up

Signal^(H)

t

w(WAKE-INT)

t

d(WAKE-STBY)

X1/X2 or

XCLKIN

XCLKOUT

t

d(IDLE−XCOL)

A. IDLE instruction is executed to put the device into STANDBY mode.

B. The PLL block responds to the STANDBY signal. SYSCLKOUT is held for the number of cycles indicated below

before being turned off:

•

16 cycles, when DIVSEL = 00 or 01

32 cycles, when DIVSEL = 10

64 cycles, when DIVSEL = 11

This delay enables the CPU pipeline and any other pending operations to flush properly.

C. Clock to the peripherals are turned off. However, the PLL and watchdog are not shut down. The device is now in

STANDBY mode. After the IDLE instruction is executed, a delay of 5 OSCCLK cycles (minimum) is needed before the

wake-up signal could be asserted.

D. The external wake-up signal is driven active.

E. The wake-up signal fed to a GPIO pin to wake up the device must meet the minimum pulse width requirement.

Furthermore, this signal must be free of glitches. If a noisy signal is fed to a GPIO pin, the wake-up behavior of the

device will not be deterministic and the device may not exit low-power mode for subsequent wake-up pulses.

F. After a latency period, the STANDBY mode is exited.

G. Normal execution resumes. The device will respond to the interrupt (if enabled).

H. From the time the IDLE instruction is executed to place the device into low-power mode (LPM), wakeup should not be

initiated until at least 4 OSCCLK cycles have elapsed.

Figure 6-36. STANDBY Entry and Exit Timing Diagram

Table 6-50. HALT Mode Timing Requirements

MIN

t_oscst+ 2t_c(OSCCLK)

t_oscst+ 8t_c(OSCCLK)

MAX

UNIT

cycles

t_w(WAKE-GPIO)

t_w(WAKE-XRS)

Pulse duration, GPIO wake-up signal

Pulse duration, XRS wakeup signal

Table 6-51. HALT Mode Switching Characteristics

over recommended operating conditions (unless otherwise noted)

PARAMETER

MIN

MAX

UNIT

cycles

ms

t_d(IDLE-XCOL)

t_p

Delay time, IDLE instruction executed to XCLKOUT low

PLL lock-up time

32t_c(SCO)

45t_c(SCO)

1

Delay time, PLL lock to program execution resume

1125t_c(SCO)

35t_c(SCO)

cycles

•

Wake up from flash

Flash module in sleep state

t_d(WAKE-HALT)

–

Wake up from SARAM

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(C)

(F)

(A)

(H)

(B)

(G)

(D)(E)

Device

Status

HALT

Flushing Pipeline

PLL Lock-up Time

Normal

Execution

Wake-up Latency

GPIOn^(I)

t

)

d(WAKE−HALT

t

w(WAKE-GPIO)

t_p

X1/X2 or

XCLKIN

Oscillator Start-up Time

XCLKOUT

t

d(IDLE−XCOL)

A. IDLE instruction is executed to put the device into HALT mode.

B. The PLL block responds to the HALT signal. SYSCLKOUT is held for the number of cycles indicated below before

oscillator is turned off and the CLKIN to the core is stopped:

•

16 cycles, when DIVSEL = 00 or 01

32 cycles, when DIVSEL = 10

64 cycles, when DIVSEL = 11

This delay enables the CPU pipeline and any other pending operations to flush properly.

C. Clocks to the peripherals are turned off and the PLL is shut down. If a quartz crystal or ceramic resonator is used as

the clock source, the internal oscillator is shut down as well. The device is now in HALT mode and consumes

absolute minimum power. It is possible to keep the zero-pin internal oscillators (INTOSC1 and INTOSC2) and the

watchdog alive in HALT mode. Keeping INTOSC1, INTOSC2, and the watchdog alive in HALT mode is done by

writing to the appropriate bits in the CLKCTL register. After the IDLE instruction is executed, a delay of 5 OSCCLK

cycles (minimum) is needed before the wake-up signal could be asserted.

D. When the GPIOn pin (used to bring the device out of HALT) is driven low, the oscillator is turned on and the oscillator

wake-up sequence is initiated. The GPIO pin should be driven high only after the oscillator has stabilized, which

enables the provision of a clean clock signal during the PLL lock sequence. Since the falling edge of the GPIO pin

asynchronously begins the wakeup procedure, care should be taken to maintain a low noise environment prior to

entering and during HALT mode.

E. The wake-up signal fed to a GPIO pin to wake up the device must meet the minimum pulse width requirement.

Furthermore, this signal must be free of glitches. If a noisy signal is fed to a GPIO pin, the wake-up behavior of the

device will not be deterministic and the device may not exit low-power mode for subsequent wake-up pulses.

F. Once the oscillator has stabilized, the PLL lock sequence is initiated, which takes 1 ms.

G. When CLKIN to the core is enabled, the device will respond to the interrupt (if enabled), after a latency. The HALT

mode is now exited.

H. Normal operation resumes.

I.

From the time the IDLE instruction is executed to place the device into low-power mode (LPM), wakeup should not be

initiated until at least 4 OSCCLK cycles have elapsed.

Figure 6-37. HALT Wake-Up Using GPIOn

Peripheral Information and Timings

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7 Device and Documentation Support

7.1 Device Support

7.1.1 Development Support

Texas Instruments (TI) offers an extensive line of development tools for the C28x™ generation of MCUs,

including tools to evaluate the performance of the processors, generate code, develop algorithm

implementations, and fully integrate and debug software and hardware modules.

The following products support development of 2805x-based applications:

Software Development Tools

•

Code Composer Studio™ Integrated Development Environment (IDE)

–

C/C++ Compiler

Code generation tools

Assembler/Linker

Cycle Accurate Simulator

•

Application algorithms

Sample applications code

Hardware Development Tools

•

Development and evaluation boards

JTAG-based emulators - XDS510™ class, XDS560™ emulator, XDS100

Flash programming tools

Power supply

Documentation and cables

For a complete listing of development-support tools for the processor platform, visit the Texas Instruments

website at www.ti.com. For information on pricing and availability, contact the nearest TI field sales office

or authorized distributor.

7.1.2 Device and Development Support Tool Nomenclature

To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all

TMS320™ MCU devices and support tools. Each TMS320™ MCU commercial family member has one of

three prefixes: TMX, TMP, or TMS (for example, TMX320F28055). Texas Instruments recommends two of

three possible prefix designators for its support tools: TMDX and TMDS. These prefixes represent

evolutionary stages of product development from engineering prototypes (with TMX for devices and TMDX

for tools) through fully qualified production devices and tools (with TMS for devices and TMDS for tools).

Device development evolutionary flow:

TMX

TMP

TMS

Experimental device that is not necessarily representative of the final device's electrical

specifications

Final silicon die that conforms to the device's electrical specifications but has not

completed quality and reliability verification

Fully qualified production device

Support tool development evolutionary flow:

TMDX Development-support product that has not yet completed Texas Instruments internal

qualification testing

TMDS Fully qualified development-support product

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TMX and TMP devices and TMDX development-support tools are shipped against the following

disclaimer:

"Developmental product is intended for internal evaluation purposes."

TMS devices and TMDS development-support tools have been characterized fully, and the quality and

reliability of the device have been demonstrated fully. TI's standard warranty applies.

Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard

production devices. Texas Instruments recommends that these devices not be used in any production

system because their expected end-use failure rate still is undefined. Only qualified production devices are

to be used.

TI device nomenclature also includes a suffix with the device family name. This suffix indicates the

package type (for example, PN) and temperature range (for example, T). Figure 7-1 provides a legend for

reading the complete device name for any family member.

For device part numbers and further ordering information, see the TI website (www.ti.com) or contact your

TI sales representative.

For additional description of the device nomenclature markings on the die, see the TMS320F28055,

TMS320F28054, TMS320F28053, TMS320F28052, TMS320F28051, TMS320F28050 Piccolo MCU

Silicon Errata (literature number SPRZ362).

TMX

320

F

28055 PN

T

PREFIX

TEMPERATURE RANGE

experimental device

prototype device

qualified device

TMX =

TMP =

TMS =

=

T

S

−40°C to 105°C

−40°C to 125°C

PACKAGE TYPE

80-Pin PN Low-Profile Quad Flatpack (LQFP)

DEVICE FAMILY

320 = TMS320 MCU Family

DEVICE

TECHNOLOGY

28055

28054

28053

28052

28051

28050

F = Flash

Figure 7-1. Device Nomenclature

Device and Documentation Support

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7.2 Documentation Support

Extensive documentation supports all of the TMS320™ MCU family generations of devices from product

announcement through applications development. The types of documentation available include: data

sheets and data manuals, with design specifications; and hardware and software applications.

The following documents can be downloaded from the TI website (www.ti.com):

Data Manual and Errata

SPRS797

TMS320F28055, TMS320F28054, TMS320F28053, TMS320F28052, TMS320F28051,

TMS320F28050 Piccolo Microcontrollers Data Manual contains the pinout, signal

descriptions, as well as electrical and timing specifications for the 2805x devices.

SPRZ362

TMS320F28055, TMS320F28054, TMS320F28053, TMS320F28052, TMS320F28051,

TMS320F28050 Piccolo MCU Silicon Errata describes known advisories on silicon and

provides workarounds.

Technical Reference Manual

SPRUHE5 TMS320x2805x Piccolo Technical Reference Manual details the integration, the

environment, the functional description, and the programming models for each peripheral

and subsystem in the 2805x microcontrollers.

CPU User's Guides

SPRU430

TMS320C28x CPU and Instruction Set Reference Guide describes the central processing

unit (CPU) and the assembly language instructions of the TMS320C28x fixed-point digital

signal processors (DSPs). This Reference Guide also describes emulation features available

on these DSPs.

Peripheral Guides

SPRU566 TMS320x28xx, 28xxx DSP Peripheral Reference Guide describes the peripheral reference

guides of the 28x digital signal processors (DSPs).

Tools Guides

SPRU513

TMS320C28x Assembly Language Tools v5.0.0 User's Guide describes the assembly

language tools (assembler and other tools used to develop assembly language code),

assembler directives, macros, common object file format, and symbolic debugging directives

for the TMS320C28x device.

SPRU514

SPRU608

TMS320C28x Optimizing C/C++ Compiler v5.0.0 User's Guide describes the

TMS320C28x™ C/C++ compiler. This compiler accepts ANSI standard C/C++ source code

and produces TMS320 DSP assembly language source code for the TMS320C28x device.

TMS320C28x Instruction Set Simulator Technical Overview describes the simulator,

available within the Code Composer Studio for TMS320C2000 IDE, that simulates the

instruction set of the C28x™ core.

7.3 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the

respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views;

see TI's Terms of Use.

TI E2E Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration

among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and

help solve problems with fellow engineers.

TI Embedded Processors Wiki Texas Instruments Embedded Processors Wiki. Established to help

developers get started with Embedded Processors from Texas Instruments and to foster

innovation and growth of general knowledge about the hardware and software surrounding

these devices.

138

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8 Mechanical Packaging and Orderable Information

8.1 Thermal Data for Package

Table 8-1 shows the thermal data. See Section 2.9 for more information on thermal design considerations.

Table 8-1. Thermal Model 80-Pin PN Results

AIR FLOW

PARAMETER

0 lfm

49.9

0.8

150 lfm

38.3

250 lfm

36.7

500 lfm

34.4

θ_JA[°C/W] High k PCB

Ψ_JT[°C/W]

Ψ_JB

1.18

1.34

1.62

21.6

14.2

21.9

20.7

20.5

20.1

θ_JC

θ_JB

8.2 Packaging Information

The following packaging information and addendum reflect the most current data available for the

designated devices. This data is subject to change without notice and without revision of this document.

Mechanical Packaging and Orderable Information

Submit Documentation Feedback

139

Product Folder Links: TMS320F28055 TMS320F28054 TMS320F28053 TMS320F28052 TMS320F28051

TMS320F28050

MECHANICAL DATA

MTQF010A – JANUARY 1995 – REVISED DECEMBER 1996

PN (S-PQFP-G80)

PLASTIC QUAD FLATPACK

0,27

0,17

0,50

60

M

0,08

41

61

40

0,13 NOM

80

21

1

20

Gage Plane

9,50 TYP

0,25

12,20

SQ

11,80

0,05 MIN

0°–7°

14,20

SQ

13,80

0,75

0,45

1,45

1,35

Seating Plane

0,08

1,60 MAX

4040135 /B 11/96

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Falls within JEDEC MS-026

1

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型号：	TMS320F28053PNQ
厂家：	TEXAS INSTRUMENTS
描述：	Piccolo Microcontrollers Piccolo微处理器微处理器微控制器
文件：	总143页 (文件大小：1522K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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