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TMS320LC203PZA-40 [TI]

IC,DSP,16-BIT,CMOS,QFP,100PIN,PLASTIC;
TMS320LC203PZA-40
型号： TMS320LC203PZA-40
厂家： TEXAS INSTRUMENTS    TEXAS INSTRUMENTS
描述：

IC,DSP,16-BIT,CMOS,QFP,100PIN,PLASTIC
文件： 总34页 (文件大小：127K)
中文：  中文翻译
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Feature Phone based on  
TMS320LC203  
Literature Number: BPRA050  
Texas Instruments Europe  
March 1997  
IMPORTANT NOTICE  
Texas Instruments (TI) reserves the right to make changes to its products or to discontinue any semiconductor  
product or service without notice, and advises its customers to obtain the latest version of relevant information to  
verify, before placing orders, that the information being relied on is current.  
TI warrants performance of its semiconductor products and related software to the specifications applicable at the  
time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the  
extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not  
necessarily performed, except those mandated by government requirements.  
Certain application using semiconductor products may involve potential risks of death, personal injury, or severe  
property or environmental damage (“Critical Applications”).  
TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR WARRANTED TO BE  
SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL  
APPLICATIONS.  
Inclusion of TI products in such applications is understood to be fully at the risk of the customer. Use of TI products in  
such applications requires the written approval of an appropriate TI officer. Questions concerning potential risk  
applications should be directed to TI through a local SC sales office.  
In order to minimize risks associated with the customer’s applications, adequate design and operating safeguards  
should be provided by the customer to minimize inherent or procedural hazards.  
TI assumes no liability for applications assistance, customer product design, software performance, or infringement of  
patents or services described herein. Nor does TI warrant or represent that any license, either express or implied, is  
granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating  
to any combination, machine, or process in which such semiconductor products or services might be or are used.  
Copyright © 1997, Texas Instruments Incorporated  
Contents  
Contents  
1. Introduction ..............................................................................................................1  
2. Hardware..................................................................................................................2  
2.1 System Overview ..........................................................................................2  
2.2 Connections to the Parallel Port....................................................................3  
2.3 On-Chip UART ..............................................................................................5  
2.4 Multiplexing the Serial Port............................................................................5  
2.5 Variable System Clock .................................................................................6  
3. Software: Initialization & Test.................................................................................7  
3.1 Communication between DSP and PC via RS232........................................7  
3.2 Serial Port and TLV320AC36........................................................................7  
3.3 Testing the external SRAM ...........................................................................7  
Appendix A. Source Code .....................................................................................11  
Appendix B. PAL Programming.............................................................................21  
Appendix C. Schematics .......................................................................................25  
Feature Phone based on TMS320LC203  
iii  
Contents  
List of Figures  
Figure 1: System Overview...............................................................................................2  
Figure 2: System Memory Map.........................................................................................4  
iv  
Literature Number: BPRA050  
Contents  
List of Tables  
Table 1: Status of memory select signals..........................................................................3  
Table 2: Variable frequency for CLKIN..............................................................................6  
Table 3: TMS320C203 clock options.................................................................................6  
Feature Phone based on TMS320LC203  
v
Contents  
vi  
Literature Number: BPRA050  
1. Introduction  
Feature Phone based on TMS320LC203  
ABSTRACT  
This application report describes a feature phone design based on the  
TMS320LC203. The LC203 is a 3V member of the TMS320C2xx DSP  
family combining low cost and low power consumption with a computing  
power of 20 MIPS. Three independent onchip ports, UART, Serial Port  
and Parallel Port, allow designing with minimal external logic saving cost,  
board space and assuring fast access times.  
This report discusses mainly the realization of an evaluation board for  
testing typical pay-phone algorithms such as signaling, speech  
processing and data transmission. Examples are given how to handle  
the different peripherals of the DSP regarding HW and SW issues. Basic  
initialization and test routines together with the board schematics  
complete this application description.  
1. Introduction  
In recent years, semiconductor manufacturers have succeeded in increasing the  
computing power of Digital Signal Processors up to 2 billion instructions per second.  
Such fast processing is not needed in every application.  
For feature phones, price per unit and power consumption are the most important  
criteria.  
The 3-V DSP TMS320LC203 satisfies both ( low power and low cost), while its  
computing power of 20 million instructions per second is more than sufficient for these  
types of applications.  
This report is based on an evaluation board developed for test and emulation of  
typical payphone algorithms such as signaling, speech processing and data  
transmission between the central office and the payphone.  
This paper will mainly discuss the realization of the hardware, giving examples of how  
to connect and initialize each port of the DSP. The schematics are included in the  
appendix.  
Chapter 3 gives a short description of the software that has been used for the testing  
and initialization of the DSP’s interfaces. The source code also is included in the  
appendix.  
Feature Phone based on TMS320LC203  
1
2. Hardware  
2. Hardware  
2.1 System Overview  
For any feature phone application, multiple interfaces to peripheral devices are  
needed. The TMS320C2xx family provides up to four totally independent ports.  
Therefore, even complex systems can be realized with a minimum of external logic -  
saving costs, board space and ensuring fast access times.  
The TMS320LC203 used in this design provides an on-chip UART for communication  
with a host processor, a 16-bit wide parallel port and a single synchronous serial port.  
The parallel port is used to interface external memory to the DSP. The serial port  
handles the data traffic between DSP and analog interfaces. In this application the  
serial port is multiplexed between the two CODECs necessary for the line and  
handset interfaces.  
The JTAG port provides direct access to the DSP and optimizes test and emulation  
capabilities of the system. In addition a seven-segment LED display gives the  
designer the opportunity to monitor the status of the DSP.  
ADDRESS  
External  
JTAG  
Program Memory  
TMS320LC303  
DATA  
64K x 16 SRAM  
DSP  
RS232  
4x  
IDT71V256SA  
TLV320AC36/37  
External  
VBAP  
Line Interface  
Data Memory  
M
U
X
64K x 16 SRAM  
TLV320AC36/37  
VBAP  
Handset Interface  
4x  
IDT71V256SA  
TIL311  
7 Segment LED  
I/O Space  
Global  
Data Memory  
32K x 8 EPROM  
1x  
Mx27L256  
Figure 1: System Overview  
2
Literature Number: BPRA050  
2. Hardware  
2.2 Connections to the Parallel Port  
The total space accessible from the DSP by the parallel port is divided in ‘Program’,  
‘Data’, ‘Global Data’ and ‘I/O’. With each access to external devices the ‘LC203  
selects one of these spaces by driving the appropriate memory select strobes (PS\,  
DS\, IS\ and BR\) low:  
Table 1: Status of memory select signals  
Enabled Space  
Program  
Data  
Global Data  
I/O  
PS\  
Low  
High  
High  
High  
DS\  
High  
Low  
Low  
High  
IS\  
BR\  
High  
High  
Low  
High  
High  
High  
High  
Low  
The address and data lines are shared by all external spaces.  
The four SRAM devices U12 to U15 (see Appendix C p.28) build the external  
program memory. PS\ combined with A15 gives the appropriate chip select signals for  
the upper (addresses 0x8000 to 0xffff) and lower (addresses 0x0000 to 0x7fff)  
memory banks.  
WE\ is connected to the write enable input of the SRAMs.  
The EPROM U16 is placed in the global data memory. It is accessed only during the  
boot load process. Once the program is transferred onto the faster SRAM in program  
space the GREG register will be changed to enable the full range of data memory.  
BR\ is connected to the chip enable of the EPROM.  
Because DS\ is low during global data accesses and data memory accesses, it is not  
possible to use DS\ alone as chip enable for the SRAMs providing the external Data  
memory (U8, U9, U10 and U11). Bus conflicts would occur during the access to the  
EPROM.  
Therefore, DS\ combined with BR\ and A15 constitute the chip select for data  
memory, A15 being the selection signal for upper and lower memory banks.  
The 7-segment LED display, U17, is the only external component in the IO space of  
the DSP. IS\ is connected directly to the strobe input of the LED.  
Feature Phone based on TMS320LC203  
3
2. Hardware  
Program  
Data  
Global Data  
I/O  
0x0000  
0x003F  
Interrupts  
(External)  
Memory mapped  
Registers and  
Reserved  
0x0040  
0x005F  
0x0060  
On-Chip  
DARAM B2  
0x007F  
0x0080  
Reserved  
0x00FF  
0x0100  
On-Chip DARAM  
B0 (CNF=0)  
Reserved (CNF=1)  
On-Chip DARAM  
B0’ (CNF=0)  
0x01FF  
0x0200  
0x02FF  
0x0300  
Reserved (CNF=1)  
External SRAM  
U12 and U13  
On-Chip  
DARAM B1  
LED  
0x03FF  
0x0400  
On-Chip  
DARAM B1  
0x04FF  
0x0500  
Reserved  
0x07FF  
0x0800  
External SRAM  
U8 and U9  
0x7FFF  
0x8000  
0xFDFF  
0xFE00  
On-Chip DARAM  
B0  
External SRAM  
U10 and U11  
External EPROM  
U16  
(CNF=1)  
External SRAM  
U14 and U15  
(CNF=0)  
On-Chip DARAM  
B0’  
(8 bit wide)  
0xFEFF  
0xFF00  
Memory mapped  
Registers and  
Reserved  
(CNF=1)  
External SRAM  
U14 and U15  
(CNF=0)  
0xFFFF  
Figure 2: System Memory Map  
4
Literature Number: BPRA050  
2. Hardware  
2.3 On-Chip UART  
The TMS320LC203 includes a complete UART on chip. This application uses only the  
TX and RX pin for a direct connection to a host via a RS232 interface. The handshake  
signals I/O0 to I/O4 are connected to a header for general purposes.  
2.4 Multiplexing the Serial Port  
Feature phone applications need two independent analog channels. One for the line  
interface and one for the handset. As the ‘C203 provides only one synchronous serial  
port it must be multiplexed between the two VBAPs (Voice Band Audio Processors).  
The master clock frequency for the VBAPs is generated by the binary ripple counter  
SN74HC4060 (U6, Appendix C, p.29). As this frequency defines the internal filters of  
the TLV320AC36/37 it must be exactly at 2.048MHz. This frequency is also used to  
clock the data in and out of the serial port. The frame sync pulse FSX for the transmit  
channel is generated by the DSP. The same pulse triggers the receive channel (FSR).  
The frame sync for the VBAPs is multiplexed with the XF output of the DSP. The PAL  
device, U18, combines FSX and XF with the following equations:  
For the line interface:  
FSL = FSX & XF  
For the handset:  
FSH = FSX & !XF  
The generated frame syncs trigger the receive and transmit operations of the serial  
port, at the same time toggling the selection of the VBAPs.  
FSX must provide the necessary 8kHz sampling frequency for the VBAPs. The QI  
(16kHz) of the binary counter (U6) is connected to the DSP via interrupt INT2\.  
Each time the DSP receives this interrupt it writes the next value to the transmit  
register and triggers the FSX pulse. If XF is toggled with every INT2 each VBAP  
receives the frame sync pulses with a frequency of 8kHz which ensures the proper  
operation of the devices.  
Due to the very efficient interrupt handling of the TMS320C203, the times between  
two frame sync pulses do not differ significantly, but it must be ensured that no  
interrupts with higher priority than INT2 occur while the VBAPs are active.  
Feature Phone based on TMS320LC203  
5
2. Hardware  
2.5 Variable System Clock  
The clock of the DSP is generated by a programmable oscillator. The inputs A, B and  
C ( See Appendix C, p.27) vary the output frequency on pin #2 as shown in table 2.  
Pin #1 always outputs the specified frequency of the device.  
Table 2: Variable frequency for CLKIN  
Inputs  
Outputs  
C
SW4  
B
SW3  
A
GND  
D
pin #2  
F
pin #1  
L
L
L
L
L
H
H
L
L
H
H
L
H
L
H
L
H
L
H
F/2  
F/4  
F/8  
F/16  
F/32  
F/64  
F/128  
F/256  
10MHz  
(5MHz)  
2.5MHz  
20MHz  
20MHz  
20MHz  
20MHz  
20MHz  
20MHz  
20MHz  
20MHz  
L
(1.25MHz)  
625kHz  
(312.5kHz)  
156.25kHz  
(78.125kHz)  
H
H
H
H
The pins DIV1 and DIV2 of the DSP specify the factor between the frequency on  
CLKIN and the DSP clock.  
Table 3: TMS320C203 clock options  
Parameter  
DIV2  
SW5  
DIV1  
SW6  
Internal divided by two with external crystal  
PLL multiply by one  
PLL multiply by two  
L
L
H
H
L
H
L
PLL multiply by four  
H
6
Literature Number: BPRA050  
3. Software: Initialization & Test  
3. Software: Initialization & Test  
The following chapter describes the programs for initialization and test routines written  
during the development of the board. The source code can be found in Appendix A of  
this report.  
3.1 Communication between DSP and PC via RS232  
Windows ‘Terminal’ software is used to establish communication between the DSP  
and the PC. The keyboard and monitor are used as input and output devices  
respectively . The DSP transfers its data to the PC via the RS232 interface driven by  
the on-chip UART.  
The exchange of data between the DSP and the PC is controlled by polling the DR  
and THRE bits of the IOSR registers of the on-chip UART. When the DR bit is set, it  
indicates that a character has been received. Similarly, when the THRE bit is set, it  
indicates that the transmit register is empty ( i.e. a character has been transmitted).  
When receiving data, the function ISRXREADY() is called, waiting until a character is  
received before attempting to read the ASDTR register in the UART.  
When transmitting data, the function ISTXREADY() is called, and waits until ASDTR  
register is empty before attempting to write to it.  
3.2 Serial Port and TLV320AC36  
The two TLV320AC36 are connected to the DSP via the serial port. The XF signal is  
used to switch between the two CODECS. Only the received serial port interrupt is  
used since the transmit and receive functions of the serial port are synchronized by  
tying together the FSX and FSR pins.  
This paragraph describes the operation of the serial port in our test program. An  
external interrupt, INT2, is received every 62.5µs (16kHz). The interrupt service  
routine for INT2 turns on one of the VBAPs by toggling the XF pin and outputs an old  
sample stored in BUFFER. Since the transmit and receive blocks of the serial port are  
synchronized, a new sample will arrive at the serial port generating a receive interrupt.  
The interrupt service routine will read the new sample from the serial port and store it  
in BUFFER.  
To perform the serial port test, an audio source may be connected to ANALOG IN. If  
speakers are connected to ANALOG OUT they should reproduce the same waveform  
as that applied to ANALOG IN.  
3.3 Testing the external SRAM  
In this test program the DSP reads and writes to external memory. Each stored value  
is checked for errors and any faults encountered increment the error counters.  
The program starts by initializing a data word to 0xffffh. This data memory is copied  
into program memory, and immediately copied back from program to data memory.  
This procedure is repeated for all the external program and data SRAMS.  
Next, the program starts a different test. The DSP executes 8 consecutive writes to  
the external data space. The data written alternates between 0x5555 and 0xaaaa with  
Feature Phone based on TMS320LC203  
7
3. Software: Initialization & Test  
each cycle. The DSP reads out this data and stores the sum of the eight values in the  
accumulator to check it. This procedure is repeated until the DSP reaches the end of  
the external memory space. The program executes the same routine with 0x0000 and  
0xffff as values to be written.  
8
Literature Number: BPRA050  
References  
References  
1. Voice-Band -Audio -Processor Application Report, G. Davis and R.  
MacDonald, Texas Instruments 1994  
2. TLV320AC36/37 3V Voice-Band Audio Processor, Texas Instruments 1994,  
SLWS006  
3. TMS320C2xx data sheet, Texas Instruments 1995, SPRS025  
4. TMS320C2xx User’s Guide, Texas Instruments 1995, SPRU127B  
5. Power Supply Circuits, Texas Instruments 1996, SLVD002  
6. Digital Design Workshop, E. Haseloff and P. Forstner, Texas Instruments 1995  
Feature Phone based on TMS320LC203  
9
3. Software: Initialization & Test  
10  
Literature Number: BPRA050  
Appendix A. Source Code  
Appendix A. Source Code  
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;  
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Memory Test for LC203 Board  
File Name: memtst.asm  
;
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Description: This program is used to check the correct  
operation of the SRAMs in the board. Different values  
are written to Data memory, then transferred to Program  
memory and finally checked to see if any errors have  
occurred. The ER_COUNT variable holds the number  
of times a faulty memory cell has been found.  
The file Make.bat will assemble and link memtst.asm  
creating the memtst.out  
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;  
IMR  
.set  
.set  
.set  
.set  
4h  
; Int Mask register  
GREG  
IFR  
5h  
; Global Mask register  
; Int Flag register  
6h  
WSGR  
0fffch  
0800h  
0600h  
0f000h  
; Wait State Generator reg  
; External data address  
; External prog address  
; memory size to be tested  
Ex_dat .set  
Ex_prg .set  
memsize .set  
TEMP_VAL .usect  
ER_COUNT .set  
TEST_VAL .set  
"temp",3  
; Temporary value  
TEMP_VAL+1  
TEMP_VAL+2  
TEMP_VAL+3  
; Error counter  
; test value  
; current program space address  
ADDR  
.set  
tstdat .usect "test_d",memsize  
tstprg .usect "test_p",memsize  
.text  
NOP  
ldp  
splk  
lst  
splk  
lst  
splk  
splk  
splk  
out  
splk  
splk  
OUT  
INIT  
#0  
;
#2E00h,TEMP_VAL  
#0,TEMP_VAL  
#21FCh,TEMP_VAL  
#1,TEMP_VAL  
#0,IMR  
; ARP=1,OVM=1,INTM=1,DP=0  
; Init ST0  
; ARB=1,CNF=0,SXM=0,XF=1,PM=0  
; Init ST1  
; No Interrupts selected  
; Disable Global Memory  
; Init WSGR  
; 7 WS I/0, 0 WS Data, 0 WS Prog  
; Initial Test Value ffffh  
; Initialised number of errors  
; write error counter to LED  
#0,GREG  
#0E00h,TEMP_VAL  
TEMP_VAL,WSGR  
#0ffffh,TEST_VAL  
#0,ER_COUNT  
ER_COUNT, 0001h  
Feature Phone based on TMS320LC203  
11  
Appendix A. Source Code  
START  
LOOP  
lar  
ar3,#memsize  
ar0  
ar0,#Ex_dat  
ar1,#Ex_prg  
TEST_VAL  
*
; Initialised loop counter  
; ar0 active pointer  
larp  
lar  
; ar0=Start External Data memory  
; ar1=Start External Prog memory  
; load Acc with test value  
; store value in Data mem  
lar  
lacl  
sacl  
sar  
ar1,TEMP_VAL  
TEMP_VAL  
; transfers  
*
; load ar1 into TEMP_VAL  
; store TEMP_VAL into acc to perform  
lacl  
tblw  
tblr  
lacl  
sub  
mar  
bcnd  
; transfer from data to prog  
; tranfer from prog to data  
; Load Acc with test value  
; Test the prog memory  
*
TEST_VAL  
*+,ar1  
*+,ar0  
COUNT,NEQ  
; If error occur update error count  
CONT  
mar  
banz  
NOP  
NOP  
*,ar3  
LOOP,ar0  
; make counter active  
; check if counter is zero  
;Start test for 8 consecutive reads and 8 consecutive writes  
LACC  
SACH  
LAR  
#memsize, 13  
; load memorisize devided by 8  
; in AR3 as loop counter  
TEMP_VAL  
AR3, TEMP_VAL  
LAR  
AR4, #Ex_dat  
; load start address of data memory  
; activate AR4  
; load 0x5555aaaa in accumulator  
MAR  
*,AR4  
CONS1: LACC  
SACL  
LACC  
OR  
#05555h  
TEMP_VAL  
TEMP_VAL, 16  
#0aaaah  
SACL  
SACH  
SACL  
SACH  
SACL  
SACH  
SACL  
SACH  
SAR  
*+  
; write 0xaaaa  
*+  
; write 0x5555  
*+  
; write 0xaaaa  
*+  
; write 0x5555  
*+  
; write 0xaaaa  
*+  
; write 0x5555  
*+  
; write 0xaaaa  
*+  
; write 0x5555  
AR4,ADDR  
; reset AR4 to the address of first  
; value written in this loop  
LACL  
SUB  
ADDR  
#8  
SACL  
LAR  
ADDR  
AR4, ADDR  
LACC  
ADD  
*+  
; read and accumulate all values  
; written before  
*+  
ADD  
*+  
ADD  
*+  
ADD  
*+  
ADD  
*+  
ADD  
*+  
ADD  
*+  
ADD  
#4  
; the sum + 4 should give 0x40000  
; check is lower 16bit are zero  
; if not increment error counter  
; decrement loop counter and repeat  
; the test for the whole data memory  
AND  
#0ffffh  
ERR_CONS1, NEQ  
*, AR3  
BCND  
C1:  
MAR  
BANZ  
CONS1,*-,AR4  
LACC  
SACH  
LAR  
#memsize, 13  
TEMP_VAL  
; same as above with 0xffff and  
; 0x0000 as values to be written  
AR3, TEMP_VAL  
AR4, #Ex_dat  
*,AR4  
LAR  
MAR  
CONS2: LACC  
SACL  
#0ffffh  
TEMP_VAL  
LACC  
TEMP_VAL, 16  
12  
Literature Number: BPRA050  
Appendix A. Source Code  
SACL  
SACH  
SACL  
SACH  
SACL  
SACH  
SACL  
SACH  
SAR  
*+  
*+  
*+  
*+  
*+  
*+  
*+  
*+  
AR4,ADDR  
LACL  
SUB  
ADDR  
#8  
SACL  
LAR  
ADDR  
AR4, ADDR  
LACC  
ADD  
*+  
*+  
ADD  
*+  
ADD  
*+  
ADD  
*+  
ADD  
*+  
ADD  
*+  
ADD  
*+  
ADD  
#4  
AND  
#0ffffh  
ERR_CONS2, NEQ  
*, AR3  
BCND  
MAR  
C2:  
BANZ  
B
CONS2,*-,AR4  
START  
; repeat the whole test  
ERR_CONS1 lacl  
ER_COUNT  
; Load counter in acc  
; add 1 to acc  
add  
#1  
sacl  
ER_COUNT  
; store back in counter  
; write error counter to LED  
OUT  
ER_COUNT, 0001h  
B
C1  
ERR_CONS2 lacl  
ER_COUNT  
; Load counter in acc  
; add 1 to acc  
; store back in counter  
; write error counter to LED  
add  
sacl  
OUT  
B
#1  
ER_COUNT  
ER_COUNT, 0001h  
C2  
COUNT  
lacl  
add  
sacl  
OUT  
b
ER_COUNT  
#1  
ER_COUNT  
ER_COUNT, 0001h  
CONT  
; Load counter in acc  
; add 1 to acc  
; store back in counter  
; write error counter to LED  
.sect  
b
"vectors"  
INIT  
Feature Phone based on TMS320LC203  
13  
Appendix A. Source Code  
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;  
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Serial Port Test for LC203 Board  
File: sp.asm  
Description: This file is used to check the correct  
operation between the on-chip serial port and the two  
VBAPS. An Audio source is connected to the ANALOG IN;  
and the speakers should be connected to ANALOG OUT  
The serial port will take samples from the ANALOG IN  
;
;
and output the same sample to the ANALOG OUT.  
;
The speaker output should be the same as that applied to  
the input.  
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;
The multiplexing between the two VBAPS is achieved as  
follows:  
INT2 provides a 16kHz interrupt which toggles  
the XF flag. The XF flag selects one of the VBAPS  
thereby giving an 8KhkHz sampling rate to each VBAP  
A file called MAKE.BAT will assemble, and link SP.ASM  
producing SP.OUT  
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;  
IMR  
.set  
.set  
.set  
.set  
.set  
4h  
; Int Mask register  
; Global Mask register  
; Int Flag register  
;ICR reg  
; Synch Serial Port  
; Transmit/Receive Reg  
; Synch Serial Port Control Reg  
; Wait State Generator reg  
GREG  
IFR  
5h  
6h  
0ffech  
0fff0h  
ICR  
SDTR  
SSPCR  
WSGR  
.set  
.set  
0fff1h  
0fffch  
TEMP_VAL .usect  
RX_READY .set  
"temp",3  
TEMP_VAL+1  
TEMP_VAL+1  
; Temporary value  
; Receive Flag  
BUFFER  
.set  
.text  
NOP  
INIT  
ldp  
#0  
splk  
lst  
#2E00h,TEMP_VAL  
#0,TEMP_VAL  
#21FCh,TEMP_VAL  
#1,TEMP_VAL  
#000Ah ,IMR  
; ARP=1,OVM=1,INTM=1,DP=0  
; Init ST0  
; ARB=1,CNF=0,SXM=0,XF=1,PM=0  
; Init ST1  
splk  
lst  
splk  
; INT2/INT3 and Serial Port Receive  
; Interrupt selected  
; INT2 selected  
splk  
out  
splk  
splk  
out  
splk  
out  
splk  
out  
lacl  
sacl  
setc  
splk  
clrc  
#0001h,TEMP_VAL  
TEMP_VAL,ICR  
#0,GREG  
#0E00h,TEMP_VAL  
TEMP_VAL,WSGR  
#000ah,TEMP_VAL  
TEMP_VAL,SSPCR  
#003ah,TEMP_VAL  
TEMP_VAL,SSPCR  
#0  
RX_READY  
XF  
#0000h,TEMP_VAL  
INTM  
; Init ICR reg  
; Disable Global Memory  
; Init WSGR  
; 7 WS I/0, 0 WS Data, 0 WS Prog  
; Loop Back Mode Selected  
; Init SSPCR  
; Boot up SSPCR  
; Init SSPCR  
; Init RX_READY flag  
; Selects the VBAP  
; TEMP_VAL = 0  
; Enable interrupts  
14  
Literature Number: BPRA050  
Appendix A. Source Code  
START  
INT2  
b START  
sst  
#1,TEMP_VAL  
TEMP_VAL  
#0010h  
TEMP_VAL  
#1,TEMP_VAL  
TEMP_VAL  
#1  
OUTPUT,EQ  
TEMP_VAL  
#1  
TEMP_VAL  
INTM  
;Load ST1 in TEMP_VAL  
lacl  
xor  
;Load ACC with ST1  
;Toggle XF bit from ST1  
sacl  
lst  
;Restore ST1  
;Load int2 interrupt counter  
;Check if two int2 have occurred  
;lacl  
;sub  
;bcnd  
;lacl  
;add  
;sacl  
;clrc  
;ret  
; add one to counter  
; store back  
;enable interrupts  
OUTPUT out  
BUFFER,SDTR  
#0000h,TEMP_VAL  
INTM  
; Output old data value  
; zero the counter  
; Enable interrupts  
; return  
splk  
clrc  
ret  
RECVINTin  
BUFFER,SDTR  
INTM  
; Input new data value  
; Enable interrupts  
; return  
clrc  
ret  
.sect  
"vectors"  
INIT  
rs  
b
b
b
b
b
b
; reset  
int1  
int2_3  
tint  
rint  
xint  
int1  
; int1/hold  
INT2  
tint  
; int2  
; timer  
RECVINT  
xint  
; Synch receive  
; Synch transmit  
; Asynch Tran/Rec  
; reserved interrupt for emulator  
txrxintb  
txrxint  
.space 2*16  
int8  
int9  
b
b
b
b
b
b
b
b
b
b
b
int8  
int9  
int10  
int11  
int12  
int13  
int14  
int15  
int16  
trap  
int10  
int11  
int12  
int13  
int14  
int15  
int16  
trap  
nmi  
nmi  
;
;
None maskable interrupt  
reserved interrupt for emulator  
.space 2*16  
int20  
int21  
int22  
int23  
int24  
int25  
int26  
int27  
int28  
int29  
int30  
int31  
b
b
b
b
b
b
b
b
b
b
b
b
int20  
int21  
int22  
int23  
int24  
int25  
int26  
int27  
int28  
int29  
int30  
int31  
Feature Phone based on TMS320LC203  
15  
Appendix A. Source Code  
/******************************************************************/  
/*  
/*  
/*  
/*  
/*  
/*  
/*  
/*  
/*  
/*  
/*  
/*  
/*  
/*  
/*  
/*  
/*  
/*  
/*  
/*  
/*  
/*  
/*  
LC203 UART TEST  
*/  
*/  
*/  
*/  
File Names: uart.c,uart1.h,initp.asm  
Description: This program is used to check the correct  
operation of the on-chip UART. A Windows based  
application is needed to establish communication  
between the PC and the UART. The executable  
file UART.TRM is used in this case. From the  
*/  
*/  
*/  
*/  
*/  
*/  
*/  
*/  
*/  
*/  
*/  
*/  
*/  
*/  
*/  
*/  
*/  
*/  
*/  
communications menu choose, 9600 Baud Rate, 1 Stop bit,  
,no parity check, 8 bit data, no flow control.  
Connect an RS-232 cable from the PC to the Board.  
Start the emulator with UART.OUT. Once UART.OUT is  
running on the DSP, click on the Windows application  
UART.TRM.  
The following message should appear on the screen:  
*** LC203 Test Platform ***  
Type a character  
The char should be displayed in the screen  
To stop the test press (s)  
A file called MAKE.BAT will compile, assemble, and link  
the necessary files creating the UART.OUT.  
/******************************************************************/  
#include "uart1.h"  
void  
{
main(void)  
#define max 100  
char C, COMMAND;  
char s[max];  
int i,n;  
int DONE = 0;  
void INIT(void);  
/* Initialization routine  
*/  
INIT();  
sendinteger (0xa);  
sendinteger (0xd);  
sendinteger (0xa);  
sendinteger (0xd);  
/* Set cursor begining of current line  
/* Set cursor to next line  
*/  
*/  
*/  
*/  
/* Set cursor begining of current line  
/* Set cursor to next line  
sendstring(" *** LC203 Test Platform ***",27);  
sendinteger (0xa);  
sendinteger (0xd);  
sendinteger (0xa);  
sendinteger (0xd);  
/* Set cursor begining of current line  
*/  
*/  
*/  
*/  
/* Set cursor to next line  
/* Set cursor begining of current line  
/* Set cursor to next line  
sendstring(" Type a character ",18);  
sendinteger (0xa);  
sendinteger (0xd);  
/* Set cursor begining of current line  
/* Set cursor to next line  
*/  
*/  
sendstring(" The char should be display in the screen",41);  
sendinteger (0xa);  
sendinteger (0xd);  
/* Set cursor begining of current line  
/* Set cursor to next line  
*/  
*/  
sendstring(" To stop the test press (s) ",28);  
sendinteger (0xa);  
sendinteger (0xd);  
while (!DONE)  
{
/* Set cursor begining of current line  
/* Set cursor to next line  
*/  
*/  
COMMAND = receivechar();  
switch (COMMAND)  
{
case ’s’: case ’S’:  
DONE =1;  
break;  
}
sendchar (COMMAND);  
}
16  
Literature Number: BPRA050  
Appendix A. Source Code  
/******************************************************************/  
/*  
Filename: UART1.h  
*/  
/******************************************************************/  
#include "c:\dsp\c2xx\lib\string.h"  
#include "c:\dsp\c2xx\lib\ioports.h"  
ioport int portfff4;  
void ISTXREADY(void);  
void ISRXREADY(void);  
unsigned char reply;  
void sendinteger (int i)  
{
ISTXREADY();  
portfff4 = i;  
}
void sendchar ( char c)  
{
ISTXREADY();  
portfff4 = c;  
}
void sendstring ( char s[],int length)  
{
int c,i;  
i = 0;  
while ( --length >= 0)  
sendchar(s[i++]);  
}
char receivechar(void)  
{
ISRXREADY();  
reply = portfff4;  
return (reply);  
}
Feature Phone based on TMS320LC203  
17  
Appendix A. Source Code  
*******************************************************************  
*
*
UART TEST PROGRAM LC203 BOARD  
File Name intp.asm  
*
*
*******************************************************************  
IMR  
GREG .set 5h  
IFR .set 6h  
ADTR .set 0fff4h  
ASPCR .set 0fff5h  
IOSR .set 0fff6h  
.set 4h  
; IMR reg  
; GREG reg  
; IFR reg  
; ADTR reg  
; ASPCR reg  
; IOSR reg  
; BRD reg  
; WSGR reg  
; Temp value  
; ST1 storage  
BRD  
.set 0fff7h  
WSGR .set 0fffch  
TEMP_VAL  
STAT1  
.usect "temp",2  
.set TEMP_VAL+1  
.def _INIT  
.def _ISTXREADY  
.def _ISRXREADY  
.ref _c_int0  
_INIT  
ldp #0  
;Set dp=0  
setc INTM  
clrc CNF  
clrc SXM  
setc OVM  
;turn off interrupts  
;Map B0 in data space  
;No sign extension  
;No overflow allowed  
;No product shift  
;Turn off interrupts  
;Clear all pending interrupt  
;Disable all global mem  
;7 WS I/O, 0 WS DAT, 0 WS PRG  
;Init WSGR  
SPM  
0
splk #0000h,IMR  
splk #0ffffh,IFR  
splk #0,GREG  
splk #0e00h,TEMP_VAL  
out  
TEMP_VAL,WSGR  
splk #0082h,TEMP_VAL  
out TEMP_VAL,BRD  
splk #0000h,TEMP_VAL  
out TEMP_VAL,IOSR  
splk #0000h,TEMP_VAL  
out TEMP_VAL,ASPCR  
;9600 Baud Rate  
;Init BDR  
;Reset TEMP_VAL  
;Init IOSR  
;Reset UART  
;Init ASPCR  
splk #2000h,TEMP_VAL  
;Boot the UART  
out  
ret  
TEMP_VAL,ASPCR  
;UART is now turned on  
_ISRXREADY SST  
#1,STAT1  
; Store ST1 in TEMP_VAL  
; Read the IOSR register  
; Test DR bit from IOSR  
; wait until TC=1  
; Load accumulator with ST1  
; Set TC=0  
READ_RX  
IN  
TEMP_VAL,IOSR  
TEMP_VAL,0111b  
BIT  
BCND READ_RX,NTC  
LACL STAT1  
AND  
#0f7ffh  
SACL STAT1  
; Store ST1 in TEMP_VAL  
; Restore ST1  
LST  
RET  
#1,STAT1  
; Return  
_ISTXREADY SST  
#1,STAT1  
; Store ST1 in TEMP_VAL  
; Read the IOSR register  
; Test THRE bit from IOSR  
; wait until TC=1  
READ_TX  
IN  
TEMP_VAL,IOSR  
TEMP_VAL,0100b  
BIT  
BCND READ_TX,NTC  
18  
Literature Number: BPRA050  
Appendix A. Source Code  
LACL STAT1  
; Load accumulator with ST1  
; Set TC=0  
AND  
#0f7ffh  
SACL STAT1  
; Store ST1 in TEMP_VAL  
; Restore ST1  
LST  
RET  
#1,STAT1  
; Return  
.sect "vectors"  
rs  
b
b
b
b
b
b
b
_c_int0  
; reset  
int1  
int1  
; int1/hold  
; int2/int3  
; timer  
int2_3  
tint  
rint  
xint  
int2_3  
tint  
rint  
xint  
; Synch receive  
; Synch transmit  
; Asynch Tran/Rec  
txrxint  
txrxint  
2*16  
.space  
; reserved interrupt for emulator  
int8  
int9  
b
int8  
int9  
b
int10  
int11  
int12  
int13  
int14  
int15  
int16  
trap  
b
int10  
int11  
int12  
int13  
int14  
int15  
int16  
trap  
b
b
b
b
b
b
b
nmi  
b
nmi  
;
;
None maskable interrupt  
reserved interrupt for emulator  
.space 2*16  
int20  
int21  
int22  
int23  
int24  
int25  
int26  
int27  
int28  
int29  
int30  
int31  
b
b
b
b
b
b
b
b
b
b
b
b
int20  
int21  
int22  
int23  
int24  
int25  
int26  
int27  
int28  
int29  
int30  
int31  
Feature Phone based on TMS320LC203  
19  
Appendix A. Source Code  
/*  
TMS320LC203 UART LINK COMMAND FILE  
*/  
uart.obj  
intp.obj  
-m uart.map  
-o uart.out  
-stack 512  
-cr  
-i c:\dsp\c2xx\lib  
-l c:\dsp\c2xx\lib\rts2xx.lib  
MEMORY  
{
PAGE 0 :  
/* Program space */  
VECS  
CODE  
EXT_PRG  
BLK_B0  
BLK_B0M  
:
:
:
:
:
o = 0x0000  
o = 0x0040  
o = 0x0600  
o = 0xFE00  
o = 0xFF00  
,
,
,
,
,
l = 0x0040  
l = 0x05C0  
l = 0xf7ff  
l = 0x0100  
l = 0x0100  
/* Vector area  
/* 1.4K CODE  
*/  
*/  
/* External Prog */  
/* BLK B0  
/* BLK B0’  
*/  
*/  
PAGE 1 :  
/* Data space  
/* Mem Map Reg  
/* BLK B2  
*/  
*/  
*/  
*/  
*/  
*/  
*/  
*/  
MEM_REG  
BLK_B2  
BLK_B0  
BLK_B0M  
BLK_B1  
BLK_B1M  
EXT_DAT  
:
:
:
:
:
:
:
o = 0x0000  
o = 0x0060  
o = 0x0100  
o = 0x0200  
o = 0x0300  
o = 0x0400  
o = 0x0800  
,
,
,
,
,
,
,
l = 0x0060  
l = 0x0020  
l = 0x0100  
l = 0x0100  
l = 0x0100  
l = 0x0100  
l = 0xf7ff  
/* BLK B0  
/* BLK B0’  
/* BLK B1  
/* BLK B1’  
/* Ext Data  
}
SECTIONS {  
vectors  
.text  
.data  
.bss  
:
:
:
:
:
:
:
:
{}  
{}  
{}  
{}  
{}  
{}  
{}  
{}  
>
>
>
>
>
>
>
>
VECS  
CODE  
PAGE 0  
PAGE 0  
/* int vectors  
/* code  
/* Init data  
/* Uninit data  
/* Temp Storage  
*/  
*/  
*/  
*/  
*/  
BLK_B0 PAGE 0  
BLK_B1 PAGE 1  
BLK_B2 PAGE 1  
EXT_PRG PAGE 0  
EXT_DAT PAGE 1  
EXT_DAT PAGE 1  
temp  
.cinit  
.stack  
.const  
}
20  
Literature Number: BPRA050  
Appendix B. PAL Programming  
Appendix B. PAL Programming  
MODULE module_name  
gpt3 DEVICE ’p16v8as’;  
"INPUTS  
A15,BR,DS,PS  
IS,XF,FSX  
PIN 2,3,4,5;  
PIN 6,7,8;  
"OUTPUTS  
PSL,PSU,DSL,DSU,FSL,FSH PIN 12,19,18,17,16,15;  
X,C,Z=.X.,.C.,.Z.;  
EQUATIONS  
!PSL  
!PSU  
= !PS & !A15;  
= !PS & A15;  
!DSL  
!DSU  
= !DS & !A15 & BR;  
= !DS & A15 & BR # !IS & A15;  
!FSL  
!FSH  
= !(FSX & !XF);  
= !(FSX & XF);  
TEST_VECTORS ([A15,BR,DS,PS,IS,XF,FSX] -> [PSL,PSU,DSL,DSU,FSL,FSH])  
[ 0, 0, 0, 0, 0, 0, 0] -> [ 0 , 1 , 1 , 1 , 0 , 0 ];  
[ 1, 1, 0, 0, 1, 1, 1] -> [ 1 , 0 , 1 , 0 , 0 , 1 ];  
[ 1, 1, 1, 1, 0, 0, 1] -> [ 1, 1 , 1 , 0 , 1 , 0 ];  
[ 1, 0, 0, 1, 1, 1, 0] -> [ 1, 1 , 1 , 1 , 0 , 0 ];  
END module_name  
Feature Phone based on TMS320LC203  
21  
Appendix B. PAL Programming  
22  
Literature Number: BPRA050  
Appendix C. Schematics  
Appendix C. Schematics  
Feature Phone based on TMS320LC203  
23  
24  
Literature Number: BPRA050  
1
2
3
4
5
6
EARAL  
Vdd  
C2  
1uF  
R19  
10K  
+
C1  
U4  
Vs+  
2
6
1
3
R1  
10K  
C1+  
C1-  
J2  
Vdd  
C3  
1uF  
1
6
2
7
3
8
4
9
5
EARGSL  
1uF  
C4  
+
U7  
LINSEL  
SW1A  
J3  
D
C
B
A
4
5
1
16  
LNSELL 15  
13  
2
4
3
D
C
B
A
Vs-  
C2+  
C2-  
EARA  
EARGS  
EARB  
DIP-SW8  
R20  
2K7  
PHONEPLUG1  
1uF  
DOUT  
FSX  
TSX/DCLKX  
FS_L  
12  
14  
14  
7
11  
10  
T1OUT  
T2OUT  
T1IN  
T2IN  
10  
6
EARMUTE  
MICMUTE  
8
9
7
EARBL  
EMUTEL  
MMUTEL  
DIN  
FSR  
DCLKR  
13  
8
12  
9
FS_L  
R1IN  
R2IN  
R1OUT  
R2OUT  
FS_L  
EMUTEL  
MMUTEL  
20  
19  
18  
DB9  
MICBIAS  
MICGS  
MICIN  
Vdd  
MAX3232  
MCLK  
11  
1
MICINL  
MCLK  
CLK  
PDN  
R13  
10K  
17  
VMID  
R3  
10K  
R4  
10K  
R5  
10K  
R6  
10K  
R7  
10K  
R8  
10K  
TLV320AC36  
Vdd  
U3  
C57  
C7  
1uF  
5
6
7
3
2
1
R14  
10K  
A
B
C
DSBL  
D
F
D[0..15]  
470pF  
SW1C  
14  
13  
12  
11  
10  
9
3
B
DIP-SW8  
14.31818 PROG OSC  
GNDa  
SW1D  
C47  
10uF  
4
C
DIP-SW8  
J4  
SW1E  
5
DIV2  
DIV1  
BIO  
DIP-SW8  
PHONEPLUG1  
U1  
Vdd  
Vdd  
SW1F  
6
GNDa  
DIP-SW8  
SW1G  
93  
95  
I/O0 96  
I/O1 97  
TX  
RX  
IO0/DTR  
IO1/DSR  
IO2/RTS  
IO3/CTS  
98  
87  
84  
85  
86  
89  
90  
XF  
MCLK  
BIO  
XF  
CLKX  
CLKR  
FSR  
DR  
FSX  
XF  
7
R2  
10K  
I/O0  
I/O1  
I/O2  
I/O3  
DIP-SW8  
I/O2  
I/O3  
8
9
SW1H  
8
BOOT*  
DR  
FSX  
DX  
R15  
10K  
SW1B  
15  
DIP-SW8  
DIP-SW8  
LNSELH  
15  
2
FSX  
S1  
12  
13  
5
3
10  
CLKIN/X2  
X1  
DIV2  
DIV1  
PLL5V  
DX  
Vdd Vcc  
6
Vdd  
HOLDA  
INT3  
INT2  
HOLD/INT1  
NMI  
20  
19  
18  
17  
INT3  
FS  
INT1  
NMI  
U5  
R16  
2K7  
INT3  
FS  
INT1  
NMI  
2
4
3
EARAH  
EARGSH  
EARBH  
SPEAKER  
LINSEL  
EARA  
EARGS  
R9  
22K  
U2  
TOUT  
92  
1
99  
2
100  
13  
12  
14  
TOUT  
TOUT  
TEST  
BIO  
BOOT  
RS  
DOUT  
FSX  
EARB  
3
7
2
1
FS_H  
FS_H  
CT  
SEN  
RESIN  
REF  
15  
CLKOUT  
CLKOUT1  
CLKOUT  
TSX/DCLKX  
6
5
10  
6
EMUTEH  
MMUTEH  
RST  
RSET  
EARMUTE  
MICMUTE  
EMUTEH  
MMUTEH  
RESET*  
49  
51  
52  
53  
43  
44  
45  
46  
47  
8
9
7
READY  
DS  
IS  
PS  
BR  
WE  
RD  
STRB  
DIN  
FSR  
DCLKR  
FS_H  
M1  
R18  
2k  
C6  
SW2  
SW-PB  
TLC7705IP  
79  
77  
76  
78  
82  
80  
81  
20  
19  
18  
+
TRST  
EMU1/OFF  
EMU0  
TCK  
TDO  
TDI  
MICBIAS  
MICGS  
MICIN  
C5  
100nF  
100nF  
Vdd Vdd  
MCLK 11  
1
CLK  
PDN  
MICROPHONE  
C45  
.33uF  
R17  
10k  
17  
VMID  
R11 R12  
10K 10K  
GNDa  
TMS  
R/W  
TLV320AC36  
C46  
1uF  
C58  
470pF  
Vdd  
TMS320LC203  
J1  
TMS  
TDI  
TRST  
1
3
5
7
9
11  
13  
2
4
6
GNDa  
TDO  
TCK  
8
10  
12  
14  
DS  
IS  
PS  
BR  
WE  
DS  
IS  
PS  
BR  
WE  
EMU0  
EMU1  
HEADER 7X2  
Title  
Feature Phone based on TMS320LC203  
A[0..15]  
Size  
B
Number  
Revision  
1.0  
Date:  
File:  
21-Oct-1996  
C:\ADVSCH\2XX\APLC203.SCH  
Sheet1 of 6  
Drawn By: Michael Seidl  
1
2
3
4
5
6
Feature Phone based on TMS320LC203  
25  
1
2
3
4
5
6
Data RAM  
Program RAM  
Global ROM  
0000-7FFF  
8000-FFFF  
0000-7FFF  
8000-FFFF  
D
C
B
D
C
B
A
A[0..14]  
U8  
U10  
U12  
U14  
A14  
A13  
A12  
A11  
A10  
A9  
A8  
A7  
A6  
A5  
U16  
A14  
A13  
A12  
A11  
A10  
A9  
A8  
A7  
A6  
A5  
1
26  
2
23  
21  
24  
25  
3
4
5
6
7
22  
20  
27  
A14  
A13  
A12  
A11  
A10  
A9  
A8  
A7  
A6  
A5  
A4  
A3  
A2  
A1  
A0  
1
26  
2
23  
21  
24  
25  
3
4
5
6
7
22  
20  
27  
A14  
A13  
A12  
A11  
A10  
A9  
A8  
A7  
A6  
A5  
1
26  
2
23  
21  
24  
25  
3
4
5
6
7
22  
20  
27  
A14  
A13  
A12  
A11  
A10  
A9  
A8  
A7  
A6  
A5  
1
26  
2
23  
21  
24  
25  
3
4
5
6
7
22  
20  
27  
A14  
A13  
A12  
A11  
A10  
A9  
A8  
A7  
A6  
A5  
27  
26  
2
23  
21  
24  
25  
3
4
5
6
7
20  
22  
BR  
A14  
A13  
A12  
A11  
A10  
A9  
A8  
A7  
A6  
A5  
OE  
CS  
WE  
A14  
A13  
A12  
A11  
A10  
A9  
A8  
A7  
A6  
A5  
OE  
CS  
WE  
A14  
A13  
A12  
A11  
A10  
A9  
A8  
A7  
A6  
A5  
OE  
CS  
WE  
OE  
CS  
WE  
A14  
A13  
A12  
A11  
A10  
A9  
A8  
A7  
A6  
A5  
A4  
A3  
A2  
A1  
A0  
MX27L256  
E
G
11  
12  
13  
17  
16  
15  
18  
19  
D0  
D1  
D2  
D3  
D4  
D5  
D6  
D7  
11  
12  
13  
17  
16  
15  
18  
19  
D0  
D1  
D2  
D3  
D4  
D5  
D6  
D7  
11  
12  
13  
17  
16  
15  
18  
19  
D0  
D1  
D2  
D3  
D4  
D5  
D6  
D7  
11  
12  
13  
17  
16  
15  
18  
19  
D0  
D1  
D2  
D3  
D4  
D5  
D6  
D7  
11  
12  
13  
15  
16  
17  
18  
19  
D0  
D1  
D2  
D3  
D4  
D5  
D6  
D7  
I/O0  
I/O1  
I/O2  
I/O5  
I/O4  
I/O3  
I/O6  
I/O7  
I/O0  
I/O1  
I/O2  
I/O5  
I/O4  
I/O3  
I/O6  
I/O7  
I/O0  
I/O1  
I/O2  
I/O5  
I/O4  
I/O3  
I/O6  
I/O7  
I/O0  
I/O1  
I/O2  
I/O5  
I/O4  
I/O3  
I/O6  
I/O7  
DQ1  
DQ2  
DQ3  
DQ4  
DQ5  
DQ6  
DQ7  
DQ8  
A4  
A3  
A2  
A1  
A4  
A3  
A2  
A1  
A4  
A3  
A2  
A1  
A4  
A3  
A2  
A1  
A4  
A3  
A2  
A1  
A4  
A3  
A2  
A1  
A4  
A3  
A2  
A1  
A4  
A3  
A2  
A1  
8
9
10  
8
9
10  
8
9
10  
8
9
10  
8
9
10  
A0  
A0  
A0  
A0  
A0  
A0  
A0  
A0  
IDT71V256SA  
IDT71V256SA  
IDT71V256SA  
IDT71V256SA  
WE  
DSL  
DSU  
PSL  
PSU  
BR  
IS  
U17  
U9  
U11  
U13  
U15  
A14  
A13  
A12  
A11  
A10  
A9  
A8  
A7  
A6  
A5  
A4  
A3  
A2  
A1  
1
26  
2
23  
21  
24  
25  
3
4
5
6
7
22  
20  
27  
A14  
A13  
A12  
A11  
A10  
A9  
A8  
A7  
A6  
A5  
A4  
A3  
A2  
A1  
1
26  
2
23  
21  
24  
25  
3
4
5
6
7
22  
20  
27  
A14  
A13  
A12  
A11  
A10  
A9  
A8  
A7  
A6  
A5  
A4  
A3  
A2  
A1  
1
26  
2
23  
21  
24  
25  
3
4
5
6
7
22  
20  
27  
A14  
A13  
A12  
A11  
A10  
A9  
A8  
A7  
A6  
A5  
A4  
A3  
A2  
A1  
1
26  
2
23  
21  
24  
25  
3
4
5
6
7
22  
20  
27  
A14  
A13  
A12  
A11  
A10  
A9  
A8  
A7  
A6  
A5  
A4  
A3  
A2  
A1  
OE  
CS  
WE  
A14  
A13  
A12  
A11  
A10  
A9  
A8  
A7  
A6  
A5  
A4  
A3  
A2  
A1  
OE  
CS  
WE  
A14  
A13  
A12  
A11  
A10  
A9  
A8  
A7  
A6  
A5  
A4  
A3  
A2  
A1  
OE  
CS  
WE  
A14  
A13  
A12  
A11  
A10  
A9  
A8  
A7  
A6  
A5  
A4  
A3  
A2  
A1  
OE  
CS  
WE  
11  
12  
13  
17  
16  
15  
18  
19  
D8  
D9  
11  
12  
13  
17  
16  
15  
18  
19  
D8  
D9  
11  
12  
13  
17  
16  
15  
18  
19  
D8  
D9  
11  
12  
13  
17  
16  
15  
18  
19  
D8  
D9  
I/O0  
I/O1  
I/O2  
I/O5  
I/O4  
I/O3  
I/O6  
I/O7  
I/O0  
I/O1  
I/O2  
I/O5  
I/O4  
I/O3  
I/O6  
I/O7  
I/O0  
I/O1  
I/O2  
I/O5  
I/O4  
I/O3  
I/O6  
I/O7  
I/O0  
I/O1  
I/O2  
I/O5  
I/O4  
I/O3  
I/O6  
I/O7  
5
3
2
13  
12  
IS  
STR  
A
D10  
D11  
D12  
D13  
D14  
D15  
D10  
D11  
D12  
D13  
D14  
D15  
D10  
D11  
D12  
D13  
D14  
D15  
D10  
D11  
D12  
D13  
D14  
D15  
8
4
10  
D0  
D1  
D2  
D3  
BLNK  
L_DEC  
R_DEC  
B
C
D
8
9
10  
8
9
10  
8
9
10  
8
9
10  
TIL311  
A0  
A0  
A0  
A0  
A0  
A0  
A0  
A0  
IDT71V256SA  
IDT71V256SA  
IDT71V256SA  
IDT71V256SA  
D[0..15]  
A
Title  
Feature Phone based on TMS320LC203  
Size  
B
Number  
Revision  
1.0  
Date:  
File:  
21-Oct-1996  
C:\ADVSCH\2XX\203MEM.SCH  
Sheet2 of 6  
Drawn By: Michael Seidl  
1
2
3
4
5
6
26  
Literature Number: BPRA050  
1
2
3
4
5
6
D
C
B
A
D
C
B
U22  
10K  
Vdd U21  
10K  
Vdd  
J8  
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
Vdd  
I/O0  
I/O1  
I/O2  
I/O3  
I/O0  
I/O1  
I/O2  
I/O3  
U18  
CLK  
1
20  
Vcc  
!PSU* = !PS* & A15  
A15  
BR  
DS  
PS  
IS  
XF  
FSX  
2
3
4
5
6
7
8
9
19  
18  
17  
16  
15  
14  
13  
12  
PSU  
A15  
BR  
DS  
PS  
IS  
XF  
FSX  
I0  
I1  
I2  
I3  
I4  
I5  
I6  
I7  
I/O0  
I/O1  
I/O2  
I/O3  
I/O4  
I/O5  
I/O6  
I/O7  
PSU  
!DSL* = !DS* & !A15 & BR*  
!DSU* = !DS* & A15 & BR* | !IS* & A15  
!FS_L = !(FSX & !XF)  
DSL  
DSU  
FS_L  
FS_H  
TOUT  
DSL  
DSU  
FS_L  
FS_H  
TOUT  
EMUTEL  
MMUTEL  
EMUTEL  
MMUTEL  
EMUTEH  
MMUTEH  
EMUTEH  
MMUTEH  
!FS_H = !(FSX & XF)  
PSL  
PSL  
!PSL* = !PS* & !A15  
10  
11  
INT3  
FS  
INT1  
NMI  
GND  
OE  
INT3  
PALLV16V8-10PC  
INT1  
NMI  
CLKOUT  
BIO  
CLKOUT  
BIO  
U6  
QD  
QE  
QF  
QG  
QH  
QI  
47  
R22  
33K  
7
5
4
11  
CKI  
28PIN  
33pF  
U23  
2.048MHz  
R21  
10M  
6
14  
13  
15  
1
2
3
FS  
FS  
C46  
QJ  
10  
12  
QL  
QM  
QN  
CKO  
CKO  
CLR  
15pF  
9
MCLK  
SN74HC4060  
A
Title  
Feature Phone based on TMS320LC203  
Size  
B
Number  
Revision  
1.0  
Date:  
File:  
21-Oct-1996  
C:\ADVSCH\2XX\203LOGIC.SCH  
Sheet3 of  
6
Drawn By: Michael Seidl  
1
2
3
4
5
6
Feature Phone based on TMS320LC203  
27  
1
2
3
4
5
6
Vdda  
Vdd  
U19  
Vcc  
U20  
TLV2217-33  
uA7805AC  
J7  
L1  
D
C
B
1
2
1
3
1
3
D
C
B
A
+3.3V  
Vin  
+5V  
Vin  
1
Ferrite Bead  
2
3
4
C14  
10uF  
C44  
10uF  
C43  
22uF  
C42  
+
10uF  
+
+
+
4 HEADER  
L2  
1
2
2
Ferrite Bead  
GNDa  
Vcca  
Vdd  
L3  
1
Ferrite Bead  
C54  
10uF  
C55  
10uF  
+
+
GNDa  
Vdd  
Vdd  
Vdda  
Close to TMS320LC203  
Close to Osc. and TLC7705  
Close to TLV320AC3x  
C26  
100nF  
C8  
100nF  
C9  
C10  
100nF  
C11  
100nF  
C12  
100nF  
C13  
100nF  
C25  
100nF  
C27  
100nF  
C28  
C29  
100nF  
100nF  
100nF  
GNDa  
Vdd  
Vdd  
Vcca  
Close to memory devices  
Close to LED displayVcc  
Close to PAL  
Close to MAX3232  
Close to TL061  
Vdd  
C41  
+
C56  
100nF  
C16  
100nF  
C17  
100nF  
C18  
100nF  
C19  
100nF  
C20  
100nF  
C21  
100nF  
C22  
100nF  
C23  
100nF  
C24  
100nF  
C30  
100nF  
C40  
100nF  
4.7uF  
GNDa  
A
Title  
Feature Phone based on TMS320LC203  
Size  
B
Number  
Revision  
1.0  
Date:  
File:  
21-Oct-1996  
C:\ADVSCH\2XX\203POWER.SCH  
Sheet4 of 6  
Drawn By: Michael Seidl  
1
2
3
4
5
6
28  
Literature Number: BPRA050  

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