TMS320M640AGDK4 [TI]
IC 32-BIT, 75.19 MHz, OTHER DSP, PBGA548, 23 X 23 MM, 0.80 MM PITCH, PLASTIC, BGA-548, Digital Signal Processor;
| 型号： | TMS320M640AGDK4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | IC 32-BIT, 75.19 MHz, OTHER DSP, PBGA548, 23 X 23 MM, 0.80 MM PITCH, PLASTIC, BGA-548, Digital Signal Processor 时钟 外围集成电路 |
| 文件： | 总187页 (文件大小：2738K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TMS320DM641/TMS320DM640
Video/Imaging Fixed-Point Digital
Signal Processors
Data Manual
Literature Number: SPRS222E
June 2003 − Revised October 2005
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
This page intentionally left blank
Revision History
Revision History
This data sheet revision history highlights the technical changes made to the SPRS222D device-specific data
sheet to make it an SPRS222E revision.
Scope: Applicable updates to the C64x device family, specifically relating to the TMS320DM641/TMS320DM640
devices, have been incorporated.
8−bit TSI Video Port mode now supported.
Added the device-specific information supporting the TMS320DM641/TMS320DM640 silicon revision 2.0, 1.2 and
1.1 devices, which are now in the production data (PD) stage of development.
PAGE(s)
ADDS/CHANGES/DELETES
NO.
44
47
Terminal Functions table:
Reset, Interrupts, and General−Purpose Input/Output section:
CLKOUT6/GPO[2]: changed “IPD” to “IPU”
CLKOUT4/GPO[1]: changed “IPD” to “IPU”
Terminal Functions table:
EMIFA (32−BIT) − ADDRESS section:
Updated the Description for Boot Configuration for AEA22:3 Signal Name from “11 − EMIFA boot” to “11 − EMIFA 8−bit ROM
boot”
66
69
Device Support, Device and Development-Support Tool Nomenclature:
Updated the TMS320DM64x DSP Device Nomenclature (Including the DM641 and DM640 Devices) figure
Device Configurations, Configurations at Reset, Device Configuration at Device Reset section:
Updated the Functional Description for Bootmode [1:0] for AEA22:21 Configuration Pin from “11 − EMIFA boot” to
“11 − EMIFA 8−bit ROM boot”
74
82
Device Configurations, Device Status Register Description section:
Device Status (DEVSTAT) Register Selection Bit Descriptions table:
Updated Bits 3 and 2 Bootmode1 and Bootmode0 Name Description from “11 − EMIFA boot” to “11 − EMIFA 8−bit ROM
boot”
Recommended Operating Conditions:
V
OS,
Maximum voltage during overshoot row
Deleted −1.0 from MIN
Added V Maximum voltage during undershoot row
US,
85
Parameter Measurement Information section:
Added AC transient rise/fall time specifications and the following figures:
AC Transient Specification Rise Time figure
AC Transient Specification Fall Time figure
104
Clock PLL, Clock PLL Electrical Data/Timing (Input and Output Clocks):
Switching Characteristics Over Recommended Operating Conditions for AECLKOUT2 for the EMIFA Module table:
Updated Parameter No. 5 from “t
to “t
d(EKIH-EKO2L)”
d(EKIL-EKO2L)”
Updated Parameter No. 5 from “Delay time, AECLKIN high to AECLKOUT2 low” to “Delay time, AECLKIN low to AECLK-
OUT2 low”
3
June 2003 − Revised October 2005
SPRS222E
Revision History
PAGE(s)
NO.
ADDS/CHANGES/DELETES
106
External Memory Interface (EMIF), EMIF Electrical Data Timing, Asynchronous Memory Timing section:
Timing Requirements for Asynchronous Memory Cycles for EMIFA Module table:
Updated Parameter No. 7, t
MIN from “2.0” to “2.5”
h(EKO1H-ARDY)
Switching Characteristics Over Recommended Operating Conditions for Asynchronous Memory Cycles for EMIFA Module
table:
Updated Parameter No. 1, t
Updated Parameter No. 8, t
MIN from “RS*E − 1.5” to “RS*E − 1.8”
MIN from “WS*E − 1.7” to “WS*E − 2.0”
osu(SELV-AREL)
osu(SELV-AWEL)
109
External Memory Interface (EMIF), EMIF Electrical Data Timing, Programmable Synchronous Interface Timing section:
Timing Requirements for Programmable Synchronous Interface Cycles for EMIFA Module table:
Updated Parameter No. 7, t
MIN from “1.5” to “1.8” for −400 and−500 device speeds
h(EKOxH-EDV)
Switching Characteristics Over Recommended Operating Conditions for Programmable Synchronous Interface Cycles for
EMIFA Module table:
Updated all delay times MIN for −400, −500 and −600 device speeds from “1.3” to “1.1”
113
External Memory Interface (EMIF), EMIF Electrical Data Timing section, Synchronous DRAM Timing section:
Timing Requirements for Asynchronous Memory Cycles for EMIFA Module table:
Updated Parameter No. 7, t
Updated Parameter No. 7, t
MIN from “2.5” to “2.8” for −400 and −500 device speeds
MIN from “1.8” to “2.1” for −600 and device speed
h(EKO1H-ARDY)
h(EKO1H-ARDY)
127−128 Multichannel Audio Serial Port (McASP) Timing section::
Updated McASP Input and Output Timings figures
140
161
External Memory Interface (EMIF), McBSP Electrical Data/Timing, Multichannel Buffered Serial Port (McBSP) Timing section:
Switching Characteristics Over Recommended Operating Conditions for McBSP table:
Updated Parameter No. 12, t , CLKX ext MIN from “2.0” to “−2.1”
dis(CKXH-DXHZ))
Updated Parameter No. 13, td
CLKX ext MIN from “2.0 + D1” to “−2.1 + D1”
(CKXH-DXV)
Ethernet Media Access (EMAC) Control, EMAC Electrical Data/Timing:
Timing Requirements for EMAC MII Receive 10/100 Mbit/s table:
Deleted paragraph
Switching Characteristics Over Recommended Operating Conditions for EMAC MII Transmit 10/100 Mbit/s table:
Deleted paragraph
168
IEEE 1149.1 JTAG Compatibility Statement section:
Updated/added paragraphs for clarity
4
SPRS222E
June 2003 − Revised October 2005
Contents
Page
Contents
Section
1
Device Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
1.1
1.2
1.3
1.4
1.5
1.6
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Device Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Device Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
CPU (DSP Core) Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
1.6.1
Memory Map Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
1.7.1 L2 Architecture Expanded . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
CPU Core Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
1.7
1.8
1.9
Bootmode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
1.9.1
1.9.2
1.9.3
Pin Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Signal Groups Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Terminal Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
1.10
Development . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
1.10.1
1.10.2
Development Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Device Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
1.10.2.1
1.10.2.2
1.10.2.3
Device and Development-Support Tool Nomenclature . . . . . . . . . 65
Documentation Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Device Silicon Revision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
2
Device Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
2.1
Configurations at Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
2.1.1
2.1.2
Peripheral Selection at Device Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Device Configuration at Device Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
2.2
Configurations After Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
2.2.1 Peripheral Selection After Device Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
2.3
2.4
2.5
2.6
2.7
Peripheral Configuration Lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Device Status Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Multiplexed Pin Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Debugging Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Configuration Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
3
4
Device Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
3.1
3.2
3.3
Absolute Maximum Ratings Over Operating Case Temperature Range . . . . . . . . . . . . . . . . . . 82
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Electrical Characteristics Over Recommended Ranges of Supply Voltage and
Operating Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
DM641/DM640 Peripheral Information and Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . 84
4.1 Parameter Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
4.1.1 Parameter Information Device-Specific Information . . . . . . . . . . . . . . . . . . . . . . . 84
4.1.1.1
4.1.1.2
Signal Transition Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Signal Transition Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
5
June 2003 − Revised October 2005
SPRS222E
Contents
Section
Page
4.1.1.3
4.1.1.4
AC Transient Rise/Fall Time Specifications . . . . . . . . . . . . . . . . . . 85
Timing Parameters and Board Routing Analysis . . . . . . . . . . . . . . 85
4.2
4.3
Recommended Clock and Control Signal Transition Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
4.3.1
4.3.2
4.3.3
4.3.4
4.3.5
4.3.6
4.3.7
Power-Supply Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Power-Supply Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Power-Supply Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Peripheral Power-Down Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Power-Down Modes Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Triggering, Wake-up, and Effects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
C64x Power-Down Mode with an Emulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
4.4
4.5
Enhanced Direct Memory Access (EDMA) Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
4.4.1
4.4.2
EDMA Device-Specific Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
4.4.1.1 EDMA Channel Synchronization Events . . . . . . . . . . . . . . . . . . . . . 90
EDMA Peripheral Register Description(s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
4.5.1
4.5.2
4.5.3
Interrupt Sources and Interrupt Selector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Interrupts Peripheral Register Description(s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
External Interrupts Electrical Data/Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
4.6
4.7
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
4.6.1 Reset Electrical Data/Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Clock PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
4.7.1
4.7.2
Clock PLL Device-Specific Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Clock PLL Electrical Data/Timing (Input and Output Clocks) . . . . . . . . . . . . . . . 101
4.8
External Memory Interface (EMIIF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
4.8.1
4.8.2
4.8.3
EMIF Device-Specific Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
EMIF Peripheral Register Description(s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
EMIF Electrical Data/Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
4.8.3.1
4.8.3.2
4.8.3.3
4.8.3.4
4.8.3.5
Asynchronous Memory Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Programmable Synchronous Interface Timing . . . . . . . . . . . . . . . 109
Synchronous DRAM Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
HOLD/HOLDA Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
BUSREQ Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
4.9
Multichannel Audio Serial Port (McASP0) Peripheral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
4.9.1
McASP0 Device-Specific Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
4.9.1.1 McASP Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
4.9.2
4.9.3
McASP0 Peripheral Register Description(s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
McASP0 Electrical Data/Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
4.9.3.1
Multichannel Audio Serial Port (McASP) Timing . . . . . . . . . . . . . 125
4.10
4.11
Inter-Integrated Circuit (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
4.10.1
4.10.2
4.10.3
I2C Device-Specific Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
I2C Peripheral Register Description(s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
I2C Electrical Data/Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
4.10.3.1 Inter-Integrated Circuits (I2C) Timing . . . . . . . . . . . . . . . . . . . . . . . 131
Host-Port Interface (HPI) [DM641 Only] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
4.11.1
4.11.2
HPI Peripheral Register Description(s) [DM641 Only] . . . . . . . . . . . . . . . . . . . . 133
Host-Port Interface (HPI) Electrical Data/Timing [DM641 Only] . . . . . . . . . . . . 133
6
SPRS222E
June 2003 − Revised October 2005
Contents
Section
4.12
Page
Multichannel Buffered Serial Port (McBSP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
4.12.1
4.12.2
McBSP Peripheral Register Description(s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
McBSP Electrical Data/Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
4.12.2.1
Multichannel Buffered Serial Port (McBSP) Timing . . . . . . . . . . . 139
4.13
Video Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
4.13.1
4.13.2
4.13.3
Video Port Device-Specific Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Video Port Peripheral Register Description(s) . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Video Port (VP0 [DM641/DM640], VP1 [DM641 Only]) Electrical
Data/Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
4.13.3.1
4.13.3.2
4.13.3.3
4.13.3.4
VCLKIN Timing (Video Capture Mode) . . . . . . . . . . . . . . . . . . . . . 149
Video Data and Control Timing (Video Capture Mode) . . . . . . . . 150
VCLKIN Timing (Video Display Mode) . . . . . . . . . . . . . . . . . . . . . . 151
Video Control Input/Output and Video Display Data Output
Timing With Respect to VPxCLKINx and VPxCLKOUTx
(Video Display Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
4.13.3.5
Video Dual-Display Sync Mode Timing (With Respect to
VPxCLKINx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
4.14
VCXO Interpolated Control (VIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
4.14.1
4.14.2
4.14.3
VIC Device-Specific Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
VIC Peripheral Register Description(s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
VIC Electrical Data/Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
4.14.3.1
Ethernet Media Access Controller (EMAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
STCLK Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
4.15
4.16
4.17
4.18
4.19
4.15.1
4.15.2
4.15.3
EMAC Device-Specific Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
EMAC Peripheral Register Description(s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
EMAC Electrical Data/Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Management Data Input/Output (MDIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
4.16.1
4.16.2
4.16.3
Device-Specific Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Peripheral Register Description(s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Management Data Input/Output (MDIO) Electrical Data/Timing . . . . . . . . . . . . 163
Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
4.17.1
4.17.2
4.17.3
Timer Device-Specific Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
Timer Peripheral Register Description(s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
Timer Electrical Data/Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
General-Purpose Input/Output (GPIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
4.18.1
4.18.2
4.18.3
GPIO Device-Specific Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
GPIO Peripheral Register Description(s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
General-Purpose Input/Output (GPIO) Electrical Data/Timing . . . . . . . . . . . . . 167
JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
4.19.1
JTAG Device-Specific Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
4.19.1.1
4.19.1.2
IEEE 1149.1 JTAG Compatibility Statement . . . . . . . . . . . . . . . . . 168
JTAG ID Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
4.19.2
4.19.3
JTAG Peripheral Register Description(s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
JTAG Test-Port Electrical Data/Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
5
Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
5.1 Thermal Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
7
June 2003 − Revised October 2005
SPRS222E
Figures
Figure
List of Figures
Page
1−1
1−2
1−3
1−4
1−5
1−6
1−7
Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
TMS320C64x CPU (DSP Core) Data Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
TMS320DM641/DM640 L2 Architecture Memory Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
DM641/DM640 Pin Map [Quadrant A] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
CPU and Peripheral Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Peripheral Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
TMS320DM64x DSP Device Nomenclature (Including the DM641 and DM640 Devices) . . . . . . . . . . 66
2−1
2−2
2−3
2−4
2−5
2−6
2−7
2−8
2−9
Peripheral Configuration Register (PERCFG) [Address Location: 0x01B3F000 − 0x01B3F003] . . . . 70
VP1, VP0, McBSP1, and McBSP0 Pin Muxing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Peripheral Enable/Disable Flow Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
PCFGLOCK Register Diagram [Address Location: 0x01B3 F018] − Read/Write Accesses . . . . . . . . 73
Device Status Register (DEVSTAT) Description − 0x01B3 F004 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Configuration Example A for DM641 (2 8-Bit Video Ports + 1 McASP0 + VIC + I2C0 + EMIF) . . . . . 78
Configuration Example B for DM641 (1 McASP0 + 2 McBSPs + VIC + I2C0 + EMIF) . . . . . . . . . . . . . 79
Configuration Example A for DM640 (1 8-Bit Video Port + 1 McASP0 + VIC + I2C0 + EMIF) . . . . . . 80
Configuration Example B for DM640 (1 McASP0 + 2 McBSPs + VIC + I2C0 + EMIF) . . . . . . . . . . . . . 81
4−1
Test Load Circuit for AC Timing Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Input and Output Voltage Reference Levels for AC Timing Measurements . . . . . . . . . . . . . . . . . . . . . . 84
Rise and Fall Transition Time Voltage Reference Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
AC Transient Specification Rise Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
AC Transient Specification Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Board-Level Input/Output Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Schottky Diode Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Power-Down Mode Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
PWRD Field of the CSR Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
External/NMI Interrupt Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
External PLL Circuitry for Either PLL Multiply Modes or x1 (Bypass) Mode . . . . . . . . . . . . . . . . . . . . . 100
CLKIN Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
CLKOUT4 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
CLKOUT6 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
AECLKIN Timing for EMIFA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
AECLKOUT1 Timing for the EMIFA Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
AECLKOUT2 Timing for the EMIFA Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Asynchronous Memory Read Timing for EMIFA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Asynchronous Memory Write Timing for EMIFA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Programmable Synchronous Interface Read Timing for EMIFA (With Read Latency = 2) . . . . . . . . . 110
4−2
4−3
4−4
4−5
4−6
4−7
4−8
4−9
4−10
4−11
4−12
4−13
4−14
4−15
4−16
4−17
4−18
4−19
4−20
4−21
8
SPRS222E
June 2003 − Revised October 2005
Figures
Page
Figure
4−22
4−23
4−24
4−25
4−26
4−27
4−28
4−29
4−30
4−31
4−32
4−33
4−34
4−35
4−36
4−37
4−38
4−39
4−40
4−41
4−42
4−43
4−44
4−45
4−46
4−47
4−48
4−49
4−50
4−51
4−52
4−53
Programmable Synchronous Interface Write Timing for EMIFA (With Write Latency = 0) . . . . . . . . . 111
Programmable Synchronous Interface Write Timing for EMIFA (With Write Latency = 1) . . . . . . . . . 112
SDRAM Read Command (CAS Latency 3) for EMIFA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
SDRAM Write Command for EMIFA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
SDRAM ACTV Command for EMIFA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
SDRAM DCAB Command for EMIFA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
SDRAM DEAC Command for EMIFA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
SDRAM REFR Command for EMIFA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
SDRAM MRS Command for EMIFA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
SDRAM Self-Refresh Timing for EMIFA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
HOLD/HOLDA Timing for EMIFA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
BUSREQ Timing for EMIFA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
McASP0 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
McASP Input Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
McASP Output Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
I2C0 Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
I2C Receive Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
I2C Transmit Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
HPI16 Read Timing (HAS Not Used, Tied High) [DM641 Only] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
HPI16 Read Timing (HAS Used) [DM641 Only] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
HPI16 Write Timing (HAS Not Used, Tied High) [DM641 Only] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
HPI16 Write Timing (HAS Used) [DM641 Only] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
McBSP Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
FSR Timing When GSYNC = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . 142
McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . 143
McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . 144
McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Video Port Capture VPxCLKINx TIming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Video Port Capture Data and Control Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
Video Port Display VPxCLKINx Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Video Port Display Data Output Timing and Control Input/Output Timing With Respect to
VPxCLKINx and VPxCLKOUTx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
4−54
4−55
4−56
4−57
4−58
4−59
4−60
4−61
4−62
Video Port Dual-Display Sync Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
STCLK Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
MRCLK Timing (EMAC − Receive) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
MTCLK Timing (EMAC − Transmit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
EMAC Receive Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
EMAC Transmit Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
MDIO Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
MDIO Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Timer Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
9
June 2003 − Revised October 2005
SPRS222E
Figures
Figure
Page
GPIO Enable Register (GPEN) [Hex Address: 01B0 0000] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
4−63
4−64
4−65
4−66
4−67
GPIO Direction Register (GPDIR) [Hex Address: 01B0 0004] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
GPIO Port Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
JTAG ID Register Description − TMS320DM641/DM640 Register Value − 0x0007 902F . . . . . . . . . 168
JTAG Test-Port Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
10
SPRS222E
June 2003 − Revised October 2005
Tables
Page
List of Tables
Table
1−1
1−2
1−3
1−4
1−5
1−6
Characteristics of the DM641 Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Characteristics of the DM640 Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Peripherals Available on the DM641 and DM640 Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
L2 Cache Registers (C64x) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
TMS320DM641/DM640 Memory Map Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Terminal Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
2−1
2−2
MAC_EN Peripheral Selection (EMAC and MDIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
DM641/DM640 Device Configuration Pins (TOUT1/LENDIAN, AEA[22:19], and
TOUT0/MAC_EN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
2−3
2−4
2−5
2−6
2−7
Peripheral Configuration (PERCFG) Register Selection Bit Descriptions . . . . . . . . . . . . . . . . . . . . . . . . 70
PCFGLOCK Register Selection Bit Descriptions − Read Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
PCFGLOCK Register Selection Bit Descriptions − Write Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Device Status (DEVSTAT) Register Selection Bit Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
DM641/DM640 Device Multiplexed Pin Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
4−1
4−2
4−3
4−4
4−5
4−6
4−7
4−8
4−9
4−10
4−11
4−12
Board-Level Timing Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Characteristics of the Power-Down Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
TMS320DM641/DM640 EDMA Channel Synchronization Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
EDMA Registers (C64x) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Quick DMA (QDMA) and Pseudo Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
EDMA Parameter RAM (C64x) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
DM641/DM640 DSP Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Interrupt Selector Registers (C64x) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Timing Requirements for External Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Timing Requirements for Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Switching Characteristics Over Recommended Operating Conditions During Reset . . . . . . . . . . . . . . 97
TMS320DM641/DM640 PLL Multiply Factor Options, Clock Frequency Ranges, and Typical
Lock Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
4−13
4−14
4−15
4−16
4−17
4−18
4−19
Timing Requirements for CLKIN for −400 Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Timing Requirements for CLKIN for −500 Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Timing Requirements for CLKIN for −600 Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Switching Characteristics Over Recommended Operating Conditions for CLKOUT4 . . . . . . . . . . . . . 102
Switching Characteristics Over Recommended Operating Conditions for CLKOUT6 . . . . . . . . . . . . . 103
Timing Requirements for AECLKIN for EMIFA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Switching Characteristics Over Recommended Operating Conditions for AECLKOUT1 for the
EMIFA Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
4−20
Switching Characteristics Over Recommended Operating Conditions for AECLKOUT2 for the
EMIFA Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
4−21
4−22
4−23
EMIFA Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Timing Requirements for Asynchronous Memory Cycles for EMIFA Module . . . . . . . . . . . . . . . . . . . . 106
Switching Characteristics Over Recommended Operating Conditions for Asynchronous Memory
Cycles for EMIFA Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
4−24
4−25
Timing Requirements for Programmable Synchronous Interface Cycles for EMIFA Module . . . . . . . 109
Switching Characteristics Over Recommended Operating Conditions for Programmable
Synchronous Interface Cycles for EMIFA Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
11
June 2003 − Revised October 2005
SPRS222E
Tables
Table
Page
Timing Requirements for Synchronous DRAM Cycles for EMIFA Module . . . . . . . . . . . . . . . . . . . . . . 113
Switching Characteristics Over Recommended Operating Conditions for Synchronous DRAM
Cycles for EMIFA Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
4−26
4−27
4−28
4−29
Timing Requirements for the HOLD/HOLDA Cycles for EMIFA Module . . . . . . . . . . . . . . . . . . . . . . . . 119
Switching Characteristics Over Recommended Operating Conditions for the HOLD/HOLDA
Cycles for EMIFA Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
4−30
Switching Characteristics Over Recommended Operating Conditions for the BUSREQ Cycles
for EMIFA Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
4−31
4−32
4−33
4−34
4−35
4−36
4−37
4−38
4−39
4−40
McASP0 Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
McASP0 Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Timing Requirements for McASP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Switching Characteristics Over Recommended Operating Conditions for McASP . . . . . . . . . . . . . . . 126
I2C0 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Timing Requirements for I2C Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Switching Characteristics for I2C Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
HPI Registers [DM641 Only] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Timing Requirements for Host-Port Interface Cycles [DM641 Only] . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Switching Characteristics Over Recommended Operating Conditions During Host-Port Interface
Cycles [DM641 Only] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
4−41
4−42
4−43
4−44
4−45
4−46
4−47
McBSP 0 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
McBSP 1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Timing Requirements for McBSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Switching Characteristics Over Recommended Operating Conditions for McBSP . . . . . . . . . . . . . . . 140
Timing Requirements for FSR When GSYNC = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Timing Requirements for McBSP as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0 . . . . . . . . . . 142
Switching Characteristics Over Recommended Operating Conditions for McBSP as SPI
Master or Slave: CLKSTP = 10b, CLKXP = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
4−48
4−49
Timing Requirements for McBSP as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0 . . . . . . . . . . 143
Switching Characteristics Over Recommended Operating Conditions for McBSP as SPI
Master or Slave: CLKSTP = 11b, CLKXP = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
4−50
4−51
Timing Requirements for McBSP as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1 . . . . . . . . . . 144
Switching Characteristics Over Recommended Operating Conditions for McBSP as SPI
Master or Slave: CLKSTP = 10b, CLKXP = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
4−52
4−53
Timing Requirements for McBSP as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1 . . . . . . . . . . 145
Switching Characteristics Over Recommended Operating Conditions for McBSP as SPI
Master or Slave: CLKSTP = 11b, CLKXP = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
4−54
4−55
4−56
4−57
4−58
Video Port 0 and 1 (VP0 and VP1) Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Timing Requirements for Video Capture Mode for VPxCLKINx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Timing Requirements in Video Capture Mode for Video Data and Control Inputs . . . . . . . . . . . . . . . . 150
Timing Requirements for Video Display Mode for VPxCLKINx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Timing Requirements in Video Display Mode for Video Control Input Shown With Respect to
VPxCLKINx and VPxCLKOUTx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
4−59
Switching Characteristics Over Recommended Operating Conditions in Video Display Mode
for Video Data and Control Output Shown With Respect to VPxCLKINx and VPxCLKOUTx . . . . . . 152
4−60
4−61
4−62
4−63
4−64
4−65
Timing Requirements for Dual-Display Sync Mode for VPxCLKINx . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
VCXO Interpolated Control (VIC) Port Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Timing Requirments for STCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Ethernet MAC (EMAC) Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
EMAC Statistics Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
EMAC Wrapper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
12
SPRS222E
June 2003 − Revised October 2005
Tables
Page
Table
4−66
4−67
4−68
4−69
4−70
EWRAP Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Timing Requirements for MRCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Timing Requirements for MTCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Timing Requirements for EMAC MII Receive 10/100 Mbit/s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Switching Characteristics Over Recommended Operating Conditions for EMAC MII Transmit
10/100 Mbit/s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
4−71
4−72
4−73
4−74
4−75
4−76
4−77
4−78
4−79
4−80
4−81
4−82
4−83
4−84
4−85
MDIO Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Timing Requirements for MDIO Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Switching Characteristics Over Recommended Operating Conditions for MDIO Output . . . . . . . . . . 163
Timer 0 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
Timer 1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
Timer 2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
Timing Requirements for Timer Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Switching Characteristics Over Recommended Operating Conditions for Timer Outputs . . . . . . . . . 165
GP0 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
Timing Requirements for GPIO Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
Switching Characteristics Over Recommended Operating Conditions for GPIO Outputs . . . . . . . . . 167
JTAG ID Register Selection Bit Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
JTAG ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
Timing Requirements for JTAG Test Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
Switching Characteristics Over Recommended Operating Conditions for JTAG Test Port . . . . . . . . 169
5−1
5−2
Thermal Resistance Characteristics (S-PBGA Package) [GDK] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Thermal Resistance Characteristics (S-PBGA Package) [GNZ] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
13
June 2003 − Revised October 2005
SPRS222E
Tables
This page intentionally left blank
14
SPRS222E
June 2003 − Revised October 2005
Device Overview
1
Device Overview
Features
1.1
D
High-Performance Digital Media Processor
(TMS320DM641/TMS320DM640)
− 1024M-Byte Total Addressable External
Memory Space
− 2.5-, 2-, 1.67-ns Instruction Cycle Time
− 400-, 500-, 600-MHz Clock Rate
− Eight 32-Bit Instructions/Cycle
− 3200, 4000, 4800 MIPS
D
D
Enhanced Direct-Memory-Access (EDMA)
Controller (64 Independent Channels)
10/100 Mb/s Ethernet MAC (EMAC)
− IEEE 802.3 Compliant
− Media Independent Interface (MII)
− 8 Independent Transmit (TX) Channels
and 1 Receive (RX) Channel
− Fully Software-Compatible With C64x™
D
VelociTI.2™ Extensions to VelociTI™
Advanced Very-Long-Instruction-Word
(VLIW) TMS320C64x™ DSP Core
− Eight Highly Independent Functional
Units With VelociTI.2™ Extensions:
− Six ALUs (32-/40-Bit), Each Supports
Single 32-Bit, Dual 16-Bit, or Quad
8-Bit Arithmetic per Clock Cycle
− Two Multipliers Support
D
D
D
Management Data Input/Output (MDIO)
Two Configurable Video Ports (DM641)
One Configurable Video Port (DM640)
− Providing a Glueless I/F to Common
Video Decoder and Encoder Devices
− Supports Multiple Resolutions and Video
Standards
Four 16 x 16-Bit Multiplies
(32-Bit Results) per Clock Cycle or
Eight 8 x 8-Bit Multiplies
(16-Bit Results) per Clock Cycle
− Load-Store Architecture With
Non-Aligned Support
− 64 32-Bit General-Purpose Registers
− Instruction Packing Reduces Code Size
− All Instructions Conditional
D
VCXO Interpolated Control Port (VIC)
− Supports Audio/Video Synchronization
D
D
Host-Port Interface (HPI) [16-Bit] (DM641)
Multichannel Audio Serial Port (McASP)
− Four Serial Data Pins
− Wide Variety of I2S and Similar Bit
Stream Format
− Integrated Digital Audio I/F Transmitter
Supports S/PDIF, IEC60958-1, AES-3,
CP-430 Formats
D
D
Instruction Set Features
− Byte-Addressable (8-/16-/32-/64-Bit Data)
− 8-Bit Overflow Protection
− Bit-Field Extract, Set, Clear
− Normalization, Saturation, Bit-Counting
− VelociTI.2™ Increased Orthogonality
L1/L2 Memory Architecture
− 128K-Bit (16K-Byte) L1P Program Cache
(Direct Mapped)
− 128K-Bit (16K-Byte) L1D Data Cache
(2-Way Set-Associative)
2
D
D
D
D
D
D
Inter-Integrated Circuit (I C) Bus
Two Multichannel Buffered Serial Ports
Three 32-Bit General-Purpose Timers
Eight General-Purpose I/O (GPIO) Pins
Flexible PLL Clock Generator
†
IEEE-1149.1 (JTAG )
Boundary-Scan-Compatible
D
D
548-Pin Ball Grid Array (BGA) Package
(GDK and ZDK Suffixes), 0.8-mm Ball Pitch
− 1M-Bit (128K-Byte) L2 Unified Mapped
RAM/Cache
(Flexible RAM/Cache Allocation)
548-Pin Ball Grid Array (BGA) Package
(GNZ and ZNZ Suffixes), 1.0-mm Ball Pitch
D
D
Endianess: Little Endian, Big Endian
D
D
D
0.13-µm/6-Level Cu Metal Process (CMOS)
3.3-V I/O, 1.2-V Internal (-400, -500)
3.3-V I/O, 1.4-V Internal (-600)
32-Bit External Memory Interface (EMIF)
− Glueless Interface to Asynchronous
Memories (SRAM and EPROM) and
Synchronous Memories (SDRAM,
SBSRAM, ZBT SRAM, and FIFO)
C64x, VelociTI.2, VelociTI, and TMS320C64x are trademarks of Texas Instruments.
All trademarks are the property of their respective owners.
†
IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
15
June 2003 − Revised October 2005
SPRS222E
Description
1.2
Description
The TMS320C64x™ DSPs (including the TMS320DM641 and TMS320DM640 devices) are the
highest-performance fixed-point DSP generation in the TMS320C6000™ DSP platform. The TMS320DM641
(DM641) and TMS320DM640 (DM640) devices are based on the second-generation high-performance,
advanced VelociTI™ very-long-instruction-word (VLIW) architecture (VelociTI.2™) developed by Texas
Instruments (TI), making these DSPs an excellent choice for digital media applications. The C64x™ is a
code-compatible member of the C6000™ DSP platform.
With performance of up to 4800 million instructions per second (MIPS) at a clock rate of 600 MHz, the DM641
device offers cost-effective solutions to high-performance DSP programming challenges.
With performance of up to 3200 million instructions per second (MIPS) at a clock rate of 400 MHz, the DM640
device offers cost-effective solutions to high-performance DSP programming challenges.
The DM641/DM640 DSP possesses the operational flexibility of high-speed controllers and the numerical
capability of array processors. The C64x™ DSP core processor has 64 general-purpose registers of 32-bit
word length and eight highly independent functional units—two multipliers for a 32-bit result and six arithmetic
logic units (ALUs)— with VelociTI.2™ extensions. The VelociTI.2™ extensions in the eight functional units
include new instructions to accelerate the performance in video and imaging applications and extend the
parallelism of the VelociTI™ architecture. The DM641 can produce four 16-bit multiply-accumulates (MACs)
per cycle for a total of 2400 million MACs per second (MMACS), or eight 8-bit MACs per cycle for a total of
4800 MMACS. The DM640 can produce four 16-bit multiply-accumulates (MACs) per cycle for a total of
1600 million MACs per second (MMACS), or eight 8-bit MACs per cycle for a total of 3200 MMACS. The
DM641/DM640 DSP also has application-specific hardware logic, on-chip memory, and additional on-chip
peripherals similar to the other C6000™ DSP platform devices.
The DM641/DM640 uses a two-level cache-based architecture and has a powerful and diverse set of
peripherals. The Level 1 program cache (L1P) is a 128-Kbit direct mapped cache and the Level 1 data cache
(L1D) is a 128-Kbit 2-way set-associative cache. The Level 2 memory/cache (L2) consists of a 1-Mbit memory
space that is shared between program and data space. L2 memory can be configured as mapped memory,
cache, or combinations of the two. The peripheral set includes: two configurable video ports (DM641); one
configurable video port (DM640); a 10/100 Mb/s Ethernet MAC (EMAC); a management data input/output
(MDIO) module; a VCXO interpolated control port (VIC); one 4-bit multichannel buffered audio serial port
(McASP0); an inter-integrated circuit (I2C) Bus module; two multichannel buffered serial ports (McBSPs);
three 32-bit general-purpose timers; a 16-bit host-port interface (HPI16) [DM641]; an 8-pin general-purpose
input/output port (GP0) with programmable interrupt/event generation modes; and a 32-bit glueless external
memory interface (EMIFA), which is capable of interfacing to synchronous and asynchronous memories and
peripherals.
The DM641 device has two single-channel 8-bit configurable video port peripherals (VP0 and VP1). The
DM640 device has one single-channel 8-bit configurable video port peripheral (VP0). These video port
peripherals provide a glueless interface to common video decoder and encoder devices. The DM641/DM640
video port peripherals support multiple resolutions and video standards (e. g., CCIR601 and ITU−BT.656).
These video port peripherals are configurable and can support either video capture and/or video display
modes.
For more details on the Video Port peripherals, see the TMS320C64x DSP Video Port/VCXO Interpolated
Control (VIC) Port Reference Guide (literature number SPRU629).
The McASP0 port supports one transmit and one receive clock zone, with four serial data pins which can be
individually allocated to any of the two zones. The serial port supports time-division multiplexing on each pin
from 2 to 32 time slots. The DM641/DM640 has sufficient bandwidth to support all 4 serial data pins
transmitting a 192-kHz stereo signal. Serial data in each zone may be transmitted and received on multiple
2
serial data pins simultaneously and formatted in a multitude of variations on the Philips Inter-IC Sound (I S)
format.
TMS320C6000, and C6000 are trademarks of Texas Instruments.
16
SPRS222E
June 2003 − Revised October 2005
Description
In addition, the McASP0 transmitter may be programmed to output multiple S/PDIF, IEC60958, AES-3,
CP-430 encoded data channels simultaneously, with a single RAM containing the full implementation of user
data and channel status fields.
McASP0 also provides extensive error-checking and recovery features, such as the bad clock detection circuit
for each high-frequency master clock which verifies that the master clock is within a programmed frequency
range.
The VCXO interpolated control (VIC) port provides digital-to-analog conversion with resolution from 9-bits to
up to 16-bits. The output of the VIC is a single bit interpolated D/A output. For more details on the VIC port,
see the TMS320C64x DSP Video Port/VCXO Interpolated Control (VIC) Port Reference Guide (literature
number SPRU629).
The ethernet media access controller (EMAC) provides an efficient interface between the DM641/DM640 DSP
core processor and the network. The DM641/DM640 EMAC support both 10Base-T and 100Base-TX, or 10
Mbits/second (Mbps) and 100 Mbps in either half- or full-duplex, with hardware flow control and quality of
service (QOS) support. The DM641/DM640 EMAC makes use of a custom interface to the DSP core that
allows efficient data transmission and reception. For more details on the EMAC, see the TMS320C6000 DSP
Ethernet Media Access Controller (EMAC) / Management Data Input/Output (MDIO) Module Reference
Guide (literature number SPRU628).
The management data input/output (MDIO) module continuously polls all 32 MDIO addresses in order to
enumerate all PHY devices in the system. Once a PHY candidate has been selected by the DSP, the MDIO
module transparently monitors its link state by reading the PHY status register. Link change events are stored
in the MDIO module and can optionally interrupt the DSP, allowing the DSP to poll the link status of the device
without continuously performing costly MDIO accesses. For more details on the MDIO, see the
TMS320C6000 DSP Ethernet Media Access Controller (EMAC) / Management Data Input/Output (MDIO)
Module Reference Guide (literature number SPRU628).
The I2C0 port on the TMS320DM641/DM640 allows the DSP to easily control peripheral devices and
communicate with a host processor. In addition, the standard multichannel buffered serial port (McBSP) may
be used to communicate with serial peripheral interface (SPI) mode peripheral devices.
The DM641/DM640 has a complete set of development tools which includes: a new C compiler, an assembly
optimizer to simplify programming and scheduling, and a Windows™ debugger interface for visibility into
source code execution.
Windows is a registered trademark of the Microsoft Corporation.
17
June 2003 − Revised October 2005
SPRS222E
Device Characteristics
1.3
Device Characteristics
Table 1−1 provides an overview of the DM641 DSP. The table shows significant features of the DM641 device,
including the capacity of on-chip RAM, the peripherals, the CPU frequency, and the package type with pin
count.
Table 1−1. Characteristics of the DM641 Processor
HARDWARE FEATURES
DM641
EMIFA (32-bit bus width)
(clock source = AECLKIN)
1
EDMA (64 independent channels)
McASP0 (uses Peripheral Clock [AUXCLK])
I2C0 (uses Peripheral Clock)
HPI (16-bit)
1
1
1
Peripherals
1 (HPI16)
McBSPs
Not all peripherals pins are
available at the same time
(For more detail, see the
Device Configuration
section).
2
(internal clock source = CPU/4 clock frequency)
Configurable Video Ports (VP0 and VP1)
10/100 Ethernet MAC (EMAC)
2
1
1
1
Management Data Input/Output (MDIO)
VCXO Interpolated Control Port (VIC)
32-Bit Timers
(internal clock source = CPU/8 clock frequency)
3
General-Purpose Input/Output Port (GP0)
Size (Bytes)
8
160K
16K-Byte (16KB) L1 Program (L1P) Cache
16KB L1 Data (L1D) Cache
128KB Unified Mapped RAM/Cache (L2)
0x0C01
On-Chip Memory
Organization
CPU ID + CPU Rev ID
JTAG BSDL_ID
Frequency
Control Status Register (CSR.[31:16])
JTAGID register (address location: 0x01B3F008)
MHz
0x0007902F
500, 600
2 ns (DM641-500)
[500-MHz CPU, 100 MHz EMIF ]
1.67 ns (DM641-600)
†
Cycle Time
ns
†
[600-MHz CPU, 133 MHz EMIF ]
1.2 V (-500)
1.4 V (-600)
Core (V)
Voltage
I/O (V)
3.3 V
PLL Options
CLKIN frequency multiplier
23 x 23 mm
Bypass (x1), x6, x12
548-Pin BGA (GDK and ZDK)
548-Pin BGA (GNZ and ZNZ)
0.13 µm
BGA Package
27 x 27 mm
Process Technology
µm
Product Preview (PP), Advance Information (AI),
or Production Data (PD)
‡
Product Status
PD
†
‡
On this DM64x™ device, the rated EMIF speed affects only the SDRAM interface on the EMIF. For more detailed information, see the EMIF device
speed portion of this data sheet.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard
warranty. Production processing does not necessarily include testing of all parameters.
18
SPRS222E
June 2003 − Revised October 2005
Device Characteristics
Table 1−2 provides an overview of the DM640 DSP. The table shows significant features of the DM640 device,
including the capacity of on-chip RAM, the peripherals, the CPU frequency, and the package type with pin
count.
Table 1−2. Characteristics of the DM640 Processor
HARDWARE FEATURES
DM640
EMIFA (32-bit bus width)
(clock source = AECLKIN)
1
EDMA (64 independent channels)
McASP0 (uses Peripheral Clock [AUXCLK])
I2C0 (uses Peripheral Clock)
1
1
1
Peripherals
McBSPs
2
Not all peripherals pins are
available at the same time
(For more detail, see the
Device Configuration
section).
(internal clock source = CPU/4 clock frequency)
Configurable Video Port (VP0)
1
1
1
1
10/100 Ethernet MAC (EMAC)
Management Data Input/Output (MDIO)
VCXO Interpolated Control Port (VIC)
32-Bit Timers
(internal clock source = CPU/8 clock frequency)
3
General-Purpose Input/Output Port (GP0)
Size (Bytes)
8
160K
16K-Byte (16KB) L1 Program (L1P) Cache
16KB L1 Data (L1D) Cache
128KB Unified Mapped RAM/Cache (L2)
0x0C01
On-Chip Memory
Organization
CPU ID + CPU Rev ID
JTAG BSDL_ID
Frequency
Control Status Register (CSR.[31:16])
JTAGID register (address location: 0x01B3F008)
MHz
0x0007902F
400
2.5 ns (DM640-400)
[400-MHz CPU, 100 MHz EMIF ]
Cycle Time
ns
†
Core (V)
1.2 V (-400)
Voltage
I/O (V)
3.3 V
PLL Options
CLKIN frequency multiplier
23 x 23 mm
Bypass (x1), x6, x12
548-Pin BGA (GDK and ZDK)
548-Pin BGA (GNZ and ZNZ)
0.13 µm
BGA Package
27 x 27 mm
Process Technology
µm
Product Preview (PP), Advance Information (AI),
or Production Data (PD)
‡
Product Status
PD
†
‡
On this DM64x™ device, the rated EMIF speed affects only the SDRAM interface on the EMIF. For more detailed information, see the EMIF device
speed portion of this data sheet.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard
warranty. Production processing does not necessarily include testing of all parameters.
19
June 2003 − Revised October 2005
SPRS222E
Device Compatibility
1.4
Device Compatibility
The DM641/DM640 device is a code-compatible member of the C6000™ DSP platform.
The C64x™ DSP generation of devices has a diverse and powerful set of peripherals. The common peripheral
set and pin-compatibility that the DM641 and DM640 devices offer lead to easier system designs and faster
time to market.
The DM640 device is a sub-set of the DM641 device and does not support an HPI peripheral or a second Video
Port (VP1) peripheral. Table 1−3 identifies the peripherals that are available on the DM641 and DM640
devices.
†‡
Table 1−3. Peripherals Available on the DM641 and DM640 Devices
PERIPHERALS/COPROCESSORS
EMIFA (32-bit bus width)
DM641
DM640
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
EDMA (64 independent channels)
10/100 EMAC
√
MDIO
√
HPI (16-bit)
—
√
McBSPs (McBSP0, McBSP1)
McASP (4-bit)
√
8-bit Video Port (VP0)
√
8-bit Video Port (VP1)
—
√
VIC
I2C
√
Timers (32-bit) [TIMER0, TIMER1, TIMER2]
GPIOs (GP[7:0])
√
√
†
‡
— denotes peripheral/coprocessor is not available on this device.
Not all peripherals pins are available at the same time. (For more details, see the Device
Configuration section.)
1.5
Functional Block Diagram
Figure 1−1 shows the functional block diagram of the DM641/DM640 devices.
20
SPRS222E
June 2003 − Revised October 2005
Functional Block Diagram
TMS320DM641/TMS320DM640
32
SDRAM
SBSRAM
ZBT SRAM
FIFO
EMIF A
Timer 2
Timer 1
Timer 0
L1P Cache
Direct-Mapped
16K Bytes Total
SRAM
VCXO
Interpolated
Control Port
(VIC)
ROM/FLASH
I/O Devices
C64x DSP Core
Instruction Fetch
Control
Registers
8-Bit
VP0
Instruction Dispatch
OR
Advanced Instruction Packet
Control
Logic
‡
Instruction Decode
McBSP0
Data Path A
Data Path B
AND
Test
A Register File
A31−A16
B Register File
B31−B16
McASP0
Control
Advanced
In-Circuit
Emulation
A15−A0
B15−B0
Enhanced
DMA
Controller
(EDMA)
L2
Cache
Memory
128KBytes
8-Bit
.L1 .S1 .M1 .D1
.D2 .M2 .S2 .L2
Interrupt
Control
†
VP1
OR
See Note A
‡
McBSP1
L1D Cache 2-Way Set-Associative
16K Bytes Total
AND
McASP0
Data
Power-Down
Logic
PLL
(x1, x6, x12)
†
HPI
EMAC
MDIO
8
GP0
I2C0
Boot Configuration
16
†
‡
HPI and VP1 are not supported on the DM640 device.
McBSPs: Framing Chips − H.100, MVIP, SCSA, T1, E1; AC97 Devices; SPI Devices; Codecs
NOTE A: The Video Port 0 (VP0) peripheral is muxed with the McBSP0 peripheral and the McASP0 control pins (DM641/DM640). The Video
Port 1 (VP1) peripheral is muxed with the McBSP1 peripheral and the McASP0 data pins (DM641 only). For more details on the
multiplexed pins of these peripherals, see the Device Configurations section of this data sheet.
Figure 1−1. Functional Block Diagram
21
June 2003 − Revised October 2005
SPRS222E
CPU (DSP Core) Description
1.6
CPU (DSP Core) Description
The CPU fetches VelociTI™ advanced very-long instruction words (VLIWs) (256 bits wide) to supply up to
eight 32-bit instructions to the eight functional units during every clock cycle. The VelociTI™ VLIW architecture
features controls by which all eight units do not have to be supplied with instructions if they are not ready to
execute. The first bit of every 32-bit instruction determines if the next instruction belongs to the same execute
packet as the previous instruction, or whether it should be executed in the following clock as a part of the next
execute packet. Fetch packets are always 256 bits wide; however, the execute packets can vary in size. The
variable-length execute packets are a key memory-saving feature, distinguishing the C64x CPUs from other
VLIW architectures. The C64x™ VelociTI.2™ extensions add enhancements to the TMS320C62x™ DSP
VelociTI™ architecture. These enhancements include:
•
•
•
•
•
•
Register file enhancements
Data path extensions
Quad 8-bit and dual 16-bit extensions with data flow enhancements
Additional functional unit hardware
Increased orthogonality of the instruction set
Additional instructions that reduce code size and increase register flexibility
The CPU features two sets of functional units. Each set contains four units and a register file. One set contains
functional units .L1, .S1, .M1, and .D1; the other set contains units .D2, .M2, .S2, and .L2. The two register
files each contain 32 32-bit registers for a total of 64 general-purpose registers. In addition to supporting the
packed 16-bit and 32-/40-bit fixed-point data types found in the C62x™ VelociTI™ VLIW architecture, the
C64x™ register files also support packed 8-bit data and 64-bit fixed-point data types. The two sets of functional
units, along with two register files, compose sides A and B of the CPU [see the functional block and CPU (DSP
core) diagram, and Figure 1−2]. The four functional units on each side of the CPU can freely share the 32
registers belonging to that side. Additionally, each side features a “data cross path”—a single data bus
connected to all the registers on the other side, by which the two sets of functional units can access data from
the register files on the opposite side. The C64x CPU pipelines data-cross-path accesses over multiple clock
cycles. This allows the same register to be used as a data-cross-path operand by multiple functional units in
the same execute packet. All functional units in the C64x CPU can access operands via the data cross path.
Register access by functional units on the same side of the CPU as the register file can service all the units
in a single clock cycle. On the C64x CPU, a delay clock is introduced whenever an instruction attempts to read
a register via a data cross path if that register was updated in the previous clock cycle.
In addition to the C62x™ DSP fixed-point instructions, the C64x™ DSP includes a comprehensive collection
of quad 8-bit and dual 16-bit instruction set extensions. These VelociTI.2™ extensions allow the C64x CPU
to operate directly on packed data to streamline data flow and increase instruction set efficiency. This is a key
factor for video and imaging applications.
Another key feature of the C64x CPU is the load/store architecture, where all instructions operate on registers
(as opposed to data in memory). Two sets of data-addressing units (.D1 and .D2) are responsible for all data
transfers between the register files and the memory. The data address driven by the .D units allows data
addresses generated from one register file to be used to load or store data to or from the other register file.
The C64x .D units can load and store bytes (8 bits), half-words (16 bits), and words (32 bits) with a single
instruction. And with the new data path extensions, the C64x .D unit can load and store doublewords (64 bits)
with a single instruction. Furthermore, the non-aligned load and store instructions allow the .D units to access
words and doublewords on any byte boundary. The C64x CPU supports a variety of indirect addressing modes
using either linear- or circular-addressing with 5- or 15-bit offsets. All instructions are conditional, and most
can access any one of the 64 registers. Some registers, however, are singled out to support specific
addressing modes or to hold the condition for conditional instructions (if the condition is not automatically
“true”).
TMS320C62x and C62x are trademarks of Texas Instruments.
22
SPRS222E
June 2003 − Revised October 2005
CPU (DSP Core) Description
The two .M functional units perform all multiplication operations. Each of the C64x .M units can perform two
16 × 16-bit multiplies or four 8 ×8-bit multiplies per clock cycle. The .M unit can also perform 16 ×32-bit multiply
operations, dual 16 × 16-bit multiplies with add/subtract operations, and quad 8 × 8-bit multiplies with add
operations. In addition to standard multiplies, the C64x .M units include bit-count, rotate, Galois field multiplies,
and bidirectional variable shift hardware.
The two .S and .L functional units perform a general set of arithmetic, logical, and branch functions with results
available every clock cycle. The arithmetic and logical functions on the C64x CPU include single 32-bit, dual
16-bit, and quad 8-bit operations.
The processing flow begins when a 256-bit-wide instruction fetch packet is fetched from a program memory.
The 32-bit instructions destined for the individual functional units are “linked” together by “1” bits in the least
significant bit (LSB) position of the instructions. The instructions that are “chained” together for simultaneous
execution (up to eight in total) compose an execute packet. A “0” in the LSB of an instruction breaks the chain,
effectively placing the instructions that follow it in the next execute packet. A C64x™ DSP device enhancement
now allows execute packets to cross fetch-packet boundaries. In the TMS320C62x™/TMS320C67x™ DSP
devices, if an execute packet crosses the fetch-packet boundary (256 bits wide), the assembler places it in
the next fetch packet, while the remainder of the current fetch packet is padded with NOP instructions. In the
C64x™ DSP device, the execute boundary restrictions have been removed, thereby, eliminating all of the
NOPs added to pad the fetch packet, and thus, decreasing the overall code size. The number of execute
packets within a fetch packet can vary from one to eight. Execute packets are dispatched to their respective
functional units at the rate of one per clock cycle and the next 256-bit fetch packet is not fetched until all the
execute packets from the current fetch packet have been dispatched. After decoding, the instructions
simultaneously drive all active functional units for a maximum execution rate of eight instructions every clock
cycle. While most results are stored in 32-bit registers, they can be subsequently moved to memory as bytes,
half-words, or doublewords. All load and store instructions are byte-, half-word-, word-, or
doubleword-addressable.
For more details on the C64x CPU functional units enhancements, see the following documents:
•
•
TMS320C6000 CPU and Instruction Set Reference Guide (literature number SPRU189)
TMS320C64x Technical Overview (literature number SPRU395)
TMS320C67x is a trademark of Texas Instruments.
23
June 2003 − Revised October 2005
SPRS222E
CPU (DSP Core) Description
src1
.L1
src2
dst
8
long dst
long src
8
32 MSBs
32 LSBs
ST1b (Store Data)
ST1a (Store Data)
8
long src
long dst
dst
8
Register
File A
(A0−A31)
src1
.S1
Data Path A
src2
See Note A
long dst
dst
See Note A
src1
.M1
src2
32 MSBs
32 LSBs
LD1b (Load Data)
LD1a (Load Data)
dst
DA1 (Address)
src1
.D1
.D2
src2
2X
1X
src2
src1
dst
DA2 (Address)
32 LSBs
32 MSBs
LD2a (Load Data)
LD2b (Load Data)
src2
src1
dst
.M2
See Note A
See Note A
long dst
Register
src2
File B
Data Path B
.S2
(B0− B31)
src1
dst
long dst
long src
8
8
32 MSBs
32 LSBs
ST2a (Store Data)
ST2b (Store Data)
8
long src
long dst
dst
8
src2
.L2
src1
Control Register
File
NOTE A: For the .M functional units, the long dst is 32 MSBs and the dst is 32 LSBs.
Figure 1−2. TMS320C64x™ CPU (DSP Core) Data Paths
24
SPRS222E
June 2003 − Revised October 2005
CPU (DSP Core) Description
1.6.1
CPU Core Registers
Table 1−4. L2 Cache Registers (C64x)
HEX ADDRESS RANGE
0184 0000
ACRONYM
REGISTER NAME
Cache configuration register
Reserved
COMMENTS
CCFG
0184 0004 − 0184 0FFC
0184 1000
−
EDMAWEIGHT L2 EDMA access control register
0184 1004 − 0184 1FFC
0184 2000
−
Reserved
L2ALLOC0
L2ALLOC1
L2ALLOC2
L2ALLOC3
−
L2 allocation register 0
0184 2004
L2 allocation register 1
0184 2008
L2 allocation register 2
0184 200C
L2 allocation register 3
0184 2010 − 0184 3FFC
0184 4000
Reserved
L2WBAR
L2WWC
L2WIBAR
L2WIWC
L2IBAR
L2IWC
L2 writeback base address register
L2 writeback word count register
L2 writeback invalidate base address register
L2 writeback invalidate word count register
L2 invalidate base address register
L2 invalidate word count register
L1P invalidate base address register
L1P invalidate word count register
L1D writeback invalidate base address register
L1D writeback invalidate word count register
Reserved
0184 4004
0184 4010
0184 4014
0184 4018
0184 401C
0184 4020
L1PIBAR
L1PIWC
L1DWIBAR
L1DWIWC
−
0184 4024
0184 4030
0184 4034
0184 4038 − 0184 4044
0184 4048
L1DIBAR
L1DIWC
−
L1D invalidate base address register
L1D invalidate word count register
Reserved
0184 404C
0184 4050 − 0184 4FFC
0184 5000
L2WB
L2 writeback all register
0184 5004
L2WBINV
−
L2 writeback invalidate all register
Reserved
0184 5008 − 0184 7FFC
MAR0 to
MAR127
0184 8000 −0184 81FC
Reserved
0184 8200
0184 8204
0184 8208
0184 820C
0184 8210
0184 8214
0184 8218
0184 821C
0184 8220
0184 8224
0184 8228
0184 822C
0184 8230
0184 8234
MAR128
MAR129
MAR130
MAR131
MAR132
MAR133
MAR134
MAR135
MAR136
MAR137
MAR138
MAR139
MAR140
MAR141
Controls EMIFA CE0 range 8000 0000 − 80FF FFFF
Controls EMIFA CE0 range 8100 0000 − 81FF FFFF
Controls EMIFA CE0 range 8200 0000 − 82FF FFFF
Controls EMIFA CE0 range 8300 0000 − 83FF FFFF
Controls EMIFA CE0 range 8400 0000 − 84FF FFFF
Controls EMIFA CE0 range 8500 0000 − 85FF FFFF
Controls EMIFA CE0 range 8600 0000 − 86FF FFFF
Controls EMIFA CE0 range 8700 0000 − 87FF FFFF
Controls EMIFA CE0 range 8800 0000 − 88FF FFFF
Controls EMIFA CE0 range 8900 0000 − 89FF FFFF
Controls EMIFA CE0 range 8A00 0000 − 8AFF FFFF
Controls EMIFA CE0 range 8B00 0000 − 8BFF FFFF
Controls EMIFA CE0 range 8C00 0000 − 8CFF FFFF
Controls EMIFA CE0 range 8D00 0000 − 8DFF FFFF
25
June 2003 − Revised October 2005
SPRS222E
CPU (DSP Core) Description
Table 1−4. L2 Cache Registers (C64x) (Continued)
HEX ADDRESS RANGE
0184 8238
0184 823C
0184 8240
0184 8244
0184 8248
0184 824C
0184 8250
0184 8254
0184 8258
0184 825C
0184 8260
0184 8264
0184 8268
0184 826C
0184 8270
0184 8274
0184 8278
0184 827C
0184 8280
0184 8284
0184 8288
0184 828C
0184 8290
0184 8294
0184 8298
0184 829C
0184 82A0
0184 82A4
0184 82A8
0184 82AC
0184 82B0
0184 82B4
0184 82B8
0184 82BC
0184 82C0
0184 82C4
0184 82C8
0184 82CC
0184 82D0
0184 82D4
0184 82D8
0184 82DC
0184 82E0
ACRONYM
REGISTER NAME
COMMENTS
MAR142
MAR143
MAR144
MAR145
MAR146
MAR147
MAR148
MAR149
MAR150
MAR151
MAR152
MAR153
MAR154
MAR155
MAR156
MAR157
MAR158
MAR159
MAR160
MAR161
MAR162
MAR163
MAR164
MAR165
MAR166
MAR167
MAR168
MAR169
MAR170
MAR171
MAR172
MAR173
MAR174
MAR175
MAR176
MAR177
MAR178
MAR179
MAR180
MAR181
MAR182
MAR183
MAR184
Controls EMIFA CE0 range 8E00 0000 − 8EFF FFFF
Controls EMIFA CE0 range 8F00 0000 − 8FFF FFFF
Controls EMIFA CE1 range 9000 0000 − 90FF FFFF
Controls EMIFA CE1 range 9100 0000 − 91FF FFFF
Controls EMIFA CE1 range 9200 0000 − 92FF FFFF
Controls EMIFA CE1 range 9300 0000 − 93FF FFFF
Controls EMIFA CE1 range 9400 0000 − 94FF FFFF
Controls EMIFA CE1 range 9500 0000 − 95FF FFFF
Controls EMIFA CE1 range 9600 0000 − 96FF FFFF
Controls EMIFA CE1 range 9700 0000 − 97FF FFFF
Controls EMIFA CE1 range 9800 0000 − 98FF FFFF
Controls EMIFA CE1 range 9900 0000 − 99FF FFFF
Controls EMIFA CE1 range 9A00 0000 − 9AFF FFFF
Controls EMIFA CE1 range 9B00 0000 − 9BFF FFFF
Controls EMIFA CE1 range 9C00 0000 − 9CFF FFFF
Controls EMIFA CE1 range 9D00 0000 − 9DFF FFFF
Controls EMIFA CE1 range 9E00 0000 − 9EFF FFFF
Controls EMIFA CE1 range 9F00 0000 − 9FFF FFFF
Controls EMIFA CE2 range A000 0000 − A0FF FFFF
Controls EMIFA CE2 range A100 0000 − A1FF FFFF
Controls EMIFA CE2 range A200 0000 − A2FF FFFF
Controls EMIFA CE2 range A300 0000 − A3FF FFFF
Controls EMIFA CE2 range A400 0000 − A4FF FFFF
Controls EMIFA CE2 range A500 0000 − A5FF FFFF
Controls EMIFA CE2 range A600 0000 − A6FF FFFF
Controls EMIFA CE2 range A700 0000 − A7FF FFFF
Controls EMIFA CE2 range A800 0000 − A8FF FFFF
Controls EMIFA CE2 range A900 0000 − A9FF FFFF
Controls EMIFA CE2 range AA00 0000 − AAFF FFFF
Controls EMIFA CE2 range AB00 0000 − ABFF FFFF
Controls EMIFA CE2 range AC00 0000 − ACFF FFFF
Controls EMIFA CE2 range AD00 0000 − ADFF FFFF
Controls EMIFA CE2 range AE00 0000 − AEFF FFFF
Controls EMIFA CE2 range AF00 0000 − AFFF FFFF
Controls EMIFA CE3 range B000 0000 − B0FF FFFF
Controls EMIFA CE3 range B100 0000 − B1FF FFFF
Controls EMIFA CE3 range B200 0000 − B2FF FFFF
Controls EMIFA CE3 range B300 0000 − B3FF FFFF
Controls EMIFA CE3 range B400 0000 − B4FF FFFF
Controls EMIFA CE3 range B500 0000 − B5FF FFFF
Controls EMIFA CE3 range B600 0000 − B6FF FFFF
Controls EMIFA CE3 range B700 0000 − B7FF FFFF
Controls EMIFA CE3 range B800 0000 − B8FF FFFF
26
SPRS222E
June 2003 − Revised October 2005
CPU (DSP Core) Description
Table 1−4. L2 Cache Registers (C64x) (Continued)
HEX ADDRESS RANGE
0184 82E4
ACRONYM
REGISTER NAME
COMMENTS
MAR185
MAR186
MAR187
MAR188
MAR189
MAR190
MAR191
Controls EMIFA CE3 range B900 0000 − B9FF FFFF
Controls EMIFA CE3 range BA00 0000 − BAFF FFFF
Controls EMIFA CE3 range BB00 0000 − BBFF FFFF
Controls EMIFA CE3 range BC00 0000 − BCFF FFFF
Controls EMIFA CE3 range BD00 0000 − BDFF FFFF
Controls EMIFA CE3 range BE00 0000 − BEFF FFFF
Controls EMIFA CE3 range BF00 0000 − BFFF FFFF
0184 82E8
0184 82EC
0184 82F0
0184 82F4
0184 82F8
0184 82FC
MAR192 to
MAR255
0184 8300 −0184 83FC
0184 8400 −0187 FFFF
Reserved
Reserved
−
27
June 2003 − Revised October 2005
SPRS222E
Memory Map Summary
1.7
Memory Map Summary
Table 1−5 shows the memory map address ranges of the DM641/DM640 device. Internal memory is always
located at address 0 and can be used as both program and data memory. The external memory address
ranges in the DM641/DM640 device begin at the hex address location 0x8000 0000 for EMIFA.
Table 1−5. TMS320DM641/DM640 Memory Map Summary
BLOCK SIZE
MEMORY BLOCK DESCRIPTION
Internal RAM (L2)
HEX ADDRESS RANGE
(BYTES)
128K
768K
23M
0000 0000 – 0001 FFFF
0004 0000 – 000F FFFF
0010 0000 – 017F FFFF
0180 0000 – 0183 FFFF
0184 0000 – 0187 FFFF
0188 0000 – 018B FFFF
018C 0000 – 018F FFFF
0190 0000 – 0193 FFFF
0194 0000 – 0197 FFFF
0198 0000 – 019B FFFF
019C 0000 – 019F FFFF
01A0 0000 – 01A3 FFFF
01A4 0000 – 01AB FFFF
01AC 0000 – 01AF FFFF
01B0 0000 – 01B3 EFFF
01B3 F000 – 01B3 FFFF
01B4 0000 – 01B4 3FFF
01B4 4000 – 01B4 BFFF
01B4 C000 – 01B4 FFFF
01B5 0000 – 01B7 FFFF
01B8 0000 – 01BB FFFF
01BC 0000 – 01BF FFFF
01C0 0000 – 01C3 FFFF
01C4 0000 – 01C4 3FFF
01C4 4000 – 01C4 7FFF
01C4 8000 – 01C4 FFFF
01C5 0000 – 01C7 FFFF
01C8 0000 – 01C8 0FFF
01C8 1000 – 01C8 2FFF
01C8 3000 – 01C8 37FF
01C8 3800 – 01C8 3FFF
01C8 4000 – 01FF FFFF
0200 0000 – 0200 0033
0200 0034 – 2FFF FFFF
3000 0000 – 33FF FFFF
Reserved
Reserved
External Memory Interface A (EMIFA) Registers
L2 Registers
256K
256K
256K
256K
256K
256K
256K
256K
256K
512K
256K
256K − 4K
4K
†
HPI Registers (DM641 only)
McBSP 0 Registers
McBSP 1 Registers
Timer 0 Registers
Timer 1 Registers
Interrupt Selector Registers
EDMA RAM and EDMA Registers
Reserved
Timer 2 Registers
GP0 Registers
Device Configuration Registers
I2C0 Data and Control Registers
Reserved
16K
32K
McASP0 Control Registers
Reserved
16K
192K
256K
256K
256K
16K
Reserved
Emulation
Reserved
VP0 Control
†
VP1 Control (DM641 only)
16K
Reserved
32K
Reserved
192K
4K
EMAC Control
EMAC Wrapper
EWRAP Registers
MDIO Control Registers
Reserved
8K
2K
2K
3.5M
52
QDMA Registers
Reserved
928M – 52
64M
McBSP 0 Data
†
For the DM640 device, these memory address locations are reserved.The DM640 device does not support the HPI and VP1 peripherals.
28
SPRS222E
June 2003 − Revised October 2005
Memory Map Summary
Table 1−5. TMS320DM641/DM640 Memory Map Summary (Continued)
BLOCK SIZE
(BYTES)
MEMORY BLOCK DESCRIPTION
McBSP 1 Data
HEX ADDRESS RANGE
64M
64M
3400 0000 – 37FF FFFF
3800 0000 – 3BFF FFFF
3C00 0000 – 3C0F FFFF
3C10 0000 – 3FFF FFFF
4000 0000 – 73FF FFFF
7400 0000 – 75FF FFFF
7600 0000 – 77FF FFFF
7800 0000 – 79FF FFFF
7A00 0000 – 7BFF FFFF
7C00 0000 – 7FFF FFFF
8000 0000 – 8FFF FFFF
9000 0000 – 9FFF FFFF
A000 0000 – AFFF FFFF
B000 0000 – BFFF FFFF
C000 0000 – FFFF FFFF
Reserved
McASP0 Data
Reserved
1M
64M − 1M
832M
32M
Reserved
VP0 Channel A Data
Reserved
32M
†
VP1 Channel A Data (DM641 only)
Reserved
32M
32M
Reserved
64M
EMIFA CE0
256M
256M
256M
256M
1G
EMIFA CE1
EMIFA CE2
EMIFA CE3
Reserved
†
For the DM640 device, these memory address locations are reserved.The DM640 device does not support the HPI and VP1 peripherals.
29
June 2003 − Revised October 2005
SPRS222E
Memory Map Summary
1.7.1
L2 Architecture Expanded
Figure 1−3 shows the detail of the L2 architecture on the TMS320DM641/DM640 devices. For more
information on the L2MODE bits, see the cache configuration (CCFG) register bit field descriptions in the
TMS320C64x Two-Level Internal Memory Reference Guide (literature number SPRU610).
†
L2MODE
L2 Memory
Block Base Address
000
001
010
011
0x0000 0000
64K-Byte RAM
0x0001 0000
0x0001 8000
32K-Byte RAM
32K-Byte RAM
0x0001 FFFF
0x0002 0000
†
The L2MODE = 111b is not supported on the DM641/DM640 devices.
Figure 1−3. TMS320DM641/DM640 L2 Architecture Memory Configuration
30
SPRS222E
June 2003 − Revised October 2005
Bootmode
1.8
Bootmode
The DM641/DM640 device resets using the active-low signal RESET. While RESET is low, the device is held
in reset and is initialized to the prescribed reset state. Refer to reset timing for reset timing characteristics and
states of device pins during reset. The release of RESET starts the processor running with the prescribed
device configuration and boot mode.
The DM641 has three types of boot modes while the DM640 has only two types of boot modes:
•
Host boot [DM641 only]
If host boot is selected, upon release of RESET, the CPU is internally “stalled” while the remainder of the
device is released. During this period, an external host can initialize the CPU’s memory space as
necessary through the host interface, including internal configuration registers, such as those that control
the EMIF or other peripherals. For the DM641 device, the HPI peripheral is used for host boot. Once the
host is finished with all necessary initialization, it must set the DSPINT bit in the HPIC register to complete
the boot process. This transition causes the boot configuration logic to bring the CPU out of the “stalled”
state. The CPU then begins execution from address 0. The DSPINT condition is not latched by the CPU,
because it occurs while the CPU is still internally “stalled”. Also, DSPINT brings the CPU out of the “stalled”
state only if the host boot process is selected. All memory may be written to and read by the host. This
allows for the host to verify what it sends to the DSP if required. After the CPU is out of the “stalled” state,
the CPU needs to clear the DSPINT, otherwise, no more DSPINTs can be received.
•
•
EMIF boot (using default ROM timings)
Upon the release of RESET, the 1K-Byte ROM code located in the beginning of CE1 is copied to address 0
by the EDMA using the default ROM timings, while the CPU is internally “stalled”. The data should be
stored in the endian format that the system is using. In this case, the EMIF automatically assembles
consecutive 8-bit bytes to form the 32-bit instruction words to be copied. The transfer is automatically done
by the EDMA as a single-frame block transfer from the ROM to address 0. After completion of the block
transfer, the CPU is released from the “stalled” state and starts running from address 0.
No boot
With no boot, the CPU begins direct execution from the memory located at address 0. Note: operation is
undefined if invalid code is located at address 0.
31
June 2003 − Revised October 2005
SPRS222E
Pin Assignments
1.9
Pin Assignments
On Quadrants A, B, C, and D, shading denotes pin assignments that have different functionality between the
DM641 and DM640 devices [DM640 denoted within ( )]. See the Terminal Functions table for details.
1.9.1
AF
AE
AD
AC
AB
AA
Y
Pin Map
1
2
3
4
5
6
7
8
9
10
11
12
13
VP1CTL0
(RSV15)
RSV13
RSV14
VP1CLK0
(RSV13)
VP1CLK1
(RSV14)
V
DV
RSV04
V
SS
V
SS
VP0CLK1
V
SS
V
SS
SS
DD
DD
(RSV18)
(RSV19)
VP1CTL1
(RSV16)
VP1D[0]/
CLKX1
VP1D[3]/
CLKS1
RSV15
CLKMODE1
DV
DV
V
SS
V
SS
V
SS
AXR0[3]
V
SS
DV
DD
DD
(RSV21)
VP1CTL2
(RSV17)
VP1D[1]/
FSX1
VP1D[4]/
DR1
VP1D[6]/
CLKR1
RSV16
VDAC
V
SS
RSV03
V
SS
AXR0[1]
AXR0[2]
RSV17
AFSX0
AMUTEIN0
(RSV22)
(RSV23)
VP1D[2]/
DX1
VP1D[5]/
FSR1
VP1D[7]
(RSV20)
RSV18
STCLK
CLKIN
V
SS
RSV02
V
SS
AXR0[0]
AHCLKX0
AMUTE0
ACLKX0
(RSV24)
RSV19
RSV20
V
V
SS
RSV01
RSV00
V
V
DV
DD
V
SS
DV
DD
CV
DD
CV
DD
DV
DD
V
SS
DV
DD
SS
SS
(RSV25)
(RSV26)
HD1
CLKMODE0
V
SS
CV
CV
V
V
SS
DV
DD
V
SS
V
SS
DV
DD
V
SS
SS
DD
DD
(RSV111)
HD5
HD3
HD0
HD2
DV
DV
CV
DD
V
SS
CV
DD
CV
DD
V
SS
CV
DD
DD
(RSV115)
(RSV113)
(RSV110)
(RSV112)
HD7
HD4
HD6
W
V
RSV06
SS
DD
SS
(RSV117)
(RSV114)
(RSV116)
HD10
HD8
HD9
RSV54
V
V
SS
PLLV
V
SS
(RSV120)
(RSV118)
(RSV119)
(RSV60)
HD14
HD12
HD13
HD11
U
DV
V
V
CV
CV
V
DD
SS
DD
(RSV124)
(RSV122)
(RSV123)
(RSV121)
HDS2
HD15
RSV55
T
V
SS
V
SS
SS
DD
(RSV101)
(RSV125)
(RSV61)
HCNTL0
(RSV106)
HCS
HDS1
RSV56
R
RSV08
V
SS
CV
DD
MDCLK
SS
(RSV109)
(RSV100)
(RSV62)
HCNTL1
HAS
P
MDIO
V
SS
RESET
V
SS
CV
DD
CV
DD
V
SS
(RSV107)
(RSV108)
1
2
3
4
5
6
7
8
9
10
11
12
13
Figure 1−4. DM641/DM640 Pin Map [Quadrant A]
32
SPRS222E
June 2003 − Revised October 2005
Pin Assignments
14
15
16
17
18
19
20
21
22
23
24
25
26
VP0D[1]/
FSX0
VP0D[0]/
CLKX0
RSV76
RSV80
RSV88
RSV89
AF
VP0CLK0
V
SS
RSV09
V
SS
V
SS
DV
DD
V
SS
(RSV82)
(RSV86)
(RSV94)
(RSV95)
VP0D[6]/
CLKR0
VP0D[2]/
DX0
RSV78
RSV82
RSV84
RSV87
AE
AD
AC
AB
AA
Y
V
VP0CTL0
VP0CTL2
VP0CTL1
RSV10
V
V
DV
DV
DD
SS
SS
SS
DD
(RSV84)
(RSV88)
(RSV90)
(RSV93)
VP0D[3]/
CLKS0
RSV74
RSV79
RSV83
RSV85
RSV86
RSV59
RSV58
VP0D[7]
RSV11
RSV12
V
SS
DV
ACLKR0
AFSR0
DD
(RSV80)
(RSV85)
(RSV89)
(RSV91)
(RSV92)
(RSV65)
(RSV64)
VP0D[4]/
DR0
RSV75
RSV77
RSV81
RSV60
RSV61
V
SS
V
SS
DV
DD
V
SS
(RSV81)
(RSV83)
(RSV87)
(RSV66)
(RSV67)
VP0D[5]/
FSR0
RSV64
RSV62
RSV63
AHCLKR0
DV
DD
V
SS
DV
DV
DD
CV
DD
CV
DD
CV
DD
V
SS
DV
DD
V
SS
DD
(RSV70)
(RSV68)
(RSV69)
DV
DD
V
SS
V
SS
DV
DD
V
SS
CV
V
SS
RSV67
RSV65
RSV66
RSV68
DD
DD
V
SS
(RSV73)
(RSV71)
(RSV72)
(RSV74)
RSV71
RSV69
RSV70
RSV72
CV
V
SS
CV
DD
CV
DD
V
SS
CV
CV
DV
DV
DD
DD
DD
(RSV77)
(RSV75)
(RSV76)
(RSV78)
RSV73
W
V
V
SS
AHOLD
AEA21
AEA17
AEA14
AEA11
DV
DD
V
SS
DD
(RSV79)
V
SS
DV
DD
V
SS
AEA18
AEA22
AEA20
AEA16
AEA13
AEA19
AEA15
U
CV
V
SS
DV
DD
DD
DD
RSV93
RSV92
T
CV
V
SS
V
SS
(RSV99)
(RSV98)
RSV91
RSV90
R
V
SS
CV
DD
V
SS
DV
DD
ASOE3
AEA12
(RSV97)
(RSV96)
P
CV
DD
V
SS
CV
DD
V
SS
ABUSREQ
AEA10
AEA9
DV
DD
AEA8
14
15
16
17
18
19
20
21
22
23
24
25
26
Figure 1−4. DM641/DM640 Pin Map (Continued) [Quadrant B]
33
June 2003 − Revised October 2005
SPRS222E
Pin Assignments
1
2
3
4
5
6
7
8
9
10
11
12
13
HRDY
HHWIL
HINT
N
DV
DD
V
SS
V
SS
CV
DD
V
SS
CV
DD
(RSV105)
(RSV104)
(RSV103)
HR/W
M
L
MTXD1
MTXD3
MCOL
MTXD0
MTXEN
MTXD2
MTCLK
GP0[0]
GP0[3]
DV
V
CV
V
SS
DD
SS
DD
(RSV102)
V
SS
V
V
CV
CV
SS
DD
HD24/
AD24/
RSV57
RSV46
K
J
DV
DD
SS
DD
(RSV63)
(RSV52)
MRXD0
RSV47
MRXD1
MRXD2
MCRS
MRXDV
V
SS
DV
DD
V
SS
(RSV53)
RSV49
H
G
F
MRXD3
V
SS
DV
DV
V
SS
RSV07
DD
(RSV55)
RSV52
RSV50
CV
CV
CV
CV
DV
CV
V
CV
CV
V
SS
CV
DD
MRCLK
MRXER
GP0[6]/
DD
DD
DD
DD
DD
DD
SS
DD
DD
(RSV58)
(RSV56)
RSV48
GP0[5]/
GP0[4]/
V
SS
V
SS
DV
V
SS
V
SS
DV
DD
V
SS
DD
DD
(RSV54)
EXT_INT6 EXT_INT5 EXT_INT4
GP0[7]/
RSV53
(RSV59)
RSV40
RSV44
RSV45
E
D
C
B
A
V
SS
SCL0
DV
DD
V
SS
DV
DD
V
SS
DV
DD
EXT_INT7
(RSV46)
(RSV50)
(RSV51)
CLKOUT4/
GP0[1]
RSV24
RSV27
RSV31
RSV35
RSV39
RSV43
V
SS
V
SDA0
DV
DD
V
SS
V
SS
V
SS
V
SS
SS
SS
(RSV30)
(RSV33)
(RSV37)
(RSV41)
(RSV45)
(RSV49)
RSV51
TOUT0/
CLKOUT6/
GP0[2]
RSV25
RSV26
RSV30
RSV34
RSV38
RSV42
V
DV
DD
V
SS
(RSV57)
MAC_EN
(RSV31)
(RSV32)
(RSV36)
(RSV40)
(RSV44)
(RSV48)
TOUT1/
RSV23
RSV29
RSV33
RSV37
RSV41
DV
DD
DV
DV
V
V
NMI
V
V
SS
DD
SS
SS
SS
LENDIAN
(RSV29)
(RSV35)
(RSV39)
(RSV43)
(RSV47)
RSV21
RSV28
RSV32
RSV36
RSV22
V
SS
TINP0
TINP1
V
V
SS
V
SS
DD
SS
(RSV27)
(RSV34)
(RSV38)
(RSV42)
(RSV28)
1
2
3
4
5
6
7
8
9
10
11
12
13
Figure 1−4. DM641/DM640 Pin Map (Continued) [Quadrant C]
34
SPRS222E
June 2003 − Revised October 2005
Pin Assignments
14
15
16
17
18
19
20
21
22
23
24
25
26
N
V
SS
CV
DD
CV
DD
V
SS
AHOLDA
AEA7
AEA6
V
SS
AEA5
M
CV
DD
V
SS
V
DV
DD
APDT
AEA4
ABE1
AEA3
ABE0
ACE1
ABE3
ABE2
SS
L
CV
V
V
AARDY
ASDCKE
ACE0
ACE3
DD
DD
SS
AAWE/
ASDWE/
ASWE
K
J
CV
DV
DD
ACE2
SS
AARE/
ASDCAS/
ASADS/
ASRE
AAOE/
ASDRAS/
ASOE
AECLKOUT2
V
SS
DV
DD
V
SS
AECLKOUT1
H
G
F
CV
CV
CV
DV
V
DV
DV
AED17
AED19
AED23
AED16
AED21
AED25
AED27
AECLKIN
AED20
AED24
AED26
AED28
AED30
V
SS
DD
DD
DD
DD
SS
DD
CV
V
CV
CV
V
CV
CV
CV
AED18
AED22
DD
SS
DD
DD
SS
DD
DD
DD
V
SS
DV
V
V
SS
DV
V
SS
V
SS
DD
SS
SS
DD
DD
E
D
C
B
A
RSV05
TRST
EMU1
TMS
V
DV
DD
V
V
V
DV
DD
V
SS
DV
DD
V
SS
V
SS
SS
EMU4
EMU3
EMU2
EMU8
EMU6
EMU5
EMU11
EMU10
EMU9
AED14
AED15
AED12
AED10
AED11
AED8
AED6
AED7
V
SS
DV
DD
V
SS
AED29
AED31
SS
SS
AED4
AED3
V
SS
DV
DD
DV
DD
TDO
V
AED2
AED0
DV
DV
DV
DD
SS
SS
DD
V
SS
EMU0
TCK
EMU7
TDI
V
AED13
AED9
V
SS
AED5
AED1
V
SS
DD
14
15
16
17
18
19
20
21
22
23
24
25
26
Figure 1−4. DM641/DM640 Pin Map (Continued) [Quadrant D]
35
June 2003 − Revised October 2005
SPRS222E
Pin Assignments
1.9.2
Signal Groups Description
RESET
NMI
GP0[7]/EXT_INT7
GP0[6]/EXT_INT6
GP0[5]/EXT_INT5
GP0[4]/EXT_INT4
CLKIN
†
‡
‡
‡
‡
CLKOUT4/GP0[1]
CLKOUT6/GP0[2]
Reset and
Interrupts
†
Clock/PLL
CLKMODE1
CLKMODE0
PLLV
RSV00
RSV01
RSV02
TMS
TDO
TDI
TCK
Reserved
TRST
EMU0
EMU1
EMU2
EMU3
EMU4
EMU5
EMU6
EMU7
EMU8
EMU9
EMU10
EMU11
RSV91(123)
RSV92(124)
RSV93(125)
IEEE Standard
1149.1
(JTAG)
Emulation
Peripheral
Control/Status
TOUT0/MAC_EN
Control/Status
‡
GP0[3]
GP0[7]/EXT_INT7
GP0[6]/EXT_INT6
GP0[5]/EXT_INT5
GP0[4]/EXT_INT4
†
‡
‡
‡
CLKOUT6/GP0[2]
CLKOUT4/GP0[1]
GP0[0]
GP0
(8-Bit)
†
General-Purpose Input/Output 0 (GP0) Port
†
These pins are muxed with the GP0 pins and by default these signals function as clocks (CLKOUT4 or CLKOUT6). To use these
muxed pins as GPIO signals, the appropriate GPIO register bits (GPxEN and GPxDIR) must be properly enabled and configured.
For more details, see the Device Configurations section of this data sheet.
‡
These pins are GP0 pins that can also function as external interrupt sources (EXT_INT[7:4]). Default after reset is EXT_INTx or
GPIO as input-only.
Figure 1−5. CPU and Peripheral Signals
36
SPRS222E
June 2003 − Revised October 2005
Pin Assignments
32
Data
AED[31:0]
AECLKIN
AECLKOUT1
AECLKOUT2
ASDCKE
ACE3
ACE2
Memory Map
Space Select
External
Memory I/F
Control
AARE/ASDCAS/ASADS/ASRE
ACE1
ACE0
AAOE/ASDRAS/ASOE
AAWE/ASDWE/ASWE
AARDY
20
Address
AEA[22:3]
ASOE3
APDT
ABE3
ABE2
ABE1
ABE0
Byte Enables
AHOLD
Bus
Arbitration
AHOLDA
ABUSREQ
EMIFA (32-bit)
Data
VDAC
VCXO Interpolated
Control Port (VIC)
HPI
(Host-Port Interface)
[DM641 only]
16
Data
HD[15:0]
HAS
HR/W
HCS
HDS1
HDS2
HRDY
HCNTL0
HCNTL1
Register Select
Control
Half-Word
Select
HHWIL
HINT
Figure 1−6. Peripheral Signals
37
June 2003 − Revised October 2005
SPRS222E
Pin Assignments
DM641/DM640
McBSP1
McBSP0
Transmit
†‡
†§
VP0D[0]/CLKX0
VP1D[0]/CLKX1
VP1D[1]/FSX1
†‡
†§
VP0D[1]/FSX0
Transmit
†‡
†§
VP0D[2]/DX0
VP1D[2]/DX1
†§
†§
†§
†‡
†‡
VP1D[6]/CLKR1
VP1D[5]/FSR1
VP1D[4]/DR1
VP0D[6]/CLKR0
VP0D[5]/FSR0
Receive
Clock
Receive
Clock
†‡
VP0D[4]/DR0
†‡
†§
VP0D[3]/CLKS0
VP1D[3]/CLKS1
McBSPs
(Multichannel Buffered Serial Ports)
TOUT1/LENDIAN
TINP1
TOUT0/MAC_EN
TINP0
Timer 0
Timer 1
Timer 2
Timers
SCL0
SDA0
I2C0
I2C0
†
For DM641, these McBSP1 and McBSP0 pins are muxed with the Video Port 1 (VP1) and Video Port 0 (VP0) peripherals, respectively. By
default, these signals function as VP1 and VP0, respectively. For more details on these muxed pins, see the Device Configurations section
of this data sheet.
For DM640, these McBSP0 pins are muxed with the Video Port 0 (VP0) peripheral. By default, these signals function as VP0. For more details
on these muxed pins, see the Device Configurations section of this data sheet.
‡
§
The DM640 device does not support the VP1 peripheral; therefore, the McBSP1 peripheral pins are standalone perpheral functions, not
muxed.
Figure 1−6. Peripheral Signals (Continued)
38
SPRS222E
June 2003 − Revised October 2005
Pin Assignments
EMAC
MTXD0
MTXD1
MTXD2
MTXD3
Transmit
MDIO
MRXD0
MRXD1
MRXD2
MRXD3
Receive
MDIO
Input/Output
MTXEN
Clock
MDCLK
MRXER
MRXDV
MCOL
Error Detect
and Control
MCRS
MTCLK
MRCLK
Clocks
Ethernet MAC (EMAC)
and MDIO
Figure 1−6. Peripheral Signals (Continued)
39
June 2003 − Revised October 2005
SPRS222E
Pin Assignments
STCLK
VP0CLK0
VP0CLK1
VP0CTL0
VP0CTL1
VP0CTL2
Timing and
Control Logic
VP0D[0]/CLKX0
VP0D[1]/FSX0
VP0D[2]/DX0
VP0D[4]/DR0
VP0D[5]/FSR0
VP0D[6]/CLKR0
VP0D[7]
Capture/Display
Buffer
(2560 Bytes)
VP0D[3]/CLKS0
†
Channel A
Video Port 0 (VP0)
†
Channel A supports: BT.656 (8-bit) display pipeline mode and BT.656 (8-bit) capture pipeline mode [TSI (8-bit) capture
pipeline mode].
Figure 1−6. Peripheral Signals (Continued)
40
SPRS222E
June 2003 − Revised October 2005
Pin Assignments
‡
STCLK
VP1CLK0
VP1CLK1
VP1CTL0
VP1CTL1
VP1CTL2
Timing and
Control Logic
VP1D[0]/CLKX1
VP1D[1]/FSX1
VP1D[2]/DX1
VP1D[4]/DR1
Capture/Display
Buffer
(2560 Bytes)
VP1D[5]/FSR1
VP1D[6]/CLKR1
VP1D[7]
VP1D[3]/CLKS1
†
Channel A
Video Port 1 (VP1) [DM641 only]
†
‡
Channel A supports: BT.656 (8-bit) display pipeline mode and BT.656 (8-bit) capture pipeline mode [TSI (8-bit) capture
pipeline mode].
For DM641, the same STCLK signal is used for both video ports (VP0 and VP1).
Figure 1−6. Peripheral Signals (Continued)
41
June 2003 − Revised October 2005
SPRS222E
Pin Assignments
(Transmit/Receive Data Pins)
(Transmit/Receive Data Pins)
8-Serial Ports
Flexible
Partitioning
Tx, Rx, OFF
AXR0[0]
AXR0[1]
AXR0[2]
AXR0[3]
(Transmit Bit Clock)
(Receive Bit Clock)
Transmit
Clock
Generator
Receive Clock
Generator
ACLKX0
ACLKR0
AHCLKR0
AHCLKX0
(Receive Master Clock)
(Transmit Master Clock)
Transmit
Clock Check
Circuit
Receive Clock
Check Circuit
Receive
Frame Sync
Transmit
Frame Sync
AFSR0
(Receive Frame Sync or
Left/Right Clock)
AFSX0
(Transmit Frame Sync or
Left/Right Clock)
AMUTE0
Error Detect
(see Note A )
Auto Mute
Logic
AMUTEIN0
McASP0
(Multichannel Audio Serial Port 0)
NOTES: A. The McASPs’ Error Detect function detects underruns, overruns, early/late frame syncs, DMA errors, and external mute input.
B. Bolded and italicized text within parentheses denotes the function of the pins in an audio system.
Figure 1−6. Peripheral Signals (Continued)
1.9.3
Terminal Functions
The terminal functions table (Table 1−6) identifies the external signal names, the associated pin (ball) numbers
along with the mechanical package designator, the pin type (I, O/Z, or I/O/Z), whether the pin has any internal
pullup/pulldown resistors and a functional pin description. For more detailed information on device
configuration, peripheral selection, multiplexed/shared pins, and debugging considerations, see the Device
Configurations section of this data sheet.
42
SPRS222E
June 2003 − Revised October 2005
Pin Assignments
Table 1−6. Terminal Functions
SIGNAL
IPD/
†
DESCRIPTION
TYPE
‡
NAME
DM641 DM640
IPU
CLOCK/PLL CONFIGURATION
Clock Input. This clock is the input to the on-chip PLL.
CLKIN
AC2
D6
AC2
D6
I
Clock output at 1/4 of the device speed (O/Z) [default] or this pin can be
programmed as a GP0 1 pin (I/O/Z).
§
CLKOUT4/GP0[1]
I/O/Z
IPU
IPU
Clock output at 1/6 of the device speed (O/Z) [default] or this pin can be
programmed as a GP0 2 pin (I/O/Z).
§
CLKOUT6/GP0[2]
C6
C6
I/O/Z
I
Clock mode select
•
CLKMODE1
CLKMODE0
AE4
AE4
IPD
IPD
Selects whether the CPU clock frequency = input clock frequency x1
(Bypass), x6, or x12.
For more details on the CLKMODE pins and the PLL multiply factors, see
the Clock PLL section of this data sheet.
AA2
V6
AA2
V6
I
¶
#
PLLV
A
PLL voltage supply
JTAG EMULATION
TMS
TDO
TDI
E15
B18
A18
A16
E15
B18
A18
A16
I
IPU
IPU
IPU
IPU
JTAG test-port mode select
JTAG test-port data out
JTAG test-port data in
JTAG test-port clock
O/Z
I
I
TCK
JTAG test-port reset. For IEEE 1149.1 JTAG compatibility, see the IEEE
1149.1 JTAG compatibility statement portion of this data sheet.
TRST
D14
D14
I
IPD
EMU11
EMU10
EMU9
EMU8
EMU7
EMU6
EMU5
EMU4
EMU3
EMU2
EMU1
D17
C17
B17
D16
A17
C16
B16
D15
C15
B15
C14
A15
D17
C17
B17
D16
A17
C16
B16
D15
C15
B15
C14
A15
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
Emulation pin 11. Reserved for future use, leave unconnected.
Emulation pin 10. Reserved for future use, leave unconnected.
Emulation pin 9. Reserved for future use, leave unconnected.
Emulation pin 8. Reserved for future use, leave unconnected.
Emulation pin 7. Reserved for future use, leave unconnected.
Emulation pin 6. Reserved for future use, leave unconnected.
Emulation pin 5. Reserved for future use, leave unconnected.
Emulation pin 4. Reserved for future use, leave unconnected.
Emulation pin 3. Reserved for future use, leave unconnected.
Emulation pin 2. Reserved for future use, leave unconnected.
||
Emulation pin 1
||
EMU0
Emulation pin 0
†
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground
IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite
supply rail, a 1-kΩ resistor should be used.)
These pins are multiplexed pins. For more details, see the Device Configurations section of this data sheet.
PLLV is not part of external voltage supply. See the Clock PLL section for information on how to connect this pin.
A = Analog signal (PLL Filter)
The EMU0 and EMU1 pins are internally pulled up with 30-kΩ resistors; therefore, for emulation and normal operation, no external
pullup/pulldown resistors are necessary. However, for boundary scan operation, pull down the EMU1 and EMU0 pins with a dedicated 1-kΩ
resistor.
‡
§
¶
#
||
43
June 2003 − Revised October 2005
SPRS222E
Pin Assignments
Table 1−6. Terminal Functions (Continued)
SIGNAL
DM641 DM640
IPD/
IPU
†
DESCRIPTION
TYPE
‡
NAME
RESET
RESETS, INTERRUPTS, AND GENERAL-PURPOSE INPUT/OUTPUTS
P4
B4
P4
B4
I
Device reset
Nonmaskable interrupt, edge-driven (rising edge)
Note: Any noise on the NMI pin may trigger an NMI interrupt; therefore, if the
NMI pin is not used, it is recommended that the NMI pin be grounded versus
relying on the IPD.
NMI
I
IPD
GP0[7]/EXT_INT7
GP0[6]/EXT_INT6
GP0[5]/EXT_INT5
E1
F2
F3
E1
F2
F3
I/O/Z
I/O/Z
I/O/Z
IPU
IPU
IPU
General-purpose input/output (GPIO) pins (I/O/Z) or external interrupts
(input only). The default after reset setting is GPIO enabled as input-only.
•
When these pins function as External Interrupts [by selecting the
corresponding interrupt enable register bit (IER.[7:4])], they are
edge-driven and the polarity can be independently selected via the
External Interrupt Polarity Register bits (EXTPOL.[3:0]).
GP0[4]/EXT_INT4
GP0[3]
F4
L5
F4
L5
I/O/Z
I/O/Z
IPU
IPD
The general-purpose 0 pin (GP0[3]) (I/O/Z).
GP0 0 pin (I/O/Z) [default]
This pin can be programmed as GPIO 0 (input only) [default] or as GP0[0]
(output only) pin or output as a general-purpose interrupt (GP0INT) signal
(output only).
GP0[0]
M5
M5
I/O/Z
IPD
Note: This pin must remain low during device reset.
CLKOUT6/
GP0[2]
Clock output at 1/6 of the device speed (O/Z) [default] or this pin can be
programmed as a GP0 2 pin (I/O/Z).
C6
D6
C6
D6
I/O/Z
I/O/Z
IPU
IPU
§
CLKOUT4/
Clock output at 1/4 of the device speed (O/Z) [default] or this pin can be
programmed as a GP0 1 pin (I/O/Z).
§
GP0[1]
HOST-PORT INTERFACE (HPI) [DM641 ONLY]
HINT
N4
P1
R3
—
—
—
I/O/Z
I/O/Z
I/O/Z
Host interrupt from DSP to host (O) [default]
HCNTL1
HCNTL0
Host control − selects between control, address, or data registers (I) [default]
Host control − selects between control, address, or data registers (I) [default]
Host half-word select − first or second half-word (not necessarily high or low
order) [For HPI16 bus width selection only] (I) [default]
HHWIL
N3
—
I/O/Z
HR/W
HAS
M1
P3
R1
R2
T2
N1
—
—
—
—
—
—
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
Host read or write select (I) [default]
Host address strobe (I) [default]
Host chip select (I) [default]
HCS
HDS1
HDS2
Host data strobe 1 (I) [default]
Host data strobe 2 (I) [default]
Host ready from DSP to host (O) [default]
HRDY
†
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground
IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite
supply rail, a 1-kΩ resistor should be used.)
‡
§
These pins are multiplexed pins. For more details, see the Device Configurations section of this data sheet.
44
SPRS222E
June 2003 − Revised October 2005
Pin Assignments
Table 1−6. Terminal Functions (Continued)
SIGNAL
DM641 DM640
IPD/
IPU
†
DESCRIPTION
TYPE
‡
NAME
HOST-PORT INTERFACE (HPI) [DM641 ONLY] (CONTINUED)
HD15
HD14
HD13
HD12
HD11
HD10
HD9
T3
U1
U3
U2
U4
V1
—
—
—
—
—
—
Host-port data (I/O/Z) [DM641 Only]
V3
—
As HPI data bus
HD8
V2
—
•
Used for transfer of data, address, and control
I/O/Z
HD7
W2
W4
Y1
—
—
—
—
—
—
—
—
For proper DM641 device operation, the HD5 pin at device reset must be
pulldown via a 10-kΩ resistor.
HD6
HD5
HD4
W3
Y2
HD3
HD2
Y4
HD1
AA1
Y3
HD0
EMIFA (32-BIT) − CONTROL SIGNALS COMMON TO ALL TYPES OF MEMORY
ACE3
ACE2
ACE1
ACE0
L26
K23
K24
K25
L26
K23
K24
K25
O/Z
O/Z
O/Z
O/Z
IPU
IPU
IPU
IPU
EMIFA memory space enables
•
•
Enabled by bits 28 through 31 of the word address
Only one pin is asserted during any external data access
ABE3
ABE2
ABE1
ABE0
M25
M26
L23
L24
M25
M26
L23
L24
O/Z
O/Z
O/Z
O/Z
IPU
IPU
IPU
IPU
EMIFA byte-enable control
•
Decoded from the low-order address bits. The number of address bits
or byte enables used depends on the width of external memory.
Byte-write enables for most types of memory
•
•
Can be directly connected to SDRAM read and write mask
signal (SDQM)
EMIFA peripheral data transfer, allows direct transfer between external
peripherals
APDT
M22
M22
O/Z
IPU
†
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground
IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite
supply rail, a 1-kΩ resistor should be used.)
‡
§
These pins are multiplexed pins. For more details, see the Device Configurations section of this data sheet.
45
June 2003 − Revised October 2005
SPRS222E
Pin Assignments
Table 1−6. Terminal Functions (Continued)
SIGNAL
DM641 DM640
IPD/
IPU
†
DESCRIPTION
TYPE
‡
NAME
EMIFA (32-BIT) − BUS ARBITRATION
AHOLDA
AHOLD
N22
W24
P22
N22
W24
P22
O
IPU
IPU
IPU
EMIFA hold-request-acknowledge to the host
I
EMIFA hold request from the host
EMIFA bus request output
ABUSREQ
O
EMIFA (32-BIT) − ASYNCHRONOUS/SYNCHRONOUS MEMORY CONTROL
EMIFA external input clock. The EMIFA input clock (AECLKIN, CPU/4 clock,
or CPU/6 clock) is selected at reset via the pullup/pulldown resistors on the
AEA[20:19] pins.
AECLKIN
H25
H25
I
IPD
AECLKIN is the default for the EMIFA input clock.
EMIFA output clock 2. Programmable to be EMIFA input clock (AECLKIN,
CPU/4 clock, or CPU/6 clock) frequency divided-by-1, -2, or -4.
AECLKOUT2
AECLKOUT1
J23
J26
J23
J26
O/Z
O/Z
IPD
IPD
EMIFA output clock 1 [at EMIFA input clock (AECLKIN, CPU/4 clock, or
CPU/6 clock) frequency].
EMIFA asynchronous memory read-enable/SDRAM column-address
strobe/programmable synchronous interface-address strobe or read-enable
•
For programmable synchronous interface, the RENEN field in the CE
Space Secondary Control Register (CExSEC) selects between ASADS
AARE/
ASDCAS/
ASADS/ASRE
J25
J25
O/Z
IPU
and ASRE:
If RENEN = 0, then the ASADS/ASRE signal functions as the ASADS
signal.
If RENEN = 1, then the ASADS/ASRE signal functions as the ASRE
signal.
AAOE/
ASDRAS/
ASOE
EMIFA asynchronous memory output-enable/SDRAM row-address
strobe/programmable synchronous interface output-enable
J24
K26
L25
J24
K26
L25
O/Z
O/Z
O/Z
IPU
IPU
IPU
AAWE/
ASDWE/
ASWE
EMIFA asynchronous memory write-enable/SDRAM
write-enable/programmable synchronous interface write-enable
EMIFA SDRAM clock-enable (used for self-refresh mode).
ASDCKE
•
If SDRAM is not in system, ASDCKE can be used as a general-purpose
output.
EMIFA synchronous memory output-enable for ACE3 (for glueless FIFO
interface)
ASOE3
R22
L22
R22
L22
O/Z
I
IPU
IPU
AARDY
Asynchronous memory ready input
†
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground
IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite
supply rail, a 1-kΩ resistor should be used.)
‡
§
These pins are multiplexed pins. For more details, see the Device Configurations section of this data sheet.
46
SPRS222E
June 2003 − Revised October 2005
Pin Assignments
Table 1−6. Terminal Functions (Continued)
SIGNAL
DM641 DM640
IPD/
IPU
†
DESCRIPTION
TYPE
‡
NAME
EMIFA (32-BIT) − ADDRESS
AEA22
AEA21
AEA20
AEA19
AEA18
AEA17
AEA16
AEA15
AEA14
AEA13
AEA12
AEA11
AEA10
AEA9
U23
V24
V25
V26
V23
U24
U25
U26
T24
T25
R23
R24
P23
P24
P26
N23
N24
N26
M23
M24
U23
V24
V25
V26
V23
U24
U25
U26
T24
T25
R23
R24
P23
P24
P26
N23
N24
N26
M23
M24
EMIFA external address (doubleword address)
EMIFA address numbering for the DM641/DM640 devices start with AEA3 to
maintain signal name compatibility with other C64x™ devices (e.g., C6414,
C6415, and C6416) [see the 32-bit EMIF addressing scheme in the
TMS320C6000 DSP External Memory Interface (EMIF) Reference Guide
(literature number SPRU266)].
Boot Configuration:
•
Controls initialization of DSP modes at reset (I) via pullup/pulldown
resistors
− Boot mode (AEA[22:21]):
00 – No boot (default mode)
01 − HPI [DM641 only]; Reserved [For DM640 device]
10 − Reserved
O/Z
IPD
11 − EMIFA 8−bit ROM boot
− EMIF clock select
− AEA[20:19]: Clock mode select for EMIFA (AECLKIN_SEL[1:0])
00 – AECLKIN (default mode)
01 − CPU/4 Clock Rate
AEA8
AEA7
AEA6
10 − CPU/6 Clock Rate
11 − Reserved
AEA5
AEA4
For more details, see the Device Configurations section of this data sheet.
EMIFA (32-BIT) − DATA
AEA3
AED31
AED30
AED29
AED28
AED27
AED26
AED25
AED24
AED23
AED22
AED21
AED20
AED19
AED18
AED17
AED16
AED15
C26
C25
D26
D25
E24
E25
F24
F25
F23
F26
G24
G25
G23
G26
H23
H24
C19
D19
C26
C25
D26
D25
E24
E25
F24
F25
F23
F26
G24
G25
G23
G26
H23
H24
C19
D19
I/O/Z
IPU
EMIFA external data
AED14
†
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground
IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite
supply rail, a 1-kΩ resistor should be used.)
‡
§
These pins are multiplexed pins. For more details, see the Device Configurations section of this data sheet.
47
June 2003 − Revised October 2005
SPRS222E
Pin Assignments
Table 1−6. Terminal Functions (Continued)
SIGNAL
DM641 DM640
IPD/
IPU
†
DESCRIPTION
TYPE
‡
NAME
EMIFA (32-BIT) − DATA (CONTINUED)
AED13
AED12
AED11
AED10
AED9
AED8
AED7
AED6
AED5
AED4
AED3
AED2
AED1
AED0
A20
D20
B20
C20
A21
D21
B21
C21
A23
C22
B22
B23
A24
B24
A20
D20
B20
C20
A21
D21
B21
C21
A23
C22
B22
B23
A24
B24
I/O/Z
IPU
EMIFA external data
MANAGEMENT DATA INPUT/OUTPUT (MDIO)
MDCLK
MDIO
R5
P5
R5
P5
I/O/Z
I/O/Z
IPD
IPU
MDIO serial clock input/output (I/O/Z).
MDIO serial data input/output (I/O/Z).
VCX0 INTERPOLATED CONTROL PORT (VIC)
VCXO Interpolated Control Port (VIC) single-bit digital-to-analog converter
(VDAC) output [output only].
VDAC
AD1
AC1
AD1
O/Z
IPD
VIDEO PORTS (VP0 [DM641/DM640] AND VP1 [DM641 ONLY])
STCLK
AC1
I
IPD
The STCLK signal drives the hardware counter on the video ports.
8-BIT VIDEO PORT 1 (VP1) [DM641 ONLY]
VP1D[7]
AC8
AD8
AC7
AD7
AE7
AC6
AD6
AE6
AF10
AF8
AD5
AE5
AF4
—
***
***
***
***
***
***
***
—
—
—
—
—
Video port 1 (VP1) data input/output (I/O/Z) or McBSP1 data input/output
(I/O/Z) [default] [DM641 only]
§
VP1D[6]/CLKR1
§
VP1D[5]/FSR1
*** − The DM640 device does not support the VP1 peripheral; therefore, the
McBSP1 peripheral pins are standalone peripheral functions, not muxed.
§
VP1D[4]/DR1
I/O/Z
IPD
§
VP1D[3]/CLKS1
§
VP1D[2]/DX1
For more details on the McBSP1 pin functions [for both the DM641 and
DM640 devices], see McBSP1 section of this table and the Device
Configurations section of this data sheet.
§
VP1D[1]/FSX1
§
VP1D[0]/CLKX1
VP1CLK1
VP1CLK0
VP1CTL2
VP1CTL1
I/O/Z
I
IPD
IPD
VP1 clock 1 (I/O/Z)
VP1 clock 0 (I)
VP1 control 2 (I/O/Z)
VP1 control 1 (I/O/Z)
VP1 control 0 (I/O/Z)
I/O/Z
IPD
VP1CTL0
†
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground
IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite
supply rail, a 1-kΩ resistor should be used.)
‡
§
These pins are multiplexed pins. For more details, see the Device Configurations section of this data sheet.
48
SPRS222E
June 2003 − Revised October 2005
Pin Assignments
Table 1−6. Terminal Functions (Continued)
SIGNAL
DM641 DM640
IPD/
IPU
†
DESCRIPTION
TYPE
‡
NAME
8-BIT VIDEO PORT 0 (VP0) [DM641 AND DM640]
VP0D[7]
AD15
AE15
AB16
AC16
AD16
AE16
AF16
AF17
AF12
AF14
AD17
AC17
AE17
AD15
AE15
AB16
AC16
AD16
AE16
AF16
AF17
AF12
AF14
AD17
AC17
AE17
§
VP0D[6]/CLKR0
§
VP0D[5]/FSR0
Video port 0 (VP0) data input/output (I/O/Z) or McBSP0 data input/output
(I/O/Z) [default]
§
VP0D[4]/DR0
I/O/Z
IPD
§
VP0D[3]/CLKS0
For more details on the McBSP0 pin functions, see McBSP0 section of this
table and the Device Configurations section of this data sheet.
§
VP0D[2]/DX0
§
VP0D[1]/FSX0
§
VP0D[0]/CLKX0
VP0CLK1
VP0CLK0
VP0CTL2
I/O/Z
I
IPD
IPD
VP0 clock 1 (I/O/Z)
VP0 clock 0 (I)
VP0 control 2 (I/O/Z)
VP0 control 1 (I/O/Z)
VP0control 0 (I/O/Z)
TIMER 2
VP0CTL1
I/O/Z
IPD
VP0CTL0
No external pins. The timer 2 peripheral pins are not pinned out as external
pins.
—
—
TIMER 1
Timer 1 output (O/Z)
Boot Configuration: Device endian mode [LENDIAN] (I).
Controls initialization of DSP modes at reset via pullup/pulldown resistors
− Device Endian mode
TOUT1/LENDIAN
TINP1
B5
A5
B5
A5
O/Z
IPU
IPD
0
1
–
−
Big Endian
Little Endian (default)
For more details on LENDIAN, see the Device Configurations section of this
data sheet.
I
Timer 1 or general-purpose input
TIMER 0
Timer 0 output (O/Z)
Boot Configuration: MAC enable pin [MAC_EN] (I)
The MAC_EN pin controls the selection (enable/disable) of the EMAC and
MDIO peripherals.
TOUT0/MAC_EN
C5
A4
C5
A4
O/Z
I
IPD
IPD
For more details, see the Device Configurations section of this data sheet.
Timer 0 or general-purpose input
TINP0
SCL0
INTER-INTEGRATED CIRCUIT 0 (I2C0)
E4
D3
E4
D3
I/O/Z
I/O/Z
—
—
I2C0 clock.
I2C0 data.
SDA0
†
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground
IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite
supply rail, a 1-kΩ resistor should be used.)
‡
§
These pins are multiplexed pins. For more details, see the Device Configurations section of this data sheet.
49
June 2003 − Revised October 2005
SPRS222E
Pin Assignments
Table 1−6. Terminal Functions (Continued)
SIGNAL
DM641 DM640
IPD/
IPU
†
DESCRIPTION
TYPE
‡
NAME
MULTICHANNEL BUFFERED SERIAL PORT 1 (McBSP1) [DM641 ONLY]
Video Port 1 (VP1) input/output data 6 pin (I/O/Z) or McBSP1 receive clock
(I/O/Z) [default]
§
VP1D[6]/CLKR1
AD8
—
I/O/Z
IPD
VP1 input/output data 5 pin (I/O/Z) or McBSP1 receive frame sync (I/O/Z)
[default]
§
VP1D[5]/FSR1
AC7
AD7
AE7
AC6
AD6
AE6
—
—
—
—
—
—
I/O/Z
I
IPD
IPD
IPD
IPD
IPD
IPD
§
VP1D[4]/DR1
VP1 input/output data 4 pin (I/O/Z) or McBSP1 receive data (I) [default]
VP1 input/output data 3 pin (I/O/Z) or McBSP1 external clock source (I)
(as opposed to internal) [default]
§
VP1D[3]/CLKS1
I
§
VP1D[2]/DX1
I/O/Z
I/O/Z
I/O/Z
VP1 input/output data 2 pin (I/O/Z) or McBSP1 transmit data (O/Z) [default]
VP1 input/output data 1 pin (I/O/Z) or McBSP1 transmit frame sync (I/O/Z)
[default]
§
VP1D[1]/FSX1
§
VP1D[0]/CLKX1
VP1 input/output data 0 pin (I/O/Z) or McBSP1 transmit clock (I/O/Z) [default]
MULTICHANNEL BUFFERED SERIAL PORT 1 (McBSP1) [DM640 ONLY]
CLKR1
FSR1
DR1
—
—
—
—
—
—
—
AD8
AC7
AD7
AE7
AC6
AD6
AE6
I/O/Z
I/O/Z
I
IPD
IPD
IPD
IPD
IPD
IPD
IPD
McBSP1 receive clock (I/O/Z)
McBSP1 receive frame sync (I/O/Z)
McBSP1 receive data (I)
CLKS1
DX1
I
McBSP1 external clock source (I) (as opposed to internal)
McBSP1 transmit data (O/Z)
I/O/Z
I/O/Z
I/O/Z
FSX1
CLKX1
McBSP1 transmit frame sync (I/O/Z)
McBSP1 transmit clock (I/O/Z)
MULTICHANNEL BUFFERED SERIAL PORT 0 (McBSP0)
Video Port 0 (VP0) input/output data 6 pin (I/O/Z) or McBSP0 receive clock
(I/O/Z) [default]
§
VP0D[6]/CLKR0
AE15
AE15
I/O/Z
IPD
VP0 input/output data 5 pin (I/O/Z) or McBSP0 receive frame sync (I/O/Z)
[default]
§
VP0D[5]/FSR0
AB16
AC16
AD16
AE16
AF16
AF17
AB16
AC16
AD16
AE16
AF16
AF17
I/O/Z
I
IPD
IPD
IPD
IPD
IPD
IPD
§
VP0D[4]/DR0
VP0 input/output data 4 pin (I/O/Z) or McBSP0 receive data (I) [default]
VP0 input/output data 3 pin (I/O/Z) or McBSP0 external clock source (I)
(as opposed to internal) [default]
§
VP0D[3]/CLKS0
I
§
VP0D[2]/DX0
O/Z
I/O/Z
I/O/Z
VP0 input/output data 2 pin (I/O/Z) or McBSP0 transmit data (O/Z) [default]
VP0 input/output data 1 pin (I/O/Z) or McBSP0 transmit frame sync (I/O/Z)
[default]
§
VP0D[1]/FSX0
§
VP0D[0]/CLKX0
VP0 input/output data 0 pin (I/O/Z) or McBSP0 transmit clock (I/O/Z) [default]
†
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground
IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite
supply rail, a 1-kΩ resistor should be used.)
‡
§
These pins are multiplexed pins. For more details, see the Device Configurations section of this data sheet.
50
SPRS222E
June 2003 − Revised October 2005
Pin Assignments
Table 1−6. Terminal Functions (Continued)
SIGNAL
DM641 DM640
IPD/
†
DESCRIPTION
TYPE
‡
IPU
ETHERNET MAC (EMAC)
EMAC Media Independent I/F (MII) data, clocks, and control pins for
NAME
MRCLK
MCRS
G1
H3
G2
J4
G1
H3
G2
J4
I
Transmit/Receive.
I
MII transmit clock (MTCLK),
Transmit clock source from the attached PHY.
MII transmit data (MTXD[3:0]),
Transmit data nibble synchronous with transmit clock (MTCLK).
MII transmit enable (MTXEN),
MRXER
MRXDV
MRXD3
MRXD2
MRXD1
MRXD0
MTCLK
MCOL
I
I
H2
J3
H2
J3
I
This signal indicates a valid transmit data on the transmit data pins
(MTDX[3:0]).
I
I
MII collision sense (MCOL)
Assertion of this signal during half-duplex operation indicates network
collision.
J1
J1
K4
L4
K4
L4
I
During full-duplex operation, transmission of new frames will not begin if
this pin is asserted.
MII carrier sense (MCRS)
Indicates a frame carrier signal is being received.
MII receive data (MRXD[3:0]),
Receive data nibble synchronous with receive clock (MRCLK).
MII receive clock (MRCLK),
Receive clock source from the attached PHY.
MII receive data valid (MRXDV),
This signal indicates a valid data nibble on the receive data pins
(MRDX[3:0]).
MII receive error (MRXER),
I
K2
L3
K2
L3
I
MTXEN
MTXD3
MTXD2
MTXD1
MTXD0
O/Z
O/Z
O/Z
O/Z
O/Z
L2
L2
M4
M2
M3
M4
M2
M3
Indicates reception of a coding error on the receive data.
MULTICHANNEL AUDIO SERIAL PORT 0 (McASP0) CONTROL
AHCLKX0
AFSX0
AC12
AD12
AB13
AC13
AD13
AB14
AC14
AD14
AC12
AD12
AB13
AC13
AD13
AB14
AC14
AD14
I/O/Z
I/O/Z
I/O/Z
O/Z
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
McASP0 transmit high-frequency master clock (I/O/Z).
McASP0 transmit frame sync or left/right clock (LRCLK) (I/O/Z).
McASP0 transmit bit clock (I/O/Z).
ACLKX0
AMUTE0
AMUTEIN0
AHCLKR0
AFSR0
McASP0 mute output (O/Z).
I/O/Z
I/O/Z
I/O/Z
I/O/Z
McASP0 mute input (I/O/Z).
McASP0 receive high-frequency master clock (I/O/Z).
McASP0 receive frame sync or left/right clock (LRCLK) (I/O/Z).
McASP0 receive bit clock (I/O/Z).
ACLKR0
MULTICHANNEL AUDIO SERIAL PORT 0 (McASP0) DATA
AE11
AXR0[3]
AXR0[2]
AXR0[1]
AE11
AC10
AD10
AC9
AC10
AD10
AC9
I/O/Z
IPD
McASP0 TX/RX data pins [3:0] (I/O/Z).
AXR0[0]
†
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground
IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite
supply rail, a 1-kΩ resistor should be used.)
‡
§
These pins are multiplexed pins. For more details, see the Device Configurations section of this data sheet.
51
June 2003 − Revised October 2005
SPRS222E
Pin Assignments
Table 1−6. Terminal Functions (Continued)
SIGNAL
DM641 DM640
IPD/
IPU
†
DESCRIPTION
TYPE
‡
NAME
RESERVED FOR TEST
Reserved. For proper DM641/DM640 device operation, this pin at device
reset must be pulled down via a 10-kΩ resistor.
RSV
RSV
RSV
RSV
E2
—
E2
Y1
H7
R6
I
I/O/Z
A
IPD
—
Reserved [for DM640 Only]. For proper DM640 device operation, this pin at
device reset must be pulled down via a 10-kΩ resistor.
Reserved. This pin must be connected directly to CV for proper device
DD
H7
R6
—
operation.
Reserved. This pin must be connected directly to DV for proper device
DD
A
—
operation.
ADDITIONAL RESERVED FOR TEST
A7
A9
A7
A9
I
IPD
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
—
A10
A11
A13
B8
A10
A11
A13
B8
Reserved (leave unconnected, do not connect to power or ground)
B9
B9
B10
B11
B12
C1
B10
B11
B12
C1
Pull down via a 10-kΩ resistor
C7
C7
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
IPD
—
C8
C8
C9
C9
C10
C11
C12
D7
C10
C11
C12
D7
RSV
D8
D8
Reserved (leave unconnected, do not connect to power or ground)
D9
D9
D10
D11
D12
E11
E12
E13
E14
F1
D10
D11
D12
E11
E12
E13
E14
F1
I/O/Z
I/O/Z
I/O/Z
I/O/Z
G3
G3
—
Pull down via a 10-kΩ resistor
G4
G4
—
H4
H4
—
†
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground
IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite
supply rail, a 1-kΩ resistor should be used.)
‡
52
SPRS222E
June 2003 − Revised October 2005
Pin Assignments
Table 1−6. Terminal Functions (Continued)
SIGNAL
DM641 DM640
IPD/
IPU
†
DESCRIPTION
TYPE
‡
NAME
J2
J2
I/O/Z
I/O/Z
I/O/Z
I
—
K1
K1
—
Pull down via a 10-kΩ resistor
K3
K3
—
R4
R4
IPU
IPU
IPU
IPD
IPU
IPU
—
R25
R25
O/Z
R26
R26
O/Z
Reserved (leave unconnected, do not connect to power or ground)
Pull down via a 10-kΩ resistor
T4
T4
O
T22
T22
O/Z
T23
T23
O/Z
V4
V4
I/O/Z
A
W7
W7
—
W23
Y23
W23
Y23
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
A
IPU
IPU
IPU
IPU
IPU
—
Y24
Y24
Y25
Y25
Y26
Y26
AA3
AA23
AA24
AA25
AA26
AB3
AB11
AB12
AB15
AB23
AB24
AB25
AC4
AC11
AC15
AC19
AC20
AC21
AC25
AC26
AD3
AD9
AD11
AD19
AA3
AA23
AA24
AA25
AA26
AB3
AB11
AB12
AB15
AB23
AB24
AB25
AC4
AC11
AC15
AC19
AC20
AC21
AC25
AC26
AD3
AD9
AD11
AD19
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I
IPU
IPU
IPU
IPU
—
RSV
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
O/Z
IPD
IPD
IPD
IPU
IPU
IPU
—
Reserved (leave unconnected, do not connect to power or ground)
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
O/Z
IPD
IPD
IPU
IPU
IPU
IPU
IPU
—
I/O/Z
I/O/Z
I/O/Z
IPD
IPD
IPU
†
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground
IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite
supply rail, a 1-kΩ resistor should be used.)
‡
53
June 2003 − Revised October 2005
SPRS222E
Pin Assignments
Table 1−6. Terminal Functions (Continued)
SIGNAL
DM641 DM640
IPD/
IPU
†
DESCRIPTION
TYPE
‡
NAME
AD20
AD21
AD22
AD23
AD25
AD26
AE9
AE18
AE20
AE21
AE22
AE23
AF3
AF5
AF6
AF18
AF20
AF21
AF23
AF24
—
AD20
AD21
AD22
AD23
AD25
AD26
AE9
AE18
AE20
AE21
AE22
AE23
AF3
AF5
AF6
AF18
AF20
AF21
AF23
AF24
M1
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
O
IPU
IPU
IPU
IPU
IPU
IPU
IPD
IPD
IPU
IPU
IPU
IPU
IPU
IPD
IPD
IPD
IPU
IPU
IPU
IPU
—
Reserved (leave unconnected, do not connect to power or ground)
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
RSV
Pull up via a 10-kΩ resistor
—
N1
—
Pull down via a 10-kΩ resistor
—
N3
—
—
N4
—
—
P1
—
—
P3
—
Pull up via a 10-kΩ resistor
—
R1
—
—
R2
—
—
R3
—
—
T2
—
—
T3
—
—
U1
—
—
U2
—
—
U3
—
—
U4
—
Pull down via a 10-kΩ resistor
—
V1
—
—
V2
—
—
V3
—
—
W2
—
—
W3
—
†
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground
IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite
supply rail, a 1-kΩ resistor should be used.)
‡
54
SPRS222E
June 2003 − Revised October 2005
Pin Assignments
Table 1−6. Terminal Functions (Continued)
SIGNAL
DM641 DM640
IPD/
IPU
†
DESCRIPTION
TYPE
‡
NAME
—
—
—
—
—
—
—
—
—
—
—
W4
Y2
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I
—
—
Y3
—
Pull down via a 10-kΩ resistor
Y4
—
AA1
AC8
AD5
AE5
AF4
AF8
AF10
—
IPD
IPD
IPD
IPD
IPD
IPD
RSV
Reserved (leave unconnected, do not connect to power or ground)
I/O/Z
SUPPLY VOLTAGE PINS
A2
A25
B1
A2
A25
B1
B2
B2
B14
B25
B14
B25
B26
C3
B26
C3
C24
D4
C24
D4
D23
E5
D23
E5
DV
S
3.3-V supply voltage
DD
E7
E7
E8
E8
E10
E17
E19
E20
E22
F9
E10
E17
E19
E20
E22
F9
F12
F15
F18
F12
F15
F18
†
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground
IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite
supply rail, a 1-kΩ resistor should be used.)
‡
55
June 2003 − Revised October 2005
SPRS222E
Pin Assignments
Table 1−6. Terminal Functions (Continued)
SIGNAL
DM641 DM640
IPD/
IPU
†
DESCRIPTION
TYPE
‡
NAME
SUPPLY VOLTAGE PINS (CONTINUED)
G5
G22
H5
G5
G22
H5
H22
J6
H22
J6
J21
J21
K5
K5
K22
M6
K22
M6
M21
N2
M21
N2
P25
R21
U5
P25
R21
U5
U22
V21
W5
U22
V21
W5
DV
S
3.3-V supply voltage
DD
W22
W25
Y5
W22
W25
Y5
Y22
AA9
AA12
AA15
AA18
AB5
AB7
AB8
AB10
AB17
AB19
AB20
Y22
AA9
AA12
AA15
AA18
AB5
AB7
AB8
AB10
AB17
AB19
AB20
†
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground
IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite
supply rail, a 1-kΩ resistor should be used.)
‡
56
SPRS222E
June 2003 − Revised October 2005
Pin Assignments
Table 1−6. Terminal Functions (Continued)
SIGNAL
DM641 DM640
IPD/
IPU
†
DESCRIPTION
TYPE
‡
NAME
SUPPLY VOLTAGE PINS (CONTINUED)
AB22
AC23
AD24
AE1
AB22
AC23
AD24
AE1
AE2
AE2
DV
S
3.3-V supply voltage
DD
AE13
AE25
AE26
AF2
AE13
AE25
AE26
AF2
AF25
AF25
F6
F7
F6
F7
F20
F21
G6
F20
F21
G6
G7
G7
G8
G8
G10
G11
G13
G14
G16
G17
G19
G20
G21
H20
K7
G10
G11
G13
G14
G16
G17
G19
G20
G21
H20
K7
1.2-V supply voltage (-400, -500 devices)
1.4-V supply voltage (-600 device)
CV
S
DD
K20
L7
K20
L7
L20
M12
M14
N7
L20
M12
M14
N7
†
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground
IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite
supply rail, a 1-kΩ resistor should be used.)
‡
57
June 2003 − Revised October 2005
SPRS222E
Pin Assignments
Table 1−6. Terminal Functions (Continued)
SIGNAL
DM641 DM640
IPD/
IPU
†
DESCRIPTION
TYPE
‡
NAME
SUPPLY VOLTAGE PINS (CONTINUED)
N13
N15
N20
P7
N13
N15
N20
P7
P12
P14
P20
R13
R15
T7
P12
P14
P20
R13
R15
T7
T20
U7
T20
U7
U20
W20
Y6
U20
W20
Y6
1.2-V supply voltage (-400, -500 devices)
1.4-V supply voltage (-600 device)
CV
S
DD
Y7
Y7
Y8
Y8
Y10
Y11
Y13
Y14
Y16
Y17
Y19
Y20
Y21
AA6
AA7
AA20
AA21
Y10
Y11
Y13
Y14
Y16
Y17
Y19
Y20
Y21
AA6
AA7
AA20
AA21
†
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground
IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite
supply rail, a 1-kΩ resistor should be used.)
‡
58
SPRS222E
June 2003 − Revised October 2005
Pin Assignments
Table 1−6. Terminal Functions (Continued)
SIGNAL
DM641 DM640
IPD/
IPU
†
DESCRIPTION
TYPE
‡
NAME
GROUND PINS
A1
A3
A1
A3
A6
A6
A8
A8
A12
A14
A19
A22
A26
B3
A12
A14
A19
A22
A26
B3
B6
B6
B7
B7
B13
B19
C2
B13
B19
C2
C4
C4
C13
C18
C23
D1
C13
C18
C23
D1
V
SS
GND
Ground pins
D2
D2
D5
D5
D13
D18
D22
D24
E3
D13
D18
D22
D24
E3
E6
E6
E9
E9
E16
E18
E21
E23
E26
E16
E18
E21
E23
E26
†
‡
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground
IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite
supply rail, a 1-kΩ resistor should be used.)
59
June 2003 − Revised October 2005
SPRS222E
Pin Assignments
Table 1−6. Terminal Functions (Continued)
SIGNAL
DM641 DM640
IPD/
IPU
†
DESCRIPTION
TYPE
‡
NAME
GROUND PINS (CONTINUED)
F5
F8
F5
F8
F10
F11
F13
F14
F16
F17
F19
F22
G9
F10
F11
F13
F14
F16
F17
F19
F22
G9
G12
G15
G18
H1
G12
G15
G18
H1
H6
H6
H21
H26
J5
H21
H26
J5
V
SS
GND
Ground pins
J7
J7
J20
J22
K6
J20
J22
K6
K21
L1
K21
L1
L6
L6
L21
M7
L21
M7
M13
M15
M20
N5
M13
M15
M20
N5
N6
N6
N12
N12
†
‡
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground
IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite
supply rail, a 1-kΩ resistor should be used.)
60
SPRS222E
June 2003 − Revised October 2005
Pin Assignments
Table 1−6. Terminal Functions (Continued)
SIGNAL
DM641 DM640
IPD/
IPU
†
DESCRIPTION
TYPE
‡
NAME
GROUND PINS (CONTINUED)
N14
N21
N25
P2
N14
N21
N25
P2
P6
P6
P13
P15
P21
R7
P13
P15
P21
R7
R12
R14
R20
T1
R12
R14
R20
T1
T5
T5
T6
T6
T21
T26
U6
T21
T26
U6
V
SS
GND
Ground pins
U21
V5
U21
V5
V7
V7
V20
V22
W1
W6
W21
W26
Y9
V20
V22
W1
W6
W21
W26
Y9
Y12
Y15
Y18
AA4
AA5
AA8
Y12
Y15
Y18
AA4
AA5
AA8
†
‡
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground
IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite
supply rail, a 1-kΩ resistor should be used.)
61
June 2003 − Revised October 2005
SPRS222E
Pin Assignments
Table 1−6. Terminal Functions (Continued)
SIGNAL
DM641 DM640
IPD/
IPU
†
DESCRIPTION
TYPE
‡
NAME
GROUND PINS (CONTINUED)
AA10
AA11
AA13
AA14
AA16
AA10
AA11
AA13
AA14
AA16
AA17
AA19
AA22
AB1
AA17
AA19
AA22
AB1
AB2
AB2
AB4
AB4
AB6
AB6
AB9
AB9
AB18
AB21
AB26
AC3
AB18
AB21
AB26
AC3
V
SS
GND
Ground pins
AC5
AC5
AC18
AC22
AC24
AD2
AC18
AC22
AC24
AD2
AD4
AD4
AD18
AE3
AD18
AE3
AE8
AE8
AE10
AE12
AE14
AE19
AE24
AF1
AE10
AE12
AE14
AE19
AE24
AF1
AF7
AF7
†
‡
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground
IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite
supply rail, a 1-kΩ resistor should be used.)
62
SPRS222E
June 2003 − Revised October 2005
Pin Assignments
Table 1−6. Terminal Functions (Continued)
SIGNAL
DM641 DM640
IPD/
IPU
†
DESCRIPTION
TYPE
‡
NAME
GROUND PINS (CONTINUED)
AF9
AF9
AF11
AF13
AF15
AF19
AF22
AF26
AF11
AF13
AF15
AF19
AF22
AF26
V
SS
GND
Ground pins
†
‡
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground
IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-kΩ IPD or IPU resistor. To pull up a signal to the opposite
supply rail, a 1-kΩ resistor should be used.)
63
June 2003 − Revised October 2005
SPRS222E
Development
1.10 Development
1.10.1 Development Support
TI offers an extensive line of development tools for the TMS320C6000™ DSP platform, including tools to
evaluate the performance of the processors, generate code, develop algorithm implementations, and fully
integrate and debug software and hardware modules.
The following products support development of C6000™ DSP-based applications:
Software Development Tools:
Code Composer Studio™ Integrated Development Environment (IDE): including Editor
C/C++/Assembly Code Generation, and Debug plus additional development tools
Scalable, Real-Time Foundation Software (DSP/BIOS™), which provides the basic run-time target software
needed to support any DSP application.
Hardware Development Tools:
Extended Development System (XDS™) Emulator (supports C6000™ DSP multiprocessor system debug)
EVM (Evaluation Module)
For a complete listing of development-support tools for the TMS320C6000™ DSP platform, visit the Texas
Instruments web site on the Worldwide Web at http://www.ti.com uniform resource locator (URL). For
information on pricing and availability, contact the nearest TI field sales office or authorized distributor.
Code Composer Studio, DSP/BIOS, and XDS are trademarks of Texas Instruments.
64
SPRS222E
June 2003 − Revised October 2005
Development
1.10.2 Device Support
1.10.2.1 Device and Development-Support Tool Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all DSP
devices and support tools. Each DSP commercial family member has one of three prefixes: TMX, TMP, or TMS
(e.g., TMS320DM641GDK600). Texas Instruments recommends two of three possible prefix designators for
its support tools: TMDX and TMDS. These prefixes represent evolutionary stages of product development
from engineering prototypes (TMX/TMDX) through fully qualified production devices/tools (TMS/TMDS).
Device development evolutionary flow:
TMX Experimental device that is not necessarily representative of the final device’s electrical specifications
TMP Final silicon die that conforms to the device’s electrical specifications but has not completed quality
and reliability verification
TMS Fully qualified production device
Support tool development evolutionary flow:
TMDX Development-support product that has not yet completed Texas Instruments internal qualification
testing.
TMDS Fully qualified development-support product
TMX and TMP devices and TMDX development-support tools are shipped against the following disclaimer:
“Developmental product is intended for internal evaluation purposes.”
TMS devices and TMDS development-support tools have been characterized fully, and the quality and
reliability of the device have been demonstrated fully. TI’s standard warranty applies.
Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard
production devices. Texas Instruments recommends that these devices not be used in any production system
because their expected end-use failure rate still is undefined. Only qualified production devices are to be used.
TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package
type (for example, GDK), the temperature range (for example, blank is the default commercial temperature
range), and the device speed range in megahertz (for example, -600 is 600 MHz). Figure 1−7 provides a
legend for reading the complete device name for any DSP platform member.
The ZDK package, like the GDK package, is a 548-ball plastic BGA only with Pb-free balls. The ZNZ package
is the Pb−free version of the GNZ package.
For device part numbers and further ordering information for TMS320DM641/DM640 in the GDK, GNZ, ZDK
and ZNZ package types, see the TI website (http://www.ti.com) or contact your TI sales representative.
65
June 2003 − Revised October 2005
SPRS222E
Development
(
)
TMS 320 DM641 GDK
600
PREFIX
DEVICE SPEED RANGE
TMX= Experimental device
400 (400-MHz CPU, 100-MHz EMIF)
500 (500-MHz CPU, 100-MHz EMIF)
600 (600-MHz CPU, 133-MHz EMIF)
TMP= Prototype device
TMS= Qualified device
SMX= Experimental device, MIL
SMJ = MIL-PRF-38535, QML
SM = High Rel (non-38535)
†
TEMPERATURE RANGE (DEFAULT: 0°C TO 90°C)
Blank = 0°C to 90°C, commercial temperature
A
=
−40°C to 105°C, extended temperature
DEVICE FAMILY
320 = TMS320t DSP family
‡§
PACKAGE TYPE
GDK = 548-pin plastic BGA
GNZ = 548-pin plastic BGA
ZDK = 548-pin plastic BGA, with Pb-free soldered balls
ZNZ = 548-pin plastic BGA, with Pb-free soldered balls
¶
DEVICE
DM64x DSP:
643
642
641
640
†
The extended temperature “A version” devices may have different operating conditions than the commercial temperature devices.
For more details, see the recommended operating conditions portion of this data sheet.
‡
§
BGA
=
Ball Grid Array
The ZDK and ZNZ mechanical package designators represent the version of the GDK and GNZ packages with Pb-free balls. For
more detailed information, see the Mechanical Data section of this document.
For actual device part numbers (P/Ns) and ordering information, see the TI website (www.ti.com).
¶
Figure 1−7. TMS320DM64x™ DSP Device Nomenclature (Including the DM641 and DM640 Devices)
1.10.2.2 Documentation Support
Extensive documentation supports all TMS320™ DSP family generations of devices from product
announcement through applications development. The types of documentation available include: data
sheets, such as this document, with design specifications; complete user’s reference guides for all devices
and tools; technical briefs; development-support tools; on-line help; and hardware and software applications.
The following is a brief, descriptive list of support documentation specific to the C6000™ DSP devices:
The TMS320C6000 CPU and Instruction Set Reference Guide (literature number SPRU189) describes the
C6000™ DSP CPU (core) architecture, instruction set, pipeline, and associated interrupts.
The TMS320C6000 DSP Peripherals Overview Reference Guide (literature number SPRU190) provides an
overview and briefly describes the functionality of the peripherals available on the C6000™ DSP platform of
devices. This document also includes a table listing the peripherals available on the C6000 devices along with
literature numbers and hyperlinks to the associated peripheral documents.
The TMS320C64x Technical Overview (literature number SPRU395) gives an introduction to the C64x™
digital signal processor, and discusses the application areas that are enhanced by the C64x™ DSP
VelociTI.2™ VLIW architecture.
The TMS320C64x DSP Video Port/VCXO Interpolated Control (VIC) Port Reference Guide (literature number
SPRU629) describes the functionality of the Video Port and VIC Port peripherals.
The TMS320C6000 DSP Multichannel Audio Serial Port (McASP) Reference Guide (literature number
SPRU041) describes the functionality of the McASP peripheral.
TMS320C6000 DSP Inter-Integrated Circuit (I2C) Module Reference Guide (literature number SPRU175)
2
describes the functionality of the I C peripheral.
TMS320C6000 DSP Ethernet Media Access Controller (EMAC)/ Management Data Input/Output (MDIO)
Module Reference Guide (literature number SPRU628) describes the functionality of the EMAC and MDIO
peripherals.
66
SPRS222E
June 2003 − Revised October 2005
Development
The TMS320DM641/TMS320DM640 Digital Signal Processors Silicon Errata (literature number SPRZ201)
describes the known exceptions to the functional specifications for particular silicon revisions of the
TMS320DM641 and TMS320DM640 devices.
The TMS320DM64x Power Consumption Summary application report (literature number SPRA962)
discusses the power consumption for user applications with the TMS320DM641/DM640 DSP devices.
The TMS320DM640/1 Hardware Designer’s Resource Guide (literature number SPRAA50) is organized by
development flow and functional areas to make design efforts as seamless as possible. This document
includes getting started, board design, system testing, and checklists to aid in initial designs and debug efforts.
Each section of this document includes pointers to valuable information including: technical documentation,
models, symbols, and reference designs for use in each phase of design. Particular attention is given to
peripheral interfacing and system-level design concerns.
The Using IBIS Models for Timing Analysis application report (literature number SPRA839) describes how to
properly use IBIS models to attain accurate timing analysis for a given system.
The tools support documentation is electronically available within the Code Composer Studio™ Integrated
Development Environment (IDE). For a complete listing of C6000™ DSP latest documentation, visit the Texas
Instruments web site on the Worldwide Web at http://www.ti.com uniform resource locator (URL).
1.10.2.3 Device Silicon Revision
The device silicon revision can be determined by the “Die PG code” marked on the top of the package. For
more detailed information on the DM641/DM640 silicon revision, package markings, and the known
exceptions to the functional specifications as well as any usage notes, refer to the device-specific silicon
errata: TMS320DM641, TMS320DM640 Digital Signal Processors Silicon Errata (literature number
SPRZ201).
67
June 2003 − Revised October 2005
SPRS222E
Device Configurations
2
Device Configurations
On the DM641/DM640 device, bootmode and certain device configurations/peripheral selections are
determined at device reset, while other device configurations/peripheral selections are software-configurable
via the peripheral configurations register (PERCFG) [address location 0x01B3F000] after device reset.
2.1
Configurations at Reset
For proper device operation; the following external pins must be configured correctly:
•
•
•
For proper DM641 device operation, the HD5 [pin Y1] at device reset must be pulled down via a 10-kΩ
resistor.
For proper DM641/DM640 device operation, the reserved (RSV) [E2] pin at device reset must be pulled
down via a 10-kΩ resistor.
For proper DM641/DM640 device operation, the GP0[0] [pin M5] (IPD) must remain low at device reset.
2.1.1
Peripheral Selection at Device Reset
On the DM641/DM640 devices there are NO peripherals sharing the same pins (internally muxed, yet mutually
exclusive) that are controlled via external pins.
•
EMAC and MDIO peripherals
The MAC_EN pin is latched at reset. This pin determines specific peripheral selection, summarized in
Table 2−1.
Table 2−1. MAC_EN Peripheral Selection (EMAC and MDIO)
PERIPHERAL SELECTION
PERIPHERALS SELECTED
MAC_EN
Pin [C5]
HPI Data
(16-Bit) [DM641 Only]
EMAC and MDIO
0
1
√
√
Disabled
√
68
SPRS222E
June 2003 − Revised October 2005
Device Configurations
2.1.2
Device Configuration at Device Reset
Table 2−2 describes the DM641/DM640 device configuration pins, which are set up via external
pullup/pulldown resistors through the specified EMIFA address bus pins (AEA[22:19]) and the
TOUT1/LENDIAN pin (all of which are latched during device reset).
Table 2−2. DM641/DM640 Device Configuration Pins
(TOUT1/LENDIAN, AEA[22:19], and TOUT0/MAC_EN)
CONFIGURATION
NO.
FUNCTIONAL DESCRIPTION
PIN
Device Endian mode (LEND)
TOUT1/LENDIAN
B5
0
1
–
−
System operates in Big Endian mode
System operates in Little Endian mode (default)
Bootmode [1:0]
− Boot mode (AEA[22:21]):
00 – No boot (default mode)
01 − HPI [DM641 only]; Reserved [For DM640 device]
10 − Reserved
[U23,
V24]
AEA[22:21]
11 − EMIFA 8−bit ROM boot
EMIFA input clock select
Clock mode select for EMIFA (AECLKIN_SEL[1:0])
00 – AECLKIN (default mode)
01 − CPU/4 Clock Rate
[V25,
V26]
AEA[20:19]
10 − CPU/6 Clock Rate
11 − Reserved
Peripheral Selection
TOUT0/MAC_EN
C5
1
0
−
−
EMAC and MDIO enabled
EMAC and MDIO disabled
2.2
Configurations After Reset
2.2.1
Peripheral Selection After Device Reset
Video Ports, McBSP1, McBSP0, McASP0, and I2C0
The DM641/DM640 device has designated registers for peripheral configuration (PERCFG), device status
(DEVSTAT), and JTAG identification (JTAGID). These registers are part of the Device Configuration module
and are mapped to a 4K block memory starting at 0x01B3F000. The CPU accesses these registers via the
CFGBUS.
The peripheral configuration register (PERCFG), allows the user to control the peripheral selection of the
Video Ports (VP0 and VP1 [DM641 only]) McBSP0, McBSP1, McASP0, and I2C0 peripherals. For more
detailed information on the PERCFG register control bits, see Figure 2−1 and Table 2−3.
69
June 2003 − Revised October 2005
SPRS222E
Device Configurations
31
24
16
8
Reserved
R-0
23
15
Reserved
R-0
Reserved
R-0
7
6
5
4
3
2
1
0
†
Reserved
R-0
Reserved
R/W-0
VP1EN
R/W-0
VP0EN
R/W-0
I2C0EN
R/W-0
MCBSP1EN
R/W-1
MCBSP0EN
R/W-1
MCASP0EN
R/W-0
Legend: R = Read only; R/W = Read/Write; -n = value after reset
†
The DM640 device does not support the VP1 peripheral; therefore, this bit is Reserved.
Figure 2−1. Peripheral Configuration Register (PERCFG) [Address Location: 0x01B3F000 − 0x01B3F003]
Table 2−3. Peripheral Configuration (PERCFG) Register Selection Bit Descriptions
BIT
NAME
DESCRIPTION
31:6
Reserved
Reserved. Read-only, writes have no effect.
VP1 Enable bit [DM641 only].
Determines whether the VP1 peripheral is enabled or disabled.
VP1 is disabled, and the module is powered down (default).
(This feature allows power savings by disabling the peripheral when not in use.)
VP1 is enabled.
0
=
5
VP1EN
1
=
The DM640 device does not support the VP1 peripheral; therefore, this bit is Reserved.
VP0 Enable bit.
Determines whether the VP0 peripheral is enabled or disabled.
0
=
VP0 is disabled, and the module is powered down (default).
(This feature allows power savings by disabling the peripheral when not in use.)
VP0 is enabled.
4
3
VP0EN
I2C0EN
1
=
Inter-integrated circuit 0 (I2C0) enable bit.
Selects whether I2C0 peripheral is enabled or disabled (default).
0
1
=
=
I2C0 is disabled, and the module is powered down (default).
I2C0 is enabled.
Video Port 1 (VP1) lower data pins vs. McBSP1 enable bit.
Selects whether VP1 peripheral lower-data pins or the McBSP1 peripheral is enabled.
0
=
VP1 lower-data pins are enabled and function (if VP1EN=1), McBSP1 is disabled; the
remaining VP1 upper-data pins are dependent on the MCASP0EN bit and the VP1EN bit
settings.
2
MCBSP1EN
1
=
McBSP1 is enabled, VP1 lower-data pin functions are disabled (default).
For a graphic (logic) representation of this Peripheral Configuration (PERCFG) Register selection bit and
the signal pins controlled/selected, see Figure 2−2.
70
SPRS222E
June 2003 − Revised October 2005
Device Configurations
Table 2−3. Peripheral Configuration (PERCFG) Register Selection Bit Descriptions (Continued)
BIT
NAME
DESCRIPTION
Video Port 0 (VP0) lower data pins vs. McBSP0 enable bit.
Selects whether VP0 peripheral lower-data pins or the McBSP1 peripheral is enabled.
0
=
VP0 lower-data pins are enabled and function (if VP0EN=1), McBSP0 is disabled; the
remaining VP0 upper-data pins are dependent on the MCASP0EN bit and the VP1EN bit
settings.
1
MCBSP0EN
1
=
McBSP0 is enabled, VP0 lower-data pin functions are disabled (default).
For a graphic (logic) representation of this Peripheral Configuration (PERCFG) Register selection bit and
the signal pins controlled/selected, see Figure 2−2.
McASP0 select bit.
Selects whether the McASP0 peripheral or the VP0 and VP1 upper-data pins are enabled.
0
1
=
=
Reserved [default].
McASP0 is enabled.
0
MCASP0EN
For proper DM641/DM640 device operation, the pin must be set to a “1”.
McBSP0EN [PERCFG.1]
1
0
McBSP0
VP0 Data (8 pins)
VP0 (Channel A)
†
VP0D[6:0] Muxed
VP0D[7] Standalone
McBSP1EN [PERCFG.2]
1
0
McBSP1
VP1 Data (8 pins)
VP1 (Channel A) [DM641 Only]
‡
VP1D[6:0] Muxed
VP1D[7] Standalone
†
Consists of: VP0D[6]/CLKR0, VP0D[5]/FSR0, VP0D[4]/DR0, VP0D[3]/CLKS0, VP0D[2]/DX0, VP0D[1]/FSX0, VP0D[0]/CLKX0.
Consists of: VP1D[6]/CLKR1, VP1D[5]/FSR1, VP1D[4]/DR1, VP1D[3]/CLKS1, VP1D[2]/DX1, VP1D[1]/FSX1, VP1D[0]/CLKX1.
‡
Figure 2−2. VP1, VP0, McBSP1, and McBSP0 Pin Muxing
71
June 2003 − Revised October 2005
SPRS222E
Device Configurations
2.3
Peripheral Configuration Lock
By default, the McASP0, VP0, VP1 [DM641 only], and I2C peripherals are disabled on power up. In order to
use these peripherals on the DM641/DM640 device, the peripheral must first be enabled in the Peripheral
Configuration register (PERCFG). Software muxed pins should not be programmed to switch
functionalities during run-time. Care should also be taken to ensure that no accesses are being
performed before disabling the peripherals. To help minimize power consumption in the DM641/DM640
device, unused peripherals may be disabled.
Figure 2−3 shows the flow needed to enable (or disable) a given peripheral on the DM641/DM640 devices.
Unlock the PERCFG Register
Using the PCFGLOCK Register
Write to
PERCFG Register
to Enable/Disable Peripherals
Read from
PERCFG Register
Wait 128 CPU Cycles Before
Accessing Enabled Peripherals
Figure 2−3. Peripheral Enable/Disable Flow Diagram
A 32-bit key (value = 0x10C0010C) must be written to the Peripheral Configuration Lock register
(PCFGLOCK) in order to unlock access to the PERCFG register. Reading the PCFGLOCK register
determines whether the PERCFG register is currently locked (LOCKSTAT bit = 1) or unlocked (LOCKSTAT
bit = 0), see Figure 2−4. A peripheral can only be enabled when the PERCFG register is “unlocked”
(LOCKSTAT bit = 0).
72
SPRS222E
June 2003 − Revised October 2005
Device Configurations
Read Accesses
31
1
0
Reserved
R-0
LOCKSTAT
R-1
Write Accesses
31
0
LOCK
W-0
Legend: R = Read only; R/W = Read/Write; -n = value after reset
Figure 2−4. PCFGLOCK Register Diagram [Address Location: 0x01B3 F018] − Read/Write Accesses
Table 2−4. PCFGLOCK Register Selection Bit Descriptions − Read Accesses
BIT
NAME
DESCRIPTION
31:1
Reserved
Reserved. Read-only, writes have no effect.
Lock status bit.
Determines whether the PERCFG register is locked or unlocked.
0
1
=
=
Unlocked, read accesses to the PERCFG register allowed.
Locked, write accesses to the PERCFG register do not modify the register state [default].
0
LOCKSTAT
Reads are unaffected by Lock Status.
Table 2−5. PCFGLOCK Register Selection Bit Descriptions − Write Accesses
BIT
NAME
DESCRIPTION
Lock bits.
0x10C0010C = Unlocks PERCFG register accesses.
31:0
LOCK
Any write to the PERCFG register will automatically relock the register. In order to avoid the unnecessary
overhead of multiple unlock/enable sequences, all peripherals should be enabled with a single write to the
PERCFG register with the necessary enable bits set.
Prior to waiting 128 CPU cycles, the PERCFG register should be read. There is no direct correlation between
the CPU issuing a write to the PERCFG register and the write actually occurring. Reading the PERCFG
register after the write is issued forces the CPU to wait for the write to the PERCFG register to occur.
Once a peripheral is enabled, the DSP (or other peripherals such as the HPI) must wait a minimum of 128 CPU
cycles before accessing the enabled peripheral. The user must ensure that no accesses are performed to a
peripheral while it is disabled.
73
June 2003 − Revised October 2005
SPRS222E
Device Configurations
2.4
Device Status Register Description
The device status register depicts the status of the device peripheral selection. For the actual register bit
names and their associated bit field descriptions, see Figure 2−5 and Table 2−6.
31
23
24
Reserved
R-0
16
Reserved
R-0
15
7
14
6
13
12
11
MAC_EN
R-x
10
Reserved
R-0
9
8
Reserved
R-0
Reserved
R-x
Reserved
R-0
5
4
3
2
1
0
Reserved
R-x
CLKMODE1
R-x
CLKMODE0
R-x
LENDIAN
R-x
BOOTMODE1 BOOTMODE0 AECLKINSEL1 AECLKINSEL0
R-x R-x R-x R-x
Legend: R = Read only; R/W = Read/Write; -n = value after reset
Figure 2−5. Device Status Register (DEVSTAT) Description − 0x01B3 F004
Table 2−6. Device Status (DEVSTAT) Register Selection Bit Descriptions
BIT
NAME
DESCRIPTION
31:12
Reserved
MAC_EN
Reserved
Reserved. Read-only, writes have no effect.
EMAC enable bit.
Shows the status of whether EMAC peripheral is enabled or disabled (default).
11
0
1
=
=
EMAC is disabled, and the module is powered down (default).
EMAC is enabled.
10:7
Reserved. Read-only, writes have no effect.
Clock mode select bits
Shows the status of whether the CPU clock frequency equals the input clock frequency X1 (Bypass), x6,
or x12.
6
CLKMODE1
Clock mode select for CPU clock frequency (CLKMODE[1:0])
00 – Bypass (x1) (default mode)
01 − x6
10 − x12
11 − Reserved
5
4
CLKMODE0
LENDIAN
For more details on the CLKMODE pins and the PLL multiply factors, see the Clock PLL section of this
data sheet.
Device Endian mode (LEND)
Shows the status of whether the system is operating in Big Endian mode or Little Endian mode (default).
0
1
–
−
System is operating in Big Endian mode
System is operating in Little Endian mode (default)
Bootmode configuration bits
Shows the status of what device bootmode configuration is operational.
Bootmode [1:0]
3
2
BOOTMODE1
BOOTMODE0
00 – No boot (default mode)
01 − HPI [DM641 only]; Reserved [For DM640 device]
10 − Reserved
11 − EMIFA 8−bit ROM boot
74
SPRS222E
June 2003 − Revised October 2005
Device Configurations
Table 2−6. Device Status (DEVSTAT) Register Selection Bit Descriptions (Continued)
BIT
NAME
DESCRIPTION
EMIFA input clock select
Shows the status of what clock mode is enabled or disabled for the EMIF.
Clock mode select for EMIFA (AECLKIN_SEL[1:0])
00 – AECLKIN (default mode)
1
AECLKINSEL1
01 − CPU/4 Clock Rate
10 − CPU/6 Clock Rate
0
AECLKINSEL0
11 − Reserved
75
June 2003 − Revised October 2005
SPRS222E
Device Configurations
2.5
Multiplexed Pin Configurations
Multiplexed pins are pins that are shared by more than one peripheral and are internally multiplexed. Some
of these pins are configured by software, and the others are configured by external pullup/pulldown resistors
only at reset. Those muxed pins that are configured by software should not be programmed to switch
functionalities during run-time. Those muxed pins that are configured by external pullup/pulldown resistors
are mutually exclusive; only one peripheral has primary control of the function of these pins after reset.
Table 2−7 identifies the multiplexed pins on the DM641/DM640 device; shows the default (primary) function
and the default settings after reset; and describes the pins, registers, etc. necessary to configure specific
multiplexed functions.
Table 2−7. DM641/DM640 Device Multiplexed Pin Configurations
MULTIPLEXED PINS
NAME
DEFAULT
FUNCTION
DEFAULT
SETTING
DESCRIPTION
NO.
These pins are software-configurable. To use these pins as
GPIO pins, the GPxEN bits in the GPIO Enable Register and
the GPxDIR bits in the GPIO Direction Register must be
properly configured.
CLKOUT4/GP0[1]
D6
CLKOUT4
CLKOUT6
GP1EN = 0 (disabled)
GP2EN = 0 (disabled)
GPxEN = 1:
GPxDIR = 0:
GPxDIR = 1:
GPx pin enabled
GPx pin is an input
GPx pin is an output
CLKOUT6/GP0[2]
C6
VP1D[6]/CLKR1
VP1D[5]/FSR1
VP1D[4]/DR1
AD8
AC7
Muxed on the DM641 device only
[The DM640 device does not support the VP1 peripheral;
therefore, the McBSP1 peripheral pins are standalone
peripheral functions, not muxed.]
VP1EN bit = 0
(disabled)
MCBSP1EN bit = 1
(enabled)
AD7
McBSP1
functions
VP1D[3]/CLKS1
VP1D[2]/DX1
AE7
By default, the McBSP1 peripheral, function is enabled upon
reset (MCBSP1EN bit = 1).
To enable the Video Port 1 data pins, the VP1EN bit in the
PERCFG register must be set to a 1.
AC6
VP1D[1]/FSX1
VP1D[0]/CLKX1
VP0D[6]/CLKR0
VP0D[5]/FSR0
VP0D[4]/DR0
AD6
AE6
AE15
AB16
AC16
AD16
AE16
AF16
AF17
VP0EN bit = 0
(disabled)
MCBSP0EN bit = 1
(enabled)
By default, the McBSP0 peripheral function is enabled upon
reset (MCBSP0EN bit = 1).
To enable the Video Port 0 data pins, the VP0EN bit in the
PERCFG register must be set to a 1.
McBSP0
functions
VP0D[3]/CLKS0
VP0D[2]/DX0
VP0D[1]/FSX0
VP0D[0]/CLKX0
76
SPRS222E
June 2003 − Revised October 2005
Device Configurations
2.6
Debugging Considerations
It is recommended that external connections be provided to device configuration pins, including
TOUT1/LENDIAN, AEA[22:19] and TOUT0/MAC_EN. Although internal pullup/pulldown resistors exist on
these pins, providing external connectivity adds convenience to the user in debugging and flexibility in
switching operating modes.
Internal pullup/pulldown resistors also exist on the non-configuration pins on the AEA bus (AEA[18:0]). Do not
oppose the internal pullup/pulldown resistors on these non-configuration pins with external pullup/pulldown
resistors. If an external controller provides signals to these non-configuration pins, these signals must be
driven to the default state of the pins at reset, or not be driven at all.
For the internal pullup/pulldown resistors for all device pins, see the terminal functions table.
2.7
Configuration Examples
Figure 2−6 through Figure 2−9 illustrate examples of peripheral selections that are configurable on the DM641
and DM640 devices.
77
June 2003 − Revised October 2005
SPRS222E
Device Configurations
32
AED[31:0]
EMIFA
AECLKIN, AARDY, AHOLD
AEA[22:3], ACE[3:0], ABE[3:0],
AECLKOUT1, AECLKOUT2,
ASDCKE, ASOE3, APDT,
AHOLDA, ABUSREQ,
AARE/ASDCAS/ASADS/ASRE,
AAOE/ASDRAS/ASOE,
16
HD[15:0]
Clock
and
System
HPI
(16-Bit)
HRDY, HINT
HCNTL0, HCNTL1,
HHWIL, HAS, HR/W,
HCS, HDS1, HDS2
AAWE/ASDWE/ASWE
CLKIN,
CLKMODE0, CLKMODE1
MTXD[3:0], MTXEN
EMAC
MDIO
TIMER2
TIMER1
TIMER0
CLKOUT4, CLKOUT6, PLLV
MRXD[3:0], MRXER,
MRXDV, MCOL, MCRS,
MTCLK, MRCLK
TINP1
MDIO, MDCLK
TOUT1/LENDIAN
†
STCLK
TINP0
VP0
(8-Bit)
VP0CLK0
VP0CLK1,
VP0CTL[2:0],
VP0D[7:0]
TOUT0/MAC_EN
GP0
and
EXT_INT
GP0[3:0]
GP0[7:4]
McBSP0
AHCLKX0, AFSX0,
ACLKX0, AMUTE0,
AMUTEIN0,
AHCLKR0, AFSR0,
ACLKR0
McASP0 Control
McASP0 Data
SCL0
SDA0
I2C0
VIC
AXR0[3:0]
VDAC
McBSP1
†
STCLK
VP1
(8-Bit)
VP1CLK0
VP1CLK1,
VP1CTL[2:0],
VP1D[7:0]
Shading denotes a peripheral module not available for this configuration.
STCLK supports both video ports (VP1 and VP0).
†
PERCFG Register Value:
Extenal Pins:
0x0000 0039
TOUT0/MAC_EN = 1
Figure 2−6. Configuration Example A for DM641
(2 8-Bit Video Ports + 1 McASP0 + VIC + I2C0 + EMIF)
[TBD Application]
78
SPRS222E
June 2003 − Revised October 2005
Device Configurations
32
AED[31:0]
EMIFA
AECLKIN, AARDY, AHOLD
AEA[22:3], ACE[3:0], ABE[3:0],
AECLKOUT1, AECLKOUT2,
ASDCKE, ASOE3, APDT,
AHOLDA, ABUSREQ,
AARE/ASDCAS/ASADS/ASRE,
AAOE/ASDRAS/ASOE,
16
HD[15:0]
Clock
and
System
HPI
(16-Bit)
HRDY, HINT
HCNTL0, HCNTL1,
HHWIL, HAS, HR/W,
HCS, HDS1, HDS2
AAWE/ASDWE/ASWE
CLKIN,
CLKMODE0, CLKMODE1
MTXD[3:0], MTXEN
EMAC
MDIO
TIMER2
TIMER1
TIMER0
CLKOUT4, CLKOUT6, PLLV
MRXD[3:0], MRXER,
MRXDV, MCOL, MCRS,
MTCLK, MRCLK
TINP1
MDIO, MDCLK
TOUT1/LENDIAN
TINP0
VP0
(8-Bit)
TOUT0/MAC_EN
CLKR0, FSR0, DR0,
CLKS0, DX0, FSX0,
CLKX0
GP0
and
EXT_INT
GP0[3:0]
GP0[7:4]
McBSP0
AHCLKX0, AFSX0,
ACLKX0, AMUTE0,
AMUTEIN0, AHCLKR0,
AFSR0, ACLKR0
McASP0 Control
McASP0 Data
SCL0
SDA0
I2C0
VIC
AXR0[3:0]
CLKR1, FSR1, DR1,
CLKS1, DX1, FSX1,
CLKX1
VDAC
McBSP1
VP1
(8-Bit)
Shading denotes a peripheral module not available for this configuration.
PERCFG Register Value:
Extenal Pins:
0x0000 000F
TOUT0/MAC_EN = 1
Figure 2−7. Configuration Example B for DM641
(1 McASP0 + 2 McBSPs + VIC + I2C0 + EMIF)
[TBD Application]
79
June 2003 − Revised October 2005
SPRS222E
Device Configurations
32
AED[31:0]
EMIFA
AECLKIN, AARDY, AHOLD
AEA[22:3], ACE[3:0], ABE[3:0],
AECLKOUT1, AECLKOUT2,
ASDCKE, ASOE3, APDT,
AHOLDA, ABUSREQ,
AARE/ASDCAS/ASADS/ASRE,
AAOE/ASDRAS/ASOE,
Clock
and
System
AAWE/ASDWE/ASWE
CLKIN,
CLKMODE0, CLKMODE1
MTXD[3:0], MTXEN
EMAC
MDIO
TIMER2
TIMER1
TIMER0
CLKOUT4, CLKOUT6, PLLV
MRXD[3:0], MRXER,
MRXDV, MCOL, MCRS,
MTCLK, MRCLK
TINP1
MDIO, MDCLK
TOUT1/LENDIAN
STCLK
TINP0
VP0
(8-Bit)
VP0CLK0
VP0CLK1,
VP0CTL[2:0],
VP0D[7:0]
TOUT0/MAC_EN
GP0
and
EXT_INT
GP0[3:0]
GP0[7:4]
McBSP0
AHCLKX0, AFSX0,
ACLKX0, AMUTE0,
AMUTEIN0,
AHCLKR0, AFSR0,
ACLKR0
McASP0 Control
McASP0 Data
SCL0
SDA0
I2C0
VIC
AXR0[3:0]
VDAC
McBSP1
Shading denotes a peripheral module not available for this configuration.
PERCFG Register Value:
0x0000 0019
Extenal Pins:
TOUT0/MAC_EN = 1
Figure 2−8. Configuration Example A for DM640
(1 8-Bit Video Port + 1 McASP0 + VIC + I2C0 + EMIF)
[TBD Application]
80
SPRS222E
June 2003 − Revised October 2005
Device Configurations
32
AED[31:0]
EMIFA
AECLKIN, AARDY, AHOLD
AEA[22:3], ACE[3:0], ABE[3:0],
AECLKOUT1, AECLKOUT2,
ASDCKE, ASOE3, APDT,
AHOLDA, ABUSREQ,
AARE/ASDCAS/ASADS/ASRE,
AAOE/ASDRAS/ASOE,
Clock
and
System
AAWE/ASDWE/ASWE
CLKIN,
CLKMODE0, CLKMODE1
MTXD[3:0], MTXEN
EMAC
MDIO
TIMER2
TIMER1
TIMER0
CLKOUT4, CLKOUT6, PLLV
MRXD[3:0], MRXER,
MRXDV, MCOL, MCRS,
MTCLK, MRCLK
TINP1
MDIO, MDCLK
TOUT1/LENDIAN
TINP0
VP0
(8-Bit)
TOUT0/MAC_EN
CLKR0, FSR0, DR0,
CLKS0, DX0, FSX0,
CLKX0
GP0
and
EXT_INT
GP0[3:0]
GP0[7:4]
McBSP0
AHCLKX0, AFSX0,
ACLKX0, AMUTE0,
AMUTEIN0, AHCLKR0,
AFSR0, ACLKR0
McASP0 Control
McASP0 Data
SCL0
SDA0
I2C0
VIC
AXR0[3:0]
CLKR1, FSR1, DR1,
CLKS1, DX1, FSX1,
CLKX1
VDAC
McBSP1
Shading denotes a peripheral module not available for this configuration.
PERCFG Register Value:
Extenal Pins:
0x0000 000F
TOUT0/MAC_EN = 1
Figure 2−9. Configuration Example B for DM640
(1 McASP0 + 2 McBSPs + VIC + I2C0 + EMIF)
[TBD Application]
81
June 2003 − Revised October 2005
SPRS222E
Device Operating Conditions
3
Device Operating Conditions
3.1
Absolute Maximum Ratings Over Operating Case Temperature Range (Unless Otherwise
Noted)†
Supply voltage ranges:
CV (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 0.3 V to 1.8 V
DD
DV (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 4 V
DD
Input voltage ranges:
Output voltage ranges:
V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 4 V
I
V
O
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 4 V
Operating case temperature ranges, T : (default) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0_C to 90_C
C
Storage temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65_C to 150_C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to V
SS
.
3.2
Recommended Operating Conditions
MIN
1.14
1.36
3.14
0
NOM
1.2
1.4
3.3
0
MAX
1.26
1.44
3.46
0
UNIT
V
‡
Supply voltage, Core (-400 and -500 devices)
CV
DV
DD
‡
Supply voltage, Core (-600 device)
V
Supply voltage, I/O
Supply ground
V
DD
V
V
V
V
V
V
SS
High-level input voltage
Low-level input voltage
2
V
IH
IL
0.8
V
§
Maximum voltage during overshoot (see Figure 4−4)
Maximum voltage during undershoot (see Figure 4−5)
Operating case temperature
4.3
V
OS
US
C
§
−1.0
V
T
0
90
_C
‡
§
Future variants of the C64x DSPs may operate at voltages ranging from 0.9 V to 1.4 V to provide a range of system power/performance options.
TI highly recommends that users design-in a supply that can handle multiple voltages within this range (i.e., 1.2 V, 1.25 V, 1.3 V, 1.35 V, 1.4 V
with 3% tolerances) by implementing simple board changes such as reference resistor values or input pin configuration modifications. Examples
of such supplies include the PT4660, PT5500, PT5520, PT6440, and PT6930 series from Power Trends, a subsidiary of Texas Instruments. Not
incorporating a flexible supply may limit the system’s ability to easily adapt to future versions of C64x devices.
The absolute maximum ratings should not be exceeded for more than 30% of the cycle period.
82
SPRS222E
June 2003 − Revised October 2005
Device Operating Conditions
3.3
Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating
Case Temperature (Unless Otherwise Noted)
†
PARAMETER
High-level output voltage
Low-level output voltage
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V
V
V
DV = MIN,
I
I
= MAX
= MAX
2.4
OH
DD
OH
OL
DV = MIN,
0.4
10
V
OL
DD
V = V to DV no opposing internal
I
SS
DD
uA
uA
resistor
V = V to DV opposing internal
I
SS
DD
50
100
150
I
I
Input current
‡
pullup resistor
V = V to DV opposing internal
pulldown resistor
I
SS
DD
−150
−100
−50
−16
−8
uA
mA
mA
‡
EMIF, CLKOUT4, CLKOUT6, EMUx
Video Ports, Timer, TDO, GPIO
(Excluding GP0[2,1]), McBSP
I
I
High-level output current
OH
HPI [DM641]
−0.5
mA
mA
EMIF, CLKOUT4, CLKOUT6, EMUx
16
Video Ports, Timer, TDO, GPIO
(Excluding GP0[2,1]), McBSP
8
mA
Low-level output current
Off-state output current
OL
SCL0 and SDA0
3
mA
mA
HPI [DM641]
1.5
I
I
V
O
= DV or 0 V
10
uA
mA
mA
mA
mA
mA
mA
pF
OZ
DD
CV = 1.4 V, CPU clock = 600 MHz
890
620
510
210
165
160
DD
§
CV = 1.2 V, CPU clock = 500 MHz
Core supply current
DD
CDD
CV = 1.2 V, CPU clock = 400 MHz
DD
DV = 3.3 V, CPU clock = 600 MHz
DD
§
DV = 3.3 V, CPU clock = 500 MHz
I
I/O supply current
DD
DDD
DV = 3.3 V, CPU clock = 400 MHz
DD
C
C
Input capacitance
Output capacitance
10
10
i
pF
o
†
‡
§
For test conditions shown as MIN, MAX, or NOM, use the appropriate value specified in the recommended operating conditions table.
Applies only to pins with an internal pullup (IPU) or pulldown (IPD) resistor.
Measured with average activity (50% high/50% low power) at 25°C case temperature and 133-MHz EMIF for -600 speed (100-MHz EMIF for
-500 and -400 speeds). This model represents a device performing high-DSP-activity operations 50% of the time, and the remainder performing
low-DSP-activity operations. The high/low-DSP-activity models are defined as follows:
High-DSP-Activity Model:
CPU: 8 instructions/cycle with 2 LDDW instructions [L1 Data Memory: 128 bits/cycle via LDDW instructions;
L1 Program Memory: 256 bits/cycle; L2/EMIF EDMA: 50% writes, 50% reads to/from SDRAM (50% bit-switching)]
McBSP: 2 channels at E1 rate
Timers: 2 timers at maximum rate
Low-DSP-Activity Model:
CPU: 2 instructions/cycle with 1 LDH instruction [L1 Data Memory: 16 bits/cycle; L1 Program Memory: 256 bits per 4 cycles;
L2/EMIF EDMA: None]
McBSP: 2 channels at E1 rate
Timers: 2 timers at maximum rate
The actual current draw is highly application-dependent. For more details on core and I/O activity, refer to the TMS320DMx Power Consumption
Summary application report (literature number SPRA962).
83
June 2003 − Revised October 2005
SPRS222E
DM641/DM640 Peripheral Information and Electrical Specifications
4
DM641/DM640 Peripheral Information and Electrical Specifications
Parameter Information
4.1
4.1.1
Parameter Information Device-Specific Information
Tester Pin Electronics
Data Sheet Timing Reference Point
42 Ω
3.5 nH
Output
Under
Test
Transmission Line
Z0 = 50 Ω
(see note)
Device Pin
(see note)
4.0 pF
1.85 pF
NOTE: The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its transmission line effects
must be taken into account. A transmission line with a delay of 2 ns or longer can be used to produce the desired transmission line effect.
The transmission line is intended as a load only. It is not necessary to add or subtract the transmission line delay (2 ns or longer) from
the data sheet timings.
Input requirements in this data sheet are tested with an input slew rate of < 4 Volts per nanosecond (4 V/ns) at the device pin.
Figure 4−1. Test Load Circuit for AC Timing Measurements
The load capacitance value stated is only for characterization and measurement of AC timing signals. This
load capacitance value does not indicate the maximum load the device is capable of driving.
4.1.1.1 Signal Transition Levels
All input and output timing parameters are referenced to 1.5 V for both “0” and “1” logic levels.
V
ref
= 1.5 V
Figure 4−2. Input and Output Voltage Reference Levels for AC Timing Measurements
All rise and fall transition timing parameters are referenced to V MAX and V MIN for input clocks, V MAX
IL
IH
OL
and V MIN for output clocks.
OH
V
ref
= V MIN (or V MIN)
IH OH
V
ref
= V MAX (or V MAX)
IL OL
Figure 4−3. Rise and Fall Transition Time Voltage Reference Levels
4.1.1.2 Signal Transition Rates
All timings are tested with an input edge rate of 4 Volts per nanosecond (4 V/ns).
84
SPRS222E
June 2003 − Revised October 2005
Parameter Information
4.1.1.3 AC Transient Rise/Fall Time Specifications
Figure 4−4 and Figure 4−5 show the AC transient specifications for Rise and Fall Time. For device-specific
information on these values, refer to the Recommended Operating Conditions section of this Data Sheet.
†
t = 0.3 t (max)
c
V
OS
(max)
Minimum
Risetime
V
IH
(min)
Waveform
Valid Region
Ground
Figure 4−4. AC Transient Specification Rise Time
t = the peripheral cycle time in nanoseconds (ns).
†
c
†
t = 0.3 t (max)
c
V
IL
(max)
V
US
(max)
Ground
Figure 4−5. AC Transient Specification Fall Time
t = the peripheral cycle time in nanoseconds (ns).
†
c
4.1.1.4 Timing Parameters and Board Routing Analysis
The timing parameter values specified in this data sheet do not include delays by board routings. As a good
board design practice, such delays must always be taken into account. Timing values may be adjusted by
increasing/decreasing such delays. TI recommends utilizing the available I/O buffer information specification
(IBIS) models to analyze the timing characteristics correctly. To properly use IBIS models to attain accurate
timing analysis for a given system, see the Using IBIS Models for Timing Analysis application report (literature
number SPRA839). If needed, external logic hardware such as buffers may be used to compensate any timing
differences.
For inputs, timing is most impacted by the round-trip propagation delay from the DSP to the external device
and from the external device to the DSP. This round-trip delay tends to negatively impact the input setup time
margin, but also tends to improve the input hold time margins (see Table 4−1 and Figure 4−6).
Figure 4−6 represents a general transfer between the DSP and an external device. The figure also represents
board route delays and how they are perceived by the DSP and the external device.
85
June 2003 − Revised October 2005
SPRS222E
Power Supplies
Table 4−1. Board-Level Timing Example (see Figure 4−6)
NO.
1
DESCRIPTION
Clock route delay
2
Minimum DSP hold time
3
Minimum DSP setup time
External device hold time requirement
External device setup time requirement
Control signal route delay
External device hold time
4
5
6
7
8
External device access time
DSP hold time requirement
DSP setup time requirement
Data route delay
9
10
11
ECLKOUTx
(Output from DSP)
1
ECLKOUTx
(Input to External Device)
2
3
†
Control Signals
(Output from DSP)
4
5
6
Control Signals
(Input to External Device)
7
8
‡
Data Signals
(Output from External Device)
9
10
11
‡
Data Signals
(Input to DSP)
† Control signals include data for Writes.
‡ Data signals are generated during Reads from an external device.
Figure 4−6. Board-Level Input/Output Timings
4.2
4.3
Recommended Clock and Control Signal Transition Behavior
All clocks and control signals must transition between V and V (or between V and V ) in a monotonic
IH
IL
IL
IH
manner.
Power Supplies
For more information regarding TI’s power management products and suggested devices to power TI DSPs,
visit www.ti.com/dsppower.
4.3.1
Power-Supply Sequencing
TI DSPs do not require specific power sequencing between the core supply and the I/O supply. However,
systems should be designed to ensure that neither supply is powered up for extended periods of time
(>1 second) if the other supply is below the proper operating voltage.
86
SPRS222E
June 2003 − Revised October 2005
Power Supplies
4.3.2
Power-Supply Design Considerations
A dual-power supply with simultaneous sequencing can be used to eliminate the delay between core and I/O
power up. A Schottky diode can also be used to tie the core rail to the I/O rail (see Figure 4−7).
I/O Supply
DV
DD
Schottky
Diode
C6000
DSP
Core Supply
CV
DD
V
SS
GND
Figure 4−7. Schottky Diode Diagram
Core and I/O supply voltage regulators should be located close to the DSP (or DSP array) to minimize
inductance and resistance in the power delivery path. Additionally, when designing for high-performance
applications utilizing the C6000™ platform of DSPs, the PC board should include separate power planes for
core, I/O, and ground, all bypassed with high-quality low-ESL/ESR capacitors.
4.3.3
Power-Supply Decoupling
In order to properly decouple the supply planes from system noise, place as many capacitors (caps) as
possible close to the DSP. Assuming 0603 caps, the user should be able to fit a total of 60 caps, 30 for the
core supply and 30 for the I/O supply. These caps need to be close to the DSP power pins, no more than
1.25 cm maximum distance to be effective. Physically smaller caps, such as 0402, are better because of their
lower parasitic inductance. Proper capacitance values are also important. Small bypass caps (near 560 pF)
should be closest to the power pins. Medium bypass caps (220 nF or as large as can be obtained in a small
package) should be next closest. TI recommends no less than 8 small and 8 medium caps per supply (32 total)
be placed immediately next to the BGA vias, using the “interior” BGA space and at least the corners of the
“exterior”.
Eight larger caps (4 for each supply) can be placed further away for bulk decoupling. Large bulk caps (on the
order of 100 µF) should be furthest away (but still as close as possible). No less than 4 large caps per supply
(8 total) should be placed outside of the BGA.
Any cap selection needs to be evaluated from a yield/manufacturing point-of-view. As with the selection of any
component, verification of capacitor availability over the product’s production lifetime should be considered.
87
June 2003 − Revised October 2005
SPRS222E
Power Supplies
4.3.4
Peripheral Power-Down Operation
The DM641/DM640 device can be powered down in three ways:
•
•
Power-down due to pin configuration
Power-down due to software configuration − relates to the default state of the peripheral configuration bits
in the PERCFG register.
•
Power-down during run-time via software configuration
On the DM641/DM640 device, the EMAC and MDIO peripherals are controlled (selected) at the pin level
during chip reset (e.g., using the MAC_EN pin).
The McASP0, McBSP0, McBSP1, VP0, VP1 [DM641 only], and I2C0 peripheral functions are selected via the
peripheral configuration (PERCFG) register bits.
For more detailed information on the peripheral configuration pins and the PERCFG register bits, see the
Device Configurations section of this document.
4.3.5
Power-Down Modes Logic
Figure 4−8 shows the power-down mode logic on the DM641/DM640.
CLKOUT4
CLKOUT6
Internal Clock Tree
Clock
Distribution
and Dividers
PD1
PD2
IFR
Power-
Internal
Peripherals
Clock
PLL
IER
CSR
Down
Logic
PWRD
CPU
PD3
TMS320DM641/DM640
CLKIN
RESET
†
External input clocks, with the exception of CLKIN, are not gated by the power-down mode logic.
†
Figure 4−8. Power-Down Mode Logic
88
SPRS222E
June 2003 − Revised October 2005
Power Supplies
4.3.6
Triggering, Wake-up, and Effects
The power-down modes and their wake-up methods are programmed by setting the PWRD field (bits 15−10)
of the control status register (CSR). The PWRD field of the CSR is shown in Figure 4−9 and described in
Table 4−2. When writing to the CSR, all bits of the PWRD field should be set at the same time. Logic 0 should
be used when writing to the reserved bit (bit 15) of the PWRD field. The CSR is discussed in detail in the
TMS320C6000 CPU and Instruction Set Reference Guide (literature number SPRU189).
31
16
15
14
13
12
11
10
9
8
Enable or
Non-Enabled
Interrupt Wake
Enabled
Interrupt Wake
Reserved
R/W-0
PD3
PD2
PD1
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
7
0
Legend: R/W−x = Read/write reset value
NOTE: The shadowed bits are not part of the power-down logic discussion and therefore are not covered here. For information on these other
bit fields in the CSR register, see the TMS320C6000 CPU and Instruction Set Reference Guide (literature number SPRU189).
Figure 4−9. PWRD Field of the CSR Register
A delay of up to nine clock cycles may occur after the instruction that sets the PWRD bits in the CSR before the
PD mode takes effect. As best practice, NOPs should be padded after the PWRD bits are set in the CSR to
account for this delay.
If PD1 mode is terminated by a non-enabled interrupt, the program execution returns to the instruction where
PD1 took effect. If PD1 mode is terminated by an enabled interrupt, the interrupt service routine will be executed
first, then the program execution returns to the instruction where PD1 took effect. In the case with an enabled
interrupt, the GIE bit in the CSR and the NMIE bit in the interrupt enable register (IER) must also be set in order
for the interrupt service routine to execute; otherwise, execution returns to the instruction where PD1 took effect
upon PD1 mode termination by an enabled interrupt.
PD2 and PD3 modes can only be aborted by device reset. Table 4−2 summarizes all the power-down modes.
89
June 2003 − Revised October 2005
SPRS222E
Enhanced Direct Memory Access (EDMA) Controller
Table 4−2. Characteristics of the Power-Down Modes
PRWD FIELD
(BITS 15−10)
POWER-DOWN
WAKE-UP METHOD
—
EFFECT ON CHIP’S OPERATION
MODE
000000
001001
No power-down
—
CPU halted (except for the interrupt logic)
PD1
Wake by an enabled interrupt
Power-down mode blocks the internal clock inputs at the
boundary of the CPU, preventing most of the CPU’s logic from
switching. During PD1, EDMA transactions can proceed between
peripherals and internal memory.
Wake by an enabled or
non-enabled interrupt
010001
011010
PD1
Output clock from PLL is halted, stopping the internal clock
structure from switching and resulting in the entire chip being
halted. All register and internal RAM contents are preserved. All
functional I/O “freeze” in the last state when the PLL clock is
turned off.
†
PD2
Wake by a device reset
Input clock to the PLL stops generating clocks. All register and
internal RAM contents are preserved. All functional I/O “freeze” in
the last state when the PLL clock is turned off. Following reset, the
PLL needs time to re-lock, just as it does following power-up.
Wake-up from PD3 takes longer than wake-up from PD2 because
the PLL needs to be re-locked, just as it does following power-up.
†
011100
PD3
Wake by a device reset
All others
Reserved
—
—
†
When entering PD2 and PD3, all functional I/O remains in the previous state. However, for peripherals which are asynchronous in nature or
peripherals with an external clock source, output signals may transition in response to stimulus on the inputs. Under these conditions,
peripherals will not operate according to specifications.
4.3.7
C64x Power-Down Mode with an Emulator
If user power-down modes are programmed, and an emulator is attached, the modes will be masked to allow
the emulator access to the system. This condition prevails until the emulator is reset or the cable is removed
from the header. If power measurements are to be performed when in a power-down mode, the emulator cable
should be removed.
When the DSP is in power-down mode PD2 or PD3, emulation logic will force any emulation execution
command (such as Step or Run) to spin in IDLE. For this reason, PC writes (such as loading code) will fail.
A DSP reset will be required to get the DSP out of PD2/PD3.
4.4
Enhanced Direct Memory Access (EDMA) Controller
The EDMA controller handles all data transfers between the level-two (L2) cache/memory controller and the
device peripherals on the DM641/DM640 DSP. These data transfers include cache servicing, non-cacheable
memory accesses, user-programmed data transfers, and host accesses.
4.4.1
EDMA Device-Specific Information
4.4.1.1 EDMA Channel Synchronization Events
The C64x EDMA supports up to 64 EDMA channels which service peripheral devices and external memory.
Table 4−3 lists the source of C64x EDMA synchronization events associated with each of the programmable
EDMA channels. For the DM641/DM640 device, the association of an event to a channel is fixed; each of the
EDMA channels has one specific event associated with it. These specific events are captured in the EDMA
event registers (ERL, ERH) even if the events are disabled by the EDMA event enable registers (EERL,
EERH). The priority of each event can be specified independently in the transfer parameters stored in the
EDMA parameter RAM. For more detailed information on the EDMA module and how EDMA events are
enabled, captured, processed, linked, chained, and cleared, etc., see the TMS320C6000 DSP Enhanced
Direct Memory Access (EDMA) Controller Reference Guide (literature number SPRU234).
90
SPRS222E
June 2003 − Revised October 2005
Enhanced Direct Memory Access (EDMA) Controller
†
Table 4−3. TMS320DM641/DM640 EDMA Channel Synchronization Events
EDMA
CHANNEL
EVENT NAME
EVENT DESCRIPTION
0
1
DSP_INT
TINT0
HPI-to-DSP interrupt [For DM641 Only; “None” for DM640]
Timer 0 interrupt
2
TINT1
Timer 1 interrupt
3
SD_INTA
GPINT4/EXT_INT4
GPINT5/EXT_INT5
GPINT6/EXT_INT6
GPINT7/EXT_INT7
GPINT0
EMIFA SDRAM timer interrupt
GP0 event 4/External interrupt pin 4
GP0 event 5/External interrupt pin 5
GP0 event 6/External interrupt pin 6
GP0 event 7/External interrupt pin 7
GP0 event 0
4
5
6
7
8
9
GPINT1
GP0 event 1
10
11
12
13
14
15
16
17
18
19
20−31
32
33
34
35
36
37
38−43
44
45
46−47
48
49
50
51
52
53
54
55
56
GPINT2
GP0 event 2
GPINT3
GP0 event 3
XEVT0
McBSP0 transmit event
McBSP0 receive event
McBSP1 transmit event
McBSP1 receive event
VP0 Channel A Y event DMA request
VP0 Channel A Cb event DMA request
VP0 Channel A Cr event DMA request
Timer 2 interrupt
REVT0
XEVT1
REVT1
VP0EVTYA
VP0EVTUA
VP0EVTVA
TINT2
–
None
AXEVTE0
AXEVTO0
AXEVT0
McASP0 transmit even event
McASP0 transmit odd event
McASP0 transmit event
McASP0 receive even event
McASP0 receive odd event
McASP0 receive event
None
AREVTE0
AREVTO0
AREVT0
–
ICREVT0
ICXEVT0
–
I2C0 receive event
I2C0 transmit event
None
GPINT8
GP0 event 8
GPINT9
GP0 event 9
GPINT10
GPINT11
GPINT12
GPINT13
GPINT14
GPINT15
VP1EVTYA
GP0 event 10
GP0 event 11
GP0 event 12
GP0 event 13
GP0 event 14
GP0 event 15
VP1 Channel A Y event DMA request [For DM641 Only; “None” for DM640]
†
In addition to the events shown in this table, each of the 64 channels can also be synchronized with the transfer completion or alternate transfer
completion events. For more detailed information on EDMA event-transfer chaining, see the TMS320C6000 DSP Enhanced Direct Memory
Access (EDMA) Controller Reference Guide (literature number SPRU234).
91
June 2003 − Revised October 2005
SPRS222E
Enhanced Direct Memory Access (EDMA) Controller
†
Table 4−3. TMS320DM641/DM640 EDMA Channel Synchronization Events (Continued)
EDMA
CHANNEL
EVENT NAME
EVENT DESCRIPTION
57
58
VP1EVTUA
VP1EVTVA
–
VP1 Channel A Cb event DMA request [For DM641 Only; “None” for DM640]
VP1 Channel A Cr event DMA request [For DM641 Only; “None” for DM640]
None
59−63
†
In addition to the events shown in this table, each of the 64 channels can also be synchronized with the transfer completion or alternate transfer
completion events. For more detailed information on EDMA event-transfer chaining, see the TMS320C6000 DSP Enhanced Direct Memory
Access (EDMA) Controller Reference Guide (literature number SPRU234).
4.4.2
EDMA Peripheral Register Description(s)
Table 4−4. EDMA Registers (C64x)
HEX ADDRESS RANGE
ACRONYM
−
REGISTER NAME
01A0 0800 − 01A0 FF98
01A0 FF9C
01A0 FFA4
Reserved
EPRH
CIPRH
CIERH
CCERH
ERH
Event polarity high register
Channel interrupt pending high register
Channel interrupt enable high register
Channel chain enable high register
Event high register
01A0 FFA8
01A0 FFAC
01A0 FFB0
01A0 FFB4
EERH
ECRH
ESRH
PQAR0
PQAR1
PQAR2
PQAR3
EPRL
PQSR
CIPRL
CIERL
CCERL
ERL
Event enable high register
Event clear high register
01A0 FFB8
01A0 FFBC
01A0 FFC0
01A0 FFC4
01A0 FFC8
01A0 FFCC
01A0 FFDC
01A0 FFE0
Event set high register
Priority queue allocation register 0
Priority queue allocation register 1
Priority queue allocation register 2
Priority queue allocation register 3
Event polarity low register
Priority queue status register
Channel interrupt pending low register
Channel interrupt enable low register
Channel chain enable low register
Event low register
01A0 FFE4
01A0 FFE8
01A0 FFEC
01A0 FFF0
01A0 FFF4
EERL
ECRL
ESRL
–
Event enable low register
01A0 FFF8
Event clear low register
01A0 FFFC
01A1 0000 − 01A3 FFFF
Event set low register
Reserved
92
SPRS222E
June 2003 − Revised October 2005
Enhanced Direct Memory Access (EDMA) Controller
Table 4−5. Quick DMA (QDMA) and Pseudo Registers
HEX ADDRESS RANGE
0200 0000
ACRONYM
QOPT
REGISTER NAME
QDMA options parameter register
0200 0004
QSRC
QCNT
QDMA source address register
QDMA frame count register
0200 0008
0200 000C
QDST
QDMA destination address register
QDMA index register
0200 0010
QIDX
0200 0014 − 0200 001C
0200 0020
Reserved
QSOPT
QSSRC
QSCNT
QSDST
QSIDX
QDMA pseudo options register
QDMA psuedo source address register
QDMA psuedo frame count register
QDMA destination address register
QDMA psuedo index register
0200 0024
0200 0028
0200 002C
0200 0030
93
June 2003 − Revised October 2005
SPRS222E
Enhanced Direct Memory Access (EDMA) Controller
†
Table 4−6. EDMA Parameter RAM (C64x)
HEX ADDRESS RANGE
ACRONYM
REGISTER NAME
Parameters for Event 0 (6 words)
COMMENTS
Parameters for Event 0
(6 words) or Reload/Link
Parameters for other Event
01A0 0000 − 01A0 0017
−
01A0 0018 − 01A0 002F
01A0 0030 − 01A0 0047
01A0 0048 − 01A0 005F
01A0 0060 − 01A0 0077
01A0 0078 − 01A0 008F
01A0 0090 − 01A0 00A7
01A0 00A8 − 01A0 00BF
01A0 00C0 − 01A0 00D7
01A0 00D8 − 01A0 00EF
01A0 00F0 − 01A0 00107
01A0 0108 − 01A0 011F
01A0 0120 − 01A0 0137
01A0 0138 − 01A0 014F
01A0 0150 − 01A0 0167
01A0 0168 − 01A0 017F
01A0 0150 − 01A0 0167
01A0 0168 − 01A0 017F
...
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
Parameters for Event 1 (6 words)
Parameters for Event 2 (6 words)
Parameters for Event 3 (6 words)
Parameters for Event 4 (6 words)
Parameters for Event 5 (6 words)
Parameters for Event 6 (6 words)
Parameters for Event 7 (6 words)
Parameters for Event 8 (6 words)
Parameters for Event 9 (6 words)
Parameters for Event 10 (6 words)
Parameters for Event 11 (6 words)
Parameters for Event 12 (6 words)
Parameters for Event 13 (6 words)
Parameters for Event 14 (6 words)
Parameters for Event 15 (6 words)
Parameters for Event 16 (6 words)
Parameters for Event 17 (6 words)
...
01A0 05D0 − 01A0 05E7
01A0 05E8 − 01A0 05FF
−
−
Parameters for Event 62 (6 words)
Parameters for Event 63 (6 words)
Reload/Link Parameters for
other Event 0−15
01A0 0600 − 01A0 0617
−
−
Reload/link parameters for Event 0 (6 words)
01A0 0618 − 01A0 062F
...
Reload/link parameters for Event 1 (6 words)
...
01A0 07E0 − 01A0 07F7
01A0 07F8 − 01A0 080F
01A0 0810 − 01A0 0827
...
−
−
−
Reload/link parameters for Event 20 (6 words)
Reload/link parameters for Event 21 (6 words)
Reload/link parameters for Event 22 (6 words)
...
01A0 13C8 − 01A0 13DF
01A0 13E0 − 01A0 13F7
01A0 13F8 − 01A0 13FF
01A0 1400 − 01A3 FFFF
−
−
−
−
Reload/link parameters for Event 147 (6 words)
Reload/link parameters for Event 148 (6 words)
Scratch pad area (2 words)
Reserved
†
The DM641/DM640 device has 213 EDMA parameters total: 64-Event/Reload channels and 149-Reload only parameter sets [six (6) words each]
that can be used to reload/link EDMA transfers.
94
SPRS222E
June 2003 − Revised October 2005
Interrupts
4.5
Interrupts
4.5.1
Interrupt Sources and Interrupt Selector
The C64x DSP core supports 16 prioritized interrupts, which are listed in Table 4−7. The highest-priority
interrupt is INT_00 (dedicated to RESET) while the lowest-priority interrupt is INT_15. The first four interrupts
(INT_00−INT_03) are non-maskable and fixed. The remaining interrupts (INT_04−INT_15) are maskable and
default to the interrupt source specified in Table 4−7. The interrupt source for interrupts 4−15 can be
programmed by modifying the selector value (binary value) in the corresponding fields of the Interrupt Selector
Control registers: MUXH (address 0x019C0000) and MUXL (address 0x019C0004).
Table 4−7. DM641/DM640 DSP Interrupts
INTERRUPT
CPU
INTERRUPT
NUMBER
SELECTOR
VALUE
(BINARY)
INTERRUPT
EVENT
SELECTOR
CONTROL
REGISTER
INTERRUPT SOURCE
†
INT_00
−
−
RESET
NMI
†
INT_01
−
−
†
INT_02
−
−
Reserved
Reserved. Do not use.
†
INT_03
−
−
Reserved
Reserved. Do not use.
‡
INT_04
MUXL[4:0]
00100
00101
00110
00111
01000
01001
00011
01010
01011
00000
00001
00010
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
GPINT4/EXT_INT4
GPINT5/EXT_INT5
GPINT6/EXT_INT6
GPINT7/EXT_INT7
EDMA_INT
EMU_DTDMA
SD_INTA
GP0 interrupt 4/External interrupt pin 4
GP0 interrupt 5/External interrupt pin 5
GP0 interrupt 6/External interrupt pin 6
GP0 interrupt 7/External interrupt pin 7
EDMA channel (0 through 63) interrupt
EMU DTDMA
‡
INT_05
MUXL[9:5]
‡
INT_06
MUXL[14:10]
‡
INT_07
MUXL[20:16]
‡
INT_08
MUXL[25:21]
‡
INT_09
MUXL[30:26]
‡
INT_10
MUXH[4:0]
EMIFA SDRAM timer interrupt
EMU real-time data exchange (RTDX) receive
EMU RTDX transmit
‡
INT_11
MUXH[9:5]
EMU_RTDXRX
EMU_RTDXTX
DSP_INT
‡
INT_12
MUXH[14:10]
‡
INT_13
MUXH[20:16]
HPI-to-DSP interrupt [DM641 Only]
Timer 0 interrupt
‡
INT_14
MUXH[25:21]
TINT0
‡
INT_15
MUXH[30:26]
TINT1
Timer 1 interrupt
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
XINT0
McBSP0 transmit interrupt
McBSP0 receive interrupt
McBSP1 transmit interrupt
McBSP1 receive interrupt
GP0 interrupt 0
RINT0
XINT1
RINT1
GPINT0
Reserved
Reserved. Do not use.
Reserved
Reserved. Do not use.
TINT2
Timer 2 interrupt
Reserved
Reserved. Do not use.
Reserved
Reserved. Do not use.
ICINT0
I2C0 interrupt
Reserved
Reserved. Do not use.
EMAC_MDIO_INT
VPINT0
EMAC/MDIO interrupt
VP0 interrupt
†
‡
Interrupts INT_00 through INT_03 are non-maskable and fixed.
Interrupts INT_04 through INT_15 are programmable by modifying the binary selector values in the Interrupt Selector Control registers fields.
Table 4−7 shows the default interrupt sources for Interrupts INT_04 through INT_15. For more detailed information on interrupt sources and
selection, see the TMS320C6000 DSP Interrupt Selector Reference Guide (literature number SPRU646).
95
June 2003 − Revised October 2005
SPRS222E
Reset
Table 4−7. DM641/DM640 DSP Interrupts (Continued)
INTERRUPT
CPU
INTERRUPT
NUMBER
SELECTOR
VALUE
(BINARY)
INTERRUPT
EVENT
SELECTOR
CONTROL
REGISTER
INTERRUPT SOURCE
−
−
−
−
−
−
−
−
−
−
11010
11011
VPINT1
Reserved
AXINT0
VP1 interrupt [DM641 Only]
Reserved. Do not use.
McASP0 transmit interrupt
McASP0 receive interrupt
Reserved. Do not use.
11100
11101
ARINT0
Reserved
11110 − 11111
†
‡
Interrupts INT_00 through INT_03 are non-maskable and fixed.
Interrupts INT_04 through INT_15 are programmable by modifying the binary selector values in the Interrupt Selector Control registers fields.
Table 4−7 shows the default interrupt sources for Interrupts INT_04 through INT_15. For more detailed information on interrupt sources and
selection, see the TMS320C6000 DSP Interrupt Selector Reference Guide (literature number SPRU646).
4.5.2
Interrupts Peripheral Register Description(s)
Table 4−8. Interrupt Selector Registers (C64x)
HEX ADDRESS RANGE
ACRONYM
REGISTER NAME
Interrupt multiplexer high
COMMENTS
Selects which interrupts drive CPU
interrupts 10−15 (INT10−INT15)
019C 0000
019C 0004
MUXH
Selects which interrupts drive CPU
interrupts 4−9 (INT04−INT09)
MUXL
Interrupt multiplexer low
Sets the polarity of the external
interrupts (EXT_INT4−EXT_INT7)
019C 0008
EXTPOL
External interrupt polarity
Reserved
019C 000C − 019F FFFF
−
4.5.3
External Interrupts Electrical Data/Timing
Table 4−9. Timing Requirements for External Interrupts (see Figure 4−10)
†
−400
−500
−600
NO.
UNIT
MIN
4P
MAX
Width of the NMI interrupt pulse low
Width of the EXT_INT interrupt pulse low
Width of the NMI interrupt pulse high
Width of the EXT_INT interrupt pulse high
ns
ns
ns
ns
1
t
t
w(ILOW)
8P
4P
8P
2
w(IHIGH)
†
P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns.
2
1
EXT_INTx, NMI
Figure 4−10. External/NMI Interrupt Timing
4.6
Reset
A hardware reset (RESET) is required to place the DSP into a known good state out of power-up. The RESET
signal can be asserted (pulled low) prior to ramping the core and I/O voltages or after the core and I/O voltages
have reached their proper operating conditions. As a best practice, reset should be held low during power-up.
Prior to deasserting RESET (low-to-high transition), the core and I/O voltages should be at their proper
operating conditions and CLKIN should also be running at the correct frequency.
96
SPRS222E
June 2003 − Revised October 2005
Reset
For information on peripheral selection at the rising edge of RESET, see the Device Configuration section of
this data manual.
4.6.1
Reset Electrical Data/Timing
Table 4−10. Timing Requirements for Reset (see Figure 4−11)
−400
−500
−600
NO.
UNIT
MIN
MAX
1
t
t
t
Width of the RESET pulse
250
µs
ns
ns
w(RST)
su(boot)
h(boot)
†
‡
16
Setup time, boot configuration bits valid before RESET high
4E or 4C
†
§
17
Hold time, boot configuration bits valid after RESET high
4P
†
AEA[22:19], LENDIAN, and HD5 are the boot configuration pins during device reset.
E = 1/AECLKIN clock frequency in ns. C = 1/CLKIN clock frequency in ns.
Select the MIN parameter value, whichever value is larger.
‡
§
P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns.
§¶#
Table 4−11. Switching Characteristics Over Recommended Operating Conditions During Reset
(see Figure 4−11)
−400
−500
−600
NO.
PARAMETER
UNIT
MIN
MAX
3P + 20E
8P + 20E
2
3
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Delay time, RESET low to AECLKIN synchronized internally
Delay time, RESET high to AECLKIN synchronized internally
Delay time, RESET low to AECLKOUT1 high impedance
Delay time, RESET high to AECLKOUT1 valid
Delay time, RESET low to EMIF Z high impedance
Delay time, RESET high to EMIF Z valid
2E
2E
2E
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
d(RSTL-ECKI)
d(RSTH-ECKI)
4
d(RSTL-ECKO1HZ)
d(RSTH-ECKO1V)
d(RSTL-EMIFZHZ)
d(RSTH-EMIFZV)
d(RSTL-EMIFHIV)
d(RSTH-EMIFHV)
d(RSTL-EMIFLIV)
d(RSTH-EMIFLV)
d(RSTL-LOWIV)
d(RSTH-LOWV)
d(RSTL-ZHZ)
5
8P + 20E
3P + 4E
6
2E
16E
2E
7
8P + 20E
8
Delay time, RESET low to EMIF high group invalid
Delay time, RESET high to EMIF high group valid
Delay time, RESET low to EMIF low group invalid
Delay time, RESET high to EMIF low group valid
Delay time, RESET low to low group invalid
9
8P + 20E
8P + 20E
11P
10
11
12
13
14
15
2E
0
Delay time, RESET high to low group valid
Delay time, RESET low to Z group high impedance
Delay time, RESET high to Z group valid
0
2P
8P
d(RSTH-ZV)
§
¶
#
P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns.
E = the EMIF input clock (AECLKIN, CPU/4 clock, or CPU/6 clock) period in ns for EMIFA.
EMIF Z group consists of:
AEA[22:3], AED[31:0], ACE[3:0], ABE[3:0], AARE/ASDCAS/ASADS/ASRE,AAWE/ASDWE/ASWE,
AAOE/ASDRAS/ASOE, ASOE3, ASDCKE, and APDT.
EMIF high group consists of: AHOLDA (when the corresponding AHOLD input is high)
EMIF low group consists of: ABUSREQ; AHOLDA (when the corresponding AHOLD input is low)
Low group consists of:
Z group consists of:
HD[15:0], VP0D[0]/CLKX0, VP0D[1]/FSX0, VP0D[2]/DX0, CLKR0, VP0D[5]/FSR0, TOUT0, TOUT1, VDAC,
GP0[7:0], HR/W, HDS2, HDS1, HCS, HCNTL1, HAS, HCNTL0, HHWIL (16-bit HPI mode only), HRDY, HINT, and
VP0D[4,3].
VP1 signals apply to DM641 only:
VP1D[0]/CLKX1, VP1D[1]/FSX1, VP1D[2]/DX1, VP1D[6]/CLKR1, VP1D[5]/FSR1, and VP1D[4,3].
97
June 2003 − Revised October 2005
SPRS222E
Reset
CLKOUT4
CLKOUT6
1
RESET
2
4
3
5
AECLKIN
AECLKOUT1
AECLKOUT2
6
7
†‡
EMIF Z Group
9
8
†
EMIF High Group
11
13
10
†
EMIF Low Group
12
14
†
Low Group
15
†‡
Z Group
16
17
Boot and Device
§
Configuration Inputs
†
EMIF Z group consists of:
AEA[22:3], AED[31:0], ACE[3:0], ABE[3:0], AARE/ASDCAS/ASADS/ASRE,AAWE/ASDWE/ASWE,
AAOE/ASDRAS/ASOE, ASOE3, ASDCKE, and APDT.
EMIF high group consists of: AHOLDA (when the corresponding AHOLD input is high)
EMIF low group consists of: ABUSREQ; AHOLDA (when the corresponding AHOLD input is low)
Low group consists of:
Z group consists of:
HD[15:0], VP0D[0]/CLKX0, VP0D[1]/FSX0, VP0D[2]/DX0, CLKR0, VP0D[5]/FSR0, TOUT0, TOUT1, VDAC,
GP0[7:0], HR/W, HDS2, HDS1, HCS, HCNTL1, HAS, HCNTL0, HHWIL (16-bit HPI mode only), HRDY, HINT, and
VP0D[4,3].
VP1 signals apply to DM641 only:
VP1D[0]/CLKX1, VP1D[1]/FSX1, VP1D[2]/DX1, VP1D[6]/CLKR1, VP1D[5]/FSR1, and VP1D[4,3].
If AEA[22:19], LENDIAN, and HD5 pins are actively driven, care must be taken to ensure
no timing contention between parameters 6, 7, 14, 15, 16, and 17.
‡
§
Boot and Device Configurations Inputs (during reset) include: AEA[22:19], LENDIAN, and HD5.
†
Figure 4−11. Reset Timing
98
SPRS222E
June 2003 − Revised October 2005
Clock PLL
4.7
Clock PLL
The PLL controller features hardware-configurable PLL multiplier controller, dividers (/2, /4, /6, and /8), and
reset controller. The PLL controller accepts an input clock, as determined by the logic state on the
CLKMODE[1:0] pins, from the CLKIN pin. The resulting clock outputs are passed to the DSP core, peripherals,
and other modules inside the C6000™ DSP.
4.7.1
Clock PLL Device-Specific Information
Most of the internal C64x™ DSP clocks are generated from a single source through the CLKIN pin. This source
clock either drives the PLL, which multiplies the source clock frequency to generate the internal CPU clock,
or bypasses the PLL to become the internal CPU clock.
To use the PLL to generate the CPU clock, the external PLL filter circuit must be properly designed.
Figure 4−12 shows the external PLL circuitry for either x1 (PLL bypass) or other PLL multiply modes.
To minimize the clock jitter, a single clean power supply should power both the C64x™ DSP device and the
external clock oscillator circuit. The minimum CLKIN rise and fall times should also be observed. For the input
clock timing requirements, see the input and output clocks electricals section.
Rise/fall times, duty cycles (high/low pulse durations), and the load capacitance of the external clock source
must meet the DSP requirements in this data sheet (see the electrical characteristics over recommended
ranges of supply voltage and operating case temperature table and the input and output clocks electricals
section).
99
June 2003 − Revised October 2005
SPRS222E
Clock PLL
3.3 V
CPU Clock
C1
C2
Peripheral Bus, EDMA
Clock
EMI
filter
/2
/8
/4
/6
10 µF 0.1 µF
Timer Internal Clock
PLLV
CLKOUT4, Peripheral Clock
(AUXCLK for McASP),
McBSP Internal Clock
CLKMODE0
CLKMODE1
CLKOUT6
PLLMULT
PLL
x6, x12
00 01 10
CLKIN
PLLCLK
1
0
/4
/2
ECLKIN
AEA[20:19]
EK2RATE
(GBLCTL.[19,18])
EMIF
00 01 10
Internal to DM641/DM640
(For the PLL Options, CLKMODE Pins Setup, and
PLL Clock Frequency Ranges, see Table 9.)
ECLKOUT1 ECLKOUT2
NOTES: A. Place all PLL external components (C1, C2, and the EMI Filter) as close to the C6000™ DSP device as possible. For the best
performance, TI recommends that all the PLL external components be on a single side of the board without jumpers, switches, or
components other than the ones shown.
B. For reduced PLL jitter, maximize the spacing between switching signals and the PLL external components (C1, C2, and the EMI
Filter).
C. The 3.3-V supply for the EMI filter must be from the same 3.3-V power plane supplying the I/O voltage, DV
.
DD
D. EMI filter manufacturer TDK part number ACF451832-333, -223, -153, -103. Panasonic part number EXCCET103U.
Figure 4−12. External PLL Circuitry for Either PLL Multiply Modes or x1 (Bypass) Mode
100
SPRS222E
June 2003 − Revised October 2005
Clock PLL
Table 4−12. TMS320DM641/DM640 PLL Multiply Factor Options, Clock Frequency Ranges,
†‡
and Typical Lock Time
GDK and ZDK PACKAGES − 23 x 23 mm BGA,
GNZ and ZNZ PACKAGES − 27 x 27 mm BGA
CLKMODE
CLKMODE1 CLKMODE0 (PLL MULTIPLY
FACTORS)
CLKIN
RANGE
(MHz)
CPU CLOCK
FREQUENCY
RANGE (MHz)
TYPICAL
CLKOUT4
RANGE (MHz)
CLKOUT6
RANGE (MHz)
LOCK TIME
§
(µs)
0
0
1
1
0
1
0
1
Bypass (x1)
x6
30−75
30−75
30−50
−
30−75
180−450
360−600
−
7.5−18.8
45−112.5
90−150
−
5−12.5
30−75
60−100
−
N/A
75
x12
Reserved
−
†
‡
These clock frequency range values are applicable to a DM641−600 speed device. For −400, −500 device speed values, see the CLKIN timing
requirements table for the specific device speed.
Use external pullup resistors on the CLKMODE pins (CLKMODE1 and CLKMODE0) to set the DM641/DM640 device to one of the valid PLL
multiply clock modes (x6 or x12). With internal pulldown resistors on the CLKMODE pins (CLKMODE1, CLKMODE0), the default clock mode
is x1 (bypass).
Under some operating conditions, the maximum PLL lock time may vary by as much as 150% from the specified typical value. For example, if
the typical lock time is specified as 100 µs, the maximum value may be as long as 250 µs.
§
4.7.2
Clock PLL Electrical Data/Timing (Input and Output Clocks)
†‡§
Table 4−13. Timing Requirements for CLKIN for −400 Devices
(see Figure 4−13)
−400
PLL MODE x6
PLL MODE x12
x1 (BYPASS)
NO.
UNIT
MIN
30
MAX
MIN
13.3
MAX
MIN
13.3
MAX
1
2
3
4
t
t
t
t
t
Cycle time, CLKIN
33.3
33.3
33.3
ns
ns
ns
ns
ns
c(CLKIN)
w(CLKINH)
w(CLKINL)
t(CLKIN)
Pulse duration, CLKIN high
Pulse duration, CLKIN low
Transition time, CLKIN
Period jitter, CLKIN
0.45C
0.45C
0.45C
0.45C
0.45C
0.45C
5
5
1
5
0.02C
0.02C
0.02C
J(CLKIN)
†
The reference points for the rise and fall transitions are measured at V MAX and V MIN.
For more details on the PLL multiplier factors (x6, x12), see the Clock PLL section of this data sheet.
C = CLKIN cycle time in ns. For example, when CLKIN frequency is 50 MHz, use C = 20 ns.
IL
IH
‡
§
†‡§
Table 4−14. Timing Requirements for CLKIN for −500 Devices
(see Figure 4−13)
−500
PLL MODE x6
PLL MODE x12
x1 (BYPASS)
NO.
UNIT
MIN
24
MAX
MIN
13.3
MAX
MIN
13.3
MAX
1
2
3
4
t
t
t
t
Cycle time, CLKIN
33.3
33.3
33.3
ns
ns
ns
ns
c(CLKIN)
w(CLKINH)
w(CLKINL)
t(CLKIN)
Pulse duration, CLKIN high
Pulse duration, CLKIN low
Transition time, CLKIN
0.45C
0.45C
0.45C
0.45C
0.45C
0.45C
5
5
1
5
t
Period jitter, CLKIN
0.02C
0.02C
0.02C
ns
J(CLKIN)
†
‡
§
The reference points for the rise and fall transitions are measured at V MAX and V MIN.
For more details on the PLL multiplier factors (x6, x12), see the Clock PLL section of this data sheet.
C = CLKIN cycle time in ns. For example, when CLKIN frequency is 50 MHz, use C = 20 ns.
IL
IH
101
June 2003 − Revised October 2005
SPRS222E
Clock PLL
†‡§
Table 4−15. Timing Requirements for CLKIN for −600 Devices
(see Figure 4−13)
−600
PLL MODE x6
PLL MODE x12
x1 (BYPASS)
NO.
UNIT
MIN
20
MAX
MIN
13.3
MAX
MIN
13.3
MAX
1
2
3
4
5
t
t
t
t
t
Cycle time, CLKIN
33.3
33.3
33.3
ns
ns
ns
ns
ns
c(CLKIN)
w(CLKINH)
w(CLKINL)
t(CLKIN)
Pulse duration, CLKIN high
Pulse duration, CLKIN low
Transition time, CLKIN
Period jitter, CLKIN
0.45C
0.45C
0.45C
0.45C
0.45C
0.45C
5
5
1
0.02C
0.02C
0.02C
J(CLKIN)
†
‡
§
The reference points for the rise and fall transitions are measured at V MAX and V MIN.
For more details on the PLL multiplier factors (x6, x12), see the Clock PLL section of this data sheet.
C = CLKIN cycle time in ns. For example, when CLKIN frequency is 50 MHz, use C = 20 ns.
IL
IH
1
5
4
2
CLKIN
3
4
Figure 4−13. CLKIN Timing
†‡§
Table 4−16. Switching Characteristics Over Recommended Operating Conditions for CLKOUT4
(see Figure 4−14)
−400
−500
−600
NO.
PARAMETER
UNIT
CLKMODE = x1, x6, x12
MIN
MAX
1
2
3
t
t
t
Pulse duration, CLKOUT4 high
2P − 0.7
2P − 0.7
2P + 0.7
2P + 0.7
1
ns
ns
ns
w(CKO4H)
w(CKO4L)
t(CKO4)
Pulse duration, CLKOUT4 low
Transition time, CLKOUT4
†
‡
§
The reference points for the rise and fall transitions are measured at V MAX and V MIN.
PH is the high period of CLKIN in ns and PL is the low period of CLKIN in ns.
P = 1/CPU clock frequency in nanoseconds (ns)
OL
OH
3
1
CLKOUT4
2
3
Figure 4−14. CLKOUT4 Timing
102
SPRS222E
June 2003 − Revised October 2005
Clock PLL
†‡§
Table 4−17. Switching Characteristics Over Recommended Operating Conditions for CLKOUT6
(see Figure 4−15)
−400
−500
−600
NO.
PARAMETER
UNIT
CLKMODE = x1, x6, x12
MIN
MAX
1
2
3
t
t
t
Pulse duration, CLKOUT6 high
3P − 0.7
3P − 0.7
3P + 0.7
3P + 0.7
1
ns
ns
ns
w(CKO6H)
w(CKO6L)
t(CKO6)
Pulse duration, CLKOUT6 low
Transition time, CLKOUT6
†
‡
§
The reference points for the rise and fall transitions are measured at V MAX and V MIN.
PH is the high period of CLKIN in ns and PL is the low period of CLKIN in ns.
P = 1/CPU clock frequency in nanoseconds (ns)
OL
OH
3
1
CLKOUT6
2
3
Figure 4−15. CLKOUT6 Timing
†‡§
Table 4−18. Timing Requirements for AECLKIN for EMIFA
(see Figure 4−16)
−400
−500
−600
NO.
UNIT
MIN
MAX
¶
1
2
3
4
t
t
t
t
Cycle time, AECLKIN
6
16P
ns
ns
ns
ns
c(EKI)
Pulse duration, AECLKIN high
Pulse duration, AECLKIN low
Transition time, AECLKIN
2.7
2.7
w(EKIH)
w(EKIL)
t(EKI)
3
5
t
Period jitter, AECLKIN
0.02E
ns
J(EKI)
†
‡
§
¶
P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns.
The reference points for the rise and fall transitions are measured at V MAX and V MIN.
E = the EMIF input clock (AECLKIN, CPU/4 clock, or CPU/6 clock) period in ns for EMIFA.
Minimum AECLKIN cycle times must be met, even when AECLKIN is generated by an internal clock source. Minimum AECLKIN times are based
on internal logic speed; the maximum useable speed of the EMIF may be lower due to AC timing requirements. On the 600 device, 133-MHz
operation is achievable if the requirements of the EMIF Device Speed section are met. On the 400 and 500 devices, 100-MHz operation is
achievable if the requirements of the EMIF Device Speed section are met.
IL
IH
1
5
4
2
AECLKIN
3
4
Figure 4−16. AECLKIN Timing for EMIFA
103
June 2003 − Revised October 2005
SPRS222E
Clock PLL
Table 4−19. Switching Characteristics Over Recommended Operating Conditions for AECLKOUT1 for the
§#||
EMIFA Module
(see Figure 4−17)
−400
−500
−600
NO.
PARAMETER
UNIT
MIN
MAX
1
2
3
4
5
t
t
t
t
t
Pulse duration, AECLKOUT1 high
Pulse duration, AECLKOUT1 low
Transition time, AECLKOUT1
EH − 0.7 EH + 0.7
EL − 0.7 EL + 0.7
1
ns
ns
ns
ns
ns
w(EKO1H)
w(EKO1L)
t(EKO1)
Delay time, AECLKIN high to AECLKOUT1 high
Delay time, AECLKIN low to AECLKOUT1 low
1
1
8
8
d(EKIH-EKO1H)
d(EKIL-EKO1L)
§
#
||
E = the EMIF input clock (AECLKIN, CPU/4 clock, or CPU/6 clock) period in ns for EMIFA.
The reference points for the rise and fall transitions are measured at V MAX and V MIN.
EH is the high period of E (EMIF input clock period) in ns and EL is the low period of E (EMIF input clock period) in ns for EMIFA.
OL
OH
kThis cycle-to-cycle jitter specification was measured with CPU/4 or CPU/6 as the source of the EMIF input clock.
AECLKIN
5
2
3
3
1
4
AECLKOUT1
Figure 4−17. AECLKOUT1 Timing for the EMIFA Module
Table 4−20. Switching Characteristics Over Recommended Operating Conditions for AECLKOUT2 for the
†‡
EMIFA Module (see Figure 4−18)
−400
−500
−600
NO.
PARAMETER
UNIT
MIN
MAX
1
2
3
4
5
t
t
t
t
t
Pulse duration, AECLKOUT2 high
0.5NE − 0.7
0.5NE − 0.7
0.5NE + 0.7
ns
ns
ns
ns
ns
w(EKO2H)
Pulse duration, AECLKOUT2 low
0.5NE + 0.7
w(EKO2L)
Transition time, AECLKOUT2
1
8
8
t(EKO2)
Delay time, AECLKIN high to AECLKOUT2 high
Delay time, AECLKIN low to AECLKOUT2 low
1
1
d(EKIH-EKO2H)
d(EKIL-EKO2L)
†
‡
The reference points for the rise and fall transitions are measured at V MAX and V MIN.
E = the EMIF input clock (AECLKIN, CPU/4 clock, or CPU/6 clock) period in ns for EMIFA.
N = the EMIF input clock divider; N = 1, 2, or 4.
OL
OH
§
This cycle-to-cycle jitter specification was measured with CPU/4 or CPU/6 as the source of the EMIF input clock.
AECLKIN
5
2
3
3
1
4
AECLKOUT2
Figure 4−18. AECLKOUT2 Timing for the EMIFA Module
104
SPRS222E
June 2003 − Revised October 2005
External Memory Interface (EMIIF)
4.8
External Memory Interface (EMIIF)
EMIF supports a glueless interface to a variety of external devices, including:
•
•
•
•
Pipelined synchronous-burst SRAM (SBSRAM)
Synchronous DRAM (SDRAM)
Asynchronous devices, including SRAM, ROM, and FIFOs
An external shared-memory device
4.8.1
EMIF Device-Specific Information
EMIF Device Speed
The rated EMIF speed of these devices only applies to the SDRAM interface when in a system that meets the
following requirements:
•
•
•
•
•
1 chip-enable (CE) space (maximum of 2 chips) of SDRAM connected to EMIF
up to 1 CE space of buffers connected to EMIF
EMIF trace lengths between 1 and 3 inches
166-MHz SDRAM for 133-MHz operation
143-MHz SDRAM for 100-MHz operation
Other configurations may be possible, but timing analysis must be done to verify all AC timings are met.
Verification of AC timings is mandatory when using configurations other than those specified above. TI
recommends utilizing I/O buffer information specification (IBIS) to analyze all AC timings.
To properly use IBIS models to attain accurate timing analysis for a given system, see the Using IBIS Models
for Timing Analysis application report (literature number SPRA839).
To maintain signal integrity, serial termination resistors should be inserted into all EMIF output signal lines (see
the Terminal Functions table for the EMIF output signals).
For more detailed information on the DM641/DM640 EMIF peripheral, see the TMS320C6000 DSP External
Memory Interface (EMIF) Reference Guide (literature number SPRU266).
4.8.2
EMIF Peripheral Register Description(s)
Table 4−21. EMIFA Registers
HEX ADDRESS RANGE
ACRONYM
GBLCTL
CECTL1
CECTL0
−
REGISTER NAME
EMIFA global control
COMMENTS
0180 0000
0180 0004
EMIFA CE1 space control
EMIFA CE0 space control
Reserved
0180 0008
0180 000C
0180 0010
CECTL2
CECTL3
SDCTL
SDTIM
SDEXT
−
EMIFA CE2 space control
EMIFA CE3 space control
EMIFA SDRAM control
0180 0014
0180 0018
0180 001C
EMIFA SDRAM refresh control
EMIFA SDRAM extension
Reserved
0180 0020
0180 0024 − 0180 003C
0180 0040
PDTCTL
CESEC1
CESEC0
−
Peripheral device transfer (PDT) control
EMIFA CE1 space secondary control
EMIFA CE0 space secondary control
Reserved
0180 0044
0180 0048
0180 004C
0180 0050
CESEC2
CESEC3
–
EMIFA CE2 space secondary control
EMIFA CE3 space secondary control
Reserved
0180 0054
0180 0058 − 0183 FFFF
105
June 2003 − Revised October 2005
SPRS222E
External Memory Interface (EMIIF)
4.8.3
EMIF Electrical Data/Timing
4.8.3.1 Asynchronous Memory Timing
†‡
Table 4−22. Timing Requirements for Asynchronous Memory Cycles for EMIFA Module
(see Figure 4−19 and Figure 4−20)
−400
−500
−600
NO.
UNIT
MIN MAX
3
4
6
7
t
t
t
t
Setup time, AEDx valid before AARE high
Hold time, AEDx valid after AARE high
6.5
1
ns
ns
ns
ns
su(EDV-AREH)
h(AREH-EDV)
Setup time, AARDY valid before AECLKOUTx high
Hold time, AARDY valid after AECLKOUTx high
3
su(ARDY-EKO1H)
h(EKO1H-ARDY)
2.5
†
‡
To ensure data setup time, simply program the strobe width wide enough. AARDY is internally synchronized. The AARDY signal is only
recognized two cycles before the end of the programmed strobe time and while AARDY is low, the strobe time is extended cycle-by-cycle. When
AARDY is recognized low, the end of the strobe time is two cycles after AARDY is recognized high. To use AARDY as an asynchronous input,
the pulse width of the AARDY signal should be wide enough (e.g., pulse width = 2E) to ensure setup and hold time is met.
RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold. These parameters are
programmed via the EMIF CE space control registers.
Table 4−23. Switching Characteristics Over Recommended Operating Conditions for Asynchronous
द
Memory Cycles for EMIFA Module
(see Figure 4−19 and Figure 4−20)
−400
−500
−600
NO.
PARAMETER
UNIT
MIN
RS * E − 1.8
RH * E − 1.9
1
MAX
7
1
2
t
t
t
t
t
t
Output setup time, select signals valid to AARE low
Output hold time, AARE high to select signals invalid
Delay time, AECLKOUTx high to AARE valid
ns
ns
ns
ns
ns
ns
osu(SELV-AREL)
oh(AREH-SELIV)
d(EKO1H-AREV)
osu(SELV-AWEL)
oh(AWEH-SELIV)
d(EKO1H-AWEV)
5
8
Output setup time, select signals valid to AAWE low
Output hold time, AAWE high to select signals invalid
Delay time, AECLKOUTx high to AAWE valid
WS * E − 2.0
WH * E − 2.5
1.3
9
10
7.1
‡
RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold. These parameters are
programmed via the EMIF CE space control registers.
E = AECLKOUT1 period in ns for EMIFA
§
¶
Select signals for EMIFA include: ACEx, ABE[3:0], AEA[22:3], AAOE; and for EMIFA writes, include AED[31:0].
106
SPRS222E
June 2003 − Revised October 2005
External Memory Interface (EMIIF)
Setup = 2
Strobe = 3
Not Ready
Hold = 2
AECLKOUTx
ACEx
2
2
1
1
1
ABE[3:0]
BE
2
AEA[22:3]
Address
3
4
AED[31:0]
2
1
5
Read Data
†
AAOE/ASDRAS/ASOE
5
†
AARE/ASDCAS/ASADS/ASRE
†
AAWE/ASDWE/ASWE
7
7
6
6
AARDY
†
AAOE/ASDRAS/ASOE, AARE/ASDCAS/ASADS/ASRE, and AAWE/ASDWE/ASWE operate as AAOE (identified under select signals), AARE,
and AAWE, respectively, during asynchronous memory accesses.
Figure 4−19. Asynchronous Memory Read Timing for EMIFA
107
June 2003 − Revised October 2005
SPRS222E
External Memory Interface (EMIIF)
Setup = 2
Hold = 2
Strobe = 3
Not Ready
AECLKOUTx
ACEx
9
9
8
8
8
8
ABE[3:0]
BE
9
9
AEA[22:3]
AED[31:0]
Address
Write Data
†
AAOE/ASDRAS/ASOE
†
AARE/ASDCAS/ASADS/ASRE
10
10
†
AAWE/ASDWE/ASWE
7
7
6
6
AARDY
†
AAOE/ASDRAS/ASOE, AARE/ASDCAS/ASADS/ASRE, and AAWE/ASDWE/ASWE operate as AAOE (identified under select signals), AARE,
and AAWE, respectively, during asynchronous memory accesses.
Figure 4−20. Asynchronous Memory Write Timing for EMIFA
108
SPRS222E
June 2003 − Revised October 2005
External Memory Interface (EMIIF)
4.8.3.2 Programmable Synchronous Interface Timing
Table 4−24. Timing Requirements for Programmable Synchronous Interface Cycles for EMIFA Module
(see Figure 4−21)
−400
−600
−500
NO.
UNIT
MIN
3.1
MAX
MIN
2
MAX
6
7
t
t
Setup time, read AEDx valid before AECLKOUTx high
Hold time, read AEDx valid after AECLKOUTx high
ns
ns
su(EDV-EKOxH)
1.8
1.5
h(EKOxH-EDV)
Table 4−25. Switching Characteristics Over Recommended Operating Conditions for Programmable
†
Synchronous Interface Cycles for EMIFA Module (see Figure 4−21−Figure 4−23)
−400
−600
−500
NO.
PARAMETER
UNIT
MIN
MAX
6.4
MIN
MAX
4.9
1
2
t
t
t
t
t
t
t
t
t
t
Delay time, AECLKOUTx high to ACEx valid
Delay time, AECLKOUTx high to ABEx valid
Delay time, AECLKOUTx high to ABEx invalid
Delay time, AECLKOUTx high to AEAx valid
Delay time, AECLKOUTx high to AEAx invalid
Delay time, AECLKOUTx high to ASADS/ASRE valid
Delay time, AECLKOUTx high to ASOE valid
Delay time, AECLKOUTx high to AEDx valid
Delay time, AECLKOUTx high to AEDx invalid
Delay time, AECLKOUTx high to ASWE valid
1.1
1.1
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
d(EKOxH-CEV)
d(EKOxH-BEV)
d(EKOxH-BEIV)
d(EKOxH-EAV)
d(EKOxH-EAIV)
d(EKOxH-ADSV)
d(EKOxH-OEV)
d(EKOxH-EDV)
d(EKOxH-EDIV)
d(EKOxH-WEV)
6.4
4.9
3
1.1
1.1
4
6.4
4.9
5
1.1
1.1
1.1
1.1
1.1
1.1
8
6.4
6.4
6.4
4.9
4.9
4.9
9
10
11
12
1.1
1.1
1.1
1.1
6.4
4.9
†
The following parameters are programmable via the EMIF CE Space Secondary Control register (CExSEC):
−
−
−
Read latency (SYNCRL): 0-, 1-, 2-, or 3-cycle read latency
Write latency (SYNCWL): 0-, 1-, 2-, or 3-cycle write latency
ACEx assertion length (CEEXT): For standard SBSRAM or ZBT SRAM interface, ACEx goes inactive after the final command has been issued
(CEEXT = 0). For synchronous FIFO interface with glue, ACEx is active when ASOE is active (CEEXT = 1).
Function of ASADS/ASRE (RENEN): For standard SBSRAM or ZBT SRAM interface, ASADS/ASRE acts as ASADS with deselect cycles
(RENEN = 0). For FIFO interface, ASADS/ASRE acts as ASRE with NO deselect cycles (RENEN = 1).
−
−
Synchronization clock (SNCCLK): Synchronized to AECLKOUT1 or AECLKOUT2
109
June 2003 − Revised October 2005
SPRS222E
External Memory Interface (EMIIF)
READ latency = 2
AECLKOUTx
1
2
1
3
5
ACEx
ABE[3:0]
BE1
BE2
BE3
BE4
4
AEA[22:3]
AED[31:0]
EA1
EA2
EA3
EA4
7
6
Q1
Q2
Q3
Q4
8
9
8
AARE/ASDCAS/ASADS/
§
ASRE
9
§
AAOE/ASDRAS/ASOE
§
AAWE/ASDWE/ASWE
†
The read latency and the length of ACEx assertion are programmable via the SYNCRL and CEEXT fields, respectively, in the EMIFA CE Space
Secondary Control register (CExSEC). In this figure, SYNCRL = 2 and CEEXT = 0.
The following parameters are programmable via the EMIF CE Space Secondary Control register (CExSEC):
‡
−
−
−
Read latency (SYNCRL): 0-, 1-, 2-, or 3-cycle read latency
Write latency (SYNCWL): 0-, 1-, 2-, or 3-cycle write latency
ACEx assertion length (CEEXT): For standard SBSRAM or ZBT SRAM interface, ACEx goes inactive after the final command has been issued
(CEEXT = 0). For synchronous FIFO interface with glue, ACEx is active when ASOE is active (CEEXT = 1).
Function of ASADS/ASRE (RENEN): For standard SBSRAM or ZBT SRAM interface, ASADS/ASRE acts as ASADS with deselect cycles
(RENEN = 0). For FIFO interface, ASADS/ASRE acts as ASRE with NO deselect cycles (RENEN = 1).
Synchronization clock (SNCCLK): Synchronized to AECLKOUT1 or AECLKOUT2
−
−
§
AARE/ASDCAS/ASADS/ASRE, AAOE/ASDRAS/ASOE, and AAWE/ASDWE/ASWE operate as ASADS/ASRE, ASOE, and ASWE,
respectively, during programmable synchronous interface accesses.
Figure 4−21. Programmable Synchronous Interface Read Timing for EMIFA
†‡
(With Read Latency = 2)
110
SPRS222E
June 2003 − Revised October 2005
External Memory Interface (EMIIF)
AECLKOUTx
ACEx
1
2
1
3
ABE[3:0]
BE1
BE2
EA2
Q2
BE3
EA3
Q3
BE4
5
4
AEA[22:3]
AED[31:0]
EA1
10
Q1
EA4
10
11
Q4
8
8
§
AARE/ASDCAS/ASADS/ASRE
§
AAOE/ASDRAS/ASOE
12
12
§
AAWE/ASDWE/ASWE
†
‡
The write latency and the length of ACEx assertion are programmable via the SYNCWL and CEEXT fields, respectively, in the EMIFA CE Space
Secondary Control register (CExSEC). In this figure, SYNCWL = 0 and CEEXT = 0.
The following parameters are programmable via the EMIF CE Space Secondary Control register (CExSEC):
−
−
−
Read latency (SYNCRL): 0-, 1-, 2-, or 3-cycle read latency
Write latency (SYNCWL): 0-, 1-, 2-, or 3-cycle write latency
ACEx assertion length (CEEXT): For standard SBSRAM or ZBT SRAM interface, ACEx goes inactive after the final command has been issued
(CEEXT = 0). For synchronous FIFO interface with glue, ACEx is active when ASOE is active (CEEXT = 1).
Function of ASADS/ASRE (RENEN): For standard SBSRAM or ZBT SRAM interface, ASADS/ASRE acts as ASADS with deselect cycles
(RENEN = 0). For FIFO interface, ASADS/ASRE acts as ASRE with NO deselect cycles (RENEN = 1).
Synchronization clock (SNCCLK): Synchronized to AECLKOUT1 or AECLKOUT2
−
−
§
AARE/ASDCAS/ASADS/ASRE, AAOE/ASDRAS/ASOE, and AAWE/ASDWE/ASWE operate as ASADS/ASRE, ASOE, and ASWE,
respectively, during programmable synchronous interface accesses.
Figure 4−22. Programmable Synchronous Interface Write Timing for EMIFA
†‡§
(With Write Latency = 0)
111
June 2003 − Revised October 2005
SPRS222E
External Memory Interface (EMIIF)
Write
Latency =
‡
1
AECLKOUTx
1
1
3
ACEx
2
ABE[3:0]
BE1
BE2
BE3
EA3
Q2
BE4
EA4
Q3
5
4
AEA[22:3]
EA1
10
EA2
10
11
8
AED[31:0]
Q1
Q4
8
AARE/ASDCAS/ASADS/
§
ASRE
§
AAOE/ASDRAS/ASOE
12
12
§
AAWE/ASDWE/ASWE
†
The write latency and the length of ACEx assertion are programmable via the SYNCWL and CEEXT fields, respectively, in the EMIFA CE Space
Secondary Control register (CExSEC). In this figure, SYNCWL = 1 and CEEXT = 0.
The following parameters are programmable via the EMIF CE Space Secondary Control register (CExSEC):
‡
−
−
−
Read latency (SYNCRL): 0-, 1-, 2-, or 3-cycle read latency
Write latency (SYNCWL): 0-, 1-, 2-, or 3-cycle write latency
ACEx assertion length (CEEXT): For standard SBSRAM or ZBT SRAM interface, ACEx goes inactive after the final command has been issued
(CEEXT = 0). For synchronous FIFO interface with glue, ACEx is active when ASOE is active (CEEXT = 1).
Function of ASADS/ASRE (RENEN): For standard SBSRAM or ZBT SRAM interface, ASADS/ASRE acts as ASADS with deselect cycles
(RENEN = 0). For FIFO interface, ASADS/ASRE acts as ASRE with NO deselect cycles (RENEN = 1).
Synchronization clock (SNCCLK): Synchronized to ECLKOUT1 or ECLKOUT2
−
−
§
AARE/ASDCAS/ASADS/ASRE, AAOE/ASDRAS/ASOE, and AAWE/ASDWE/ASWE operate as ASADS/ASRE, ASOE, and ASWE,
respectively, during programmable synchronous interface accesses.
Figure 4−23. Programmable Synchronous Interface Write Timing for EMIFA
†‡
(With Write Latency = 1)
112
SPRS222E
June 2003 − Revised October 2005
External Memory Interface (EMIIF)
4.8.3.3 Synchronous DRAM Timing
Table 4−26. Timing Requirements for Synchronous DRAM Cycles for EMIFA Module (see Figure 4−24)
−400
−600
−500
NO.
UNIT
MIN MAX
MIN MAX
6
7
t
t
Setup time, read AEDx valid before AECLKOUTx high
Hold time, read AEDx valid after AECLKOUTx high
2.1
2.8
0.6
2.1
ns
ns
su(EDV-EKO1H)
h(EKO1H-EDV)
Table 4−27. Switching Characteristics Over Recommended Operating Conditions for Synchronous DRAM
Cycles for EMIFA Module (see Figure 4−24−Figure 4−31)
−400
−600
−500
NO.
PARAMETER
UNIT
MIN
MAX
6.4
MIN
MAX
4.9
1
2
t
t
t
t
t
t
t
t
t
t
t
t
Delay time, AECLKOUTx high to ACEx valid
Delay time, AECLKOUTx high to ABEx valid
Delay time, AECLKOUTx high to ABEx invalid
Delay time, AECLKOUTx high to AEAx valid
Delay time, AECLKOUTx high to AEAx invalid
Delay time, AECLKOUTx high to ASDCAS valid
Delay time, AECLKOUTx high to AEDx valid
Delay time, AECLKOUTx high to AEDx invalid
Delay time, AECLKOUTx high to ASDWE valid
Delay time, AECLKOUTx high to ASDRAS valid
Delay time, AECLKOUTx high to ASDCKE valid
Delay time, AECLKOUTx high to APDT valid
1.3
1.3
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
d(EKO1H-CEV)
d(EKO1H-BEV)
d(EKO1H-BEIV)
d(EKO1H-EAV)
d(EKO1H-EAIV)
d(EKO1H-CASV)
d(EKO1H-EDV)
d(EKO1H-EDIV)
d(EKO1H-WEV)
d(EKO1H-RAS)
d(EKO1H-ACKEV)
6.4
4.9
3
1.3
1.3
4
6.4
4.9
5
1.3
1.3
1.3
1.3
8
6.4
6.4
4.9
4.9
9
10
11
12
13
14
1.3
1.3
1.3
1.3
1.3
1.3
1.3
1.3
1.3
1.3
6.4
6.4
6.4
6.4
4.9
4.9
4.9
4.9
d(EKO1H-PDTV)
113
June 2003 − Revised October 2005
SPRS222E
External Memory Interface (EMIIF)
READ
AECLKOUTx
ACEx
1
4
1
2
3
ABE[3:0]
BE1
BE2
BE3
BE4
5
5
5
Bank
AEA[22:14]
AEA[12:3]
4
Column
4
AEA13
6
7
D2
AED[31:0]
D1
D3
D4
†
AAOE/ASDRAS/ASOE
8
8
AARE/ASDCAS/ASADS/
†
ASRE
†
AAWE/ASDWE/ASWE
14
14
‡
APDT
†
AARE/ASDCAS/ASADS/ASRE, AAWE/ASDWE/ASWE, and AAOE/ASDRAS/ASOE operate as ASDCAS, ASDWE, and ASDRAS,
respectively, during SDRAM accesses.
APDT signal is only asserted when the EDMA is in PDT mode (set the PDTS bit to 1 in the EDMA options parameter RAM). For APDT read, data
is not latched into EMIF. The PDTRL field in the PDT control register (PDTCTL) configures the latency of the APDT signal with respect to the
data phase of a read transaction. The latency of the APDT signal for a read can be programmed to 0, 1, 2, or 3 by setting PDTRL to 00, 01, 10,
or 11, respectively. PDTRL equals 00 (zero latency) in Figure 4−24.
‡
Figure 4−24. SDRAM Read Command (CAS Latency 3) for EMIFA
114
SPRS222E
June 2003 − Revised October 2005
External Memory Interface (EMIIF)
WRITE
AECLKOUTx
ACEx
1
2
4
4
4
9
2
4
5
5
5
9
3
ABE[3:0]
BE1
BE2
BE3
BE4
Bank
AEA[22:14]
Column
AEA[12:3]
AEA13
10
AED[31:0]
D1
D2
D3
D4
†
AAOE/ASDRAS/ASOE
8
8
AARE/ASDCAS/ASADS/
†
ASRE
11
14
11
†
AAWE/ASDWE/ASWE
14
‡
APDT
†
‡
AARE/ASDCAS/ASADS/ASRE, AAWE/ASDWE/ASWE, and AAOE/ASDRAS/ASOE operate as ASDCAS, ASDWE, and ASDRAS,
respectively, during SDRAM accesses.
APDT signal is only asserted when the EDMA is in PDT mode (set the PDTD bit to 1 in the EDMA options parameter RAM). For APDT write,
data is not driven (in High-Z). The PDTWL field in the PDT control register (PDTCTL) configures the latency of the APDT signal with respect to
the data phase of a write transaction. The latency of the APDT signal for a write transaction can be programmed to 0, 1, 2, or 3 by setting PDTWL
to 00, 01, 10, or 11, respectively. PDTWL equals 00 (zero latency) in Figure 4−25.
Figure 4−25. SDRAM Write Command for EMIFA
115
June 2003 − Revised October 2005
SPRS222E
External Memory Interface (EMIIF)
ACTV
AECLKOUTx
1
4
1
ACEx
ABE[3:0]
5
5
5
Bank Activate
AEA[22:14]
AEA[12:3]
4
Row Address
4
Row Address
AEA13
AED[31:0]
12
12
†
AAOE/ASDRAS/ASOE
AARE/ASDCAS/ASADS/
†
ASRE
†
AAWE/ASDWE/ASWE
†
AARE/ASDCAS/ASADS/ASRE, AAWE/ASDWE/ASWE, and AAOE/ASDRAS/ASOE operate as ASDCAS, ASDWE, and ASDRAS,
respectively, during SDRAM accesses.
Figure 4−26. SDRAM ACTV Command for EMIFA
DCAB
AECLKOUTx
1
1
ACEx
ABE[3:0]
AEA[22:14, 12:3]
4
12
11
5
12
11
AEA13
AED[31:0]
†
AAOE/ASDRAS/ASOE
AARE/ASDCAS/ASADS/
†
ASRE
†
AAWE/ASDWE/ASWE
†
AARE/ASDCAS/ASADS/ASRE, AAWE/ASDWE/ASWE, and AAOE/ASDRAS/ASOE operate as ASDCAS, ASDWE, and ASDRAS,
respectively, during SDRAM accesses.
Figure 4−27. SDRAM DCAB Command for EMIFA
116
SPRS222E
June 2003 − Revised October 2005
External Memory Interface (EMIIF)
DEAC
AECLKOUTx
1
1
ACEx
ABE[3:0]
4
5
AEA[22:14]
AEA[12:3]
Bank
4
5
AEA13
AED[31:0]
12
11
12
11
†
AAOE/ASDRAS/ASOE
AARE/ASDCAS/ASADS/
†
ASRE
†
AAWE/ASDWE/ASWE
†
AARE/ASDCAS/ASADS/ASRE, AAWE/ASDWE/ASWE, and AAOE/ASDRAS/ASOE operate as ASDCAS, ASDWE, and ASDRAS,
respectively, during SDRAM accesses.
Figure 4−28. SDRAM DEAC Command for EMIFA
REFR
AECLKOUTx
1
1
ACEx
ABE[3:0]
AEA[22:14, 12:3]
AEA13
AED[31:0]
12
8
12
8
†
AAOE/ASDRAS/ASOE
AARE/ASDCAS/ASADS/
†
ASRE
†
AAWE/ASDWE/ASWE
†
AARE/ASDCAS/ASADS/ASRE, AAWE/ASDWE/ASWE, and AAOE/ASDRAS/ASOE operate as ASDCAS, ASDWE, and ASDRAS,
respectively, during SDRAM accesses.
Figure 4−29. SDRAM REFR Command for EMIFA
117
June 2003 − Revised October 2005
SPRS222E
External Memory Interface (EMIIF)
MRS
AECLKOUTx
1
4
1
5
ACEx
ABE[3:0]
AEA[22:3]
AED[31:0]
MRS value
12
8
12
8
AAOE/ASDRAS/
†
ASOE
AARE/ASDCAS/ASADS/
†
ASRE
11
11
†
AAWE/ASDWE/ASWE
†
AARE/ASDCAS/ASADS/ASRE, AAWE/ASDWE/ASWE, and AAOE/ASDRAS/ASOE operate as ASDCAS, ASDWE, and ASDRAS,
respectively, during SDRAM accesses.
Figure 4−30. SDRAM MRS Command for EMIFA
≥ TRAS cycles
End Self-Refresh
Self Refresh
AECLKOUTx
ACEx
ABE[3:0]
AEA[22:14, 12:3]
AEA13
AED[31:0]
†
AAOE/ASDRAS/ASOE
AARE/ASDCAS/ASADS/
†
ASRE
†
AAWE/ASDWE/ASWE
13
13
ASDCKE
†
AARE/ASDCAS/ASADS/ASRE, AAWE/ASDWE/ASWE, and AAOE/ASDRAS/ASOE operate as ASDCAS, ASDWE, and ASDRAS,
respectively, during SDRAM accesses.
Figure 4−31. SDRAM Self-Refresh Timing for EMIFA
118
SPRS222E
June 2003 − Revised October 2005
External Memory Interface (EMIIF)
4.8.3.4 HOLD/HOLDA Timing
†
Table 4−28. Timing Requirements for the HOLD/HOLDA Cycles for EMIFA Module (see Figure 4−32)
−400
−500
−600
MIN MAX
E
NO.
UNIT
3
t
Hold time, HOLD low after HOLDA low
ns
h(HOLDAL-HOLDL)
†
E = the EMIF input clock (ECLKIN, CPU/4 clock, or CPU/6 clock) period in ns for EMIFA.
Table 4−29. Switching Characteristics Over Recommended Operating Conditions for the HOLD/HOLDA
†‡§
Cycles for EMIFA Module
(see Figure 4−32)
−400
−500
−600
NO.
PARAMETER
UNIT
MIN
MAX
¶
1
2
4
5
6
7
t
t
t
t
t
t
Delay time, HOLD low to EMIFA Bus high impedance
Delay time, EMIF Bus high impedance to HOLDA low
Delay time, HOLD high to EMIF Bus low impedance
Delay time, EMIFA Bus low impedance to HOLDA high
Delay time, HOLD low to AECLKOUTx high impedance
Delay time, HOLD high to AECLKOUTx low impedance
2E
0
ns
ns
ns
ns
ns
ns
d(HOLDL-EMHZ)
d(EMHZ-HOLDAL)
d(HOLDH-EMLZ)
d(EMLZ-HOLDAH)
d(HOLDL-EKOHZ)
d(HOLDH-EKOLZ)
2E
7E
2E
0
2E
¶
2E
2E
7E
†
‡
E = the EMIF input clock (ECLKIN, CPU/4 clock, or CPU/6 clock) period in ns for EMIFA.
EMIFA Bus consists of: ACE[3:0], ABE[3:0], AED[31:0], AEA[22:3], AARE/ASDCAS/ASADS/ASRE, AAOE/ASDRAS/ASOE, and
AAWE/ASDWE/ASWE , ASDCKE, ASOE3, and APDT.
The EKxHZ bits in the EMIF Global Control register (GBLCTL) determine the state of the ECLKOUTx signals during HOLDA. If EKxHZ = 0,
ECLKOUTx continues clocking during Hold mode. If EKxHZ = 1, ECLKOUTx goes to high impedance during Hold mode, as shown in Figure 4−32.
All pending EMIF transactions are allowed to complete before HOLDA is asserted. If no bus transactions are occurring, then the minimum delay
time can be achieved. Also, bus hold can be indefinitely delayed by setting NOHOLD = 1.
§
¶
External Requestor
DSP Owns Bus
DSP Owns Bus
Owns Bus
3
HOLD
2
5
HOLDA
1
4
7
†
EMIF Bus
DM641/DM640
DM641/DM640
‡
AECLKOUTx
(EKxHZ = 0)
6
‡
AECLKOUTx
(EKxHZ = 1)
†
‡
EMIFA Bus consists of: ACE[3:0], ABE[3:0], AED[31:0], AEA[22:3], AARE/ASDCAS/ASADS/ASRE, AAOE/ASDRAS/ASOE, and
AAWE/ASDWE/ASWE, ASDCKE, ASOE3, and APDT.
The EKxHZ bits in the EMIF Global Control register (GBLCTL) determine the state of the ECLKOUTx signals during HOLDA. If EKxHZ = 0,
ECLKOUTx continues clocking during Hold mode. If EKxHZ = 1, ECLKOUTx goes to high impedance during Hold mode, as shown in Figure 4−32.
Figure 4−32. HOLD/HOLDA Timing for EMIFA
119
June 2003 − Revised October 2005
SPRS222E
External Memory Interface (EMIIF)
4.8.3.5 BUSREQ Timing
Table 4−30. Switching Characteristics Over Recommended Operating Conditions for the BUSREQ Cycles
for EMIFA Module (see Figure 4−33)
−400
−600
−500
NO.
PARAMETER
UNIT
MIN
MAX
MIN
MAX
1
t
Delay time, AECLKOUTx high to ABUSREQ valid
0.6
7.1
1
5.5
ns
d(AEKO1H-ABUSRV)
AECLKOUTx
1
1
ABUSREQ
Figure 4−33. BUSREQ Timing for EMIFA
120
SPRS222E
June 2003 − Revised October 2005
Multichannel Audio Serial Port (McASP0) Peripheral
4.9
Multichannel Audio Serial Port (McASP0) Peripheral
The McASP functions as a general-purpose audio serial port optimized for the needs of multichannel audio
applications. The McASP is useful for time-division multiplexed (TDM) stream, Inter-Integrated Sound (I2S)
protocols, and intercomponent digital audio interface transmission (DIT).
4.9.1
McASP0 Device-Specific Information
The TMS320DM641/DM640 device includes one multichannel audio serial port (McASP) interface peripheral
(McASP0). The McASP is a serial port optimized for the needs of multichannel audio applications.
The McASP consists of a transmit and receive section. These sections can operate completely independently
with different data formats, separate master clocks, bit clocks, and frame syncs or alternatively, the transmit
and receive sections may be synchronized. The McASP module also includes a pool of 16 shift registers that
may be configured to operate as either transmit data, receive data, or general-purpose I/O (GPIO).
The transmit section of the McASP can transmit data in either a time-division-multiplexed (TDM) synchronous
serial format or in a digital audio interface (DIT) format where the bit stream is encoded for S/PDIF, AES-3,
IEC-60958, CP-430 transmission. The receive section of the McASP supports the TDM synchronous serial
format.
The McASP can support one transmit data format (either a TDM format or DIT format) and one receive format
at a time. All transmit shift registers use the same format and all receive shift registers use the same format.
However, the transmit and receive formats need not be the same.
Both the transmit and receive sections of the McASP also support burst mode which is useful for non-audio
data (for example, passing control information between two DSPs).
The McASP peripheral has additional capability for flexible clock generation, and error detection/handling, as
well as error management.
For more detailed information on and the functionality of the McASP peripheral, see the TMS320C6000 DSP
Multichannel Audio Serial Port (McASP) Reference Guide (literature number SPRU041).
4.9.1.1 McASP Block Diagram
Figure 4−34 illustrates the major blocks along with external signals of the TMS320DM641/DM640 McASP0
peripheral; and shows the 8 serial data [AXR] pins. The McASP also includes full general-purpose I/O (GPIO)
control, so any pins not needed for serial transfers can be used for general-purpose I/O.
121
June 2003 − Revised October 2005
SPRS222E
Multichannel Audio Serial Port (McASP0) Peripheral
McASP0
Transmit
Frame Sync
Generator
DIT
RAM
AFSX0
Transmit
Transmit
Clock
Generator
AHCLKX0
ACLKX0
Clock Check
(High-
Frequency)
AMUTE0
AMUTEIN0
Error
Detect
Receive
Clock Check
(High-
Receive
Clock
Generator
AHCLKR0
ACLKR0
Frequency)
Transmit
Data
Formatter
Receive
Frame Sync
Generator
AFSR0
Serializer 0
AXR0[0]
AXR0[1]
AXR0[2]
AXR0[3]
Serializer 1
Serializer 2
Serializer 3
Serializer 4
Serializer 5
Serializer 6
Serializer 7
Receive
Data
Formatter
GPIO
Control
Figure 4−34. McASP0 Configuration
122
SPRS222E
June 2003 − Revised October 2005
Multichannel Audio Serial Port (McASP0) Peripheral
4.9.2
McASP0 Peripheral Register Description(s)
Table 4−31. McASP0 Control Registers
HEX ADDRESS RANGE
ACRONYM
PID
REGISTER NAME
Peripheral Identification register [Register value: 0x0010 0101]
Power down and emulation management register
Reserved
01B4 C000
01B4 C004
01B4 C008
01B4 C00C
01B4 C010
01B4 C014
01B4 C018
PWRDEMU
−
−
Reserved
PFUNC
PDIR
Pin function register
Pin direction register
PDOUT
Pin data out register
Pin data in / data set register
Read returns: PDIN
Writes affect: PDSET
01B4 C01C
PDIN/PDSET
01B4 C020
PDCLR
−
Pin data clear register
Reserved
01B4 C024 − 01B4 C040
01B4 C044
GBLCTL
AMUTE
DLBCTL
DITCTL
−
Global control register
Mute control register
Digital Loop-back control register
DIT mode control register
Reserved
01B4 C048
01B4 C04C
01B4 C050
01B4 C054 − 01B4 C05C
Alias of GBLCTL containing only Receiver Reset bits, allows transmit to be reset
independently from receive.
01B4 C060
RGBLCTL
01B4 C064
01B4 C068
RMASK
RFMT
Receiver format unit bit mask register
Receive bit stream format register
Receive frame sync control register
Receive clock control register
High-frequency receive clock control register
Receive TDM slot 0−31 register
Receiver interrupt control register
Status register − Receiver
01B4 C06C
AFSRCTL
ACLKRCTL
AHCLKRCTL
RTDM
01B4 C070
01B4 C074
01B4 C078
01B4 C07C
RINTCTL
RSTAT
01B4 C080
01B4 C084
RSLOT
Current receive TDM slot register
Receiver clock check control register
Reserved
01B4 C088
RCLKCHK
−
01B4 C08C − 01B4 C09C
Alias of GBLCTL containing only Transmitter Reset bits, allows transmit to be reset
independently from receive.
01B4 C0A0
XGBLCTL
01B4 C0A4
01B4 C0A8
01B4 C0AC
01B4 C0B0
01B4 C0B4
01B4 C0B8
01B4 C0BC
01B4 C0C0
01B4 C0C4
01B4 C0C8
XMASK
XFMT
Transmit format unit bit mask register
Transmit bit stream format register
Transmit frame sync control register
Transmit clock control register
AFSXCTL
ACLKXCTL
AHCLKXCTL
XTDM
High-frequency Transmit clock control register
Transmit TDM slot 0−31 register
Transmit interrupt control register
Status register − Transmitter
XINTCTL
XSTAT
XSLOT
Current transmit TDM slot
XCLKCHK
Transmit clock check control register
123
June 2003 − Revised October 2005
SPRS222E
Multichannel Audio Serial Port (McASP0) Peripheral
Table 4−31. McASP0 Control Registers (Continued)
HEX ADDRESS RANGE
01B4 C0CC
ACRONYM
XEVTCTL
−
REGISTER NAME
Transmitter DMA control register
Reserved
01B4 C0D0 − 01B4 C0FC
01B4 C100
DITCSRA0
DITCSRA1
DITCSRA2
DITCSRA3
DITCSRA4
DITCSRA5
DITCSRB0
DITCSRB1
DITCSRB2
DITCSRB3
DITCSRB4
DITCSRB5
DITUDRA0
DITUDRA1
DITUDRA2
DITUDRA3
DITUDRA4
DITUDRA5
DITUDRB0
DITUDRB1
DITUDRB2
DITUDRB3
DITUDRB4
DITUDRB5
−
Left (even TDM slot) channel status register file
Left (even TDM slot) channel status register file
Left (even TDM slot) channel status register file
Left (even TDM slot) channel status register file
Left (even TDM slot) channel status register file
Left (even TDM slot) channel status register file
Right (odd TDM slot) channel status register file
Right (odd TDM slot) channel status register file
Right (odd TDM slot) channel status register file
Right (odd TDM slot) channel status register file
Right (odd TDM slot) channel status register file
Right (odd TDM slot) channel status register file
Left (even TDM slot) user data register file
Left (even TDM slot) user data register file
Left (even TDM slot) user data register file
Left (even TDM slot) user data register file
Left (even TDM slot) user data register file
Left (even TDM slot) user data register file
Right (odd TDM slot) user data register file
Right (odd TDM slot) user data register file
Right (odd TDM slot) user data register file
Right (odd TDM slot) user data register file
Right (odd TDM slot) user data register file
Right (odd TDM slot) user data register file
Reserved
01B4 C104
01B4 C108
01B4 C10C
01B4 C110
01B4 C114
01B4 C118
01B4 C11C
01B4 C120
01B4 C124
01B4 C128
01B4 C12C
01B4 C130
01B4 C134
01B4 C138
01B4 C13C
01B4 C140
01B4 C144
01B4 C148
01B4 C14C
01B4 C150
01B4 C154
01B4 C158
01B4 C15C
01B4 C160 − 01B4 C17C
01B4 C180
SRCTL0
SRCTL1
SRCTL2
SRCTL3
−
Serializer 0 control register
01B4 C184
Serializer 1 control register
01B4 C188
Serializer 2 control register
01B4 C18C
Serializer 3 control register
01B4 C190 − 01B4 C1FC
01B4 C200
Reserved
XBUF0
Transmit Buffer for Serializer 0
01B4 C204
XBUF1
Transmit Buffer for Serializer 1
01B4 C208
XBUF2
Transmit Buffer for Serializer 2
01B4 C20C
XBUF3
Transmit Buffer for Serializer 3
01B4 C210 − 01B4 C27C
01B4 C280
−
Reserved
RBUF0
Receive Buffer for Serializer 0
01B4 C284
RBUF1
Receive Buffer for Serializer 1
01B4 C288
RBUF2
Receive Buffer for Serializer 2
01B4 C28C
RBUF3
Receive Buffer for Serializer 3
01B4 C290 − 01B4 FFFF
−
Reserved
124
SPRS222E
June 2003 − Revised October 2005
Multichannel Audio Serial Port (McASP0) Peripheral
Table 4−32. McASP0 Data Registers
HEX ADDRESS RANGE
ACRONYM
REGISTER NAME
COMMENTS
(Used when RSEL or XSEL
bits = 0 [these bits are located
in the RFMT or XFMT
McASPx receive buffers or McASPx transmit buffers via
the Peripheral Data Bus.
3C00 0000 − 3C0F FFFF
RBUF/XBUFx
registers, respectively].)
4.9.3
McASP0 Electrical Data/Timing
4.9.3.1 Multichannel Audio Serial Port (McASP) Timing
Table 4−33. Timing Requirements for McASP (see Figure 4−35 and Figure 4−36)
−400
−500
−600
NO.
UNIT
MIN
20
MAX
1
2
3
4
t
t
t
t
Cycle time, AHCLKR/X
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
c(AHCKRX)
w(AHCKRX)
c(CKRX)
Pulse duration, AHCLKR/X high or low
Cycle time, ACLKR/X
10
33
16.5
5
ACLKR/X ext
ACLKR/X ext
ACLKR/X int
ACLKR/X ext
ACLKR/X int
ACLKR/X ext
ACLKR/X int
ACLKR/X ext
ACLKR/X int
ACLKR/X ext
Pulse duration, ACLKR/X high or low
w(CKRX)
5
6
7
8
t
t
t
t
Setup time, AFSR/X input valid before ACLKR/X latches data
Hold time, AFSR/X input valid after ACLKR/X latches data
Setup time, AXR input valid before ACLKR/X latches data
Hold time, AXR input valid after ACLKR/X latches data
su(FRXC-KRX)
h(CKRX-FRX)
su(AXR-CKRX)
h(CKRX-AXR)
5
5
5
5
5
5
5
125
June 2003 − Revised October 2005
SPRS222E
Multichannel Audio Serial Port (McASP0) Peripheral
Table 4−34. Switching Characteristics Over Recommended Operating Conditions for McASP
(see Figure 4−35 and Figure 4−36)
−400
−500
−600
NO.
PARAMETER
UNIT
MIN
20
MAX
9
t
t
t
t
Cycle time, AHCLKR/X
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
c(AHCKRX)
w(AHCKRX)
c(CKRX)
10
11
12
Pulse duration, AHCLKR/X high or low
Cycle time, ACLKR/X
10
33
16.5
−1
0
ACLKR/X int
ACLKR/X int
ACLKR/X int
ACLKR/X ext
ACLKX int
Pulse duration, ACLKR/X high or low
w(CKRX)
5
13
14
15
t
t
t
Delay time, ACLKR/X transmit edge to AFSX/R output valid
Delay time, ACLKX transmit edge to AXR output valid
d(CKRX-FRX)
10
5
−1
0
d(CKX-AXRV)
ACLKX ext
10
10
10
ACLKR/X int
ACLKR/X ext
0
Disable time, AXR high impedance following last data bit from
ACLKR/X transmit edge
dis(CKRX−AXRHZ)
0
126
SPRS222E
June 2003 − Revised October 2005
Multichannel Audio Serial Port (McASP0) Peripheral
MULTICHANNEL AUDIO SERIAL PORT (McASP) TIMING (CONTINUED)
2
1
2
AHCLKR/X (Falling Edge Polarity)
AHCLKR/X (Rising Edge Polarity)
4
3
4
†
ACLKR/X (CLKRP = CLKXP = 0)
‡
ACLKR/X (CLKRP = CLKXP = 1)
6
5
AFSR/X (Bit Width, 0 Bit Delay)
AFSR/X (Bit Width, 1 Bit Delay)
AFSR/X (Bit Width, 2 Bit Delay)
AFSR/X (Slot Width, 0 Bit Delay)
AFSR/X (Slot Width, 1 Bit Delay)
AFSR/X (Slot Width, 2 Bit Delay)
8
7
AXR[n] (Data In/Receive)
A0 A1
A30 A31 B0 B1
B30 B31 C0 C1 C2 C3
C31
†
‡
For CLKRP = CLKXP = 0, the McASP transmitter is configured for rising edge (to shift data out) and the McASP receiver is configured for falling
edge (to shift data in).
For CLKRP = CLKXP = 1, the McASP transmitter is configured for falling edge (to shift data out) and the McASP receiver is configured for rising
edge (to shift data in).
Figure 4−35. McASP Input Timings
127
June 2003 − Revised October 2005
SPRS222E
Multichannel Audio Serial Port (McASP0) Peripheral
MULTICHANNEL AUDIO SERIAL PORT (McASP) TIMING (CONTINUED)
10
10
9
AHCLKR/X (Falling Edge Polarity)
AHCLKR/X (Rising Edge Polarity)
12
11
12
†
ACLKR/X (CLKRP = CLKXP = 1)
‡
ACLKR/X (CLKRP = CLKXP = 0)
13
13
13
13
AFSR/X (Bit Width, 0 Bit Delay)
AFSR/X (Bit Width, 1 Bit Delay)
AFSR/X (Bit Width, 2 Bit Delay)
AFSR/X (Slot Width, 0 Bit Delay)
AFSR/X (Slot Width, 1 Bit Delay)
AFSR/X (Slot Width, 2 Bit Delay)
AXR[n] (Data Out/Transmit)
13
13
13
14
15
A0 A1
A30 A31 B0 B1
B30 B31 C0 C1 C2 C3
C31
†
‡
For CLKRP = CLKXP = 1, the McASP transmitter is configured for falling edge (to shift data out) and the McASP receiver is configured for rising
edge (to shift data in).
For CLKRP = CLKXP = 0, the McASP transmitter is configured for rising edge (to shift data out) and the McASP receiver is configured for falling
edge (to shift data in).
Figure 4−36. McASP Output Timings
128
SPRS222E
June 2003 − Revised October 2005
Inter-Integrated Circuit (I2C)
4.10 Inter-Integrated Circuit (I2C)
The inter-integrated circuit (I2C) module provides an interface between a TMS320C6000™ DSP and other
2
devices compliant with Philips Semiconductors Inter-IC bus (I C-bus) specification version 2.1 and connected
by way of an I2C-bus. External components attached to this 2-wire serial bus can transmit/receive up to 8-bit
data to/from the DSP through the I2C module.
4.10.1 I2C Device-Specific Information
The I2C module on the TMS320DM641/DM640 may be used by the DSP to control local peripherals ICs
(DACs, ADCs, etc.) while the other may be used to communicate with other controllers in a system or to
implement a user interface.
The I2C port supports:
•
•
•
•
•
•
•
Compatible with Philips I2C Specification Revision 2.1 (January 2000)
Fast Mode up to 400 Kbps (no fail-safe I/O buffers)
Noise Filter to Remove Noise 50 ns or less
Seven- and Ten-Bit Device Addressing Modes
Master (Transmit/Receive) and Slave (Transmit/Receive) Functionality
Events: DMA, Interrupt, or Polling
Slew-Rate Limited Open-Drain Output Buffers
Figure 4−37 is a block diagram of the I2C0 module.
I2C0 Module
Clock
Prescale
Peripheral Clock
(CPU/4)
I2CPSCx
Bit Clock
Control
Generator
SCL
Noise
Own
Address
I2C Clock
Filter
I2CCLKHx
I2CCLKLx
I2COARx
I2CSARx
I2CMDRx
I2CCNTx
Slave
Address
Mode
Transmit
I2CXSRx
Data
Count
Transmit
Shift
Transmit
Buffer
I2CDXRx
SDA
Interrupt/DMA
I2CIERx
Noise
Filter
I2C Data
Interrupt
Enable
Receive
Receive
Buffer
I2CDRRx
Interrupt
Status
I2CSTRx
Interrupt
Source
Receive
Shift
I2CRSRx
I2CISRCx
NOTE A: Shading denotes control/status registers.
Figure 4−37. I2C0 Module Block Diagram
129
June 2003 − Revised October 2005
SPRS222E
Inter-Integrated Circuit (I2C)
For more detailed information on the I2C peripheral, see the TMS320C6000 DSP Inter-Integrated Circuit (I2C)
Module Reference Guide (literature number SPRU175).
4.10.2 I2C Peripheral Register Description(s)
Table 4−35. I2C0 Registers
HEX ADDRESS RANGE
01B4 0000
ACRONYM
I2COAR0
I2CIER0
I2CSTR0
I2CCLKL0
I2CCLKH0
I2CCNT0
I2CDRR0
I2CSAR0
I2CDXR0
I2CMDR0
I2CISRC0
−
REGISTER NAME
I2C0 own address register
01B4 0004
I2C0 interrupt enable register
I2C0 interrupt status register
I2C0 clock low-time divider register
I2C0 clock high-time divider register
I2C0 data count register
01B4 0008
01B4 000C
01B4 0010
01B4 0014
01B4 0018
I2C0 data receive register
01B4 001C
I2C0 slave address register
I2C0 data transmit register
01B4 0020
01B4 0024
I2C0 mode register
01B4 0028
I2C0 interrupt source register
Reserved
01B4 002C
01B4 0030
I2CPSC0
I2CPID10
I2CPID20
−
I2C0 prescaler register
01B4 0034
I2C0 Peripheral Identification register 1 [Value: 0x0000 0101]
I2C0 Peripheral Identification register 2 [Value: 0x0000 0005]
Reserved
01B4 0038
01B4 003C − 01B4 3FFF
130
SPRS222E
June 2003 − Revised October 2005
Inter-Integrated Circuit (I2C)
4.10.3 I2C Electrical Data/Timing
4.10.3.1 Inter-Integrated Circuits (I2C) Timing
†
Table 4−36. Timing Requirements for I2C Timings (see Figure 4−38)
−400
−500
−600
NO.
UNIT
STANDARD
MODE
FAST
MODE
MIN MAX
MIN MAX
1
2
t
t
Cycle time, SCL
10
2.5
µs
µs
c(SCL)
Setup time, SCL high before SDA low (for a repeated START
condition)
4.7
0.6
0.6
su(SCLH-SDAL)
Hold time, SCL low after SDA low (for a START and a repeated
START condition)
3
t
4
µs
h(SCLL-SDAL)
4
5
t
t
t
t
t
t
t
t
t
t
t
Pulse duration, SCL low
4.7
4
1.3
0.6
µs
µs
ns
µs
µs
ns
ns
ns
ns
µs
ns
pF
w(SCLL)
Pulse duration, SCL high
w(SCLH)
‡
6
Setup time, SDA valid before SCL high
250
100
su(SDAV-SDLH)
h(SDA-SDLL)
w(SDAH)
r(SDA)
2
§
§
¶
7
Hold time, SDA valid after SCL low (For I C bus™ devices)
0
0
0.9
8
Pulse duration, SDA high between STOP and START conditions
Rise time, SDA
4.7
1.3
#
9
1000 20 + 0.1C
300
300
300
300
b
b
b
b
#
#
#
10
11
12
13
14
15
Rise time, SCL
1000 20 + 0.1C
300 20 + 0.1C
300 20 + 0.1C
r(SCL)
Fall time, SDA
f(SDA)
Fall time, SCL
f(SCL)
Setup time, SCL high before SDA high (for STOP condition)
Pulse duration, spike (must be suppressed)
Capacitive load for each bus line
4
0.6
0
su(SCLH-SDAH)
50
w(SP)
#
C
400
400
b
†
‡
The I2C pins SDA and SCL do not feature fail-safe I/O buffers. These pins could potentially draw current when the device is powered down.
2
2
A Fast-mode I C-bus™ device can be used in a Standard-mode I C-bus™ system, but the requirement t
≥ 250 ns must then be met.
su(SDA−SCLH)
This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period
of the SCL signal, it must output the next data bit to the SDA line t max + t
I C-Bus Specification) before the SCL line is released.
= 1000 + 250 = 1250 ns (according to the Standard-mode
r
su(SDA−SCLH)
2
§
A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the V
region of the falling edge of SCL.
of the SCL signal) to bridge the undefined
] of the SCL signal.
IHmin
¶
#
The maximum t
has only to be met if the device does not stretch the low period [t
h(SDA−SCLL)
w(SCLL)
C = total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed.
b
11
9
SDA
6
8
14
4
13
5
10
SCL
1
12
3
2
7
3
Stop
Start
Repeated
Start
Stop
Figure 4−38. I2C Receive Timings
131
June 2003 − Revised October 2005
SPRS222E
Inter-Integrated Circuit (I2C)
†
Table 4−37. Switching Characteristics for I2C Timings (see Figure 4−39)
−400
−500
−600
NO.
PARAMETER
UNIT
STANDARD
MODE
FAST
MODE
MIN MAX
2.5
MIN MAX
16
17
t
t
Cycle time, SCL
10
µs
µs
c(SCL)
Delay time, SCL high to SDA low (for a repeated START condition)
4.7
0.6
d(SCLH-SDAL)
Delay time, SDA low to SCL low (for a START and a repeated
START condition)
18
t
4
0.6
µs
d(SDAL-SCLL)
19
20
21
22
23
24
25
26
27
28
29
t
t
t
t
t
t
t
t
t
t
Pulse duration, SCL low
4.7
4
1.3
0.6
µs
µs
ns
µs
µs
ns
ns
ns
ns
µs
pF
w(SCLL)
Pulse duration, SCL high
w(SCLH)
d(SDAV-SDLH)
v(SDLL-SDAV)
w(SDAH)
r(SDA)
Delay time, SDA valid to SCL high
250
0
100
2
Valid time, SDA valid after SCL low (For I C bus™ devices)
0
0.9
Pulse duration, SDA high between STOP and START conditions
4.7
1.3
†
Rise time, SDA
1000 20 + 0.1C
300
300
300
300
b
b
b
b
†
†
†
Rise time, SCL
1000 20 + 0.1C
r(SCL)
Fall time, SDA
300 20 + 0.1C
300 20 + 0.1C
f(SDA)
Fall time, SCL
f(SCL)
Delay time, SCL high to SDA high (for STOP condition)
Capacitance for each I2C pin
4
0.6
d(SCLH-SDAH)
C
10
10
p
†
C = total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed.
b
26
24
SDA
21
23
19
28
20
25
SCL
16
27
18
17
22
18
Stop
Start
Repeated
Start
Stop
Figure 4−39. I2C Transmit Timings
132
SPRS222E
June 2003 − Revised October 2005
Host-Port Interface (HPI) [DM641 Only]
4.11 Host-Port Interface (HPI) [DM641 Only]
The HPI is a parallel port through which a host processor can directly access the CPU memory space. The
host device functions as a master to the interface, which increases ease of access. The host and CPU can
exchange information via internal or external memory. The host also has direct access to memory-mapped
peripherals. Connectivity to the CPU memory space is provided through the enhanced DMA (EDMA)
controller. Both the host and the CPU can access the HPI control register (HPIC) and the HPI address register
(HPIA). The host can access the HPI data register (HPID) and the HPIC by using the external data and
interface control signals.
For more detailed information on the HPI peripheral, see the TMS320C6000 DSP Host Port Interface (HPI)
Reference Guide (literature number SPRU578).
4.11.1 HPI Peripheral Register Description(s) [DM641 Only]
Table 4−38. HPI Registers [DM641 Only]
HEX ADDRESS RANGE
ACRONYM
HPID
REGISTER NAME
HPI data register
COMMENTS
Host read/write access only
−
0188 0000
HPIC
HPI control register
HPIC has both Host/CPU read/write access
HPIA
(HPIAW)
HPI address register
(Write)
0188 0004
†
HPIA has both Host/CPU read/write access
HPIA
(HPIAR)
HPI address register
(Read)
0188 0008
†
0188 000C − 0189 FFFF
018A 0000
−
Reserved
HPI transfer request control
register
HPI_TRCTL
018A 0004 − 018B FFFF
−
Reserved
†
Host access to the HPIA register updates both the HPIAW and HPIAR registers. The CPU can access HPIAW and HPIAR independently.
4.11.2 Host-Port Interface (HPI) Electrical Data/Timing [DM641 Only]
†‡
Table 4−39. Timing Requirements for Host-Port Interface Cycles (see Figure 4−40 through Figure 4−43)
[DM641 Only]
−400
−500
−600
NO.
UNIT
MIN MAX
§
1
2
t
t
t
t
t
t
t
t
Setup time, select signals valid before HSTROBE low
5
ns
ns
ns
ns
ns
ns
ns
ns
su(SELV-HSTBL)
h(HSTBL-SELV)
w(HSTBL)
§
Hold time, select signals valid after HSTROBE low
2.4
¶
3
Pulse duration, HSTROBE low
4P
4P
5
4
Pulse duration, HSTROBE high between consecutive accesses
w(HSTBH)
§
10
11
12
13
Setup time, select signals valid before HAS low
su(SELV-HASL)
h(HASL-SELV)
su(HDV-HSTBH)
h(HSTBH-HDV)
§
Hold time, select signals valid after HAS low
2
Setup time, host data valid before HSTROBE high
Hold time, host data valid after HSTROBE high
5
2.8
Hold time, HSTROBE low after HRDY low. HSTROBE should not be
inactivated until HRDY is active (low); otherwise, HPI writes will not complete
properly.
14
t
2
ns
h(HRDYL-HSTBL)
18
19
t
t
Setup time, HAS low before HSTROBE low
Hold time, HAS low after HSTROBE low
2
ns
ns
su(HASL-HSTBL)
2.1
h(HSTBL-HASL)
†
‡
§
¶
HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns.
Select signals include: HCNTL[1:0], HR/W, and HHWIL.
Select the parameter value of 4P or 12.5 ns, whichever is larger.
133
June 2003 − Revised October 2005
SPRS222E
Host-Port Interface (HPI) [DM641 Only]
Table 4−40. Switching Characteristics Over Recommended Operating Conditions During Host-Port
†‡
Interface Cycles (see Figure 4−40 through Figure 4−43) [DM641 Only]
−400
−500
−600
NO.
PARAMETER
UNIT
MIN
1.3
2
MAX
#
6
7
t
t
Delay time, HSTROBE low to HRDY high
4P + 8
ns
ns
d(HSTBL-HRDYH)
Delay time, HSTROBE low to HD low impedance for an HPI read
d(HSTBL-HDLZ)
8
9
t
t
t
t
Delay time, HD valid to HRDY low
−3
ns
ns
ns
ns
d(HDV-HRDYL)
oh(HSTBH-HDV)
d(HSTBH-HDHZ)
Output hold time, HD valid after HSTROBE high
Delay time, HSTROBE high to HD high impedance
Delay time, HSTROBE low to HD valid (HPI16 mode, 2nd half-word only)
1.5
15
16
12
4P + 8
d(HSTBL-HDV)
†
‡
#
HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns.
This parameter is used during HPID reads and writes. For reads, at the beginning of the first half-word transfer (HPI16) on the falling edge of
HSTROBE, the HPI sends the request to the EDMA internal address generation hardware, and HRDY remains high until the EDMA internal
address generation hardware loads the requested data into HPID. For writes, HRDY goes high if the internal write buffer is full.
HAS
1
1
1
1
2
2
2
2
2
2
HCNTL[1:0]
HR/W
1
1
HHWIL
4
3
3
†
HSTROBE
HCS
15
9
15
9
7
16
2nd half-word
HD[15:0] (output)
HRDY
1st half-word
6
8
†
HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
Figure 4−40. HPI16 Read Timing (HAS Not Used, Tied High) [DM641 Only]
134
SPRS222E
June 2003 − Revised October 2005
Host-Port Interface (HPI) [DM641 Only]
†
HAS
19
11
19
11
10
10
10
10
HCNTL[1:0]
HR/W
11
11
11
11
10
10
HHWIL
4
3
‡
HSTROBE
18
18
HCS
15
15
7
9
16
9
HD[15:0] (output)
HRDY
1st half-word
2nd half-word
6
8
†
‡
For correct operation, strobe the HAS signal only once per HSTROBE active cycle.
HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
Figure 4−41. HPI16 Read Timing (HAS Used) [DM641 Only]
HAS
1
1
2
2
2
2
2
2
3
HCNTL[1:0]
HR/W
1
1
1
1
HHWIL
3
4
†
HSTROBE
HCS
12
12
13
2nd half-word
13
HD[15:0] (input)
1st half-word
6
14
HRDY
†
HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
Figure 4−42. HPI16 Write Timing (HAS Not Used, Tied High) [DM641 Only]
135
June 2003 − Revised October 2005
SPRS222E
Host-Port Interface (HPI) [DM641 Only]
19
11
19
†
HAS
11
11
11
10
10
10
10
HCNTL[1:0]
11
11
10
HR/W
10
HHWIL
3
4
‡
HSTROBE
18
12
18
HCS
12
13
2nd half-word
13
HD[15:0] (input)
1st half-word
6
14
HRDY
†
For correct operation, strobe the HAS signal only once per HSTROBE active cycle.
HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
‡
Figure 4−43. HPI16 Write Timing (HAS Used) [DM641 Only]
136
SPRS222E
June 2003 − Revised October 2005
Multichannel Buffered Serial Port (McBSP)
4.12 Multichannel Buffered Serial Port (McBSP)
The McBSP provides these functions:
•
•
•
•
Full-duplex communication
Double-buffered data registers, which allow a continuous data stream
Independent framing and clocking for receive and transmit
Direct interface to industry-standard codecs, analog interface chips (AICs), and other serially connected
analog-to-digital (A/D) and digital-to-analog (D/A) devices
•
External shift clock or an internal, programmable frequency shift clock for data transfer
For more detailed information on the McBSP peripheral, see the TMS320C6000 DSP Multichannel Buffered
Serial Port (McBSP) Reference Guide (literature number SPRU580).
4.12.1 McBSP Peripheral Register Description(s)
Table 4−41. McBSP 0 Registers
HEX ADDRESS RANGE
ACRONYM
REGISTER NAME
COMMENTS
The CPU and EDMA controller
can only read this register; they
cannot write to it.
018C 0000
DRR0
McBSP0 data receive register via Configuration Bus
0x3000 0000 − 0x33FF FFFF
018C 0004
DRR0
DXR0
McBSP0 data receive register via Peripheral Bus
McBSP0 data transmit register via Configuration Bus
McBSP0 data transmit register via Peripheral Bus
McBSP0 serial port control register
0x3000 0000 − 0x33FF FFFF
018C 0008
DXR0
SPCR0
RCR0
018C 000C
McBSP0 receive control register
018C 0010
XCR0
McBSP0 transmit control register
018C 0014
SRGR0
MCR0
McBSP0 sample rate generator register
018C 0018
McBSP0 multichannel control register
018C 001C
RCERE00
XCERE00
PCR0
McBSP0 enhanced receive channel enable register 0
McBSP0 enhanced transmit channel enable register 0
McBSP0 pin control register
018C 0020
018C 0024
018C 0028
RCERE10
XCERE10
RCERE20
XCERE20
RCERE30
XCERE30
–
McBSP0 enhanced receive channel enable register 1
McBSP0 enhanced transmit channel enable register 1
McBSP0 enhanced receive channel enable register 2
McBSP0 enhanced transmit channel enable register 2
McBSP0 enhanced receive channel enable register 3
McBSP0 enhanced transmit channel enable register 3
Reserved
018C 002C
018C 0030
018C 0034
018C 0038
018C 003C
018C 0040 − 018F FFFF
137
June 2003 − Revised October 2005
SPRS222E
Multichannel Buffered Serial Port (McBSP)
Table 4−42. McBSP 1 Registers
HEX ADDRESS RANGE
ACRONYM
REGISTER NAME
COMMENTS
The CPU and EDMA controller
can only read this register; they
cannot write to it.
0190 0000
DRR1
McBSP1 data receive register via Configuration Bus
0x3400 0000 − 0x37FF FFFF
0190 0004
DRR1
DXR1
McBSP1 data receive register via peripheral bus
McBSP1 data transmit register via configuration bus
McBSP1 data transmit register via peripheral bus
McBSP1 serial port control register
0x3400 0000 − 0x37FF FFFF
0190 0008
DXR1
SPCR1
RCR1
0190 000C
McBSP1 receive control register
0190 0010
XCR1
McBSP1 transmit control register
0190 0014
SRGR1
MCR1
McBSP1 sample rate generator register
0190 0018
McBSP1 multichannel control register
0190 001C
RCERE01
XCERE01
PCR1
McBSP1 enhanced receive channel enable register 0
McBSP1 enhanced transmit channel enable register 0
McBSP1 pin control register
0190 0020
0190 0024
0190 0028
RCERE11
XCERE11
RCERE21
XCERE21
RCERE31
XCERE31
–
McBSP1 enhanced receive channel enable register 1
McBSP1 enhanced transmit channel enable register 1
McBSP1 enhanced receive channel enable register 2
McBSP1 enhanced transmit channel enable register 2
McBSP1 enhanced receive channel enable register 3
McBSP1 enhanced transmit channel enable register 3
Reserved
0190 002C
0190 0030
0190 0034
0190 0038
0190 003C
0190 0040 − 0193 FFFF
138
SPRS222E
June 2003 − Revised October 2005
Multichannel Buffered Serial Port (McBSP)
4.12.2 McBSP Electrical Data/Timing
4.12.2.1 Multichannel Buffered Serial Port (McBSP) Timing
†
Table 4−43. Timing Requirements for McBSP (see Figure 4−44)
−400
−500
−600
NO.
UNIT
MIN
MAX
‡§
2
3
t
t
Cycle time, CLKR/X
CLKR/X ext
CLKR/X ext
CLKR int
CLKR ext
CLKR int
CLKR ext
CLKR int
CLKR ext
CLKR int
CLKR ext
CLKX int
CLKX ext
CLKX int
CLKX ext
4P or 6.67
ns
ns
c(CKRX)
¶
Pulse duration, CLKR/X high or CLKR/X low
0.5t
− 1
w(CKRX)
c(CKRX)
9
5
6
t
t
t
t
t
t
Setup time, external FSR high before CLKR low
Hold time, external FSR high after CLKR low
Setup time, DR valid before CLKR low
ns
ns
ns
ns
ns
ns
su(FRH-CKRL)
h(CKRL-FRH)
su(DRV-CKRL)
h(CKRL-DRV)
su(FXH-CKXL)
h(CKXL-FXH)
1.3
6
3
8
7
0.9
3
8
Hold time, DR valid after CLKR low
3.1
9
10
11
Setup time, external FSX high before CLKX low
Hold time, external FSX high after CLKX low
1.3
6
3
†
‡
§
CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also inverted.
P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns.
Use whichever value is greater. Minimum CLKR/X cycle times must be met, even when CLKR/X is generated by an internal clock source. The
minimum CLKR/X cycle times are based on internal logic speed; the maximum usable speed may be lower due to EDMA limitations and AC timing
requirements.
¶
This parameter applies to the maximum McBSP frequency. Operate serial clocks (CLKR/X) in the reasonable range of 40/60 duty cycle.
139
June 2003 − Revised October 2005
SPRS222E
Multichannel Buffered Serial Port (McBSP)
†‡
Table 4−44. Switching Characteristics Over Recommended Operating Conditions for McBSP
(see Figure 4−44)
−400
−500
−600
NO.
PARAMETER
UNIT
MIN
MAX
Delay time, CLKS high to CLKR/X high for internal CLKR/X generated
from CLKS input
1
t
1.4
10
ns
d(CKSH-CKRXH)
§¶#
||
2
3
4
t
t
t
Cycle time, CLKR/X
CLKR/X int
CLKR/X int
CLKR int
CLKX int
CLKX ext
CLKX int
CLKX ext
CLKX int
CLKX ext
4P or 6.67
ns
ns
ns
c(CKRX)
||
Pulse duration, CLKR/X high or CLKR/X low
Delay time, CLKR high to internal FSR valid
C − 1
C + 1
w(CKRX)
−2.1
−1.7
3
d(CKRH-FRV)
3
9
t
t
t
Delay time, CLKX high to internal FSX valid
ns
ns
ns
d(CKXH-FXV)
dis(CKXH-DXHZ)
d(CKXH-DXV)
1.7
9
4
−3.9
Disable time, DX high impedance following last data bit
from CLKX high
12
13
−2.1
9
−3.9 + D1k
−2.1 + D1k
4 + D2k
9 + D2k
Delay time, CLKX high to DX valid
Delay time, FSX high to DX valid
h
h
FSX int
FSX ext
−2.3 + D1
5.6 + D2
14
t
ns
d(FXH-DXV)
ONLY applies when in data
delay 0 (XDATDLY = 00b) mode
h
h
1.9 + D1
9 + D2
†
‡
§
CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also inverted.
Minimum delay times also represent minimum output hold times.
Minimum CLKR/X cycle times must be met, even when CLKR/X is generated by an internal clock source. Minimum CLKR/X cycle times are based
on internal logic speed; the maximum usable speed may be lower due to EDMA limitations and AC timing requirements.
P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns.
Use whichever value is greater.
¶
#
||
C = H or L
S = sample rate generator input clock = 4P if CLKSM = 1 (P = 1/CPU clock frequency)
=
sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
CLKGDV should be set appropriately to ensure the McBSP bit rate does not exceed the maximum limit (see ¶ footnote above).
kExtra delay from CLKX high to DX valid applies only to the first data bit of a device, if and only if DXENA = 1 in SPCR.
if DXENA = 0, then D1 = D2 = 0
if DXENA = 1, then D1 = 4P, D2 = 8P
hExtra delay from FSX high to DX valid applies only to the first data bit of a device, if and only if DXENA = 1 in SPCR.
if DXENA = 0, then D1 = D2 = 0
if DXENA = 1, then D1 = 4P, D2 = 8P
140
SPRS222E
June 2003 − Revised October 2005
Multichannel Buffered Serial Port (McBSP)
CLKS
1
2
3
3
CLKR
FSR (int)
FSR (ext)
DR
4
4
5
6
7
8
Bit(n-1)
(n-2)
(n-3)
2
3
3
CLKX
9
FSX (int)
11
10
FSX (ext)
FSX (XDATDLY=00b)
†
13
14
13
†
12
DX
Bit 0
Bit(n-1)
(n-2)
(n-3)
†
Parameter No. 13 applies to the first data bit only when XDATDLY ≠ 0.
Figure 4−44. McBSP Timing
Table 4−45. Timing Requirements for FSR When GSYNC = 1 (see Figure 4−45)
−400
−500
−600
NO.
UNIT
MIN
MAX
1
2
t
t
Setup time, FSR high before CLKS high
Hold time, FSR high after CLKS high
4
4
ns
ns
su(FRH-CKSH)
h(CKSH-FRH)
CLKS
1
2
FSR external
CLKR/X (no need to resync)
CLKR/X (needs resync)
Figure 4−45. FSR Timing When GSYNC = 1
141
June 2003 − Revised October 2005
SPRS222E
Multichannel Buffered Serial Port (McBSP)
Table 4−46. Timing Requirements for McBSP as SPI Master or Slave:
†‡
CLKSTP = 10b, CLKXP = 0 (see Figure 4−46)
−400
−500
−600
NO.
UNIT
MASTER
SLAVE
MIN MAX
MIN
12
4
MAX
4
5
t
t
Setup time, DR valid before CLKX low
Hold time, DR valid after CLKX low
2 − 12P
5 + 24P
ns
ns
su(DRV-CKXL)
h(CKXL-DRV)
†
‡
P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns.
For all SPI Slave modes, CLKG is programmed as 1/4 of the CPU clock by setting CLKSM = CLKGDV = 1.
Table 4−47. Switching Characteristics Over Recommended Operating Conditions for McBSP as
†‡
SPI Master or Slave: CLKSTP = 10b, CLKXP = 0 (see Figure 4−46)
−400
−500
−600
NO.
PARAMETER
UNIT
§
MASTER
MIN MAX
T − 2 T + 3
SLAVE
MIN
MAX
¶
1
2
3
t
t
t
Hold time, FSX low after CLKX low
ns
ns
ns
h(CKXL-FXL)
d(FXL-CKXH)
d(CKXH-DXV)
#
Delay time, FSX low to CLKX high
Delay time, CLKX high to DX valid
L − 2.5
L + 3
4
−2
12P + 2.8 20P + 17
Disable time, DX high impedance following last data bit
from CLKX low
6
t
L − 2
L + 3
ns
dis(CKXL-DXHZ)
Disable time, DX high impedance following last data bit
from FSX high
7
8
t
t
4P + 3 12P + 17
ns
ns
dis(FXH-DXHZ)
Delay time, FSX low to DX valid
8P + 1.8 16P + 17
d(FXL-DXV)
†
‡
§
P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns.
For all SPI Slave modes, CLKG is programmed as 1/4 of the CPU clock by setting CLKSM = CLKGDV = 1.
S = Sample rate generator input clock = 4P if CLKSM = 1 (P = 1/CPU clock frequency)
=
Sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
T = CLKX period = (1 + CLKGDV) * S
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
FSRP = FSXP = 1. As a SPI Master, FSX is inverted to provide active-low slave-enable output. As a Slave, the active-low signal input on FSX
and FSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for Master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for Slave McBSP
¶
#
FSX should be low before the rising edge of clock to enable Slave devices and then begin a SPI transfer at the rising edge of the Master clock
(CLKX).
CLKX
1
2
8
FSX
7
6
3
DX
DR
Bit 0
Bit(n-1)
Bit(n-1)
(n-2)
(n-3)
(n-4)
4
5
Bit 0
(n-2)
(n-3)
(n-4)
Figure 4−46. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0
142
SPRS222E
June 2003 − Revised October 2005
Multichannel Buffered Serial Port (McBSP)
Table 4−48. Timing Requirements for McBSP as SPI Master or Slave:
†‡
CLKSTP = 11b, CLKXP = 0 (see Figure 4−47)
−400
−500
−600
NO.
UNIT
MASTER
SLAVE
MIN MAX
MIN
12
4
MAX
4
5
t
t
Setup time, DR valid before CLKX high
Hold time, DR valid after CLKX high
2 − 12P
ns
ns
su(DRV-CKXH)
5 + 24P
h(CKXH-DRV)
†
‡
P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns.
For all SPI Slave modes, CLKG is programmed as 1/4 of the CPU clock by setting CLKSM = CLKGDV = 1.
Table 4−49. Switching Characteristics Over Recommended Operating Conditions for McBSP as
†‡
SPI Master or Slave: CLKSTP = 11b, CLKXP = 0 (see Figure 4−47)
−400
−500
−600
NO.
PARAMETER
UNIT
§
MASTER
SLAVE
MIN MAX
MIN
MAX
¶
1
2
3
t
t
t
Hold time, FSX low after CLKX low
L − 2
L + 3
ns
ns
ns
h(CKXL-FXL)
d(FXL-CKXH)
d(CKXL-DXV)
#
Delay time, FSX low to CLKX high
Delay time, CLKX low to DX valid
T − 2.5 T + 3
−2
4
12P + 3 20P + 17
12P + 3 20P + 17
8P + 2 16P + 17
Disable time, DX high impedance following last data bit from
CLKX low
6
7
t
t
−2
4
ns
ns
dis(CKXL-DXHZ)
d(FXL-DXV)
Delay time, FSX low to DX valid
H − 2 H + 4
†
‡
§
P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns.
For all SPI Slave modes, CLKG is programmed as 1/4 of the CPU clock by setting CLKSM = CLKGDV = 1.
S = Sample rate generator input clock = 4P if CLKSM = 1 (P = 1/CPU clock frequency)
=
Sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
T = CLKX period = (1 + CLKGDV) * S
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
FSRP = FSXP = 1. As a SPI Master, FSX is inverted to provide active-low slave-enable output. As a Slave, the active-low signal input on FSX
and FSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for Master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for Slave McBSP
¶
#
FSX should be low before the rising edge of clock to enable Slave devices and then begin a SPI transfer at the rising edge of the Master clock
(CLKX).
CLKX
1
2
7
FSX
DX
6
3
Bit 0
Bit(n-1)
Bit(n-1)
(n-2)
(n-3)
(n-3)
(n-4)
4
5
DR
Bit 0
(n-2)
(n-4)
Figure 4−47. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0
143
June 2003 − Revised October 2005
SPRS222E
Multichannel Buffered Serial Port (McBSP)
Table 4−50. Timing Requirements for McBSP as SPI Master or Slave:
†‡
CLKSTP = 10b, CLKXP = 1 (see Figure 4−48)
−400
−500
−600
NO.
UNIT
MASTER
SLAVE
MIN MAX
MIN
12
4
MAX
4
5
t
t
Setup time, DR valid before CLKX high
Hold time, DR valid after CLKX high
2 − 12P
ns
ns
su(DRV-CKXH)
5 + 24P
h(CKXH-DRV)
†
‡
P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns.
For all SPI Slave modes, CLKG is programmed as 1/4 of the CPU clock by setting CLKSM = CLKGDV = 1.
Table 4−51. Switching Characteristics Over Recommended Operating Conditions for McBSP as
†‡
SPI Master or Slave: CLKSTP = 10b, CLKXP = 1 (see Figure 4−48)
−400
−500
−600
NO.
PARAMETER
UNIT
§
MASTER
MIN MAX
SLAVE
MIN
MAX
¶
1
2
3
t
t
t
Hold time, FSX low after CLKX high
T − 2 T + 3
ns
ns
ns
h(CKXH-FXL)
d(FXL-CKXL)
d(CKXL-DXV)
#
Delay time, FSX low to CLKX low
H − 2.5 H + 3
Delay time, CLKX low to DX valid
−2
4
12P + 3 20P + 17
Disable time, DX high impedance following last data bit
from CLKX high
6
t
H − 2 H + 3
ns
dis(CKXH-DXHZ)
Disable time, DX high impedance following last data bit
from FSX high
7
8
t
t
4P + 3 12P + 17
8P + 2 16P + 17
ns
ns
dis(FXH-DXHZ)
Delay time, FSX low to DX valid
d(FXL-DXV)
†
‡
§
P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns.
For all SPI Slave modes, CLKG is programmed as 1/4 of the CPU clock by setting CLKSM = CLKGDV = 1.
S = Sample rate generator input clock = 4P if CLKSM = 1 (P = 1/CPU clock frequency)
=
Sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
T = CLKX period = (1 + CLKGDV) * S
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
FSRP = FSXP = 1. As a SPI Master, FSX is inverted to provide active-low slave-enable output. As a Slave, the active-low signal input on FSX
and FSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for Master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for Slave McBSP
¶
#
FSX should be low before the rising edge of clock to enable Slave devices and then begin a SPI transfer at the rising edge of the Master clock
(CLKX).
CLKX
1
2
8
FSX
7
6
3
DX
DR
Bit 0
Bit(n-1)
Bit(n-1)
(n-2)
(n-3)
(n-4)
4
5
Bit 0
(n-2)
(n-3)
(n-4)
Figure 4−48. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1
144
SPRS222E
June 2003 − Revised October 2005
Multichannel Buffered Serial Port (McBSP)
Table 4−52. Timing Requirements for McBSP as SPI Master or Slave:
†‡
CLKSTP = 11b, CLKXP = 1 (see Figure 4−49)
−400
−500
−600
NO.
UNIT
MASTER
SLAVE
MIN MAX
MIN
12
4
MAX
4
5
t
t
Setup time, DR valid before CLKX high
Hold time, DR valid after CLKX high
2 − 12P
ns
ns
su(DRV-CKXH)
5 + 24P
h(CKXH-DRV)
†
‡
P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns.
For all SPI Slave modes, CLKG is programmed as 1/4 of the CPU clock by setting CLKSM = CLKGDV = 1.
Table 4−53. Switching Characteristics Over Recommended Operating Conditions for McBSP as
†‡
SPI Master or Slave: CLKSTP = 11b, CLKXP = 1 (see Figure 4−49)
−400
−500
−600
NO.
PARAMETER
UNIT
§
MASTER
MIN
SLAVE
MIN
MAX
MAX
¶
1
2
3
t
t
t
Hold time, FSX low after CLKX high
H − 2
H + 3
ns
ns
ns
h(CKXH-FXL)
d(FXL-CKXL)
d(CKXH-DXV)
#
Delay time, FSX low to CLKX low
T − 2.5 T + 1.5
Delay time, CLKX high to DX valid
−2
−2
4
4
12P + 3 20P + 17
12P + 3 20P + 17
8P + 2 16P + 17
Disable time, DX high impedance following last data bit
from CLKX high
6
7
t
t
ns
ns
dis(CKXH-DXHZ)
d(FXL-DXV)
Delay time, FSX low to DX valid
L − 2
L + 4
†
‡
§
P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns.
For all SPI Slave modes, CLKG is programmed as 1/4 of the CPU clock by setting CLKSM = CLKGDV = 1.
S = Sample rate generator input clock = 4P if CLKSM = 1 (P = 1/CPU clock frequency)
=
Sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
T = CLKX period = (1 + CLKGDV) * S
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
FSRP = FSXP = 1. As a SPI Master, FSX is inverted to provide active-low slave-enable output. As a Slave, the active-low signal input on FSX
and FSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for Master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for Slave McBSP
¶
#
FSX should be low before the rising edge of clock to enable Slave devices and then begin a SPI transfer at the rising edge of the Master clock
(CLKX).
CLKX
1
2
FSX
DX
7
6
3
Bit 0
Bit 0
Bit(n-1)
Bit(n-1)
(n-2)
(n-3)
(n-4)
4
5
DR
(n-2)
(n-3)
(n-4)
Figure 4−49. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1
145
June 2003 − Revised October 2005
SPRS222E
Video Port
4.13 Video Port
Each Video Port is capable of sending and receiving digital video data. The Video Ports are also capable of
capturing/displaying RAW data. The Video Port peripherals follow video standards such as CCIR601 and
ITU-BT.656.
4.13.1 Video Port Device-Specific Information
The TMS320DM641 device has two video port peripherals [VP0 and VP1]. The TMS320DM640 device only
supports one video port peripheral [VP0].
The video port peripheral can operate as a video capture port, video display port, or as a transport stream
interface (TSI) capture port.
The port consists of a single channel A. A 2560-byte capture/display buffer is utilized on this channel. The port
is always configured for either video capture or display only. Separate data pipelines control the parsing and
formatting of video capture or display data for each of the BT.656, raw video, and TSI modes.
For video capture operation, the video port may operate as a single channel of 8-bit BT.656, 8-bit raw video,
or 8-bit TSI.
For video display operation, the video port may operate as 8-bit BT.656 or 8-bit raw video.
For more detailed information on the DM641 and DM640 Video Port peripherals, see the TMS320C64x DSP
Video Port/VCXO Interpolated Control (VIC) Port Reference Guide (literature number SPRU629).
4.13.2 Video Port Peripheral Register Description(s)
Table 4−54. Video Port 0 and 1 (VP0 and VP1) Control Registers
HEX ADDRESS RANGE
ACRONYM
DESCRIPTION
VP1
[DM641 ONLY]
VP0
01C4 0000
01C4 0004
01C4 0008
01C4 000C
01C4 0020
01C4 0024
01C4 0028
01C4 002C
01C4 0030
01C4 0034
01C4 0038
01C4 003C
01C4 0040
01C4 0044
01C4 00C0
01C4 00C4
01C4 00C8
01C4 00CC
01C4 0100
01C4 4000
01C4 4004
01C4 4008
01C4 400C
01C4 4020
01C4 4024
01C4 4028
01C4 402C
01C4 4030
01C4 4034
01C4 4038
01C4 403C
01C4 4040
01C4 4044
01C4 40C0
01C4 40C4
01C4 40C8
01C4 40CC
01C4 4100
VP_PIDx
VP_PCRx
−
Video Port Peripheral Identification Register
Video Port Peripheral Control Register
Reserved
−
Reserved
VP_PFUNCx
VP_PDIRx
VP_PDINx
VP_PDOUTx
VP_PDSETx
VP_PDCLRx
VP_PIENx
VP_PIPOx
VP_PISTATx
VP_PICLRx
VP_CTLx
VP_STATx
VP_IEx
Video Port Pin Function Register
Video Port Pin Direction Register
Video Port Pin Data Input Register
Video Port Pin Data Output Register
Video Port Pin Data Set Register
Video Port Pin Data Clear Register
Video Port Pin Interrupt Enable Register
Video Port Pin Interrupt Polarity Register
Video Port Pin Interrupt Status Register
Video Port Pin Interrupt Clear Register
Video Port Control Register
Video Port Status Register
Video Port Interrupt Enable Register
Video Port interrupt Status Register
Video Capture Channel A Status Register
VP_ISx
VC_STATx
146
SPRS222E
June 2003 − Revised October 2005
Video Port
Table 4−54. Video Port 0 and 1 (VP0 and VP1) Control Registers (Continued)
HEX ADDRESS RANGE
ACRONYM
DESCRIPTION
VP1
VP0
[DM641 ONLY]
01C4 0104
01C4 0108
01C4 010C
01C4 0110
01C4 0114
01C4 0118
01C4 011C
01C4 0120
01C4 0180
01C4 0184
01C4 0188
01C4 018C
01C4 0190
01C4 0194
01C4 0198
01C4 019C
01C4 01A0
01C4 01A4
01C4 0200
01C4 0204
01C4 0208
01C4 020C
01C4 0210
01C4 0214
01C4 0218
01C4 021C
01C4 0220
01C4 0224
01C4 0228
01C4 022C
01C4 0230
01C4 0234
01C4 0238
01C4 023C
01C4 0240
01C4 0244
01C4 0248
01C4 024C
01C4 0250
01C4 0254
01C4 4104
01C4 4108
01C4 410C
01C4 4110
01C4 4114
01C4 4118
01C4 411C
01C4 4120
01C4 4180
01C4 4184
01C4 4188
01C4 418C
01C4 4190
01C4 4194
01C4 4198
01C4 419C
01C4 41A0
01C4 41A4
01C4 4200
01C4 4204
01C4 4208
01C4 420C
01C4 4210
01C4 4214
01C4 4218
01C4 421C
01C4 4220
01C4 4224
01C4 4228
01C4 422C
01C4 4230
01C4 4234
01C4 4238
01C4 423C
01C4 4240
01C4 4244
01C4 4248
01C4 424C
01C4 4250
01C4 4254
VC_CTLx
VC_ASTRTx
VC_ASTOPx
VC_ASTRTx
VC_ASTOPx
VC_AVINTx
Video Capture Channel A Control Register
Video Capture Channel A Field 1 Start Register
Video Capture Channel A Field 2 Stop Register
Video Capture Channel A Field 2 Start Register
Video Capture Channel A Field 1 Stop Register
Video Capture Channel A Vertical Interrupt Register
Video Capture Channel A Threshold Register
Video Capture Channel A Event Count Register
TCI Capture Control Register
VC_ATHRLDx
VC_AEVTCTx
TSI_CTLx
TSI_CLKINITLx
TSI_CLKINITMx
TSI_STCLKLx
TSI_STCLKMx
TSI_STCMPLx
TSI_STCMPMx
TSI_STMSKLx
TSI_STMSKMx
TSI_TICKSx
TCI Clock Initialization LSB Register
TCI Clock Initialization MSB Register
TCI System Time Clock LSB Register
TCI System Time Clock MSB Register
TCI System Time Clock Compare LSB Register
TCI System Time Clock Compare MSB Register
TCI System Time Clock Compare Mask LSB Register
TCI System Time Clock Compare Mask MSB Register
TCI System Time Clock Ticks Interrupt Register
Video Display Status Register
VD_STATx
VD_CTLx
Video Display Control Register
VD_FRMSZx
VD_HBLNKx
VD_VBLKS1x
VD_VBLKE1x
VD_VBLKS2x
VD_VBLKE2x
VD_IMGOFF1x
VD_IMGSZ1x
VD_IMGOFF2x
VD_IMGSZ2x
VD_FLDT1x
Video Display Frame Size Register
Video Display Horizontal Blanking Register
Video Display Field 1 Vertical Blanking Start Register
Video Display Field 1 Vertical Blanking End Register
Video Display Field 2 Vertical Blanking Start Register
Video Display Field 2 Vertical Blanking End Register
Video Display Field 1 Image Offset Register
Video Display Field 1 Image Size Register
Video Display Field 2 Image Offset Register
Video Display Field 2 Image Size Register
Video Display Field 1 Timing Register
VD_FLDT2x
Video Display Field 2 Timing Register
VD_THRLDx
VD_HSYNCx
VD_VSYNS1x
VD_VSYNE1x
VD_VSYNS2x
VD_VSYNE2x
VD_RELOADx
VD_DISPEVTx
Video Display Threshold Register
Video Display Horizontal Synchronization Register
Video Display Field 1 Vertical Synchronization Start Register
Video Display Field 1 Vertical Synchronization End Register
Video Display Field 2 Vertical Synchronization Start Register
Video Display Field 2 Vertical Synchronization End Register
Video Display Counter Reload Register
Video Display Display Event Register
147
June 2003 − Revised October 2005
SPRS222E
Video Port
Table 4−54. Video Port 0 and 1 (VP0 and VP1) Control Registers (Continued)
HEX ADDRESS RANGE
ACRONYM
DESCRIPTION
Video Display Clipping Register
VP1
[DM641 ONLY]
VP0
01C4 0258
01C4 025C
01C4 0260
01C4 0264
01C4 0268
01C4 026C
7400 000
01C4 4258
01C4 425C
01C4 4260
01C4 4264
01C4 4268
01C4 426C
7800 0000
7800 0008
7800 0010
7800 0020
7800 0028
7800 0030
VD_CLIPx
VD_DEFVALx
VD_VINTx
VD_FBITx
VD_VBIT1x
VD_VBIT2x
Y_RSCA
Video Display Default Display Value Register
Video Display Vertical Interrupt Register
Video Display Field Bit Register
Video Display Field 1Vertical Blanking Bit Register
Video Display Field 2Vertical Blanking Bit Register
Y FIFO Source Register A
7400 0008
7400 0010
7400 0020
7400 0028
7400 0030
CB_SRCA
CR_SRCA
Y_DSTA
CB FIFO Source Register A
CR FIFO Source Register A
Y FIFO Destination Register A
CB_DST
CB FIFO Destination Register A
CR_DST
CR FIFO Destination Register A
148
SPRS222E
June 2003 − Revised October 2005
Video Port
4.13.3 Video Port (VP0 [DM641/DM640], VP1 [DM641 Only]) Electrical Data/Timing
4.13.3.1 VCLKIN Timing (Video Capture Mode)
†
Table 4−55. Timing Requirements for Video Capture Mode for VPxCLKINx (see Figure 4−50)
−400
−500
−600
NO.
UNIT
MIN
12.5
5.4
MAX
1
2
3
4
t
t
t
t
Cycle time, VPxCLKINx
ns
ns
ns
ns
c(VKI)
Pulse duration, VPxCLKINx high
Pulse duration, VPxCLKINx low
Transition time, VPxCLKINx
w(VKIH)
w(VKIL)
t(VKI)
5.4
3
†
The reference points for the rise and fall transitions are measured at V MAX and V MIN.
IL
IH
4
1
2
3
VPxCLKINx
4
Figure 4−50. Video Port Capture VPxCLKINx TIming
149
June 2003 − Revised October 2005
SPRS222E
Video Port
4.13.3.2 Video Data and Control Timing (Video Capture Mode)
Table 4−56. Timing Requirements in Video Capture Mode for Video Data and Control Inputs
(see Figure 4−51)
−400
−500
−600
NO.
UNIT
MIN
2.9
0.5
2.9
0.5
MAX
1
2
3
4
t
t
t
t
Setup time, VPxDx valid before VPxCLKINx high
Hold time, VPxDx valid after VPxCLKINx high
Setup time, VPxCTLx valid before VPxCLKINx high
Hold time, VPxCTLx valid after VPxCLKINx high
ns
ns
ns
ns
su(VDATV-VKIH)
h(VDATV-VKIH)
su(VCTLV-VKIH)
h(VCTLV-VKIH)
VPxCLKINx
1
3
2
VPxD[7:0] (Input)
VPxCTLx (Input)
4
Figure 4−51. Video Port Capture Data and Control Input Timing
150
SPRS222E
June 2003 − Revised October 2005
Video Port
4.13.3.3 VCLKIN Timing (Video Display Mode)
†
Table 4−57. Timing Requirements for Video Display Mode for VPxCLKINx (see Figure 4−52)
−400
−500
−600
NO.
UNIT
MIN
9
MAX
1
2
3
4
t
t
t
t
Cycle time, VPxCLKINx
ns
ns
ns
ns
c(VKI)
Pulse duration, VPxCLKINx high
Pulse duration, VPxCLKINx low
Transition time, VPxCLKINx
4.1
4.1
w(VKIH)
w(VKIL)
t(VKI)
3
†
The reference points for the rise and fall transitions are measured at V MAX and V MIN.
IL
IH
4
1
2
3
VPxCLKINx
4
Figure 4−52. Video Port Display VPxCLKINx Timing
4.13.3.4 Video Control Input/Output and Video Display Data Output Timing With Respect to
VPxCLKINx and VPxCLKOUTx (Video Display Mode)
Table 4−58. Timing Requirements in Video Display Mode for Video Control Input Shown With
Respect to VPxCLKINx and VPxCLKOUTx (see Figure 4−53)
−400
−500
−600
NO.
UNIT
MIN
MAX
13
14
15
16
t
t
t
t
Setup time, VPxCTLx valid before VPxCLKINx high
Hold time, VPxCTLx valid after VPxCLKINx high
Setup time, VPxCTLx valid before VPxCLKOUTx high
2.9
0.5
ns
ns
ns
ns
su(VCTLV-VKIH)
h(VCTLV-VKIH)
su(VCTLV-VKOH)
h(VCTLV-VKOH)
‡
7.4
‡
Hold time, VPxCTLx valid after VPxCLKOUTx high
−0.9
‡
Assuming non-inverted VPxCLKOUTx signal.
151
June 2003 − Revised October 2005
SPRS222E
Video Port
Table 4−59. Switching Characteristics Over Recommended Operating Conditions in Video
Display Mode for Video Data and Control Output Shown With Respect to
†‡
VPxCLKINx and VPxCLKOUTx (see Figure 4−53)
−400
−500
−600
NO.
PARAMETER
UNIT
MIN
V − 0.7
MAX
1
2
3
4
5
6
7
8
t
t
t
t
t
t
t
t
Cycle time, VPxCLKOUTx
V + 0.7
ns
ns
ns
ns
ns
ns
ns
ns
c(VKO)
Pulse duration, VPxCLKOUTx high
Pulse duration, VPxCLKOUTx low
VH − 0.7 VH + 0.7
VL − 0.7 VL + 0.7
1.8
w(VKOH)
w(VKOL)
Transition time, VPxCLKOUTx
t(VKO)
§
Delay time, VPxCLKINx high to VPxCLKOUTx high
1.1
1.1
1.1
1.1
5.7
5.7
5.7
5.7
d(VKIH-VKOH)
d(VKIL-VKOL)
§
Delay time, VPxCLKINx low to VPxCLKOUTx low
Delay time, VPxCLKINx high to VPxCLKOUTx low
Delay time, VPxCLKINx low to VPxCLKOUTx high
d(VKIH-VKOL)
d(VKIL-VKOH)
¶
9
t
t
t
t
Delay time, VPxCLKINx high to VPxOUT valid
9
ns
ns
ns
ns
d(VKIH-VPOUTV)
d(VKIH-VPOUTIV)
d(VKOH-VPOUTV)
d(VKOH-VPOUTIV)
¶
10
11
12
Delay time, VPxCLKINx high to VPxOUT invalid
1.7
†¶
Delay time, VPxCLKOUTx high to VPxOUT valid
4.3
†¶
Delay time, VPxCLKOUTx high to VPxOUT invalid
−0.2
†
‡
§
¶
V = the video input clock (VPxCLKINx) period in ns.
VH is the high period of V (video input clock period) in ns and VL is the low period of V (video input clock period) in ns.
Assuming non-inverted VPxCLKOUTx signal.
VPxOUT consists of VPxCTLx and VPxD[7:0]
VPxCLKINx
5
7
2
1
6
8
3
VPxCLKOUTx
[VCLK2P = 0]
4
4
VPxCLKOUTx
(Inverted)
[VCLK2P = 1]
12
10
11
9
VPxCTLx,
VPxD[7:0]
(Outputs)
15
16
14
13
VPxCTLx
(Input)
Figure 4−53. Video Port Display Data Output Timing and Control Input/Output Timing
With Respect to VPxCLKINx and VPxCLKOUTx
152
SPRS222E
June 2003 − Revised October 2005
Video Port
4.13.3.5 Video Dual-Display Sync Mode Timing (With Respect to VPxCLKINx)
Table 4−60. Timing Requirements for Dual-Display Sync Mode for VPxCLKINx (see Figure 4−54)
−400
−500
−600
NO.
UNIT
MIN
MAX
1
t
Skew rate, VPxCLKINx before VPyCLKINy
500
ps
skr(VKI)
VPxCLKINx
VPyCLKINy
1
Figure 4−54. Video Port Dual-Display Sync Timing
153
June 2003 − Revised October 2005
SPRS222E
VCXO Interpolated Control (VIC)
4.14 VCXO Interpolated Control (VIC)
The VIC can be used in conjunction with the Video Ports (VPs) to maintain synchronization of a video stream.
The VIC can also be used to control a VCXO to adjust the pixel clock rate to a video port.
4.14.1 VIC Device-Specific Information
The VCXO interpolated control (VIC) port provides digital-to-analog conversation with resolution from 9-bits
to up to 16-bits. The output of the VIC is a single bit interpolated D/A output (VDAC pin).
Typical D/A converters provide a discrete output level for every value of the digital word that is being converted.
This is a problem for digital words that are long. This is avoided in a Sigma Delta type D/A converter by
choosing a few widely spaced output levels and interpolating values between them. The interpolating
mechanism causes the output to oscillate rapidly between the levels in such a manner that the average output
represents the value of input code.
In the VIC, two output levels are chosen (0 and 1), and Sigma Delta interpolation scheme is implemented to
interpolate between these levels with a rapidly changing signal. The frequency of interpolation is dependent
on the resolution needed.
When the video port is used in transport stream interface (TSI) mode, the VIC port is used to control the system
clock, VCXO, for MPEG transport stream.
The VIC supports the following features:
•
•
•
Single interpolation for D/A conversion
Programmable precision from 9-to-16 bits
Interface for register accesses
For more detailed information on the DM641 and DM640 VCXO interpolated control (VIC) peripheral, see the
TMS320C64x DSP Video Port/VCXO Interpolated Control (VIC) Port Reference Guide (literature number
SPRU629).
4.14.2 VIC Peripheral Register Description(s)
Table 4−61. VCXO Interpolated Control (VIC) Port Registers
HEX ADDRESS RANGE
01C4 C000
ACRONYM
VICCTL
VICIN
REGISTER NAME
VIC control register
01C4 C004
VIC input register
VIC clock divider register
Reserved
01C4 C008
VPDIV
−
01C4 C00C − 01C4 FFFF
154
SPRS222E
June 2003 − Revised October 2005
VCXO Interpolated Control (VIC)
4.14.3 VIC Electrical Data/Timing
4.14.3.1 STCLK Timing
†
Table 4−62. Timing Requirments for STCLK (see Figure 4−55)
−400
−500
−600
NO.
UNIT
MIN
MAX
1
2
3
4
t
t
t
t
Cycle time, STCLK
33.3
16
ns
ns
ns
ns
c(STCLK)
w(STCLKH)
w(STCLKL)
t(STCLK)
Pulse duration, STCLK high
Pulse duration, STCLK low
Transition time, STCLK
16
3
†
The reference points for the rise and fall transitions are measured at V MAX and V MIN.
IL
IH
4
1
2
3
STCLK
4
Figure 4−55. STCLK Timing
155
June 2003 − Revised October 2005
SPRS222E
Ethernet Media Access Controller (EMAC)
4.15 Ethernet Media Access Controller (EMAC)
The EMAC controls the flow of packet data from the DSP to the PHY.
4.15.1 EMAC Device-Specific Information
The ethernet media access controller (EMAC) provides an efficient interface between the DM641/DM640 DSP
core processor and the network. The DM641/DM640 EMAC support both 10Base-T and 100Base-TX, or 10
Mbits/second (Mbps) and 100 Mbps in either half- or full-duplex, with hardware flow control and quality of
service (QOS) support. The DM641/DM640 EMAC makes use of a custom interface to the DSP core that
allows efficient data transmission and reception.
The EMAC controls the flow of packet data from the DSP to the PHY. The MDIO module controls PHY
configuration and status monitoring.
Both the EMAC and the MDIO modules interface to the DSP through a custom interface that allows efficient
data transmission and reception. This custom interface is referred to as the EMAC control module, and is
considered integral to the EMAC/MDIO peripheral. The control module is also used to control device reset,
interrupts, and system priority.
TheTMS320C6000 DSP Ethernet Media Access Controller (EMAC) / Management Data Input/Output (MDIO)
Module Reference Guide (literature number SPRU628) describes the DM641/DM640 EMAC peripheral in
detail. Some of the features documented in this peripheral reference guide are not supported on the
DM641/DM640 at this time. The DM641/DM640 supports one receive channel and does not support receive
quality of service (QOS). For a list of supported registers and register fields, see Table 4−63 [Ethernet MAC
(EMAC) Control Registers] and Table 4−64 [EMAC Statistics Registers] in this data manual.
4.15.2 EMAC Peripheral Register Description(s)
Table 4−63. Ethernet MAC (EMAC) Control Registers
HEX ADDRESS RANGE
01C8 0000
ACRONYM
TXIDVER
REGISTER NAME
Transmit Identification and Version Register
Transmit Control Register
Transmit Teardown Register
Reserved
01C8 0004
TXCONTROL
TXTEARDOWN
−
01C8 0008
01C8 000C
01C8 0010
RXIDVER
Receive Identification and Version Register
Receive Control Register
01C8 0014
RXCONTROL
Receive Teardown Register
(RXTDNCH field only supports writes of 0.)
01C8 0018
RXTEARDOWN
01C8 001C − 01C8 00FF
−
Reserved
Receive Multicast/Broadcast/Promiscuous Channel Enable Register
(The RXQOSEN field is reserved and only supports writes of 0. The
PROMCH, BROADCH, and MUCTCH bit fields only support writes of 0.)
01C8 0100
RXMBPENABLE
Receive Unicast Set Register
(Bits 7−1 are reserved and only support writes of 0.)
01C8 0104
01C8 0108
RXUNICASTSET
Receive Unicast Clear Register
(Bits 7−1 are reserved and only support writes of 0.)
RXUNICASTCLEAR
01C8 010C
01C8 0110
RXMAXLEN
RXBUFFEROFFSET
RXFILTERLOWTHRESH
−
Receive Maximum Length Register
Receive Buffer Offset Register
01C8 0114
Receive Filter Low Priority Packets Threshold Register
Reserved
01C8 0118 − 01C8 011F
01C8 0120
RX0FLOWTHRESH
Receive Channel 0 Flow Control Threshold Register
156
SPRS222E
June 2003 − Revised October 2005
Ethernet Media Access Controller (EMAC)
Table 4−63. Ethernet MAC (EMAC) Control Registers (Continued)
HEX ADDRESS RANGE
01C8 0124
ACRONYM
RX1FLOWTHRESH
RX2FLOWTHRESH
RX3FLOWTHRESH
RX4FLOWTHRESH
RX5FLOWTHRESH
RX6FLOWTHRESH
RX7FLOWTHRESH
RX0FREEBUFFER
RX1FREEBUFFER
RX2FREEBUFFER
RX3FREEBUFFER
RX4FREEBUFFER
RX5FREEBUFFER
RX6FREEBUFFER
RX7FREEBUFFER
MACCONTROL
MACSTATUS
REGISTER NAME
01C8 0128
01C8 012C
01C8 0130
Reserved. Do not write.
01C8 0134
01C8 0138
01C8 013C
01C8 0140
Receive Channel 0 Free Buffer Count Register
Reserved. Do not write.
01C8 0144
01C8 0148
01C8 014C
01C8 0150
01C8 0154
01C8 0158
01C8 015C
01C8 0160
MAC Control Register
01C8 0164
MAC Status Register (RXQOSACT field is reserved.)
Reserved
01C8 0168 − 01C8 016C
01C8 0170
−
TXINTSTATRAW
TXINTSTATMASKED
TXINTMASKSET
TXINTMASKCLEAR
MACINVECTOR
−
Transmit Interrupt Status (Unmasked) Register
Transmit Interrupt Status (Masked) Register
Transmit Interrupt Mask Set Register
Transmit Interrupt Mask Clear Register
MAC Input Vector Register
01C8 0174
01C8 0178
01C8 017C
01C8 0180
01C8 0184 − 01C8 018F
Reserved
Receive Interrupt Status (Unmasked) Register
(Bits 7−1 are reserved.)
01C8 0190
01C8 0194
01C8 0198
01C8 019C
RXINTSTATRAW
RXINTSTATMASKED
RXINTMASKSET
Receive Interrupt Status (Masked) Register
(Bits 7−1 are reserved.)
Receive Interrupt Mask Set Register
(Bits 7−1 are reserved and only support writes of 0.)
Receive Interrupt Mask Clear Register
(Bits 7−1 are reserved and only support writes of 0.)
RXINTMASKCLEAR
01C8 01A0
01C8 01A4
01C8 01A8
01C8 01AC
01C8 01B0
01C8 01B4
01C8 01B8
01C8 01BC
01C8 01C0
01C8 01C4
01C8 01C8
01C8 01CC
01C8 01D0
MACINTSTATRAW
MACINTSTATMASKED
MACINTMASKSET
MACINTMASKCLEAR
MACADDRL0
MAC Interrupt Status (Unmasked) Register
MAC Interrupt Status (Masked) Register
MAC Interrupt Mask Set Register
MAC Interrupt Mask Clear Register
MAC Address Channel 0 Lower Byte Register
MACADDRL1
MACADDRL2
MACADDRL3
MACADDRL4
Reserved. Do not write.
MACADDRL5
MACADDRL6
MACADDRL7
MACADDRM
MAC Address Middle Byte Register
157
June 2003 − Revised October 2005
SPRS222E
Ethernet Media Access Controller (EMAC)
Table 4−63. Ethernet MAC (EMAC) Control Registers (Continued)
HEX ADDRESS RANGE
01C8 01D4
01C8 01D8
01C8 01DC
01C8 01E0
ACRONYM
MACADDRH
MACHASH1
MACHASH2
BOFFTEST
TPACETEST
RXPAUSE
TXPAUSE
−
REGISTER NAME
MAC Address High Bytes Register
MAC Address Hash 1 Register
MAC Address Hash 2 Register
Backoff Test Register
01C8 01E4
Transmit Pacing Test Register
01C8 01E8
Receive Pause Timer Register
01C8 01EC
01C8 01F0 − 01C8 01FF
01C8 0200 − 01C8 05FF
01C8 0600
Transmit Pause Timer Register
Reserved
(see Table 4−64)
TX0HDP
EMAC Statistics Registers
Transmit Channel 0 DMA Head Descriptor Pointer Register
Transmit Channel 1 DMA Head Descriptor Pointer Register
Transmit Channel 2 DMA Head Descriptor Pointer Register
Transmit Channel 3 DMA Head Descriptor Pointer Register
Transmit Channel 4 DMA Head Descriptor Pointer Register
Transmit Channel 5 DMA Head Descriptor Pointer Register
Transmit Channel 6 DMA Head Descriptor Pointer Register
Transmit Channel 7 DMA Head Descriptor Pointer Register
Receive Channel 0 DMA Head Descriptor Pointer Register
01C8 0604
TX1HDP
01C8 0608
TX2HDP
01C8 060C
01C8 0610
TX3HDP
TX4HDP
01C8 0614
TX5HDP
01C8 0618
TX6HDP
01C8 061C
01C8 0620
TX7HDP
RX0HDP
01C8 0624
RX1HDP
01C8 0628
RX2HDP
01C8 062C
01C8 0630
RX3HDP
RX4HDP
Reserved. Do not write.
01C8 0634
RX5HDP
01C8 0638
RX6HDP
01C8 063C
01C8 0640
RX7HDP
TX0INTACK
TX1INTACK
TX2INTACK
TX3INTACK
TX4INTACK
TX5INTACK
TX6INTACK
TX7INTACK
RX0INTACK
RX1INTACK
RX2INTACK
RX3INTACK
RX4INTACK
RX5INTACK
RX6INTACK
RX7INTACK
−
Transmit Channel 0 Interrupt Acknowledge Register
Transmit Channel 1 Interrupt Acknowledge Register
Transmit Channel 2 Interrupt Acknowledge Register
Transmit Channel 3 Interrupt Acknowledge Register
Transmit Channel 4 Interrupt Acknowledge Register
Transmit Channel 5 Interrupt Acknowledge Register
Transmit Channel 6 Interrupt Acknowledge Register
Transmit Channel 7 Interrupt Acknowledge Register
Receive Channel 0 Interrupt Acknowledge Register
01C8 0644
01C8 0648
01C8 064C
01C8 0650
01C8 0654
01C8 0658
01C8 065C
01C8 0660
01C8 0664
01C8 0668
01C8 066C
01C8 0670
Reserved. Do not write.
Reserved
01C8 0674
01C8 0678
01C8 067C
01C8 0680 − 01C8 0FFF
158
SPRS222E
June 2003 − Revised October 2005
Ethernet Media Access Controller (EMAC)
Table 4−64. EMAC Statistics Registers
HEX ADDRESS RANGE
01C8 0200
01C8 0204
01C8 0208
01C8 020C
01C8 0210
01C8 0214
01C8 0218
01C8 021C
01C8 0220
01C8 0224
01C8 0228
01C8 022C
01C8 0230
01C8 0234
01C8 0238
01C8 023C
01C8 0240
01C8 0244
01C8 0248
01C8 024C
01C8 0250
01C8 0254
01C8 0258
01C8 025C
01C8 0260
01C8 0264
01C8 0268
01C8 026C
01C8 0270
01C8 0274
01C8 0278
ACRONYM
REGISTER NAME
RXGOODFRAMES
RXBCASTFRAMES
RXMCASTFRAMES
RXPAUSEFRAMES
RXCRCERRORS
RXALIGNCODEERRORS
RXOVERSIZED
RXJABBER
Good Receive Frames Register
Broadcast Receive Frames Register
Multicast Receive Frames Register
Pause Receive Frames Register
Receive CRC Errors Register
Receive Alignment/Code Errors Register
Receive Oversized Frames Register
Receive Jabber Frames Register
RXUNDERSIZED
RXFRAGMENTS
RXFILTERED
Receive Undersized Frames Register
Receive Frame Fragments Register
Filtered Receive Frames Register
Reserved
RXQOSFILTERED
RXOCTETS
Receive Octet Frames Register
TXGOODFRAMES
TXBCASTFRAMES
TXMCASTFRAMES
TXPAUSEFRAMES
TXDEFERRED
Good Transmit Frames Register
Broadcast Transmit Frames Register
Multicast Transmit Frames Register
Pause Transmit Frames Register
Deferred Transmit Frames Register
Collision Register
TXCOLLISION
TXSINGLECOLL
TXMULTICOLL
Single Collision Transmit Frames Register
Multiple Collision Transmit Frames Register
Excessive Collisions Register
TXEXCESSIVECOLL
TXLATECOLL
Late Collisions Register
TXUNDERRUN
TXCARRIERSLOSS
TXOCTETS
Transmit Underrun Register
Transmit Carrier Sense Errors Register
Transmit Octet Frames Register
FRAME64
Transmit and Receive 64 Octet Frames Register
Transmit and Receive 65 to 127 Octet Frames Register
Transmit and Receive 128 to 255 Octet Frames Register
Transmit and Receive 256 to 511 Octet Frames Register
Transmit and Receive 512 to 1023 Octet Frames Register
FRAME65T127
FRAME128T255
FRAME256T511
FRAME512T1023
Transmit and Receive 1024 or Above Octet Frames
Register
01C8 027C
FRAME1024TUP
01C8 0280
01C8 0284
NETOCTETS
RXSOFOVERRUNS
RXMOFOVERRUNS
RXDMAOVERRUNS
−
Network Octet Frames Register
Receive Start of Frame Overruns Register
Receive Middle of Frame Overruns Register
Receive DMA Overruns Register
Reserved
01C8 0288
01C8 028C
01C8 0290 − 01C8 05FF
Table 4−65. EMAC Wrapper
HEX ADDRESS RANGE
01C8 1000 − 01C8 1FFF
01C8 2000 − 01C8 2FFF
ACRONYM
REGISTER NAME
EMAC Control Module Descriptor Memory
Reserved
−
159
June 2003 − Revised October 2005
SPRS222E
Ethernet Media Access Controller (EMAC)
Table 4−66. EWRAP Registers
HEX ADDRESS RANGE
01C8 3000
ACRONYM
EWTRCTRL
EWCTL
REGISTER NAME
TR control
01C8 3004
Interrupt control register
Interrupt timer count
Reserved
01C8 3008
EWINTTCNT
−
01C8 300C − 01C8 37FF
4.15.3 EMAC Electrical Data/Timing
Table 4−67. Timing Requirements for MRCLK (see Figure 4−56)
−400
−500
−600
NO.
UNIT
MIN
MAX
1
2
3
t
t
t
Cycle time, MRCLK
40
14
14
ns
ns
ns
c(MRCLK)
Pulse duration, MRCLK high
Pulse duration, MRCLK low
w(MRCLKH)
w(MRCLKL)
1
2
3
MRCLK
Figure 4−56. MRCLK Timing (EMAC − Receive)
Table 4−68. Timing Requirements for MTCLK (see Figure 4−56)
−400
−500
−600
NO.
UNIT
MIN
MAX
1
2
3
t
t
t
Cycle time, MTCLK
40
14
14
ns
ns
ns
c(MTCLK)
Pulse duration, MTCLK high
Pulse duration, MTCLK low
w(MTCLKH)
w(MTCLKL)
1
2
3
MTCLK
Figure 4−57. MTCLK Timing (EMAC − Transmit)
160
SPRS222E
June 2003 − Revised October 2005
Ethernet Media Access Controller (EMAC)
Table 4−69. Timing Requirements for EMAC MII Receive 10/100 Mbit/s† (see Figure 4−58)
−400
−500
−600
NO.
UNIT
MIN MAX
1
2
t
t
Setup time, receive selected signals valid before MRCLK high
Hold time, receive selected signals valid after MRCLK high
8
8
ns
ns
su(MRXD-MRCLKH)
h(MRCLKH-MRXD)
†
Receive selected signals include: MRXD3−MRXD0, MRXDV, and MRXER.
1
2
MRCLK (Input)
MRXD3−MRXD0,
MRXDV, MRXER (Inputs)
Figure 4−58. EMAC Receive Interface Timing
Table 4−70. Switching Characteristics Over Recommended Operating Conditions for EMAC
‡
MII Transmit 10/100 Mbit/s (see Figure 4−59)
−400
−500
−600
NO.
UNIT
MIN
MAX
1
t
Delay time, MTCLK high to transmit selected signals valid
5
25
ns
d(MTCLKH-MTXD)
‡
Transmit selected signals include: MTXD3−MTXD0, and MTXEN.
1
MTCLK (Input)
MTXD3−MTXD0,
MTXEN (Outputs)
Figure 4−59. EMAC Transmit Interface Timing
161
June 2003 − Revised October 2005
SPRS222E
Management Data Input/Output (MDIO)
4.16 Management Data Input/Output (MDIO)
The MDIO module controls PHY configuration and status monitoring.
4.16.1 Device-Specific Information
The management data input/output (MDIO) module continuously polls all 32 MDIO addresses in order to
enumerate all PHY devices in the system.
The management data input/output (MDIO) module implements the 802.3 serial management interface to
interrogate and control Ethernet PHY(s) using a shared two-wire bus. Host software uses the MDIO module
to configure the auto-negotiation parameters of each PHY attached to the EMAC, retrieve the negotiation
results, and configure required parameters in the EMAC module for correct operation. The module is designed
to allow almost transparent operation of the MDIO interface, with very little maintenance from the core
processor.
TheTMS320C6000 DSP Ethernet Media Access Controller (EMAC) / Management Data Input/Output (MDIO)
Module Reference Guide (literature number SPRU628) describes the DM641/DM640 MDIO peripheral in
detail. Some of the features documented in this peripheral reference guide are not supported on the
DM641/DM640 at this time. The DM641/DM640 only supports one EMAC module. For a list of supported
registers and register fields, see Table 4−71 [MDIO Registers] in this data manual.
4.16.2 Peripheral Register Description(s)
Table 4−71. MDIO Registers
HEX ADDRESS RANGE
01C8 3800
ACRONYM
VERSION
CONTROL
ALIVE
REGISTER NAME
MDIO Version Register
MDIO Control Register
01C8 3804
01C8 3808
MDIO PHY Alive Indication Register
MDIO PHY Link Status Register
01C8 380C
LINK
MDIO Link Status Change Interrupt Register
01C8 3810
01C8 3814
01C8 3818
01C8 381C
01C8 3820
01C8 3824
LINKINTRAW
LINKINTMASKED
USERINTRAW
(MAC1 field is reserved and only supports writes of 0.)
MDIO Link Status Change Interrupt (Masked) Register
(MAC1 field is reserved and only supports writes of 0.)
MDIO User Command Complete Interrupt Register
(MAC1 field is reserved and only supports writes of 0.)
MDIO User Command Complete Interrupt (Masked) Register
(MAC1 field is reserved and only supports writes of 0.)
USERINTMASKED
USERINTMASKSET
USERINTMASKCLEAR
MDIO User Command Complete Interrupt Mask Set Register
(MAC1 field is reserved and only supports writes of 0.)
MDIO User Command Complete Interrupt Mask Clear Register
(MAC1 field is reserved and only supports writes of 0.)
01C8 3828
01C8 382C
USERACCESS0
USERACCESS1
USERPHYSEL0
USERPHYSEL1
−
MDIO User Access Register 0
Reserved. Do not write.
MDIO User PHY Select Register 0
Reserved. Do not write.
Reserved
01C8 3830
01C8 3834
01C8 3838 − 01C8 3FFF
162
SPRS222E
June 2003 − Revised October 2005
Management Data Input/Output (MDIO)
4.16.3 Management Data Input/Output (MDIO) Electrical Data/Timing
Table 4−72. Timing Requirements for MDIO Input (see Figure 4−60 and Figure 4−61)
−400
−500
−600
NO.
UNIT
MIN
MAX
1
2
3
t
t
t
Cycle time, MDCLK
400
180
10
ns
ns
ns
c(MDCLK)
Pulse duration, MDCLK high/low
Setup time, MDIO data input valid before MDCLK high
w(MDCLK)
su(MDIO-MDCLKH)
4
t
Hold time, MDIO data input valid after MDCLK high
0
ns
h(MDCLKH-MDIO)
1
MDCLK
3
4
MDIO
(input)
Figure 4−60. MDIO Input Timing
Table 4−73. Switching Characteristics Over Recommended Operating Conditions for MDIO Output
(see Figure 4−61)
−400
−500
NO.
UNIT
−600
MIN
−10
MAX
7
t
Delay time, MDCLK low to MDIO data output valid
100
ns
d(MDCLKL-MDIO)
1
MDCLK
7
MDIO
(output)
Figure 4−61. MDIO Output Timing
163
June 2003 − Revised October 2005
SPRS222E
Timer
4.17 Timer
The C6000™ DSP device has 32-bit general-purpose timers that can be used to:
•
•
•
•
•
Time events
Count events
Generate pulses
Interrupt the CPU
Send synchronization events to the DMA
The timers have two signaling modes and can be clocked by an internal or an external source. The timers have
an input pin and an output pin. The input and output pins (TINP and TOUT) can function as timer clock input
and clock output. They can also be respectively configured for general-purpose input and output.
With an internal clock, for example, the timer can signal an external A/D converter to start a conversion, or
it can trigger the DMA controller to begin a data transfer. With an external clock, the timer can count external
events and interrupt the CPU after a specified number of events.
4.17.1 Timer Device-Specific Information
The DM641/DM640 device has a total of three 32-bit general-purpose timers (Timer0, Timer1, and Timer2).
Timer2 is not externally pinned out.
For more detailed information, see the TMS320C6000 DSP 32-Bit Timer Reference Guide (literature number
SPRU582).
4.17.2 Timer Peripheral Register Description(s)
Table 4−74. Timer 0 Registers
HEX ADDRESS RANGE
ACRONYM
REGISTER NAME
COMMENTS
Determines the operating mode of the timer, monitors the
timer status, and controls the function of the TOUT pin.
0194 0000
CTL0
Timer 0 control register
Contains the number of timer input clock cycles to count.
This number controls the TSTAT signal frequency.
0194 0004
PRD0
Timer 0 period register
0194 0008
CNT0
Timer 0 counter register
Reserved
Contains the current value of the incrementing counter.
0194 000C − 0197 FFFF
−
Table 4−75. Timer 1 Registers
HEX ADDRESS RANGE
ACRONYM
REGISTER NAME
COMMENTS
Determines the operating mode of the timer, monitors the
timer status, and controls the function of the TOUT pin.
0198 0000
CTL1
Timer 1 control register
Timer 1 period register
Contains the number of timer input clock cycles to count.
This number controls the TSTAT signal frequency.
0198 0004
PRD1
0198 0008
CNT1
Timer 1 counter register
Reserved
Contains the current value of the incrementing counter.
0198 000C − 019B FFFF
−
Table 4−76. Timer 2 Registers
HEX ADDRESS RANGE
ACRONYM
REGISTER NAME
COMMENTS
Determines the operating mode of the timer, monitors the
timer status.
01AC 0000
CTL2
Timer 2 control register
Timer 2 period register
Contains the number of timer input clock cycles to count.
This number controls the TSTAT signal frequency.
01AC 0004
PRD2
01AC 0008
CNT2
Timer 2 counter register
Reserved
Contains the current value of the incrementing counter.
01AC 000C − 01AF FFFF
−
164
SPRS222E
June 2003 − Revised October 2005
Timer
4.17.3 Timer Electrical Data/Timing
†
Table 4−77. Timing Requirements for Timer Inputs (see Figure 4−62)
−400
−500
−600
NO.
UNIT
MIN
MAX
1
2
t
t
Pulse duration, TINP high
Pulse duration, TINP low
8P
8P
ns
ns
w(TINPH)
w(TINPL)
†
P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns.
†
Table 4−78. Switching Characteristics Over Recommended Operating Conditions for Timer Outputs
(see Figure 4−62)
−400
−500
−600
NO.
PARAMETER
UNIT
MIN MAX
3
4
t
t
Pulse duration, TOUT high
Pulse duration, TOUT low
8P−3
8P−3
ns
ns
w(TOUTH)
w(TOUTL)
†
P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns.
2
1
TINPx
4
3
TOUTx
Figure 4−62. Timer Timing
165
June 2003 − Revised October 2005
SPRS222E
General-Purpose Input/Output (GPIO)
4.18 General-Purpose Input/Output (GPIO)
The GPIO peripheral provides dedicated general-purpose pins that can be configured as either inputs or
outputs. When configured as an output, you can write to an internal register to control the state driven on the
output pin. When configured as an input, you can detect the state of the input by reading the state of an internal
register.
In addition, the GPIO peripheral can produce CPU interrupts and EDMA events in different interrupt/event
generation modes.
4.18.1 GPIO Device-Specific Information
To use the GP[7:0] software-configurable GPIO pins, the GPxEN bits in the GP Enable (GPEN) Register and
the GPxDIR bits in the GP Direction (GPDIR) Register must be properly configured.
GPxEN =
GPxDIR =
GPxDIR =
1
0
1
GP[x] pin is enabled
GP[x] pin is an input
GP[x] pin is an output
where “x” represents one of the 7 through 0 GPIO pins
Figure 4−63 shows the GPIO enable bits in the GPEN register for the DM641/DM640 device. To use any of
the GPx pins as general-purpose input/output functions, the corresponding GPxEN bit must be set to “1”
(enabled). Default values are device-specific, so refer to Figure 4−63 for the DM641/DM640 default
configuration.
31
24 23
Reserved
R-0
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
GP7
EN
GP6
EN
GP5
EN
GP4
EN
GP3
EN
GP2
EN
GP1
EN
GP0
EN
Reserved
R/W-0000 0000
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-0 R/W-0 R/W-1
Legend: R/W = Readable/Writeable; -n = value after reset, -x = undefined value after reset
Figure 4−63. GPIO Enable Register (GPEN) [Hex Address: 01B0 0000]
Figure 4−64 shows the GPIO direction bits in the GPDIR register. This register determines if a given GPIO
pin is an input or an output providing the corresponding GPxEN bit is enabled (set to “1”) in the GPEN register.
By default, all the GPIO pins are configured as input pins.
31
24 23
Reserved
R-0
16
15
14
13
12
Reserved
R/W-0000 0000
11
9
8
6
4
3
1
0
10
7
5
2
GP7
DIR
GP6
DIR
GP5
DIR
GP4
DIR
GP3
DIR
GP2
DIR
GP1
DIR
GP0
DIR
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
Legend: R/W = Readable/Writeable; -n = value after reset, -x = undefined value after reset
Figure 4−64. GPIO Direction Register (GPDIR) [Hex Address: 01B0 0004]
For more detailed information on general-purpose inputs/outputs (GPIOs), see the TMS320C6000 DSP
General-Purpose Input/Output (GPIO) Reference Guide (literature number SPRU584).
166
SPRS222E
June 2003 − Revised October 2005
General-Purpose Input/Output (GPIO)
4.18.2 GPIO Peripheral Register Description(s)
Table 4−79. GP0 Registers
HEX ADDRESS RANGE
01B0 0000
ACRONYM
GPEN
GPDIR
GPVAL
−
REGISTER NAME
GP0 enable register
01B0 0004
GP0 direction register
GP0 value register
01B0 0008
01B0 000C
Reserved
01B0 0010
GPDH
GPHM
GPDL
GPLM
GPGC
GPPOL
−
GP0 delta high register
GP0 high mask register
GP0 delta low register
GP0 low mask register
GP0 global control register
GP0 interrupt polarity register
Reserved
01B0 0014
01B0 0018
01B0 001C
01B0 0020
01B0 0024
01B0 0028 − 01B3 EFFF
4.18.3 General-Purpose Input/Output (GPIO) Electrical Data/Timing
†‡
Table 4−80. Timing Requirements for GPIO Inputs (see Figure 4−65)
−400
−500
−600
NO.
UNIT
MIN
MAX
1
2
t
t
Pulse duration, GPIx high
Pulse duration, GPIx low
8P
8P
ns
ns
w(GPIH)
w(GPIL)
†
‡
P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns.
The pulse width given is sufficient to generate a CPU interrupt or an EDMA event. However, if a user wants to have the DSP recognize the GPIx
changes through software polling of the GPIO register, the GPIx duration must be extended to at least 12P to allow the DSP enough time to access
the GPIO register through the CFGBUS.
†
Table 4−81. Switching Characteristics Over Recommended Operating Conditions for GPIO Outputs
(see Figure 4−65)
−400
−500
−600
NO.
PARAMETER
UNIT
MIN
MAX
‡
3
4
t
t
Pulse duration, GPOx high
Pulse duration, GPOx low
24P − 8
ns
ns
w(GPOH)
‡
24P − 8
w(GPOL)
†
‡
P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns.
This parameter value should not be used as a maximum performance specification. Actual performance of back-to-back accesses of the GPIO
is dependent upon internal bus activity.
2
1
GPIx
4
3
GPOx
Figure 4−65. GPIO Port Timing
167
June 2003 − Revised October 2005
SPRS222E
JTAG
4.19 JTAG
The JTAG interface is used for BSDL testing and emulation of the DM641/DM640 device.
4.19.1 JTAG Device-Specific Information
4.19.1.1 IEEE 1149.1 JTAG Compatibility Statement
The TMS320DM641/DM640 DSP requires that both TRST and RESET be asserted upon power up to be
properly initialized. While RESET initializes the DSP core, TRST initializes the DSP’s emulation logic. Both
resets are required for proper operation.
Note: TRST is synchronous and must be clocked by TCLK; otherwise, BSCAN may not respond as expected
after TRST is asserted.
While both TRST and RESET need to be asserted upon power up, only RESET needs to be released for the
DSP to boot properly. TRST may be asserted indefinitely for normal operation, keeping the JTAG port interface
and DSP’s emulation logic in the reset state. TRST only needs to be released when it is necessary to use a
JTAG controller to debug the DSP or exercise the DSP’s boundary scan functionality. RESET must be
released in order for boundary-scan JTAG to read the variant field of IDCODE correctly. Other boundary-scan
instructions work correctly independent of current state of RESET.
The TMS320DM641/DM640 DSP includes an internal pulldown (IPD) on the TRST pin to ensure that TRST
will always be asserted upon power up and the DSP’s internal emulation logic will always be properly initialized
when this pin is not routed out. JTAG controllers from Texas Instruments actively drive TRST high. However,
some third-party JTAG controllers may not drive TRST high but expect the use of an external pullup resistor
on TRST. When using this type of JTAG controller, assert TRST to initialize the DSP after powerup and
externally drive TRST high before attempting any emulation or boundary scan operations.
Following the release of RESET, the low-to-high transition of TRST must occur to latch the state of EMU1 and
EMU0. The EMU[1:0] pins configure the device for either Boundary Scan mode or Normal/Emulation mode.
For more detailed information, see the terminal functions section of this data sheet.
Note: The DESIGN_WARNING section of the TMS320DM641/DM640 BSDL file contains information and
constraints regarding proper device operation while in Boundary Scan Mode.
For more detailed information on the DM641 and DM640 JTAG emulation, see the TMS320C6000 DSP
Designing for JTAG Emulation Reference Guide (literature number SPRU641).
4.19.1.2 JTAG ID Register Description
The JTAG ID register is a read-only register that identifies to the customer the JTAG/Device ID. For the
DM641/DM640 device, the JTAG ID register resides at address location 0x01B3 F008. The register hex value
for the DM641/DM640 device is: 0x0007 902F. For the actual register bit names and their associated bit field
descriptions, see Figure 4−66 and Table 4−82.
31−28
VARIANT (4-Bit)
R-0000
27−12
11−1
0
PART NUMBER (16-Bit)
R-0000 0000 0111 1001
MANUFACTURER (11-Bit)
R-0000 0010 111
LSB
R-1
Legend: R = Read only; -n = value after reset
Figure 4−66. JTAG ID Register Description − TMS320DM641/DM640 Register Value − 0x0007 902F
168
SPRS222E
June 2003 − Revised October 2005
JTAG
Table 4−82. JTAG ID Register Selection Bit Descriptions
BIT
31:28
27:12
11−1
0
NAME
VARIANT
DESCRIPTION
Variant (4-Bit) value. DM641/DM640 value: 0000.
PART NUMBER
Part Number (16-Bit) value. DM641/DM640 value: 0000 0000 0111 1001.
MANUFACTURER
LSB
Manufacturer (11-Bit) value. DM641/DM640 value: 0000 0010 111.
LSB. This bit is read as a “1” for DM641/DM640.
4.19.2 JTAG Peripheral Register Description(s)
Table 4−83. JTAG ID Register
HEX ADDRESS RANGE
ACRONYM
REGISTER NAME
JTAG Identification Register
COMMENTS
Read-only. Provides 32-bit
JTAG ID of the device.
01B3 F008
JTAGID
4.19.3 JTAG Test-Port Electrical Data/Timing
Table 4−84. Timing Requirements for JTAG Test Port (see Figure 4−67)
−400
−500
−600
NO.
UNIT
MIN
MAX
1
3
4
t
t
t
Cycle time, TCK
35
10
9
ns
ns
ns
c(TCK)
Setup time, TDI/TMS/TRST valid before TCK high
Hold time, TDI/TMS/TRST valid after TCK high
su(TDIV-TCKH)
h(TCKH-TDIV)
Table 4−85. Switching Characteristics Over Recommended Operating Conditions for JTAG Test Port
(see Figure 4−67)
−400
−500
−600
NO.
PARAMETER
UNIT
MIN
MAX
2
t
Delay time, TCK low to TDO valid
0
18
ns
d(TCKL-TDOV)
1
TCK
TDO
2
2
4
3
TDI/TMS/TRST
Figure 4−67. JTAG Test-Port Timing
169
June 2003 − Revised October 2005
SPRS222E
Mechanical Data
5
Mechanical Data
The following table(s) show the thermal resistance characteristics for the PBGA − GDK, GNZ, ZDK and ZNZ
mechanical packages.
5.1
Thermal Data
Table 5−1. Thermal Resistance Characteristics (S-PBGA Package) [GDK]
†
NO
°C/W
3.3
Air Flow (m/s )
1
2
RΘ
RΘ
Junction-to-case
Junction-to-board
N/A
N/A
0.00
0.5
JC
7.92
18.2
15.3
13.7
12.2
0.37
0.47
0.57
0.7
JB
3
4
RΘ
Junction-to-free air
Junction-to-package top
Junction-to-board
JA
JT
JB
5
1.0
6
2.00
0.00
0.5
7
8
Psi
Psi
9
1.0
10
11
12
13
14
2.00
0.00
0.5
11.4
11
10.7
10.2
1.0
2.00
†
m/s = meters per second
Table 5−2. Thermal Resistance Characteristics (S-PBGA Package) [ZDK]
†
NO
1
°C/W
Air Flow (m/s )
RΘ
RΘ
Junction-to-case
Junction-to-board
3.3
7.92
18.2
15.3
13.7
12.2
0.37
0.47
0.57
0.7
N/A
N/A
0.00
0.5
JC
2
JB
3
4
RΘ
Junction-to-free air
Junction-to-package top
Junction-to-board
JA
JT
JB
5
1.0
6
2.00
0.00
0.5
7
8
Psi
Psi
9
1.0
10
11
12
13
14
2.00
0.00
0.5
11.4
11
10.7
10.2
1.0
2.00
†
m/s = meters per second
170
SPRS222E
June 2003 − Revised October 2005
Mechanical Data
Table 5−3. Thermal Resistance Characteristics (S-PBGA Package) [GNZ]
†
NO
1
°C/W
Air Flow (m/s )
RΘ
RΘ
Junction-to-case
Junction-to-board
3.3
7.46
17.4
14.0
12.3
10.8
0.37
0.47
0.57
0.7
N/A
N/A
0.00
0.5
JC
2
JB
3
4
RΘ
Junction-to-free air
Junction-to-package top
Junction-to-board
JA
JT
JB
5
1.0
6
2.00
0.00
0.5
7
8
Psi
Psi
9
1.0
10
11
12
13
14
2.00
0.00
0.5
11.4
11
10.7
10.2
1.0
2.00
†
m/s = meters per second
Table 5−4. Thermal Resistance Characteristics (S-PBGA Package) [ZNZ]
†
NO
1
°C/W
Air Flow (m/s )
RΘ
RΘ
Junction-to-case
Junction-to-board
3.3
7.46
17.4
14.0
12.3
10.8
0.37
0.47
0.57
0.7
N/A
N/A
0.00
0.5
JC
2
JB
3
4
RΘ
Junction-to-free air
Junction-to-package top
Junction-to-board
JA
5
1.0
6
2.00
0.00
0.5
7
8
Psi
JT
9
1.0
10
11
12
13
14
2.00
0.00
0.5
11.4
11
Psi
JB
10.7
10.2
1.0
2.00
†
m/s = meters per second
171
June 2003 − Revised October 2005
SPRS222E
Mechanical Data
The following mechanical package diagram(s) reflect the most up-to-date mechanical data released for these
designated device(s).
172
SPRS222E
June 2003 − Revised October 2005
PACKAGE OPTION ADDENDUM
www.ti.com
24-Nov-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Type
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Drawing
GDK
GNZ
GDK
GNZ
GDK
GDK
GNZ
GNZ
ZDK
GDK
GDK
GNZ
GNZ
GDK
GNZ
GDK
GDK
GNZ
GNZ
GDK
GNZ
GDK
GDK
GNZ
GNZ
GDK
GNZ
TMS320DM640AGDK4
TMS320DM640AGNZ4
TMS320DM640GDK400
TMS320DM640GNZ400
TMS320DM641AGDK5
TMS320DM641AGDK6
TMS320DM641AGNZ5
TMS320DM641AGNZ6
TMS320DM641AZDK6
TMS320DM641GDK500
TMS320DM641GDK600
TMS320DM641GNZ500
TMS320DM641GNZ600
TMS320M640AGDK4
TMS320M640AGNZ4
TMS320M641AGDK5
TMS320M641AGDK6
TMS320M641AGNZ5
TMS320M641AGNZ6
TMS320V640AGDK4
TMS320V640AGNZ4
TMS320V641AGDK5
TMS320V641AGDK6
TMS320V641AGNZ5
TMS320V641AGNZ6
TMX320DM641GDK
TMX320DM641GNZ
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
FCBGA
FCBGA
FCBGA
FCBGA
FCBGA
FCBGA
FCBGA
FCBGA
FCBGA
FCBGA
FCBGA
FCBGA
FCBGA
FCBGA
FCBGA
FCBGA
FCBGA
FCBGA
FCBGA
FCBGA
FCBGA
FCBGA
FCBGA
FCBGA
FCBGA
FCBGA
FCBGA
548
548
548
548
548
548
548
548
548
548
548
548
548
548
548
548
548
548
548
548
548
548
548
548
548
548
548
60
40
60
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
SNPB
SNPB
SNPB
Call TI
SNPB
SNPB
SNPB
SNPB
SNAGCU
Call TI
Call TI
Call TI
Call TI
SNPB
SNPB
SNPB
SNPB
SNPB
SNPB
SNPB
SNPB
SNPB
SNPB
SNPB
SNPB
Call TI
Call TI
Level-4-220C-72HR
Level-4-220C-72HR
Level-4-220C-72HR
Call TI
60
60
40
40
60
Level-4-220C-72HR
Level-4-220C-72HR
Level-4-220C-72HR
Level-4-220C-72HR
Level-4-260C-72HR
Call TI
Call TI
Call TI
Call TI
60
40
60
60
40
40
60
40
60
60
40
40
Level-4-220C-72HR
Level-4-220C-72HR
Level-4-220C-72HR
Level-4-220C-72HR
Level-4-220C-72HR
Level-4-220C-72HR
Level-4-220C-72HR
Level-4-220C-72HR
Level-4-220C-72HR
Level-4-220C-72HR
Level-4-220C-72HR
Level-4-220C-72HR
Call TI
Call TI
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS
&
no Sb/Br)
-
please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
24-Nov-2005
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
MECHANICAL DATA
MPBG301 – JULY 2002
GDK (S–PBGA–N548)
PLASTIC BALL GRID ARRAY
23,10
22,90
SQ
SQ
20,00 TYP
21,10
20,90
0,80
0,40
AF
AD
AB
Y
AE
AC
AA
W
U
V
0,80
T
R
P
N
M
K
L
0,40
A1 Corner
J
H
G
F
E
D
C
B
A
1
3
5
7
9
11 13 15 17 19 21 23 25
2
4
6
8
10 12 14 16 18 20 22 24 26
Bottom View
2,80 MAX
0,50 NOM
Seating Plane
0,12
0,55
0,45
0,10
0,45
0,35
4203481-3/B 07/02
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Flip chip application only.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂꢃꢄ ꢅꢆꢂ ꢄꢇ ꢈ ꢄꢉꢄ
MPBG314A – OCTOBER 2002 – REVISED DECEMBER 2002
GNZ (S–PBGA–N548)
PLASTIC BALL GRID ARRAY
27,20
26,80
25,00 TYP
1,00
SQ
SQ
25,20
24,80
0,50
AF
AE
AD
AC
AB
AA
Y
W
V
1,00
U
T
R
P
N
M
L
0,50
K
J
H
A1 Corner
G
F
E
D
C
B
A
1
3
5
7
9
11 13 15 17 19 21 23 25
10 12 14 16 18 20 22 24 26
2
4
6
8
Bottom View
2,80 MAX
0,50 NOM
Seating Plane
0,15
0,70
0,50
0,10
0,60
0,40
4202595-5\E 12/02
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Flip chip application only.
D. Substrate color may vary.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,
enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
orders and should verify that such information is current and complete. All products are sold subject to TI’s terms
and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty. Except where mandated by government requirements, testing of all
parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for
their products and applications using TI components. To minimize the risks associated with customer products
and applications, customers should provide adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,
copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process
in which TI products or services are used. Information published by TI regarding third-party products or services
does not constitute a license from TI to use such products or services or a warranty or endorsement thereof.
Use of such information may require a license from a third party under the patents or other intellectual property
of the third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of information in TI data books or data sheets is permissible only if reproduction is without
alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction
of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for
such altered documentation.
Resale of TI products or services with statements different from or beyond the parameters stated by TI for that
product or service voids all express and any implied warranties for the associated TI product or service and
is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.
Following are URLs where you can obtain information on other Texas Instruments products and application
solutions:
Products
Applications
Audio
Amplifiers
amplifier.ti.com
www.ti.com/audio
Data Converters
dataconverter.ti.com
Automotive
www.ti.com/automotive
DSP
dsp.ti.com
Broadband
Digital Control
Military
www.ti.com/broadband
www.ti.com/digitalcontrol
www.ti.com/military
Interface
Logic
interface.ti.com
logic.ti.com
Power Mgmt
Microcontrollers
power.ti.com
Optical Networking
Security
www.ti.com/opticalnetwork
www.ti.com/security
www.ti.com/telephony
www.ti.com/video
microcontroller.ti.com
Telephony
Video & Imaging
Wireless
www.ti.com/wireless
Mailing Address:
Texas Instruments
Post Office Box 655303 Dallas, Texas 75265
Copyright 2005, Texas Instruments Incorporated
E n te r K e y w o r d
a l l s e a r c h e s
C o n t a c t U s
| T I Wo
T I Ho m e > Se m i co n d u ct o rs > DSP Pl a t f o rm s > T M S3 2 0 C6 0 0 0 ™ Hi g h Pe rf o rm a n ce DSPs > T M S3 2 0 DM 6 4 x DSPs >
T MS 3 2 0 D M6 4 0 , Sta tu s : ACTIVE
Vide o/Im a ging Fix e d- Point Digit a l Signa l Pr oc e s s or
c le a r g if
Ref ine Y our Select ion
- Ge tti n g Sta rte d
F eat ures
Samples
Technical D ocument s
A pplicat ions Not es
Simulat ion Models
Ref erence D esigns
Qualit y & P b-F ree D at a
Relat ed P roduct s
Tools & Sof t ware
P ricing/P ackaging
I nv ent ory
- Se l e cti o n Gu i d e s
- DSP P l a tf o rm s : T M S3 2 0
DSP s
Sy mbols/F oot print s
Support
D at asheet
- Kn o wl e d g e Ba s e
- C o n ta ct T e ch n i ca l Su p p
- T ra i n i n g
T MS 3 2 0 D M6 4 1 / T MS 3 2 0 D M6 4 0 Vi d e o / I m a g i n g F i x e d - P o i n t D i g i t a l S i g n a l
P r o c e s s o r s ( Re v . E ) ( tm s 3 2 0 d m 6 4 0 . p d f , 2 5 3 6 KB)
1 4 O c t 2 0 0 5 D o w n l o a d
- Di s cu s s i o n Gro u p s
- C o n s u l ti n g Se rvi ce s
Do w n lo a d Da t a s h e e t
T MS 3 2 0 D M6 4 1 , T MS 3 2 0 D M6 4 0 D S P s S i l i c o n E r r a t a ( S i l i c o n Re v i s i o n s 2 . 0 , 1 . 2 , 1 . 1 , 1 . 0 ) ( Re v .
Relat ed Block D iagrams
- Di g i ta l Se t T o p Bo x
- Di g i ta l Sti l l C a m e ra
- L C D T V
G ) ( s p rz 2 0 1 g . p d f , 2 0 5 KB)
3 1 A u g 2 0 0 5 D o w n l o a d
- More Block D iagrams
T MS 3 2 0 D M6 4 0 / 1 H a r d wa r e D e s i g n e r ' s Re s o u r c e G u i d e ( Re v . A ) ( s p ra a 5 0 a . h tm , 9 KB)
2 4 O c t 2 0 0 5 A b s tr a c t
TMS320D M640-400
CP U
1 C 6 4 x ; Vi d e o
P eak MMA CS
F requency (MHz)
3 2 0 0
4 0 0
Tot al On-Chip
Memory (KB)
1 6 0
On-Chip L1/SRA M
On-Chip L2/SRA M
EMI F
3 2 KB
1 2 8 KB
1 3 2 - Bi t
Ext ernal Memory
Ty pe Support ed
As yn c SR AM , SDR AM , SBSR AM
D MA
6 4 - C h EDM A
A pplicat ion-Specif ic Vi d e o P o rt, VI C , EM AC
or A nalog I /O
Video P ort
1 8 - Bi t Si n g l e - C h
(Conf igurable)
VI C
1
EMA C
Serial I /O
McBSP
I 2C
1 0 / 1 0 0
M cBSP , M cASP , I 2 C
2
1
McA SP
Timers
1
3 3 2 - Bi t GP
Core Supply (Volt s) 1 . 2 V
I O Supply (Volt s)
3 . 3 V
Operat ing
0 to 9 0
Temperat ure Range
(°C)
Sa m p l e s
I n ve n to ry
P roduct I nf ormat ion
F eat ures
Sav e t his t o y our personal library
Hi g h - P e r f o r m a n c e D i g i ta l M e d i a P r o c e s s o r ( T M S 3 2 0 D M 6 4 1 / T M S 3 2 0 D M 6 4 0 )
2 . 5 - , 2 - , 1 . 6 7 - n s I n s tr u c ti o n C y c l e T i m e
4 0 0 - , 5 0 0 - , 6 0 0 - M Hz C l o c k R a te
E i g h t 3 2 - B i t I n s tr u c ti o n s / C y c l e
3 2 0 0 , 4 0 0 0 , 4 8 0 0 M I P S
Fu l l y S o f tw a r e - C o m p a ti b l e W i th C 6 4 x ™
V e l o c i T I . 2 ™ E x te n s i o n s to V e l o c i T I ™ A d v a n c e d V e r y - L o n g - I n s tr u c ti o n - W o r d ( V L I W )
T M S 3 2 0 C 6 4 x ™ D S P C o r e
E i g h t Hi g h l y I n d e p e n d e n t Fu n c ti o n a l U n i ts W i th V e l o c i T I . 2 ™ E x te n s i o n s :
S i x A L U s ( 3 2 - / 4 0 - B i t) , E a c h S u p p o r ts S i n g l e 3 2 - B i t, D u a l 1 6 - B i t, o r Q u a d 8 - B i t A r i th m e ti c
p e r C l o c k C y c l e
T w o M u l ti p l i e r s S u p p o r t Fo u r 1 6 x 1 6 - B i t M u l ti p l i e s ( 3 2 - B i t R e s u l ts ) p e r C l o c k C y c l e o r E i g h t
8 x 8 - B i t M u l ti p l i e s ( 1 6 - B i t R e s u l ts ) p e r C l o c k C y c l e
L o a d - S to r e A r c h i te c tu r e W i th N o n - A l i g n e d S u p p o r t
6 4 3 2 - B i t G e n e r a l - P u r p o s e R e g i s te r s
I n s tr u c ti o n P a c k i n g R e d u c e s C o d e S i z e
A l l I n s tr u c ti o n s C o n d i ti o n a l
I n s tr u c ti o n S e t Fe a tu r e s
B y te - A d d r e s s a b l e ( 8 - / 1 6 - / 3 2 - / 6 4 - B i t D a ta )
8 - B i t O v e r f l o w P r o te c ti o n
B i t- Fi e l d E x tr a c t, S e t, C l e a r
N o r m a l i z a ti o n , S a tu r a ti o n , B i t- C o u n ti n g
V e l o c i T I . 2 ™ I n c r e a s e d O r th o g o n a l i ty
L 1 / L 2 M e m o r y A r c h i te c tu r e
1 2 8 K - B i t ( 1 6 K - B y te ) L 1 P P r o g r a m C a c h e ( D i r e c t M a p p e d )
1 2 8 K - B i t ( 1 6 K - B y te ) L 1 D D a ta C a c h e ( 2 - W a y S e t- A s s o c i a ti v e )
1 M - B i t ( 1 2 8 K - B y te ) L 2 U n i f i e d M a p p e d R A M / C a c h e ( Fl e x i b l e R A M / C a c h e A l l o c a ti o n )
E n d i a n e s s : L i ttl e E n d i a n , B i g E n d i a n
3 2 - B i t E x te r n a l M e m o r y I n te r f a c e ( E M I F)
G l u e l e s s I n te r f a c e to A s y n c h r o n o u s M e m o r i e s ( S R A M a n d E P R O M ) a n d S y n c h r o n o u s M e m o r i e s
( S D R A M , S B S R A M , Z B T S R A M , a n d FI FO )
1 0 2 4 M - B y te T o ta l A d d r e s s a b l e E x te r n a l M e m o r y S p a c e
E n h a n c e d D i r e c t- M e m o r y - A c c e s s ( E D M A ) C o n tr o l l e r ( 6 4 I n d e p e n d e n t C h a n n e l s )
1 0 / 1 0 0 M b / s E th e r n e t M A C ( E M A C )
I E E E 8 0 2 . 3 C o m p l i a n t
M e d i a I n d e p e n d e n t I n te r f a c e ( M I I )
8 I n d e p e n d e n t T r a n s m i t ( T X ) a n d 1 R e c e i v e ( R X ) C h a n n e l
M a n a g e m e n t D a ta I n p u t/ O u tp u t ( M D I O )
T w o C o n f i g u r a b l e V i d e o P o r ts ( D M 6 4 1 )
O n e C o n f i g u r a b l e V i d e o P o r t ( D M 6 4 0 )
P r o v i d i n g a G l u e l e s s I / F to C o m m o n V i d e o D e c o d e r a n d E n c o d e r D e v i c e s
S u p p o r ts M u l ti p l e R e s o l u ti o n s a n d V i d e o S ta n d a r d s
V C X O I n te r p o l a te d C o n tr o l P o r t ( V I C )
S u p p o r ts A u d i o / V i d e o S y n c h r o n i z a ti o n
Ho s t- P o r t I n te r f a c e ( HP I ) [ 1 6 - B i t] ( D M 6 4 1 )
M u l ti c h a n n e l A u d i o S e r i a l P o r t ( M c A S P )
Fo u r S e r i a l D a ta P i n s
W i d e V a r i e ty o f I 2 S a n d S i m i l a r B i t S tr e a m Fo r m a t
I n te g r a te d D i g i ta l A u d i o I / F T r a n s m i tte r S u p p o r ts S / P D I F, I E C 6 0 9 5 8 - 1 , A E S - 3 , C P - 4 3 0
Fo r m a ts
2
I n te r - I n te g r a te d C i r c u i t ( I C ) B u s
T w o M u l ti c h a n n e l B u f f e r e d S e r i a l P o r ts
T h r e e 3 2 - B i t G e n e r a l - P u r p o s e T i m e r s
E i g h t G e n e r a l - P u r p o s e I / O ( G P I O ) P i n s
Fl e x i b l e P L L C l o c k G e n e r a to r
I E E E - 1 1 4 9 . 1 ( J T A G ) B o u n d a r y - S c a n - C o m p a ti b l e
5 4 8 - P i n B a l l G r i d A r r a y ( B G A ) P a c k a g e ( G D K a n d Z D K S u f f i x e s ) , 0 . 8 - m m B a l l P i tc h
5 4 8 - P i n B a l l G r i d A r r a y ( B G A ) P a c k a g e ( G N Z a n d Z N Z S u f f i x e s ) , 1 . 0 - m m B a l l P i tc h
0 . 1 3 - µ m / 6 - L e v e l C u M e ta l P r o c e s s ( C M O S )
3 . 3 - V I / O s , 1 . 2 - V I n te r n a l ( - 4 0 0 , - 5 0 0 )
3 . 3 - V I / O s , 1 . 4 - V I n te r n a l ( - 6 0 0 )
C 64x , Ve lo ciT I. 2, Ve lo ciT I, a nd T M S320C 64x a re tra d e m a rk s o f T e x a s Instrum e nts.
All tra d e m a rk s a re the p ro p e rty o f the ir re sp e ctiv e o w ne rs.
IEEE Sta nd a rd 1149. 1- 1990 Sta nd a rd - T e st- Acce ss P o rt a nd Bo und a ry Sca n Archite cture .
T M S320C 6000 a nd C 6000 a re tra d e m a rk s o f T e x a s Instrum e nts.
W ind o w s is a re g iste re d tra d e m a rk o f the M icro so f t C o rp o ra tio n.
D escript ion
T h e T M S 3 2 0 C 6 4 x ™ D S P s ( i n c l u d i n g th e T M S 3 2 0 D M 6 4 1 a n d T M S 3 2 0 D M 6 4 0 d e v i c e s ) a r e th e h i g h e s t-
p e r f o r m a n c e f i x e d - p o i n t D S P g e n e r a ti o n i n th e T M S 3 2 0 C 6 0 0 0 ™ D S P p l a tf o r m . T h e T M S 3 2 0 D M 6 4 1
( D M 6 4 1 ) a n d T M S 3 2 0 D M 6 4 0 ( D M 6 4 0 ) d e v i c e s a r e b a s e d o n th e s e c o n d - g e n e r a ti o n h i g h - p e r f o r m a n c e ,
a d v a n c e d V e l o c i T I ™ v e r y - l o n g - i n s tr u c ti o n - w o r d ( V L I W ) a r c h i te c tu r e ( V e l o c i T I . 2 ™ ) d e v e l o p e d b y T e x a s
I n s tr u m e n ts ( T I ) , m a k i n g th e s e D S P s a n e x c e l l e n t c h o i c e f o r d i g i ta l m e d i a a p p l i c a ti o n s . T h e C 6 4 x ™ i s a
c o d e - c o m p a ti b l e m e m b e r o f th e C 6 0 0 0 ™ D S P p l a tf o r m .
W i th p e r f o r m a n c e o f u p to 4 8 0 0 m i l l i o n i n s tr u c ti o n s p e r s e c o n d ( M I P S ) a t a c l o c k r a te o f 6 0 0 M Hz , th e
D M 6 4 1 d e v i c e o f f e r s c o s t- e f f e c ti v e s o l u ti o n s to h i g h - p e r f o r m a n c e D S P p r o g r a m m i n g c h a l l e n g e s .
W i th p e r f o r m a n c e o f u p to 3 2 0 0 m i l l i o n i n s tr u c ti o n s p e r s e c o n d ( M I P S ) a t a c l o c k r a te o f 4 0 0 M Hz , th e
D M 6 4 0 d e v i c e o f f e r s c o s t- e f f e c ti v e s o l u ti o n s to h i g h - p e r f o r m a n c e D S P p r o g r a m m i n g c h a l l e n g e s .
T h e D M 6 4 1 / D M 6 4 0 D S P p o s s e s s e s th e o p e r a ti o n a l f l e x i b i l i ty o f h i g h - s p e e d c o n tr o l l e r s a n d th e n u m e r i c a l
c a p a b i l i ty o f a r r a y p r o c e s s o r s . T h e C 6 4 x ™ D S P c o r e p r o c e s s o r h a s 6 4 g e n e r a l - p u r p o s e r e g i s te r s o f 3 2 -
b i t w o r d l e n g th a n d e i g h t h i g h l y i n d e p e n d e n t f u n c ti o n a l u n i ts — tw o m u l ti p l i e r s f o r a 3 2 - b i t r e s u l t a n d s i x
a r i th m e ti c l o g i c u n i ts ( A L U s ) — w i th V e l o c i T I . 2 ™ e x te n s i o n s . T h e V e l o c i T I . 2 ™ e x te n s i o n s i n th e e i g h t
f u n c ti o n a l u n i ts i n c l u d e n e w i n s tr u c ti o n s to a c c e l e r a te th e p e r f o r m a n c e i n v i d e o a n d i m a g i n g a p p l i c a ti o n s
a n d e x te n d th e p a r a l l e l i s m o f th e V e l o c i T I ™ a r c h i te c tu r e . T h e D M 6 4 1 c a n p r o d u c e f o u r 1 6 - b i t m u l ti p l y -
a c c u m u l a te s ( M A C s ) p e r c y c l e f o r a to ta l o f 2 4 0 0 m i l l i o n M A C s p e r s e c o n d ( M M A C S ) , o r e i g h t 8 - b i t M A C s
p e r c y c l e f o r a to ta l o f 4 8 0 0 M M A C S . T h e D M 6 4 0 c a n p r o d u c e f o u r 1 6 - b i t m u l ti p l y - a c c u m u l a te s ( M A C s )
p e r c y c l e f o r a to ta l o f 1 6 0 0 m i l l i o n M A C s p e r s e c o n d ( M M A C S ) , o r e i g h t 8 - b i t M A C s p e r c y c l e f o r a to ta l
o f 3 2 0 0 M M A C S . T h e D M 6 4 1 / D M 6 4 0 D S P a l s o h a s a p p l i c a ti o n - s p e c i f i c h a r d w a r e l o g i c , o n - c h i p m e m o r y ,
a n d a d d i ti o n a l o n - c h i p p e r i p h e r a l s s i m i l a r to th e o th e r C 6 0 0 0 ™ D S P p l a tf o r m d e v i c e s .
T h e D M 6 4 1 / D M 6 4 0 u s e s a tw o - l e v e l c a c h e - b a s e d a r c h i te c tu r e a n d h a s a p o w e r f u l a n d d i v e r s e s e t o f
p e r i p h e r a l s . T h e L e v e l 1 p r o g r a m c a c h e ( L 1 P ) i s a 1 2 8 - K b i t d i r e c t m a p p e d c a c h e a n d th e L e v e l 1 d a ta
c a c h e ( L 1 D ) i s a 1 2 8 - K b i t 2 - w a y s e t- a s s o c i a ti v e c a c h e . T h e L e v e l 2 m e m o r y / c a c h e ( L 2 ) c o n s i s ts o f a n 1 -
M b i t m e m o r y s p a c e th a t i s s h a r e d b e tw e e n p r o g r a m a n d d a ta s p a c e . L 2 m e m o r y c a n b e c o n f i g u r e d a s
m a p p e d m e m o r y , c a c h e , o r c o m b i n a ti o n s o f th e tw o . T h e p e r i p h e r a l s e t i n c l u d e s : tw o c o n f i g u r a b l e v i d e o
p o r ts ( D M 6 4 1 ) ; o n e c o n f i g u r a b l e v i d e o p o r t ( D M 6 4 0 ) ; a 1 0 / 1 0 0 M b / s E th e r n e t M A C ( E M A C ) ; a
m a n a g e m e n t d a ta i n p u t/ o u tp u t ( M D I O ) m o d u l e ; a V C X O i n te r p o l a te d c o n tr o l p o r t ( V I C ) ; o n e 4 - b i t
m u l ti c h a n n e l b u f f e r e d a u d i o s e r i a l p o r t ( M c A S P 0 ) ; a n i n te r - i n te g r a te d c i r c u i t ( I 2 C ) B u s m o d u l e ; tw o
m u l ti c h a n n e l b u f f e r e d s e r i a l p o r ts ( M c B S P s ) ; th r e e 3 2 - b i t g e n e r a l - p u r p o s e ti m e r s ; a 1 6 - b i t h o s t- p o r t
i n te r f a c e ( HP I 1 6 ) ; a 8 - p i n g e n e r a l - p u r p o s e i n p u t/ o u tp u t p o r t ( G P 0 ) w i th p r o g r a m m a b l e i n te r r u p t/ e v e n t
g e n e r a ti o n m o d e s ; a n d a 3 2 - b i t g l u e l e s s e x te r n a l m e m o r y i n te r f a c e ( E M I FA ) , w h i c h i s c a p a b l e o f
i n te r f a c i n g to s y n c h r o n o u s a n d a s y n c h r o n o u s m e m o r i e s a n d p e r i p h e r a l s .
T h e D M 6 4 1 d e v i c e h a s tw o s i n g l e - c h a n n e l 8 - b i t c o n f i g u r a b l e v i d e o p o r t p e r i p h e r a l s ( V P 0 a n d V P 1 ) . T h e
D M 6 4 0 d e v i c e h a s o n e s i n g l e - c h a n n e l 8 - b i t c o n f i g u r a b l e v i d e o p o r t p e r i p h e r a l ( V P 0 ) . T h e s e v i d e o p o r t
p e r i p h e r a l s p r o v i d e a g l u e l e s s i n te r f a c e to c o m m o n v i d e o d e c o d e r a n d e n c o d e r d e v i c e s . T h e
D M 6 4 1 / D M 6 4 0 v i d e o p o r t p e r i p h e r a l s s u p p o r t m u l ti p l e r e s o l u ti o n s a n d v i d e o s ta n d a r d s ( e . g . , C C I R 6 0 1
a n d I T U – ) .
T h e s e v i d e o p o r t p e r i p h e r a l s a r e c o n f i g u r a b l e a n d c a n s u p p o r t e i th e r v i d e o c a p tu r e a n d / o r v i d e o d i s p l a y
m o d e s .
Fo r m o r e d e ta i l s o n th e V i d e o P o r t p e r i p h e r a l s , s e e th e T M S3 2 0 C 6 4 x DSP V i d e o P o r t/ V C X O I n te r p o l a te d
C o n tr o l ( V I C ) P o r t R e f e r e n c e G u i d e ( l i te r a tu r e n u m b e r S P R U 6 2 9 ) .
T h e M c A S P 0 p o r t s u p p o r ts o n e tr a n s m i t a n d o n e r e c e i v e c l o c k z o n e , w i th f o u r s e r i a l d a ta p i n s w h i c h c a n
b e i n d i v i d u a l l y a l l o c a te d to a n y o f th e tw o z o n e s . T h e s e r i a l p o r t s u p p o r ts ti m e - d i v i s i o n m u l ti p l e x i n g o n
e a c h p i n f r o m 2 to 3 2 ti m e s l o ts . T h e D M 6 4 1 / D M 6 4 0 h a s s u f f i c i e n t b a n d w i d th to s u p p o r t a l l 4 s e r i a l d a ta
p i n s tr a n s m i tti n g a 1 9 2 - k Hz s te r e o s i g n a l . S e r i a l d a ta i n e a c h z o n e m a y b e tr a n s m i tte d a n d r e c e i v e d o n
m u l ti p l e s e r i a l d a ta p i n s s i m u l ta n e o u s l y a n d f o r m a tte d i n a m u l ti tu d e o f v a r i a ti o n s o n th e P h i l i p s I n te r - I C
2
S o u n d ( I S ) f o r m a t.
I n a d d i ti o n , th e M c A S P 0 tr a n s m i tte r m a y b e p r o g r a m m e d to o u tp u t m u l ti p l e S / P D I F, I E C 6 0 9 5 8 , A E S - 3 ,
C P - 4 3 0 e n c o d e d d a ta c h a n n e l s s i m u l ta n e o u s l y , w i th a s i n g l e R A M c o n ta i n i n g th e f u l l i m p l e m e n ta ti o n o f
u s e r d a ta a n d c h a n n e l s ta tu s f i e l d s .
M c A S P 0 a l s o p r o v i d e s e x te n s i v e e r r o r - c h e c k i n g a n d r e c o v e r y f e a tu r e s , s u c h a s th e b a d c l o c k d e te c ti o n
c i r c u i t f o r e a c h h i g h - f r e q u e n c y m a s te r c l o c k w h i c h v e r i f i e s th a t th e m a s te r c l o c k i s w i th i n a p r o g r a m m e d
f r e q u e n c y r a n g e .
T h e V C X O i n te r p o l a te d c o n tr o l ( V I C ) p o r t p r o v i d e s d i g i ta l - to - a n a l o g c o n v e r s i o n w i th r e s o l u ti o n f r o m 9 -
b i ts to u p to 1 6 - b i ts . T h e o u tp u t o f th e V I C i s a s i n g l e b i t i n te r p o l a te d D / A o u tp u t. Fo r m o r e d e ta i l s o n th e
V I C p o r t, s e e th e T M S3 2 0 C 6 4 x DSP V i d e o P o r t/ V C X O I n te r p o l a te d C o n tr o l ( V I C ) P o r t R e f e r e n c e G u i d e
( l i te r a tu r e n u m b e r S P R U 6 2 9 ) .
T h e e th e r n e t m e d i a a c c e s s c o n tr o l l e r ( E M A C ) p r o v i d e s a n e f f i c i e n t i n te r f a c e b e tw e e n th e D M 6 4 1 / D M 6 4 0
D S P c o r e p r o c e s s o r a n d th e n e tw o r k . T h e D M 6 4 1 / D M 6 4 0 E M A C s u p p o r ts b o th 1 0 B a s e - T a n d 1 0 0 B a s e - T X ,
o r 1 0 M b i ts / s e c o n d ( M b p s ) a n d 1 0 0 M b p s i n e i th e r h a l f - o r f u l l - d u p l e x , w i th h a r d w a r e f l o w c o n tr o l a n d
q u a l i ty o f s e r v i c e ( Q O S ) s u p p o r t. T h e D M 6 4 1 / D M 6 4 0 E M A C m a k e s u s e o f a c u s to m i n te r f a c e to th e D S P
c o r e th a t a l l o w s e f f i c i e n t d a ta tr a n s m i s s i o n a n d r e c e p ti o n . Fo r m o r e d e ta i l s o n th e E M A C , s e e th e
T M S3 2 0 C 6 0 0 0 DSP E th e r n e t M e d i a A c c e s s C o n tr o l l e r ( E M A C ) / M a n a g e m e n t Da ta I n p u t/ O u tp u t ( M DI O )
M o d u l e R e f e r e n c e G u i d e ( l i te r a tu r e n u m b e r S P R U 6 2 8 ) .
T h e m a n a g e m e n t d a ta i n p u t/ o u tp u t ( M D I O ) m o d u l e c o n ti n u o u s l y p o l l s a l l 3 2 M D I O a d d r e s s e s i n o r d e r to
e n u m e r a te a l l P HY d e v i c e s i n th e s y s te m . O n c e a P HY c a n d i d a te h a s b e e n s e l e c te d b y th e D S P , th e M D I O
m o d u l e tr a n s p a r e n tl y m o n i to r s i ts l i n k s ta te b y r e a d i n g th e P HY s ta tu s r e g i s te r . L i n k c h a n g e e v e n ts a r e
s to r e d i n th e M D I O m o d u l e a n d c a n o p ti o n a l l y i n te r r u p t th e D S P , a l l o w i n g th e D S P to p o l l th e l i n k s ta tu s
o f th e d e v i c e w i th o u t c o n ti n u o u s l y p e r f o r m i n g c o s tl y M D I O a c c e s s e s . Fo r m o r e d e ta i l s o n th e M D I O , s e e
th e T M S3 2 0 C 6 0 0 0 DSP E th e r n e t M e d i a A c c e s s C o n tr o l l e r ( E M A C ) / M a n a g e m e n t Da ta I n p u t/ O u tp u t ( M DI O )
M o d u l e R e f e r e n c e G u i d e ( l i te r a tu r e n u m b e r S P R U 6 2 8 ) .
T h e I 2 C 0 p o r t o n th e T M S 3 2 0 D M 6 4 1 / D M 6 4 0 a l l o w s th e D S P to e a s i l y c o n tr o l p e r i p h e r a l d e v i c e s a n d
c o m m u n i c a te w i th a h o s t p r o c e s s o r . I n a d d i ti o n , th e s ta n d a r d m u l ti c h a n n e l b u f f e r e d s e r i a l p o r t ( M c B S P )
m a y b e u s e d to c o m m u n i c a te w i th s e r i a l p e r i p h e r a l i n te r f a c e ( S P I ) m o d e p e r i p h e r a l d e v i c e s .
T h e D M 6 4 1 / D M 6 4 0 h a s a c o m p l e te s e t o f d e v e l o p m e n t to o l s w h i c h i n c l u d e s : a n e w C c o m p i l e r , a n
a s s e m b l y o p ti m i z e r to s i m p l i f y p r o g r a m m i n g a n d s c h e d u l i n g , a n d a W i n d o w s ™ d e b u g g e r i n te r f a c e f o r
v i s i b i l i ty i n to s o u r c e c o d e e x e c u ti o n .
P ricing/P ackaging/CA D D esign Tools/Samples
P rice
P ackaging
CA D D esign Tools
Samples
I ndust ry
Budget P rice St andard (TI
($US) | QTY P kg) | P ins
St andard P ack
Quant it y
D ev ice
St at us
Sy mbols
F oot print s
Samples
T M S3 2 0 DM 6 4 0 AGDK4 AC T I VE
T M S3 2 0 DM 6 4 0 AGNZ4 AC T I VE
T M S3 2 0 DM 6 4 0 GDK4 0 0 AC T I VE
2 2 . 5 4 | 1 KU FC BGA ( GDK) | 6 0
5 4 8
P u rch a s e
Sa m p l e s
2 2 . 5 4 | 1 KU FC BGA ( GNZ) | 4 0
5 4 8
P u rch a s e
Sa m p l e s
2 2 . 5 4 | 1 KU FC BGA ( GDK) | 6 0
5 4 8
C o n ta ct T I
Di s tri b u to r o r
Sa l e s O f f i ce
T M S3 2 0 DM 6 4 0 GNZ4 0 0 AC T I VE
FC BGA ( GNZ) |
5 4 8
P u rch a s e
Sa m p l e s
T M S3 2 0 M 6 4 0 AGDK4
T M S3 2 0 M 6 4 0 AGNZ4
T M S3 2 0 V6 4 0 AGDK4
T M S3 2 0 V6 4 0 AGNZ4
AC T I VE
AC T I VE
AC T I VE
AC T I VE
2 2 . 5 4 | 1 KU FC BGA ( GDK) | 6 0
5 4 8
P u rch a s e
Sa m p l e s
2 2 . 5 4 | 1 KU FC BGA ( GNZ) | 4 0
5 4 8
P u rch a s e
Sa m p l e s
2 2 . 5 4 | 1 KU FC BGA ( GDK) | 6 0
5 4 8
P u rch a s e
Sa m p l e s
2 2 . 5 4 | 1 KU FC BGA ( GNZ) | 4 0
5 4 8
P u rch a s e
Sa m p l e s
I nv ent ory
TI I nv ent ory St at us
Report ed D ist ribut or I nv ent ory
As o f 8 : 4 6 AM GM T , 2 9 No v 2 0 0 5
I n
V i e w a l l D i s tr i b u to r s
C h o o s e a R e g i o n
As o f 8 : 4 6 AM GM T , 2 9 No v
2 0 0 5
TMS320D M640A GD K4
I n
I n P rogress Lead
St ock QTY | D at e Time
Region Company
P urchase
St ock
0 *
>1 0 k | 6
Fe b
1 2
W e e k s
No n e R e p o rte d
Vi e w Di s tri b u to rs
As o f 8 : 4 6 AM GM T , 2 9 No v
2 0 0 5
TMS320D M640A GNZ4
TMS320D M640GD K400
As o f 8 : 4 6 AM GM T , 2 9 No v 2 0 0 5
I n
I n P rogress Lead
I n
St ock
Region Company
P urchase
St ock QTY | D at e Time
0 *
>1 0 k | 4
J a n
6 W e e k s No n e R e p o rte d
Vi e w Di s tri b u to rs
As o f 8 : 4 6 AM GM T , 2 9 No v
2 0 0 5
As o f 8 : 4 6 AM GM T , 2 9 No v 2 0 0 5
I n
I n P rogress Lead
I n
St ock
Region Company
P urchase
St ock QTY | D at e Time
0 *
1 2 +
Am e ri ca s Di g i Ke y
1 2 0
W e e k s
Eu ro p e
Avn e t-
SI L I C A
1 0
As o f 8 : 4 6 AM GM T , 2 9 No v
2 0 0 5
TMS320D M640GNZ400
As o f 8 : 4 6 AM GM T , 2 9 No v 2 0 0 5
I n
I n P rogress Lead
I n
St ock
Region Company
P urchase
St ock QTY | D at e Time
0 *
C a l l * *
Am e ri ca s Avn e t
Di g i Ke y
1 9 0
1 9 4
1 8
Eu ro p e
Sp o e rl e
As o f 8 : 4 6 AM GM T , 2 9 No v
2 0 0 5
TMS320M640A GD K4
TMS320M640A GNZ4
TMS320V640A GD K4
As o f 8 : 4 6 AM GM T , 2 9 No v 2 0 0 5
I
n
I
n
P
r
o
g
r
e
s
s
L
e
a
d
I n
St ock
R
e
g
i
o
n
C
o
m
p
a
n
y
P
u
r
c
h
a
s
e
S
t
o
c
k
Q
T
Y
|
D
a
t
e
T
i
m
e
0
*
>1 0 k | 6
Fe b
1 2
W e e k s
No n e R e p o rte d
Vi e w Di s tri b u to rs
As o f 8 : 4 6 AM GM T , 2 9 No v
2 0 0 5
As o f 8 : 4 6 AM GM T , 2 9 No v 2 0 0 5
I n
I n P rogress Lead
I n
St ock
Region Company
P urchase
St ock QTY | D at e Time
0 *
>1 0 k | 4
J a n
6 W e e k s No n e R e p o rte d
Vi e w Di s tri b u to rs
As o f 8 : 4 6 AM GM T , 2 9 No v
2 0 0 5
As o f 8 : 4 6 AM GM T , 2 9 No v 2 0 0 5
I n
I n P rogress Lead
I n
St ock
Region Company
P urchase
St ock QTY | D at e Time
0 *
>1 0 k | 6
Fe b
1 2
W e e k s
No n e R e p o rte d
Vi e w Di s tri b u to rs
As o f 8 : 4 6 AM GM T , 2 9 No v
2 0 0 5
TMS320V640A GNZ4
As o f 8 : 4 6 AM GM T , 2 9 No v 2 0 0 5
I n
I n P rogress Lead
I n
St ock
Region Company
P urchase
St ock QTY | D at e Time
0 *
>1 0 k | 4
J a n
6 W e e k s No n e R e p o rte d
Vi e w Di s tri b u to rs
* O u r i n f o r m a ti o n i s u p d a te d d a i l y , s o p l e a s e c h e c k b a c k w i th u s * * L e a d ti m e i n f o r m a ti o n i s n o t a v a i l a b l e a t th i s ti m e . Ho w e v e r ,
s o o n i f th i s d o e s n o t m e e t y o u r n e e d s . Y o u m a y a l s o c o n ta c t
y o u r T I A u th o r i z e d D i s tr i b u to r , i n c l u d i n g th o s e l i s te d a b o v e , f o r
r e a l ti m e s to c k i n f o r m a ti o n .
o u r i n f o r m a ti o n i s u p d a te d d a i l y s o p l e a s e c h e c k b a c k w i th u s
s o o n . P l e a s e c o n ta c t y o u r p r e f e r r e d T I A u th o r i z e d D i s tr i b u to r f o r
a d d i ti o n a l i n f o r m a ti o n .
Qualit y & Lead (P b)-F ree D at a
P roduct Cont ent
MTBF /F I T Rat e
D et ails
D ev ice
Eco P lan*
T BD
Lead/Ball F inish
SNP B
MSL Rat ing/P eak Ref low D et ails
T M S3 2 0 DM 6 4 0 AGDK4
T M S3 2 0 DM 6 4 0 AGNZ4
T M S3 2 0 DM 6 4 0 GDK4 0 0
T M S3 2 0 DM 6 4 0 GNZ4 0 0
T M S3 2 0 M 6 4 0 AGDK4
T M S3 2 0 M 6 4 0 AGNZ4
T M S3 2 0 V6 4 0 AGDK4
T M S3 2 0 V6 4 0 AGNZ4
L e ve l - 4 - 2 2 0 C - 7 2 HR
L e ve l - 4 - 2 2 0 C - 7 2 HR
L e ve l - 4 - 2 2 0 C - 7 2 HR
Vi e w
Vi e w
Vi e w
Vi e w
Vi e w
Vi e w
Vi e w
Vi e w
Vi e w
Vi e w
Vi e w
T BD
SNP B
T BD
SNP B
T BD
T BD
T BD
T BD
SNP B
SNP B
SNP B
SNP B
L e ve l - 4 - 2 2 0 C - 7 2 HR
L e ve l - 4 - 2 2 0 C - 7 2 HR
L e ve l - 4 - 2 2 0 C - 7 2 HR
L e ve l - 4 - 2 2 0 C - 7 2 HR
Vi e w
Vi e w
Vi e w
Vi e w
* T h e p l a n n e d e c o - f r i e n d l y c l a s s i f i c a ti o n : P b - Fr e e ( R o HS ) o r
G r e e n ( R o HS & n o S b / B r ) - p l e a s e c l i c k o n th e P r o d u c t C o n te n t
D e ta i l s " V i e w " l i n k i n th e ta b l e a b o v e f o r th e l a te s t a v a i l a b i l i ty
i n f o r m a ti o n a n d a d d i ti o n a l p r o d u c t c o n te n t d e ta i l s .
I f th e i n f o r m a ti o n y o u a r e r e q u e s ti n g i s n o t a v a i l a b l e o n l i n e a t
th i s ti m e , c o n ta c t o n e o f o u r P r o d u c t I n f o r m a ti o n C e n te r s
r e g a r d i n g th e a v a i l a b i l i ty o f th i s i n f o r m a ti o n .
Technical D ocument s
D at asheet s
Keep t rack of what 's new
T MS 3 2 0 D M6 4 1 / T MS 3 2 0 D M6 4 0 Vi d e o / I m a g i n g F i x e d - P o i n t D i g i t a l S i g n a l P r o c e s s o r s ( Re v . E ) ( tm s 3 2 0 d m 6 4 0 . p d f , 2 5 3 6
KB)
1 4 O c t 2 0 0 5 D o w n l o a d
T MS 3 2 0 D M6 4 1 , T MS 3 2 0 D M6 4 0 D S P s S i l i c o n E r r a t a ( S i l i c o n Re v i s i o n s 2 . 0 , 1 . 2 , 1 . 1 , 1 . 0 ) ( Re v . G ) ( s p rz 2 0 1 g . p d f , 2 0 5 KB)
3 1 A u g 2 0 0 5 D o w n l o a d
A pplicat ion Not es
T MS 3 2 0 D M6 4 0 / 1 H a r d wa r e D e s i g n e r ' s Re s o u r c e G u i d e ( Re v . A ) ( s p ra a 5 0 a . h tm , 9 KB)
2 4 O c t 2 0 0 5 A b s tr a c t
T MS 3 2 0 C 6 4 x t o T MS 3 2 0 C 6 4 x + C P U Mi g r a t i o n G u i d e ( Re v . A ) ( s p ra a 8 4 a . h tm , 9 KB)
2 0 O c t 2 0 0 5 A b s tr a c t
T MS 3 2 0 D M6 4 x P o we r C o n s u m p t i o n S u m m a r y ( Re v . F ) ( s p ra 9 6 2 f . h tm , 1 0 KB)
1 8 Fe b 2 0 0 5 A b s tr a c t
U s e a n d H a n d l i n g o f S e m i c o n d u c t o r P a c k a g e s Wi t h E NI G P a d F i n i s h e s ( s p ra a 5 5 . h tm , 8 KB)
3 1 A u g 2 0 0 4 A b s tr a c t
T MS 3 2 0 C 6 0 0 0 Mc BS P : U A RT ( Re v . B) ( s p ra 6 3 3 b . h tm , 9 KB)
2 0 M a y 2 0 0 4 A b s tr a c t
I n t e r f a c i n g a n L C D C o n t r o l l e r t o a D M6 4 2 Vi d e o P o r t ( Re v . B) ( s p ra 9 7 5 b . h tm , 1 0 KB)
0 3 M a y 2 0 0 4 A b s tr a c t
H i g h Re s o l u t i o n Vi d e o U s i n g t h e D M6 4 2 D S P a n d t h e T H S 8 2 0 0 D r i v e r ( Re v . A ) ( s p ra 9 6 1 a . h tm , 1 0 KB)
0 3 M a y 2 0 0 4 A b s tr a c t
T MS 3 2 0 C 6 0 0 0 T o o l s : Ve c t o r T a b l e a n d Bo o t ROM C r e a t i o n ( Re v . D ) ( s p ra 5 4 4 d . h tm , 9 KB)
2 6 A p r 2 0 0 4 A b s tr a c t
T MS 3 2 0 C 6 0 0 0 Bo a r d D e s i g n : C o n s i d e r a t i o n s f o r D e b u g ( Re v . C ) ( s p ra 5 2 3 c. h tm , 8 KB)
2 1 A p r 2 0 0 4 A b s tr a c t
T MS 3 2 0 C 6 0 0 0 E MI F - t o - E x t e r n a l S D RA M I n t e r f a c e ( Re v . D ) ( s p ra 4 3 3 d . h tm , 9 KB)
3 1 M a r 2 0 0 4 A b s tr a c t
T MS 3 2 0 C 6 0 0 0 Mc BS P I n i t i a l i z a t i o n ( Re v . C ) ( s p ra 4 8 8 c. h tm , 9 KB)
0 8 M a r 2 0 0 4 A b s tr a c t
T MS 3 2 0 C 6 0 0 0 E D MA I O S c h e d u l i n g a n d P e r f o r m a n c e ( s p ra a 0 0 . h tm , 9 KB)
0 5 M a r 2 0 0 4 A b s tr a c t
U s i n g I BI S Mo d e l s f o r T i m i n g A n a l y s i s ( Re v . A ) ( s p ra 8 3 9 a . h tm , 9 KB)
1 5 A p r 2 0 0 3 A b s tr a c t
T MS 3 2 0 C 6 0 0 0 Mc BS P I n t e r f a c e t o a n S T - BU S D e v i c e ( Re v . B) ( s p ra 5 1 1 b . h tm , 9 KB)
0 4 J u n 2 0 0 2 A b s tr a c t
T MS 3 2 0 C 6 0 0 0 H P I t o P C I I n t e r f a c i n g U s i n g t h e P L X P C I 9 0 5 0 ( Re v . C ) ( s p ra 5 3 7 c. h tm , 9 KB)
1 7 A p r 2 0 0 2 A b s tr a c t
T MS 3 2 0 C 6 0 0 0 Bo a r d D e s i g n f o r J T A G ( Re v . C ) ( s p ra 5 8 4 c. h tm , 9 KB)
0 2 A p r 2 0 0 2 A b s tr a c t
T MS 3 2 0 C 6 0 0 0 E MI F t o E x t e r n a l F l a s h Me m o r y ( Re v . A ) ( s p ra 5 6 8 a . h tm , 9 KB)
1 3 Fe b 2 0 0 2 A b s tr a c t
C a c h e U s a g e i n H i g h - P e r f o r m a n c e D S P A p p l i c a t i o n s wi t h t h e T MS 3 2 0 C 6 4 x ( s p ra 7 5 6 . h tm , 1 0 KB)
1 3 D e c 2 0 0 1 A b s tr a c t
U s i n g a T MS 3 2 0 C 6 0 0 0 Mc BS P f o r D a t a P a c k i n g ( Re v . A ) ( s p ra 5 5 1 a . h tm , 9 KB)
3 1 O c t 2 0 0 1 A b s tr a c t
T MS 3 2 0 C 6 0 0 0 E n h a n c e d D MA : E x a m p l e A p p l i c a t i o n s ( Re v . A ) ( s p ra 6 3 6 a . h tm , 1 0 KB)
2 4 O c t 2 0 0 1 A b s tr a c t
I n t e r f a c i n g t h e T MS 3 2 0 C 6 0 0 0 E MI F t o a P C I Bu s U s i n g t h e A MC C S 5 9 3 3 P C I C o n t r o l l e r ( Re v . A ) ( s p ra 4 7 9 a . h tm , 9 KB)
3 0 S e p 2 0 0 1 A b s tr a c t
T MS 3 2 0 C 6 0 0 0 H o s t P o r t t o MC 6 8 3 6 0 I n t e r f a c e ( Re v . A ) ( s p ra 5 4 5 a . h tm , 9 KB)
3 0 S e p 2 0 0 1 A b s tr a c t
U s i n g t h e T MS 3 2 0 C 6 0 0 0 Mc BS P a s a H i g h S p e e d C o m m u n i c a t i o n P o r t ( Re v . A ) ( s p ra 4 5 5 a . h tm , 1 0 KB)
3 1 A u g 2 0 0 1 A b s tr a c t
T MS 3 2 0 C 6 0 0 0 H o s t P o r t t o t h e i 8 0 9 6 0 Mi c r o p r o c e s s o r s I n t e r f a c e ( Re v . A ) ( s p ra 5 4 1 a . h tm , 9 KB)
3 1 A u g 2 0 0 1 A b s tr a c t
T MS 3 2 0 C 6 0 0 0 E MI F t o E x t e r n a l A s y n c h r o n o u s S RA M I n t e r f a c e ( Re v . A ) ( s p ra 5 4 2 a . h tm , 9 KB)
3 1 A u g 2 0 0 1 A b s tr a c t
T MS 3 2 0 C 6 0 0 0 S y s t e m C l o c k C i r c u i t E x a m p l e ( Re v . A ) ( s p ra 4 3 0 a . h tm , 9 KB)
1 5 A u g 2 0 0 1 A b s tr a c t
T MS 3 2 0 C 6 0 0 0 Mc BS P t o Vo i c e Ba n d A u d i o P r o c e s s o r ( VBA P ) I n t e r f a c e ( Re v . A ) ( s p ra 4 8 9 a . h tm , 9 KB)
2 3 J u l 2 0 0 1 A b s tr a c t
T MS 3 2 0 C 6 0 0 0 Mc BS P : A C ' 9 7 C o d e c I n t e r f a c e ( T L V3 2 0 A I C 2 7 ) ( Re v . A ) ( s p ra 5 2 8 a . h tm , 1 0 KB)
1 0 J u l 2 0 0 1 A b s tr a c t
T MS 3 2 0 C 6 0 0 0 Mc BS P : I n t e r f a c e t o S P I ROM ( Re v . C ) ( s p ra 4 8 7 c. h tm , 9 KB)
3 0 J u n 2 0 0 1 A b s tr a c t
T MS 3 2 0 C 6 0 0 0 H o s t P o r t t o MP C 8 6 0 I n t e r f a c e ( Re v . A ) ( s p ra 5 4 6 a . h tm , 9 KB)
2 1 J u n 2 0 0 1 A b s tr a c t
T MS 3 2 0 C 6 0 0 0 Mc BS P : I OM- 2 I n t e r f a c e ( Re v . A ) ( s p ra 5 6 9 a . h tm , 9 KB)
2 1 M a y 2 0 0 1 A b s tr a c t
C i r c u l a r Bu f f e r i n g o n T MS 3 2 0 C 6 0 0 0 ( Re v . A ) ( s p ra 6 4 5 a . h tm , 9 KB)
1 2 S e p 2 0 0 0 A b s tr a c t
T MS 3 2 0 C 6 0 0 0 Mc BS P a s a T D M H i g h wa y ( Re v . A ) ( s p ra 4 9 1 a . h tm , 9 KB)
1 1 S e p 2 0 0 0 A b s tr a c t
T MS 3 2 0 C 6 0 0 0 u - L a w a n d a - L a w C o m p a n d i n g wi t h S o f t wa r e o r t h e Mc BS P ( s p ra 6 3 4 . h tm , 9 KB)
0 2 Fe b 2 0 0 0 A b s tr a c t
T MS 3 2 0 C 6 0 0 0 E MI F : Ov e r v i e w o f S u p p o r t o f H i g h P e r f o r m a n c e Me m o r y T e c h n o l o g y ( s p ra 6 3 1 . h tm , 9 KB)
0 1 Fe b 2 0 0 0 A b s tr a c t
G e n e r a l G u i d e t o I m p l e m e n t L o g a r i t h m i c a n d E x p o n e n t i a l Op e r a t i o n s o n F i x e d - P o i n t ( s p ra 6 1 9 . h tm , 9 KB)
3 1 J a n 2 0 0 0 A b s tr a c t
T MS 3 2 0 C 6 0 0 0 C C o m p i l e r : C I m p l e m e n t a t i o n o f I n t r i n s i c s ( s p ra 6 1 6 . h tm , 9 KB)
0 7 D e c 1 9 9 9 A b s tr a c t
T MS 3 2 0 C 6 0 0 0 Mc BS P : I 2 S I n t e r f a c e ( s p ra 5 9 5 . h tm , 9 KB)
0 8 S e p 1 9 9 9 A b s tr a c t
V i e w A p p l i c a ti o n N o te s f o r T M S 3 2 0 D M 6 4 x D S P s
User Guides
T MS 3 2 0 C 6 4 x / C 6 4 x + D S P C P U a n d I n s t r u c t i o n S e t Re f e r e n c e G u i d e ( Re v . A ) ( s p ru 7 3 2 a . h tm , 9 KB)
3 0 J u n 2 0 0 5 A b s tr a c t
T MS 3 2 0 C 6 0 0 0 D S P Mu l t i c h a n n e l A u d i o S e r i a l P o r t ( Mc A S P ) Re f e r e n c e G u i d e ( Re v . F ) ( s p ru 0 4 1 f . h tm , 9 KB)
0 1 M a y 2 0 0 5 A b s tr a c t
T MS 3 2 0 C 6 0 0 0 D S P E x t e r n a l Me m o r y I n t e r f a c e ( E MI F ) Re f e r e n c e G u i d e ( Re v . D ) ( s p ru 2 6 6 d . h tm , 8 KB)
1 9 A p r 2 0 0 5 A b s tr a c t
T MS 3 2 0 C 6 0 0 0 D S P E n h a n c e d D i r e c t Me m o r y A c c e s s ( E D MA ) C o n t r o l l e r Re f e r e n c e G u i d e ( Re v . B) ( s p ru 2 3 4 b . h tm , 9 KB)
2 3 M a r 2 0 0 5 A b s tr a c t
T MS 3 2 0 C 6 0 0 0 D S P P e r i p h e r a l s Ov e r v i e w Re f e r e n c e G u i d e ( Re v . H ) ( s p ru 1 9 0 h . h tm , 8 KB)
0 8 M a r 2 0 0 5 A b s tr a c t
T MS 3 2 0 C 6 0 0 0 D S P P o we r - D o wn L o g i c a n d Mo d e s Re f e r e n c e G u i d e ( Re v . C ) ( s p ru 7 2 8 c. h tm , 8 KB)
0 1 M a r 2 0 0 5 A b s tr a c t
T MS 3 2 0 C 6 0 0 0 D S P 3 2 - b i t T i m e r Re f e r e n c e G u i d e ( Re v . B) ( s p ru 5 8 2 b . h tm , 9 KB)
2 5 J a n 2 0 0 5 A b s tr a c t
T MS 3 2 0 C 6 4 x D S P Vi d e o P o r t / VC XO I n t e r p o l a t e d C o n t r o l ( VI C ) P o r t Re f e r e n c e G u i d e ( Re v . D ) ( s p ru 6 2 9 d . h tm , 9 KB)
1 4 J a n 2 0 0 5 A b s tr a c t
T MS 3 2 0 C 6 0 0 0 D S P Mu l t i c h a n n e l Bu f f e r e d S e r i a l P o r t ( Mc BS P ) Re f e r e n c e G u i d e ( Re v . D ) ( s p ru 5 8 0 d . h tm , 9 KB)
0 9 S e p 2 0 0 4 A b s tr a c t
T MS 3 2 0 C 6 4 x D S P T wo L e v e l I n t e r n a l Me m o r y Re f e r e n c e G u i d e ( Re v . B) ( s p ru 6 1 0 b . h tm , 9 KB)
1 3 A u g 2 0 0 4 A b s tr a c t
T MS 3 2 0 C 6 0 0 0 D S P E MA C / MD I O Mo d u l e Re f e r e n c e G u i d e ( Re v . A ) ( s p ru 6 2 8 a . h tm , 9 KB)
2 6 M a r 2 0 0 4 A b s tr a c t
T MS 3 2 0 C 6 0 0 0 D S P G e n e r a l - P u r p o s e I n p u t / Ou t p u t ( G P I O) Re f e r e n c e G u i d e ( Re v . A ) ( s p ru 5 8 4 a . h tm , 9 KB)
2 5 M a r 2 0 0 4 A b s tr a c t
T MS 3 2 0 C 6 0 0 0 D S P I n t e r r u p t S e l e c t o r Re f e r e n c e G u i d e ( Re v . A ) ( s p ru 6 4 6 a . h tm , 8 KB)
0 9 J a n 2 0 0 4 A b s tr a c t
T MS 3 2 0 C 6 0 0 0 D S P D e s i g n i n g f o r J T A G E m u l a t i o n Re f e r e n c e G u i d e ( s p ru 6 4 1 . h tm , 9 KB)
3 1 J u l 2 0 0 3 A b s tr a c t
T MS 3 2 0 C 6 0 0 0 D S P C a c h e U s e r ' s G u i d e ( Re v . A ) ( s p ru 6 5 6 a . h tm , 9 KB)
0 5 M a y 2 0 0 3 A b s tr a c t
T MS 3 2 0 C 6 0 0 0 D S P I n t e r - I n t e g r a t e d C i r c u i t ( I 2 C ) Mo d u l e Re f e r e n c e G u i d e ( Re v . A ) ( s p ru 1 7 5 a . h tm , 9 KB)
0 9 O c t 2 0 0 2 A b s tr a c t
T MS 3 2 0 C 6 4 x T e c h n i c a l Ov e r v i e w ( Re v . B) ( s p ru 3 9 5 b . p d f , 1 9 2 KB)
3 0 J a n 2 0 0 1 D o w n l o a d
V i e w U s e r G u i d e s f o r T M S 3 2 0 D M 6 4 x D S P s
Simulat ion Models
I BI S Mo d e l
D M6 4 0 G D K/ G NZ I BI S Mo d e l ( s p rm 1 2 6 . i b s , 4 2 4 KB)
0 5 S e p 2 0 0 3 i b i s / z i p
BS D L Mo d e l
D M6 4 0 G D K BS D L Mo d e l ( s p rm 1 3 2 . z i p , 9 KB)
1 2 S e p 2 0 0 3 z i p
D M6 4 0 G NZ BS D L Mo d e l ( s p rm 1 3 3 . z i p , 9 KB)
1 2 S e p 2 0 0 3 z i p
More Lit erat ure
D S P S e l e c t i o n G u i d e 3 Q 2 0 0 5 ( Re v . Q) ( s s d v0 0 4 q . p d f , 4 3 5 9 KB)
0 1 J u l 2 0 0 5 D o w n l o a d
T MS 3 2 0 D M6 4 x D i g i t a l Me d i a P r o c e s s o r s - P r o d u c t Bu l l e t i n ( Re v . B) ( s p rt2 7 7 b . p d f , 1 0 7 KB)
0 7 S e p 2 0 0 4 D o w n l o a d
Vi d e o / I m a g i n g Be n c h m a r k s ( Re v . A ) ( s p rt2 9 1 a . p d f , 3 9 KB)
0 1 M a r 2 0 0 4 D o w n l o a d
Vi d e o S e c u r i t y o v e r I P ( VS I P ) D e v e l o p m e n t P l a t f o r m P r o d u c t Bu l l e t i n ( s p rt2 8 4 . p d f , 2 1 9 KB)
0 5 N o v 2 0 0 3 D o w n l o a d
T MS 3 2 0 D M6 4 x D i g i t a l Me d i a D e v e l o p m e n t T o o l s P r o d u c t Bu l l e t i n ( s p rt2 8 1 . p d f , 1 3 3 KB)
3 1 J u l 2 0 0 3 D o w n l o a d
Tools & Sof t ware
Name
P art #
Company
Sof t ware/Tool Ty pe
C o d e C o m p o s e r Stu d i o I DE
C C ST U DI O
T e x a s I n s tru m e n ts
C o d e C o m p o s e r Stu d i o ( T M ) I DE
C o d e C o m p o s e r Stu d i o ( T M ) I DE
C o d e C o m p o s e r Stu d i o I DE
Su b s cri p ti o n Se rvi ce
C C ST U DI O SU BSC R I P T I O NS T e x a s I n s tru m e n ts
DM 6 4 2 Eva l u a ti o n M o d u l e
T M DSEVM 6 4 2
T M DSVSK6 4 1 6
T e x a s I n s tru m e n ts
T e x a s I n s tru m e n ts
De ve l o p m e n t Bo a rd s / EVM s
De ve l o p m e n t Bo a rd s / EVM s
Vi d e o Se cu ri ty o ve r I P ( VSI P )
De ve l o p m e n t P l a tf o rm
Ne two rk a n d Vi d e o 1 GHz
De ve l o p m e n t Ki t
T M DXNVK6 4 1 5 - T
T M DX3 P NV6 4 1 6 S
T e x a s I n s tru m e n ts
T e x a s I n s tru m e n ts
De ve l o p m e n t P l a tf o rm s
De ve l o p m e n t P l a tf o rm s
Ne two rk a n d Vi d e o De ve l o p m e n t
Ki t
XDS5 1 0 C l a s s Em u l a to rs
XDS5 1 0
XDS5 6 0
T e x a s I n s tru m e n ts
T e x a s I n s tru m e n ts
Em u l a to rs / An a l yz e rs
Em u l a to rs / An a l yz e rs
XDS5 6 0 C l a s s Hi g h Sp e e d
Em u l a to rs
Fl a s h Bu rn P o rti n g Ki t
T M DSSDSFBP K
T M DSDSK6 4 1 6
T e x a s I n s tru m e n ts
T e x a s I n s tru m e n ts
Fl a s h T o o l s
Sta rte r Ki ts
T M S3 2 0 C 6 4 1 6 DSP Sta rte r Ki t
( DSK)
T M S3 2 0 C 6 0 0 0 C h i p Su p p o rt
L i b ra ry
SP R C 0 9 0
SP R C 1 2 2
T e x a s I n s tru m e n ts
T e x a s I n s tru m e n ts
Ap p l i ca ti o n So f twa re
T M S3 2 0 C 6 2 x / T M S3 2 0 C 6 4 x
Fa s tR T S L i b ra ry
Si g n a l P ro ce s s i n g L i b ra ri e s
Dri ve r De ve l o p e r' s Ki t ( DDK)
DSP / BI O S I I R e a l - T i m e Ke rn e l
SP R C 1 1 8
DSP BI O S
SP R C 1 1 6
T e x a s I n s tru m e n ts
T e x a s I n s tru m e n ts
T e x a s I n s tru m e n ts
Ap p l i ca ti o n So f twa re
DSP / BI O S R e a l - T i m e Ke rn e l
T M S3 2 0 DSP Al g o ri th m Sta n d a rd
T M S3 2 0 C 6 0 0 0 DSP Al g o ri th m
De ve l o p e r' s Ki t
Relat ed P roduct s
Relat ed Block D iagrams
Di g i ta l Se t T o p Bo x
Di g i ta l Sti l l C a m e ra
L C D T V
P o rta b l e M e d i a P l a ye r ( P M P )
Se cu ri ty I P DVR
Stre a m i n g M e d i a
Su rve i l l a n ce I P Vi d e o No d e
A ll Block D iagrams
Relat ed A pplicat ions
Vi d e o a n d I m a g i n g
Stre a m i n g M e d i a
Su rve i l l a n ce I P C a m e ra s
A ll A pplicat ions
P r o d u c t s | A p p l i c a t i o n s | D e s i g n S u p p o r t | Bu y | C o n ta c t U s | T I W o r l d w i d e | m y . T I L o g i n | A l l S e a r c h e s | C o m p a n y I n f o |
P r e s s R e l e a s e s | R S S | S i te M a p
© C o p yri g h t 1 9 9 5 - 2 0 0 5 T e x a s I n s tru m e n ts I n co rp o ra te d . Al l ri g h ts re s e rve d . T ra d e m a rk s | P ri va cy P o l i cy | T e rm s o f U s e
相关型号：
©2020 ICPDF网 联系我们和版权申明