TMS320UC5409PGE_技术文档

TMS320UC5409

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS101A – APRIL 1999 – REVISED AUGUST 1999

Advanced Multibus Architecture With Three

Separate 16-Bit Data Memory Buses and

One Program Memory Bus

Arithmetic Instructions With Parallel Store

and Parallel Load

Conditional Store Instructions

Fast Return From Interrupt

40-Bit Arithmetic Logic Unit (ALU),

Including a 40-Bit Barrel Shifter and Two

Independent 40-Bit Accumulators

On-Chip Peripherals

– Software-Programmable Wait-State

Generator and Programmable Bank

Switching

– On-Chip Phase-Locked Loop (PLL) Clock

Generator With Internal Oscillator or

External Clock Source

17- × 17-Bit Parallel Multiplier Coupled to a

40-Bit Dedicated Adder for Non-Pipelined

Single-Cycle Multiply/Accumulate (MAC)

Operation

Compare, Select, and Store Unit (CSSU) for

the Add/Compare Selection of the Viterbi

Operator

– Three Multichannel Buffered Serial Ports

(McBSPs)

– Enhanced 8-Bit Parallel Host-Port

Interface With 16-Bit Data/Addressing

– One 16-Bit Timer

– Six-Channel Direct Memory Access

(DMA) Controller

Exponent Encoder to Compute an

Exponent Value of a 40-Bit Accumulator

Value in a Single Cycle

Two Address Generators With Eight

Auxiliary Registers and Two Auxiliary

Register Arithmetic Units (ARAUs)

Power Consumption Control With IDLE1,

IDLE2, and IDLE3 Instructions With

Power-Down Modes

Data Bus With a Bus-Holder Feature

Extended Addressing Mode for 8M × 16-Bit

Maximum Addressable External Program

Space

CLKOUT Off Control to Disable CLKOUT

On-Chip Scan-Based Emulation Logic,

†

IEEE Std 1149.1 (JTAG) Boundary Scan

16K x 16-Bit On-Chip ROM

Logic

32K x 16-Bit Dual-Access On-Chip RAM

12.5-ns Single-Cycle Fixed-Point

Instruction Execution Time (80 MIPS)

Single-Instruction-Repeat and

Block-Repeat Operations for Program Code

1.8-V Core Power Supply

Block-Memory-Move Instructions for Better

Program and Data Management

1.8-V to 3.6-V I/O Power Supply Enables

Operation With a SIngle 1.8-V Supply or

With Dual Power Supplies

Instructions With a 32-Bit Long Word

Operand

Available in a 144-Pin Plastic Thin Quad

Flatpack (TQFP) (PGE Suffix) and a 144-Pin

Ball Grid Array (BGA) (GGU Suffix)

Instructions With Two- or Three-Operand

Reads

description

The TMS320UC5409 fixed-point, digital signal processor (DSP) (hereafter referred to as the ’UC5409 unless

otherwisespecified)isidealforlow-power, high-performanceapplications. Thisprocessoroffersverylowpower

consumption and the flexibility to support various system voltage configurations. The wide range of I/O voltage

enables it to operate with a single 1.8-V power supply or with dual power supplies for mixed voltage systems.

This feature eliminates the need for external level-shifting and reduces power consumption in emerging sub-3V

systems.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

†

IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.

ADVANCE INFORMATION concerns new products in the sampling or

preproduction phase of development. Characteristic data and other

specifications are subject to change without notice.

1

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320UC5409

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS101A – APRIL 1999 – REVISED AUGUST 1999

description (continued)

The TMS320UC5409 fixed-point, digital signal processor (DSP) (hereafter referred to as the ’UC5409 unless

otherwise specified) is based on an advanced modified Harvard architecture that has one program memory bus

and three data memory buses. This processor provides an arithmetic logic unit (ALU) with a high degree of

parallelism, application-specific hardware logic, on-chip memory, and additional on-chip peripherals. The basis

of the operational flexibility and speed of this DSP is a highly specialized instruction set.

For detailed information on the architecture of the ’C5000 family of DSPs, see the TMS320C5000 DSP Family

Functional Overview (literature number SPRU307).

†‡

TMS320UC5409 PGE PACKAGE

(TOP VIEW)

1

108

107

106

105

104

103

102

101

100

99

V

A18

A17

SS

A22

2

3

V

SS

DD

4

A16

D5

DV

5

A10

HD7

A11

A12

A13

A14

A15

6

D4

D3

D2

D1

D0

RS

X2/CLKIN

X1

HD3

CLKOUT

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

98

97

CV

HAS

DD

96

95

V

SS

DD

94

93

V

SS

HPIENA

CV

92

HCS

HR/W

READY

PS

91

DD

SS

TMS

90

V

89

88

TCK

TRST

TDI

TDO

EMU1/OFF

EMU0

TOUT

HD2

HPI16

CLKMD3

CLKMD2

CLKMD1

DS

87

IS

86

R/W

85

MSTRB

IOSTRB

MSC

84

83

82

XF

81

HOLDA

IAQ

HOLD

BIO

80

79

78

77

MP/MC

76

V

SS

DV

V

BDR1

DD

SS

75

DD

74

BDX1

BFSX1

73

BFSR1

†

‡

NC = No internal connection

DV is the power supply for the I/O pins while CV

is the power supply for the core CPU. V

DD SS

is the ground for both the I/O

DD

pins and the core CPU.

2

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320UC5409

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS101A – APRIL 1999 – REVISED AUGUST 1999

TMS320UC5409 GGU PACKAGE

(BOTTOM VIEW)

13 12 11 10

9

8

7

6

5

4

3

2

1

A

B

C

D

E

F

G

H

J

K

L

M

N

The pin assignments table to follow lists each signal quadrant and BGA ball number for the

TMS320UC5409GGU (144-pin BGA package).

3

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320UC5409

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS101A – APRIL 1999 – REVISED AUGUST 1999

†

Pin Assignments TMS320UC5409GGU (144-Pin BGA Package)

SIGNAL

QUADRANT 1

SIGNAL

QUADRANT 2

SIGNAL

QUADRANT 3

SIGNAL

QUADRANT 4

BGA BALL #

V

A1

B1

C2

C1

D4

D3

D2

D1

E4

E3

E2

E1

F4

F3

F2

F1

G2

G1

G3

G4

H1

H2

H3

H4

J1

BFSX1

BDX1

N13

M13

L12

L13

K10

K11

K12

K13

J10

J11

V

N1

N2

M3

N3

K4

A19

A20

A13

A12

B11

A11

D10

C10

B10

A10

D9

C9

B9

SS

A22

SS

BCLKR1

HCNTL0

V

DV

V

SS

DV

DD

SS

DV

V

SS

V

SS

DD

A10

DD

D6

CLKMD1

CLKMD2

CLKMD3

HPI16

HD2

BCLKR0

BCLKR2

BFSR0

BFSR2

BDR0

HD7

A11

A12

A13

A14

A15

L4

D7

D8

M4

N4

K5

D9

D10

D11

D12

HD4

D13

D14

D15

HD5

TOUT

EMU0

EMU1/OFF

TDO

HCNTL1

BDR2

L5

J12

J13

H10

H11

H12

H13

G12

G13

G11

G10

F13

F12

F11

F10

E13

E12

E11

E10

D13

D12

D11

C13

C12

C11

B13

B12

M5

N5

K6

CV

DD

HAS

BCLKX0

BCLKX2

A9

D8

C8

B8

V

TDI

V

L6

SS

HINT

CV

TRST

M6

N6

M7

N7

L7

SS

CV

DD

HCS

TCK

A8

DD

TMS

BFSX0

BFSX2

HRDY

CV

B7

DD

HR/W

READY

PS

V

SS

HDS1

A7

SS

CV

C7

D7

A6

DD

HPIENA

DV

K7

V

DD

SS

HDS2

DV

DS

V

SS

V

SS

N8

M8

L8

IS

CLKOUT

HD3

X1

HD0

BDX0

BDX2

IACK

HBIL

NMI

B6

DD

A0

R/W

C6

D6

A5

MSTRB

IOSTRB

MSC

XF

K8

A1

A2

A3

HD6

A4

A5

A6

A7

A8

A9

X2/CLKIN

RS

N9

M9

L9

J2

B5

J3

D0

C5

D5

A4

HOLDA

IAQ

J4

D1

INT0

INT1

INT2

INT3

K9

K1

K2

K3

L1

D2

N10

M10

L10

N11

M11

L11

N12

M12

HOLD

BIO

D3

B4

D4

C4

A3

MP/MC

D5

CV

DD

DV

L2

A16

HD1

B3

DD

V

SS

L3

V

SS

V

SS

CV

DD

A21

C3

A2

BDR1

M1

M2

A17

A18

BCLKX1

BFSR1

V

SS

B2

SS

is the power supply for the core CPU. V

†

DV

is the power supply for the I/O pins while CV

DD

is the ground for both the I/O pins and the core

SS

DD

CPU.

4

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320UC5409

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS101A – APRIL 1999 – REVISED AUGUST 1999

terminal functions

The following table lists each signal, function, and operating mode(s) grouped by function.

Terminal Functions

TERMINAL

NAME

†

I/O

DESCRIPTION

DATA SIGNALS

O/Z

A22 (MSB)

A21

A20

A19

A18

A17

A16

A15

A14

A13

A12

A11

A10

A9

A8

A7

A6

A5

A4

A3

A2

A1

Parallel address bus A22 [most significant bit (MSB)] through A0 [least significant bit (LSB)]. The lower sixteen

address pins (A0 to A15) are multiplexed to address all external memory (program, data) or I/O while the upper seven

address pins (A16 to A22) are only used to address external program space. These pins are placed in the

high-impedance state when the hold mode is enabled, or when OFF is low.

I

These pins can be used to address internal memory via the HPI when the HPI16 pin

is high (A0 – A15).

A15

A14

A13

A12

A11

A10

A9

(MSB)

A8

A7

A6

A5

A4

A3

A2

A1

A0

(LSB)

A0

(LSB)

I/O/Z

I/O

Parallel data bus D15 (MSB) through D0 (LSB). The sixteen data pins (D0 to D15) are

multiplexed to transfer data between the core CPU and external data/program

memory or I/O devices. The data bus is placed in the high-impedance state when not

outputting or when RS or HOLD is asserted. The data bus also goes into the

high-impedance state when OFF is low.

D15 (MSB)

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

(MSB)

The data bus has bus holders to reduce the static power dissipation caused by

floating, unused pins. These bus holders also eliminate the need for external bias

resistors on unused pins. When the data bus is not being driven by the ’UC5409, the

bus holders keep the pins at the previous logic level. The data bus holders on the

’UC5409 are disabled at reset and can be enabled/disabled via the BH bit of the

bank-switching control register (BSCR).

D4

D3

D2

D1

D0

(LSB)

D0

(LSB)

INITIALIZATION, INTERRUPT, AND RESET OPERATIONS

Interrupt acknowledge signal. IACK indicates receipt of an interrupt and that the program counter is fetching the

interrupt vector location designated by A15–A0. IACK also goes into the high-impedance state when OFF is low.

IACK

O/Z

INT0

INT1

INT2

INT3

External user interrupts. INT0–INT3 are prioritized and are maskable by the interrupt mask register and the interrupt

mode bit. INT0 –INT3 can be polled and reset by way of the interrupt flag register.

I

Nonmaskable interrupt. NMI is an external interrupt that cannot be masked by way of the INTM or the IMR. When

NMI is activated, the processor traps to the appropriate vector location.

NMI

I

†

I = Input, O = Output, Z = High-impedance, S = Supply

5

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320UC5409

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS101A – APRIL 1999 – REVISED AUGUST 1999

Terminal Functions (Continued)

TERMINAL

NAME

†

I/O

DESCRIPTION

INITIALIZATION, INTERRUPT, AND RESET OPERATIONS (CONTINUED)

Reset. RS causes the digital signal processor (DSP) to terminate execution and causes a reinitialization of the CPU

and peripherals. When RS is brought to a high level, execution begins at location 0FF80h of program memory. RS

affects various registers and status bits.

RS

I

Microprocessor/microcomputer mode select. If active low at reset, microcomputer mode is selected, and the internal

programROM is mapped into the upper program memory space. If the pin is driven high during reset, microprocessor

mode is selected, and the on-chip ROM is removed from program space. MP/MC is only sampled at reset, and the

MP/MC bit of the PMST register can override the mode that is selected at reset.

MP/MC

MULTIPROCESSING SIGNALS

Branch control. A branch can be conditionally executed when BIO is active. If low, the processor executes the

conditional instruction. For the XC instruction, the BIO condition is sampled during the decode phase of the pipeline;

all other instructions sample BIO during the read phase of the pipeline.

BIO

XF

I

External flag output (latched software-programmable signal). XF is set high by the SSBX XF instruction, set low by

theRSBX XF instruction or by loading ST1. XF is used for signaling other processors in multiprocessor configurations

or used as a general-purpose output pin. XF goes into the high-impedance state when OFF is low, and is set high

at reset.

O/Z

MEMORY CONTROL SIGNALS

DS

PS

IS

Data, program, and I/O space select signals. DS, PS, and IS are always high unless driven low for accessing a

particular external memory space. Active period corresponds to valid address information. DS, PS, and IS are placed

into the high-impedance state in the hold mode; the signals also go into the high-impedance state when OFF is low.

O/Z

Memory strobe signal. MSTRB is always high unless low-level asserted to indicate an external bus access to data

or program memory. MSTRB is placed in the high-impedance state in the hold mode; it also goes into the

high-impedance state when OFF is low.

MSTRB

READY

R/W

Data ready. READY indicates that an external device is prepared for a bus transaction to be completed. If the device

is not ready (READY is low), the processor waits one cycle and checks READY again. Note that the processor

performs ready detection if at least two software wait states are programmed. The READY signal is not sampled until

the completion of the software wait states.

I

Read/write signal. R/W indicates transfer direction during communication to an external device. R/W is normally in

the read mode (high), unless it is asserted low when the DSP performs a write operation. R/W is placed in the

high-impedance state in hold mode; it also goes into the high-impedance state when OFF is low.

O/Z

I/Ostrobesignal. IOSTRBisalwayshighunlesslow-levelassertedtoindicateanexternalbusaccesstoanI/Odevice.

IOSTRB

HOLD

O/Z

I

IOSTRB is placed in the high-impedance state in the hold mode; it also goes into the high-impedance state when OFF

is low.

Hold. HOLD is asserted to request control of the address, data, and control lines. When acknowledged by the ’C54x,

these lines go into the high-impedance state.

Hold acknowledge. HOLDA indicates that the ’UC5409 is in a hold state and that the address, data, and control lines

are in the high-impedance state, allowing the external memory interface to be accessed by other devices. HOLDA

also goes into the high-impedance state when OFF is low.

HOLDA

O/Z

Microstate complete. MSC indicates completion of all software wait states. When two or more software wait states

are enabled, the MSC pin goes low during the last of these wait states. If connected to the READY input, MSC forces

one external wait state after the last internal wait state is completed. MSC also goes into the high-impedance state

when OFF is low.

MSC

IAQ

O/Z

Instruction acquisition signal. IAQ is asserted (active low) when there is an instruction address on the address bus.

IAQ goes into the high-impedance state when OFF is low.

OSCILLATOR/TIMER SIGNALS

Master clock output signal. CLKOUT cycles at the machine-cycle rate of the CPU. The internal machine cycle is

bounded by rising edges of this signal. CLKOUT also goes into the high-impedance state when OFF is low.

CLKOUT

O/Z

†

I = Input, O = Output, Z = High-impedance, S = Supply

6

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320UC5409

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS101A – APRIL 1999 – REVISED AUGUST 1999

Terminal Functions (Continued)

TERMINAL

NAME

†

I/O

DESCRIPTION

OSCILLATOR/TIMER SIGNALS (CONTINUED)

Clock mode select signals. These inputs select the mode that the clock generator is initialized to after reset. The logic

levels of CLKMD1–CLKMD3 are latched when the reset pin is low, and the clock mode register is initialized to the

selected mode. After reset, the clock mode can be changed through software, but the clock mode select signals have

no effect until the device is reset again.

CLKMD1

CLKMD2

CLKMD3

I

X2/CLKIN

X1

I

Clock/oscillator input. If the internal oscillator is not being used, X2/CLKIN functions as the clock input.

Outputpinfromtheinternaloscillatorforthecrystal. Iftheinternaloscillatorisnotused,X1shouldbeleftunconnected.

X1 does not go into the high-impedance state when OFF is low.

O

Timer output. TOUT signals a pulse when the on-chip timer counts down past zero. The pulse is one CLKOUT cycle

wide. TOUT also goes into the high-impedance state when OFF is low.

TOUT

O/Z

MULTICHANNEL BUFFERED SERIAL PORT SIGNALS

BCLKR0

BCLKR1

BCLKR2

I/O/Z

I

Receive clock input. BCLKR serves as the serial shift clock for the buffered serial port receiver.

BDR0

BDR1

BDR2

Serial data receive input

BFSR0

BFSR1

BFSR2

I/O/Z

O/Z

I/O/Z

Frame synchronization pulse for receive input. The BFSR pulse initiates the receive data process over BDR.

BCLKX0

BCLKX1

BCLKX2

Transmit clock. BCLKX serves as the serial shift clock for the McBSP transmitter. BCLKX can be configured as an

inputoranoutput;itisconfiguredasaninputfollowingreset. BCLKXentersthehigh-impedancestatewhenOFFgoes

low.

BDX0

BDX1

BDX2

Serial data transmit output. BDX is placed in the high-impedance state when not transmitting, when RS is asserted,

or when OFF is low.

BFSX0

BFSX1

BFSX2

Framesynchronization pulse for transmit input/output. The BFSX pulse initiates the transmit data process. BFSX can

beconfigured as an input or an output; it is configured as an input following reset. BFSX goes into the high-impedance

state when OFF is low.

HOST-PORT INTERFACE SIGNALS

A0 – A15

I

These pins can be used to address internal memory via the HPI when the HPI16 pin is high.

These pins can be used to read/write internal memory via the HPI when the HPI16 pin is high. The sixteen data pins,

D0 to D15, are multiplexed to transfer data between the core CPU and external data/program memory, I/O devices,

or HPI in 16-bit mode. The data bus is placed in the high-impedance state when not outputting or when RS or HOLD

is asserted. The data bus also goes into the high-inmpedance state when OFF is low.

D0 – D15

I/O

The data bus includes bus holders to reduce the static power dissipation caused by floating, unused pins. The bus

holders also eliminate the need for external bias resistors on unused pins. When the data bus is not being driven by

the ’UC5409, the bus holders keep the pins at the logic level that was most recently driven. The data bus holders of

the ’UC5409 are disabled at reset, and can be enabled/disabled via the BH bit of the BSCR.

Parallel bidirectional data bus. These pins can also be used as general-purpose I/O pins when the HPI16 pin is high.

HD0–HD7 is placed in the high-impedance state when not outputting data or when OFF is low. The HPI data bus

includes bus holders to reduce the static power dissipation caused by floating, unused pins. When the HPI data bus

is not being driven by the ’UC5409, the bus holders keep the pins at the logic level that was most recently driven. The

HPI data bus holders are disabled at reset and can be enabled/disabled via the HBH bit of the BSCR.

HD0 – HD7

I/O/Z

†

I = Input, O = Output, Z = High-impedance, S = Supply

7

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320UC5409

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS101A – APRIL 1999 – REVISED AUGUST 1999

Terminal Functions (Continued)

TERMINAL

NAME

†

I/O

DESCRIPTION

HOST-PORT INTERFACE SIGNALS (CONTINUED)

HCNTL0

HCNTL1

Control. HCNTL0 and HCNTL1 select a host access to one of the three HPI registers. The control inputs have internal

pullup resistors that are only enabled when HPIENA = 0.

I

Byte identification. HBIL identifies the first or second byte of transfer. The HBIL input has an internal pullup resistor

that is only enabled when HPIENA = 0.

HBIL

HCS

Chip select. HCS is the select input for the HPI and must be driven low during accesses. The chip-select input has

an internal pullup resistor that is only enabled when HPIENA = 0.

HDS1

HDS2

Data strobe. HDS1 and HDS2 are driven by the host read and write strobes to control transfers. The strobe inputs

have internal pullup resistors that are only enabled when HPIENA = 0.

Address strobe. Hosts with multiplexed address and data pins require HAS to latch the address in the HPIA register.

HAS has an internal pullup resistor that is only enabled when HPIENA = 0.

HAS

Read/write. HR/W controls the direction of an HPI transfer. R/W has an internal pullup resistor that is only enabled

when HPIENA = 0.

HR/W

HRDY

HINT

Ready. The ready output informs the host when the HPI is ready for the next transfer. HRDY goes into the

high-impedance state when OFF is low.

O/Z

Interrupt. This output is used to interrupt the host. When the DSP is in reset, HINT is driven high. The signal goes

into the high-impedance state when OFF is low.

HPImoduleselect. HPIENAmustbedrivenhighduringresettoenabletheHPI. Aninternalpulldownresistorisalways

active and the HPIENA pin is sampled on the rising edge of RS. If HPIENA is left open or is driven low during reset,

the HPI module is disabled. Once the HPI is disabled, the HPIENA pin has no effect until the ’UC5409 is reset.

HPIENA

HPI16

I

HPI 16-bit select pin. HPI16 = 1 selects the non-multiplexed mode. The non-multiplexed mode allows hosts with

separate address/data buses to access the HPI address range via the 16 address pins (A0–A15). The 16-bit data

is also accessible through pins D0 through D15. Host-to-DSP and DSP-to-Host interrupts are not supported. There

are no HPIC and HPIA registers in the non-multiplexed mode since HCNTRL0 and HCNTRL1 signals are available.

SUPPLY PNS

CV

DV

S

+V . Dedicated 1.8-V power supply for the core CPU

DD

+V . Dedicated 3.3-V power supply for the I/O pins

DD

V

SS

Ground

TEST PINS

IEEE standard 1149.1 test clock. TCK is normally a free-running clock signal with a 50% duty cycle. The changes

on the test access port (TAP) of input signals TMS and TDI are clocked into the TAP controller, instruction register,

or selected test data register on the rising edge of TCK. Changes at the TAP output signal (TDO) occur on the falling

edge of TCK.

TCK

I

IEEE standard 1149.1 test data input pin with internal pullup device. TDI is clocked into the selected register

(instruction or data) on a rising edge of TCK.

TDI

I

IEEE standard 1149.1 test data output. The contents of the selected register (instruction or data) are shifted out of

TDO on the falling edge of TCK. TDO is in the high-impedance state except when the scanning of data is in progress.

TDO also goes into the high-impedance state when OFF is low.

TDO

TMS

TRST

O/Z

IEEE standard 1149.1 test mode select. Pin with internal pullup device. This serial control input is clocked into the

TAP controller on the rising edge of TCK.

I

IEEE standard 1149.1 test reset. TRST, when high, gives the IEEE standard 1149.1 scan system control of the

operations of the device. If TRST is not connected or is driven low, the device operates in its functional mode, and

the IEEE standard 1149.1 signals are ignored. Pin with internal pulldown device.

†

I = Input, O = Output, Z = High-impedance, S = Supply

8

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320UC5409

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS101A – APRIL 1999 – REVISED AUGUST 1999

Terminal Functions (Continued)

TERMINAL

NAME

†

I/O

DESCRIPTION

TEST PINS (CONTINUED)

Emulator 0 pin. When TRST is driven low, EMU0 must be high for activation of the OFF condition. When TRST is

driven high, EMU0 is used as an interrupt to or from the emulator system and is defined as input/output by way of

the IEEE standard 1149.1 scan system.

EMU0

I/O/Z

Emulator 1 pin/disable all outputs. When TRST is driven high, EMU1/OFF is used as an interrupt to or from the

emulator system and is defined as input/output by way of the IEEE standard 1149.1 scan system. When TRST is

driven low, EMU1/OFF is configured as OFF. The EMU1/OFF signal, when active low, puts all output drivers into the

high-impedancestate. Note that OFF is used exclusively for testing and emulation purposes (not for multiprocessing

EMU1/OFF

applications). Therefore, for the OFF feature, the following apply:

TRST = low

EMU0 = high

EMU1/OFF = low

†

I = Input, O = Output, Z = High-impedance, S = Supply

memory

The ’UC5409 device provides both on-chip ROM and RAM memories to aid in system performance and

integration.

on-chip ROM with bootloader

The ’5409 features a 16K-word × 16-bit on-chip maskable ROM. Customers can arrange to have the ROM of

the ’5409 programmed with contents unique to any particular application. A security option is available to protect

a custom ROM. This security option is described in the TMS320C54xDSPCPUandPeripheralsReferenceSet,

Volume 1 (literature number SPRU131). Note that only the ROM security option, and not the ROM/RAM option,

is available on the ’5409 .

A bootloader is available in the standard ’5409 on-chip ROM. This bootloader can be used to automatically

transfer user code from an external source to anywhere in the program memory at power up. If the MP/MC pin

is sampled low during a hardware reset, execution begins at location FF80h of the on-chip ROM. This location

contains a branch instruction to the start of the bootloader program. The standard ’5409 bootloader provides

different ways to download the code to accomodate various system requirements:

Parallel from 8-bit or 16-bit-wide EPROM

Parallel from I/O space 8-bit or 16-bit mode

Serial boot from serial ports 8-bit or 16-bit mode

Host-port interface boot

SPI serial EEPROM 8-bit boot mode

9

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320UC5409

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS101A – APRIL 1999 – REVISED AUGUST 1999

on-chip ROM with bootloader (continued)

The standard on-chip ROM layout is shown in Table 1.

†

Table 1. Standard On-Chip ROM Layout

ADDRESS RANGE

DESCRIPTION

0x0000h – 0xBFFFh

External program space

Reserved

0xC000h – 0xF7FFh

0xF800h – 0xFBFFh

Bootloader

0xFC00h – 0xFEFFh Reserved

†

0xFF00h – 0xFF7Fh

0xFF80h – 0xFFFFh

Reserved

Interrupt vector table

†

In the ’VC5409 ROM, 128 words are reserved for factory device-testing purposes. Application

code to be implemented in on-chip ROM must reserve these 128 words at addresses

FF00h–FF7Fh in program space.

on-chip RAM

The ’UC5409 device contains 32K × 16-bit of on-chip dual-access RAM (DARAM). The DARAM is composed

of four blocks of 8K words each. Each block in the DARAM can support two reads in one cycle, or a read and

a write in one cycle. The DARAM is located in the address range 0080h–7FFFh in data space, and can be

mapped into program/data space by setting the OVLY bit to one.

10

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320UC5409

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS101A – APRIL 1999 – REVISED AUGUST 1999

memory map

Page 0 Program

Data

Hex

0000

Hex

0000

Hex

0000

Memory-

Mapped

Registers

Reserved

(OVLY = 1)

External

(OVLY = 0)

Reserved

(OVLY = 1)

External

(OVLY = 0)

005F

0060

Scratch-Pad

RAM

007F

0080

007F

0080

007F

0080

On-Chip DARAM

(OVLY = 1)

On-Chip DARAM

(OVLY = 1)

On-Chip DARAM

(32K words)

External

(OVLY = 0)

External

(OVLY = 0)

7FFF

8000

7FFF

8000

7FFF

8000

External

BFFF

C000

BFFF

C000

External

On-Chip ROM

(16K Words)

ROM

(DROM=1)

FEFF

FF00

or External

(DROM=0)

Reserved

FF7F

FF80

FF7F

FF80

FEFF

FF00

Reserved

(DROM=1)

or External

(DROM=0)

Interrupts

(External)

Interrupts

(On-Chip)

FFFF

MP/MC= 1

(Microprocessor Mode)

MP/MC= 0

(Microcomputer Mode)

Figure 1. Memory Map

relocatable interrupt vector table

The reset, interrupt, and trap vectors are addressed in program space. These vectors are soft — meaning that

the processor, when taking the trap, loads the program counter (PC) with the trap address and executes the

code at the vector location. Four words are reserved at each vector location to accommodate a delayed branch

instruction, either two 1-word instructions or one 2-word instruction, which allows branching to the appropriate

interrupt service routine with minimal overhead.

At device reset, the reset, interrupt, and trap vectors are mapped to address FF80h in program space. However,

these vectors can be remapped to the beginning of any 128-word page in program space after device reset.

This is done by loading the interrupt vector pointer (IPTR) bits in the PMST register with the appropriate

128-word page boundary address. After loading IPTR, any user interrupt or trap vector is mapped to the new

128-word page.

NOTE: The hardware reset (RS) vector cannot be remapped because a hardware reset loads the IPTR

with 1s. Therefore, the reset vector is always fetched at location FF80h in program space.

11

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320UC5409

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS101A – APRIL 1999 – REVISED AUGUST 1999

extended program memory

The ’UC5409 uses a paged extended memory scheme in program space to allow access of up to 8M program

memory locations. In order to implement this scheme, the ’UC5409 includes several features that are also

present on the ’548/’549 devices:

Twenty-three address lines, instead of sixteen

An extra memory-mapped register, the XPC register defines the page selection. This register is

memory-mapped into data space to address 001Eh. At a hardware reset, the XPC is initialized to 0.

Six extra instructions for addressing extended program space. These six instructions affect the XPC.

–

FB[D] pmad (23 bits) – Far branch

FBACC[D] Accu[22:0] – Far branch to the location specified by the value in accumulator A or

accumulator B

–

FCALL[D] pmad (23 bits) – Far call

FCALA[D] Accu[22:0] – Far call to the location specified by the value in accumulator A or accumulator B

FRET[D] – Far return

FRETE[D] – Far return with interrupts enabled

In addition to these new instructions, two ’54x instructions are extended to use 23 bits in the ’UC5409:

–

READA data_memory (using 23-bit accumulator address)

WRITA data_memory (using 23-bit accumulator address)

All other instructions, software interrupts, and hardware interrupts do not modify the XPC register and access

only memory within the current page.

Program memory in the ’UC5409 is organized into 127 pages that are each 64K in length, as shown in Figure 2.

00 0000

1 0000

2 0000

7F 0000

. . .

Internal

32K

Page 1

Lower

32K

Page 2

Lower

32K

Page 127

Lower

32K

†

External

. . .

Page 0

1 7FFF

1 8000

2 7FFF

2 8000

7F 7FFF

7F 8000

32K

Page 1

Upper

32K

Page 2

Upper

32K

Page 127

Upper

32K

External

. . .

0 FFFF

1 FFFF

2 FFFF

7F FFFF

†

The lower 32K words of pages 1 through 126 are available only when the OVLY bit is cleared to 0. If the OVLY bit is set to 1, the on-chip RAM

is mapped to the lower 32K words of all program space pages.

Figure 2. Extended Program Memory

12

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320UC5409

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS101A – APRIL 1999 – REVISED AUGUST 1999

on-chip peripherals

The ’UC5409 device has the following peripherals:

Software-programmable wait-state generator with programmable bank-switching wait states

An enhanced 8-bit host-port interface (HPI8/16) with 16-bit data/addressing

Three multichannel buffered serial ports (McBSPs)

One hardware timer

A clock generator with a phase-locked loop (PLL)

A direct memory access (DMA) controller

software-programmable wait-state generator

The software wait-state generator of the ’UC5409 is similar to that of the ’5410 and it can extend external bus

cycles by up to fourteen machine cycles. Devices that require more than fourteen wait states can be interfaced

using the hardware READY line. When all external accesses are configured for zero wait states, the internal

clocks to the wait-state generator are automatically disabled. Disabling the wait-state generator clocks reduces

the power comsumption of the ’UC5409.

The software wait-state register (SWWSR) controls the operation of the wait-state generator. The 14 LSBs of

the SWWSR specify the number of wait states (0 to 7) to be inserted for external memory accesses to five

separate address ranges. This allows a different number of wait states for each of the five address ranges.

Additionally, the software wait-state multiplier (SWSM) bit of the system configuration register (SCR) defines

a multiplication factor of 1 or 2 for the number of wait states. At reset, the wait-state generator is initialized to

provide seven wait states on all external memory accesses. The SWWSR bit fields are shown in Figure 3 and

described in Table 2.

15

14

12 11

9

8

6

5

3

2

0

XPA

I/O

R/W-111

Data

R/W-111

Data

Program

R/W-111

Program

R/W-111

R/W-0

R/W-111

LEGEND: R = Read, W = Write

Figure 3. Software Wait-State Register (SWWSR) [Memory-Mapped Register (MMR) Address 0028h]

13

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320UC5409

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS101A – APRIL 1999 – REVISED AUGUST 1999

software-programmable wait-state generator (continued)

Table 2. Software Wait-State Register (SWWSR) Bit Fields

BIT

RESET

VALUE

FUNCTION

NO.

NAME

Extended program address control bit. XPA is used in conjunction with the program space fields

(bits 0 through 5) to select the address range for program space wait states.

15

XPA

0

1

I/O space. The field value (0–7) corresponds to the base number of wait states for I/O space accesses

within addresses 0000–FFFFh. The SWSM bit of the SWCR defines a multiplication factor of 1 or 2 for

the base number of wait states.

14–12

11–9

8–6

I/O

Upper data space. The field value (0–7) corresponds to the base number of wait states for external data

space accesses within addresses 8000–FFFFh. The SWSM bit of the SWCR defines a multiplication

factor of 1 or 2 for the base number of wait states.

Data

1

Lower data space. The field value (0–7) corresponds to the base number of wait states for external data

space accesses within addresses 0000–7FFFh. The SWSM bit of the SWCR defines a multiplication

factor of 1 or 2 for the base number of wait states.

Upper program space. The field value (0–7) corresponds to the base number of wait states for external

program space accesses within the following addresses:

XPA = 0: x8000 – xFFFFh

5–3

2–0

Program

1

XPA = 1: The upper program space bit field has no effect on wait states.

The SWSM bit of the SWCR defines a multiplication factor of 1 or 2 for the base number of wait states.

Program space. The field value (0–7) corresponds to the base number of wait states for external program

space accesses within the following addresses:

XPA = 0: x0000–x7FFFh

XPA = 1: 00000–FFFFFh

The SWSM bit of the SWCR defines a multiplication factor of 1 or 2 for the base number of wait states.

The software wait-state multiplier bit of the software wait-state configuration register is used to extend the base

number of wait states selected by the SWWSR. The SWCR bit fields are shown in Figure 4 and described in

Table 3.

15

1

0

SWSM

Reserved

R/W-0

LEGEND: R = Read, W = Write

Figure 4. Software Wait-State Configuration Register (SWCR) [MMR Address 002Bh]

Table 3. Software Wait-State Configuration Register (SWCR) Bit Fields

RESET

VALUE

FUNCTION

These bits are reserved and are unaffected by writes.

NO.

NAME

15–1

Reserved

0

Softwarewait-statemultiplier. UsedtomultiplythenumberofwaitstatesdefinedintheSWWSRbyafactor

of 1 or 2.

0

SWSM

0

SWSM = 0: wait-state base values are unchanged (multiplied by 1).

SWSM = 1: wait-state base values are multiplied by 2 for a maximum of 14 wait states.

14

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320UC5409

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS101A – APRIL 1999 – REVISED AUGUST 1999

programmable bank-switching wait states

The programmable bank-switching logic of the ’UC5409 is functionally equivalent to that of the ’548/’549

devices. This feature automatically inserts one cycle when accesses cross memory-bank boundaries within

program or data memory space. A bank-switching wait state can also be automatically inserted when accesses

cross the data space boundary into program space.

The bank-switching control register (BSCR) defines the bank size for bank-switching wait-states. Figure 5

shows the BSCR and its bits are described in Table 4.

15

12

11

10

3

2

1

0

BNKCMP

R/W-1111

PS-DS

Reserved

R-0

HBH

BH

EXIO

R/W-1

R/W-0

LEGEND: R = Read, W = Write

Figure 5. Bank-Switching Control Register (BSCR) [MMR Address 0029h]

Table 4. Bank-Switching Control Register Fields

BIT

NAME

RESET

FUNCTION

VALUE

NO.

Bank compare. BNKCMP determines the external memory-bank size. BNKCMP is used to mask the four

15–12 BNKCMP

1111

MSBs of an address. For example, if BNKCMP = 1111b, the four MSBs (bits 12–15) are compared, resulting

in a bank size of 4K words. Bank sizes of 4K words to 64K words are allowed.

Program read – data read access. PS-DS inserts an extra cycle between consecutive accesses of program

read and data read or data read and program read.

11

10–3

2

PS - DS

Reserved

HBH

1

0

PS-DS = 0

PS-DS = 1

No extra cycles are inserted by this feature.

One extra cycle is inserted between consecutive data and program reads.

These bits are reserved and are unaffected by writes.

HPI bus holder. HBH controls the HPI bus holder feature. HBH is cleared to 0 at reset.

HBH = 0

HBH = 1

The bus holder is disabled.

The bus holder is enabled. When not driven, the HPI data bus (HD[7:0]) is held in the

previous logic level.

Bus holder. BH controls the data bus holder feature. BH is cleared to 0 at reset.

BH = 0

BH = 1

The bus holder is disabled.

The bus holder is enabled. When not driven, the data bus (D[15:0]) is held in the

previous logic level.

1

0

BH

0

External bus interface off. The EXIO bit controls the external bus-off function.

EXIO = 0

EXIO = 1

The external bus interface functions as usual.

The address bus, data bus, and control signals become inactive after completing the

current bus cycle. Note that the DROM, MP/MC, and OVLY bits in the PMST and the HM

bit of ST1 cannot be modified when the interface is disabled.

EXIO

15

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320UC5409

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS101A – APRIL 1999 – REVISED AUGUST 1999

parallel I/O ports

The ’UC5409 has a total of 64K I/O ports. These ports can be addressed by the PORTR instruction or the

PORTW instruction. The IS signal indicates a read/write operation through an I/O port. The ’UC5409 can

interface easily with external devices through the I/O ports while requiring minimal off-chip address-decoding

circuits.

enhanced 8-bit host-port interface (HPI8/16)

The ’UC5409 host-port interface, also referred to as the HPI8/16, is an enhanced version of the standard 8-bit

HPI found on earlier ’54x DSPs (’542, ’545, ’548, and ’549). The HPI8/16 is an 8-bit parallel port for

interprocessor communication. The features of the HPI8/16 include:

Standard features:

Sequential transfers (with autoincrement) or random-access transfers

Host interrupt and ’54x interrupt capability

Multiple data strobes and control pins for interface flexibility

Enhanced features of the ’UC5409 HPI8/16:

Access to entire on-chip RAM through DMA bus

Capability to continue transferring during emulation stop

Capability to transfer 16-bit address and 16-bit data (non-multiplexed mode)

The HPI8/16 functions as a slave and enables the host processor to access the on-chip memory of the ’UC5409.

A major enhancement to the ’UC5409 HPI over previous versions is that it allows host access to the entire

on-chip memory range of the DSP. The HPI8/16 does not have access to external memory. The host and the

DSP both have access to the on-chip RAM at all times and host accesses are always synchronized to the DSP

clock. If the host and the DSP contend for access to the same location, the host has priority, and the DSP waits

for one HPI8/16 cycle. Note that since host accesses are always synchronized to the ’UC5409 clock, an active

input clock (CLKIN) is required for HPI8/16 accesses during IDLE states, and host accesses are not allowed

while the ’UC5409 reset pin is asserted.

In standard 8-bit mode, the HPI8/16 interface consists of an 8-bit bidirectional data bus and various control

signals. Sixteen-bit transfers are accomplished in two parts with the HBIL input designating high or low byte.

The host communicates with the HPI8/16 through three dedicated registers — HPI address register (HPIA), HPI

data register (HPID), and an HPI control register (HPIC). The HPIA and HPID registers are only accessible by

the host, and the HPIC register is accessible by both the host and the ’UC5409.

In 16-bit nonmultiplexed mode (HPI16=1), the HPI8/16 can read and write to internal memory via the external

address and data pins, A0 – A15 and D0–D15, respectively. HD0–HD7 can be configured as general-purpose

input/output (GPIO). The HPI16 non-multiplexed mode does not support the use of the HPID and HPIA

registers. Host-to-DSP and DSP-to-host interrupts are also not supported. See Figure 6 for the HPI memory

map.

16

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320UC5409

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS101A – APRIL 1999 – REVISED AUGUST 1999

enhanced 8-bit host-port interface (HPI8/16) (continued)

0000h

Reserved

005Fh

0060h

Scratch-Pad

RAM

007Fh

0080h

On-Chip RAM

(32K x 16 Bits)

7FFFh

8000h

Reserved

FFFFh

Figure 6. ’UC5409 HPI Memory Map

HPI nonmultiplexed mode

In nonmultiplexed mode, a host with separate address/data buses can access the HPI16 data register (HPID)

via the HD 16-bit bidirectional data bus, and the address register (HPIA) via the 16-bit HA address bus. The host

initiates the access with the strobe signals (HDS1, HDS2, HCS) and controls the direction of the access with

the HR/W signal. The HPI16 can stall host accesses via the HRDY signal. Note that the HPIC register is not

available in nonmultiplexed mode since there are no HCNTL signals available. All host accesses initiate a DMA

read or write access. Figure 7 shows a block diagram of the HPI16 in nonmultiplexed mode.

HOST

HPI16

PPD[15:0]

DATA[15:0]

HPID[15:0]

HINT

DMA

Address[15:0]

HCNTL0

V

CC

HCNTL1

HBIL

HAS

R/W

HR/W

’54xx

CPU

Data Strobes

HDS1, HDS2, HCS

HRDY

READY

Figure 7. Host-Port Interface — Nonmultiplexed Mode

host access control

Host accesses are controlled by the data strobes (HDS1 and HDS2), along with chip select (HCS), in exactly

the same fashion as documented in the HPI nonmultiplexed mode section.

host access type

In nonmultiplexed mode, only one access type (HPID read/write) is available since the HPIA register is not

needed because of direct address inputs, and since the HCNTL pins are not available for access-type selection.

17

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320UC5409

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS101A – APRIL 1999 – REVISED AUGUST 1999

HPI16 control register (HPIC)

In nonmultiplexed mode, the HPIC register is not accessible via the host. This precludes DSP-to-host or

host-to-DSP interrupts, data prefetch via the FETCH bit, and HRDY polling. Extended addressing capability still

exists (even without the XHPIA bit) because the HA bus is 16 bits wide.

HPI16 address register (HPIA)

In nonmultiplexed mode, the HPIA register is not needed because direct address inputs A[15:0] are used as

HA[15:0]. The DMA address comes directly from the HA pins. Note that the HA bus is still always latched at the

end of the host access (on the rising edge of HDS = HDS1 XNOR HDS2) in order to ensure a valid address

during the DMA write access.

host data prefetch

Since the HPIA register is not used in nonmultiplexed mode, the prefetch mechanism is not supported. Random

address accesses in nonmultiplexed mode are still faster than those in multiplexed mode because of the

separate address and data buses.

host ready logic (HRDY)

Hardware HRDY logic operation in nonmultiplexed mode is the same as that in multiplexed mode. HRDY

operation during prefetches and HRDY/FETCH bit interaction are not supported with nonmultiplexed mode.

host/DSP interrupts

Host-to-DSP and DSP-to-host interrupts are not supported by HPI16 in nonmultiplexed mode.

other HPI system considerations

operation during IDLE2

The HPI can continue to operate during IDLE1 or IDLE2 by using special clock management logic that turns

on relevant clocks to perform a synchronous memory access, and then turns the clocks back off to save power.

The DSP CPU does not wake up from the IDLE mode during this process.

multichannel buffered serial ports

The ’UC5409 device has three high-speed, full-duplex multichannel buffered serial ports (McBSPs) that allow

direct interface to other ’C54x/’LC54x devices, codecs, and other devices in a system. The McBSPs are based

on the standard serial port interface found on other ’54x devices. Like its predecessors, the McBSP provides:

Full-duplex communication

Double-buffer data registers, which allow a continuous data stream

Independent framing and clocking for receive and transmit

In addition, the McBSP has the following capabilities:

Direct interface to:

–

T1/E1 framers

MVIP switching-compatible and ST-BUS compliant devices

IOM-2 compliant devices

AC97-compliant devices

Serial peripheral interface (SPI ) devices

Multichannel transmit and receive of up to 128 channels

A wide selection of data sizes including 8, 12, 16, 20, 24, or 32 bits

µ-law and A-law companding

Programmable polarity for both frame synchronization and data clocks

Programmable internal clock and frame generation

SPI is a trademark of Motorola Inc.

18

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320UC5409

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS101A – APRIL 1999 – REVISED AUGUST 1999

multichannel buffered serial ports (continued)

The McBSPs consist of separate transmit and receive channels that operate independently. The external

interface of each McBSP consists of the following pins:

BCLKX

BDX

Transmit reference clock

Transmit data

BFSX

BCLKR

BDR

Transmit frame synchronization

Receive reference clock

Receive data

BFSR

Receive frame synchronization

The six pins listed are functionally equivalent to the pins of previous serial port interface pins in the ’C5000 family

ofDSPs. Onthetransmitter, transmitframesynchronizationandclockingareindicatedbytheBFSXandBCLKX

pins, respectively. The CPU or DMA can initiate transmission of data by writing to the data transmit register

(DXR). Data written to DXR is shifted out on the BDX pin through a transmit shift register (XSR). This structure

allows DXR to be loaded with the next word to be sent while the transmission of the current word is in progress.

On the receiver, receive frame synchronization and clocking are indicated by the BFSR and BCLKR pins,

respectively. The CPU or DMA can read received data from the data receive register (DRR). Data received on

the BDR pin is shifted into a receive shift register (RSR) and then buffered in the receive buffer register (RBR).

If the DRR is empty, the RBR contents are copied into the DRR. If not, the RBR holds the data until the DRR

is available. This structure allows storage of the two previous words while the reception of the current word is

in progress.

The CPU and DMA can move data to and from the McBSPs and can synchronize transfers based on McBSP

interrupts, event signals, and status flags. The DMA is capable of handling data movement between the

McBSPs and memory with no intervention from the CPU.

In addition to the standard serial port functions, the McBSP provides programmable clock and frame sync

generation. Among the programmable functions are:

Frame synchronization pulse width

Frame period

Frame synchronization delay

Clock reference (internal vs. external)

Clock division

Clock and frame sync polarity

The on-chip companding hardware allows compression and expansion of data in either µ-law or A-law format.

When companding is used, transmit data is encoded according to specified companding law and received data

is decoded to 2s complement format.

The McBSP allows the multiple channels to be independently selected for the transmitter and receiver. When

multiple channels are selected, each frame represents a time-division multiplexed (TDM) data stream. In using

TDM data streams, the CPU may only need to process a few of them. Thus, to save memory and bus bandwidth,

multichannel selection allows independent enabling of particular channels for transmission and reception. Up

to 32 channels in a stream of up to 128 channels can be enabled.

The clock-stop mode (CLKSTP) in the McBSP provides compatibility with the serial peripheral interface (SPI)

protocol. Clock-stop mode works with only single-phase frames and one word per frame. The word sizes

supported by the McBSP are programmable for 8-, 12-, 16-, 20-, 24-, or 32-bit operation. When the McBSP is

configured to operate in SPI mode, both the transmitter and the receiver operate together as a master or as a

slave.

The McBSP is fully static and operates at arbitrarily low clock frequencies. The maximum frequency is CPU

clock frequency divided by 2.

19

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320UC5409

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS101A – APRIL 1999 – REVISED AUGUST 1999

sample rate generator external clock options

Although the CLKS pin is not available on the ’5409 PGE and GGU packages, the ’5409 is capable of

synchronizationto external clock sources. CLKX or CLKR can be used by the sample rate generator for external

synchronization. Thesamplerateclockmodeextended(SCLKME) bitfieldislocatedinthePCRtoaccomodate

this option.

15

14

13

XIOEN

RW

12

RIOEN

RW

11

10

FSRM

RW

9

8

Reserved

FSXM

RW

CLKXM

RW

CLKRM

RW

7

6

5

4

3

2

1

0

SCLKME

CLKS STAT

RW

DX STAT

RW

DR STAT

RW

FSXP

RW

FSRP

RW

CLKXP

RW

CLKRP

RW

Legend: R = Read, W = Write

Figure 8. Pin Control Register (PCR)

20

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320UC5409

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS101A – APRIL 1999 – REVISED AUGUST 1999

sample rate generator external clock options (continued)

Table 5. Pin Control Register (PCR) Bit Field Description

BIT

15 – 14 Reserved Reserved. Pins are not used.

Transmit/Receive general-purpose I/O mode ONLY when XRST=0 in the SPCR(1/2)

NAME

FUNCTION

XIOEN = 0

XIOEN = 1

DXpinisnotageneral-purposeoutput. FSXandCLKXarenotgeneral-purposeI/Os.

DX pin is a general-purpose output. FSX and CLKX are general-purpose I/Os. These

serial port pins do not perform serial port operations.

13

XIOEN

Transmit/Receive general-purpose I/O mode ONLY when RRST=0 in the SPCR(1/2)

RIOEN = 0

RIOEN = 1

DR and CLKS pins are not general-purpose inputs. FSR and CLKR are not

general-purpose I/Os.

DR and CLKS pins are general-purpose inputs. FSR and CLKR aregeneral-purpose

I/Os. These serial port pins do not perform serial port operations. The CLKS pin is

affected by a combination of RRST and RIOEN signals of the receiver.

12

RIOEN

Transmit frame synchronization mode

FSRM = 0

FSRM = 1

Frame synchronization signal derived from an external source.

Frame synchronization is determined by the sample rate generator frame

synchronization mode bit (FSGM) in the SRGR2.

11

10

FSXM

FSRM

Receive frame synchronization mode

FSRM = 0

FSRM = 1

Frame synchronization pulses generated by an external device. FSR is an input pin.

Frame synchronization generated internally by the sample rate generator. FSR is an

output pin except when GSYNC=1 in the SRGR.

Receiver clock mode

Case 1: Digital loop-back mode is not set (CLB=0) in SPCR1.

CLKRM = 0

CLKRM= 1

Receive clock (CLKR) is an input pin driven by an external clock.

CLKR is an output pin and is driven by the internal sample rate generator

9

CLKRM

Case 2: Digital loop-back mode set (CLB=1) in SPCR1

CLKRM = 0

CLKRM= 1

Receive clock (Not the CLKR pin) is driven by transmit clock (CLKX), which is based

on CLKXM bit in the PCR. CLKR pin is in high-impedance mode.

CLKRisanoutputpinandisdrivenbythetransmitclock. Thetransmitclockisderived

based on the CLKXM bit in the PCR.

Transmitter clock mode

CLKXM = 0

CLKXM= 1

Receiver/transmitter clock is driven by an external clock with CLK(R/X) as an input

CLK(R/X) is an output pin and is driven by the internal sample rate generator

8

CLKXM

During SPI mode (CLKSTP is a non-zero value):

CLKXM = 0

CLKXM= 1

McBSP is a slave and clock (CLKX) is driven by the SPI master in the system. CLKR

is internally driven by CLKX.

McBSP is a master and generates the clock (CLKX) to drive its receive clock (CLKR)

and the shift clock of the SPI-compliant slaves in the system.

21

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320UC5409

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS101A – APRIL 1999 – REVISED AUGUST 1999

sample rate generator external clock options (continued)

Table 5. Pin Control Register (PCR) Bit Field Description (Continued)

BIT

NAME

FUNCTION

Sample rate clock mode extended

SCLKME = 0

SCLKME = 1

External clock via CLKS or CPU clock is used as a reference by the sample rate

generator.

External clock via CLKR or CLKX clock is used as a reference by the sample rate

generator.

7

SCLKME

CLKS

STAT

6

CLKS pin status. CLKS STAT reflects value on CLKS pin when selected as a general-purpose input.

5

4

DX STAT DX pin status. DX STAT reflects value on DX pin when it is selected as a general-purpose output.

DR STAT DR pin status. DR STAT reflects value on DR pin when it is selected as a general-purpose input.

Receive/Transmit frame synchronization polarity.

FSXP

3 – 2

FSRP

FS(R/X)P = 0

FS(R/X)P = 1

Frame synchronization pulse FS(R/X) is active high

Frame synchronization pulse FS(R/X) is active low

Transmit clock polarity

1

0

CLKXP

CLKXP = 0

CLKXP = 1

Transmit data sampled on rising edge of CLKR

Transmit data sampled on falling edge of CLKR

Receive clock polarity

CLKRP

CLKRP = 0

CLKRP = 1

Receive data sampled on falling edge of CLKR

Receive data sampled on rising edge of CLKR

The ’5409 sample rate generator has four clock input options that are only available when both the PCR and

SRGR2 are used. Table 6 shows the sample rate generator clock input options.

Table 6. Sample Rate Generator Clock Input Options

SCLKME

(PCR.7)

CLKSM

(SRGR2.13)

MODE

CLKS pin

CPU

0

1

0

1

0

1

CLKR pin

CLKX pin

15

GSYNC

RW

14

CLKSP

RW

13

12

11

10

9

8

7

6

5

FPER

RW

4

3

2

1

0

CLKSM FSGM

RW

Legend: R = Read, W = Write

Figure 9. Sample Rate Generator Register 2 (SRGR2)

22

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320UC5409

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS101A – APRIL 1999 – REVISED AUGUST 1999

sample rate generator external clock options (continued)

Table 7. Sample Rate Generator Register 2 (SRGR2) Bit Field Descriptions

BIT

NAME

FUNCTION

Sample rate gnereator clock synchronization. Only used when the external clock (CLKS) drives the

sample rate generator clock (CLKSM=0)

GSYNC = 0

GSYNC = 1

The sample rate generator clock (CLKG) is free-running.

15

GSYNC

Thesample rate generator clock (CLKG) is running. But CLKG is resynchronized and

frame sync signal (FSG) is generated only after detecting the receive frame

synchronization signal (FSR). Also, frame period (FPER) is a don’t care because the

period is dictated by the external frame sync pulse.

CLKS polarity clock edge select. Only used when the external clock (CLKS) drives the sample rate

generator clock (CLKSM=0).

14

13

CLKSP

CLKSM

CLKSP = 0

CLKSP = 1

Rising edge of CLKS generates CLKG and FSG.

Falling edge of CLKS generates CLKG and FSG.

McBSP sample rate generator clock mode

SCLKME = 0

(in PCR)

CLKSM = 0

CLKSM = 1

Sample rate generator clock derived from the CLKS pin

Sample rate generator clock derived from CPU clock

SCLKME = 1

(in PCR)

CLKSM = 0

CLKSM = 1

Sample rate generator clock derived from CLKR pin

Smaple rate generator clock derived from CLKX pin

Sample rate generator transmit frame synchronization mode. Used when FSXM=1 in the PCR.

FSGM = 0

FSGN = 1

Transmit frame sync signal (FSX) due to DXR(1/2) copy

Transmit frame sync signal driven by the sample rate generator frame sync signal

(FSG)

12

FSGM

FPER

Frame period. This determines when the next frame sycn signal should become active. Range: up to

12

11 – 0

2

; 1 to 4096 CLKG periods.

hardware timer

The ’UC5409 device features one 16-bit timing circuit with a 4-bit prescaler. The main counter of each timer is

decremented by one every CLKOUT cycle. Each time the counter decrements to 0, a timer interrupt is

generated. The timer can be stopped, restarted, reset, or disabled by specific control bits.

clock generator

The clock generator provides clocks to the ’UC5409 device, and consists of an internal oscillator and a

phase-locked loop (PLL) circuit. The clock generator requires a reference clock input, which can be provided

by using a crystal resonator with the internal oscillator, or from an external clock source. The reference clock

input is then divided by two (DIV mode) to generate clocks for the ’UC5409 device, or the PLL circuit can be

used (PLL mode) to generate the device clock by multiplying the reference clock frequency by a scale factor,

allowing use of a clock source with a lower frequency than that of the CPU.The PLL is an adaptive circuit that,

once synchronized, locks onto and tracks an input clock signal.

When the PLL is initially started, it enters a transitional mode during which the PLL acquires lock with the input

signal. Once the PLL is locked, it continues to track and maintain synchronization with the input signal. Then,

other internal clock circuitry allows the synthesis of new clock frequencies for use as master clock for the

’UC5409 device.

23

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320UC5409

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS101A – APRIL 1999 – REVISED AUGUST 1999

clock generator (continued)

This clock generator allows system designers to select the clock source. The sources that drive the clock

generator are:

A crystal resonator circuit. The crystal resonator circuit is connected across the X1 and X2/CLKIN pins of

the ’UC5409 to enable the internal oscillator.

An external clock. The external clock source is directly connected to the X2/CLKIN pin, and X1 is left

unconnected.

The software-programmable PLL features a high level of flexibility, and includes a clock scaler that provides

various clock multiplier ratios, capability to directly enable and disable the PLL, and a PLL lock timer that can

be used to delay switching to PLL clocking mode of the device until lock is achieved. Devices that have a built-in

software-programmable PLL can be configured in one of two clock modes:

PLL mode. The input clock (X2/CLKIN) is multiplied by 1 of 31 possible ratios. These ratios are achieved

using the PLL circuitry.

DIV (divider) mode. The input clock is divided by 2 or 4. Note that when DIV mode is used, the PLL can be

completely disabled in order to minimize power dissipation.

The software-programmable PLL is controlled using the 16-bit memory-mapped (address 0058h) clock mode

register (CLKMD). The CLKMD register is used to define the clock configuration of the PLL clock module. Upon

reset, the CLKMD register is initialized with a predetermined value dependent only upon the state of the

CLKMD1 – CLKMD3 pins as shown in Table 8.

Table 8. Clock Mode Settings at Reset

CLKMD

RESET VALUE

CLKMD1

CLKMD2

CLKMD3

CLOCK MODE

0

1

E007h

9007h

PLL x 15

PLL x 10

0

1

0

1

0

1

0

1

0

1

4007h

1007h

F007h

0000h

F000h

—

PLL x 5

PLL x 2

PLL x 1

1/2 (PLL disabled)

1/4 (PLL disabled)

Reserved (Bypass mode)

24

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320UC5409

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS101A – APRIL 1999 – REVISED AUGUST 1999

DMA controller

The ’UC5409 direct memory access (DMA) controller transfers data between points in the memory map without

intervention by the CPU. The DMA controller allows movements of data to and from internal program/data

memory, internal peripherals (such as the McBSPs), and external program/data memory to occur in the

background of CPU operation. The DMA has six independent programmable channels allowing six different

contexts for DMA operation.

features

The DMA has the following features:

The DMA has external memory access.

The DMA operates independently of the CPU.

The DMA has six channels. The DMA can keep track of the contexts of six independent block transfers.

The DMA has higher priority than the CPU for internal accesses.

Each channel has independently programmable priorities.

Each channel’s source and destination address registers can have configurable indexes through memory

on each read and write transfer, respectively. The address may remain constant, be post-incremented,

post-decremented, or be adjusted by a programmable value.

Each read or write transfer may be initialized by selected events. (Internally only)

Each DMA channel is capable of sending interrupts to the CPU.

The DMA can perform double-word transfers (a 32-bit transfer of two 16-bit words). (Internally only)

DMA external access

The ’UC5409 DMA supports external accesses to extended program, data memory, and extended I/O memory.

Only two channels are available for external accesses. (One for external reads/one for external writes.)

Single-word transfers are supported for external accesses.

The DMA does not support transfers from peripherals to external memory.

The DMA does not support transfers from external memory to the peripherals.

DMA external transfer

Unlike the ’5410, the ’5409 DMA mode control register (DMMCRx) has two additional bits; DLAXS

(DMMCRn[5]) and SLAXS (DMMCRn[11]). These new bits specify the on/off-chip memory for the source and

destination of the program/data/IO spaces.

When DLAXS is set to 0 (default), the DMA does not perform an external access for the destination. When

DLAXS is set to 1, the DMA performs an external access to the destination location.

When SLAXS is set to 0 (default), the DMA does not perform an external access for the source. When

DLAXS is set to 1, the DMA performs an external access from the source location.

Two new registers are added to the ’5409 DMA to support DMA accesses to/from DMA extended data memory,

page 1 to page 127.

The DMA extended source data page register (XSRCDP[6:0]) is located at subbank address 028h.

The DMA extended destination data page register (XDSTDP[6:0]) is located at subbank address 029h.

25

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320UC5409

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS101A – APRIL 1999 – REVISED AUGUST 1999

DMA memory map

The DMA memory map, as shown in Figure 10, allows DMA transfers to be unaffected by the status of the

MP/MC, DROM, and OVLY bits.

Data

Program

Data

I/O

Program

Hex

010000

Hex

xx0000

Hex

xx0000

Hex

0000

Hex

0000

Hex

0000

Reserved

DRR20

001F

0020

Reserved

007F

0080

DRR10

DXR20

DXR10

0021

0022

0023

0024

Reserved

002F

0030

0031

0032

DRR22

DRR12

DXR22

DXR12

0033

0034

DARAM

Internal

32K

External

Reserved

0035

0036

RCERA2

XCERA2

0037

0038

Reserved

0039

003A

RCERA0

XCERA0

003B

003C

External

Reserved

DRR21

7FFF

8000

017FFF

018000

003F

0040

DRR11

DXR21

DXR11

0041

0042

0043

0044

On-Chip

ROM

Reserved

0049

004A

004B

004C

RCERA1

XCERA1

External

BFFF

C000

Reserved

005F

0060

Scratch-

Pad RAM

007F

0080

DARAM

External

7FFF

8000

xxFFFF

FFFF

xxFFFF

FFFF

01FFFF

Page 0, 1, ... 127

Page 0

Page 1, 2, ... 127

Page n

Page 5, 6, ...

NOTE A: n = 1, 2, 3, or 4

Figure 10. TMS320UC5409 DMA Memory Map

DMA priority level

Each DMA channel can be independently assigned high priority or low priority relative to each other. Multiple

DMA channels that are assigned to the same priority level are handled in a round-robin manner.

26

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320UC5409

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS101A – APRIL 1999 – REVISED AUGUST 1999

DMA source/destination address modification

The DMA provides flexible address-indexing modes for easy implementation of data management schemes

such as autobuffering and circular buffers. Source and destination addresses can be indexed separately and

can be post-incremented, post-decremented, or post-incremented with a specified index offset.

DMA in autoinitialization mode

The DMA can automatically reinitialize itself after completion of a block transfer. Some of the DMA registers can

be preloaded for the next block transfer through the DMA global reload registers (DMGSA, DMGDA, and

DMGCR). Autoinitialization allows:

Continuous operation: Normally, the CPU would have to reinitialize the DMA immediately after the

completion of the current block transfer; but with the global reload registers, it can reinitialize these values

for the next block transfer any time after the current block transfer begins.

Repetitive operation: The CPU does not preload the global reload register with new values for each block

transfer but only loads them on the first block transfer.

DMA transfer counting

The DMA channel element count register (DMCTRx) and the frame count register (DMFRCx) contain bit fields

that represent the number of frames and the number of elements per frame to be transferred.

Framecount. This8-bitvaluedefinesthetotalnumberofframesintheblocktransfer. Themaximumnumber

of frames per block transfer is 128 (FRAME COUNT= 0ffh). The counter is decremented upon the last read

transfer in a frame transfer. Once the last frame is transferred, the selected 8-bit counter is reloaded with

the DMA global frame reload register (DMGFR) if the AUTOINIT bit is set to 1. A frame count of 0 (default

value) means the block transfer contains a single frame.

Element count. This 16-bit value defines the number of elements per frame. This counter is decremented

after the read transfer of each element. The maximum number of elements per frame is 65536

(DMCTRn = 0FFFFh). In autoinitialization mode, once the last frame is transferred, the counter is reloaded

with the DMA global count reload register (DMGCR).

DMA transfers in double-word mode (Internal Only)

Double-word mode allows the DMA to transfer 32-bit words in any index mode. In double-word mode, two

consecutive 16-bit transfers are initiated and the source and destination addresses are automatically updated

following each transfer. In this mode, each 32-bit word is considered to be one element.

DMA channel index registers

The particular DMA channel index register is selected by way of the SIND and DIND field in the DMA mode

control register (DMMCRx). Unlike basic address adjustment, in conjunction with the frame index DMFRI0 and

DMFRI1, the DMA allows different adjustment amounts depending on whether or not the element transfer is

the last in the current frame. The normal adjustment value (element index) is contained in the element index

registers DMIDX0 and DMIDX1. The adjustment value (frame index) for the end of the frame is determined by

the selected DMA frame index register (either DMFRI0 or DMFRI1).

The element index and the frame index affect address adjustment as follows:

Element index: For all except the last transfer in the frame, the element index determines the amount to be

added to the DMA channel for the source/destination address register (DMSRCx/DMDSTx) as selected by

the SIND/DIND bits.

Frame index: If the transfer is the last in a frame, the frame index is used for address adjustment as selected

by the SIND/DIND bits. This occurs in both single-frame and multi-frame transfer.

27

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320UC5409

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS101A – APRIL 1999 – REVISED AUGUST 1999

DMA interrupts

The ability of the DMA to interrupt the CPU based on the status of the data transfer is configurable and is

determined by the IMOD and DINM bits in the DMA channel mode control register (DMMCRn). The available

modes are shown in Table 9.

Table 9. DMA Interrupts

MODE

ABU (non-decrement)

Multi-Frame

DINM

IMOD

INTERRUPT

1

0

1

0

1

X

At full buffer only

At half buffer and full buffer

At block-transfer complete (DMCTRn = DMSEFCn[7:0] = 0)

At end of frame and end of block (DMCTRn = 0)

No interrupt generated

Multi-Frame

Either

No interrupt generated

DMA controller synchronization events

The transfers associated with each DMA channel can be synchronized to one of several events. The DSYN bit

field of the DMSEFCn register selects the synchronization event for a channel. The list of possible events and

the DSYN values are shown in Table 10.

Table 10. DMA Synchronization Events

DSYN VALUE

0000b

0001b

0010b

0011b

0100b

0101b

0110b

0111b

DMA SYNCHRONIZATION EVENT

No synchronization used

McBSP0 receive event

McBSP0 transmit event

McBSP2 receive event

McBSP2 transmit event

McBSP1 receive event

McBSP1 transmit event

Reserved

1000b

1001b

1010b

1011b

1100b

1101b

1110b

Reserved

Timer interrupt event

External interrupt 3

Reserved

1111b

28

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320UC5409

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS101A – APRIL 1999 – REVISED AUGUST 1999

DMA channel interrupt selection

The DMA controller can generate a CPU interrupt for each of the six channels. However, due to a limit on the

number of internal CPU interrupt inputs, channels 0, 1, 2, and 3 are multiplexed with other interrupt sources.

DMA channels 0, 1, 2, and 3 share an interrupt line with the receive and transmit portions of the McBSP. When

the ’UC5409 is reset, the interrupts from these three DMA channels are deselected. The INTSEL bit field in the

DMPREC register can be used to select these interrupts, as shown in Table 11.

Table 11. DMA Channel Interrupt Selection

INTSEL Value

00b (reset)

01b

IMR/IFR[6]

BRINT2

DMAC0

IMR/IFR[7]

BXINT2

IMR/IFR[10]

BRINT1

IMR/IFR[11]

BXINT1

BXINT2

DMAC2

DMAC3

10b

DMAC1

DMAC2

DMAC3

11b

Reserved

29

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320UC5409

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS101A – APRIL 1999 – REVISED AUGUST 1999

memory-mapped registers

The ’UC5409 has 27 memory-mapped CPU registers, which are mapped in data memory space addresses 0h

to 1Fh. The device also has a set of memory-mapped registers associated with peripherals. Table 12 gives a

list of CPU memory-mapped registers (MMRs) available on ’UC5409. Table 13 shows additional peripheral

MMRs associated with the ’UC5409.

Table 12. CPU Memory-Mapped Registers

ADDRESS

NAME

IMR

DESCRIPTION

DEC

0

HEX

0

Interrupt mask register

Interrupt flag register

Reserved for testing

Status register 0

IFR

–

1

2–5

6

2–5

6

ST0

ST1

AL

7

Status register 1

8

Accumulator A low word (15–0)

AH

9

Accumulator A high word (31–16)

Accumulator A guard bits (39–32)

Accumulator B low word (15–0)

Accumulator B high word (31–16)

Accumulator B guard bits (39–32)

Temporary register

AG

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

A

BL

B

BH

C

BG

D

TREG

TRN

AR0

AR1

AR2

AR3

AR4

AR5

AR6

AR7

SP

E

F

Transition register

10

11

12

13

14

15

16

17

18

19

1A

1B

1C

1D

1E

1F

Auxiliary register 0

Auxiliary register 1

Auxiliary register 2

Auxiliary register 3

Auxiliary register 4

Auxiliary register 5

Auxiliary register 6

Auxiliary register 7

Stack pointer register

BK

Circular buffer size register

Block repeat counter

BRC

RSA

REA

PMST

XPC

–

Block repeat start address

Block repeat end address

Processor mode status (PMST) register

Extended program page register

Reserved

30

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320UC5409

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS101A – APRIL 1999 – REVISED AUGUST 1999

memory-mapped registers (continued)

Table 13. Peripheral Memory-Mapped Registers

NAME

ADDRESS

DESCRIPTION

TYPE

McBSP #0

Timer

DRR20

DRR10

DXR20

DXR10

TIM

20h

21h

Data receive register 2

Data receive register 1

Data transmit register 2

Data transmit register 1

Timer register

22h

23h

24h

PRD

25h

Timer period counter

Timer

TCR

26h

Timer control register

Timer

–

27h

Reserved

SWWSR

BSCR

–

28h

Software wait-state register

Bank-switching control register

Reserved

External Bus

29h

2Ah

SWCR

HPIC

2Bh

Software wait-state control register

HPI control register

External Bus

HPI

2Ch

–

2Dh–2Fh

30h

Reserved

DRR22

DRR12

DXR22

DXR12

SPSA2

SPSD2

–

Data receive register 2

Data receive register 1

Data transmit register 2

McBSP2 subbank address register

McBSP2 subbank data register

Reserved

McBSP #2

31h

32h

33h

34h

35h

36–37h

38h

SPSA0

SPCD0

–

McBSP0 subbank address register

McBSP0 subbank data register

Reserved

McBSP #0

39h

3Ah–3Bh

3C

GPIOCR

GPIOSR

–

General-purpose I/O pins control register

General-purpose I/O pins status register

Reserved

GPIO

3D

3E–3F

40h

DRR21

DRR11

DXR21

DXR11

–

Data receive register 1

Data receive register 2

Data transmit register 1

Data transmit register 2

Reserved

McBSP #1

41h

42h

43h

44h–47h

48h

SPSA1

SPCD1

–

McBSP1 subbank address register

McBSP1 subbank data register

Reserved

McBSP #1

49h

4Ah–53h

54h

DMPREC

DMSA

DMSDI

DMSDN

CLKMD

–

DMA channel priority and enable control register

DMA subbank address register

DMA subbank data register with autoincrement

DMA subbank data registrer

Clock mode register

DMA

PLL

55h

56h

57h

58h

59h–5Fh

Reserved

31

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320UC5409

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS101A – APRIL 1999 – REVISED AUGUST 1999

McBSP control registers and subaddresses

The control registers for the multichannel buffered serial port (McBSP) are accessed using the subbank

addressing scheme. This allows a set or subbank of registers to be accessed through a single memory location.

The serial port subbank address (SPSA) register is used as a pointer to select a particular register within the

subbank. The serial port subbank data (SPSD) register is used to access (read or write) the selected register.

Table 14 shows the McBSP control registers and their corresponding subaddresses.

Table 14. McBSP Control Registers and Subaddresses

McBSP0

McBSP1

SUB

ADDRESS

NAME

ADDRESS

NAME

ADDRESS

DESCRIPTION

Serial port control register 1

SPCR10

SPCR20

RCR10

39h

SPCR11

SPCR21

RCR11

49h

00h

01h

02h

03h

04h

05h

06h

07h

08h

09h

0Ah

0Bh

0Ch

0Dh

0Eh

Serial port control register 2

Receive control register 1

RCR20

RCR21

Receive control register 2

XCR10

XCR11

Transmit control register 1

XCR20

XCR21

Transmit control register 2

SRGR10

SRGR20

MCR10

MCR20

RCERA0

RCERB0

XCERA0

XCERB0

PCR0

SRGR11

SRGR21

MCR11

MCR21

RCERA1

RCERB1

XCERA1

XCERB1

PCR1

Sample rate generator register 1

Sample rate generator register 2

Multichannel register 1

Multichannel register 2

Receive channel enable register partition A

Receive channel enable register partition B

Transmit channel enable register partition A

Transmit channel enable register partition B

Pin control register

DMA subbank addressed registers

The direct memory access (DMA) controller has several control registers associated with it. The main control

register (DMPREC) is a standard memory mapped register. However, the other registers are accessed using

the subbank addressing scheme. This allows a set, or subbank of registers to be accessed through a single

memory location. The DMA subbank address (DMSA) register is used as a pointer to select a particular register

within the subbank, while the DMA subbank data (DMSDN) register or the DMA subbank data register with

autoincrement (DMSDI) is used to access (read or write) the selected register.

When the DMSDI register is used to access the subbank, the subbank address is automatically

postincremented so that a subsequent access affects the next register within the subbank. This autoincrement

feature is intended for efficient, successive accesses to several control registers. If the autoincrement feature

is not required, the DMSDN register should be used to access the subbank. Table 15 shows the DMA controller

subbank addressed registers and their corresponding subaddresses.

32

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320UC5409

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS101A – APRIL 1999 – REVISED AUGUST 1999

DMA subbank addressed registers (continued)

Table 15. DMA Subbank Addressed Registers

DMA

SUB

ADDRESS

NAME

ADDRESS

DESCRIPTION

DMSRC0

DMDST0

DMCTR0

DMSFC0

DMMCR0

DMSRC1

DMDST1

DMCTR1

DMSFC1

DMMCR1

DMSRC2

DMDST2

DMCTR2

DMSFC2

DMMCR2

DMSRC3

DMDST3

DMCTR3

DMSFC3

DMMCR3

DMSRC4

DMDST4

DMCTR4

DMSFC4

DMMCR4

DMSRC5

DMDST5

DMCTR5

DMSFC5

DMMCR5

DMSRCP

DMDSTP

DMIDX0

DMIDX1

DMFRI0

56h/57h

00h

01h

02h

03h

04h

05h

06h

07h

08h

09h

0Ah

0Bh

0Ch

0Dh

0Eh

0Fh

10h

11h

12h

13h

14h

15h

16h

17h

18h

19h

1Ah

1Bh

1Ch

1Dh

1Eh

1Fh

20h

21h

22h

23h

24h

25h

26h

27h

DMA channel 0 source address register

DMA channel 0 destination address register

DMA channel 0 element count register

DMA channel 0 sync select and frame count register

DMA channel 0 transfer mode control register

DMA channel 1 source address register

DMA channel 1 destination address register

DMA channel 1 element count register

DMA channel 1 sync select and frame count register

DMA channel 1 transfer mode control register

DMA channel 2 source address register

DMA channel 2 destination address register

DMA channel 2 element count register

DMA channel 2 sync select and frame count register

DMA channel 2 transfer mode control register

DMA channel 3 source address register

DMA channel 3 destination address register

DMA channel 3 element count register

DMA channel 3 sync select and frame count register

DMA channel 3 transfer mode control register

DMA channel 4 source address register

DMA channel 4 destination address register

DMA channel 4 element count register

DMA channel 4 sync select and frame count register

DMA channel 4 transfer mode control register

DMA channel 5 source address register

DMA channel 5 destination address register

DMA channel 5 element count register

DMA channel 5 sync select and frame count register

DMA channel 5 transfer mode control register

DMA source program page address (common channel)

DMA destination program page address (common channel)

DMA element index address register 0

DMA element index address register 1

DMA frame index register 0

DMFRI1

DMA frame index register 1

DMGSA

DMA global source address reload register

DMA global destination address reload register

DMA global count reload register

DMGDA

DMGCR

DMGFR

DMA global frame count reload register

33

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320UC5409

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS101A – APRIL 1999 – REVISED AUGUST 1999

interrupts

Vector-relative locations and priorities for all internal and external interrupts are shown in Table 16.

Table 16. Interrupt Locations and Priorities

LOCATION

DECIMAL

NAME

PRIORITY

FUNCTION

HEX

00

RS, SINTR

NMI, SINT16

SINT17

0

1

2

Reset (hardware and software reset)

Nonmaskable interrupt

4

04

8

08

—

3

Software interrupt #17

SINT18

12

0C

10

Software interrupt #18

SINT19

16

Software interrupt #19

SINT20

20

14

Software interrupt #20

SINT21

24

18

Software interrupt #21

SINT22

28

1C

20

Software interrupt #22

SINT23

32

Software interrupt #23

SINT24

36

24

Software interrupt #24

SINT25

40

28

Software interrupt #25

SINT26

44

2C

30

Software interrupt #26

SINT27

48

Software interrupt #27

SINT28

52

34

Software interrupt #28

SINT29

56

38

Software interrupt #29

SINT30

60

3C

40

Software interrupt #30

INT0, SINT0

INT1, SINT1

INT2, SINT2

TINT, SINT3

64

External user interrupt #0

External user interrupt #1

External user interrupt #2

Timer interrupt

68

44

4

72

48

5

76

4C

50

6

BRINT0, SINT4

80

7

McBSP #0 receive interrupt (default)

McBSP #0 transmit interrupt (default)

McBSP #2 receive interrupt (default)

McBSP #2 transmit interrupt (default)

External user interrupt #3

HPI interrupt

BXINT0, SINT5

84

54

8

BRINT2, SINT7, DMAC0

BXINT2, SINT6, DMAC1

INT3, SINT8

88

58

9

92

5C

60

10

11

12

13

14

15

16

—

96

HINT, SINT9

100

104

108

112

116

120–127

64

BRINT1, SINT10, DMAC2

BXINT1, SINT11, DMAC3

DMAC4,SINT12

68

McBSP #1 receive interrupt (default)

McBSP #1 transmit interrupt (default)

DMA channel 4 interrupt (default)

DMA channel 5 interrupt (default)

Reserved

6C

70

DMAC5,SINT13

74

Reserved

78–7F

34

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320UC5409

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS101A – APRIL 1999 – REVISED AUGUST 1999

interrupts (continued)

The bits of the interrupt flag register (IFR) and interrupt mask register (IMR) are arranged as shown in Figure 11.

The function of each bit is described in Table 17.

15–14

RES

13

12

11

10

9

8

7

6

5

4

3

2

1

0

BXINT1 BRINT1

DMAC3 DMAC2

BXINT2 BRINT2

DMAC1 DMAC0

DMAC5

DMAC4

HINT

INT3

BXINT0 BRINT0

TINT

INT2

INT1

INT0

Figure 11. IFR and IMR Registers

Table 17. IFR and IMR Register Bit Fields

BIT

FUNCTION

NUMBER

NAME

15–14

–

Reserved for future expansion

13

12

11

10

9

DMAC5

DMAC4

DMA channel 5 interrupt flag/mask bit

DMA channel 4 interrupt flag/mask bit

McBSP1 transmit interrupt flag/mask bit

McBSP1 receive interrupt flag/mask bit

Host to ’54x interrupt flag/mask

BXINT1/DMAC3

BRINT1/DMAC2

HINT

8

INT3

External interrupt 3 flag/mask

7

BXINT2/DMAC1

BRINT2/DMAC0

BXINT0

McBSP2 transmit interrupt flag/mask bit

McBSP2 receive interrupt flag/mask bit

McBSP0 transmit interrupt flag/mask bit

McBSP0 receive interrupt flag/mask bit

Timer interrupt flag/mask bit

6

5

4

BRINT0

3

TINT

2

INT2

External interrupt 2 flag/mask bit

External interrupt 1 flag/mask bit

External interrupt 0 flag/mask bit

1

INT1

0

INT0

35

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320UC5409

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS101A – APRIL 1999 – REVISED AUGUST 1999

documentation support

Extensive documentation supports all TMS320 family generations of devices from product announcement

through applications development. The following types of documentation are available to support the design

and use of the ’C5000 family of DSPs:

TMS320C5000 DSP Family Functional Overview (literature number SPRU307)

Device-specific data sheets (such as this document)

Complete User Guides

Development-support tools

Hardware and software application reports

The four-volume TMS320C54x DSP Reference Set (literature number SPRU210) consists of:

Volume 1: CPU and Peripherals (literature number SPRU131)

Volume 2: Mnemonic Instruction Set (literature number SPRU172)

Volume 3: Algebraic Instruction Set (literature number SPRU179)

Volume 4: Applications Guide (literature number SPRU173)

The reference set describes in detail the TMS320C54x products currently available, and the hardware and

software applications, including algorithms, for fixed-point TMS320 devices.

For general background information on DSPs and Texas Instruments (TI ) devices, see the three-volume

publication Digital Signal Processing Applications with the TMS320 Family (literature numbers SPRA012,

SPRA016, and SPRA017).

A series of DSP textbooks is published by Prentice-Hall and John Wiley & Sons to support digital signal

processing research and education. The TMS320 newsletter, Details on Signal Processing, is published

quarterly and distributed to update TMS320 customers on product information.

Information regarding TI DSP products is also available on the Worldwide Web at http://www.ti.com uniform

resource locator (URL).

TI is a trademark of Texas Instruments Incorporated.

36

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320UC5409

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS101A – APRIL 1999 – REVISED AUGUST 1999

†

absolute maximum ratings over specified temperature range (unless otherwise noted)

Supply voltage I/O range, DV ‡ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 4.0 V

DD

‡

Supply voltage core range, CV

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 2.0 V

Input voltage range, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 4.5 V

Output voltage range, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 4.5 V

Operating case temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 100°C

I

O

C

Storage temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to 150°C

stg

†

‡

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

All voltage values are with respect to V

.

SS

recommended operating conditions

MIN

1.71

NOM

MAX

3.6

UNIT

V

DV

CV

Device supply voltage, I/O

Device supply voltage, core

DD

1.8

0

1.98

V

SS

Supply voltage, GND

V

RS, INTn, NMI, X2/CLKIN, BIO, BCLKR0,

BCLKR1, BCLKX0, BCLKX1, HCS, HDS1,

2.2

2.0

DV

+ 0.3

DD

V

IH

High-level input voltage, I/O

HDS2, TCK, CLKMDn, DV

= 3.3 0.3 V

DD

All other inputs

+ 0.3

RS, INTn, NMI, X2/CLKIN, BIO, BCLKR0,

BCLKR1, BCLKX0, BCLKX1, HCS, HDS1,

–0.3

0.6

V

IL

Low-level input voltage

V

HDS2, TCK, CLKMDn, DV

= 3.3 0.3 V

DD

All other inputs

0.8

I

High-level output current

Low-level output current

Operating case temperature

–300

1.5

µA

mA

°C

OH

OL

T

–40

100

C

37

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320UC5409

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS101A – APRIL 1999 – REVISED AUGUST 1999

electrical characteristics over recommended operating case temperature range (unless otherwise

noted)

†

TYP

PARAMETER

High-level output voltage

Low-level output voltage

TEST CONDITIONS

MIN

2.4

MAX

UNIT

V

I

= MAX

V

OH

0.4

V

OL

Bus holders enabled, DV

DD

= MAX,

Input current for

outputs in high

impedance

D[15:0], HD[7:0]

–175

175

V = V

to DV

I

SS

DD

I

IZ

µA

All other inputs

X2/CLKIN

DV

= MAX, V = V

to DV

DD

–5

5

DD

O

SS

–40

40

TRST

With internal pulldown

–5

300

Input current

HPIENA

(V = V

I

SS

I

µA

to DV

)

DD

With internal pullups,

HPIENA = 0

TMS, TCK, TDI, HPI

–300

–5

5

All other input-only pins

I

Supply current, core CPU

Supply current, pins

CV

DV

= 1.8 V, f

= 3.3 V, f

= 40 MHz,

T

= 25°C

45

mA

DDC

DD

clock

C

30

5

mA

DDP

IDLE2

IDLE3

PLL × 1 mode, 40 MHz input

Divide-by-two mode, CLKIN stopped

Supply current,

standby

I

DD

5

µA

C

Input capacitance

Output capacitance

5

pF

i

o

†

‡

§

All values are typical unless otherwise specified.

HPI input signals except for HPIENA.

Clock mode: PLL × 1 with external source

PARAMETER MEASUREMENT INFORMATION

I

OL

50 Ω

Output

Under

Test

Tester Pin

Electronics

V

Load

C

T

I

OH

Where:

I

= 1.5 mA (all outputs)

= 300 µA (all outputs)

= 1.5 V

OL

OH

V

Load

C

= 40 pF typical load circuit capacitance

T

Figure 12. 3.3-V Test Load Circuit

38

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320UC5409

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS101A – APRIL 1999 – REVISED AUGUST 1999

internal oscillator with external crystal

The internal oscillator is enabled by connecting a crystal across X1 and X2/CLKIN. The frequency of CLKOUT

is a multiple of the oscillator frequency. The multiply ratio is determined by the bit settings in the CLKMD register.

The crystal should be in fundamental-mode operation, and parallel resonant, with an effective series resistance

of 30 Ω and power dissipation of 1 mW. The circuit shown in Figure 13representsfundamental-modeoperation.

recommended operating conditions of internal oscillator with external crystal (see Figure 13)

MIN NOM

MAX

UNIT

MHz

pF

f

Input clock frequency

10

20

clock

C1, C2

10

X1

X2/CLKIN

Crystal

C1

C2

Figure 13. Internal Oscillator With External Crystal

39

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320UC5409

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS101A – APRIL 1999 – REVISED AUGUST 1999

divide-by-two clock option

The frequency of the external reference clock provided at the X2/CLKIN pin can be divided by a factor of two

to generate the internal machine cycle. The selection of the clock mode is described in the clock generator

section.

The external frequency injected must conform to specifications listed in the timing requirements table.

†

switching characteristics over recommended operating conditions [H = 0.5t

Figure 14, and the recommended operating conditions table)

] (see Figure 13,

c(CO)

PARAMETER

MIN

TYP

MAX

UNIT

ns

‡

10

†

t

Cycle time, CLKOUT

2t

c(CI)

6

c(CO)

t

Delay time, X2/CLKIN high to CLKOUT high/low

Fall time, CLKOUT

3

10

ns

d(CIH-CO)

t

2

ns

f(CO)

t

Rise time, CLKOUT

ns

r(CO)

Pulse duration, CLKOUT low

Pulse duration, CLKOUT high

H–2

H–1

H

ns

w(COL)

w(COH)

ns

†

This device utilizes a fully static design and therefore can operate with t

approaching 0 Hz.

It is recommended that the PLL clocking option be used for maximum frequency operation.

approaching ∞. The device is characterized at frequencies

c(CI)

‡

timing requirements (see Figure 14)

MIN

MAX

UNIT

ns

†

t

Cycle time, X2/CLKIN

Fall time, X2/CLKIN

Rise time, X2/CLKIN

5

c(CI)

f(CI)

r(CI)

1

ns

†

This device utilizes a fully static design and therefore can operate with t

approaching 0 Hz.

approaching ∞. The device is characterized at frequencies

c(CI)

t

r(CI)

t

f(CI)

t

c(CI)

X2/CLKIN

CLKOUT

t

w(COH)

t

f(CO)

t

c(CO)

t

r(CO)

t

d(CIH-CO)

t

w(COL)

Figure 14. External Divide-by-Two Clock Timing

40

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320UC5409

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS101A – APRIL 1999 – REVISED AUGUST 1999

multiply-by-N clock option

The frequency of the external reference clock provided at the X2/CLKIN pin can be multiplied by a factor of N

to generate the internal machine cycle. The selection of the clock mode and the value of N is described in the

clock generator section.

The external frequency injected must conform to specifications listed in the timing requirements table.

switching characteristics over recommended operating conditions [H = 0.5t

(see Figure 13 and Figure 15)

]

c(CO)

PARAMETER

MIN

10

4

TYP

MAX

UNIT

ns

s

†

t

Cycle time, CLKOUT

t

c(CO)

c(CI)/N

10

t

Delay time, X2/CLKIN high/low to CLKOUT high/low

Fall time, CLKOUT

16

d(CI-CO)

t

2

f(CO)

r(CO)

w(COL)

w(COH)

p

t

Rise time, CLKOUT

Pulse duration, CLKOUT low

Pulse duration, CLKOUT high

Transitory phase, PLL lock up time

H–2

H–1

H

–

†

N = Multiplication factor

†

timing requirements (see Figure 15)

MIN

MAX

UNIT

Integer PLL multiplier N (N = 1–15)

PLL multiplier N = x.5

10N 200N

10N 100N

t

Cycle time, X2/CLKIN

ns

c(CI)

PLL multiplier N = x.25, x.75

t

Fall time, X2/CLKIN

Rise time, X2/CLKIN

8

ns

f(CI)

r(CI)

†

N = Multiplication factor

t

f(CI)

t

r(CI)

t

c(CI)

X2/CLKIN

t

d(CI-CO)

t

f(CO)

t

w(COH)

t

c(CO)

t

w(COL)

t

tp

r(CO)

Unstable

CLKOUT

Figure 15. External Multiply-by-One Clock Timing

41

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320UC5409

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS101A – APRIL 1999 – REVISED AUGUST 1999

memory and parallel I/O interface timing

switching characteristics over recommended operating conditions for a memory read

†

(MSTRB = 0) (see Figure 16)

PARAMETER

MIN

0

MAX

UNIT

ns

‡

t

Delay time, CLKOUT low to address valid

3

d(CLKL-A)

§

Delay time, CLKOUT high (transition) to address valid

0

ns

d(CLKH-A)

t

Delay time, CLKOUT low to MSTRB low

0

ns

d(CLKL-MSL)

t

Delay time, CLKOUT low to MSTRB high

0

ns

d(CLKL-MSH)

‡

t

Hold time, address valid after CLKOUT low

0

ns

h(CLKL-A)R

§

t

Hold time, address valid after CLKOUT high

0

ns

h(CLKH-A)R

†

‡

§

Address, PS, and DS timings are all included in timings referenced as address.

In the case of a memory read preceded by a memory read

In the case of a memory read preceded by a memory write

†

timing requirements for a memory read (MSTRB = 0) [H = 0.5 t

] (see Figure 16)

c(CO)

MIN

MAX

UNIT

ns

t

Access time, read data access from address valid

Access time, read data access from MSTRB low

Setup time, read data before CLKOUT low

Hold time, read data after CLKOUT low

2H–10

a(A)M

ns

a(MSTRBL)

su(D)R

4

0

ns

h(D)R

Hold time, read data after address invalid

Hold time, read data after MSTRB high

ns

h(A-D)R

ns

h(D)MSTRBH

†

Address, PS, and DS timings are all included in timings referenced as address.

42

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320UC5409

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS101A – APRIL 1999 – REVISED AUGUST 1999

memory and parallel I/O interface timing (continued)

CLKOUT

t

d(CLKL-A)

t

h(CLKL-A)R

A[19:0]

t

h(A-D)R

t

su(D)R

t

a(A)M

t

h(D)R

D[15:0]

t

h(D)MSTRBH

t

d(CLKL-MSL)

t

d(CLKL-MSH)

t

a(MSTRBL)

MSTRB

R/W

PS, DS

Figure 16. Memory Read (MSTRB = 0)

43

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320UC5409

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS101A – APRIL 1999 – REVISED AUGUST 1999

memory and parallel I/O interface timing (continued)

switching characteristics over recommended operating conditions for a memory write

†

(MSTRB = 0) [H = 0.5 t

] (see Figure 17)

c(CO)

PARAMETER

MIN

0

MAX

UNIT

ns

‡

t

Delay time, CLKOUT high to address valid

3

d(CLKH-A)

§

Delay time, CLKOUT low to address valid

Delay time, CLKOUT low to MSTRB low

Delay time, CLKOUT low to data valid

Delay time, CLKOUT low to MSTRB high

Delay time, CLKOUT high to R/W low

Delay time, CLKOUT high to R/W high

Delay time, R/W low to MSTRB low

0

3

ns

d(CLKL-A)

t

0

3

ns

d(CLKL-MSL)

t

0

5

ns

d(CLKL-D)W

t

– 2

H – 2

0

3

ns

d(CLKL-MSH)

t

3

ns

d(CLKH-RWL)

t

ns

d(CLKH-RWH)

t

H + 2

3

ns

d(RWL-MSTRBL)

‡

t

Hold time, address valid after CLKOUT high

ns

h(A)W

§

t

Hold time, write data valid after MSTRB high

Pulse duration, MSTRB low

H–3 H+3

ns

h(D)MSH

w(SL)MS

su(A)W

2H–4

Setup time, address valid before MSTRB low

Setup time, write data valid before MSTRB high

Enable time, data bus driven after R/W low

Disable time, R/W high to data bus high impedance

2H–4

§

2H–5 2H+5

H–5

su(D)MSH

en(D–RWL)

dis(RWH–D)

0

†

‡

§

Address, PS, and DS timings are all included in timings referenced as address.

In the case of a memory write preceded by a memory write

In the case of a memory write preceded by an I/O cycle

44

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320UC5409

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS101A – APRIL 1999 – REVISED AUGUST 1999

memory and parallel I/O interface timing (continued)

CLKOUT

A[19:0]

D[15:0]

MSTRB

R/W

t

d(CLKH-A)

t

d(CLKL-A)

t

h(A)W

t

d(CLKL-D)W

t

h(D)MSH

t

su(D)MSH

t

d(CLKL-MSL)

t

dis(RWH-D)

t

d(CLKL-MSH)

t

su(A)W

t

d(CLKH-RWL)

d(CLKH-RWH)

t

w(SL)MS

en(D-RWL)

t

d(RWL-MSTRBL)

PS, DS

Figure 17. Memory Write (MSTRB = 0)

45

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320UC5409

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS101A – APRIL 1999 – REVISED AUGUST 1999

memory and parallel I/O interface timing (continued)

switching characteristics over recommended operating conditions for a parallel I/O port read

†

(IOSTRB = 0) (see Figure 18)

PARAMETER

Delay time, CLKOUT low to address valid

Delay time, CLKOUT high to IOSTRB low

Delay time, CLKOUT high to IOSTRB high

Hold time, address after CLKOUT low

MIN

0

MAX

UNIT

ns

t

3

d(CLKL-A)

t

0

ns

d(CLKH-ISTRBL)

t

0

ns

d(CLKH-ISTRBH)

t

0

ns

h(A)IOR

†

Address and IS timings are included in timings referenced as address.

†

timing requirements for a parallel I/O port read (IOSTRB = 0) [H = 0.5 t

] (see Figure 18)

c(CO)

MIN

MAX

3H–10

2H–10

UNIT

ns

t

Access time, read data access from address valid

Access time, read data access from IOSTRB low

Setup time, read data before CLKOUT high

Hold time, read data after CLKOUT high

a(A)IO

ns

a(ISTRBL)IO

su(D)IOR

4

0

ns

h(D)IOR

Hold time, read data after IOSTRB high

ns

h(ISTRBH-D)R

†

Address and IS timings are included in timings referenced as address.

CLKOUT

t

h(A)IOR

d(CLKL-A)

A[19:0]

t

h(D)IOR

t

su(D)IOR

t

a(A)IO

D[15:0]

t

h(ISTRBH-D)R

d(CLKH-ISTRBH)

t

a(ISTRBL)IO

t

d(CLKH-ISTRBL)

IOSTRB

R/W

IS

Figure 18. Parallel I/O Port Read (IOSTRB = 0)

46

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320UC5409

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS101A – APRIL 1999 – REVISED AUGUST 1999

memory and parallel I/O interface timing (continued)

switching characteristics over recommended operating conditions for a parallel I/O port write

†

(IOSTRB = 0) [H = 0.5 t

] (see Figure 19)

c(CO)

PARAMETER

MIN MAX

UNIT

ns

t

Delay time, CLKOUT low to address valid

Delay time, CLKOUT high to IOSTRB low

Delay time, CLKOUT high to write data valid

Delay time, CLKOUT high to IOSTRB high

Delay time, CLKOUT low to R/W low

0

3

d(CLKL-A)

t

ns

d(CLKH-ISTRBL)

t

H–5

0

H+3

3

ns

d(CLKH-D)IOW

t

ns

d(CLKH-ISTRBH)

t

0

3

ns

d(CLKL-RWL)

d(CLKL-RWH)

t

Delay time, CLKOUT low to R/W high

0

3

ns

Hold time, address valid after CLKOUT low

Hold time, write data after IOSTRB high

Setup time, write data before IOSTRB high

Setup time, address valid before IOSTRB low

0

H–3

3

H+3

H+1

H+3

ns

h(A)IOW

h(D)IOW

su(D)IOSTRBH

su(A)IOSTRBL

†

Address and IS timings are included in timings referenced as address.

CLKOUT

t

su(A)IOSTRBL

t

h(A)IOW

t

d(CLKL-A)

A[19:0]

t

d(CLKH-D)IOW

t

h(D)IOW

D[15:0]

t

d(CLKH-ISTRBL)

t

d(CLKH-ISTRBH)

t

su(D)IOSTRBH

t

IOSTRB

R/W

t

d(CLKL-RWL)

d(CLKL-RWH)

IS

Figure 19. Parallel I/O Port Write (IOSTRB = 0)

47

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320UC5409

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS101A – APRIL 1999 – REVISED AUGUST 1999

ready timing for externally generated wait states

†

timing requirements for externally generated wait states [H = 0.5 t

Figure 22, and Figure 23)

] (see Figure 20, Figure 21,

c(CO)

MIN

5

MAX

UNIT

ns

t

Setup time, READY before CLKOUT low

Hold time, READY after CLKOUT low

su(RDY)

0

ns

h(RDY)

‡

Valid time, READY after MSTRB low

4H–8

5H–8

ns

v(RDY)MSTRB

h(RDY)MSTRB

v(RDY)IOSTRB

h(RDY)IOSTRB

v(MSCL)

‡

Hold time, READY after MSTRB low

4H

ns

‡

Valid time, READY after IOSTRB low

ns

‡

Hold time, READY after IOSTRB low

5H

0

ns

Valid time, MSC low after CLKOUT low

Valid time, MSC high after CLKOUT low

3

ns

0

ns

v(MSCH)

†

The hardware wait states can be used only in conjunction with the software wait states to extend the bus cycles. To generate wait states using

READY, at least two software wait states must be programmed.

These timings are included for reference only. The critical timings for READY are those referenced to CLKOUT.

‡

CLKOUT

A[19:0]

t

su(RDY)

t

h(RDY)

READY

MSTRB

MSC

t

v(RDY)MSTRB

t

h(RDY)MSTRB

t

v(MSCH)

t

v(MSCL)

Wait State

Generated

by READY

Wait States

Generated Internally

Figure 20. Memory Read With Externally Generated Wait States

48

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320UC5409

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS101A – APRIL 1999 – REVISED AUGUST 1999

ready timing for externally generated wait states (continued)

CLKOUT

A[19:0]

D[15:0]

READY

MSTRB

MSC

t

h(RDY)

t

su(RDY)

t

v(RDY)MSTRB

t

h(RDY)MSTRB

t

v(MSCH)

t

v(MSCL)

Wait States

Generated Internally

Wait State Generated

by READY

Figure 21. Memory Write With Externally Generated Wait States

49

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320UC5409

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS101A – APRIL 1999 – REVISED AUGUST 1999

ready timing for externally generated wait states (continued)

CLKOUT

A[19:0]

t

h(RDY)

t

su(RDY)

READY

IOSTRB

MSC

t

v(RDY)IOSTRB

t

h(RDY)IOSTRB

t

v(MSCH)

t

v(MSCL)

Wait State Generated

by READY

Wait

States

Generated

Internally

Figure 22. I/O Read With Externally Generated Wait States

50

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320UC5409

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS101A – APRIL 1999 – REVISED AUGUST 1999

ready timing for externally generated wait states (continued)

CLKOUT

A[19:0]

D[15:0]

READY

t

h(RDY)

t

su(RDY)

t

v(RDY)IOSTRB

t

h(RDY)IOSTRB

IOSTRB

MSC

t

v(MSCH)

t

v(MSCL)

Wait State Generated

by READY

Wait States

Generated

Internally

Figure 23. I/O Write With Externally Generated Wait States

51

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320UC5409

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS101A – APRIL 1999 – REVISED AUGUST 1999

HOLD and HOLDA timings

switching characteristics over recommended operating conditions for memory control signals

and HOLDA, [H = 0.5 t

] (see Figure 24)

c(CO)

PARAMETER

MIN

MAX

5

UNIT

ns

t

Disable time, address, PS, DS, IS high impedance from CLKOUT low

Disable time, R/W high impedance from CLKOUT low

Disable time, MSTRB, IOSTRB high impedance from CLKOUT low

Enable time, address, PS, DS, IS from CLKOUT low

dis(CLKL-A)

dis(CLKL-RW)

dis(CLKL-S)

en(CLKL-A)

en(CLKL-RW)

en(CLKL-S)

5

ns

5

ns

2H+5

ns

Enable time, R/W enabled from CLKOUT low

ns

Enable time, MSTRB, IOSTRB enabled from CLKOUT low

2

0

ns

5

3

ns

Valid time, HOLDA low after CLKOUT low

t

v(HOLDA)

– 2

2H–3

Valid time, HOLDA high after CLKOUT low

Pulse duration, HOLDA low duration

w(HOLDA)

timing requirements for memory control signals and HOLDA, [H = 0.5 t

] (see Figure 24)

c(CO)

MIN

4H+10

10

MAX

UNIT

ns

t

Pulse duration, HOLD low

w(HOLD)

Setup time, HOLD low/high before CLKOUT low

ns

su(HOLD)

CLKOUT

t

su(HOLD)

t

w(HOLD)

HOLD

t

v(HOLDA)

t

w(HOLDA)

HOLDA

dis(CLKL-A)

t

en(CLKL-A)

A[19:0]

PS, DS, IS

D[15:0]

R/W

t

dis(CLKL-RW)

dis(CLKL-S)

en(CLKL-RW)

t

en(CLKL-S)

MSTRB

IOSTRB

t

en(CLKL-S)

Figure 24. HOLD and HOLDA Timings (HM = 1)

52

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320UC5409

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS101A – APRIL 1999 – REVISED AUGUST 1999

reset, BIO, interrupt, and MP/MC timings

timing requirements for reset, BIO, interrupt, and MP/MC [H = 0.5 t

and Figure 27)

] (see Figure 25, Figure 26,

c(CO)

MIN

0

MAX

UNIT

ns

t

Hold time, RS after CLKOUT low

Hold time, BIO after CLKOUT low

Hold time, INTn, NMI, after CLKOUT low

Hold time, MP/MC after CLKOUT low

h(RS)

0

h(BIO)

†

0

h(INT)

0

h(MPMC)

w(RSL)

‡§

Pulse duration, RS low

4H+5

2H+5

4H

2H+7

4H

2H+7

4H

8

Pulse duration, BIO low, synchronous

Pulse duration, BIO low, asynchronous

w(BIO)S

w(BIO)A

w(INTH)S

w(INTH)A

w(INTL)S

w(INTL)A

w(INTL)WKP

su(RS)

Pulse duration, INTn, NMI high (synchronous)

Pulse duration, INTn, NMI high (asynchronous)

Pulse duration, INTn, NMI low (synchronous)

Pulse duration, INTn, NMI low (asynchronous)

Pulse duration, INTn, NMI low for IDLE2/IDLE3 wakeup

¶

Setup time, RS before X2/CLKIN low

5

Setup time, BIO before CLKOUT low

8

10

su(BIO)

Setup time, INTn, NMI, RS before CLKOUT low

Setup time, MP/MC before CLKOUT low

8

su(INT)

8

su(MPMC)

†

The external interrupts (INT0–INT3, NMI) are synchronized to the core CPU by way of a two-flip-flop synchronizer which samples these inputs

with consecutive falling edges of CLKOUT. The input to the interrupt pins is required to represent a 1-0-0 sequence at the timing that is

corresponding to three CLKOUT sampling sequences.

If the PLL mode is selected, then at power-on sequence, or at wakeup from IDLE3, RS must be held low for at least 50 µs to ensure

synchronization and lock-in of the PLL.

‡

§

¶

Note that RS may cause a change in clock frequency, therefore changing the value of H.

Divide-by-two mode

53

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320UC5409

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS101A – APRIL 1999 – REVISED AUGUST 1999

reset, BIO, interrupt, and MP/MC timings (continued)

X2/CLKIN

t

su(RS)

t

w(RSL)

RS, INTn, NMI

t

su(INT)

t

h(RS)

CLKOUT

t

su(BIO)

t

h(BIO)

BIO

t

w(BIO)S

Figure 25. Reset and BIO Timings

CLKOUT

t

su(INT)

h(INT)

INTn, NMI

t

w(INTH)A

t

w(INTL)A

Figure 26. Interrupt Timing

CLKOUT

RS

t

h(MPMC)

t

su(MPMC)

MP/MC

Figure 27. MP/MC Timing

54

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320UC5409

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS101A – APRIL 1999 – REVISED AUGUST 1999

instruction acquisition (IAQ), interrupt acknowledge (IACK), external flag (XF), and TOUT timings

switching characteristics over recommended operating conditions for IAQ and IACK

[H = 0.5 t

] (see Figure 28)

c(CO)

PARAMETER

MIN

0

MAX

UNIT

ns

t

Delay time, CLKOUT low to IAQ low

Delay time, CLKOUT low to IAQ high

Delay time, address valid to IAQ low

Delay time, CLKOUT low to IACK low

Delay time , CLKOUT low to IACK high

Delay time, address valid to IACK low

Hold time, IAQ high after address invalid

Hold time, IACK high after address invalid

Pulse duration, IAQ low

3

4

3

d(CLKL-IAQL)

t

0

ns

d(CLKL-IAQH)

d(A)IAQ

t

ns

t

0

ns

d(CLKL-IACKL)

t

ns

d(CLKL-IACKH)

d(A)IACK

h(A)IAQ

t

ns

0

ns

h(A)IACK

w(IAQL)

2H–5

ns

Pulse duration, IACK low

ns

w(IACKL)

CLKOUT

A[19:0]

IAQ

t

d(CLKL-IAQH)

d(CLKL-IAQL)

t

h(A)IAQ

t

d(A)IAQ

t

w(IAQL)

t

d(CLKL-IACKH)

d(CLKL-IACKL)

t

h(A)IACK

t

d(A)IACK

t

w(IACKL)

IACK

MSTRB

Figure 28. IAQ and IACK Timings

55

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320UC5409

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS101A – APRIL 1999 – REVISED AUGUST 1999

instruction acquisition (IAQ), interrupt acknowledge (IACK), external flag (XF), and TOUT timings

(continued)

switching characteristics over recommended operating conditions for XF and TOUT

[H = 0.5 t

] (see Figure 29 and Figure 30)

c(CO)

PARAMETER

MIN

MAX UNIT

Delay time, CLKOUT low to XF high

Delay time, CLKOUT low to XF low

Delay time, CLKOUT low to TOUT high

Delay time, CLKOUT low to TOUT low

Pulse duration, TOUT

0

3

t

ns

3

d(XF)

0

t

0

3

ns

d(TOUTH)

d(TOUTL)

w(TOUT)

2H–10

CLKOUT

t

d(XF)

XF

Figure 29. XF Timing

CLKOUT

TOUT

t

d(TOUTL)

d(TOUTH)

t

w(TOUT)

Figure 30. TOUT Timing

56

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320UC5409

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS101A – APRIL 1999 – REVISED AUGUST 1999

multichannel buffered serial port timing

timing requirements for McBSP [H=0.5t

†

] (see Figure 31 and Figure 32)

c(CO)

MIN

MAX

UNIT

ns

t

Cycle time, BCLKR/X

BCLKR/X ext

4H

c(BCKRX)

Pulse duration, BCLKR/X high or BCLKR/X low

BCLKR/X ext

BCLKR int

BCLKR ext

BCLKR int

BCLKR ext

BCLKR int

BCLKR ext

BCLKR int

BCLKR ext

BCLKX int

BCLKX ext

BCLKX int

BCLKX ext

BCLKR/X ext

2H–1

ns

w(BCKRX)

8

1

0

3

5

0

4

7

0

3

t

Setup time, external BFSR high before BCLKR low

ns

su(BFRH-BCKRL)

h(BCKRL-BFRH)

su(BDRV-BCKRL)

h(BCKRL-BDRV)

su(BFXH-BCKXL)

h(BCKXL-BFXH)

Hold time, external BFSR high after BCLKR low

Setup time, BDR valid before BCLKR low

Hold time, BDR valid after BCLKR low

Setup time, external BFSX high before BCLKX low

Hold time, external BFSX high after BCLKX low

t

Rise time, BCKR/X

Fall time, BCKR/X

8

ns

r(BCKRX)

f(BCKRX)

†

CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that signal are also inverted.

†

switching characteristics for McBSP [H=0.5t

] (see Figure 31 and Figure 32)

c(CO)

PARAMETER

MIN

MAX

UNIT

ns

t

Cycle time, BCLKR/X

BCLKR/X int

4H

c(BCKRX)

‡

Pulse duration, BCLKR/X high

D – 2

C – 2

D + 2

ns

w(BCKRXH)

‡

t

Pulse duration, BCLKR/X low

BCLKR/X int

BCLKR int

BCLKR ext

BCLKX int

BCLKX ext

BCLKX int

BCLKX ext

BCLKX int

BCLKX ext

BFSX int

C + 2

ns

w(BCKRXL)

–2

3

2

9

4

t

Delay time, BCLKR high to internal BFSR valid

Delay time, BCLKX high to internal BFSX valid

d(BCKRH-BFRV)

0

t

ns

d(BCKXH-BFXV)

dis(BCKXH-BDXHZ)

d(BCKXH-BDXV)

d(BFXH-BDXV)

8

11

4

–1

3

Disable time, BCLKX high to BDX high impedance following last data

bit of transfer

9

§

0

7

Delay time, BCLKX high to BDX valid

3

§

11

3

–1

Delay time, BFSX high to BDX valid

ONLY applies when in data delay 0 (XDATDLY = 00b) mode

BFSX ext

3

13

†

‡

CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that signal are also inverted.

T = BCLKRX period = (1 + CLKGDV) * 2H

C = BCLKRX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * 2H when CLKGDV is even

D = BCLKRX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) * 2H when CLKGDV is even

Minimum delay times also represent minimum output hold times.

§

57

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320UC5409

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS101A – APRIL 1999 – REVISED AUGUST 1999

multichannel buffered serial port timing (continued)

t

c(BCKRX)

w(BCKRXH)

w(BCKRXL)

t

r(BCKRX)

BCLKR

BFSR (int)

BFSR (ext)

t

d(BCKRH–BFRV)

t

d(BCKRH–BFRV)

t

r(BCKRX)

tsu(BFRH–BCKRL)

t

h(BCKRL–BFRH)

t

h(BCKRL–BDRV)

(n–2)

t

su(BDRV–BCKRL)

t

BDR

Bit (n–1)

(n–3)

(n–4)

(n–3)

(RDATDLY=00b)

su(BDRV–BCKRL)

t

h(BCKRL–BDRV)

(n–2)

BDR

(RDATDLY=01b)

Bit (n–1)

t

su(BDRV–BCKRL)

h(BCKRL–BDRV)

(n–2)

BDR

(RDATDLY=10b)

Bit (n–1)

Figure 31. McBSP Receive Timings

t

c(BCKRX)

w(BCKRXH)

t

r(BCKRX)

t

f(BCKRX)

t

w(BCKRXL)

BCLKX

BFSX (int)

BFSX (ext)

t

d(BCKXH–BFXV)

t

d(BCKXH–BFXV)

t

su(BFXH–BCKXL)

t

h(BCKXL–BFXH)

t

d(BDFXH–BDXV)

Bit (n–1)

t

d(BCKXH–BDXV)

(n–3)

e(BDFXH–BDX)

BDX

Bit 0

(n–2)

(n–4)

(n–3)

(n–2)

(XDATDLY=00b)

d(BCKXH–BDXV)

(n–2)

t

e(BCKXH–BDX)

Bit (n–1)

BDX

(XDATDLY=01b)

Bit 0

t

d(BCKXH–BDXV)

Bit (n–1)

t

dis(BCKXH–BDXHZ)

Bit 0

t

e(BCKXH–BDX)

BDX

(XDATDLY=10b)

Figure 32. McBSP Transmit Timings

58

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320UC5409

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS101A – APRIL 1999 – REVISED AUGUST 1999

multichannel buffered serial port timing (continued)

timing requirements for McBSP general-purpose I/O (see Figure 33)

MIN

9

MAX

UNIT

ns

†

Setup time, BGPIOx input mode before CLKOUT high

t

su(BGPIO-COH)

†

Hold time, BGPIOx input mode after CLKOUT high

0

ns

h(COH-BGPIO)

†

BGPIOx refers to BCLKRx, BFSRx, BDRx, BCLKXx, or BFSXx when configured as a general-purpose input.

switching characteristics for McBSP general-purpose I/O (see Figure 33)

PARAMETER

MIN

MAX

UNIT

‡

t

Delay time, CLKOUT high to BGPIOx output mode

0

5

ns

d(COH-BGPIO)

‡

BGPIOx refers to BCLKRx, BFSRx, BCLKXx, BFSXx, or BDXx when configured as a general-purpose output.

t

su(BGPIO-COH)

d(COH-BGPIO)

CLKOUT

t

h(COH-BGPIO)

BGPIOx Input

†

Mode

BGPIOx Output

‡

Mode

†

‡

BGPIOx refers to BCLKRx, BFSRx, BDRx, BCLKXx, or BFSXx when configured as a general-purpose input.

BGPIOx refers to BCLKRx, BFSRx, BCLKXx, BFSXx, or BDXx when configured as a general-purpose output.

Figure 33. McBSP General-Purpose I/O Timings

59

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320UC5409

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS101A – APRIL 1999 – REVISED AUGUST 1999

multichannel buffered serial port timing (continued)

†

timing requirements for McBSP as SPI master or slave: [H=0.5t

(see Figure 34)

] CLKSTP = 10b, CLKXP = 0

c(CO)

MASTER

SLAVE

MIN MAX

UNIT

MIN

9

MAX

t

Setup time, BDR valid before BCLKX low

Hold time, BDR valid after BCLKX low

– 12H

ns

su(BDRV-BCKXL)

0

5 + 12H

10

h(BCKXL-BDRV)

t

Setup time, BFSX low before BCLKX low

Cycle time, BCLKX

ns

su(BFXL-BCKXL)

32H

c(BCKX)

†

For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.

switching characteristics for McBSP as SPI master or slave: [H=0.5t

] CLKSTP = 10b,

c(CO)

†

CLKXP = 0 (see Figure 34)

‡

MASTER

SLAVE

UNIT

PARAMETER

MIN MAX

MIN

MAX

§

t

Hold time, BFSX low after BCLKX low

T – 3 T + 4

C – 5 C + 3

ns

h(BCKXL-BFXL)

d(BFXL-BCKXH)

d(BCKXH-BDXV)

¶

Delay time, BFSX low to BCLKX high

Delay time, BCLKX high to BDX valid

–2

4

6H +54 10H + 15

Disable time, BDX high impedance following last data bit from

BCLKX low

t

C – 2 C + 3

ns

dis(BCKXL-BDXHZ)

Disable time, BDX high impedance following last data bit from

BFSX high

t

2H+ 4

6H + 17

8H + 17

ns

dis(BFXH-BDXHZ)

Delay time, BFSX low to BDX valid

4H + 2

d(BFXL-BDXV)

†

‡

For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.

T = BCLKX period = (1 + CLKGDV) * 2H

C = BCLKX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * 2H when CLKGDV is even

FSRP = FSXP = 1. As a SPI master, BFSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on BFSX

and BFSR is inverted before being used internally.

§

CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP

CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP

BFSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock

(BCLKX).

¶

MSB

LSB

BCLKX

BFSX

t

h(BCKXL-BFXL)

t

d(BFXL-BCKXH)

t

dis(BFXH-BDXHZ)

t

d(BFXL-BDXV)

t

d(BCKXH-BDXV)

(n-2)

dis(BCKXL-BDXHZ)

BDX

BDR

Bit 0

Bit(n-1)

(n-3)

(n-4)

t

su(BDRV-BCLXL)

t

h(BCKXL-BDRV)

Bit 0

Bit(n-1)

(n-2)

(n-3)

(n-4)

Figure 34. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0

60

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320UC5409

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS101A – APRIL 1999 – REVISED AUGUST 1999

multichannel buffered serial port timing (continued)

†

timing requirements for McBSP as SPI master or slave: [H=0.5t

(see Figure 35)

] CLKSTP = 11b, CLKXP = 0

c(CO)

MASTER

SLAVE

MIN MAX

UNIT

MIN

12

4

MAX

t

Setup time, BDR valid before BCLKX low

Hold time, BDR valid after BCLKX high

2 – 12H

ns

su(BDRV-BCKXL)

5 + 12H

10

h(BCKXH-BDRV)

t

Setup time, BFSX low before BCLKX high

Cycle time, BCLKX

ns

su(BFXL-BCKXH)

32H

c(BCKX)

†

For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.

switching characteristics for McBSP as SPI master or slave: [H=0.5t

CLKXP = 0 (see Figure 35)

] CLKSTP = 11b,

c(CO)

†

‡

MASTER

SLAVE

UNIT

PARAMETER

MIN MAX

MIN

MAX

§

t

Hold time, BFSX low after BCLKX low

C – 3 C +43

T – 5 T + 3

ns

h(BCKXL-BFXL)

d(BFXL-BCKXH)

d(BCKXL-BDXV)

¶

Delay time, BFSX low to BCLKX high

Delay time, BCLKX low to BDX valid

–2

6

6H + 5 10H + 15

6H + 3 10H + 17

Disable time, BDX high impedance following last data bit from

BCLKX low

t

–2

4

ns

dis(BCKXL-BDXHZ)

t

Delay time, BFSX low to BDX valid

D – 2 D + 4

4H – 2

8H + 17

d(BFXL-BDXV)

†

‡

For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.

T = BCLKX period = (1 + CLKGDV) * 2H

C = BCLKX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * 2H when CLKGDV is even

D = BCLKX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) * 2H when CLKGDV is even

FSRP = FSXP = 1. As a SPI master, BFSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on BFSX

and BFSR is inverted before being used internally.

§

CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP

CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP

BFSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock

(BCLKX).

¶

MSB

LSB

BCLKX

t

d(BFXL-BCKXH)

h(BCKXL-BFXL)

BFSX

t

d(BCKXL-BDXV)

d(BFXL-BDXV)

dis(BCKXL-BDXHZ)

BDX

Bit 0

Bit(n-1)

(n-2)

(n-3)

(n-4)

t

su(BDRV-BCKXL)

t

h(BCKXH-BDRV)

BDR

Bit 0

(n-2)

(n-3)

(n-4)

Figure 35. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0

61

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320UC5409

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS101A – APRIL 1999 – REVISED AUGUST 1999

multichannel buffered serial port timing (continued)

†

timing requirements for McBSP as SPI master or slave: [H=0.5t

(see Figure 36)

] CLKSTP = 10b, CLKXP = 1

c(CO)

MASTER

SLAVE

MIN MAX

UNIT

MIN

12

4

MAX

t

Setup time, BDR valid before BCLKX high

Hold time, BDR valid after BCLKX high

2 – 12H

ns

su(BDRV-BCKXH)

5 + 12H

10

h(BCKXH-BDRV)

t

Setup time, BFSX low before BCLKX low

Cycle time, BCLKX

ns

su(BFXL-BCKXL)

32H

c(BCKX)

†

For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.

switching characteristics for McBSP as SPI master or slave: [H=0.5t

CLKXP = 1 (see Figure 36)

] CLKSTP = 10b,

c(CO)

†

‡

MASTER

SLAVE

UNIT

PARAMETER

MIN MAX

MIN

MAX

§

t

Hold time, BFSX low after BCLKX high

T – 3 T + 4

D – 5 D + 3

ns

h(BCKXH-BFXL)

d(BFXL-BCKXL)

d(BCKXL-BDXV)

¶

Delay time, BFSX low to BCLKX low

Delay time, BCLKX low to BDX valid

–2

6

6H + 5 10H + 15

Disable time, BDX high impedance following last data bit from

BCLKX high

t

D – 2 D + 3

ns

dis(BCKXH-BDXHZ)

Disable time, BDX high impedance following last data bit from

BFSX high

t

2H + 3

4H – 2

6H + 17

8H + 17

ns

dis(BFXH-BDXHZ)

Delay time, BFSX low to BDX valid

d(BFXL-BDXV)

†

‡

For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.

T = BCLKX period = (1 + CLKGDV) * 2H

D = BCLKX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) * 2H when CLKGDV is even

FSRP = FSXP = 1. As a SPI master, BFSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on BFSX

and BFSR is inverted before being used internally.

§

CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP

CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP

BFSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock

(BCLKX).

¶

LSB

MSB

BCLKX

BFSX

t

h(BCKXH-BFXL)

t

d(BFXL-BCKXL)

t

d(BFXL-BDXV)

dis(BFXH-BDXHZ)

t

d(BCKXL-BDXV)

dis(BCKXH-BDXHZ)

BDX

BDR

Bit 0

Bit(n-1)

(n-2)

(n-3)

(n-4)

t

su(BDRV-BCKXH)

h(BCKXH-BDRV)

(n-2)

Bit 0

Bit(n-1)

(n-3)

(n-4)

Figure 36. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1

62

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320UC5409

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS101A – APRIL 1999 – REVISED AUGUST 1999

multichannel buffered serial port timing (continued)

†

timing requirements for McBSP as SPI master or slave: [H=0.5t

(see Figure 37)

] CLKSTP = 11b, CLKXP = 1

c(CO)

MASTER

SLAVE

MIN MAX

UNIT

MIN

9

MAX

t

Setup time, BDR valid before BCLKX low

Hold time, BDR valid after BCLKX low

– 12H

ns

su(BDRV-BCKXL)

0

5 + 12H

10

h(BCKXL-BDRV)

t

Setup time, BFSX low before BCLKX low

Cycle time, BCLKX

ns

su(BFXL-BCKXL)

32H

c(BCKX)

†

For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.

switching characteristics for McBSP as SPI master or slave: [H=0.5t

CLKXP = 1 (see Figure 37)

] CLKSTP = 11b,

c(CO)

†

‡

MASTER

SLAVE

UNIT

PARAMETER

MIN MAX

MIN

MAX

§

t

Hold time, BFSX low after BCLKX high

D – 3 D + 4

T – 5 T + 3

ns

h(BCKXH-BFXL)

d(BFXL-BCKXL)

d(BCKXH-BDXV)

¶

Delay time, BFSX low to BCLKX low

Delay time, BCLKX high to BDX valid

–2

6

6H + 5 10H + 15

6H + 3 10H + 17

Disable time, BDX high impedance following last data bit from

BCLKX high

t

–2

4

ns

dis(BCKXH-BDXHZ)

t

Delay time, BFSX low to BDX valid

C – 2 C + 4

4H – 2

8H + 17

d(BFXL-BDXV)

†

‡

For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.

T = BCLKX period = (1 + CLKGDV) * 2H

C = BCLKX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * 2H when CLKGDV is even

D = BCLKX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) * 2H when CLKGDV is even

FSRP = FSXP = 1. As a SPI master, BFSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on BFSX

and BFSR is inverted before being used internally.

§

CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP

CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP

BFSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock

(BCLKX).

¶

MSB

LSB

BCLKX

t

h(BCKXH-BFXL)

d(BFXL-BCKXL)

BFSX

t

d(BCKXH-BDXV)

(n-2)

dis(BCKXH-BDXHZ)

d(BFXL-BDXV)

BDX

Bit 0

Bit(n-1)

(n-3)

(n-4)

t

su(BDRV-BCKXL)

t

h(BCKXL-BDRV)

BDR

Bit 0

(n-2)

(n-3)

(n-4)

Figure 37. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1

63

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320UC5409

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS101A – APRIL 1999 – REVISED AUGUST 1999

HPI8 timing

switching characteristics over recommended operating conditions†‡§¶ [H = 0.5t

(see Figure 38, Figure 39, Figure 40, and Figure 41)

]

c(CO)

PARAMETER

MIN

MAX

UNIT

t

Enable time, HD driven from DS low

2

17

ns

en(DSL-HD)

Case 1a: Memory accesses when

DMAC is active in 16-bit mode and

18H+18 – t

w(DSH)

t

< 18H

w(DSH)

Case 1b: Memory accesses when

DMAC is active in 16-bit mode and

18

t

≥ 18H

w(DSH)

Case 1c: Memory access when

DMAC is active in 32-bit mode and

26H+18 – t

18

w(DSH)

t

< 26H

Delay time, DS low to HDx valid for

first byte of an HPI read

w(DSH)

t

ns

d(DSL-HDV1)

Case 1d: Memory access when

DMAC is active in 32-bit mode and

t

≥ 26H

w(DSH)

Case 2a: Memory accesses when

DMAC is inactive and t < 10H

10H+18 – t

18

w(DSH)

Case 2b: Memory accesses when

DMAC is inactive and t ≥ 10H

w(DSH)

Case 3: Register accesses

18

5

t

Delay time, DS low to HDx valid for second byte of an HPI read

Hold time, HDx valid after DS high, for a HPI read

Valid time, HDx valid after HRDY high

ns

d(DSL-HDV2)

h(DSH-HDV)R

v(HYH-HDV)

d(DSH-HYL)

3

5

Delay time, DS high to HRDY low (see Note 1)

10

ns

Case 1a: Memory accesses when

DMAC is active in 16-bit mode

18H+10

Case 1b: Memory accesses when

DMAC is active in 32-bit mode

26H+10

10H+10

6H+10

ns

t

Delay time, DS high to HRDY high

d(DSH-HYH)

Case 2: Memory accesses when

DMAC is inactive

Case 3: Write accesses to HPIC

register (see Note 2)

8

ns

t

Delay time, HCS low/high to HRDY low/high

Delay time, CLKOUT high to HRDY high

Delay time, CLKOUT high to HINT change

d(HCS-HRDY)

)

d(COH-HYH

10

d(COH-HTX)

d(COH-GPIO)

Delay time, CLKOUT high to HDx output change. HDx is configured as a

general-purpose output.

t

6

ns

NOTES: 1. The HRDY output is always high when the HCS input is high, regardless of DS timings.

2. This timing applies when writing a one to the DSPINT bit or HINT bit of the HPIC register. All other writes to the HPIC occur

asynchronoulsy, and do not cause HRDY to be deasserted.

DS refers to the logical OR of HCS, HDS1, and HDS2.

HDx refers to any of the HPI data bus pins (HD0, HD1, HD2, etc.).

DMAC stands for direct memory access (DMA) controller. The HPI8 shares the internal DMA bus with the DMAC, thus HPI8 access times are

affected by DMAC activity.

†

‡

§

¶

GPIO refers to the HD pins when they are configured as general-purpose input/outputs.

64

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320UC5409

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS101A – APRIL 1999 – REVISED AUGUST 1999

HPI8 timing (continued)

timing requirements†‡§ (see Figure 38, Figure 39, Figure 40, and Figure 41)

MIN

10

5

MAX

UNIT

ns

t

Setup time, HBIL valid before DS low

Hold time, HBIL valid after DS low

su(HBV-DSL)

ns

h(DSL-HBV)

t

Setup time, HAS low before DS low

5

20

10

5

ns

su(HSL-DSL)

Pulse duration, DS low

w(DSL)

Pulse duration, DS high

w(DSH)

Setup time, HDx valid before DS high, HPI write

Hold time, HDx valid after DS high, HPI write

su(HDV-DSH)

h(DSH-HDV)W

su(GPIO-COH)

h(GPIO-COH)

3

Setup time, HDx input valid before CLKOUT high, HDx configured as general-purpose input

Hold time, HDx input valid after CLKOUT high, HDx configured as general-purpose input

3

0

†

DS refers to the logical OR of HCS, HDS1, and HDS2.

‡

§

HDx refers to any of the HPI data bus pins (HD0, HD1, HD2, etc.).

GPIO refers to the HD pins when they are configured as general-purpose input/outputs.

65

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320UC5409

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS101A – APRIL 1999 – REVISED AUGUST 1999

HPI8 timing (continued)

Second Byte

First Byte

Second Byte

HAS

t

su(HBV-DSL)

t

su(HSL-DSL)

t

h(DSL-HBV)

†

HAD

Valid

‡

t

su(HBV-DSL)

‡

t

h(DSL-HBV)

HBIL

HCS

t

w(DSH)

t

w(DSL)

HDS

t

d(DSH-HYH)

t

d(DSH-HYL)

HRDY

t

en(DSL-HD)

t

d(DSL-HDV2)

t

d(DSL-HDV1)

Valid

t

h(DSH-HDV)R

HD READ

Valid

t

su(HDV-DSH)

t

v(HYH-HDV)

Valid

t

h(DSH-HDV)W

HD WRITE

CLKOUT

Valid

t

d(COH-HYH)

†

‡

HAD refers to HCNTL0, HCNTL1, and HR/W.

When HAS is not used (HAS always high)

Figure 38. Using HDS to Control Accesses (HCS Always Low)

66

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320UC5409

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS101A – APRIL 1999 – REVISED AUGUST 1999

HPI8 timing (continued)

Second Byte

First Byte

Second Byte

HCS

HDS

t

d(HCS-HRDY)

HRDY

Figure 39. Using HCS to Control Accesses

CLKOUT

t

d(COH-HTX)

HINT

Figure 40. HINT Timing

CLKOUT

t

su(GPIO-COH)

t

h(GPIO-COH)

†

GPIOx Input Mode

t

d(COH-GPIO)

GPIOx Output Mode

†

GPIOx refers to HD0, HD1, HD2, ...HD7, when the HD bus is configured for general-purpose input/output (I/O).

†

Figure 41. GPIOx Timings

67

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320UC5409

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS101A – APRIL 1999 – REVISED AUGUST 1999

HPI16 timing

†‡§

¶

switching characteristics over recommended operating conditions

(see Figure 42 and Figure 43)

[H = 0.5t

]

c(CO)

PARAMETER

MIN

MAX

UNIT

t

Enable time, Dx driven from DS low

7

17

ns

en(DSL-HD)

Case 1a: Memory accesses when

DMAC is active in 16-bit mode and

18H+22 – t

w(DSH)

t

< 18H

w(DSH)

Case 1b: Memory accesses when

DMAC is active in 16-bit mode and

22

t

≥ 18H

Delay time, DS low to Dx valid for an

HPI read

w(DSH)

Case 2a: Memory accesses when

DMAC is inactive and t < 10H

t

ns

d(DSL-HDV1)

10H+22 – t

22

w(DSH)

Case 2b: Memory accesses when

DMAC is inactive and t ≥ 10H

w(DSH)

Case 3: Register accesses

22

8

§

t

Hold time, Dx valid after DS rising edge, read

1

ns

h(DSH-HDV)R

su(HDV-HYH)

d(DSH-HYL)

Setup time, Dx valid before HRDY rising edge

‡

Delay time, DS or HCS high to HRDY low

10

Case 1: Memory access when DMAC

is active in 16-bit mode

18H+10

§

Delay time, DS high to HRDY high

(writes and autoincrement reads)

t

ns

d(DSH-HYH)

Case 2: Memory access when DMAC

is inactive

10H+10

t

Delay time, HDS or HCS low/high to HRDY low/high

Delay time, CLKOUT high to HRDY high

8

ns

d(DSL-HYL)

d(COH–HTH)

Delay time, CLKOUT rising edge to HDx output change. HDx is configured as a

general-purpose output.

t

6

ns

d(COH–GPIO)

NOTE: The HRDY output is always high when the HCS input is high, regardless of DS timings.

†

‡

§

DS refers to the logical OR of HCS, HDS1, or HDS2.

Dx refers to any of the DPI data bus pins (D0, D1, D2, etc.).

DMAC stands for direct memory access (DMA) controller. The HPI16 shares the internal DMA bus with the DMAC, thus HPI16 access times

are affected by DMAC activity.

GPIO refers to the HD pins when they are configured as general-purpose input/outputs.

¶

68

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320UC5409

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS101A – APRIL 1999 – REVISED AUGUST 1999

HPI16 timing (continued)

†‡§

timing requirements

[H = 0.5t

] (see Note 1, Figure 42, and Figure 43)

c(CO)

MIN

10

5

UNIT

ns

†‡

†

t

Setup time, HAD valid before DS falling edge

†‡

su(HBV-DSL)

Hold time, HAD valid after DS falling edge

Setup time, HAD valid before DS falling edge

ns

h(DSL-HBV)

t

ns

su(HAV-DSL)

h(DSH-HAV)

su(HDV-DSH)

h(DSH-HDV)W

w(DSL)

†

Hold time, address valid after DS rising edge

Setup time, Dx valid before DS high (HPI write)

Hold time, Dx valid aftere DS high (HPI write)

3

20

10

2

‡

Pulse duration, DS low

‡

Pulse duration, DS high

w(DSH)

Setuptime, Dx input valid before CLKOUT high, HDx configured as general-purpose input

Hold time, Dx input valid after CLKOUT high, HDx configured as general-purpose input

su(GPIO-COH)

h(GPIO-COH)

0

Cycle time, DS rising edge to next DS rising

edge

Nonmultiplexed mode (no increment)

with no DMA activity.

ns

‡

t

c(DSH-DSH)

Nonmultiplexed mode (no increment)

with 16-bit DMA activity.

(Minimum timings represent WRITEs while

maximum timings represent READs)

†

‡

§

DS refers to the logical OR of HCS and HDS1 and HDS2.

.Dx refers to any of the HPI data bus pins (D0, D1, D2, etc.).

GPIO refers tothe HD pins when they are configured as general-purpose input/outputs.

69

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320UC5409

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS101A – APRIL 1999 – REVISED AUGUST 1999

HPI16 timing (continued)

HCS

t

w(DSH)

t

c(DSH–DSH)

HDS

t

w(DSL)

t

su(HBV–DSL)

t

h(DSL–HBV)

HR/W

t

h(DSH–HAV)

t

su(HAV–DSL)

Valid Address

HA[15:0]

(A[15:0])

Valid Address

t

d(DSL–HDV1)

Data Valid

t

h(DSH–HDV)R

t

d(DSL–HD)

D[15:0]

HRDY

Data Valid

t

su(HDV–HYH)

t

d(DSL–HYH)

Figure 42. Nonmultiplexed Read Timings

70

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320UC5409

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS101A – APRIL 1999 – REVISED AUGUST 1999

HPI16 timing (continued)

HCS

t

c(DSH–DSH)

t

w(DSH)

HDS

t

su(HBV–DSL)

w(DSL)

t

h(DSL–HBV)

HR/W

t

su(HAV–DSL)

t

h(DSH–HAV)

HA[15:0]

(A[15:0])

Valid Address

t

su(HDV–DSH)

t

h(DSH–HDV)W

D[15:0]

HRDY

Data Valid

t

d(DSH–HYH)

t

d(DSH–HYL)

Figure 43. Nonmultiplexed Write Timings

71

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320UC5409

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS101A – APRIL 1999 – REVISED AUGUST 1999

MECHANICAL DATA

PGE (S-PQFP-G144)

PLASTIC QUAD FLATPACK

108

73

109

72

0,27

0,17

M

0,08

0,50

0,13 NOM

144

37

1

36

Gage Plane

17,50 TYP

20,20

SQ

19,80

0,25

0,05 MIN

22,20

SQ

0°–7°

21,80

0,75

0,45

1,45

1,35

Seating Plane

0,08

1,60 MAX

4040147/C 10/96

NOTES: B. All linear dimensions are in millimeters.

C. This drawing is subject to change without notice.

D. Falls within JEDEC MO-136

Thermal Resistance Characteristics

PARAMETER

°C/W

R

56

ΘJA

ΘJC

R

5

72

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

TMS320UC5409

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS101A – APRIL 1999 – REVISED AUGUST 1999

MECHANICAL DATA

GGU (S-PBGA-N144)

PLASTIC BALL GRID ARRAY PACKAGE

12,10

11,90

SQ

9,60 TYP

0,80

N

M

L

K

J

H

G

F

E

D

C

B

A

1

2 3 4 5 6 7 8 9 10 11 12 13

0,95

0,85

1,40 MAX

Seating Plane

0,10

0,55

0,45

0,12

0,08

M

0,08

0,45

0,35

4073221/A 11/96

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. MicroStar BGA configuration

Thermal Resistance Characteristics

PARAMETER

°C/W

R

38

ΘJA

ΘJC

R

5

MicroStar BGA is a trademark of Texas Instruments Incorporated.

73

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

IMPORTANT NOTICE

Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue

any product or service without notice, and advise customers to obtain the latest version of relevant information

to verify, before placing orders, that information being relied on is current and complete. All products are sold

subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those

pertaining to warranty, patent infringement, and limitation of liability.

TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in

accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent

TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily

performed, except those mandated by government requirements.

CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF

DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL

APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR

WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER

CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO

BE FULLY AT THE CUSTOMER’S RISK.

In order to minimize risks associated with the customer’s applications, adequate design and operating

safeguards must be provided by the customer to minimize inherent or procedural hazards.

TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent

that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other

intellectual property right of TI covering or relating to any combination, machine, or process in which such

semiconductor products or services might be or are used. TI’s publication of information regarding any third

party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.


型号：	TMS320UC5409PGE
厂家：	TEXAS INSTRUMENTS
描述：	FIXED-POINT DIGITAL SIGNAL PROCESSOR 定点数字信号处理器数字信号处理器
文件：	总74页 (文件大小：1027K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TMS320UC5409PGE [TI]

相关型号：

TMS320UC5409PGE-80

TMS320UC5409PGER

TMS320UVC5402

TMS320UVC5402GGU

TMS320UVC5402PGE

TMS320UVC5402PGE30

TMS320UVC5409

TMS320UVC5409GGU

TMS320V642AGDK5

TMS320V642AGDK6

TMS320V642AGNZ6

TMS320V642AZDK5