TMS320VC5410 [TI]
FIXED-POINT DIGITAL SIGNAL PROCESSOR; 定点数字信号处理器
| 型号： | TMS320VC5410 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | FIXED-POINT DIGITAL SIGNAL PROCESSOR |
| 文件： | 总79页 (文件大小：1167K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
T MS 32 0V C5 41 0
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SPRS075D – OCTOBER 1998 – REVISED MAY 2000
D
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Advanced Multibus Architecture With Three
Separate 16-Bit Data Memory Buses and
One Program Memory Bus
D
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Instructions With Two- or Three-Operand
Reads
Arithmetic Instructions With Parallel Store
and Parallel Load
40-Bit Arithmetic Logic Unit (ALU)
Including a 40-Bit Barrel Shifter and Two
Independent 40-Bit Accumulators
Conditional Store Instructions
Fast Return From Interrupt
17- × 17-Bit Parallel Multiplier Coupled to a
40-Bit Dedicated Adder for Non-Pipelined
Single-Cycle Multiply/Accumulate (MAC)
Operation
On-Chip Peripherals
– Software-Programmable Wait-State
Generator and Programmable
Bank-Switching
– On-Chip Programmable Phase-Locked
Loop (PLL) Clock Generator With
Internal Oscillator or External Clock
Source
– One 16-Bit Timer
– Six-Channel Direct Memory Access
(DMA) Controller
D
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Compare, Select, and Store Unit (CSSU) for
the Add/Compare Selection of the Viterbi
Operator
Exponent Encoder to Compute an
Exponent Value of a 40-Bit Accumulator
Value in a Single Cycle
Two Address Generators With Eight
Auxiliary Registers and Two Auxiliary
Register Arithmetic Units (ARAUs)
– Three Multichannel Buffered Serial Ports
(McBSPs)
– 8-Bit Enhanced Parallel Host-Port
Interface (HPI8)
D
D
Data Bus With a Bus Holder Feature
Extended Addressing Mode for 8M × 16-Bit
Maximum Addressable External Program
Space
D
Power Consumption Control With IDLE1,
IDLE2, and IDLE3 Instructions With
Power-Down Modes
D
64K x 16-Bit On-Chip RAM Composed of:
– Four Blocks of 2K × 16-Bit On-Chip
Dual-Access Program/Data RAM
– Seven Blocks of 8K × 16-Bit On-Chip
Single-Access Program/Data RAM
D
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CLKOUT Off Control to Disable CLKOUT
On-Chip Scan-Based Emulation Logic,
†
IEEE Std 1149.1 (JTAG) Boundary Scan
Logic
D
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144-Pin Thin Quad Flatpack (TQFP)
(PGE Suffix)
D
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D
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16K × 16-Bit On-Chip ROM Configured to
Program Memory
176-Pin Ball Grid Array (BGA)
(GGW Suffix)
Enhanced External Parallel Interface (XIO2)
Single-Instruction-Repeat and
Block-Repeat Operations for Program Code
10-ns and 8.3-ns Single-Cycle Fixed-Point
Instruction Execution Time (100 and 120
MIPS)
Block-Memory-Move Instructions for Better
Program and Data Management
D
3.3-V I/O and 2.5-V Core Supply Voltages
Instructions With a 32-Bit Long Word
Operand
description
The TMS320VC5410 fixed-point, digital signal processor (DSP) (hereafter referred to as the ’5410 unless
otherwise specified) is based on an advanced modified Harvard architecture that has one program memory bus
and three data memory buses. This processor provides an arithmetic logic unit (ALU) with a high degree of
parallelism, application-specific hardware logic, on-chip memory, and additional on-chip peripherals. The basis
of the operational flexibility and speed of this DSP is a highly specialized instruction set.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
†
IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
Copyright 2000, Texas Instruments Incorporated
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description (continued)
Separate program and data spaces allow simultaneous access to program instructions and data, providing a
high degree of parallelism. Two read operations and one write operation can be performed in a single cycle.
Instructions with parallel store and application-specific instructions can fully utilize this architecture. In addition,
data can be transferred between data and program spaces. Such parallelism supports a powerful set of
arithmetic, logic, and bit-manipulation operations that can all be performed in a single machine cycle. The ’5410
also includes the control mechanisms to manage interrupts, repeated operations, and function calls.
NOTE:This data sheet is designed to be used in conjunction with the TMS320C5000 DSP Family Functional Overview
(literature number SPRU307).
†‡
PGE PACKAGE
(TOP VIEW)
V
1
108
107
106
105
104
103
102
101
100
99
A18
A17
SS
A22
2
V
3
V
SS
DD
SS
DV
4
A16
D5
A10
HD7
A11
A12
A13
A14
A15
5
6
D4
D3
D2
D1
D0
RS
X2/CLKIN
X1
HD3
CLKOUT
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
98
CV
HAS
97
DD
96
V
95
SS
V
94
SS
CV
HCS
93
V
DD
SS
92
HPIENA
HR/W
READY
PS
91
CV
DD
90
V
SS
89
TMS
DS
88
TCK
TRST
TDI
IS
87
R/W
86
MSTRB
IOSTRB
MSC
XF
HOLDA
IAQ
HOLD
BIO
MP/MC
85
TDO
84
EMU1/OFF
EMU0
TOUT
HD2
83
82
81
80
NC
79
CLKMD3
CLKMD2
CLKMD1
78
77
DV
V
BDR1
76
V
DV
BDX1
DD
SS
SS
DD
75
74
73
BFSR1
BFSX1
†
‡
V
and DV
DD
are power supplies for I/O pins while V
and CV are power supplies for core CPU.
DD
SS
SS
The McBSP pins BCLKS0, BCLKS1, and BCLKS2 are not available on the PGE package.
The pin assignments table lists each signal and pin number for the TMS320VC5410PGE (144-pin) package.
The terminal functions table lists each terminal name, function, and operating mode for the TMS320VC5410.
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SPRS075D – OCTOBER 1998 – REVISED MAY 2000
description (continued)
GGW PACKAGE
(BOTTOM VIEW)
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B
A
1
3
5
7
9
11
13
15
17
16
2
4
6
8
10
12
14
The pin assignments table lists each signal and pin number for the TMS320VC5410GGW (176-pin) package.
The terminal functions table lists each terminal name, function, and operating modes for the TMS320VC5410.
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PRO CE SSO R
SPRS075D – OCTOBER 1998 – REVISED MAY 2000
Pin Assignments for the TMS320VC5410PGE (144-Pin Package)
and the TMS320VC5410GGW (176-Pin Package)
PGE
PIN NO.
GGW
PIN NO.
PGE
PIN NO.
GGW
PIN NO.
PIN NAME
PIN NAME
V
1
2
3
4
B1
C2
C1
D3
D2
D1
E3
E2
E1
F3
F2
F1
G4
G3
G2
G1
H1
H4
H3
H2
J1
BFSR1
36
R2
T1
SS
A22
CV
DD
V
SS
V
SS
37
38
39
40
U2
DV
CV
BCLKR1
HCNTL0
T3
DD
DD
U3
A10
HD7
5
6
V
R4
SS
DV
T4
DD
V
SS
BCLKR0
BCLKR2
BFSR0
BCLKS0
BFSR2
BDR0
41
42
43
U4
A11
A12
A13
A14
A15
7
8
R5
T5
9
U5
10
11
44
45
R6
T6
DV
V
SS
U6
DD
DD
CV
12
13
14
15
16
17
18
19
20
21
HCNTL1
BDR2
46
47
P7
HAS
R7
V
V
CV
T7
SS
DD
BCLKX0
BCLKX2
BCLKS2
48
49
U7
SS
CV
DD
HCS
U8
P8
HR/W
READY
PS
V
50
51
52
53
54
55
56
57
58
59
R8
SS
HINT
CV
J4
T8
J3
U9
DD
DS
J2
BFSX0
BFSX2
HRDY
P9
V
SS
K1
K2
K4
K3
L1
R9
IS
22
23
T9
R/W
DV
U10
T10
P10
R10
U11
T11
R11
P11
U12
T12
R12
U13
T13
R13
U14
T14
D17
D16
DD
DV
V
SS
DD
MSTRB
IOSTRB
24
25
HD0
L2
BDX0
CV
L3
CV
DD
DD
MSC
XF
26
27
28
29
30
31
32
33
34
L4
BDX2
IACK
60
61
M1
M2
M3
N1
N2
N3
P1
P2
P3
R1
R14
U15
HOLDA
IAQ
V
SS
HBIL
NMI
62
63
64
65
HOLD
BIO
INT0
INT1
MP/MC
DV
DV
DD
DD
V
SS
INT2
INT3
66
67
68
BCLKS1
BDR1
HD1
35
69
70
CV
CV
DD
DD
V
SS
A16
105
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SPRS075D – OCTOBER 1998 – REVISED MAY 2000
Pin Assignments for the TMS320VC5410PGE (144-Pin Package)
and the TMS320VC5410GGW (176-Pin Package) (Continued)
PGE
PIN NO.
GGW
PIN NO.
PGE
PIN NO.
GGW
PIN NO.
PIN NAME
PIN NAME
BCLKX1
71
72
T15
U16
T17
R16
R17
P15
P16
P17
N15
N16
N17
M15
M16
M17
L14
L15
L16
L17
K17
K14
K15
K16
J17
J14
J15
J16
H17
H16
H14
H15
G17
G16
G15
G14
F17
F16
F15
E17
E16
E15
B5
V
106
107
108
D15
C17
C16
B17
A16
B15
A15
C14
B14
A14
C13
B13
A13
C12
B12
A12
D11
C11
B11
A11
A10
D10
C10
B10
A9
SS
V
A17
A18
SS
CV
DD
BFSX1
BDX1
73
74
75
76
77
78
79
80
81
82
83
DV
DD
DD
CV
DV
A19
A20
109
110
111
112
113
114
115
116
117
118
DD
V
SS
CLKMD1
CLKMD2
CLKMD3
NC
V
SS
DV
DD
D6
D7
D8
HD2
TOUT
D9
EMU0
D10
D11
V
SS
EMU1/OFF
TDO
84
85
86
87
88
89
90
91
92
93
DV
DD
D12
HD4
119
120
TDI
TRST
TCK
V
SS
D13
D14
D15
HD5
121
122
123
124
125
126
127
128
129
130
131
132
TMS
V
SS
CV
DD
HPIENA
CV
DD
V
V
SS
HDS1
SS
DV
D9
DD
CLKOUT
HD3
94
95
96
97
98
V
C9
SS
HDS2
DV
B9
X1
A8
DD
A0
A1
CV
X2/CLKIN
RS
B8
D8
V
SS
C8
DD
D0
D1
99
A2
A3
133
134
A7
100
B7
DV
DV
C7
DD
DD
D2
D3
101
102
HD6
A4
135
136
D7
A6
V
SS
D4
V
SS
B6
103
104
A5
A6
137
138
C6
D5
A5
DV
DV
C4
DD
DD
DD
A7
A8
A9
139
140
141
C5
CV
142
143
144
A3
A4
A21
B3
B4
V
SS
A2
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PRO CE SSO R
SPRS075D – OCTOBER 1998 – REVISED MAY 2000
terminal functions
The terminal functions table lists each signal, function, and operating mode(s) grouped by function.
Terminal Functions
TERMINAL
NAME
†
I/O
DESCRIPTION
DATA SIGNALS
A22 (MSB)
A21
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
O/Z
Parallel address bus A22 [most significant bit (MSB)] through A0 [least significant bit (LSB)]. The sixteen LSB
lines, A0 to A15, are multiplexed to address external memory (program, data) or I/O. The seven MSB lines, A16
to A22, address external program space memory. A22–A0 is placed in the high-impedance state in the hold
mode. A22–A0 also goes into the high-impedance state when OFF is low.
The address bus has a bus holder feature that eliminates passive components and the power dissipation
associated with them. The bus holder keeps the address bus at the previous logic level when the bus goes into
a high-impedance state.
A8
A7
A6
A5
A4
A3
A2
A1
A0
(LSB)
D15 (MSB)
D14
D13
D12
D11
D10
D9
I/O/Z
Parallel data bus D15 (MSB) through D0 (LSB). D15–D0 is multiplexed to transfer data between the core CPU
and external data/program memory or I/O devices. D15–D0 is placed in high-impedance state when not
outputting data or when RS or HOLD is asserted. D15–D0 also goes into the high-impedance state when OFF
is low.
The data bus has a bus holder feature that eliminates passive components and the power dissipation associated
with them. The bus holder keeps the data bus at the previous logic level when the bus goes into a
high-impedance state. The bus holders on the data bus can be enabled/disabled under software control.
D8
D7
D6
D5
D4
D3
D2
D1
D0
(LSB)
†
I = Input, O = Output, Z = High-impedance, S = Supply
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SPRS075D – OCTOBER 1998 – REVISED MAY 2000
Terminal Functions (Continued)
TERMINAL
NAME
†
I/O
DESCRIPTION
INITIALIZATION, INTERRUPT AND RESET OPERATIONS
Interrupt acknowledge signal. IACK indicates receipt of an interrupt and that the program counter is fetching the
interrupt vector location designated by A15–A0. IACK also goes into the high-impedance state when OFF is low.
IACK
O/Z
I
INT0
INT1
INT2
INT3
External user interrupt inputs. INT0–INT3 is prioritized and is maskable by the interrupt mask register (IMR) and
interrupt mode bit. INT0 –INT3 can be polled and reset by way of the interrupt flag register (IFR).
Nonmaskable interrupt. NMI is an external interrupt that cannot be masked by way of the INTM or the IMR. When
NMI is activated, the processor traps to the appropriate vector location.
NMI
I
I
Reset. RS causes the digitial signal processor (DSP) to terminate execution and forces the program counter to
0FF80h. When RS is brought to a high level, execution begins at location 0FF80h of program memory. RS affects
various registers and status bits.
RS
Microprocessor/microcomputer mode select pin. If active low at reset (microcomputer mode), MP/MC causes
the internal program ROM to be mapped into the upper 16K words of program memory space. In the
microprocessor mode, off-chip memory and its corresponding addresses (instead of internal program ROM) are
accessed by the DSP.
MP/MC
I
MULTIPROCESSING SIGNALS
Branch control. A branch can be conditionally executed when BIO is active. If low, the processor executes the
conditional instruction. The BIO condition is sampled during the decode phase of the pipeline for the XC
instruction, and all other instructions sample BIO during the read phase of the pipeline.
BIO
XF
I
External flag output (latched software-programmable signal). XF is set high by the SSBX XF instruction, set low
by RSBX XF instruction or by loading ST1. XF is used for signaling other processors in multiprocessor
configurations or used as a general-purpose output pin. XF goes into the high-impedance state when OFF is
low, and is set high at reset.
O/Z
MEMORY CONTROL SIGNALS
Data, program, and I/O space select signals. DS, PS, and IS are always high unless driven low for
communicating to a particular external space. Active period corresponds to valid address information. DS, PS,
and IS are placed into the high-impedance state in the hold mode; these signals also go into the high-impedance
state when OFF is low.
DS
PS
IS
O/Z
O/Z
I
Memory strobe signal. MSTRB is always high unless low-level asserted to indicate an external bus access to
data or program memory. MSTRB is placed in the high-impedance state in the hold mode; it also goes into the
high-impedance state when OFF is low.
MSTRB
READY
R/W
Data ready. READY indicates that an external device is prepared for a bus transaction to be completed. If the
device is not ready (READY is low), the processor waits one cycle and checks READY again. Note that the
processor performs ready detection if at least two software wait states are programmed. The READY signal is
not sampled until the completion of the software wait states.
Read/write signal. R/W indicates transfer direction during communication to an external device. R/W is normally
in the read mode (high), unless it is asserted low when the DSP performs a write operation. R/W is placed in
the high-impedance state in the hold mode; and it also goes into the high-impedance state when OFF is low.
O/Z
I/O strobe signal. IOSTRB is always high unless low-level asserted to indicate an external bus access to an I/O
device. IOSTRB is placed in the high-impedance state in the hold mode; it also goes into the high-impedance
state when OFF is low.
IOSTRB
HOLD
O/Z
I
Hold input. HOLD is asserted to request control of the address, data, and control lines. When acknowledged by
the ’VC5410, these lines go into the high-impedance state.
Hold acknowledge. HOLDA indicates to the external circuitry that the processor is in a hold state and that the
address, data, and control lines are in the high-impedance state, allowing them to be available to the external
circuitry. HOLDA also goes into the high-impedance state when OFF is low.
HOLDA
O/Z
Microstate complete. MSC goes low when the last wait state of two or more internal software wait states
programmed is executed. If connected to the READY line, MSC forces one external wait state after the last
internal wait state has been completed. MSC also goes into the high-impedance state when OFF is low.
MSC
O/Z
†
I = Input, O = Output, Z = High-impedance, S = Supply
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SPRS075D – OCTOBER 1998 – REVISED MAY 2000
Terminal Functions (Continued)
TERMINAL
NAME
†
I/O
DESCRIPTION
MEMORY CONTROL SIGNALS (CONTINUED)
Instruction acquisition signal. IAQ is asserted (active low) when there is an instruction address on the address
bus and goes into the high-impedance state when OFF is low.
IAQ
O/Z
OSCILLATOR/TIMER SIGNALS
Clock output signal. CLKOUT can represent the machine-cycle rate of the CPU divided by 1, 2, 3, or 4 as
configured in the bank-switching control register (BSCR). Following reset, CLKOUT represents the
machine-cycle rate divided by 4.
CLKOUT
O/Z
I
CLKMD1
CLKMD2
CLKMD3
Clock mode select signals. CLKMD1 – CLKMD3 allows the selection and configuration of different clock modes
such as crystal, external clock, PLL mode.
X2/CLKIN
I
Clock/oscillator input. If the internal oscillator is not being used, X2/CLKIN functions as the clock input.
Output pin from the internal oscillator for the crystal. If the internal oscillator is not used, X1 should be left
unconnected. X1 does not go into the high-impedance state when OFF is low.
X1
O
Timer output. TOUT signals a pulse when the on-chip timer counts down past zero. The pulse is one CLKOUT
cycle wide. TOUT also goes into the high-impedance state when OFF is low.
TOUT
O
MULTICHANNEL BUFFERED SERIAL PORT 0 (McBSP #0), MULTICHANNEL BUFFERED SERIAL PORT 1 (McBSP #1),
AND MULTICHANNEL BUFFERED SERIAL PORT 2 (McBSP #2) SIGNALS
BCLKR0
BCLKR1
BCLKR2
I/O/Z
I
Receive clock input. BCLKR serves as the serial shift clock for the buffered serial port receiver.
Serial data receive input
BDR0
BDR1
BDR2
BFSR0
BFSR1
BFSR2
I/O/Z
I/O/Z
O/Z
I/O/Z
I
Frame synchronization pulse for receive input. The BFSR pulse initiates the receive data process over BDR.
BCLKX0
BCLKX1
BCLKX2
Transmit clock. BCLKX serves as the serial shift clock for the McBSP transmitter. BCLKX can be configured as
an input or an output, and is configured as an input following reset. BCLKX enters the high-impedance state when
OFF goes low.
BDX0
BDX1
BDX2
Serial data transmit output. BDX is placed in the high-impedance state when not transmitting, when RS is
asserted, or when OFF is low.
BFSX0
BFSX1
BFSX2
Frame synchronization pulse for transmit input/output. The BFSX pulse initiates the data transmit process over
BDX. BFSX can be configured as an input or an output, and is configured as an input following reset. BFSX goes
into the high-impedance state when OFF is low.
BCLKS0
BCLKS1
BCLKS2
Serial port clock reference. The McBSP can be programmed to use either BCLKS or the CPU clock as a
reference for generation of internal clock and frame sync signals. Pins with internal pullup devices.
NOTE: These pins are not available on the PGE package.
MISCELLANEOUS SIGNAL
No connection
NC
HOST-PORT INTERFACE SIGNALS
Parallel bidirectional data bus. HD0–HD7 is placed in the high-impedance state when not outputting data. The
signals go into the high-impedance state when OFF is low. The HPI data bus has a feature called a bus holder
that eliminates passive components and the power dissipation associated with them. The bus holder keeps the
data bus at the previous logic level when the bus goes into high-impedance state. The bus holder on the HPI
data bus can be enabled/disabled under software control.
HD0–HD7
I/O/Z
†
I = Input, O = Output, Z = High-impedance, S = Supply
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Terminal Functions (Continued)
TERMINAL
NAME
†
I/O
DESCRIPTION
HOST-PORT INTERFACE SIGNALS (CONTINUED)
Control inputs
HCNTL0
HCNTL1
I
HBIL
I
I
Byte identification
Chip select
HCS
HDS1
HDS2
I
Data strobe
HAS
I
I
Address strobe
HR/W
HRDY
Read/write
O/Z
Ready output. HRDY goes into the high-impedance state when OFF is low.
Interrupt output. When the DSP is in reset, HINT is driven high. HINT goes into the high-impedance state when
OFF is low.
HINT
O/Z
HPI module select. HPIENA must be tied to DV
DD
to have HPI selected. If HPIENA is left open or connected
to ground, the HPI module is not selected, internal pullup for the HPI input pins are enabled, and the HPI data
bus has holders set. HPIENA is provided with an internal pulldown resistor that is active only when RS is low.
HPIENA is sampled when RS goes high and is ignored until RS goes low again.
HPIENA
I
SUPPLY PNS
V
S
S
S
Ground. Dedicated power supply for the core CPU.
SS
CV
DV
+V . Dedicated power supply for the core CPU.
DD
DD
DD
+V . Dedicated power supply for I/O pins.
DD
TEST PINS
IEEE standard 1149.1 test clock. TCK is normally a free-running clock signal with a 50% duty cycle. The changes
on test access port (TAP) of input signals TMS and TDI are clocked into the TAP controller, instruction register,
or selected test data register on the rising edge of TCK. Changes at the TAP output signal (TDO) occur on the
falling edge of TCK.
TCK
I
IEEE standard 1149.1 test data input. Pin with internal pullup device. TDI is clocked into the selected register
(instruction or data) on a rising edge of TCK.
TDI
I
IEEE standard 1149.1 test data output. The contents of the selected register (instruction or data) are shifted out
of TDO on the falling edge of TCK. TDO is in the high-impedance state except when the scanning of data is in
progress. TDO also goes into the high-impedance state when OFF is low.
TDO
TMS
TRST
O/Z
IEEE standard 1149.1 test mode select. Pin with internal pullup device. This serial control input is clocked into
the TAP controller on the rising edge of TCK.
I
I
IEEE standard 1149.1 test reset. TRST, when high, gives the IEEE standard 1149.1 scan system control of the
operations of the device. If TRST is not connected or driven low, the device operates in its functional mode, and
the IEEE standard 1149.1 signals are ignored. Pin with internal pulldown device.
Emulator 0 pin. When TRST is driven low, EMU0 must be high for activation of the OFF condition. When TRST
is driven high, EMU0 is used as an interrupt to or from the emulator system and is defined as input/output by
way of the IEEE standard 1149.1 scan system.
EMU0
I/O/Z
Emulator 1 pin/disable all outputs. When TRST is driven high, EMU1/OFF is used as an interrupt to or from the
emulator system and is defined as input/output by way of IEEE standard 1149.1 scan system. When TRST is
driven low, EMU1/OFF is configured as OFF. The EMU1/OFF signal, when active low, puts all output drivers into
the high-impedance state. Note that OFF is used exclusively for testing and emulation purposes (not for
multiprocessing applications). Therefore, for the OFF condition, the following apply:
TRST = low,
EMU1/OFF
I/O/Z
EMU0 = high
EMU1/OFF = low
†
I = Input, O = Output, Z = High-impedance, S = Supply
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architecture
The ’VC5410 DSP implements the standard ’C54x CPU which uses an advanced, modified Harvard
architecture that maximizes processing power by maintaining three separate bus structures for data memory
and one for program memory. Separate program and data spaces allow simultaneous access to program
instructions and data, providing a high degree of parallelism. For example, two read operations and one write
operation can be performed in a single cycle. Instructions with parallel store and application-specific instructions
fully utilize this architecture. In addition, data can be transferred between data and program spaces. Such
parallelism supports a powerful set of arithmetic, logic, and bit-manipulation operations that can all be performed
in a single machine cycle. In addition, the ’VC5410 includes the control mechanisms to manage interrupts,
repeated operations, and function calls.
For detailed information on the architecture of the C5000 family of DSPs, refer to the TMS320C5000 DSP
Family Functional Overview (literature number SPRU307).
memory
The ’VC5410 device provides both on-chip ROM and RAM memories to aid in system performance and
integration.
on-chip ROM with bootloader
The ’VC5410 features a 16K-word × 16-bit on-chip maskable ROM that can only be mapped into program
memory space.
Customers can arrange to have the ROM of the ’VC5410 programmed with contents unique to any particular
application.
A bootloader is available in the standard ’VC5410 on-chip ROM. This bootloader can be used to automatically
transfer user code from an external source to anywhere in the program memory at power up. If MP/MC of the
device is sampled low during a hardware reset, execution begins at location FF80h of the on-chip ROM. This
location contains a branch instruction to the start of the bootloader program. The standard ’VC5410 devices
provide different ways to download the code to accomodate various system requirements:
D
D
D
D
D
Parallel from 8-bit or 16-bit-wide EPROM
Parallel from I/O space, 8-bit or 16-bit mode
Serial boot from serial ports, 8-bit or 16-bit mode
Host-port interface boot
Warm boot
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on-chip ROM with bootloader (continued)
The standard on-chip ROM layout is shown in Table 1.
†
Table 1. Standard On-Chip ROM Layout
ADDRESS RANGE
C000h–D4FFh
D500h–D6FFh
D700h–DCFFh
DD00h–DEFFh
DF00h–F7FFh
F800h–FBFFh
FC00h–FCFFh
FD00h–FDFFh
FE00h–FEFFh
FF00h–FF7Fh
FF80h–FFFFh
DESCRIPTION
ROM tables for the GSM EFR speech codec
256-point complex radix-2 DIT FFT with looped code
FFT twiddle factors for a 256-point complex radix-2 FFT
1024-point complex radix-2 DIT FFT with looped code
FFT twiddle factors for a 1024-point complex radix-2 FFT
Bootloader
µ-Law expansion table
A-Law expansion table
Sine look-up table
†
Reserved
Interrupt vector table
†
In the ’VC5410 ROM, 128 words are reserved for factory device-testing purposes. Application
code to be implemented in on-chip ROM must reserve these 128 words at addresses
FF00h–FF7Fh in program space.
on-chip RAM
The ’VC5410 device contains 8K words × 16-bit on-chip dual-access RAM (DARAM) and 56K words × 16-bit
of on-chip single-access RAM (SARAM).
The DARAM is composed of four blocks of 2K words each. Each block in the DARAM can support two reads
in one cycle, or a read and a write in one cycle. The DARAM is located in the address range 0080h–1FFFh in
data space, and can be mapped into program/data space by setting the OVLY bit to one.
The SARAM is composed of seven blocks of 8K words each. Each of these seven blocks is a single-access
memory. For example, an instruction word can be fetched from one SARAM block in the same cycle as a data
word is written to another SARAM block. The SARAM located in the address range 2000h–7FFFh in data space
can be mapped into program space by setting the OVLY bit to one, while the SARAM located in the address
range 18000h–1FFFFh in program space can be mapped into data space by setting the DROM bit to one.
on-chip memory security
The ’VC5410 device has a maskable option to protect the contents of on-chip memories. When the ROM protect
bit is set, no externally originating instruction can access the on-chip memory spaces. In addition, when the
ROM protect option is enabled, HPI8 read access is limited to address range 0001000h – 0001FFFh. Data
located outside this range cannot be read through the HPI8. Write access to the entire HPI8 memory map is
still maintained.
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memory map
Program
Program
Program
Program
Data
Hex
0000
Hex
010000
Hex
010000
Hex
0000
Hex
0000
Reserved
(OVLY = 1)
External
(OVLY = 0)
Reserved
(OVLY = 1)
External
(OVLY = 0)
Memory-Mapped
Registers
005F
0060
Scratch-Pad
RAM
007F
0080
007F
0080
007F
0080
Mapped to
Lower Page 0
(OVLY = 1)
External
(OVLY = 0)
Mapped to
On-Chip
DARAM
(OVLY = 1)
External
(OVLY = 0)
On-Chip
DARAM
(OVLY = 1)
External
(OVLY = 0)
Lower Page 0
(OVLY = 1)
On-Chip
DARAM
(8K Words)
External
(OVLY = 0)
1FFF
2000
1FFF
2000
1FFF
2000
On-Chip
SARAM1
(OVLY = 1)
On-Chip
SARAM1
(OVLY = 1)
On-Chip
SARAM1
(24K Words)
External
(OVLY = 0)
External
(OVLY = 0)
017FFF
018000
7FFF
8000
7FFF
8000
7FFF
8000
017FFF
018000
External
External
External
On-Chip
SARAM2
BFFF
C000
On-Chip
SARAM2
(DROM = 1)
External
(DROM = 0)
On-Chip
ROM
(16K Words)
FF7F
FF80
FF7F
FF80
Interrupts and
Reserved
(External)
Interrupts and
Reserved
(On-Chip ROM)
FFFF
01FFFF
01FFFF
FFFF
FFFF
Page 1
Page 0
Page 1
Page 0
MP/MC= 1
(Microprocessor Mode)
MP/MC= 0
(Microcomputer Mode)
Figure 1. Memory Map
program memory
Software can configure their memory cells to reside inside or outside of the program address map. When the
cells are mapped into program space, the device automatically accesses them when their addresses are within
bounds. When the program-address generation (PAGEN) logic generates an address outside its bounds, the
device automatically generates an external access. The advantages of operating from on-chip memory are as
follows:
D
D
D
Higher performance because no wait states are required
Lower cost than external memory
Lower power than external memory
The advantage of operating from off-chip memory is the ability to access a larger address space.
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relocatable interrupt vector table
The reset, interrupt, and trap vectors are addressed in program space. These vectors are soft — meaning that
the processor, when taking the trap, loads the program counter (PC) with the trap address and executes the
code at the vector location. Four words, either two 1-word instructions or one 2-word instruction, are reserved
at each vector location to accommodate a delayed branch instruction which allows branching to the appropriate
interrupt service routine without the overhead.
At device reset, the reset, interrupt, and trap vectors are mapped to address FF80h in program space. However,
these vectors can be remapped to the beginning of any 128-word page in program space after device reset.
This is done by loading the interrupt vector pointer (IPTR) bits in the PMST register with the appropriate
128-word page boundary address. After loading IPTR, any user interrupt or trap vector is mapped to the new
128-word page.
NOTE: The hardware reset (RS) vector cannot be remapped because the hardware reset loads the IPTR
with 1s. Therefore, the reset vector is always fetched at location FF80h in program space.
extended program memory
The ’VC5410 uses a paged extended memory scheme in program space to allow access of up to 8192K of
program memory. In order to implement this scheme, the ’VC5410 includes several features which are also
present on ’C548/549:
D
D
D
Twenty-three address lines, instead of sixteen
An extra memory-mapped register, the XPC
Six extra instructions for addressing extended program space
Program memory in the ’VC5410 is organized into 128 pages that are each 64K in length, as shown in Figure 2.
00 0000
01 0000
02 0000
7F 0000
. . .
Page 0
Page 1
Page 2
Page 127
64K
Words
64K
Words
64K
Words
64K
Words
. . .
00 FFFF
01 FFFF
02 FFFF
7F FFFF
XPC = 0
XPC = 1
XPC = 2
XPC=127
Figure 2. Extended Program Memory
(On-Chip RAM Not Mapped in Program Space and Data Space, OVLY = 0)
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extended program memory (continued)
When the on-chip RAM is enabled in program space, each page of program memory is made up of two parts: a
common block of 32K words and a unique block of 32K words. The common block is shared by all pages and each
unique block is accessible only through its assigned page. Figure 3 shows the common and unique blocks.
xx 0000
xx 7FFF
Page 0
†
32K Words
On-Chip
XPC = xx
00 8000
00 FFFF
01 8000
01 FFFF
02 8000
02 FFFF
7F 8000
7F FFFF
Page 0
Page 1
Page 2
. . .
. . .
Page 127
32K Words
External
32K Words
On-Chip
32K Words
External
32K Words
External
XPC = 0
XPC = 1
XPC = 2
XPC=127
†
See Figure 1 for more information about this on-chip memory region.
NOTE A: When the on-chip RAM is enabled in program space, all accesses to the region xx 0000 – xx 7FFF, regardless of page number, are
mapped to the on-chip RAM at 00 0000 – 00 7FFF.
Figure 3. Extended Program Memory
(On-Chip RAM Mapped in Program Space and Data Space, OVLY = 1)
If the on-chip ROM is enabled (MP/MC = 0), it is enabled only on page 0. It is not mapped to any other page
in program memory.
The value of the XPC register defines the page selection. This register is memory-mapped into data space to
address 001Eh. At a hardware reset, the XPC is initialized to 0.
To facilitate page-switching through software, the ’VC5410 has six special instructions that affect the XPC:
D
D
FB[D] pmad (23 bits) – Far branch
FBACC[D] Accu[22:0] – Far branch to the location specified by the value in accumulator A or
accumulator B
D
D
D
D
FCALL[D] pmad (23 bits) – Far call
FCALA[D] Accu[22:0] – Far call to the location specified by the value in accumulator A or accumulator B
FRET[D] – Far return
FRETE[D] – Far return with interrupts enabled
In addition to these new instructions, two ’54x instructions are extended to use 23 bits in the ’VC5410:
D
D
READA data_memory (using 23-bit accumulator address)
WRITA data_memory (using 23-bit accumulator address)
All other instructions, software and hardware interrupts do not modify the XPC register and access only memory
within the current page.
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data memory
The data memory space addresses up to 64K of 16-bit words. The device automatically accesses the on-chip
RAM when addressing within its bounds. When an address is generated outside the RAM bounds, the device
automatically generates an external access.
The advantages of operating from on-chip memory are as follows:
D
D
D
D
Higher performance because no wait states are required
Higher performance because of better flow within the pipeline of the central arithmetic logic unit (CALU)
Lower cost than external memory
Lower power than external memory
The advantage of operating from off-chip memory is the ability to access a larger address space.
on-chip peripherals
The ’VC5410 device has the following peripherals:
D
D
D
D
D
D
D
D
Software-programmable wait-state generator
Programmable bank-switching
A host-port interface (HPI8)
Three multichannel buffered serial ports (McBSPs)
A hardware timer
A clock generator with a multiple phase-locked loop (PLL)
Enhanced external parallel interface (XIO2)
A DMA controller (DMA)
software-programmable wait-state generator
The software-programmable wait-state generator can extend external bus cycles by up to fourteen CLKOUT
cycles, providing a convenient means of interfacing the ’VC5410 with slower external devices. Devices that
require more than fourteen wait states can be interfaced using the hardware READY line. When all external
accesses are configured for zero wait states, the internal clocks to the wait-state generator are shut off; shutting
off these paths from the internal clocks allows the device to run with lower power consumption.
The software-programmable wait-state generator is controlled by the 16-bit software wait-state register
(SWWSR), which is memory-mapped to address 0028h in data space.
The program and data spaces each consist of two 32K-word blocks; the I/O space consists of one 64K-word block.
Each of these blocks has a corresponding 3-bit field in the SWWSR. These fields are shown in Figure 4 and
described in Table 2.
The value of a 3-bit field in SWWSR, in conjunction with the software wait-state multiplier (SWSM) bit in the
software wait-state control register (SWCR), specifies the number of wait states to be inserted for each access
in the corresponding space and address range.
D
D
When SWSM = 0, the possible values for the number of wait states are 0, 1, 2, 3, 4, 5, 6, and 7. This is the
default configuration.
When SWSM = 1, the possible values for the number of wait states are 0, 2, 4, 6, 8, 10, 12, and 14.
At reset, the SWWSR is set to 7FFFh, and SWSM to 0, configuring seven wait states for all external accesses.
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software-programmable wait-state generator (continued)
15
14
12 11
9
8
6
5
3
2
0
SWWSR (0x28)
XPA
I/O
Data
R/W
Data
R/W
Program
R/W
Program
R/W
R/W
R/W
R = Read, W = Write, Reset value = 7FFFh
Figure 4. Software Wait-State Register (SWWSR)
Table 2. Software Wait-State Register Fields
RESET
VALUE
BIT
NAME
FUNCTION
15
XPA
0
1
Extended program address control bit. XPA selects the address ranges selected by the program fields.
I/O space. The field value (0–14) corresponds to the number of wait states for I/O space 0000–FFFFh.
14–12 I/O
Data space. The field value (0–14) corresponds to the number of wait states for data space
8000–FFFFh.
11–9
8–6†
Data
1
1
Data space. The field value (0–14) corresponds to the number of wait states for data space
0000–7FFFh.
Data
Program space. The field value (0–14) corresponds to the number of wait states for:
XPA = 0
XPA = 1
xx8000–xxFFFFh
400000h–7FFFFF
5–3
2–0
Program
1
1
Program space. The field value (0–14) corresponds to the number of wait states for:
XPA = 0
XPA = 1
xx0000–xx7FFFh
000000–3FFFFFh
Program
†
Although this field is present to maintain compatibility with previous C5000 family DSPs, there is no external data space on the ’VC5410 in this
address range; therefore, the configuration of this bit field has no effect.
The SWSM bit is located in the software wait-state control register (SWCR), a memory-mapped register (MMR)
at address 0x2B, bit 0 position (LSB). The bit fields of the SWCR are shown in Figure 5 and are described in
Table 3.
15
1
0
SWCR (0x2B)
Reserved
SWSM
Figure 5. Software Wait-State Control Register (SWCR)
Table 3. Software Wait-State Control Register Fields
RESET
VALUE
BIT
NAME
FUNCTION
15–1
0
Reserved
–
Reserved
Software wait-state multiplier bit.
SWSM = 0 Wait states in SWWSR are not multiplied by 2
SWSM = 1 Wait states in SWWSR are multiplied by 2
SWSM
0
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programmable bank-switching
Programmable bank-switching logic allows the ’VC5410 to switch between external memory banks without
requiring external wait states for memories that need additional time to turn off. The bank-switching logic
automatically inserts one cycle when accesses cross a 32K-word memory-bank boundary inside program or
data space.
Bank-switching is defined by the bank-switching control register (BSCR), which is memory-mapped at
address 0029h. The bit fields of the BSCR are shown in Figure 6 and are described in Table 4.
15
14
13
DIVFCT
R/W
12
11
3
2
1
0
Rsvd
R
BSCR (0x29)
CONSEC
R/W
IACKOFF
R/W
Rsvd
R
HBH
BH
R/W
R/W
R = Read, W = Write
Figure 6. Bank-Switching Control Register (BSCR)
Table 4. Bank-Switching Control Register Fields
RESET
VALUE
BIT
NAME
FUNCTION
Consecutive bank-switching. Specifies the bank-switching mode.
Bank-switching on 32K bank boundaries only. This bit is cleared if fast access is desired for
continuous memory reads (i.e., no starting and trailing cycles between read cycles).
CONSEC = 0
CONSEC = 1
†
15
CONSEC
1
consecutive bank switches on external memory reads. Each read cycle consists of 3 cycles:
starting cycle, read cycle, and trailing cycle.
CLKOUT output divide factor. The CLKOUT output is driven by an on-chip source having a frequency
equal to 1/(DIVFCT+1) of the DSP clock.
DIVFCT = 00
DIVFCT = 01
DIVFCT = 10
DIVFCT = 11
CLKOUT is not divided.
13–14 DIVFCT
11
CLKOUT is divided by 2 from the DSP clock.
CLKOUT is divided by 3 from the DSP clock.
CLKOUT is divided by 4 from the DSP clock (default value following reset).
IACK signal output off. Controls the output of the IACK signal. IACKOFF is set to 1 at reset.
IACKOFF = 0 The IACK signal output off function is disabled.
IACKOFF = 1 The IACK signal output off function is enabled.
Reserved
12
IACKOFF
1
–
11–3
Rsvd
HBH
HPI bus holder. Controls the HPI bus holder. HBH is cleared to 0 at reset.
HBH = 0
The bus holder is disabled.
2
0
The bus holder is enabled. When not driven, the HPI data bus, HD[7:0] is held in the previous
logic level.
HBH = 1
Bus holder. Controls the bus holder. BH is cleared to 0 at reset.
BH = 0
The bus holder is disabled.
1
0
BH
0
–
The bus holder is enabled. When not driven, the data bus, D[15:0] is held in the previous logic
level.
BH = 1
Rsvd
Reserved
†
For additional information, see the “enhanced external parallel interface (XIO2)” section of this document.
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programmable bank-switching (continued)
The ’VC5410 has an internal register that holds the MSB of the last address used for a read or write operation
in program or data space. In the non-consecutive bank switches (CONSEC = 0), if the MSB of the address used
for the current read does not match that contained in this internal register, the MSTRB (memory strobe) signal
is not asserted for one CLKOUT cycle. During this extra cycle, the address bus switches to the new address.
The contents of the internal register are replaced with the MSB for the read of the current address. If the MSB
of the address used for the current read matches the bits in the register, a normal read cycle occurs.
In non-consecutive bank switches (CONSEC = 0), if repeated reads are performed from the same memory
bank, no extra cycles are inserted. When a read is performed from a different memory bank, memory conflicts
are avoided by inserting an extra cycle. For more information, see the “enhanced external parallel interface
(XIO2)” section of this document.
The bank-switching mechanism automatically inserts one extra cycle in the following cases:
D
D
D
D
A memory read followed by another memory read from a different memory bank.
A program-memory read followed by a data-memory read.
A data-memory read followed by a program-memory read.
A program-memory read followed by another program-memory read from a different page.
parallel I/O ports
Each device has a total of 64K I/O ports. These ports can be addressed by the PORTR instruction or the PORTW
instruction. The IS signal indicates a read/write operation through an I/O port. The ’VC5410 can interface easily
with external devices through the I/O ports while requiring minimal off-chip address-decoding circuits.
enhanced host-port interface (HPI8)
The enhanced host-port interface (HPI8) in the ’VC5410 is an 8-bit parallel port used to interface a host
processor to the DSP. Data can be exchanged between the host processor and the DSP throughout the entire
on-chip memory via the DMA controller. The extended program memory pages are also accessible by both the
host and the DSP. The DSP and the host control the HPI8 activity through the HPI8 control register (HPIC). The
host can address memory through the HPI8 address register (HPIA).
Data transfers of 16-bit words occur as two consecutive bytes with a dedicated pin (HBIL) indicating whether
the high or low byte is being transmitted. Two pins (controlled by the host), HCNTL0 and HCNTL1, indicate
whether the being exchanged is the most significant or least significant byte. Control pins (HCNTL0 and
HCNTL1) determine whether the data is directed to the HPIA, the HPIC, or to memory. The DSP can interrupt
the host with a dedicated HINT pin that the host can acknowledge and clear.
The ’VC5410 is the first device in the C5000 family in which the HPI8 can address all on-chip memory, including
extended memory pages. Extended memory addresses are defined by a 23-bit address. The HPI8 sets the
upper 6 bits of the extended memory address by writing a one to the XHPIA bit in HPIC, and then writing address
bits A[22:16] into HPIA. The lower 16 bits of the extended memory address are set by writing a zero to XHPIA,
followed by writing bits A[15:0] to HPIA. Similar to previous implementations of the HPI, after a write is performed
to XHPIA or HPIA, a memory prefetch is initiated. The XHPIA bit is accessible only to the host. XHPIA is
uninitialized following reset. The host should always initialize XHPIA prior to the first HPI8 access following a
device reset.
The HPI8 interface has two data strobes (HDS1 and HDS2), a read/write strobe (HR/W), and an address strobe
(HAS), to enable a glueless interface to a variety of industry-standard host devices. The HPI8 is easily interfaced
to hosts with multiplexed address/data bus, separate address and data buses, one data strobe, and a read/write
strobe, or two separate strobes for read and write.
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enhanced host-port interface (HPI8) (continued)
All memory accesses on the ’VC5410 are in shared-access mode, meaning both the DSP and the host can
access memory. Asynchronous host accesses are resynchronized internally, and in the event that the CPU and
the host both request access to the same memory block, the host has access priority. The HRDY pin provides
handshaking to the host during memory access.
The HPI8 also provides the capability to access memory during reset and power-down states. During reset, data
or application code can be loaded via the HPI8, and the application can be initiated through the HPI option of
the bootloader. During IDLE2/3 states, the HPI8 and the other six DMA channels continue to operate, and all
pending DMA events complete before the DSP stops the clocks. The HPI8 has higher priority than the other
six DMA channels. The HPI8 continues to have access to memory in IDLE2/3 even after the DSP has stopped
the internal clocks as long as X2/CLKIN is maintained. The ’VC5410 HPI8 also remains active during emulation
stop. The HPI8 can access any on-chip RAM on the device. The HPI8 memory map for the ’VC5410 is shown
in Figure 7. The HPI8 determines memory location by address only (program or data space is not relevant).
Address (Hex)
000 0000
Reserved
000 005F
000 0060
Scratch-Pad
RAM
000 007F
000 0080
DARAM
000 1FFF
000 2000
SARAM1
000 7FFF
000 8000
Reserved
001 7FFF
001 8000
SARAM2
001 FFFF
Figure 7. HPI8 Memory Map
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multichannel buffered serial ports
The ’VC5410 device provides three high-speed, full-duplex, multichannel buffered serial ports that allow direct
interface to other ’C54x/’LC54x devices, codecs, and other devices in a system. The McBSPs are based on the
standard serial-port interface found on other ’54x devices. Like their predecessors, the McBSPs provide:
D
D
D
Full-duplex communication
Double-buffer data registers, which allow a continuous data stream
Independent framing and clocking for receive and transmit
In addition, the McBSPs have the following capabilities:
D
Direct interface to:
–
–
–
–
–
–
T1/E1 framers
MVIP switching compatible and ST-BUS compliant devices
IOM-2 compliant devices
AC97-compliant devices
IIS-compliant devices
Serial peripheral interface (SPIt)
D
D
D
D
D
Multichannel transmit and receive of up to 128 channels
A wide selection of data sizes, including 8, 12, 16, 20, 24, or 32 bits
µ-law and A-law companding
Programmable polarity for both frame synchronization and data clocks
Programmable internal clock and frame generation
The McBSPs consist of separate transmit and receive channels that operate independently. The external
interface of each McBSP consists of the following pins:
D
D
D
D
D
D
D
BCLKX
BDX
BFSX
BCLKR
BDR
Transmit reference clock
Transmit data
Transmit frame synchronization
Receive reference clock
Receive data
BFSR
BCLKS
Receive frame synchronization
External clock reference for the programmable clock generator
The first six pins listed are identical to the previous serial-port interface pins on the C5000 family of DSPs. The
BCLKS pin is an additional signal to provide a clock reference to the McBSP programmable clock generator.
As a compatibility option, the ’VC5410 is provided in a 144-pin TQFP package (designated PGE) that is
pin-compatible with the ’C548/549 devices. BCLKS is not implemented on this package.
On the transmitter, transmit frame synchronization and clocking are indicated by the BFSX and BCLKX pins,
respectively. The CPU or DMA can initiate transmission of data by writing to the data transmit register (DXR).
Data written to DXR is shifted out on the BDX pin through a transmit shift register (XSR). This structure allows
DXR to be loaded with the next word to be sent while the transmission of the current word is in progress.
On the receiver, receive frame synchronization and clocking are indicated by the BFSR and BCLKR pins
respectively. The CPU or DMA can read received data from the data receive register (DRR). Data received on
the BDR pin is shifted into a receive shift register (RSR) and then buffered in the receive buffer register (RBR).
If DRR is empty, the RBR contents are copied into DRR. If not, RBR holds the data until DRR is available. This
structure allows storage of the two previous words while the reception of the current word is in progress.
SPI is a trademark of Motorola Incorporated.
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multichannel buffered serial ports (continued)
The CPU and DMA can move data to and from the McBSPs and can synchronize transfers based on McBSP
interrupts, event signals, and status flags. The DMA is capable of handling data movement between the
McBSPs and memory with no intervention from the CPU.
In addition to the standard serial-port functions, the McBSP provides programmable clock and frame
synchronization generation. Among the programmable functions are:
D
D
D
D
D
D
Frame synchronization pulse width
Frame period
Frame synchronization delay
Clock reference (internal vs. external)
Clock division
Clock and frame synchronization polarity
The on-chip companding hardware allows compression and expansion of data in either µ-law or A-law format.
When companding is used, transmit data is encoded according to specified companding law and received data
is decoded to 2s complement format.
The McBSP allows the multiple channels to be independently selected for the transmitter and receiver. When
the multiple channels are selected, each frame represents a time-division multiplexed (TDM) data stream. In
using TDM data streams, the CPU may only need to process a few of them. Thus, to save memory and bus
bandwidth, multichannel selection allows independent enabling of particular channels for transmission and
reception. Up to 32 channels in a bit stream of up to 128 channels can be enabled.
The clock-stop mode (CLKSTP) in the McBSP provides compatibility with the serial peripheral interface (SPI)
protocol. Clock-stop mode works with only single-phase frames and one word per frame. The word sizes
supported by the McBSP are programmable for 8-, 12-, 16-, 20-, 24-, or 32-bit operation. When the McBSP is
configured to operate in SPI mode, both the transmitter and the receiver operate together as a master or as a
slave.
The McBSP is fully static and operates at arbitrarily low clock frequencies. The maximum frequency is CPU
clock frequency divided by 2.
hardware timer
The ’VC5410 device features a 16-bit timing circuit with a 4-bit prescaler. The timer counter is decremented by
one every CPU clock cycle. Each time the counter decrements to 0, a timer interrupt is generated. The timer
can be stopped, restarted, reset, or disabled by specific status bits.
clock generator
The clock generator provides clocks to the ’VC5410 device, and consists of an internal oscillator and a
phase-locked loop (PLL) circuit. The clock generator requires a reference clock input, which can be provided
by using a crystal resonator with the internal oscillator, or from an external clock source. The reference clock
input is then divided by two (DIV mode) to generate clocks for the ’VC5410 device, or the PLL circuit can be
used (PLL mode) to generate the device clock by multiplying the reference clock frequency by a scale factor,
allowing use of a clock source with a lower frequency than that of the CPU.The PLL is an adaptive circuit that,
once synchronized, locks onto and tracks an input clock signal.
When the PLL is initially started, it enters a transitional mode during which the PLL acquires lock with the input
signal. Once the PLL is locked, it continues to track and maintain synchronization with the input signal. Then,
other internal clock circuitry allows the synthesis of new clock frequencies for use as master clock for the
’VC5410 device.
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clock generator (continued)
This clock generator allows system designers to select the clock source. The sources that drive the clock
generator are:
D
D
A crystal resonator circuit. The crystal resonator circuit is connected across the X1 and X2/CLKIN pins of
the ’VC5410 to enable the internal oscillator.
An external clock. The external clock source is directly connected to the X2/CLKIN pin, and X1 is left
unconnected.
The software-programmable PLL features a high level of flexibility, and includes a clock scaler that provides
various clock multiplier ratios, capability to directly enable and disable the PLL, and a PLL lock timer that can
be used to delay switching to PLL clocking mode of the device until lock is achieved.Devices that have a built-in
software-programmable PLL can be configured in one of two clock modes:
D
PLL mode. The input clock (X2/CLKIN) is multiplied by 1 of 31 possible ratios.
DIV (divider) mode. The input clock is divided by 2 or 4. Note that when DIV mode is used, the PLL can be
completely disabled in order to minimize power dissipation.
D
The software-programmable PLL is controlled using the 16-bit memory-mapped (address 0058h) clock mode
register (CLKMD). The CLKMD register is used to define the clock configuration of the PLL clock module. Note
that upon reset, the CLKMD register is initialized with a predetermined value dependent only upon the state of
the CLKMD1 – CLKMD3 pins. The CLKMD pin configured clock options are shown in Table 5.
Table 5. CLKMD Pin Configured Clock Options
CLKMD REGISTER
RESET VALUE
CLKMD1
CLKMD2
CLKMD3
CLOCK MODE
0
0
0
0
0
1
0000h
Divide-by-2, with external source
Divide-by-2, with external source
1000h
0
0
1
1
1
1
1
1
0
0
1
1
0
1
0
1
0
1
2000h
–
Divide-by-2, with external source
Stop mode
4000h
0007h
6000h
7000h
Divide-by-2, internal oscillator enabled
PLLx1 with external source
Divide-by-2, with external source
Reserved
enhanced external parallel interface (XIO2)
The ’VC5410 external interface has been redesigned to include several improvements, including: simplification
of the bus sequence, more immunity to bus contention when transitioning between read and write operation,
the ability for external memory access to the DMA controller, and optimization of the power-down modes.
The bus sequence on the ’VC5410 still maintains all of the same interface signals as on previous ’54x devices,
but the signal sequence has been simplified. Most external accesses now require 3 cycles composed of a
leading cycle, an active (read or write) cycle, and a trailing cycle. The leading and trailing cycles provide
additional immunity against bus contention when switching between read operations and write operations. To
maintain high-speed read access, a consecutive read mode that performs single-cycle reads as on previous
’54x devices is available.
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enhanced external parallel interface (XIO2) (continued)
Figure 8 shows the bus sequence for three cases: all I/O reads, memory reads in nonconsecutive mode, or
single memory reads in consecutive mode. The accesses shown in Figure 8 always require 3 CLKOUT cycles
to complete.
CLKOUT
A[22:0]
D[15:0]
R/W
READ
MSTRB or IOSTRB
PS/DS/IS
Leading
Cycle
Read
Cycle
Trailing
Cycle
Figure 8. Nonconsecutive Memory Read and I/O Read Bus Sequence
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enhanced external parallel interface (XIO2) (continued)
Figure 9 shows the bus sequence for repeated memory reads in consecutive mode. The accesses shown in
Figure 9 require (2+n) CLKOUT cycles to complete, where n is the number of consecutive reads performed.
CLKOUT
A[22:0]
D[15:0]
R/W
READ
READ
READ
MSTRB
PS/DS
Leading
Cycle
Read
Cycle
Read
Cycle
Read
Cycle
Trailing
Cycle
Figure 9. Consecutive Memory Read Bus Sequence (n = 3 reads)
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enhanced external parallel interface (XIO2) (continued)
Figure 10 shows the bus sequence for all memory writes and I/O writes. The accesses shown in Figure 10
always require 3 CLKOUT cycles to complete.
CLKOUT
A[22:0]
D[15:0]
R/W
WRITE
MSTRB or IOSTRB
PS/DS/IS
Leading
Cycle
Write
Cycle
Trailing
Cycle
Figure 10. Memory Write and I/O Write Bus Sequence
The enhanced interface also provides the ability for DMA transfers to extend to external memory. For more
information on DMA capability, see the DMA sections that follow.
The enhanced interface improves the low-power performance already present on the ’C5000 family by
switching off the internal clocks to the interface when it is not being used. This power-saving feature is automatic,
requires no software setup, and causes no latency in the operation of the interface.
Additional features integrated in the enhanced interface are the ability to automatically insert bank-switching
cycles when crossing 32K memory boundaries (see the “programmable bank-switching” section), the ability to
program up to 14 wait states through software (see the “software-programmable wait-state generator” section),
and the ability to divide down CLKOUT by a factor of 1, 2, 3, or 4. Dividing down CLKOUT provides an alternative
to wait states when interfacing to slower external memory or peripheral devices. While inserting wait states
extends the bus sequence during read or write accesses, it does not slow down the bus signal sequences at
the beginning and the end of the access. Dividing down CLKOUT provides a method of slowing the entire bus
sequence when necessary. The CLKOUT divide-down factor is controlled through the DIVFCT field in the
bank-switching control register (BSCR).
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DMA controller
The ’VC5410 direct memory access (DMA) controller transfers data between points in the memory map without
intervention by the CPU. The DMA allows movements of data to and from internal program/data memory,
internal peripherals (such as the McBSPs), or external memory devices to occur in the background of CPU
operation. The DMA has six independent programmable channels, allowing six different contexts for DMA
operation.
features
The DMA has the following features:
D
D
D
D
D
The DMA operates independently of the CPU.
The DMA has six channels. The DMA can keep track of the contexts of six independent block transfers.
The DMA has higher priority than the CPU for both internal and external accesses.
Each channel has independently programmable priorities.
Each channel’s source and destination address registers can have configurable indexes through memory
on each read and write transfer, respectively. The address may remain constant, be post-incremented, be
post-decremented, or be adjusted by a programmable value.
D
D
D
Each read or write transfer may be initialized by selected events.
On completion of a half- or entire-block transfer, each DMA channel may send an interrupt to the CPU.
The DMA can perform double-word transfers (a 32-bit transfer of two 16-bit words).
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DMA memory map
The DMA memory map, see Figure 11, allows the DMA transfer to be unaffected by the status of the MP/MC,
DROM, and OVLY bits.
Program
Program
Program
Data
Hex
0000
Hex
Hex
XX0000
Hex
010000
0000
Reserved
DRR20
001F
0020
Reserved
007F
0080
0021
0022
0023
0024
DRR10
DXR20
DXR10
Reserved
002F
0030
0031
0032
DRR22
DRR12
DXR22
0033
0034
DXR12
Reserved
0035
0036
RCERA2
XCERA2
0037
0038
Reserved
External
External
External
0039
003A
RCERA0
XCERA0
003B
003C
Reserved
DRR21
003F
0040
0041
DRR11
DXR21
DXR11
0042
0043
0044
Reserved
0049
004A
004B
004C
RCERA1
XCERA1
Reserved
BFFF
C000
005F
0060
Scratch-Pad
RAM
017FFF
018000
007F
0080
DARAM
1FFF
2000
SARAM2
Page 1
On-Chip ROM
SARAM1
External
7FFF
8000
FFFF
01FFFF
XXFFFF
FFFF
Page 0
Page 2,3,...
Figure 11. DMA Memory Map
DMA priority level
Each DMA channel can be independently assigned high- or low-priority relative to each other. Multiple DMA
channels that are assigned to the same priority level are handled in a round-robin manner.
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DMA source/destination address modification
The DMA provides flexible address-indexing modes for easy implementation of data management schemes
such as autobuffering and circular buffers. Source and destination addresses can be indexed separately and
can be post-incremented, post-decremented, or post-incremented with a specified index offset.
DMA in autoinitialization mode
The DMA can automatically reinitialize itself after completion of a block transfer. Some of the DMA registers can
be preloaded for the next block transfer through the DMA global reload registers (DMGSA, DMGDA, and
DMGCR). Autoinitialization allows:
D
D
Continuous operation: Normally, the CPU would have to reinitialize the DMA immediately after the
completion of the current block transfers, but with the global reload registers, it can reinitialize these values
for the next block transfer any time after the current block transfer begins.
Repetitive operation: The CPU does not preload the global reload register with new values for each block
transfer but only loads them on the first block transfer.
DMA transfer counting
The DMA channel element count register (DMCTRx) and the frame count register (DMFRCx) contain bit fields
that represent the number of frames and the number of elements per frame to be transferred.
D
Frame count. This 8-bit value defines the total number of frames in the block transfer. The maximum
number of frames per block transfer is 128 (FRAME COUNT= 0ffh). The counter is decremented upon the
last read transfer in a frame transfer. Once the last frame is transferred, the selected 8-bit counter is
reloaded with the DMA global frame reload register (DMGFR) if the AUTOINIT bit is set to 1. A frame count
of 0 (default value) means the block transfer contains a single frame.
D
Element count. This 16-bit value defines the number of elements per frame. This counter is decremented
after the read transfer of each element. The maximum number of elements per frame is 65536
(DMCTRn = 0ffffh). In autoinitialization mode, once the last frame is transferred, the counter is reloaded with
the DMA global count reload register (DMGCR).
DMA transfer in double-word mode
Double-word mode allows the DMA to transfer 32-bit words in any index mode. In double-word mode, two
consecutive 16-bit transfers are initiated and the source and destination addresses are automatically updated
following each transfer. In this mode, each 32-bit word is considered to be one element.
DMA channel index registers
The particular DMA channel index register is selected by way of the SIND and DIND fields in the DMA mode
control register (DMMCRx). Unlike basic address adjustment, in conjunction with the frame index DMFRI0 and
DMFRI1, the DMA allows different adjustment amounts depending on whether or not the element transfer is
the last in the current frame. The normal adjustment value (element index) is contained in the element index
registers DMIDX0 and DMIDX1. The adjustment value (frame index) for the end of the frame, is determined by
the selected DMA frame index register, either DMFRI0 or DMFRI1.
The element index and the frame index affect address adjustment as follows:
D
D
Element index: For all except the last transfer in the frame, the element index determines the amount to be
added to the DMA channel for the source/destination address register (DMSRCx/DMDSTx) as selected by
the SIND/DIND bits.
Frame index: If the transfer is the last in a frame, frame index is used for address adjustment as selected
by the SIND/DIND bits. This occurs in both single-frame and multi-frame transfers.
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DMA interrupts
The ability of the DMA to interrupt the CPU based on the status of the data transfer is configurable and is
determined by the IMOD and DINM bits in the DMA channel mode control register (DMMCRn). The available
modes are shown in Table 6.
Table 6. DMA Interrupts
MODE
ABU (non-decrement)
ABU (non-decrement)
Multi-Frame
DINM
IMOD
INTERRUPT
1
1
1
1
0
0
0
1
0
1
X
X
At full buffer only
At half buffer and full buffer
At block transfer complete (DMCTRn = DMSEFCn[7:0] = 0)
At end of frame and end of block (DMCTRn = 0)
No interrupt generated
Multi-Frame
Either
Either
No interrupt generated
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memory-mapped registers
The ’VC5410 has 27 memory-mapped CPU registers, which are mapped in data memory space address 0h
to 1Fh. Each ’VC5410 device also has a set of memory-mapped registers associated with peripherals. Table 7
gives a list of CPU memory-mapped registers (MMRs) available on ’VC5410. Table 8 shows additional
peripheral MMRs associated with the ’VC5410.
Table 7. CPU Memory-Mapped Registers
ADDRESS
NAME
DESCRIPTION
DEC
0
HEX
0
IMR
IFR
—
Interrupt mask register
Interrupt flag register
Reserved for testing
Status register 0
1
1
2–5
6
2–5
6
ST0
ST1
AL
7
7
Status register 1
8
8
Accumulator A low word (15–0)
AH
9
9
Accumulator A high word (31–16)
Accumulator A guard bits (39–32)
Accumulator B low word (15–0)
Accumulator B high word (31–16)
Accumulator B guard bits (39–32)
Temporary register
AG
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
A
BL
B
BH
C
BG
D
TREG
TRN
AR0
AR1
AR2
AR3
AR4
AR5
AR6
AR7
SP
E
F
Transition register
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
Auxiliary register 0
Auxiliary register 1
Auxiliary register 2
Auxiliary register 3
Auxiliary register 4
Auxiliary register 5
Auxiliary register 6
Auxiliary register 7
Stack pointer register
BK
Circular buffer size register
Block repeat counter
BRC
RSA
REA
PMST
XPC
—
Block repeat start address
Block repeat end address
Processor mode status (PMST) register
Extended program page register
Reserved
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memory-mapped registers (continued)
Table 8. Peripheral Memory-Mapped Registers
NAME
DRR20
ADDRESS
20h
SUB-ADDRESS
DESCRIPTION
McBSP0 data receive register
TYPE
McBSP #0
McBSP #0
McBSP #0
McBSP #0
Timer
—
—
DRR10
DXR20
DXR10
TIM
21h
McBSP0 data receive register
McBSP0 data transmit register
McBSP0 data transmit register
Timer register
22h
—
23h
—
24h
—
PRD
25h
—
Timer period counter
Timer
TCR
26h
—
Timer control register
Timer
—
27h
—
Reserved
SWWSR
BSCR
28h
—
Software wait-state register
External Bus
External Bus
29h
—
Bank-switching control register
Reserved
—
2Ah
2Bh
2Ch
2Dh–2Fh
30h
—
SWCR
HPIC
—
Software wait-state control register
HPI control register
External Bus
HPI
—
—
—
Reserved
DRR22
DRR12
DXR22
DXR12
SPSA2
SPCR12
SPCR22
RCR12
RCR22
XCR12
XCR22
SRGR12
SRGR22
MCR12
MCR22
RCERA2
RCERB2
XCERA2
XCERB2
PCR2
—
McBSP2 data receive register
McBSP2 data receive register
McBSP2 data transmit register
McBSP2 data transmit register
McBSP2 sub-address register
McBSP2 serial port control register 1
McBSP2 serial port control register 2
McBSP2 receive control register 1
McBSP2 receive control register 2
McBSP2 transmit control register 1
McBSP2 transmit control register 2
McBSP2 sample rate generator register 1
McBSP2 sample rate generator register 2
McBSP2 multichannel register 1
McBSP2 multichannel register 2
McBSP2 receive channel enable register partition A
McBSP2 receive channel enable register partition B
McBSP2 transmit channel enable register partition A
McBSP2 transmit channel enable register partition B
McBSP2 pin control register
McBSP #2
McBSP #2
McBSP #2
McBSP #2
McBSP #2
McBSP #2
McBSP #2
McBSP #2
McBSP #2
McBSP #2
McBSP #2
McBSP #2
McBSP #2
McBSP #2
McBSP #2
McBSP #2
McBSP #2
McBSP #2
McBSP #2
McBSP #2
31h
—
32h
—
33h
—
34h
—
35h
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
—
35h
35h
35h
35h
35h
35h
35h
35h
35h
35h
35h
35h
35h
35h
—
36h–37h
38h
Reserved
SPSA0
SPCR10
SPCR20
RCR10
RCR20
XCR10
—
McBSP0 sub-address register
McBSP0 serial port control register 1
McBSP0 serial port control register 2
McBSP0 receive control register 1
McBSP0 receive control register 2
McBSP0 transmit control register 1
McBSP #0
McBSP #0
McBSP #0
McBSP #0
McBSP #0
McBSP #0
39h
00h
01h
02h
03h
04h
39h
39h
39h
39h
†
Accesses to address 56h update the sub-addressed register and post-increment the sub-address contained in DMSBAR. Accesses to 57h
update the sub-addressed register without modifying DMSBAR.
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memory-mapped registers (continued)
Table 8. Peripheral Memory-Mapped Registers (Continued)
NAME
XCR20
ADDRESS
39h
SUB-ADDRESS
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
—
DESCRIPTION
McBSP0 transmit control register 2
McBSP0 sample rate generator register 1
McBSP0 sample rate generator register 2
McBSP0 multichannel register 1
TYPE
McBSP #0
McBSP #0
McBSP #0
McBSP #0
McBSP #0
McBSP #0
McBSP #0
McBSP #0
McBSP #0
McBSP #0
SRGR10
SRGR20
MCR10
MCR20
RCERA0
RCERB0
XCERA0
XCERB0
PCR0
39h
39h
39h
39h
McBSP0 multichannel register 2
39h
McBSP0 receive channel enable register partition A
McBSP0 receive channel enable register partition B
McBSP0 transmit channel enable register partition A
McBSP0 transmit channel enable register partition B
McBSP0 pin control register
39h
39h
39h
39h
—
3Ah–3Fh
40h
Reserved
DRR21
DRR11
DXR21
DXR11
—
McBSP1 Data receive register 2
McBSP #1
McBSP #1
McBSP #1
McBSP #1
41h
—
McBSP1 Data receive register 1
42h
—
McBSP1 Data transmit register 2
43h
—
McBSP1 Data transmit register 1
—
44h–47h
48h
—
Reserved
SPSA1
SPCR11
SPCR21
RCR11
RCR21
XCR11
—
McBSP1 sub-address register
McBSP #1
McBSP #1
McBSP #1
McBSP #1
McBSP #1
McBSP #1
McBSP #1
McBSP #1
McBSP #1
McBSP #1
McBSP #1
McBSP #1
McBSP #1
McBSP #1
McBSP #1
McBSP #1
49h
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
—
McBSP1 serial port control register 1
McBSP1 serial port control register 2
McBSP1 receive control register 1
49h
49h
49h
McBSP1 receive control register 2
49h
McBSP1 transmit control register 1
McBSP1 transmit control register 2
McBSP1 sample rate generator register 1
McBSP1 sample rate generator register 2
McBSP1 multichannel register 1
XCR21
SRGR11
SRGR21
MCR11
MCR21
RCERA1
RCERB1
XCERA1
XCERB1
PCR1
49h
49h
49h
49h
49h
McBSP1 multichannel register 2
49h
McBSP1 receive channel enable register partition A
McBSP1 receive channel enable register partition B
McBSP1 transmit channel enable register partition A
McBSP1 transmit channel enable register partition B
McBSP1 pin control register
49h
49h
49h
49h
—
4Ah–53h
54h
Reserved
DMPREC
DMSBAR
DMSRC0
DMDST0
DMCTR0
DMSFC0
DMMCR0
DMSRC1
—
DMA channel priority and enable control register
DMA channel sub-address register
DMA channel 0 source address register
DMA channel 0 destination address register
DMA channel 0 element count register
DMA channel 0 sync select and frame count register
DMA channel 0 transfer mode control register
DMA channel 1 source address register
DMA
DMA
DMA
DMA
DMA
DMA
DMA
DMA
55h
—
†
†
†
†
†
†
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
00h
01h
02h
03h
04h
05h
†
Accesses to address 56h update the sub-addressed register and post-increment the sub-address contained in DMSBAR. Accesses to 57h
update the sub-addressed register without modifying DMSBAR.
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memory-mapped registers (continued)
Table 8. Peripheral Memory-Mapped Registers (Continued)
NAME
DMDST1
ADDRESS
SUB-ADDRESS
06h
DESCRIPTION
TYPE
DMA
DMA
DMA
DMA
DMA
DMA
DMA
DMA
DMA
DMA
DMA
DMA
DMA
DMA
DMA
DMA
DMA
DMA
DMA
DMA
DMA
DMA
DMA
DMA
†
†
†
†
†
†
†
†
†
†
†
†
†
†
†
†
†
†
†
†
†
†
†
†
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
DMA channel 1 destination address register
DMA channel 1 element count register
DMCTR1
DMSFC1
DMMCR1
DMSRC2
DMDST2
DMCTR2
DMSFC2
DMMCR2
DMSRC3
DMDST3
DMCTR3
DMSFC3
DMMCR3
DMSRC4
DMDST4
DMCTR4
DMSFC4
DMMCR4
DMSRC5
DMDST5
DMCTR5
DMSFC5
DMMCR5
07h
08h
DMA channel 1 sync select and frame count register
DMA channel 1 transfer mode control register
DMA channel 2 source address register
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
DMA channel 2 destination address register
DMA channel 2 element count register
DMA channel 2 sync select and frame count register
DMA channel 2 transfer mode control register
DMA channel 3 source address register
10h
DMA channel 3 destination address register
DMA channel 3 element count register
11h
12h
DMA channel 3 sync select and frame count register
DMA channel 3 transfer mode control register
DMA channel 4 source address register
13h
14h
15h
DMA channel 4 destination address register
DMA channel 4 element count register
16h
17h
DMA channel 4 sync select and frame count register
DMA channel 4 transfer mode control register
DMA channel 5 source address register
18h
19h
1Ah
1Bh
1Ch
1Dh
DMA channel 5 destination address register
DMA channel 5 element count register
DMA channel 5 sync select and frame count register
DMA channel 5 transfer mode control register
DMA source program page address (common
channel)
†
†
DMSRCP
DMDSTP
56h/57h
56h/57h
1Eh
1Fh
DMA
DMA
DMA destination program page address (common
channel)
†
†
†
†
†
†
†
†
DMIDX0
DMIDX1
DMFRI0
DMFRI1
DMGSA
DMGDA
DMGCR
DMGFR
CLKMD
—
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
58h
20h
21h
22h
23h
24h
25h
26h
27h
—
DMA element index address register 0
DMA element index address register 1
DMA frame index register 0
DMA
DMA
DMA
DMA
DMA
DMA
DMA
DMA
PLL
DMA frame index register 1
DMA global source address reload register
DMA global destination address reload register
DMA global count reload register
DMA global frame count reload register
Clock mode register
59h – 5Fh
—
Reserved
†
Accesses to address 56h update the sub-addressed register and post-increment the sub-address contained in DMSBAR. Accesses to 57h
update the sub-addressed register without modifying DMSBAR.
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interrupts
Vector-relative locations and priorities for all internal and external interrupts are shown in Table 9.
Table 9. Interrupt Locations and Priorities
LOCATION
DECIMAL
NAME
PRIORITY
FUNCTION
HEX
00
RS, SINTR
NMI, SINT16
SINT17
0
1
2
Reset (hardware and software reset)
Nonmaskable interrupt
4
04
8
08
—
—
—
—
—
—
—
—
—
—
—
—
—
—
3
Software interrupt #17
SINT18
12
0C
10
Software interrupt #18
SINT19
16
Software interrupt #19
SINT20
20
14
Software interrupt #20
SINT21
24
18
Software interrupt #21
SINT22
28
1C
20
Software interrupt #22
SINT23
32
Software interrupt #23
SINT24
36
24
Software interrupt #24
SINT25
40
28
Software interrupt #25
SINT26
44
2C
30
Software interrupt #26
SINT27
48
Software interrupt #27
SINT28
52
34
Software interrupt #28
SINT29
56
38
Software interrupt #29
SINT30
60
3C
40
Software interrupt #30
INT0, SINT0
INT1, SINT1
INT2, SINT2
TINT, SINT3
RINT0, SINT4
XINT0, SINT5
RINT2, SINT6
XINT2, SINT7
INT3, SINT8
HINT, SINT9
64
External user interrupt #0
External user interrupt #1
External user interrupt #2
Timer interrupt
68
44
4
72
48
5
76
4C
50
6
80
7
McBSP #0 receive interrupt (default)
McBSP #0 transmit interrupt (default)
McBSP #2 receive interrupt (default)
McBSP #2 transmit interrupt (default)
External user interrupt #3
HPI interrupt
84
54
8
88
58
9
92
5C
60
10
11
12
13
14
15
16
—
96
100
104
108
112
116
120–127
64
RINT1, SINT10
XINT1, SINT11
DMAC4,SINT12
DMAC5,SINT13
Reserved
68
McBSP #1 receive interrupt (default)
McBSP #1 transmit interrupt (default)
DMA channel 4 (default)
DMA channel 5 (default)
Reserved
6C
70
74
78–7F
The bit layout of the interrupt flag register (IFR) and the interrupt mask register (IMR) is shown in Figure 12.
15–14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RES DMAC5 DMAC4 XINT1 RINT1 HINT
INT3
XINT2 RINT2 XINT0 RINT0
TINT
INT2
INT1
INT0
Figure 12. IFR and IMR
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documentation support
Extensive documentation supports all TMS320 family generations of devices from product announcement
through applications development. The following types of documentation are available to support the design
and use of the ’C5000 family of DSPs:
D
D
D
D
D
TMS320C5000 DSP Family Functional Overview (literature number SPRU307)
Device-specific data sheets (such as this document)
Complete user’s guides
Development support tools
Hardware and software application reports
The four-volume TMS320C54x DSP Reference Set (literature number SPRU210) consists of:
D
D
D
D
Volume 1: CPU and Peripherals (literature number SPRU131)
Volume 2: Mnemonic Instruction Set (literature number SPRU172)
Volume 3: Algebraic Instruction Set (literature number SPRU179)
Volume 4: Applications Guide (literature number SPRU173)
The reference set describes in detail the ’54x TMS320 products currently available and the hardware and
software applications, including algorithms, for fixed-point TMS320 devices.
For general background information on DSPs and TI devices, see the three-volume publication Digital Signal
Processing Applications with the TMS320 Family (literature numbers SPRA012, SPRA016, and SPRA017).
A series of DSP textbooks is published by Prentice-Hall and John Wiley & Sons to support digital signal
processing research and education. The TMS320 newsletter, Details on Signal Processing, is published
quarterly and distributed to update TMS320 customers on product information.
Information regarding TI DSP products is also available on the Worldwide Web at http://www.ti.com uniform
resource locator (URL).
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†
absolute maximum ratings over specified temperature range (unless otherwise noted)
Supply voltage I/O range, DV ‡ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 4.6 V
DD
DD
‡
Supply voltage core range, CV
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 3.75 V
Input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 4.6 V
Output voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 4.6 V
Operating case temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 100°C
C
Storage temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to 150°C
stg
†
‡
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to V
.
SS
recommended operating conditions
MIN NOM
MAX
3.6
UNIT
V
§
DV
CV
Device supply voltage, I/O
3
3.3
2.5
DD
DD
§
Device supply voltage, core
Supply voltage, GND
2.4
2.75
V
V
V
V
0
V
V
SS
TCK, DV
DD
= 3.3"0.3 V
3
DV
+ 0.3
DD
RS, INTn, NMI, X2/CLKIN,
BCLKR0, BCLKR1, BCLKR2,
BCLKX0, BCLKX1, BCLKX2,
BCLKS0, BCLKS1, BCLKS2,
HCS, HDS1, HDS2, HAS
High-level input voltage, I/O
2.5
DV
DV
+ 0.3
+ 0.3
IH
DD
DD
V
CLKMDn, DV
DD
= 3.3"0.3 V
All other inputs
2
Low-level input voltage
High-level output current
Low-level output current
Operating case temperature
–0.3
0.8
V
IL
I
I
–300
1.5
µA
mA
°C
OH
OL
T
C
–40
100
§
Texas Instrument DSPs do not require specific power sequencing between the core supply and the I/O supply. However, systems should be
designed to ensure that neither supply is powered up for extended periods of time if the other supply is below the proper operating voltage.
Excessive exposure to these conditions can adversely affect the long term reliability of the devices. System-level concerns such as bus contention
may require supply sequencing to be implemented. In this case, the core supply should be powered up at the same time as or prior to the I/O
buffers and then powered down after the I/O buffers.
Refer to Figure 13 for 3.3-V device test load circuit values.
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SPRS075D – OCTOBER 1998 – REVISED MAY 2000
electrical characteristics over recommended operating case temperature range (unless otherwise
noted)
†
TYP
PARAMETER
TEST CONDITIONS
= 3.3"0.3 V,I = MAX
MIN
2.4
MAX
UNIT
‡
V
V
DV
V
High-level output voltage
OH
DD
= MAX
OH
‡
Low-level output voltage
I
0.4
V
OL
OL
DV
Input current in high
I
I
A[22:0]
= MAX, V = V
SS
to DV
DD
–175
175
µA
IZ
DD
O
impedance
TRST
With internal pulldown
–10
–10
800
400
HPIENA
With internal pulldown, RS = 0
TMS, TCK, TDI,
BCLKS0, BCLKS1,
BCLKS2, HPI
With internal pullups
–400
10
Input current
µA
§
I
(V = V
SS
to V )
DD
I
Bus holders enabled, DV
DD
= MAX,
D[15:0], HD[7:0]
–175
–10
175
10
V = DV
to DV
I
SS
DD
All other input-only pins
¶
= 2.5 V, 100 MHz CPU clock,
CV
DD
= 25°C
#
I
I
Supply current, core CPU
Supply current, pins
47
mA
DDC
T
C
DV
= 3.3 V, 100 MHz CPU clock,
= 25°C
DD
||
22
mA
mA
DDP
T
C
IDLE2
IDLE3
PLL × 2 mode, 50 MHz input, T = 25°C
2
5
C
Supply current,
standby
I
DD
Divide-by-two mode, CLKIN stopped,
µA
T
C
= 25°C
C
C
Input capacitance
Output capacitance
10
10
pF
pF
i
o
†
‡
§
¶
#
All values are typical unless otherwise specified.
All input and output voltage levels except RS, INT0–INT3, NMI, X2/CLKIN, CLKMD0–CLKMD3 are LVTTL-compatible.
HPI input signals except for HPIENA.
Clock mode: PLL × 2 with external source
This value was obtained with 50% usage of MAC and 50% usage of NOP instructions. Actual operating current varies with program being
executed.
||
This value was obtained with continous external writes, CLKOFF = 0 and load = 15 pF. For more details on how this calculation is performed,
refer to the Calculation of TMS320LC54x Power Dissipation application report (literature number SPRA164).
37
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
T M S3 2 0 VC5 410
E
F
I
X
D
Ć
P
O
I
N
T
D
I
G
I
TA
L
S
I
GN
A
L
PRO CE SSO R
SPRS075D – OCTOBER 1998 – REVISED MAY 2000
PARAMETER MEASUREMENT INFORMATION
I
OL
50 Ω
Output
Under
Test
Tester Pin
Electronics
V
Load
C
T
I
OH
Where:
I
I
= 1.5 mA (all outputs)
= 300 µA (all outputs)
= 1.5 V
OL
OH
V
Load
C
= 40-pF typical load circuit capacitance
T
Figure 13. 3.3-V Test Load Circuit
38
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
T MS 3 20 VC 54 10
F IX EDĆPO I NT DI GI TAL SI G NAL P RO C ES S O R
SPRS075D – OCTOBER 1998 – REVISED MAY 2000
internal divide-by-two clock option with external crystal
The internal oscillator on the ’5410 is enabled by setting the CLKMD(1,2,3) pins to (1,0,0) at reset and
connecting a crystal or ceramic resonator across X1 and X2/CLKIN. The CPU clock frequency is one-half the
crystal’s oscillation frequency following reset. Since the internal oscillator can be used as a clock source to the
PLL, the crystal oscillation frequency can be multiplied to generate the CPU clock if desired.
The crystal should be in fundamental mode operation and parallel resonant with an effective series resistance
of 30 ohms and power dissipation of 1 mW. The connection of the required circuit, consisting of the crystal and
two load capacitors, is shown in Figure 14. The load capacitors, C and C , should be chosen such that the
1
2
equation below is satisfied. C in the equation is the load specified for the crystal.
L
C1C2
CL +
(C1 ) C2)
’VC5410-100
’VC5410-120
MIN NOM MAX
UNIT
MIN NOM
MAX
†
0
‡
50
†
0
‡
50
f
x
Input clock frequency
MHz
†
‡
This device utilizes a fully static design and therefore can operate with t
approaching 0 Hz.
It is recommended that the PLL clocking option be used for maximum frequency operation.
approaching ∞. The device is characterized at frequencies
c(CI)
X1
X2/CLKIN
Crystal
C1
C2
Figure 14. Internal Divide-by-Two Clock Option With External Crystal
PR O DU C T PR EVI EW inf or ma tio n co nce r ns pr od uct s in th e fo rm at iv e o r
de s i gn ph a s e of de ve lopm ent . C ha ra ct er is tic da ta an d o the r
s pe c i fi c a t io ns a r e de s ig n goa ls . Tex as Ins tr um ent s r es er v es th e r i gh t to
c ha n ge or di s c on ti nu e th es e pr od uct s w ith out not ice .
39
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
T M S3 2 0 VC5 410
F I X ED ĆPOI N T DI G I TAL S I GN AL PRO CE SSO R
SPRS075D – OCTOBER 1998 – REVISED MAY 2000
external divide-by-two clock option
An external frequency source can be used by applying an input clock to X2/CLKIN with X1 left unconnected.
Table 5 shows the configuration options for the CLKMD pins that generate the external divide-by-2 clock option.
This external input clock frequency is divided by two to generate the CPU machine cycle.
The external frequency injected must conform to specifications listed in the timing requirements table.
switching characteristics over recommended operating conditions [H = 0.5t
(see Figure 14, Figure 15, and the recommended operating conditions table)
]
c(CO)
’VC5410-100
’VC5410-120
PARAMETER
UNIT
MIN
TYP
MAX
MIN
TYP
MAX
†
‡
†
‡
t
Cycle time, CLKOUT
10
2t
8.33
2t
ns
ns
ns
ns
ns
ns
c(CO)
c(CI)
6
c(CI)
6
t
Delay time, X2/CLKIN high to CLKOUT high/low
Fall time, CLKOUT
3
10
3
10
d(CIH-CO)
t
2
2
2
2
f(CO)
t
t
t
Rise time, CLKOUT
r(CO)
Pulse duration, CLKOUT low
Pulse duration, CLKOUT high
H–2
H–2
H–1
H–1
H
H
H–2
H–2
H–1
H–1
H
H
w(COL)
w(COH)
†
‡
It is recommended that the PLL clocking option be used for maximum frequency operation.
This device utilizes a fully static design and therefore can operate with t
approaching 0 Hz.
approaching ∞. The device is characterized at frequencies
c(CI)
P ROD UCT PR EV IEW in f or m a ti on co nce r ns pr od uct s in th e fo rm at iv e or
d e s i g n ph a s e of de v e l op me nt. C ha ra ct er is tic da ta an d ot her
s p e c i fi ca t i ons a r e de s i gn go a ls . Tex a s Ins tr um ent s r es er v es th e r igh t to
c h a n g e or di s c on ti nue t he s e pr od uct s w ith out not ice .
40
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
T MS 3 20 VC 54 10
F IX EDĆPO I NT DI GI TAL SI G NAL P RO C ES S O R
SPRS075D – OCTOBER 1998 – REVISED MAY 2000
external divide-by-two clock option (continued)
timing requirements (see Figure 15)
’VC5410-100
’VC5410-120
UNIT
MIN
MAX
MIN
MAX
†
†
t
t
t
t
t
Cycle time, X2/CLKIN
5
4.167
ns
ns
ns
ns
ns
c(CI)
Fall time, X2/CLKIN
1
1
f(CI)
Rise time, X2/CLKIN
1
†
1
†
r(CI)
Pulse duration, X2/CLKIN low
Pulse duration, X2/CLKIN high
2
2
2
2
w(CIL)
w(CIH)
†
†
†
This device utilizes a fully static design and therefore can operate with t
approaching 0 Hz.
approaching ∞. The device is characterized at frequencies
c(CI)
t
t
t
t
f(CI)
r(CI)
c(CI)
w(CIH)
t
w(CIL)
X2/CLKIN
t
f(CO)
t
c(CO)
t
t
r(CO)
w(COH)
t
d(CIH–CO)
t
w(COL)
CLKOUT
NOTE A: The CLKOUT timing in this diagram assumes the CLKOUT divide factor (DIVFCT field in the BSCR) is configured as 00 (CLKOUT not
divided). DIVFCT is configured as CLKOUT divided-by-4 mode following reset.
Figure 15. External Divide-by-Two Clock Timing
PR O DU C T PR EVI EW inf or ma tio n co nce r ns pr od uct s in th e fo rm at iv e o r
de s i gn
s pe c i fi c a t io ns a r e de s ig n goa ls . Tex as Ins tr um ent s r es er v es th e r i gh t to
c ha n ge or di s c on ti nu e th es e pr od uct s w ith out not ice .
p
h
a
s
e
of
d
e
v
e
l
o
p
m
e
n
t
.
C
h
a
r
a
c
t
e
r
i
s
t
i
c
d
a
t
a
a
n
d
o
t
h
e
r
41
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
T M S3 2 0 VC5 410
F I X ED ĆPOI N T DI G I TAL S I GN AL PRO CE SSO R
SPRS075D – OCTOBER 1998 – REVISED MAY 2000
external multiply-by-N clock option
An external frequency source can be used by applying an input clock to X2/CLKIN with X1 left unconnected.
Figure 14 shows the configuration options for the CLKMD pins that generate the external divide-by-2 clock
option. Following reset, the software PLL can be programmed for the desired multiplication factor. Refer to the
TMS320C54x DSP CPU and Peripherals Reference Set, Volume 1 (literature number SPRU131) for detailed
information on programming the PLL. The external input clock frequency is multiplied by the multiplication factor
N to generate the internal CPU machine cycle.
The external frequency injected must conform to specifications listed in the timing requirements table.
switching characteristics over recommended operating conditions [H = 0.5t
(see Figure 16 and the recommended operating conditions table)
]
c(CO)
’VC5410-100
PARAMETER
’VC5410-120
TYP
UNIT
MIN
10
3
TYP
MAX
MIN
8.33
3
MAX
†
†
t
Cycle time, CLKOUT
t
t
c(CI)/N
ns
ns
ns
ns
ns
ns
ms
c(CO)
c(CI)/N
t
Delay time, X2/CLKIN high/low to CLKOUT high/low
Fall time, CLKOUT
6
10
6
10
d(CI-CO)
t
2
2
2
2
f(CO)
r(CO)
w(COL)
w(COH)
p
t
t
t
t
Rise time, CLKOUT
Pulse duration, CLKOUT low
Pulse duration, CLKOUT high
Transitory phase, PLL lock-up time
H–2
H–2
H–1
H–1
H
H
H–2
H–2
H–1
H–1
H
H
35
35
†
N is the multiplication factor.
†
timing requirements (see Figure 16)
’VC5410-100
MIN MAX
’VC5410-120
MIN MAX
UNIT
Integer PLL multiplier N (N = 1–15)
PLL multiplier N = x.5
10N 400N 8.33N 400N
10N 200N 8.33N 200N
10N 100N 8.33N 100N
t
Cycle time, X2/CLKIN
ns
c(CI)
PLL multiplier N = x.25, x.75
t
t
t
t
Fall time, X2/CLKIN
4
4
4
4
ns
ns
ns
ns
f(CI)
Rise time, X2/CLKIN
r(CI)
Pulse duration, X2/CLKIN low
Pulse duration, X2/CLKIN high
2
2
2
2
w(CIL)
w(CIH)
†
N is the multiplication factor.
t
w(CIL)
t
t
w(CIH)
f(CI)
t
t
r(CI)
c(CI)
X2/CLKIN
t
d(CI–CO)
t
f(CO)
t
w(COH)
t
c(CO)
t
w(COL)
t
t
r(CO)
p
Unstable
CLKOUT
NOTE A: The CLKOUT timing in this diagram assumes the CLKOUT divide factor (DIVFCT field in the BSCR) is configured as 00 (CLKOUT not
divided). DIVFCT is configured as CLKOUT divided-by-4 mode following reset.
Figure 16. External Multiply-by-One Clock Timing
P ROD UCT PR EV IEW in f or m a ti on co nce r ns pr od uct s in th e fo rm at iv e or
da ta
d e s i g n
ph a s e
o
f
d
e
v
e
l
o
p
m
e
n
t
.
C
h
a
r
a
c
t
e
r
i
s
t
i
c
a
n
d
o
t
h
e
r
s p e c i fi ca t i ons a r e de s i gn go a ls . Tex a s Ins tr um ent s r es er v es th e r igh t to
c h a n g e or di s c on ti nue t he s e pr od uct s w ith out not ice .
42
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
T MS 3 20 VC 54 10
F IX EDĆPO I NT DI GI TAL SI G NAL P RO C ES S O R
SPRS075D – OCTOBER 1998 – REVISED MAY 2000
memory and parallel I/O interface timing
memory read
External memory reads can be performed in consecutive or nonconsecutive mode under control of the
CONSEC bit in the BSCR.
†
switching characteristics over recommended operating conditions (MSTRB = 0) (see Figure 17
and Figure 18)
’VC5410-100
’VC5410-120
PARAMETER
UNIT
MIN
– 1
– 1
– 1
MAX
MIN
– 1
– 1
– 1
MAX
t
Delay time, CLKOUT low to address valid
Delay time, CLKOUT low to MSTRB low
Delay time, CLKOUT low to MSTRB high
4
4
4
6
6
6
ns
ns
ns
d(CLKL-A)
t
d(CLKL-MSL)
t
d(CLKL-MSH)
†
Address,R/W, PS, DS, and IS timings are all included in timings referenced as address.
†
timing requirements (MSTRB = 0) [H = 0.5 t
] (see Figure 17 and Figure 18)
c(CO)
’VC5410-100
’VC5410-120
UNIT
ns
MIN
MAX
MIN
MAX
t
t
Access time, read data access from address valid, first read access
4H–10
4H–10
a(A)M1
Access time, read data access from address valid, consecutive read
accesses
2H–10
2H–10
ns
a(A)M2
t
t
Setup time, read data valid before CLKOUT low
Hold time, read data valid after CLKOUT low
6
0
6
0
ns
ns
su(D)R
h(D)R
†
Address,R/W, PS, DS, and IS timings are all included in timings referenced as address.
PR O DU C T PR EVI EW inf or ma tio n co nce r ns pr od uct s in th e fo rm at iv e o r
de s i gn ph a s e of de ve lopm ent . C ha ra ct er is tic da ta an d o the r
s pe c i fi c a t io ns a r e de s ig n goa ls . Tex as Ins tr um ent s r es er v es th e r i gh t to
c ha n ge or di s c on ti nu e th es e pr od uct s w ith out not ice .
43
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
T M S3 2 0 VC5 410
E
F
I
X
D
Ć
P
O
I
N
T
D
I
G
I
TA
L
S
I
GN
A
L
PRO CE SSO R
SPRS075D – OCTOBER 1998 – REVISED MAY 2000
memory and parallel I/O interface timing (continued)
CLKOUT
t
d(CLKL-A)
A[22:0]
t
d(CLKL-MSL)
t
d(CLKL-MSH)
t
a(A)M1
D[15:0]
t
su(D)R
t
h(D)R
MSTRB
R/W
PS/DS
Figure 17. Nonconsecutive Mode Memory Reads
44
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
T MS 3 20 VC 54 10
A
F
I
X
E
D
Ć
P
O
I
N
T
D
I
GI
TA
L
S
I
G
N
L
P RO C ES S O R
SPRS075D – OCTOBER 1998 – REVISED MAY 2000
memory and parallel I/O interface timing (continued)
CLKOUT
t
d(CLKL-A)
t
d(CLKL-MSL)
t
d(CLKL-MSH)
A[22:0]
D[15:0]
t
a(A)M1
t
a(A)M2
t
t
su(D)R
su(D)R
t
t
h(D)R
h(D)R
MSTRB
R/W
PS/DS
Figure 18. Consecutive Mode Memory Reads
45
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
T M S3 2 0 VC5 410
F I X ED ĆPOI N T DI G I TAL S I GN AL PRO CE SSO R
SPRS075D – OCTOBER 1998 – REVISED MAY 2000
memory and parallel I/O interface timing (continued)
memory write
†
switching characteristics over recommended operating conditions (MSTRB = 0) [H = 0.5 t
(see Figure 19)
]
c(CO)
’VC5410-100
’VC5410-120
PARAMETER
UNIT
MIN
– 1
MAX
MIN
– 1
MAX
t
Delay time, CLKOUT low to address valid
Setup time, address valid before MSTRB low
Delay time, CLKOUT low to data valid
Setup time, data valid before MSTRB high
Hold time, data valid after MSTRB high
Delay time, CLKOUT low to MSTRB low
Pulse duration, MSTRB low
4
6
ns
ns
ns
ns
ns
ns
ns
ns
d(CLKL-A)
t
2H – 5
0
2H – 5
0
su(A)MSL
t
5
7
d(CLKL-D)W
t
2H – 5
2H – 5
– 1
2H + 5 2H – 5
2H + 5 2H – 5
su(D)MSH
t
h(D)MSH
t
4
– 1
2H – 5
– 1
6
6
d(CLKL-MSL)
t
2H – 5
– 1
w(SL)MS
t
Delay time, CLKOUT low to MSTRB high
4
d(CLKL-MSH)
†
Address, R/W, PS, DS, and IS timings are all included in timings referenced as address.
CLKOUT
t
d(CLKL-A)
t
d(CLKL-D)W
t
su(A)MSL
A[22:0]
D[15:0]
t
su(D)MSH
t
h(D)MSH
t
d(CLKL-MSL)
t
d(CLKL-MSH)
t
w(SL)MS
MSTRB
R/W
PS/DS
Figure 19. Memory Write (MSTRB = 0)
P ROD UCT PR EV IEW in f or m a ti on co nce r ns pr od uct s in th e fo rm at iv e or
d e s i g n ph a s e of de v e l op me nt. C ha ra ct er is tic da ta an d ot her
s p e c i fi ca t i ons a r e de s i gn go a ls . Tex a s Ins tr um ent s r es er v es th e r igh t to
c h a n g e or di s c on ti nue t he s e pr od uct s w ith out not ice .
46
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
T MS 3 20 VC 54 10
F IX EDĆPO I NT DI GI TAL SI G NAL P RO C ES S O R
SPRS075D – OCTOBER 1998 – REVISED MAY 2000
memory and parallel I/O interface timing (continued)
I/O read
†
switching characteristics over recommended operating conditions (IOSTRB = 0) (see Figure 20)
’VC5410-100
’VC5410-120
PARAMETER
UNIT
MIN
– 1
– 1
– 1
MAX
MIN
– 1
– 1
– 1
MAX
t
Delay time, CLKOUT low to address valid
Delay time, CLKOUT low to IOSTRB low
Delay time, CLKOUT low to IOSTRB high
4
4
4
6
6
6
ns
ns
ns
d(CLKL-A)
t
d(CLKL-IOSL)
t
d(CLKL-IOSH)
†
Address R/W, PS, DS, and IS timings are included in timings referenced as address.
†
timing requirements for a parallel I/O port read (IOSTRB = 0) [H = 0.5 t
] (see Figure 20)
c(CO)
’VC5410-100
’VC5410-120
UNIT
MIN
MAX
MIN
MAX
t
t
t
Access time, read data access from address valid, first read access
Setup time, read data valid before CLKOUT low
4H–10
4H–10
ns
ns
ns
a(A)M1
su(D)R
h(D)R
6
0
6
0
Hold time, read data valid after CLKOUT low
†
Address R/W, PS, DS, and IS timings are included in timings referenced as address.
PR O DU C T PR EVI EW inf or ma tio n co nce r ns pr od uct s in th e fo rm at iv e o r
de s i gn ph a s e of de ve lopm ent . C ha ra ct er is tic da ta an d o the r
s pe c i fi c a t io ns a r e de s ig n goa ls . Tex as Ins tr um ent s r es er v es th e r i gh t to
c ha n ge or di s c on ti nu e th es e pr od uct s w ith out not ice .
47
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
T M S3 2 0 VC5 410
E
F
I
X
D
Ć
P
O
I
N
T
D
I
G
I
TA
L
S
I
GN
A
L
P
R
O
C
E
S
S
O
R
SPRS075D – OCTOBER 1998 – REVISED MAY 2000
memory and parallel I/O interface timing (continued)
CLKOUT
t
d(CLKL-A)
t
d(CLKL-IOSL)
t
d(CLKL-IOSH)
A[22:0]
t
a(A)M1
t
su(D)R
t
h(D)R
D[15:0]
IOSTRB
R/W
IS
Figure 20. Parallel I/O Port Read (IOSTRB = 0)
48
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
T MS 3 20 VC 54 10
F IX EDĆPO I NT DI GI TAL SI G NAL P RO C ES S O R
SPRS075D – OCTOBER 1998 – REVISED MAY 2000
memory and parallel I/O interface timing (continued)
I/O write
switching characteristics over recommended operating conditions (IOSTRB = 0) [H = 0.5 t
(see Figure 21)
]
c(CO)
†
’VC5410-100
’VC5410-120
PARAMETER
UNIT
MIN
– 1
MAX
MIN
– 1
MAX
t
Delay time, CLKOUT low to address valid
Setup time, address valid before IOSTRB low
Delay time, CLKOUT low to write data valid
Setup time, data valid before IOSTRB high
Hold time, data valid after IOSTRB high
Delay time, CLKOUT low to IOSTRB low
Pulse duration, IOSTRB low
4
6
ns
ns
ns
ns
ns
ns
ns
ns
d(CLKL-A)
t
2H – 5
0
2H – 5
0
su(A)IOSL
t
5
7
d(CLKL-D)W
t
2H – 5 2H + 5
2H – 5 2H + 5
2H – 5 2H + 5
2H – 5 2H + 5
su(D)IOSH
t
h(D)IOSH
t
t
t
– 1
2H – 5
– 1
4
– 1
2H – 5
– 1
6
d(CLKL-IOSL)
w(SL)IOS
Delay time, CLKOUT low to IOSTRB high
4
6
d(CLKL-IOSH)
†
Address R/W, PS, DS, and IS timings are included in timings referenced as address.
PR O DU C T PR EVI EW inf or ma tio n co nce r ns pr od uct s in th e fo rm at iv e o r
de s i gn ph a s e of de ve lopm ent . C ha ra ct er is tic da ta an d o the r
s pe c i fi c a t io ns a r e de s ig n goa ls . Tex as Ins tr um ent s r es er v es th e r i gh t to
c ha n ge or di s c on ti nu e th es e pr od uct s w ith out not ice .
49
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
T M S3 2 0 VC5 410
E
F
I
X
D
Ć
P
O
I
N
T
D
I
G
I
TA
L
S
I
GN
A
L
P
R
O
C
E
S
S
O
R
SPRS075D – OCTOBER 1998 – REVISED MAY 2000
memory and parallel I/O interface timing (continued)
CLKOUT
t
d(CLKL-A)
A[22:0]
D[15:0]
t
d(CLKL-D)W
t
d(CLKL-D)W
t
su(A)IOSL
t
su(D)IOSH
t
h(D)IOSH
IOSTRB
R/W
IS
Figure 21. Parallel I/O Port Write (IOSTRB = 0)
50
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
T MS 3 20 VC 54 10
F IX EDĆPO I NT DI GI TAL SI G NAL P RO C ES S O R
SPRS075D – OCTOBER 1998 – REVISED MAY 2000
ready timing for externally generated wait states
†‡
switching characteristics over recommended operating conditions (see Figure 22, Figure 23,
Figure 24, and Figure 25)
’VC5410-100
’VC5410-120
PARAMETER
UNIT
MIN
– 1
MAX
MIN
– 1
MAX
t
Delay time, CLKOUT low to MSC low
Delay time, CLKOUT low to MSC high
4
4
6
6
ns
ns
d(MSCL)
t
– 1
– 1
d(MSCH)
†
The hardware wait states can be used only in conjunction with the software wait states to extend the bus cycles. To generate wait states by
READY, at least two software wait states must be programmed. READY is not sampled until the completion of the internal software wait states.
These timings are included for reference only. The critical timings for READY are those referenced to CLKOUT.
‡
†
timing requirements for externally generated wait states [H = 0.5 t
Figure 24, and Figure 25)
] (see Figure 22, Figure 23,
c(CO)
’VC5410-100
’VC5410-120
UNIT
MIN
MAX
MIN
5
MAX
t
t
t
t
t
t
Setup time, READY before CLKOUT low
Hold time, READY after CLKOUT low
5
0
ns
ns
ns
ns
ns
ns
su(RDY)
0
h(RDY)
‡
Valid time, READY after MSTRB low
4H–8
4H–8
4H–8
4H–8
v(RDY)MSTRB
h(RDY)MSTRB
v(RDY)IOSTRB
h(RDY)IOSTRB
‡
Hold time, READY after MSTRB low
4H
4H
‡
Valid time, READY after IOSTRB low
‡
Hold time, READY after IOSTRB low
4H
4H
†
The hardware wait states can be used only in conjunction with the software wait states to extend the bus cycles. To generate wait states by
READY, at least two software wait states must be programmed. READY is not sampled until the completion of the internal software wait states.
These timings are included for reference only. The critical timings for READY are those referenced to CLKOUT.
‡
PR O DU C T PR EVI EW inf or ma tio n co nce r ns pr od uct s in th e fo rm at iv e o r
de s i gn ph a s e of de ve lopm ent . C ha ra ct er is tic da ta an d o the r
s pe c i fi c a t io ns a r e de s ig n goa ls . Tex as Ins tr um ent s r es er v es th e r i gh t to
c ha n ge or di s c on ti nu e th es e pr od uct s w ith out not ice .
51
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
T M S3 2 0 VC5 410
E
F
I
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D
Ć
P
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I
N
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D
I
G
I
T
A
L
S
I
GN
A
L
PRO CE SSO R
SPRS075D – OCTOBER 1998 – REVISED MAY 2000
ready timing for externally generated wait states (continued)
CLKOUT
A[22:0]
t
su(RDY)
t
h(RDY)
READY
MSTRB
MSC
t
v(RDY)MSTRB
t
h(RDY)MSTRB
t
d(MSCL)
t
d(MSCH)
Leading
Cycle
Wait States
Generated
Internally
Wait
States
Generated
by READY
Trailing
Cycle
Figure 22. Memory Read With Externally Generated Wait States
52
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T MS 3 20 VC 54 10
A
F
I
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E
D
Ć
P
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I
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I
GI
TA
L
S
I
G
N
L
P RO C ES S O R
SPRS075D – OCTOBER 1998 – REVISED MAY 2000
ready timing for externally generated wait states (continued)
CLKOUT
A[22:0]
D[15:0]
t
h(RDY)
t
su(RDY)
READY
MSTRB
MSC
t
v(RDY)MSTRB
t
h(RDY)MSTRB
t
d(MSCL)
t
d(MSCH)
Wait States
Generated Internally
Wait State Generated
by READY
Figure 23. Memory Write With Externally Generated Wait States
53
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
T M S3 2 0 VC5 410
E
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P
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I
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I
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S
I
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A
L
PRO CE SSO R
SPRS075D – OCTOBER 1998 – REVISED MAY 2000
ready timing for externally generated wait states (continued)
CLKOUT
A[22:0]
t
su(RDY)
t
h(RDY)
READY
IOSTRB
MSC
t
v(RDY)IOSTRB
t
h(RDY)IOSTRB
t
d(MSCL)
t
d(MSCH)
Leading
Cycle
Wait States
Generated
Internally
Wait
States
Generated
by READY
Trailing
Cycle
Figure 24. I/O Read With Externally Generated Wait States
54
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
T MS 3 20 VC 54 10
A
F
I
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E
D
Ć
P
O
I
N
T
D
I
GI
TA
L
S
I
G
N
L
P
R
O
C
E
S
S
O
R
SPRS075D – OCTOBER 1998 – REVISED MAY 2000
ready timing for externally generated wait states (continued)
CLKOUT
A[22:0]
D[15:0]
t
su(RDY)
t
h(RDY)
READY
IOSTRB
MSC
t
v(RDY)IOSTRB
t
h(RDY)IOSTRB
t
d(MSCL)
t
d(MSCH)
Leading
Cycle
Wait
States
Wait
States
Generated
by READY
Generated
Internally
Trailing
Cycle
Figure 25. I/O Write With Externally Generated Wait States
55
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
T M S3 2 0 VC5 410
F I X ED ĆPOI N T DI G I TAL S I GN AL PRO CE SSO R
SPRS075D – OCTOBER 1998 – REVISED MAY 2000
HOLD and HOLDA timings
switching characteristics over recommended operating conditions for memory control signals
and HOLDA [H = 0.5 t
] (see Figure 26)
c(CO)
’VC5410-100
’VC5410-120
PARAMETER
UNIT
MIN
MAX
5
MIN
MAX
5
t
t
t
t
t
t
Disable time, Address, PS, DS, IS high impedance from CLKOUT low
Disable time, R/W high impedance from CLKOUT low
Disable time, MSTRB, IOSTRB high impedance from CLKOUT low
Enable time, Address, PS, DS, IS valid from CLKOUT low
Enable time, R/W enabled from CLKOUT low
ns
ns
ns
ns
ns
ns
dis(CLKL-A)
dis(CLKL-RW)
dis(CLKL-S)
en(CLKL-A)
en(CLKL-RW)
en(CLKL-S)
5
5
5
5
2H+5
2H+5
2H+5
2H+5
2H+5
2H+5
Enable time, MSTRB, IOSTRB enabled from CLKOUT low
– 1
– 1
4
4
– 1
– 1
4
4
ns
ns
ns
Valid time, HOLDA low after CLKOUT low
t
t
v(HOLDA)
Valid time, HOLDA high after CLKOUT low
Pulse duration, HOLDA low duration
2H–3
2H–3
w(HOLDA)
timing requirements for HOLD [H = 0.5 t
] (see Figure 26)
c(CO)
’VC5410-100
’VC5410-120
UNIT
MAX
4H+10
9
MIN
MAX
4H+10
9
MIN
t
t
Pulse duration, HOLD low duration
Setup time, HOLD before CLKOUT low
ns
ns
w(HOLD)
su(HOLD)
P ROD UCT PR EV IEW in f or m a ti on co nce r ns pr od uct s in th e fo rm at iv e or
d e s i g n ph a s e of de v e l op me nt. C ha ra ct er is tic da ta an d ot her
s p e c i fi ca t i ons a r e de s i gn go a ls . Tex a s Ins tr um ent s r es er v es th e r igh t to
c h a n g e or di s c on ti nue t he s e pr od uct s w ith out not ice .
56
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
T MS 3 20 VC 54 10
A
F
I
X
E
D
Ć
P
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I
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T
D
I
G
I
TA
L
S
I
G
N
L
P RO C ES S O R
SPRS075D – OCTOBER 1998 – REVISED MAY 2000
HOLD and HOLDA timings (continued)
CLKOUT
t
t
su(HOLD)
su(HOLD)
t
w(HOLD)
HOLD
t
t
v(HOLDA)
v(HOLDA)
t
w(HOLDA)
HOLDA
t
t
en(CLKL–A)
dis(CLKL–A)
A[22:0]
PS, DS, IS
D[15:0]
R/W
t
t
t
t
dis(CLKL–RW)
dis(CLKL–S)
dis(CLKL–S)
en(CLKL–RW)
t
en(CLKL–S)
MSTRB
IOSTRB
t
en(CLKL–S)
Figure 26. HOLD and HOLDA Timings (HM = 1)
57
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
T M S3 2 0 VC5 410
F I X ED ĆPOI N T DI G I TAL S I GN AL PRO CE SSO R
SPRS075D – OCTOBER 1998 – REVISED MAY 2000
reset, BIO, interrupt, and MP/MC timings
timing requirements for reset, BIO, interrupt, and MP/MC [H = 0.5 t
and Figure 29)
] (see Figure 27, Figure 28,
c(CO)
’VC5410-100
’VC5410-120
UNIT
MIN
MAX
MIN
0
MAX
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Hold time, RS after CLKOUT low
Hold time, BIO after CLKOUT low
Hold time, INTn, NMI, after CLKOUT low
Hold time, MP/MC after CLKOUT low
0
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
h(RS)
0
h(BIO)
†
0
0
h(INT)
0
0
h(MPMC)
w(RSL)
‡§
Pulse duration, RS low
4H+5
2H+5
4H
2H+7
4H
2H+7
4H
8
4H+5
2H+5
4H
2H+7
4H
2H+7
4H
8
Pulse duration, BIO low, synchronous
Pulse duration, BIO low, asynchronous
w(BIO)S
w(BIO)A
w(INTH)S
w(INTH)A
w(INTL)S
w(INTL)A
w(INTL)WKP
su(RS)
Pulse duration, INTn, NMI high (synchronous)
Pulse duration, INTn, NMI high (asynchronous)
Pulse duration, INTn, NMI low (synchronous)
Pulse duration, INTn, NMI low (asynchronous)
Pulse duration, INTn, NMI low for IDLE2/IDLE3 wakeup
¶
Setup time, RS before X2/CLKIN low
5
5
Setup time, BIO before CLKOUT low
8
12
13
8
12
12
su(BIO)
Setup time, INTn, NMI, RS before CLKOUT low
Setup time, MP/MC before CLKOUT low
9
8
su(INT)
8
8
su(MPMC)
†
The external interrupts (INT0–INT3, NMI) are synchronized to the core CPU by way of a two-flip-flop synchronizer that samples these inputs
with consecutive falling edges of CLKOUT. The input to the interrupt pins is required to represent a 1–0–0 sequence at the timing that is
corresponding to three CLKOUTs sampling sequence.
If the PLL mode is selected, then at power-on sequence, or at wakeup from IDLE3, RS must be held low for at least 50 µs to ensure
synchronization and lock-in of the PLL.
‡
§
¶
Note that RS may cause a change in clock frequency, therefore changing the value of H.
The diagram assumes clock mode is divide-by-2 and the CLKOUT divide factor is set to no-divide mode (DIVFCT=00 field in the BSCR).
P ROD UCT PR EV IEW in f or m a ti on co nce r ns pr od uct s in th e fo rm at iv e or
d e s i g n ph a s e of de v e l op me nt. C ha ra ct er is tic da ta an d ot her
s p e c i fi ca t i ons a r e de s i gn go a ls . Tex a s Ins tr um ent s r es er v es th e r igh t to
c h a n g e or di s c on ti nue t he s e pr od uct s w ith out not ice .
58
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
T MS 3 20 VC 54 10
A
F
I
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E
D
Ć
P
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I
N
T
D
I
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T
A
L
S
I
G
N
L
P RO C ES S O R
SPRS075D – OCTOBER 1998 – REVISED MAY 2000
reset, BIO, interrupt, and MP/MC timings (continued)
X2/CLKIN
t
su(RS)
t
w(RSL)
RS, INTn, NMI
t
su(INT)
t
h(RS)
CLKOUT
t
su(BIO)
t
h(BIO)
BIO
t
w(BIO)S
Figure 27. Reset and BIO Timings
CLKOUT
t
t
t
su(INT)
su(INT)
h(INT)
INTn, NMI
t
w(INTH)A
t
w(INTL)A
Figure 28. Interrupt Timing
CLKOUT
RS
t
h(MPMC)
t
su(MPMC)
MP/MC
Figure 29. MP/MC Timing
59
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
T M S3 2 0 VC5 410
F I X ED ĆPOI N T DI G I TAL S I GN AL PRO CE SSO R
SPRS075D – OCTOBER 1998 – REVISED MAY 2000
instruction acquisition (IAQ), interrupt acknowledge (IACK), external flag (XF), and TOUT timings
switching characteristics over recommended operating conditions for IAQ and IACK
[H = 0.5 t
] (see Figure 30)
c(CO)
’VC5410-100
’VC5410-120
PARAMETER
UNIT
MIN
– 1
MAX
MIN
– 1
MAX
t
Delay time, CLKOUT low to IAQ low
Delay time, CLKOUT low to IAQ high
Delay time, IAQ low to address valid
Delay time, CLKOUT low to IACK low
Delay time, CLKOUT low to IACK high
Delay time, IACK low to address valid
Hold time, address valid after IAQ high
Hold time, address valid after IACK high
Pulse duration, IAQ low
4
4
3
4
4
3
7
7
4
6
6
3
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
d(CLKL-IAQL)
t
t
– 1
– 1
d(CLKL-IAQH)
d(A)IAQ
t
– 1
– 1
– 1
– 1
d(CLKL-IACKL)
t
d(CLKL-IACKH)
d(A)IACK
h(A)IAQ
t
t
t
t
t
– 3
– 3
– 6
– 6
h(A)IACK
w(IAQL)
2H–3
2H–3
2H–6
2H–6
Pulse duration, IACK low
w(IACKL)
CLKOUT
A[22:0]
IAQ
t
t
d(CLKL–IAQH)
d(CLKL–IAQL)
t
h(A)IAQ
t
d(A)IAQ
t
w(IAQL)
t
t
d(CLKL–IACKH)
d(CLKL–IACKL)
t
h(A)IACK
t
d(A)IACK
t
w(IACKL)
IACK
Figure 30. Instruction Acquisition (IAQ) and Interrupt Acknowledge (IACK) Timings
P ROD UCT PR EV IEW in f or m a ti on co nce r ns pr od uct s in th e fo rm at iv e or
d e s i g n ph a s e of de v e l op me nt. C ha ra ct er is tic da ta an d ot her
s p e c i fi ca t i ons a r e de s i gn go a ls . Tex a s Ins tr um ent s r es er v es th e r igh t to
c h a n g e or di s c on ti nue t he s e pr od uct s w ith out not ice .
60
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
T MS 3 20 VC 54 10
F IX EDĆPO I NT DI GI TAL SI G NAL P RO C ES S O R
SPRS075D – OCTOBER 1998 – REVISED MAY 2000
instruction acquisition (IAQ), interrupt acknowledge (IACK), external flag (XF), and TOUT timings
(continued)
switching characteristics over recommended operating conditions for XF and TOUT
[H = 0.5 t
] (see Figure 31 and Figure 32)
c(CO)
’VC5410-100
’VC5410-120
PARAMETER
UNIT
MIN
–1
MAX
MIN
–1
MAX
Delay time, CLKOUT low to XF high
Delay time, CLKOUT low to XF low
Delay time, CLKOUT low to TOUT high
Delay time, CLKOUT low to TOUT low
Pulse duration, TOUT
4
4
4
4
6
6
6
6
t
ns
d(XF)
–1
–1
t
t
t
–1
–1
ns
ns
ns
d(TOUTH)
d(TOUTL)
w(TOUT)
–1
–1
2H–10
2H–6
CLKOUT
t
d(XF)
XF
Figure 31. External Flag (XF) Timing
CLKOUT
TOUT
t
t
d(TOUTL)
d(TOUTH)
t
w(TOUT)
Figure 32. TOUT Timing
PR O DU C T PR EVI EW inf or ma tio n co nce r ns pr od uct s in th e fo rm at iv e o r
de s i gn ph a s e of de ve lopm ent . C ha ra ct er is tic da ta an d o the r
s pe c i fi c a t io ns a r e de s ig n goa ls . Tex as Ins tr um ent s r es er v es th e r i gh t to
c ha n ge or di s c on ti nu e th es e pr od uct s w ith out not ice .
61
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
T M S3 2 0 VC5 410
F I X ED ĆPOI N T DI G I TAL S I GN AL PRO CE SSO R
SPRS075D – OCTOBER 1998 – REVISED MAY 2000
multichannel buffered serial port timing
†
timing requirements for McBSP [H=0.5t
] (see Figure 33 and Figure 34)
c(CO)
’VC5410-100
’VC5410-120
UNIT
MIN
4H
2H–1
13
4
MAX
MIN
4H
2H–1
13
4
MAX
t
t
Cycle time, BCLKR/X
BCLKR/X ext
BCLKR/X ext
BCLKR int
BCLKR ext
BCLKR int
BCLKR ext
BCLKR int
BCLKR ext
BCLKR int
BCLKR ext
BCLKX int
BCLKX ext
BCLKX int
BCLKX ext
BCLKR/X ext
BCLKR/X ext
ns
ns
c(BCKRX)
Pulse duration, BCLKR/X high or BCLKR/X low
w(BCKRX)
t
t
t
t
t
t
Setup time, external BFSR high before BCLKR low
ns
ns
ns
ns
ns
ns
su(BFRH-BCKRL)
h(BCKRL-BFRH)
su(BDRV-BCKRL)
h(BCKRL-BDRV)
su(BFXH-BCKXL)
h(BCKXL-BFXH)
0
0
Hold time, external BFSR high after BCLKR low
Setup time, BDR valid before BCLKR low
Hold time, BDR valid after BCLKR low
4
4
13
3
13
3
0
0
5
5
13
5
13
5
Setup time, external BFSX high before BCLKX low
Hold time, external BFSX high after BCLKX low
0
0
4
4
t
t
Rise time, BCLKR/X
Fall time, BCLKR/X
8
8
8
8
ns
ns
r(BCKRX)
f(BCKRX)
†
CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that signal are also inverted.
†
switching characteristics for McBSP [H=0.5t
] (see Figure 33 and Figure 34)
c(CO)
’VC5410-100
’VC5410-120
PARAMETER
UNIT
MIN
MAX
MIN
MAX
t
t
Cycle time, BCLKR/X
BCLKR/X int
BCLKR/X int
4H
4H
ns
ns
c(BCKRX)
‡
‡
‡
2
‡
‡
‡
2
Pulse duration, BCLKR/X high
D – 2
C – 2
D
C
D – 2
C – 2
D
C
w(BCKRXH)
‡
‡
t
Pulse duration, BCLKR/X low
BCLKR/X int
BCLKR int
BCLKR ext
BCLKX int
BCLKX ext
BCLKX int
BCLKX ext
BCLKX int
BCLKX ext
ns
ns
ns
w(BCKRXL)
– 4
1
– 4
1
t
Delay time, BCLKR high to internal BFSR valid
Delay time, BCLKX high to internal BFSX valid
d(BCKRH-BFRV)
13
2
13
2
– 4
1
– 4
1
t
ns
ns
ns
d(BCKXH-BFXV)
13
5
13
5
– 3
1
– 3
1
Disable time, BCLKX high to BDX high impedance
following last data bit of transfer
t
dis(BCKXH-BDXHZ)
19
6
19
6
§
3
§
§
3
§
0
0
Delay time, BCLKX high to BDX valid
t
d(BCKXH-BDXV)
d(BFXH-BDXV)
15
15
Delay time, BFSX high to BDX valid
BFSX int
BFSX ext
0
8
0
8
t
ns
ONLY applies when in data delay 0 (XDATDLY =
00b) mode
0
10
0
10
†
‡
CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that signal are also inverted.
T = BCLKRX period = (1 + CLKGDV) * 2H
C = BCLKRX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * 2H when CLKGDV is even
D = BCLKRX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) * 2H when CLKGDV is even
Minimum delay times also represent minimum output hold times.
§
P ROD UCT PR EV IEW in f or m a ti on co nce r ns pr od uct s in th e fo rm at iv e or
d e s i g n ph a s e of de v e l op me nt. C ha ra ct er is tic da ta an d ot her
s p e c i fi ca t i ons a r e de s i gn go a ls . Tex a s Ins tr um ent s r es er v es th e r igh t to
c h a n g e or di s c on ti nue t he s e pr od uct s w ith out not ice .
62
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
T MS 3 20 VC 54 10
A
F
I
X
E
D
Ć
P
O
I
N
T
D
I
GI
T
A
L
S
I
G
N
L
P RO C ES S O R
SPRS075D – OCTOBER 1998 – REVISED MAY 2000
multichannel buffered serial port timing (continued)
t
c(BCKRX)
t
w(BCKRXH)
w(BCKRXL)
t
t
r(BCKRX)
f(BCKRX)
t
BCLKR
BFSR (int)
BFSR (ext)
BDR
t
d(BCKRH-BFRV)
t
d(BCKRH-BFRV)
t
su(BFRH-BCKRL)
t
h(BCKRL-BFRH)
t
su(BDRV-BCKRL)
t
h(BCKRL-BDRV)
(n-2)
(n-3)
Bit(n-1)
Figure 33. McBSP Receive Timings
t
c(BCKRX)
t
t
w(BCKRXH)
t
t
f(BCKRX)
r(BCKRX)
w(BCKRXL)
BCLKX
t
d(BCKXH-BFXV)
BFSX (int)
t
h(BCKXL-BFXH)
t
su(BFXH-BCKXL)
BFSX (ext)
BFSX
(XDATDLY=00b)
t
d(BCKXH-BDXV)
t
d(BFXH-BDXV)
t
t
dis(BCKXH-BDXHZ)
d(BCKXH-BDXV)
BDX
Bit 0
Bit(n-1)
(n-2)
(n-3)
Figure 34. McBSP Transmit Timings
63
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
T M S3 2 0 VC5 410
F I X ED ĆPOI N T DI G I TAL S I GN AL PRO CE SSO R
SPRS075D – OCTOBER 1998 – REVISED MAY 2000
multichannel buffered serial port timing (continued)
timing requirements for McBSP general-purpose I/O (see Figure 35)
’VC5410-100
’VC5410-120
UNIT
MIN
9
MAX
MIN
8
MAX
†
t
t
Setup time, BGPIOx input mode before CLKOUT high
ns
ns
su(BGPIO-COH)
†
Hold time, BGPIOx input mode after CLKOUT high
0
0
h(COH-BGPIO)
†
BGPIOx refers to BCLKRx, BFSRx, BDRx, BCLKXx, or BFSXx when configured as a general-purpose input.
switching characteristics for McBSP general-purpose I/O (see Figure 35)
’VC5410-100
’VC5410-120
PARAMETER
UNIT
MIN
MAX
MIN
MAX
‡
t
Delay time, CLKOUT high to BGPIOx output mode
0
5
0
5
ns
d(COH-BGPIO)
‡
BGPIOx refers to BCLKRx, BFSRx, BCLKXx, BFSXx, or BDXx when configured as a general-purpose output.
t
t
su(BGPIO-COH)
d(COH-BGPIO)
CLKOUT
t
h(COH-BGPIO)
BGPIOx Input
†
mode
BGPIOx Output
‡
mode
†
‡
BGPIOx refers to BCLKRx, BFSRx, BDRx, BCLKXx, or BFSXx when configured as a general-purpose input.
BGPIOx refers to BCLKRx, BFSRx, BCLKXx, BFSXx, or BDXx when configured as a general-purpose output.
Figure 35. McBSP General-Purpose I/O Timings
P ROD UCT PR EV IEW in f or m a ti on co nce r ns pr od uct s in th e fo rm at iv e or
d e s i g n ph a s e of de v e l op me nt. C ha ra ct er is tic da ta an d ot her
s p e c i fi ca t i ons a r e de s i gn go a ls . Tex a s Ins tr um ent s r es er v es th e r igh t to
c h a n g e or di s c on ti nue t he s e pr od uct s w ith out not ice .
64
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
T MS 3 20 VC 54 10
F IX EDĆPO I NT DI GI TAL SI G NAL P RO C ES S O R
SPRS075D – OCTOBER 1998 – REVISED MAY 2000
multichannel buffered serial port timing (continued)
†
timing requirements for McBSP as SPI master or slave: [H=0.5t
(see Figure 36)
] CLKSTP = 10b, CLKXP = 0
c(CO)
’5410-100
’5410-120
MASTER
SLAVE
MIN MAX
MASTER
SLAVE
MIN MAX
UNIT
MIN
12
0
MAX
MIN
12
0
MAX
Setup time, BDR valid before BCLKX
low
t
7 – 6H
7 – 6H
5 + 6H
ns
ns
su(BDRV-BCKXL)
t
Hold time, BDR valid after BCLKX low
5 + 6H
h(BCKXL-BDRV)
†
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
switching characteristics for McBSP as SPI master or slave: [H=0.5t
] CLKSTP = 10b,
c(CO)
†
CLKXP = 0 (see Figure 36)
’5410-100
’5410-120
‡
‡
MASTER
SLAVE
MIN
MASTER
SLAVE
MIN
PARAMETER
UNIT
MIN MAX
MAX
MIN MAX
MAX
Hold time, BFSX low after
BCLKX low
t
t
t
T – 7 T + 4
C – 7 C + 5
T – 7 T + 4
C – 7 C + 5
ns
ns
ns
h(BCKXL-BFXL)
d(BFXL-BCKXH)
d(BCKXH-BDXV)
§
Delay time, BFSX low to
¶
BCLKX high
Delay time, BCLKX high to
BDX valid
– 3
4
6H + 4 10H + 15
– 3
4
6H + 4 10H + 15
Disable time, BDX high
impedance following last
data bit from BCLKX low
t
C – 2 C + 3
C – 2 C + 3
ns
dis(BCKXL-BDXHZ)
Disable time, BDX high
impedance following last
data bit from BFSX high
t
2H+ 3
6H + 17
8H + 17
2H+ 3
6H + 17
8H + 17
ns
ns
dis(BFXH-BDXHZ)
Delay time, BFSX low to BDX
valid
t
4H + 2
4H + 2
d(BFXL-BDXV)
†
‡
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
T = BCLKX period = (1 + CLKGDV) * 2H
C = BCLKX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * 2H when CLKGDV is even
FSRP = FSXP = 1. As a SPI master, BFSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on BFSX
and BFSR is inverted before being used internally.
§
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
BFSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock
(BCLKX).
¶
PR O DU C T PR EVI EW inf or ma tio n co nce r ns pr od uct s in th e fo rm at iv e o r
de s i gn ph a s e of de ve lopm ent . C ha ra ct er is tic da ta an d o the r
s pe c i fi c a t io ns a r e de s ig n goa ls . Tex as Ins tr um ent s r es er v es th e r i gh t to
c ha n ge or di s c on ti nu e th es e pr od uct s w ith out not ice .
65
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
T M S3 2 0 VC5 410
E
F
I
X
D
Ć
P
O
I
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T
D
I
G
I
TA
L
S
I
GN
A
L
PRO CE SSO R
SPRS075D – OCTOBER 1998 – REVISED MAY 2000
multichannel buffered serial port timing (continued)
MSB
LSB
BCLKX
BFSX
t
h(BCKXL-BFXL)
t
d(BFXL-BCKXH)
t
dis(BFXH-BDXHZ)
t
d(BFXL-BDXV)
t
t
d(BCKXH-BDXV)
(n-2)
dis(BCKXL-BDXHZ)
BDX
BDR
Bit 0
Bit(n-1)
(n-3)
(n-4)
t
su(BDRV-BCLXL)
t
h(BCKXL-BDRV)
Bit 0
Bit(n-1)
(n-2)
(n-3)
(n-4)
Figure 36. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0
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T MS 3 20 VC 54 10
A
F
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E
D
Ć
P
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I
N
T
D
I
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TA
L
S
I
G
N
L
P RO C ES S O R
SPRS075D – OCTOBER 1998 – REVISED MAY 2000
multichannel buffered serial port timing (continued)
†
timing requirements for McBSP as SPI master or slave: [H=0.5t
(see Figure 37)
] CLKSTP = 11b, CLKXP = 0
c(CO)
’5410-100
’5410-120
MASTER
SLAVE
MIN
MASTER
SLAVE
MIN MAX
UNIT
MIN
MAX
MAX
MIN
MAX
Setup time, BDR valid
before BCLKX low
t
t
12
7 – 6H
5 + 6H
12
7 – 6H
5 + 6H
ns
ns
su(BDRV-BCKXL)
Hold time, BDR valid
after BCLKX high
0
0
h(BCKXH-BDRV)
†
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
switching characteristics for McBSP as SPI master or slave: [H=0.5t
CLKXP = 0 (see Figure 37)
] CLKSTP = 11b,
c(CO)
†
’5410-100
’5410-120
‡
‡
MASTER
SLAVE
MIN
MASTER
SLAVE
MIN
PARAMETER
UNIT
MIN MAX
MAX
MIN MAX
MAX
Hold time, BFSX low after
BCLKX low
t
t
t
C – 7 C + 4
T –7 T + 5
C – 7 C + 4
T –7 T + 5
ns
ns
ns
h(BCKXL-BFXL)
d(BFXL-BCKXH)
d(BCKXL-BDXV)
§
Delay time, BFSX low to
¶
BCLKX high
Delay time, BCLKX low to
BDX valid
– 3
–2
4
4
6H + 4 10H + 15
6H + 3 10H + 17
– 3
–2
4
4
6H + 4 10H + 15
6H + 3 10H + 17
Disable time, BDX high
impedance following last
data bit from BCLKX low
t
ns
ns
dis(BCKXL-BDXHZ)
Delay time, BFSX low to
BDX valid
t
D – 3 D + 5
4H + 2
8H + 17 D – 3 D + 5 4H + 2
8H + 17
d(BFXL-BDXV)
†
‡
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
T = BCLKX period = (1 + CLKGDV) * 2H
C = BCLKX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * 2H when CLKGDV is even
D = BCLKX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) * 2H when CLKGDV is even
FSRP = FSXP = 1. As a SPI master, BFSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on BFSX
and BFSR is inverted before being used internally.
§
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
BFSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock
(BCLKX).
¶
67
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
T M S3 2 0 VC5 410
F I X ED ĆPOI N T DI G I TAL S I GN AL PRO CE SSO R
SPRS075D – OCTOBER 1998 – REVISED MAY 2000
multichannel buffered serial port timing (continued)
MSB
LSB
BCLKX
t
t
d(BFXL-BCKXH)
h(BCKXL-BFXL)
BFSX
t
t
t
d(BCKXL-BDXV)
d(BFXL-BDXV)
dis(BCKXL-BDXHZ)
BDX
BDR
Bit 0
Bit(n-1)
Bit(n-1)
(n-2)
(n-3)
(n-4)
t
su(BDRV-BCKXL)
t
h(BCKXH-BDRV)
Bit 0
(n-2)
(n-3)
(n-4)
Figure 37. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0
P ROD UCT PR EV IEW in f or m a ti on co nce r ns pr od uct s in th e fo rm at iv e or
d e s i g n ph a s e of de v e l op me nt. C ha ra ct er is tic da ta an d ot her
s p e c i fi ca t i ons a r e de s i gn go a ls . Tex a s Ins tr um ent s r es er v es th e r igh t to
c h a n g e or di s c on ti nue t he s e pr od uct s w ith out not ice .
68
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
T MS 3 20 VC 54 10
F IX EDĆPO I NT DI GI TAL SI G NAL P RO C ES S O R
SPRS075D – OCTOBER 1998 – REVISED MAY 2000
multichannel buffered serial port timing (continued)
†
timing requirements for McBSP as SPI master or slave: [H=0.5t
(see Figure 38)
] CLKSTP = 10b, CLKXP = 1
c(CO)
’5410-100
’5410-120
MASTER
SLAVE
MIN
MASTER
SLAVE
MIN MAX
UNIT
MIN
MAX
MAX
MIN
MAX
Setup time, BDR valid
before BCLKX high
t
t
12
7 – 6H
5 + 6H
12
7 – 6H
5 + 6H
ns
ns
su(BDRV-BCKXH)
Hold time, BDR valid
after BCLKX high
0
0
h(BCKXH-BDRV)
†
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
switching characteristics for McBSP as SPI master or slave: [H=0.5t
CLKXP = 1 (see Figure 38)
] CLKSTP = 10b,
c(CO)
†‡
’5410-100
’5410-120
SLAVE
MIN MAX
MASTER
SLAVE
MIN
MASTER
MIN MAX
PARAMETER
UNIT
MIN
MAX
MAX
Hold time, BFSX low after
BCLKX high
t
t
t
T – 7 T + 4
T – 7 T + 4
D – 7 D + 5
ns
ns
ns
h(BCKXH-BFXL)
d(BFXL-BCKXL)
d(BCKXL-BDXV)
§
Delay time, BFSX low to
D – 7 D + 5
¶
BCLKX low
Delay time, BCLKX low to
BDX valid
– 3
4
6H + 4 10H + 15
– 3
4
6H + 4 10H + 15
Disable time, BDX high
impedance following last
data bit from BCLKX high
t
D – 2 D + 3
D – 2 D + 3
ns
dis(BCKXH-BDXHZ)
Disable time, BDX high
impedance following last
data bit from BFSX high
t
t
2H + 3
4H + 2
6H + 17
8H + 17
2H + 3
4H + 2
6H + 17
8H + 17
ns
ns
dis(BFXH-BDXHZ)
Delay time, BFSX low to
BDX valid
d(BFXL-BDXV)
†
‡
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
T = BCLKX period = (1 + CLKGDV) * 2H
D = BCLKX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) * 2H when CLKGDV is even
FSRP = FSXP = 1. As a SPI master, BFSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on BFSX
and BFSR is inverted before being used internally.
§
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
BFSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock
(BCLKX).
¶
PR O DU C T PR EVI EW inf or ma tio n co nce r ns pr od uct s in th e fo rm at iv e o r
de s i gn ph a s e of de ve lopm ent . C ha ra ct er is tic da ta an d o the r
s pe c i fi c a t io ns a r e de s ig n goa ls . Tex as Ins tr um ent s r es er v es th e r i gh t to
c ha n ge or di s c on ti nu e th es e pr od uct s w ith out not ice .
69
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
T M S3 2 0 VC5 410
E
F
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D
Ć
P
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I
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T
D
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I
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S
I
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A
L
PRO CE SSO R
SPRS075D – OCTOBER 1998 – REVISED MAY 2000
multichannel buffered serial port timing (continued)
LSB
MSB
BCLKX
t
h(BCKXH-BFXL)
t
d(BFXL-BCKXL)
BFSX
t
t
d(BFXL-BDXV)
dis(BFXH-BDXHZ)
t
t
t
d(BCKXL-BDXV)
dis(BCKXH-BDXHZ)
BDX
BDR
Bit 0
Bit(n-1)
(n-2)
(n-3)
(n-4)
t
su(BDRV-BCKXH)
h(BCKXH-BDRV)
(n-2)
Bit 0
Bit(n-1)
(n-3)
(n-4)
Figure 38. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1
70
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
T MS 3 20 VC 54 10
F IX EDĆPO I NT DI GI TAL SI G NAL P RO C ES S O R
SPRS075D – OCTOBER 1998 – REVISED MAY 2000
multichannel buffered serial port timing (continued)
†
timing requirements for McBSP as SPI master or slave: [H=0.5t
(see Figure 39)
] CLKSTP = 11b, CLKXP = 1
c(CO)
’5410-100
’5410-120
MASTER
SLAVE
MIN MAX
MASTER
SLAVE
MIN MAX
UNIT
MIN
12
0
MAX
MIN
12
0
MAX
Setup time, BDR valid before BCLKX
low
t
t
7 – 6H
7 – 6H
5 + 6H
ns
ns
su(BDRV-BCKXL)
Hold time, BDR valid after BCLKX low
5 + 6H
h(BCKXL-BDRV)
†
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
switching characteristics for McBSP as SPI master or slave: [H=0.5t
CLKXP = 1 (see Figure 39)
] CLKSTP = 11b,
c(CO)
†‡
’5410-100
’5410-120
‡
‡
MASTER
MIN MAX
SLAVE
MIN
MASTER
MIN MAX
SLAVE
MIN
PARAMETER
UNIT
MAX
MAX
Hold time, BFSX low after
BCLKX high
t
t
t
D – 7 D + 4
T – 7 T + 5
D – 7 D + 4
T – 7 T + 5
ns
ns
ns
h(BCKXH-BFXL)
d(BFXL-BCKXL)
d(BCKXH-BDXV)
§
Delay time, BFSX low to
¶
BCLKX low
Delay time, BCLKX high to
BDX valid
– 3
–2
4
4
6H + 4 10H + 15
6H + 3 10H + 17
– 3
–2
4
4
6H + 4 10H + 15
6H + 3 10H + 17
Disable time, BDX high
impedance following last
data bit from BCLKX high
t
ns
ns
dis(BCKXH-BDXHZ)
Delay time, BFSX low to BDX
valid
t
C – 3 C + 5 4H + 2
8H + 17 C – 3 C + 5 4H + 2
8H + 17
d(BFXL-BDXV)
†
‡
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
T = BCLKX period = (1 + CLKGDV) * 2H
C = BCLKX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * 2H when CLKGDV is even
D = BCLKX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) * 2H when CLKGDV is even
FSRP = FSXP = 1. As a SPI master, BFSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on BFSX
and BFSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
§
¶
BFSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock
(BCLKX).
PR O DU C T PR EVI EW inf or ma tio n co nce r ns pr od uct s in th e fo rm at iv e o r
de s i gn ph a s e of de ve lopm ent . C ha ra ct er is tic da ta an d o the r
s pe c i fi c a t io ns a r e de s ig n goa ls . Tex as Ins tr um ent s r es er v es th e r i gh t to
c ha n ge or di s c on ti nu e th es e pr od uct s w ith out not ice .
71
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
T M S3 2 0 VC5 410
E
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D
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P
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I
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D
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I
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L
S
I
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A
L
PRO CE SSO R
SPRS075D – OCTOBER 1998 – REVISED MAY 2000
multichannel buffered serial port timing (continued)
MSB
LSB
BCLKX
t
t
h(BCKXH-BFXL)
d(BFXL-BCKXL)
BFSX
t
t
t
d(BCKXH-BDXV)
(n-2)
dis(BCKXH-BDXHZ)
d(BFXL-BDXV)
BDX
BDR
Bit 0
Bit(n-1)
Bit(n-1)
(n-3)
(n-4)
t
su(BDRV-BCKXL)
t
h(BCKXL-BDRV)
Bit 0
(n-2)
(n-3)
(n-4)
Figure 39. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1
72
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
T MS 3 20 VC 54 10
F IX EDĆPO I NT DI GI TAL SI G NAL P RO C ES S O R
SPRS075D – OCTOBER 1998 – REVISED MAY 2000
HPI8 timing
switching characteristics over recommended operating conditions [H = 0.5 t
†‡§
]
c(CO)
(see Figure 40 Figure 41 and Figure 42)
,
,
’5410-100
MAX
’5410-120
MAX
PARAMETER
UNIT
MIN
MIN
t
Enable time, HD driven from DS low
Case 1a: Memory accesses
when DMAC is active in 16-bit
mode and t < 18H
2
15
2
15
ns
en(DSL-HD)
18H+15 – t
18H+15 – t
w(DSH)
w(DSH)
w(DSH)
w(DSH)
w(DSH)
Case 1b: Memory accesses
when DMAC is active in 16-bit
15
15
mode and t
≥ 18H
w(DSH)
Case 1c: Memory access when
DMAC is active in 32-bit mode
26H+15 – t
26H+15 – t
and t
< 26H
w(DSH)
Delay time, DS low to
HDx valid for first byte
of an HPI read
Case 1d: Memory access when
DMAC is active in 32-bit mode
t
ns
d(DSL-HDV1)
15
15
and t
≥ 26H
w(DSH)
Case 2a: Memory accesses
when DMAC is inactive and
10H+15 – t
15
10H+15 – t
15
w(DSH)
w(DSH)
t
< 10H
w(DSH)
Case 2b: Memory accesses
when DMAC is inactive and
t
≥ 10H
w(DSH)
Case 3: Register accesses
15
15
15
15
Delay time, DS low to HDx valid for second byte of an
HPI read
t
ns
ns
d(DSL-HDV2)
t
Hold time, HDx valid after DS high, for a HPI read
Valid time, HDx valid after HRDY high
1
5
5
8
1
5
5
8
h(DSH-HDV)R
t
v(HYH-HDV)
t
Delay time, DS high to HRDY low (see Note 1)
ns
ns
d(DSH-HYL)
Case 1a: Memory accesses
when DMAC is active in 16-bit
mode
18H+12
18H+12
Case 1b: Memory accesses
when DMAC is active in 32-bit
mode
26H+12
26H+12
ns
ns
Delay time, DS high to
HRDY high
t
d(DSH-HYH)
Case 2: Memory accesses
when DMAC is inactive
10H+12
6H+12
10H+12
6H+12
Case 3: Write accesses to
HPIC register (see Note 2)
5
5
ns
ns
ns
t
Delay time, HCS low/high to HRDY low/high
Delay time, CLKOUT high to HRDY high
Delay time, CLKOUT high to HINT change
d(HCS-HRDY)
t
t
)
10
10
10
10
d(COH-HYH
d(COH-HTX)
†
‡
§
DS refers to the logical OR of HCS, HDS1, and HDS2.
HD refers to any of the HPI data bus pins (HD0, HD1, HD2, etc.). HAD stands for HCNTL0, HCNTL1, and HR/W.
DMAC stands for direct memory access controller (DMAC). The HPI8 shares the internal DMA bus with the DMAC, thus HPI8 access times are
affected by DMAC activity.
NOTES: 1. The HRDY output is always high when the HCS input is high, regardless of DS timings.
2. This timing applies when writing a one to the DSPINT bit or HINT bit of the HPIC register. All other writes to the HPIC occur
asynchronously, and do not cause HRDY to be deasserted.
P
R
O
D
U
C
T
P
R
E
V
I
E
W
i
n
f
o
r
m
a
t
i
o
n
c
o
n
c
e
r
n
s
p
r
o
d
u
c
t
s
i
n
t
h
e
f
o
r
m
a
t
i
v
e
o
r
de s i gn
s pe c i fi c a t io ns a r e de s ig n goa ls . Tex as Ins tr um ent s r es er v es th e r i gh t to
c ha n ge or di s c on ti nu e th es e pr od uct s w ith out not ice .
p
h
a
s
e
of
d
e
v
e
l
o
p
m
e
n
t
.
C ha ra ct er is tic
d
a
t
a
a
n
d
o
t
h
e
r
73
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
T M S3 2 0 VC5 410
F I X ED ĆPOI N T DI G I TAL S I GN AL PRO CE SSO R
SPRS075D – OCTOBER 1998 – REVISED MAY 2000
HPI8 timing (continued)
†‡
timing requirements (see Figure 40 Figure 41 and Figure 42)
,
,
’VC5410-100
’VC5410-120
UNIT
MIN
5
MAX
MIN
5
MAX
§
t
t
t
t
t
t
t
Setup time, HBIL valid before DS low
Hold time, HBIL valid after DS low
Setup time, HAS low before DS low
Pulse duration, DS low
ns
ns
ns
ns
ns
ns
ns
su(HBV-DSL)
h(DSL-HBV)
su(HSL-DSL)
w(DSL)
5
5
10
20
10
5
10
20
10
5
Pulse duration, DS high
w(DSH)
Setup time, HD valid before DS high, HPI write
Hold time, HD valid after DS high, HPI write
su(HDV-DSH)
h(DSH-HDV)W
3
3
†
DS refers to the logical OR of HCS, HDS1, and HDS2.
‡
§
HD refers to any of the HPI data bus pins (HD0, HD1, HD2, etc.).
When HAS is not used (HAS always high), this timing refers to DS
P ROD UCT PR EV IEW in f or m a ti on co nce r ns pr od uct s in th e fo rm at iv e or
d e s i g n ph a s e of de v e l op me nt. C ha ra ct er is tic da ta an d ot her
s p e c i fi ca t i ons a r e de s i gn go a ls . Tex a s Ins tr um ent s r es er v es th e r igh t to
c h a n g e or di s c on ti nue t he s e pr od uct s w ith out not ice .
74
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
T MS 3 20 VC 54 10
A
F
I
X
E
D
Ć
P
O
I
N
T
D
I
GI
TA
L
S
I
G
N
L
P RO C ES S O R
SPRS075D – OCTOBER 1998 – REVISED MAY 2000
HPI8 timing (continued)
Second Byte
First Byte
Second Byte
HAS
‡
t
su(HBV-DSL)
t
su(HSL-DSL)
t
h(DSL-HBV)
†
HAD
Valid
Valid
‡
t
su(HBV-DSL)
‡
t
h(DSL-HBV)
HBIL
HCS
t
w(DSH)
t
w(DSL)
HDS
t
d(DSH-HYH)
t
d(DSH-HYL)
HRDY
t
en(DSL-HD)
t
d(DSL-HDV2)
t
d(DSL-HDV1)
Valid
t
h(DSH-HDV)R
HD READ
Valid
Valid
t
su(HDV-DSH)
t
v(HYH-HDV)
Valid
t
h(DSH-HDV)W
HD WRITE
CLKOUT
Valid
Valid
t
d(COH-HYH)
†
‡
HAD refers to HCNTL0, HCNTL1, and HR/W.
When HAS is not used (HAS always high), this timing refers to DS
Figure 40. Using HDS to Control Accesses (HCS Always Low)
75
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
T M S3 2 0 VC5 410
E
F
I
X
D
Ć
P
O
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N
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D
I
G
I
TA
L
S
I
GN
A
L
P
R
O
C
E
S
S
O
R
SPRS075D – OCTOBER 1998 – REVISED MAY 2000
HPI8 timing (continued)
Second Byte
First Byte
Second Byte
HCS
HDS
t
d(HCS-HRDY)
HRDY
Figure 41. Using HCS to Control Accesses
CLKOUT
t
d(COH-HTX)
HINT
Figure 42. HINT Timing
76
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
T MS 3 20 VC 54 10
A
F
I
X
E
D
Ć
P
O
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T
D
I
GI
TA
L
S
I
G
N
L
P RO C ES S O R
SPRS075D – OCTOBER 1998 – REVISED MAY 2000
MECHANICAL DATA
PGE (S-PQFP-G144)
PLASTIC QUAD FLATPACK
108
73
109
72
0,27
M
0,08
0,17
0,50
0,13 NOM
144
37
1
36
Gage Plane
17,50 TYP
20,20
SQ
19,80
0,25
0,05 MIN
22,20
SQ
0°–ā7°
21,80
0,75
0,45
1,45
1,35
Seating Plane
0,08
1,60 MAX
4040147/C 11/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
Thermal Resistance Characteristics
PARAMETER
°C/W
R
56
ΘJA
ΘJC
R
5
77
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
T M S3 2 0 VC5 410
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S
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A
L
PRO CE SSO R
SPRS075D – OCTOBER 1998 – REVISED MAY 2000
MECHANICAL DATA
GGW (S-PBGA-N176)
PLASTIC BALL GRID ARRAY PACKAGE
15,10
SQ
12,80 TYP
0,80
14,90
U
T
R
P
N
M
L
0,80
K
J
H
G
F
E
D
C
B
A
1
3
5
7
9
11 13 15 17
10 12 14 16
2
4
6
8
0,95
0,85
1,40 MAX
Seating Plane
0,10
0,55
0,12
M
0,08
0,45
0,35
0,45
0,08
4145255/B 11/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. MicroStar BGA configuration
MicroStar BGA is a trademark of Texas Instruments Incorporated.
78
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
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