TMS320VC5503_15 [TI]
Fixed-Point Digital Signal Processor;
| 型号： | TMS320VC5503_15 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Fixed-Point Digital Signal Processor |
| 文件： | 总123页 (文件大小：1295K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TMS320VC5503 Fixed-Point
Digital Signal Processor
Data Manual
Literature Number: SPRS245C
April 2004 − Revised January 2005
ADVANCE INFORMATION concerns new products in the sampling or
preproduction phase of development. Characteristic data and other
specifications are subject to change without notice.
This page was intentionally left blank
Revision History
REVISION HISTORY
This data sheet revision history highlights the technical changes made to the SPRS245B device-specific data
sheet to make it an SPRS245C revision.
Scope: Added Section 4.1, Notices Concerning JTAG (IEEE 1149.1) Boundary Scan Test Capability; added
Package Addendum, etc.
PAGE(S)
ADDITIONS/CHANGES/DELETIONS
NO.
Global:
−
−
moved “Package Thermal Resistance Characteristics” section to Section 6, Mechanical Data
added Package Addendum
17
35
Table 2−3, Signal Descriptions:
HPI.HRDY: changed value of “I/O/Z” column from “O/Z” to “O”
−
Section 3.5.1, External Bus Selection Register (EBSR):
−
appended “After reset, the parallel port should be selected to function in either EMIF mode or HPI mode. Dynamic
switching of the parallel port, once configured, is not recommended.” to “The reset value of the parallel port mode bit field
is determined by ...” paragraph
2
57
63
63
Table 3−27, I C Module Registers:
−
2
0x3C0B: changed “I C General-Purpose Register” (I2CGPIO) to “Reserved”
Section 4:
−
renamed section from “Documentation Support” to “Support”
Section 4, Support:
−
−
−
added Section 4.1, Notices Concerning JTAG (IEEE 1149.1) Boundary Scan Test Capability
added Section 4.1.1, Initialization Requirements for Boundary Scan Test
added Section 4.1.2, Boundary Scan Description Language (BSDL) Model
63
64
Added section title “4.2 Documentation Support”
Updated Section 4.3, Device and Development-Support Tool Nomenclature
Figure 5−32, EHPI Nonmultiplexed Read/Write Timings:
111
−
updated “The falling edge of HCS must occur concurrent with or before the falling edge of HDS ...” footnote
112
113
114
115
119
Figure 5−33, EHPI Multiplexed Memory (HPID) Read/Write Timings Without Autoincrement:
updated “The falling edge of HCS must occur concurrent with or before the falling edge of HDS ...” footnote
−
Figure 5−34, EHPI Multiplexed Memory (HPID) Read Timings With Autoincrement:
updated “The falling edge of HCS must occur concurrent with or before the falling edge of HDS ...” footnote
−
Figure 5−35, EHPI Multiplexed Memory (HPID) Write Timings With Autoincrement:
updated “The falling edge of HCS must occur concurrent with or before the falling edge of HDS ...” footnote
−
Figure 5−36, EHPI Multiplexed Register Read/Write Timings:
updated “The falling edge of HCS must occur concurrent with or before the falling edge of HDS ...” footnote
−
Section 6, Mechanical Data:
−
−
added new Section 6.1, Package Thermal Resistance Characteristics
added new Section 6.2, Packaging Information
3
April 2004 − Revised January 2005
SPRS245C
Revision History
4
SPRS245C
April 2004 − Revised January 2005
Contents
Contents
Section
Page
1
TMS320VC5503 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11
2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12
12
13
13
15
17
2.1
2.2
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.1
2.2.2
Terminal Assignments for the GHH Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin Assignments for the PGE Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3
Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3
Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
27
28
28
28
29
31
32
32
33
34
34
35
37
38
40
40
41
43
45
46
48
59
60
62
62
62
3.1
Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.1
3.1.2
3.1.3
3.1.4
On-Chip Dual-Access RAM (DARAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
On-Chip Read-Only Memory (ROM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Memory Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Boot Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2
3.3
Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Direct Memory Access (DMA) Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3.1
DMA Channel Control Register (DMA_CCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2
3.4
3.5
I C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Configurable External Buses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5.1
3.5.2
3.5.3
External Bus Selection Register (EBSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Parallel Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Parallel Port Signal Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.6
General-Purpose Input/Output (GPIO) Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.6.1
3.6.2
3.6.3
Dedicated General-Purpose I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Address Bus General-Purpose I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EHPI General-Purpose I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.7
System Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Memory-Mapped Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Peripheral Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.8
3.9
3.10
3.10.1
3.10.2
3.10.3
3.10.4
IFR and IER Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Waking Up From IDLE Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Idling Clock Domain When External Parallel Bus Operating in EHPI Mode . . . . . .
4
Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
63
63
63
63
63
64
64
4.1
Notices Concerning JTAG (IEEE 1149.1) Boundary Scan Test Capability . . . . . . . . . . . . . . . . .
4.1.1
4.1.2
Initialization Requirements for Boundary Scan Test . . . . . . . . . . . . . . . . . . . . . . . . . .
Boundary Scan Description Language (BSDL) Model . . . . . . . . . . . . . . . . . . . . . . . .
4.2
4.3
4.4
Documentation Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Device and Development-Support Tool Nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TMS320VC5503 Device Nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5
April 2004 − Revised January 2005
SPRS245C
Contents
Section
Page
5
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
65
65
66
66
67
68
69
5.1
5.2
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.2.1
5.2.2
5.2.3
Recommended Operating Conditions for CV = 1.2 V (108 MHz) . . . . . . . . . . . . .
DD
Recommended Operating Conditions for CV = 1.35 V (144 MHz) . . . . . . . . . . . .
DD
Recommended Operating Conditions for CV = 1.6 V (200 MHz) . . . . . . . . . . . . .
DD
5.3
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3.1
5.3.2
5.3.3
Electrical Characteristics Over Recommended Operating Case Temperature
Range for CV = 1.2 V (108 MHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
69
70
DD
Electrical Characteristics Over Recommended Operating Case Temperature
Range for CV = 1.35 V (144 MHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DD
Electrical Characteristics Over Recommended Operating Case Temperature
Range for CV = 1.6 V (200 MHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
71
72
72
73
73
74
75
76
77
78
78
81
89
89
90
91
92
92
93
94
95
96
96
98
101
109
110
116
DD
5.4
5.5
5.6
ESD Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timing Parameter Symbology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.6.1
5.6.2
5.6.3
5.6.4
5.6.5
Internal System Oscillator With External Crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Layout Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock Generation in Bypass Mode (DPLL Disabled) . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock Generation in Lock Mode (DPLL Synthesis Enabled) . . . . . . . . . . . . . . . . . . .
Real-Time Clock Oscillator With External Crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.7
5.8
Memory Interface Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.7.1
5.7.2
Asynchronous Memory Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Synchronous DRAM (SDRAM) Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reset Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.8.1
5.8.2
5.8.3
Power-Up Reset (On-Chip Oscillator Active) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power-Up Reset (On-Chip Oscillator Inactive) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Warm Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.9
External Interrupt Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Wake-Up From IDLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
XF Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
General-Purpose Input/Output (GPIOx) Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TIN/TOUT Timings (Timer0 Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Multichannel Buffered Serial Port (McBSP) Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.10
5.11
5.12
5.13
5.14
5.14.1
5.14.2
5.14.3
5.14.4
McBSP0 Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
McBSP1 and McBSP2 Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
McBSP as SPI Master or Slave Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
McBSP General-Purpose I/O Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.15
5.16
Enhanced Host-Port Interface (EHPI) Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2
I C Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6
Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
119
119
119
6.1
6.2
Package Thermal Resistance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Packaging Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6
SPRS245C
April 2004 − Revised January 2005
Figures
Page
List of Figures
Figure
2−1
2−2
179-Terminal GHH Ball Grid Array (Bottom View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
144-Pin PGE Low-Profile Quad Flatpack (Top View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13
15
3−1
3−2
3−3
3−4
3−5
3−6
3−7
3−8
3−9
Block Diagram of the TMS320VC5503 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TMS320VC5503 Memory Map (PGE Package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TMS320VC5503 Memory Map (GHH Package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DMA_CCR Bit Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
External Bus Selection Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Parallel Port Signal Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Parallel Port (EMIF) Signal Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I/O Direction Register (IODIR) Bit Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I/O Data Register (IODATA) Bit Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
27
29
30
33
35
38
39
40
41
41
42
42
43
43
44
45
60
61
3−10 Address/GPIO Enable Register (AGPIOEN) Bit Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−11 Address/GPIO Direction Register (AGPIODIR) Bit Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−12 Address/GPIO Data Register (AGPIODATA) Bit Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−13 EHPI GPIO Enable Register (EHPIGPIOEN) Bit Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−14 EHPI GPIO Direction Register (EHPIGPIODIR) Bit Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−15 EHPI GPIO Data Register (EHPIGPIODATA) Bit Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−16 System Register Bit Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−17 IFR0 and IER0 Bit Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−18 IFR1 and IER1 Bit Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−1
Device Nomenclature for the TMS320VC5503 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
64
5−1
5−2
5−3
5−4
5−5
5−6
5−7
5−8
5−9
3.3-V Test Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Internal System Oscillator With External Crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bypass Mode Clock Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
External Multiply-by-N Clock Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Real-Time Clock Oscillator With External Crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Asynchronous Memory Read Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Asynchronous Memory Write Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Three SDRAM Read Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Three SDRAM WRT Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
72
73
75
77
77
79
80
82
83
84
85
86
87
88
5−10 SDRAM ACTV Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−11 SDRAM DCAB Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−12 SDRAM REFR Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−13 SDRAM MRS Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−14 SDRAM Self-Refresh Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7
April 2004 − Revised January 2005
SPRS245C
Figures
Figure
Page
5−15 Power-Up Reset (On-Chip Oscillator Active) Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−16 Power-Up Reset (On-Chip Oscillator Inactive) Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−17 Reset Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−18 External Interrupt Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−19 Wake-Up From IDLE Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−20 XF Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−21 General-Purpose Input/Output (IOx) Signal Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−22 TIN/TOUT Timings When Configured as Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−23 TIN/TOUT Timings When Configured as Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−24 McBSP Receive Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−25 McBSP Transmit Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−26 McBSP Timings as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0 . . . . . . . . . . . . . . . . . . . . . . .
5−27 McBSP Timings as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0 . . . . . . . . . . . . . . . . . . . . . . .
5−28 McBSP Timings as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1 . . . . . . . . . . . . . . . . . . . . . . .
5−29 McBSP Timings as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1 . . . . . . . . . . . . . . . . . . . . . . .
5−30 McBSP General-Purpose I/O Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−31 HINT Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−32 EHPI Nonmultiplexed Read/Write Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−33 EHPI Multiplexed Memory (HPID) Read/Write Timings Without Autoincrement . . . . . . . . . . . . . . . .
5−34 EHPI Multiplexed Memory (HPID) Read Timings With Autoincrement . . . . . . . . . . . . . . . . . . . . . . . .
5−35 EHPI Multiplexed Memory (HPID) Write Timings With Autoincrement . . . . . . . . . . . . . . . . . . . . . . . .
5−36 EHPI Multiplexed Register Read/Write Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
89
90
91
92
92
93
94
95
95
100
100
102
104
106
108
109
111
111
112
113
114
115
117
118
2
5−37 I C Receive Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2
5−38 I C Transmit Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8
SPRS245C
April 2004 − Revised January 2005
Tables
Page
List of Tables
Table
2−1
2−2
2−3
Pin Assignments for the GHH Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin Assignments for the PGE Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14
16
17
3−1
3−2
3−3
3−4
3−5
3−6
3−7
3−8
DARAM Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Boot Configuration Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Synchronization Control Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
External Bus Selection Register Bit Field Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TMS320VC5503 Parallel Port Signal Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I/O Direction Register (IODIR) Bit Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I/O Data Register (IODATA) Bit Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Address/GPIO Enable Register (AGPIOEN) Bit Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Address/GPIO Direction Register (AGPIODIR) Bit Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Address/GPIO Data Register (AGPIODATA) Bit Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EHPI GPIO Enable Register (EHPIGPIOEN) Bit Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EHPI GPIO Direction Register (EHPIGPIODIR) Bit Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EHPI GPIO Data Register (EHPIGPIODATA) Bit Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
System Register Bit Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CPU Memory-Mapped Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Idle Control, Status, and System Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
External Memory Interface Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DMA Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Real-Time Clock Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Multichannel Serial Port #0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Multichannel Serial Port #1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Multichannel Serial Port #2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Device Revision ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28
31
33
35
37
40
41
41
42
42
43
43
44
45
46
48
48
49
52
53
53
54
55
56
57
57
57
58
58
59
60
61
3−9
3−10
3−11
3−12
3−13
3−14
3−15
3−16
3−17
3−18
3−19
3−20
3−21
3−22
3−23
3−24
3−25
3−26
3−27
3−28
3−29
3−30
3−31
3−32
2
I C Module Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Watchdog Timer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
External Bus Selection Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IFR0 and IER0 Register Bit Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IFR1 and IER1 Register Bit Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−1
5−2
5−3
5−4
5−5
5−6
5−7
5−8
Recommended Crystal Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CLKIN Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CLKOUT Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Multiply-By-N Clock Option Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Multiply-By-N Clock Option Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Recommended RTC Crystal Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Asynchronous Memory Cycle Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Asynchronous Memory Cycle Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
73
75
75
76
76
77
78
78
9
April 2004 − Revised January 2005
SPRS245C
Tables
Table
Page
5−9
Synchronous DRAM Cycle Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Synchronous DRAM Cycle Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power-Up Reset (On-Chip Oscillator Active) Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . .
Power-Up Reset (On-Chip Oscillator Inactive) Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . .
Power-Up Reset (On-Chip Oscillator Inactive) Switching Characteristics . . . . . . . . . . . . . . . . . . . .
Reset Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reset Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
External Interrupt Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Wake-Up From IDLE Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
XF Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GPIO Pins Configured as Inputs Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GPIO Pins Configured as Outputs Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TIN/TOUT Pins Configured as Inputs Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TIN/TOUT Pins Configured as Outputs Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . .
McBSP0 Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
McBSP0 Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
McBSP1 and McBSP2 Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
McBSP1 and McBSP2 Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0) . . . . . . . . . .
McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 0) . . . . . .
McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 0) . . . . . . . . . .
McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 0) . . . . . . .
McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 1) . . . . . . . . . .
McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 1) . . . . . .
McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 1) . . . . . . . . . .
McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 1) . . . . . . .
McBSP General-Purpose I/O Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
McBSP General-Purpose I/O Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EHPI Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EHPI Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
81
81
89
90
90
91
91
92
92
93
94
94
95
95
96
97
98
5−10
5−11
5−12
5−13
5−14
5−15
5−16
5−17
5−18
5−19
5−20
5−21
5−22
5−23
5−24
5−25
5−26
5−27
5−28
5−29
5−30
5−31
5−32
5−33
5−34
5−35
5−36
5−37
5−38
5−39
5−40
99
101
101
103
103
105
105
107
107
109
109
110
110
116
118
2
I C Signals (SDA and SCL) Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2
I C Signals (SDA and SCL) Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−1
6−2
Thermal Resistance Characteristics (Ambient) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Thermal Resistance Characteristics (Case) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
119
119
10
SPRS245C
April 2004 − Revised January 2005
Features
1
TMS320VC5503 Features
D High-Performance, Low-Power, Fixed-Point
TMS320C55x Digital Signal Processor
− 9.26-, 6.95-, 5-ns Instruction Cycle Time
− 108-, 144-, 200-MHz Clock Rate
− One/Two Instruction(s) Executed per
Cycle
D On-Chip Peripherals
− Two 20-Bit Timers
− Watchdog Timer
− Six-Channel Direct Memory Access
(DMA) Controller
− Three Multichannel Buffered Serial Ports
(McBSPs)
− Dual Multipliers [Up to 400 Million
Multiply-Accumulates per Second
(MMACS)]
− Two Arithmetic/Logic Units (ALUs)
− Three Internal Data/Operand Read Buses
and Two Internal Data/Operand Write
Buses
− Programmable Phase-Locked Loop
Clock Generator
− Seven (LQFP) or Eight (BGA) General-
Purpose I/O (GPIO) Pins and a General-
Purpose Output Pin (XF)
2
D 32K x 16-Bit On-Chip RAM, Composed of:
− 64K Bytes of Dual-Access RAM (DARAM)
8 Blocks of 4K × 16-Bit
− Inter-Integrated Circuit (I C) Multi-Master
and Slave Interface
− Real-Time Clock (RTC) With Crystal
Input, Separate Clock Domain, Separate
Power Supply
D 64K Bytes of One-Wait-State On-Chip ROM
(32K × 16-Bit)
†
D 8M × 16-Bit Maximum Addressable External
D IEEE Std 1149.1 (JTAG) Boundary Scan
Memory Space (Synchronous DRAM)
Logic
D 16-Bit External Parallel Bus Memory
D Packages:
Supporting Either:
− 144-Terminal Low-Profile Quad Flatpack
(LQFP) (PGE Suffix)
− External Memory Interface (EMIF) With
GPIO Capabilities and Glueless Interface
to:
− Asynchronous Static RAM (SRAM)
− Asynchronous EPROM
− Synchronous DRAM (SDRAM)
− 16-Bit Parallel Enhanced Host-Port
Interface (EHPI) With GPIO Capabilities
− 179-Terminal MicroStar BGA (Ball Grid
Array) (GHH Suffix)
D 1.2-V Core (108 MHz), 2.7-V – 3.6-V I/Os
D 1.35-V Core (144 MHz), 2.7-V – 3.6-V I/Os
D 1.6-V Core (200 MHz), 2.7-V – 3.6-V I/Os
D Programmable Low-Power Control of Six
Device Functional Domains
D On-Chip Scan-Based Emulation Logic
TMS320C55x and MicroStar BGA are trademarks of Texas Instruments.
All trademarks are the property of their respective owners.
†
IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
11
April 2004 − Revised January 2005
SPRS245C
Introduction
2
Introduction
This section describes the main features of the TMS320VC5503, lists the pin assignments, and describes the
function of each pin. This data manual also provides a detailed description section, electrical specifications,
parameter measurement information, and mechanical data about the available packaging.
NOTE: This data manual is designed to be used in conjunction with theTMS320C55x DSP Functional
Overview (literature number SPRU312), the TMS320C55x DSP CPU Reference Guide (literature
number SPRU371), and the TMS320C55x DSP Peripherals Overview Reference Guide (literature
number SPRU317).
2.1 Description
The TMS320VC5503 fixed-point digital signal processor (DSP) is based on the TMS320C55x DSP generation
CPU processor core. The C55x DSP architecture achieves high performance and low power through
increased parallelism and total focus on reduction in power dissipation. The CPU supports an internal bus
structure that is composed of one program bus, three data read buses, two data write buses, and additional
buses dedicated to peripheral and DMA activity. These buses provide the ability to perform up to three data
reads and two data writes in a single cycle. In parallel, the DMA controller can perform up to two data transfers
per cycle independent of the CPU activity.
The C55x CPU provides two multiply-accumulate (MAC) units, each capable of 17-bit x 17-bit multiplication
in a single cycle. A central 40-bit arithmetic/logic unit (ALU) is supported by an additional 16-bit ALU. Use of
the ALUs is under instruction set control, providing the ability to optimize parallel activity and power
consumption. These resources are managed in the Address Unit (AU) and Data Unit (DU) of the C55x CPU.
The C55x DSP generation supports a variable byte width instruction set for improved code density. The
Instruction Unit (IU) performs 32-bit program fetches from internal or external memory and queues instructions
for the Program Unit (PU). The Program Unit decodes the instructions, directs tasks to AU and DU resources,
and manages the fully protected pipeline. Predictive branching capability avoids pipeline flushes on execution
of conditional instructions.
The 64K bytes of on-chip memory on TMS320VC5503 is sufficient for many small hand-held appliances,
portable personal appliances, gaming devices, and personal medical care appliances. Many of these
appliances typically require 64K bytes or smaller amount of on-chip memory and need to operate in standby
mode for more than 60% to 70% of the time. For applications that require more than 64K bytes of on-chip
memory but less than 128K bytes of memory, Texas Instruments (TI) offers the TMS320VC5507 device, which
is based on the TMS320C55x DSP core.
The general-purpose input and output functions provide sufficient pins for status, interrupts, and bit I/O for
LCDs, keyboards, and media interfaces. The parallel interface operates in two modes, either as a slave to a
microcontroller using the HPI port or as a parallel media interface using the asynchronous EMIF. Serial media
is supported through three McBSPs.
The 5503 peripheral set includes an external memory interface (EMIF) that provides glueless access to
asynchronous memories like EPROM and SRAM, as well as to high-speed, high-density memories such as
2
synchronous DRAM. Additional peripherals include real-time clock, watchdog timer, and I C multi-master and
slave interface. Three full-duplex multichannel buffered serial ports (McBSPs) provide glueless interface to
a variety of industry-standard serial devices, and multichannel communication with up to 128 separately
enabled channels. The enhanced host-port interface (HPI) is a 16-bit parallel interface used to provide host
processor access to 32K bytes of internal memory on the 5503. The HPI can be configured in either
multiplexed or non-multiplexed mode to provide glueless interface to a wide variety of host processors. The
DMA controller provides data movement for six independent channel contexts without CPU intervention,
providing DMA throughput of up to two 16-bit words per cycle. Two general-purpose timers, up to eight
dedicated general-purpose I/O (GPIO) pins, and digital phase-locked loop (DPLL) clock generation are also
included.
C55x, eXpressDSP, Code Composer Studio, DSP/BIOS, RTDX, and XDS510 are trademarks of Texas Instruments.
12
SPRS245C
April 2004 − Revised January 2005
Introduction
The 5503 is supported by the industry’s award-winning eXpressDSP, Code Composer Studio Integrated
Development Environment (IDE), DSP/BIOS, Texas Instruments’ algorithm standard, and the industry’s
largest third-party network. The Code Composer Studio IDE features code generation tools including a
C Compiler and Visual Linker, simulator, RTDX, XDS510 emulation device drivers, and evaluation
modules. The 5503 is also supported by the C55x DSP Library which features more than 50 foundational
software kernels (FIR filters, IIR filters, FFTs, and various math functions) as well as chip and board support
libraries.
2.2 Pin Assignments
Figure 2−1 illustrates the ball locations for the 179-pin ball grid array (BGA) package and is used in conjunction
with Table 2−1 to locate signal names and ball grid numbers.
DV is the power supply for the I/O pins while CV is the power supply for the core. V is the ground for
DD
DD
SS
both the I/O pins and the core. RCV and RDV are RTC module core and I/O supply, respectively.
DD
DD
2.2.1 Terminal Assignments for the GHH Package
P
N
M
L
K
J
H
G
F
E
D
C
B
A
1
2 3 4 5 6 7 8 9 10 11 12 13 14
Figure 2−1. 179-Terminal GHH Ball Grid Array (Bottom View)
13
April 2004 − Revised January 2005
SPRS245C
Introduction
Table 2−1. Pin Assignments for the GHH Package
SIGNAL
NAME
SIGNAL
NAME
SIGNAL
NAME
BALL #
SIGNAL NAME
BALL #
BALL #
BALL #
A2
A3
V
D5
D6
GPIO5
DR0
H2
H3
H4
H5
H10
H11
H12
H13
H14
J1
DV
L13
L14
M1
M2
M3
M4
M5
M6
M7
M8
M9
M10
M11
M12
M13
M14
N1
D15
SS
DD
GPIO4
DV
A19
CV
DD
A4
D7
CLKR1
DR1
C4
C5
C10
C13
DD
A5
FSR0
CV
D8
A6
D9
DV
DV
V
SS
DD
DD
DD
A7
FSR1
DV
D10
D11
D12
D13
D14
E1
FSX2
A’[0]
RESET
SDA
SCL
CV
DD
A8
V
V
SS
DD
SS
A9
CLKR2
DR2
NC
NC
A5
A10
A11
A12
A13
A14
B1
A1
A15
D3
DX2
NC
C6
RTCINX1
GPIO1
GPIO2
J2
DV
DD
RDV
RDV
E2
J3
C7
C8
D6
DD
DD
E3
DV
J4
CV
DD
DD
DD
V
E4
V
V
J5
CV
DV
SS
SS
SS
DD
DD
DD
B2
CV
E5
J10
J11
J12
J13
J14
K1
CV
CV
V
SS
DD
B3
GPIO3
TIN/TOUT0
CLKR0
E6
DV
D12
DD
B4
E7
DX0
FSX1
DX1
NC
TRST
TCK
TMS
A18
C9
V
V
SS
SS
B5
E8
N2
B6
FSX0
E9
N3
A13
A10
A7
B7
CV
CV
E10
E11
E12
E13
E14
F1
N4
DD
DD
B8
NC
K2
N5
B9
V
V
V
K3
C11
N6
DV
SS
SS
SS
DD
DD
DD
B10
B11
B12
B13
B14
C1
CLKX2
K4
V
V
N7
CV
CV
SS
SS
V
XF
X1
K5
N8
SS
RTCINX2
RDV
K6
A3
N9
V
V
SS
SS
F2
X2/CLKIN
GPIO0
K7
A2
D1
N10
N11
N12
N13
N14
P1
DD
V
F3
K8
D8
SS
NC
F4
V
K9
A14
D11
SS
C2
V
F5
CLKOUT
DV
K10
K11
K12
K13
K14
L1
DV
DV
DD
SS
DD
C3
NC
F10
F11
F12
F13
F14
G1
EMU0
EMU1/OFF
TDO
V
V
V
DD
SS
SS
SS
C4
GPIO6
V
SS
C5
V
INT4
DV
P2
SS
C6
CLKX0
TDI
P3
A12
A9
DD
C7
V
INT3
CV
CV
P4
SS
DD
C8
CLKX1
FSR2
L2
C14
P5
A17
A4
DD
C9
G2
C1
L3
C12
A11
A8
P6
C10
C11
C12
C13
C14
D1
CV
G3
A20
C2
L4
P7
A16
DD
V
G4
L5
P8
DV
DD
SS
RCV
G5
C0
L6
A6
P9
D2
D5
DD
V
G10
G11
G12
G13
G14
H1
INT2
L7
A0
P10
P11
P12
P13
P14
SS
DV
CV
L8
D0
D7
DD
DD
GPIO7
DV
V
L9
D4
D10
SS
D2
INT1
INT0
C3
L10
L11
L12
D9
DV
DD
DD
DD
D3
RSVD2
RSVD1
D13
D14
DV
D4
14
SPRS245C
April 2004 − Revised January 2005
Introduction
2.2.2 Pin Assignments for the PGE Package
The TMS320VC5503PGE 144-pin low-profile quad flatpack (LQFP) pin assignments are shown in Figure 2−2
and is used in conjunction with Table 2−2 to locate signal names and pin numbers.
DV is the power supply for the I/O pins while CV is the power supply for the core. V is the ground for
DD
DD
SS
both the I/O pins and the core. RCV and RDV are RTC module core and I/O supply, respectively.
DD
DD
108
73
109
72
144
37
1
36
Figure 2−2. 144-Pin PGE Low-Profile Quad Flatpack (Top View)
15
April 2004 − Revised January 2005
SPRS245C
Introduction
Table 2−2. Pin Assignments for the PGE Package
PIN NO.
1
SIGNAL NAME
PIN NO.
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
SIGNAL NAME
PIN NO.
73
SIGNAL NAME
PIN NO.
109
110
111
SIGNAL NAME
V
V
V
RDV
RCV
SS
SS
SS
DD
DD
2
NC
A13
A12
A11
74
D12
D13
D14
D15
3
RSVD1
RSVD2
75
RTCINX2
RTCINX1
4
76
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
5
DV
CV
77
V
V
V
DD
DD
SS
SS
SS
6
GPIO7
A10
A9
78
CV
DD
7
V
79
EMU0
EMU1/OFF
TDO
SS
8
DV
A8
80
DX2
DD
9
GPIO2
GPIO1
V
81
FSX2
SS
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
A7
82
TDI
CV
DD
V
A6
A5
83
CV
CLKX2
DR2
SS
DD
GPIO0
X2/CLKIN
X1
84
TRST
TCK
DV
85
FSR2
DD
A4
A3
A2
86
TMS
V
SS
CLKOUT
C0
87
CV
DV
CLKR2
DX1
DD
DD
88
C1
CV
89
SDA
SCL
FSX1
DD
CV
A1
A0
90
DV
DD
DD
C2
91
RESET
CLKX1
DR1
C3
C4
C5
C6
DV
92
V
SS
DD
D0
D1
D2
93
INT0
INT1
FSR1
CLKR1
DX0
94
95
CV
DD
DV
V
96
INT2
INT3
CV
DD
DD
SS
C7
C8
D3
97
FSX0
CLKX0
DR0
D4
D5
98
DV
DD
C9
99
INT4
C11
V
100
101
102
103
104
105
106
107
108
V
FSR0
CLKR0
SS
SS
CV
D6
XF
DD
DD
CV
D7
D8
V
V
SS
SS
SS
C14
C12
V
DV
DD
CV
DV
TIN/TOUT0
GPIO6
DD
DD
V
D9
D10
D11
NC
NC
DV
SS
C10
C13
GPIO4
GPIO3
DD
V
DV
V
V
SS
SS
DD
SS
16
SPRS245C
April 2004 − Revised January 2005
Introduction
2.3 Signal Descriptions
Table 2−3 lists each signal, function, and operating mode(s) grouped by function. See Section 2.2 for pin
locations based on package type.
Table 2−3. Signal Descriptions
TERMINAL MULTIPLEXED
RESET
CONDITION
†
‡
I/O/Z
FUNCTION
BK
NAME
SIGNAL NAME
PARALLEL BUS
A subset of the parallel address bus A13−A0 of the C55x DSP core
bonded to external pins. These pins serve in one of three functions: HPI
address bus (HPI.HA[13:0]), EMIF address bus (EMIF.A[13:0]), or
general-purpose I/O (GPIO.A[13:0]). The initial state of these pins
depends on the GPIO0 pin. See Section 3.5.1 for more information.
A[13:0]
I/O/Z
The address bus has a bus holder feature that eliminates passive
component requirement and the power dissipation associated with them.
The bus holders keep the address bus at the previous logic level when the
bus goes into a high-impedance state.
GPIO0 = 1:
HPI address bus. HPI.HA[13:0] is selected when the Parallel Port Mode bit
field of the External Bus Selection Register is 10. This setting enables the
HPI in non-multiplexed mode.
Output,
EMIF.A[13:0]
HPI.HA[13:0]
EMIF.A[13:0]
I
HPI.HA[13:0] provides DSP internal memory access to host. In
non-multiplexed mode, these signals are driven by an external host as
address lines.
BK
GPIO0 = 0:
Input,
EMIF address bus. EMIF.A[13:0] is selected when the Parallel Port Mode
bit field of the External Bus Selection Register is 01. This setting enables
the full EMIF mode and the EMIF drives the parallel port address bus. The
internal A[14] address is exclusive-ORed with internal A[0] address and
the result is routed to the A[0] pin.
HPI.HA[13:0]
O/Z
General-purpose I/O address bus. GPIO.A[13:0] is selected when the
Parallel Port Mode bit field of the External Bus Selection Register is 11.
This setting enables the HPI in multiplexed mode with the Parallel Port
GPIO register controlling the parallel port address bus. GPIO is also
selected when the Parallel Port Mode bit field is 00, enabling the Data
EMIF mode.
GPIO.A[13:0]
I/O/Z
O/Z
A′[0]
(BGA only)
EMIF address bus A′[0]. This pin is not multiplexed with EMIF.A[14] and is
used as the least significant external address pin on the BGA package.
EMIF.A′[0]
Output
†
I = Input, O = Output, S = Supply, Hi-Z = High-impedance
BK = bus keeper (the bus keeper maintains the previous voltage level during reset or while the output pin is not driven), PU = pullup,
PD = pulldown, H = hysteresis input buffer, FS = fail-safe buffer
‡
17
April 2004 − Revised January 2005
SPRS245C
Introduction
Table 2−3. Signal Descriptions (Continued)
TERMINAL MULTIPLEXED
RESET
CONDITION
†
‡
I/O/Z
FUNCTION
BK
NAME
SIGNAL NAME
PARALLEL BUS (CONTINUED)
A subset of the parallel address bus A15−A14 of the C55x DSP core
bonded to external pins. These pins serve in one of two functions: EMIF
address bus (EMIF.A[15:14]), or general-purpose I/O (GPIO.A[15:14]).
The initial state of these pins depends on the GPIO0 pin. See Section 3.5.1
for more information.
A[15:14]
I/O/Z
(BGA only)
The address bus has a bus holder feature that eliminates passive
component requirement and the power dissipation associated with them.
The bus holders keep the address bus at the previous logic level when the
bus goes into a high-impedance state.
GPIO0 = 1:
Output,
EMIF.A[15:14]
BK
EMIF address bus. EMIF.A[15:14] is selected when the Parallel Port Mode
bit field of the External Bus Selection Register is 01. This setting enables
the full EMIF mode and the EMIF drives the parallel port address bus.
GPIO0 = 0:
Input,
EMIF.A[15:14]
GPIO.A[15:14]
O/Z
GPIO.A[15:14]
General-purpose I/O address bus. GPIO.A[15:14] is selected when the
Parallel Port Mode bit field of the External Bus Selection Register is 11.
This setting enables the HPI in multiplexed mode with the Parallel Port
GPIO register controlling the parallel port address bus. GPIO is also
selected when the Parallel Port Mode bit field is 00, enabling the Data
EMIF mode.
I/O/Z
EMIF address bus. At reset, these address pins are set as output.
A[20:16]
EMIF.A[20:16]
O/Z
Output
(BGA only)
NOTE: These pins only function as EMIF address pins and they are not
multiplexed for any other function.
A subset of the parallel bidirectional data bus D31−D0 of the C55x DSP
core. These pins serve in one of two functions: EMIF data bus
(EMIF.D[15:0]) or HPI data bus (HPI.HD[15:0]). The initial state of these
pins depends on the GPIO0 pin. See Section 3.5.1 for more information.
GPIO0 = 1:
Input,
The data bus includes bus keepers to reduce the static power dissipation
caused by floating, unused pins. This eliminates the need for external bias
resistors on unused pins. When the data bus is not being driven by the
CPU, the bus keepers keep the pins at the logic level that was most
recently driven. (The data bus keepers are disabled at reset, and can be
enabled/disabled under software control.)
D[15:0]
I/O/Z
EMIF.D[15:0]
BK
GPIO0 = 0:
Input,
HPI.HD[15:0]
EMIF data bus. EMIF.D[15:0] is selected when the Parallel Port Mode bit
field of the External Bus Selection Register is 00 or 01.
EMIF.D[15:0]
HPI.HD[15:0]
I/O/Z
I/O/Z
HPI data bus. HPI.HD[15:0] is selected when the Parallel Port Mode bit
field of the External Bus Selection Register is 10 or 11.
†
I = Input, O = Output, S = Supply, Hi-Z = High-impedance
BK = bus keeper (the bus keeper maintains the previous voltage level during reset or while the output pin is not driven), PU = pullup,
PD = pulldown, H = hysteresis input buffer, FS = fail-safe buffer
‡
18
SPRS245C
April 2004 − Revised January 2005
Introduction
Table 2−3. Signal Descriptions (Continued)
TERMINAL MULTIPLEXED
RESET
CONDITION
†
‡
I/O/Z
FUNCTION
BK
NAME
SIGNAL NAME
PARALLEL BUS (CONTINUED)
EMIF asynchronous memory read enable or general-purpose IO8. This
pin serves in one of two functions: EMIF asynchronous memory read
enable (EMIF.ARE) or general-purpose IO8 (GPIO8). The initial state of
this pin depends on the GPIO0 pin. See Section 3.5.1 for more information.
GPIO0 = 1:
Output,
C0
I/O/Z
EMIF.ARE
Active-low EMIF asynchronous memory read enable. EMIF.ARE is
selected when the Parallel Port Mode bit field of the External Bus Selection
Register is 00 or 01.
BK
EMIF.ARE
GPIO8
O/Z
GPIO0 = 0:
Input,
GPIO8
General-purpose IO8. GPIO8 is selected when the Parallel Port Mode bit
field of the External Bus Selection Register is set to 10 or 11.
I/O/Z
EMIF asynchronous memory output enable or HPI interrupt output. This
pin serves in one of two functions: EMIF asynchronous memory output
enable (EMIF.AOE) or HPI interrupt output (HPI.HINT). The initial state of
this pin depends on the GPIO0 pin. See Section 3.5.1 for more information.
GPIO0 = 1:
Output,
C1
O/Z
EMIF.AOE
Active-low asynchronous memory output enable. EMIF.AOE is selected
when the Parallel Port Mode bit field of the External Bus Selection Register
is 00 or 01.
EMIF.AOE
HPI.HINT
O/Z
O/Z
GPIO0 = 0:
Output,
HPI.HINT
Active-low HPI interrupt output. HPI.HINT is selected when the Parallel
Port Mode bit field of the External Bus Selection Register is 10 or 11.
EMIF asynchronous memory write enable or HPI read/write. This pin
serves in one of two functions: EMIF asynchronous memory write enable
(EMIF.AWE) or HPI read/write (HPI.HR/W). The initial state of this pin
depends on the GPIO0 pin. See Section 3.5.1 for more information.
C2
I/O/Z
GPIO0 = 1:
Output,
EMIF.AWE
Active-low EMIF asynchronous memory write enable. EMIF.AWE is
selected when the Parallel Port Mode bit field of the External Bus Selection
Register is 00 or 01.
BK
EMIF.AWE
HPI.HR/W
O/Z
I
GPIO0 = 0:
Input,
HPI read/write. HPI.HR/W is selected when the Parallel Port Mode bit field
of the External Bus Selection Register is 10 or 11. HPI.HR/W controls the
direction of the HPI transfer.
HPI.HR/W
EMIF data ready input or HPI ready output. This pin serves in one of two
functions: EMIF data ready input (EMIF.ARDY) or HPI ready output
(HPI.HRDY). The initial state of this pin depends on the GPIO0 pin. See
Section 3.5.1 for more information.
GPIO0 = 1:
Input,
C3
I/O/Z
EMIF.ARDY
EMIF data ready input. Used to insert wait states for slow memories.
EMIF.ARDY is selected when the Parallel Port Mode bit field of the
External Bus Selection Register is 00 or 01.
H
EMIF.ARDY
HPI.HRDY
I
GPIO0 = 0:
Output,
HPI.HRDY
HPI ready output. HPI.HRDY is selected when the Parallel Port Mode bit
field of the External Bus Selection Register is 10 or 11.
O
†
I = Input, O = Output, S = Supply, Hi-Z = High-impedance
BK = bus keeper (the bus keeper maintains the previous voltage level during reset or while the output pin is not driven), PU = pullup,
PD = pulldown, H = hysteresis input buffer, FS = fail-safe buffer
‡
19
April 2004 − Revised January 2005
SPRS245C
Introduction
Table 2−3. Signal Descriptions (Continued)
TERMINAL MULTIPLEXED
RESET
CONDITION
†
‡
I/O/Z
FUNCTION
BK
NAME
SIGNAL NAME
PARALLEL BUS (CONTINUED)
EMIF chip select for memory space CE0 or general-purpose IO9. This pin
serves in one of two functions: EMIF chip select for memory space CE0
(EMIF.CE0) or general-purpose IO9 (GPIO9). The initial state of this pin
depends on the GPIO0 pin. See Section 3.5.1 for more information.
GPIO0 = 1:
Output,
C4
I/O/Z
EMIF.CE0
Active-low EMIF chip select for memory space CE0. EMIF.CE0 is selected
when the Parallel Port Mode bit field of the External Bus Selection Register
is set to 00 or 01.
BK
EMIF.CE0
GPIO9
O/Z
GPIO0 = 0:
Input,
GPIO9
General-purpose IO9. GPIO9 is selected when the Parallel Port Mode bit
field of the External Bus Selection Register is set to 10 or 11.
I/O/Z
EMIF chip select for memory space CE1 or general-purpose IO10. This pin
serves in one of two functions: EMIF chip-select for memory space CE1
(EMIF.CE1) or general-purpose IO10 (GPIO10). The initial state of this pin
depends on the GPIO0 pin. See Section 3.5.1 for more information.
GPIO0 = 1:
Output,
C5
I/O/Z
EMIF.CE1
Active-low EMIF chip select for memory space CE1. EMIF.CE1 is selected
when the Parallel Port Mode bit field of the External Bus Selection Register
is set to 00 or 01.
BK
EMIF.CE1
GPIO10
O/Z
GPIO0 = 0:
Input,
GPIO10
General-purpose IO10. GPIO10 is selected when the Parallel Port Mode
bit field of the External Bus Selection Register is set to 10 or 11.
I/O/Z
EMIF chip select for memory space CE2 or HPI control input 0. This pin
serves in one of two functions: EMIF chip-select for memory space CE2
(EMIF.CE2) or HPI control input 0 (HPI.HCNTL0). The initial state of this
pin depends on the GPIO0 pin. See Section 3.5.1 for more information.
C6
I/O/Z
O/Z
I
GPIO0 = 1:
Output,
Active-low EMIF chip select for memory space CE2. EMIF.CE2 is selected
when the Parallel Port Mode bit field of the External Bus Selection Register
is set to 00 or 01.
EMIF.CE2
EMIF.CE2
BK
GPIO0 = 0:
Input,
HPI control input 0. This pin, in conjunction with HPI.HCNTL1, selects a
host access to one of the three HPI registers. HPI.HCNTL0 is selected
when the Parallel Port Mode bit field of the External Bus Selection Register
is set to 10 or 11.
HPI.HCNTL0
HPI.HCNTL0
EMIF chip select for memory space CE3, general-purpose IO11, or HPI
control input 1. This pin serves in one of three functions: EMIF chip-select
C7
I/O/Z for memory space CE3 (EMIF.CE3), general-purpose IO11 (GPIO11), or
HPI control input 1 (HPI.HCNTL1). The initial state of this pin depends on
the GPIO0 pin. See Section 3.5.1 for more information.
GPIO0 = 1:
Output,
Active-low EMIF chip select for memory space CE3. EMIF.CE3 is selected
EMIF.CE3
EMIF.CE3
GPIO11
O/Z
I/O/Z
I
when the Parallel Port Mode bit field is of the External Bus Selection
Register set to 00 or 01.
BK
GPIO0 = 0:
Input,
General-purpose IO11. GPIO11 is selected when the Parallel Port Mode
bit field is set to 10.
HPI.HCNTL1
HPI control input 1. This pin, in conjunction with HPI.HCNTL0, selects a
host access to one of the three HPI registers. The HPI.HCNTL1 mode is
selected when the Parallel Port Mode bit field is set to 11.
HPI.HCNTL1
†
I = Input, O = Output, S = Supply, Hi-Z = High-impedance
BK = bus keeper (the bus keeper maintains the previous voltage level during reset or while the output pin is not driven), PU = pullup,
PD = pulldown, H = hysteresis input buffer, FS = fail-safe buffer
‡
20
SPRS245C
April 2004 − Revised January 2005
Introduction
Table 2−3. Signal Descriptions (Continued)
TERMINAL MULTIPLEXED
RESET
CONDITION
†
‡
I/O/Z
FUNCTION
BK
NAME
SIGNAL NAME
PARALLEL BUS (CONTINUED)
EMIF byte enable 0 control or HPI byte identification. This pin serves in one
of two functions: EMIF byte enable 0 control (EMIF.BE0) or HPI byte
identification (HPI.HBE0). The initial state of this pin depends on the
GPIO0 pin. See Section 3.5.1 for more information.
C8
I/O/Z
GPIO0 = 1:
Output,
EMIF.BE0
Active-low EMIF byte enable 0 control. EMIF.BE0 is selected when the
Parallel Port Mode bit field of the External Bus Selection Register is set to
00 or 01.
BK
EMIF.BE0
HPI.HBE0
O/Z
I
GPIO0 = 0:
Input,
HPI byte identification. This pin, in conjunction with HPI.HBE1, identifies
the first or second byte of the transfer. HPI.HBE0 is selected when the
Parallel Port Mode bit field is set to 10 or 11.
HPI.HBE0
EMIF byte enable 1 control or HPI byte identification. This pin serves in one
of two functions: EMIF byte enable 1 control (EMIF.BE1) or HPI byte
identification (HPI.HBE1). The initial state of this pin depends on the
GPIO0 pin. See Section 3.5.1 for more information.
C9
I/O/Z
GPIO0 = 1:
Output,
EMIF.BE1
Active-low EMIF byte enable 1 control. EMIF.BE1 is selected when the
Parallel Port Mode bit field of the External Bus Selection Register is set to
00 or 01.
BK
EMIF.BE1
HPI.HBE1
O/Z
I
GPIO0 = 0:
Input,
HPI byte identification. This pin, in conjunction with HPI.HBE0, identifies
the first or second byte of the transfer. HPI.HBE1 is selected when the
Parallel Port Mode bit field is set to 10 or 11.
HPI.HBE1
EMIF SDRAM row strobe, HPI address strobe, or general-purpose IO12.
This pin serves in one of three functions: EMIF SDRAM row strobe
C10
I/O/Z (EMIF.SDRAS), HPI address strobe (HPI.HAS), or general-purpose IO12
(GPIO12). The initial state of this pin depends on the GPIO0 pin. See
Section 3.5.1 for more information.
GPIO0 = 1:
Output,
Active-low EMIF SDRAM row strobe. EMIF.SDRAS is selected when the
EMIF.SDRAS
EMIF.SDRAS
O/Z
Parallel Port Mode bit field of the External Bus Selection Register is set to
00 or 01.
BK
GPIO0 = 0:
Input,
Active-low HPI address strobe. This signal latches the address in the HPIA
register in the HPI Multiplexed mode. HPI.HAS is selected when the
Parallel Port Mode bit field is set to 11.
HPI.HAS
HPI.HAS
GPIO12
I
General-purpose IO12. GPIO12 is selected when the Parallel Port Mode
bit field is set to 10.
I/O/Z
†
I = Input, O = Output, S = Supply, Hi-Z = High-impedance
BK = bus keeper (the bus keeper maintains the previous voltage level during reset or while the output pin is not driven), PU = pullup,
PD = pulldown, H = hysteresis input buffer, FS = fail-safe buffer
‡
21
April 2004 − Revised January 2005
SPRS245C
Introduction
Table 2−3. Signal Descriptions (Continued)
TERMINAL MULTIPLEXED
RESET
CONDITION
†
‡
I/O/Z
FUNCTION
BK
NAME
SIGNAL NAME
PARALLEL BUS (CONTINUED)
EMIF SDRAM column strobe or HPI chip select input. This pin serves in
one of two functions: EMIF SDRAM column strobe (EMIF.SDCAS) or HPI
chip select input (HPI.HCS). The initial state of this pin depends on the
GPIO0 pin. See Section 3.5.1 for more information.
C11
I/O/Z
GPIO0 = 1:
Output,
EMIF.SDCAS
Active-low EMIF SDRAM column strobe. EMIF.SDCAS is selected when
the Parallel Port Mode bit field of the External Bus Selection Register is set
to 00 or 01.
BK
EMIF.SDCAS
HPI.HCS
O/Z
I
GPIO0 = 0:
Input,
HPI Chip Select Input. HPI.HCS is the select input for the HPI and must be
driven low during accesses. HPI.HCS is selected when the Parallel Port
Mode bit field is set to 10 or 11.
HPI.HCS
EMIF SDRAM write enable or HPI Data Strobe 1 input. This pin serves in
one of two functions: EMIF SDRAM write enable (EMIF.SDWE) or HPI
data strobe 1 (HPI.HDS1). The initial state of this pin depends on the
GPIO0 pin. See Section 3.5.1 for more information.
GPIO0 = 1:
Output,
C12
I/O/Z
EMIF.SDWE
EMIF SDRAM write enable. EMIF. SDWE is selected when the Parallel
Port Mode bit field of the External Bus Selection Register is set to 00 or 01.
BK
EMIF.SDWE
HPI.HDS1
O/Z
I
GPIO0 = 0:
Input,
HPI Data Strobe 1 Input. HPI.HDS1 is driven by the host read or write
strobes to control the transfer. HPI.HDS1 is selected when the Parallel
Port Mode bit field is set to 10 or 11.
HPI.HDS1
SDRAM A10 address line or general-purpose IO13. This pin serves in one
of two functions: SDRAM A10 address line (EMIF.SDA10) or
general-purpose IO13 (GPIO13). The initial state of this pin depends on
the GPIO0 pin. See Section 3.5.1 for more information.
C13
I/O/Z
GPIO0 = 1:
Output,
SDRAM A10 address line. Address line/autoprecharge disable for
SDRAM memory. Serves as a row address bit (logically equivalent to A12)
during ACTV commands and also disables the autoprecharging function
of SDRAM during read or write operations. EMIF.SDA10 is selected when
the Parallel Port Mode bit field of the External Bus Selection Register is set
to 00 or 01.
EMIF.SDA10
BK
EMIF.SDA10
GPIO13
O/Z
GPIO0 = 0:
Input,
GPIO13
General-purpose IO13. GPIO13 is selected when the Parallel Port Mode
bit field is set to 10 or 11.
I/O/Z
Memory interface clock for SDRAM, HPI Data Strobe 2 input, or
general-purpose IO14. This pin serves in one of two functions: memory
C14
I/O/Z interface clock for SDRAM (EMIF.CLKMEM) or HPI data strobe 2
(HPI.HDS2). The initial state of this pin depends on the GPIO0 pin. See
Section 3.5.1 for more information.
GPIO0 = 1:
Output,
EMIF.CLKMEM
Memory interface clock for SDRAM. EMIF.CLKMEM is selected when the
BK
EMIF.CLKMEM
HPI.HDS2
O/Z
I
Parallel Port Mode bit field of the External Bus Selection Register is set to
00 or 01.
GPIO0 = 0:
Input,
HPI.HDS2
HPI Data Strobe 2 Input. HPI.HDS2 is driven by the host read or write
strobes to control the transfer. HPI.HDS2 is selected when the Parallel
Port Mode bit field is set to 10 or 11.
†
I = Input, O = Output, S = Supply, Hi-Z = High-impedance
BK = bus keeper (the bus keeper maintains the previous voltage level during reset or while the output pin is not driven), PU = pullup,
PD = pulldown, H = hysteresis input buffer, FS = fail-safe buffer
‡
22
SPRS245C
April 2004 − Revised January 2005
Introduction
Table 2−3. Signal Descriptions (Continued)
TERMINAL MULTIPLEXED
RESET
CONDITION
†
‡
I/O/Z
FUNCTION
BK
NAME
SIGNAL NAME
INTERRUPT AND RESET PINS
Active-low external user interrupt inputs. INT[4:0] are maskable and are
prioritized by the interrupt enable register (IER) and the interrupt mode bit.
INT[4:0]
I
H, FS
H, FS
Input
Input
Active-low reset. RESET causes the digital signal processor (DSP) to
terminate execution and forces the program counter to FF8000h. When
RESET is brought to a high level, execution begins at location FF8000h of
program memory. RESET affects various registers and status bits. Use an
external pullup resistor on this pin.
RESET
I
BIT I/O SIGNALS
7-bit (LQFP package) or 8-bit (BGA package) Input/Output lines that can
be individually configured as inputs or outputs, and also individually set or
GPIO[7:6,4:0] (LQFP)
GPIO[7:0] (BGA)
BK
(GPIO5
only)
I/O/Z reset when configured as outputs. At reset, these pins are configured as
inputs. After reset, the on-chip bootloader samples GPIO[3:0] to
determine the boot mode selected.
Input
H
SDRAM CKE signal. The GPIO4 pin can be configured to serve as
(except
GPIO5)
SDRAM CKE pin by setting the following bits in the External Bus Selection
Input
EMIF.CKE
(GPIO4)
O/Z
Register: CKE SEL = 1 and CKE EN = 1. In default mode, this pin serves as
(GPIO4)
GPIO4.
External flag. XF is set high by the BSET XF instruction, set low by BCLR
XF instruction or by loading ST1. XF is used for signaling other processors
XF
O/Z
in multiprocessor configurations or used as a general-purpose output pin.
XF goes into the high-impedance state when OFF is low, and is set high
following reset.
Output
SDRAM CKE signal. The XF pin can be configured to serve as SDRAM
CKE pin by setting the following bits in the External Bus Selection Register:
CKE SEL = 0 and CKE EN = 1. In default mode, this pin serves as XF.
Output
(XF)
EMIF.CKE
O/Z
O/Z
OSCILLATOR/CLOCK SIGNALS
DSP clock output signal. CLKOUT cycles at the machine-cycle rate of the
CPU. CLKOUT goes into high-impedance state when OFF is low.
CLKOUT
Output
System clock/oscillator input. If the internal oscillator is not being used,
X2/CLKIN functions as the clock input.
Oscillator
Input
NOTE: In CLKGEN domain idle (OSC IDLE) mode, this pin becomes
output and is driven low to stop external crystals (if used) from
oscillating or an external clock source from driving the DSP’s
internal logic.
X2/CLKIN
I/O
Output pin from the internal system oscillator for the crystal. If the internal
oscillator is not used, X1 should be left unconnected. X1 does not go into
the high-impedance state when OFF is low.
Oscillator
Output
X1
O
†
I = Input, O = Output, S = Supply, Hi-Z = High-impedance
BK = bus keeper (the bus keeper maintains the previous voltage level during reset or while the output pin is not driven), PU = pullup,
PD = pulldown, H = hysteresis input buffer, FS = fail-safe buffer
‡
23
April 2004 − Revised January 2005
SPRS245C
Introduction
Table 2−3. Signal Descriptions (Continued)
TERMINAL MULTIPLEXED
RESET
CONDITION
†
‡
I/O/Z
FUNCTION
BK
NAME
SIGNAL NAME
TIMER SIGNALS
Timer0 Input/Output. When output, TIN/TOUT0 signals a pulse or a
change of state when the on-chip timer counts down past zero. When
input, TIN/TOUT0 provides the clock source for the internal timer module.
At reset, this pin is configured as an input.
TIN/TOUT0
I/O/Z
H
Input
NOTE: Only the Timer0 signal is brought out. The Timer1 signal is
terminated internally and is not available for external use.
REAL-TIME CLOCK
Real-Time Clock Oscillator input
Real-Time Clock Oscillator output
RTCINX1
RTCINX2
I
Input
O
Output
2
I C
2
SDA
SCL
I/O/Z I C (bidirectional) data. At reset, this pin is in high-impedance mode.
H
H
Hi-Z
Hi-Z
2
I/O/Z I C (bidirectional) clock. At reset, this pin is in high-impedance mode.
MULTICHANNEL BUFFERED SERIAL PORTS SIGNALS
McBSP0 receive clock. CLKR0 serves as the serial shift clock for the serial
CLKR0
DR0
I/O/Z
H
Hi-Z
Input
Hi-Z
port receiver. At reset, this pin is in high-impedance mode.
I
McBSP0 receive data
FS
McBSP0 receive frame synchronization. The FSR0 pulse initiates the data
receive process over DR0. At reset, this pin is in high-impedance mode.
FSR0
I/O/Z
McBSP0 transmit clock. CLKX0 serves as the serial shift clock for the
serial port transmitter. The CLKX0 pin is configured as input after reset.
CLKX0
DX0
I/O/Z
O/Z
H
Input
Hi-Z
McBSP0 transmit data. DX0 is placed in the high-impedance state when
not transmitting, when RESET is asserted, or when OFF is low.
McBSP0 transmit frame synchronization. The FSX0 pulse initiates the
data transmit process over DX0. Configured as an input following reset.
FSX0
I/O/Z
Input
McBSP1 receive clock. CLKR1 serves as the serial shift clock for the serial
port receiver.
CLKR1
DR1
I/Z
I/Z
I/Z
H
Input
Input
Input
McBSP1 serial data receive
McBSP1 receive frame synchronization. The FSR1 pulse initiates the data
receive process over DR1.
FSR1
McBSP1 serial data transmit. DX1 is placed in the high-impedance state
when not transmitting, when RESET is asserted, or when OFF is low.
DX1
O/Z
I/O/Z
I/O/Z
BK
H
Hi-Z
Input
Input
McBSP1 transmit clock. CLKX1 serves as the serial shift clock for the
serial port transmitter. The CLKX1 pin is configured as input after reset.
CLKX1
McBSP1 transmit frame synchronization. The FSX1 pulse initiates the
data transmit process over DX1. Configured as an input following reset.
FSX1
†
I = Input, O = Output, S = Supply, Hi-Z = High-impedance
BK = bus keeper (the bus keeper maintains the previous voltage level during reset or while the output pin is not driven), PU = pullup,
PD = pulldown, H = hysteresis input buffer, FS = fail-safe buffer
‡
24
SPRS245C
April 2004 − Revised January 2005
Introduction
Table 2−3. Signal Descriptions (Continued)
TERMINAL MULTIPLEXED
NAME SIGNAL NAME
RESET
CONDITION
†
‡
I/O/Z
FUNCTION
BK
MULTICHANNEL BUFFERED SERIAL PORTS SIGNALS (CONTINUED)
McBSP2 receive clock. CLKR2 serves as the serial shift clock for the serial
CLKR2
I
H
Input
Input
Input
port receiver.
DR2
I
I
McBSP2 serial data receive
McBSP2 receive frame synchronization. The FSR2 pulse initiates the data
receive process over DR2.
FSR2
McBSP2 serial data transmit. DX2 is placed in the high-impedance state
when not transmitting, when RESET is asserted, or when OFF is low.
DX2
O/Z
I/O/Z
I/O/Z
BK
H
Hi-Z
Input
Input
McBSP2 transmit clock. CLKX2 serves as the serial shift clock for the
serial port transmitter. The CLKX2 pin is configured as input after reset.
CLKX2
FSX2
McBSP2 frame synchronization. The FSX2 pulse initiates the data
transmit process over DX2. FSX2 is configured as an input following reset.
TEST/EMULATION PINS
IEEE standard 1149.1 test clock. TCK is normally a free-running clock
signal with a 50% duty cycle. The changes on test access port (TAP) of
input signals TMS and TDI are clocked into the TAP controller, instruction
register, or selected test data register on the rising edge of TCK. Changes
at the TAP output signal (TDO) occur on the falling edge of TCK.
PU
H
TCK
I
Input
IEEE standard 1149.1 test data input. Pin with internal pullup device. TDI is
clocked into the selected register (instruction or data) on a rising edge of
TCK.
TDI
I
O/Z
I
PU
Input
Hi-Z
IEEE standard 1149.1 test data output. The contents of the selected
register (instruction or data) are shifted out of TDO on the falling edge of
TCK. TDO is in the high-impedance state except when the scanning of
data is in progress.
TDO
TMS
IEEE standard 1149.1 test mode select. Pin with internal pullup device.
This serial control input is clocked into the TAP controller on the rising edge
of TCK.
PU
Input
IEEE standard 1149.1 test reset. TRST, when high, gives the IEEE
standard 1149.1 scan system control of the operations of the device. If
TRST is not connected or driven low, the device operates in its functional
mode, and the IEEE standard 1149.1 signals are ignored. This pin has an
internal pulldown.
PD
FS
TRST
EMU0
I
Input
Input
Emulator 0 pin. When TRST is driven low, EMU0 must be high for
activation of the OFF condition. When TRST is driven high, EMU0 is used
as an interrupt to or from the emulator system and is defined as I/O by way
of the IEEE standard 1149.1 scan system.
I/O/Z
PU
PU
Emulator 1 pin/disable all outputs. When TRST is driven high, EMU1/OFF
is used as an interrupt to or from the emulator system and is defined as I/O
by way of IEEE standard 1149.1 scan system. When TRST is driven low,
EMU1/OFF is configured as OFF. The EMU1/OFF signal, when
active-low, puts all output drivers into the high-impedance state. Note that
OFF is used exclusively for testing and emulation purposes (not for
multiprocessing applications). Therefore, for the OFF condition, the
following apply: TRST = low, EMU0 = high, EMU1/OFF = low
EMU1/OFF
I/O/Z
Input
†
I = Input, O = Output, S = Supply, Hi-Z = High-impedance
BK = bus keeper (the bus keeper maintains the previous voltage level during reset or while the output pin is not driven), PU = pullup,
PD = pulldown, H = hysteresis input buffer, FS = fail-safe buffer
‡
25
April 2004 − Revised January 2005
SPRS245C
Introduction
Table 2−3. Signal Descriptions (Continued)
TERMINAL MULTIPLEXED
RESET
CONDITION
†
‡
I/O/Z
FUNCTION
BK
NAME
SIGNAL NAME
SUPPLY PINS
CV
S
S
Digital Power, + V . Dedicated power supply for the core CPU.
DD
DD
DD
DV
Digital Power, + V . Dedicated power supply for the I/O pins.
DD
Digital Power, + V . Dedicated power supply for the I/O pins of the RTC
DD
RDV
RCV
S
DD
DD
module.
S
S
Digital Power, + V . Dedicated power supply for the RTC module
DD
V
Digital Ground. Dedicated ground for the I/O and core pins.
RESERVED
SS
RSVD1
RSVD2
Reserved. Must be pulled up. Use 10-kΩ resistor.
Reserved. Must be pulled low. Use 10-kΩ resistor.
MISCELLANEOUS
NC
No connection
†
I = Input, O = Output, S = Supply, Hi-Z = High-impedance
BK = bus keeper (the bus keeper maintains the previous voltage level during reset or while the output pin is not driven), PU = pullup,
PD = pulldown, H = hysteresis input buffer, FS = fail-safe buffer
‡
26
SPRS245C
April 2004 − Revised January 2005
Functional Overview
3
Functional Overview
The following functional overview is based on the block diagram in Figure 3−1.
†
†
7/8
5
†
Number of pins determined by package type.
Figure 3−1. Block Diagram of the TMS320VC5503
27
April 2004 − Revised January 2005
SPRS245C
Functional Overview
3.1 Memory
The 5503 supports a unified memory map (program and data accesses are made to the same physical space).
The total on-chip memory is 128K bytes (32K 16-bit words of RAM and 32K 16-bit words of ROM).
3.1.1 On-Chip Dual-Access RAM (DARAM)
The DARAM is located in the byte address range 000000h−00FFFFh and is composed of eight blocks of
8K bytes each (see Table 3−1). Each DARAM block can perform two accesses per cycle (two reads, two
writes, or a read and a write). DARAM can be accessed by the internal program, data, or DMA buses. The
HPI can only access the first four (32K bytes) DARAM blocks.
Table 3−1. DARAM Blocks
BYTE ADDRESS RANGE
000000h − 001FFFh
002000h − 003FFFh
004000h − 005FFFh
006000h − 007FFFh
008000h − 009FFFh
00A000h − 00BFFFh
00C000h − 00DFFFh
00E000h − 00FFFFh
MEMORY BLOCK
†
DARAM 0 (HPI accessible)
DARAM 1 (HPI accessible)
DARAM 2 (HPI accessible)
DARAM 3 (HPI accessible)
DARAM 4
DARAM 5
DARAM 6
DARAM 7
†
First 192 bytes are reserved for Memory-Mapped Registers (MMRs).
3.1.2 On-Chip Read-Only Memory (ROM)
The one-wait-state ROM is located at the byte address range FF0000h−FFFFFFh, for a total of 64K bytes of
ROM. The ROM address space can be mapped by software to the external memory or to the internal ROM.
The standard 5503 device includes a bootloader program resident in the ROM. When the MPNMC bit field
of the ST3 status register is set through software, the on-chip ROM is disabled and not present in the memory
map, and byte address range FF0000h−FFFFFFh is directed to external memory space. A hardware reset
always clears the MPNMC bit, so it is not possible to disable the ROM at reset. However, the software reset
instruction does not affect the MPNMC bit. The on-chip ROM can be accessed by the program, data, or DMA
buses. The first 16-bit word access to ROM requires three cycles. Subsequent accesses require two cycles
per 16-bit word.
28
SPRS245C
April 2004 − Revised January 2005
Functional Overview
3.1.3 Memory Maps
3.1.3.1 PGE Package Memory Map
The PGE package features 14 address bits representing 16K-byte linear address for asynchronous memories
per CE space. Due to address row/column multiplexing, address reach for SDRAM devices is 4M bytes for
each CE space. The largest SDRAM device that can be used with the 5503 in a PGE package is 128M-bit
SDRAM.
Byte Address
(Hex)†
Memory Blocks
MMR (Reserved)
Block Size
000000
0000C0
DARAM / HPI Access
(32K − 192) Bytes
32K Bytes
008000
010000
DARAM‡
Reserved
040000
400000
800000
C00000
FF0000
16K Bytes − Asynchronous
External§ − CE0
External§ − CE1
4M Bytes − 64K Bytes SDRAM¶
16K Bytes − Asynchronous
4M Bytes − SDRAM
16K Bytes − Asynchronous
4M Bytes − SDRAM
External§ − CE2
External§ − CE3
16K Bytes − Asynchronous
4M Bytes − SDRAM (MPNMC = 1)
4M Bytes − 64K Bytes if internal ROM selected (MPNMC = 0)
External§ − CE3
(if MPNMC=1)
ROM#
(if MPNMC=0)
64K Bytes
FFFFFF
†
Address shown represents the first byte address in each block.
‡
§
Dual-access RAM (DARAM): two accesses per cycle per block, 8 blocks of 8K bytes.
External memory spaces are selected by the chip-enable signal shown (CE[0:3]). Supported memory types include: asynchronous static
RAM (SRAM) and synchronous DRAM (SDRAM).
The minus 64K bytes consists of 32K-byte DARAM/HPI access and 32K-byte DARAM.
Read-only memory (ROM): one access every two cycles.
¶
#
Figure 3−2. TMS320VC5503 Memory Map (PGE Package)
29
April 2004 − Revised January 2005
SPRS245C
Functional Overview
3.1.3.2 GHH Package Memory Map
The GHH package features 21 address bits representing 2M-byte linear address for asynchronous memories
per CE space. Due to address row/column multiplexing, address reach for SDRAM devices is 4M bytes for
each CE space. The largest SDRAM device that can be used with the 5503 in a GHH package is 128M-bit
SDRAM.
Byte Address
(Hex)†
Memory Blocks
MMR (Reserved)
Block Size
000000
0000C0
008000
DARAM / HPI Access
(32K − 192) Bytes
32K Bytes
DARAM‡
Reserved
010000
040000
400000
800000
C00000
FF0000
2M Bytes − Asynchronous
External§ − CE0
External§ − CE1
4M Bytes − 64K Bytes SDRAM¶
2M Bytes − Asynchronous
4M Bytes − SDRAM
2M Bytes − Asynchronous
4M Bytes − SDRAM
External§ − CE2
External§ − CE3
2M Bytes − Asynchronous
4M Bytes − SDRAM (MPNMC = 1)
4M Bytes − 64K Bytes if internal ROM selected (MPNMC = 0)
External§ − CE3
(if MPNMC=1)
ROM#
(if MPNMC=0)
64K Bytes
FFFFFF
†
Address shown represents the first byte address in each block.
‡
§
Dual-access RAM (DARAM): two accesses per cycle per block, 8 blocks of 8K bytes.
External memory spaces are selected by the chip-enable signal shown (CE[0:3]). Supported memory types include: asynchronous static
RAM (SRAM) and synchronous DRAM (SDRAM).
The minus 64K bytes consists of 32K-byte DARAM/HPI access and 32K-byte DARAM.
Read-only memory (ROM): one access every two cycles.
¶
#
Figure 3−3. TMS320VC5503 Memory Map (GHH Package)
30
SPRS245C
April 2004 − Revised January 2005
Functional Overview
3.1.4 Boot Configuration
The on-chip bootloader provides a method to transfer application code and tables from an external source to
the on-chip RAM memory at power up. These options include:
•
•
•
•
•
•
Enhanced host-port interface (HPI) in multiplexed or nonmultiplexed mode
External asynchronous memory boot (via the EMIF) from 8-bit-wide or 16-bit-wide memory
Serial port boot (from McBSP0) with 8-bit or 16-bit data length
Serial EPROM boot (from McBSP0) supporting EPROMs with 16-bit or 24-bit address
2
I C EEPROM
Direct execution from external 16-bit-wide asynchronous memory
External pins select the boot configuration. The values of GPIO[3:0] are sampled, following reset, upon
execution of the on-chip bootloader code. It is not possible to disable the bootloader at reset because the 5503
always starts execution from the on-chip ROM following a hardware reset. A summary of boot configurations
is shown in Table 3−2. For more information on using the bootloader, see the Using the
TMS320VC5503/VC5507/VC5509/VC5509ABootloader application report (literature number SPRA375).
Table 3−2. Boot Configuration Summary
GPIO0
GPIO3
GPIO2
BOOT MODE PROCESS
GPIO1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Reserved
Serial (SPI) EPROM Boot (24-bit address) via McBSP0
Reserved
2
I C EEPROM (7-bit address)
Reserved
HPI – multiplexed mode
HPI – nonmultiplexed mode
Reserved
Execute from 16-bit-wide asynchronous memory (on CE1 space)
Serial (SPI) EPROM Boot (16-bit address) via McBSP0
8-bit asynchronous memory (on CE1 space)
16-bit asynchronous memory (on CE1 space)
Reserved
Reserved
Standard serial boot via McBSP0 (16-bit data)
Standard serial boot via McBSP0 (8-bit data)
31
April 2004 − Revised January 2005
SPRS245C
Functional Overview
3.2 Peripherals
The 5503 supports the following peripherals:
•
A Configurable Parallel External Interface supporting either:
−
−
16-bit external memory interface (EMIF) for asynchronous memory and/or SDRAM
16-bit enhanced host-port interface (HPI)
•
•
•
•
•
•
•
•
A six-channel direct memory access (DMA) controller
A programmable phase-locked loop clock generator
Two 20-bit timers
Watchdog Timer
Three multichannel buffered serial ports (McBSPs)
Seven (LQFP) or Eight (BGA) configurable general-purpose I/O pins
2
2
I C multi-master and slave interface (I C compatible except, no fail-safe I/O buffers)
Real-time clock with crystal input, separate clock domain and supply pins
For detailed information on the C55x DSP peripherals, see the following documents:
•
•
TMS320C55x DSP Functional Overview (literature number SPRU312)
TMS320C55x DSP Peripherals Overview Reference Guide (literature number SPRU317)
3.3 Direct Memory Access (DMA) Controller
The 5503 DMA provides the following features:
•
Three standard ports, one for each of the following data resources: DARAM, Peripherals, and External
Memory
•
•
•
•
Six channels, which allow the DMA controller to track the context of six independent DMA channels
Programmable low/high priority for each DMA channel
One interrupt for each DMA channel
Event synchronization. DMA transfers in each channel can be dependent on the occurrence of selected
events.
•
•
Programmable address modification for source and destination addresses
Dedicated Idle Domain allows the DMA controller to be placed in a low-power (idle) state under software
control.
•
Dedicated DMA channel used by the HPI to access internal memory (DARAM)
The 5503 DMA controller allows transfers to be synchronized to selected events. The 5503 supports
15 separate sync events and each channel can be tied to separate sync events independent of the other
channels. Sync events are selected by programming the SYNC field in the channel-specific DMA Channel
Control Register (DMA_CCR).
32
SPRS245C
April 2004 − Revised January 2005
Functional Overview
3.3.1 DMA Channel Control Register (DMA_CCR)
The channel control register (DMA_CCR) bit layouts are shown in Figure 3−4.
15
14
13
12
11
10
Reserved
R, 0
9
8
DST AMODE
R/W, 00
SRC AMODE
R/W, 00
END PROG
R/W, 0
REPEAT
R/W, 0
AUTO INIT
R/W, 0
7
6
5
4
0
EN
PRIO
FS
SYNC
R/W, 0
R/W, 0
R/W, 0
R/W, 00000
LEGEND: R = Read, W = Write, n = value after reset
Figure 3−4. DMA_CCR Bit Locations
The SYNC[4:0] bits specify the event that can initiate the DMA transfer for the corresponding DMA channel.
The five bits allow several configurations as listed in Table 3−3. The bits are set to zero upon reset. For those
synchronization modes with more than one peripheral listed, the Serial Port Mode bit field of the External Bus
Selection Register dictates which peripheral event is actually connected to the DMA input.
Table 3−3. Synchronization Control Function
SYNC FIELD IN
DMA_CCR
SYNCHRONIZATION MODE
00000b
00001b
00010b
00011b
00100b
00101b
00110b
00111b
01000b
01001b
01010b
01011b
01100b
01101b
01110b
01111b
10000b
10001b
10010b
10011b
10100b
No event synchronized
McBSP 0 Receive Event (REVT0)
McBSP 0 Transmit Event (XEVT0)
Reserved. These bits should always be written with 0.
Reserved. These bits should always be written with 0.
McBSP1 Receive Event (REVT1)
McBSP1 Transmit Event (XEVT1)
Reserved. These bits should always be written with 0.
Reserved. These bits should always be written with 0.
McBSP2 Receive Event (REVT2)
McBSP2 Transmit Event (XEVT2)
Reserved. These bits should always be written with 0.
Reserved. These bits should always be written with 0.
Timer 0 Interrupt Event
Timer 1 Interrupt Event
External Interrupt 0
External Interrupt 1
External Interrupt 2
External Interrupt 3
2
†
External Interrupt 4 / I C Receive Event (REVTI2C)
2
I C Transmit Event (XEVTI2C)
Other values
Reserved (Do not use these values)
†
2
The I C receive event (REVTI2C) and external interrupt 4 (INT4) share a synchronization input to the DMA. When the SYNC field of the
DMA_CCR is set to 10011b, the logical OR of these two sources is used for DMA synchronization.
33
April 2004 − Revised January 2005
SPRS245C
Functional Overview
3.4 I2C Interface
2
2
The TMS320VC5503 includes an I C serial port. The I C port supports:
2
•
•
•
•
•
Compatible with Philips I C Specification Revision 2.1 (January 2000)
Operates at 100 Kbps or 400 Kbps
7-bit addressing mode
Master (transmit/receive) and slave (transmit/receive) modes of operation
Events: DMA, interrupt, or polling
2
The I C module clock must be in the range from 7 MHz to 12 MHz. This is necessary for proper operation of
2
2
the I C module. With the I C module clock in this range, the noise filters on the SDA and SCL pins suppress
2
noise that has a duration of 50 ns or shorter. The I C module clock is derived from the DSP clock divided by
a programmable prescaler.
NOTE: I/O buffers are not fail-safe. The SDA and SCL pins could potentially draw current if the
2
device is powered down and SDA and SCL are driven by other devices connected to the I C bus.
3.5 Configurable External Buses
The 5503 offers combinations of configurations for its external parallel port. This allows the system designer
to choose the appropriate media interface for its application without the need of a large-pin-count package.
The External Bus Selection Register controls the routing of the parallel port signals.
34
SPRS245C
April 2004 − Revised January 2005
Functional Overview
3.5.1 External Bus Selection Register (EBSR)
The External Bus Selection Register determines the mapping of the 14 (LQFP) or 21 (BGA) address signals,
16 data signals, and 15 control signals of the external parallel port. The External Bus Selection Register is
memory-mapped at port address 0x6C00. Once the bit fields of this register are changed, the routing of the
signals takes place on the next CPU clock cycle.
The reset value of the parallel port mode bit field is determined by the state of the GPIO0 pin at reset. If GPIO0
is high at reset, the full EMIF mode is enabled and the parallel port mode bit field is set to 01. If GPIO0 is low
at reset, the HPI multiplexed mode is enabled and the parallel port mode bit field is set to 11. After reset, the
parallel port should be selected to function in either EMIF mode or HPI mode. Dynamic switching of the parallel
port, once configured, is not recommended.
15
14
OSC Disable
R/W, 0
13
HIDL
R/W, 0
5
12
11
10
HOLD
R/W, 0
2
9
8
CKE SEL
R/W, 0
0
CLKOUT
Disable
BKE
SR STAT
R/W, 0
HOLDA
R/W, 1
1
R/W, 0
7
R/W, 0
6
Reserved
(see NOTE)
Parallel Port
CKE EN
SR CMD
Mode
R/W, 01 if GPIO0 = 1
11 if GPIO0 = 0
R/W, 0
R/W, 0
R, 0000
LEGEND: R = Read, W = Write, n = value after reset
NOTE: These bits are Reserved and must be kept as 0000 during any writes to EBSR.
Figure 3−5. External Bus Selection Register
Table 3−4. External Bus Selection Register Bit Field Description
BITS
DESCRIPTION
CLKOUT disable.
15
CLKOUT disable = 0:
CLKOUT disable = 1:
CLKOUT enabled
CLKOUT disabled
Oscillator disable. Works with IDLE instruction to put the clock generation domain into IDLE mode.
14
13
OSC disable = 0:
OSC disable = 1:
Oscillator enabled
Oscillator disabled
Host mode idle bit. (Applicable only if the parallel bus is configured as EHPI.)
When the parallel bus is set to EHPI mode, the clock domain is not allowed to go to idle, so a host processor can
access the DSP internal memory. The HIDL bit works around this restriction and allows the DSP to idle the clock
domain and the EHPI. When the clock domain is in idle, a host processor will not be able to access the DSP
memory.
HIDL = 0:
HIDL = 1:
Host access to DSP enabled. Idling EHPI and clock domain is not allowed.
Idles the HPI and the clock domain upon execution of the IDLE instruction when the parallel
port mode is set to 10 or 11 selecting HPI mode. In addition, bit 4 of the Idle Control Register
must be set to 1 prior to the execution of the IDLE instruction.
†
Bus keeper enable.
12
11
BKE = 0:
BKE = 1:
Bus keeper, pullups/pulldowns enabled
Bus keeper, pullups/pulldowns disabled
SDRAM self-refresh status bit.
SR STAT = 0: SDRAM self-refresh signal is not asserted.
SR STAT = 1: SDRAM self-refresh signal is asserted
†
Function available when the port or pins configured as input.
35
April 2004 − Revised January 2005
SPRS245C
Functional Overview
Table 3−4. External Bus Selection Register Bit Field Description (Continued)
BITS
DESCRIPTION
EMIF hold
10
HOLD = 0:
HOLD = 1:
DSP drives the external memory bus
Request the external memory bus to be placed in high-impedance so that another device can
drive the memory bus
EMIF hold acknowledge.
HOLDA = 0: DSP indicates that a hold request on the external memory bus has occured, the EMIF
completed any pending external bus activity, and placed the external memory bus signals in
high-impedance state (address bus, data bus, CE[3:0], AOE, AWE, ARE, SDRAS, SDCAS,
SDWE, SDA10, CLKMEM). Once this bit is cleared, an external device can drive the bus.
HOLDA = 1: No hold acknowledge
9
SDRAM CKE pin selection bit.
8
7
CKE SEL = 0: Use XF for SDRAM CKE signal
CKE SEL = 1: Use GPIO.4 for SDRAM CKE signal
SDRAM CKE enable bit.
CKE EN = 0: XF or GPIO.4 operates in normal mode
CKE EN = 1: Based on the CKE SEL bit, either XF or GPIO.4 drives the SDRAM CKE pin
SDRAM self-refresh command.
6
SR CMD = 0: EMIF will not issue a SDRAM self-refresh command
SR CMD = 1: EMIF will issue a SDRAM self-refresh command
5−2
Reserved. Must be kept as 0000 during any writes to EBSR.
Parallel port mode. EMIF/HPI/GPIO Mode. Determines the mode of the parallel port.
Parallel Port Mode = 00: Data EMIF mode. The 16 EMIF data signals and 13 EMIF control signals are
routed to the corresponding external parallel bus data and control signals. The
14 (LQFP) or 16 (BGA) address bus signals can be used as general-purpose I/O
only.
Parallel Port Mode = 01: Full EMIF mode. The 14 (LQFP) or 21 (BGA) address signals, 16 data signals, and
15 control signals are routed to the corresponding external parallel bus address,
data, and control signals.
Parallel Port Mode = 10: Non-multiplexed HPI mode. The HPI is enabled an its 14 address signals,
16 data signals, and 7 control signals are routed to the corresponding address,
data, control signals of the external parallel bus. Moreover, 8 control signals of the
external parallel bus are used as general-purpose I/O.
1−0
Parallel Port Mode = 11: Multiplexed HPI mode. The HPI is enabled and its 16 data signals and
10 control signals are routed to the external parallel bus. In addition, 3 control
signals of the external parallel bus are used as general-purpose I/O. The
14 (LQFP) or 16 (BGA) external parallel port address bus signals are used as
general-purpose I/O.
†
Function available when the port or pins configured as input.
36
SPRS245C
April 2004 − Revised January 2005
Functional Overview
3.5.2 Parallel Port
The parallel port of the 5503 consists of 14 (LQFP) or 21 (BGA) address signals, 16 data signals, and 15 control
signals. Its 14 bits for address allow it to access 16K (LQFP) or 2M bytes of external memory when using the
asynchronous SRAM interface. On the other hand, the SDRAM interface can access the whole external
memory space of 16M bytes. The parallel bus supports four different modes:
•
Full EMIF mode: the EMIF with its 14 (LQFP) or 21 address signals, 16 data signals, and 15 control
signals routed to the corresponding external parallel bus address, data, and control signals.
•
Data EMIF mode: the EMIF with its 16 data signals, and 15 control signals routed to the corresponding
external parallel bus data and control signals. The 14 (LQFP) or 16 (BGA) address bus signals can be
used as general-purpose I/O signals only.
•
•
Non-multiplexed HPI mode: the HPI is enabled with its 14 address signals, 16 data signals, and
8 control signals routed to the corresponding address, data, and control signals of the external parallel
bus. Moreover, 7 control signals of the external parallel bus are used as general-purpose I/O.
Multiplexed HPI mode: the HPI is enabled with its 16 data signals and 10 control signals routed to the
external parallel bus. In addition, 5 control signals of the external parallel bus are used as general-purpose
I/O. The external parallel port’s 14 (LQFP) or 16 (BGA) address signals are used as general-purpose I/O.
Table 3−5. TMS320VC5503 Parallel Port Signal Routing
†
†
†
†
Pin Signal
Data EMIF (00)
Full EMIF (01)
Address Bus
EMIF.A[0] (BGA)
Non-Multiplex HPI (10)
Multiplex HPI (11)
A’[0]
A[0]
N/A
N/A
N/A
GPIO.A[0] (LQFP)
GPIO.A[0] (BGA)
GPIO.A[13:1] (LQFP)
GPIO.A[13:1] (BGA)
GPIO.A[15:14] (BGA)
N/A
EMIF.A[0] (LQFP)
HPI.HA[0] (LQFP)
HPI.HA[0] (BGA)
HPI.HA[13:1] (LQFP)
HPI.HA[13:1] (BGA)
N/A
GPIO.A[0] (LQFP)
GPIO.A[0] (BGA)
GPIO.A[13:1] (LQFP)
GPIO.A[13:1] (BGA)
GPIO.A[15:14] (BGA)
N/A
EMIF.A[13:1] (LQFP)
EMIF.A[13:1] (BGA)
EMIF.A[15:14] (BGA)
EMIF.A[20:16] (BGA)
Data Bus
A[13:1]
A[15:14]
‡
A[20:16]
N/A
D[15:0]
EMIF.D[15:0]
EMIF.D[15:0]
Control Bus
EMIF.ARE
HPI.HD[15:0]
HPI.HD[15:0]
C0
C1
EMIF.ARE
EMIF.AOE
GPIO8
HPI.HINT
HPI.HR/W
HPI.HRDY
GPIO9
GPIO8
HPI.HINT
HPI.HR/W
HPI.HRDY
GPIO9
EMIF.AOE
C2
EMIF.AWE
EMIF.ARDY
EMIF.CE0
EMIF.AWE
C3
EMIF.ARDY
C4
EMIF.CE0
C5
EMIF.CE1
EMIF.CE1
GPIO10
GPIO10
C6
EMIF.CE2
EMIF.CE2
HPI.HCNTL0
GPIO11
HPI.HCNTL0
HPI.HCNTL1
HPI.HBE0
HPI.HBE1
HPI.HAS
C7
EMIF.CE3
EMIF.CE3
C8
EMIF.BE0
EMIF.BE0
HPI.HBE0
HPI.HBE1
GPIO12
C9
EMIF.BE1
EMIF.BE1
C10
C11
C12
C13
C14
EMIF.SDRAS
EMIF.SDCAS
EMIF.SDWE
EMIF.SDA10
EMIF.CLKMEM
EMIF.SDRAS
EMIF.SDCAS
EMIF.SDWE
EMIF.SDA10
EMIF.CLKMEM
HPI.HCS
HPI.HDS1
GPIO13
HPI.HCS
HPI.HDS1
GPIO13
HPI.HDS2
HPI.HDS2
†
‡
Represents the Parallel Port Mode bits of the External Bus Selection Register.
A[20:16] of the BGA package always functions as EMIF address pins and they cannot be reconfigured for any other function.
37
April 2004 − Revised January 2005
SPRS245C
Functional Overview
3.5.3 Parallel Port Signal Routing
The 5503 allows access to 16-bit-wide (read and write) or 8-bit-wide (read only) asynchronous memory and
16-bit-wide SDRAM. For 16-bit-wide memories, EMIF.A[0] is kept low and is not used. To provide as many
address pins as possible, the 5503 routes the parallel port signals as shown in Figure 3−6.
Figure 3−6 shows the addition of the A′[0] signal in the BGA package. This pin is used for asynchronous
memory interface only, while the A[0] pin is used with HPI or GPIO. Figure 3−7 summarizes the use of the
parallel port signals for memory interfacing.
EMIF.A[0]
A’[0] (BGA only)
A[0]
GPIO.A[0]
HPI.HA[0]
EMIF.A[13:1]
HPI.HA[13:1]
GPIO.A[13:1]
A[13:1]
EMIF.A[14]
GPIO.A[14]
A[14] (BGA only)
EMIF.A[15]
GPIO.A[15]
A[15] (BGA only)
EMIF.A[20:16]
A[20:16] (BGA only)
Figure 3−6. Parallel Port Signal Routing
38
SPRS245C
April 2004 − Revised January 2005
Functional Overview
16-Bit-Wide Asynchronous Memory
16-Bit-Wide SDRAM
CEx
WE
RE
CS
WE
RE
OE
CEx
CS
CLKMEM
SDRAS
SDCAS
SDWE
BE[1:0]
A[0]
CLK
RAS
16-Bit
Asynchronous
Memory
CAS
OE
5503
LQFP
WE
BE[1:0]
64 MBit or
128 MBit
SDRAM
BE[1:0]
A[13:1]
A[0]
5503
LQFP
DQM[H:L]
BA[1]
BA[0]
A[11]
A[10]
A[9:0]
D[15:0]
A[12:0]
A[13]
A[13]
D[15:0]
D[15:0]
A[12]
SDA10
A[10:1]
D[15:0]
CEx
WE
RE
CS
WE
RE
OE
16-Bit
Asynchronous
Memory
OE
5503
BGA
BE[1:0]
A[20:14]
A[13:1]
D[15:0]
BE[1:0]
A[19:13]
A[12:0]
D[15:0]
CEx
CLKMEM
SDRAS
SDCAS
SDWE
CS
CLK
RAS
CAS
WE
64 MBit or
128 MBit
SDRAM
5503
BGA
BE[1:0]
A[14]
DQM[H:L]
BA[1]
BA[0]
A[11]
A[10]
A[9:0]
D[15:0]
8-Bit-Wide Asynchronous Memory
A[13]
CEx
WE
RE
CS
A[12]
WE
SDA10
A[10:1]
D[15:0]
RE
8-Bit
Asynchronous
Memory
5503
LQFP
OE
OE
BE[1:0]
A[13:0]
D[7:0]
BE[1:0]
A[13:0]
D[7:0]
CEx
WE
RE
CS
WE
RE
OE
OE
8-Bit
Asynchronous
Memory
5503
BGA
BE[1:0]
BE[1:0]
A[20:14]
A[13:1]
A[0]
A[20:14]
A[13:1]
A’[0]
D[7:0]
D[7:0]
Figure 3−7. Parallel Port (EMIF) Signal Interface
39
April 2004 − Revised January 2005
SPRS245C
Functional Overview
3.6 General-Purpose Input/Output (GPIO) Ports
3.6.1 Dedicated General-Purpose I/O
The 5503 provides eight dedicated general-purpose input/output pins, GPIO0−GPIO7. Each pin can be
indepedently configured as an input or an output using the I/O Direction Register (IODIR). The I/O Data
Register (IODATA) is used to monitor the logic state of pins configured as inputs and control the logic state
of pins configured as outputs. See Table 3−25 for address information. The description of the IODIR is shown
in Figure 3−8 and Table 3−6. The description of IODATA is shown in Figure 3−9 and Table 3−7.
To configure a GPIO pin as an input, clear the direction bit that corresponds to the pin in IODIR to 0. To read
the logic state of the input pin, read the corresponding bit in IODATA.
To configure a GPIO pin as an output, set the direction bit that corresponds to the pin in IODIR to 1. To control
the logic state of the output pin, write to the corresponding bit in IODATA.
15
8
7
6
5
4
3
2
1
0
IO5DIR
(BGA)
Reserved
IO7DIR
R/W−0
IO6DIR
R/W−0
IO4DIR
R/W−0
IO3DIR
R/W−0
IO2DIR
R/W−0
IO1DIR
R/W−0
IO0DIR
R/W−0
R−00000000
R/W−0
LEGEND: R = Read, W = Write, n = value after reset
Figure 3−8. I/O Direction Register (IODIR) Bit Layout
Table 3−6. I/O Direction Register (IODIR) Bit Functions
BIT
NO.
BIT
NAME
RESET
VALUE
FUNCTION
15−8
Reserved
0
These bits are reserved and are unaffected by writes.
IOx Direction Control Bit. Controls whether IOx operates as an input or an output.
†
7−0
IOxDIR
0
IOxDIR = 0
IOxDIR = 1
IOx is configured as an input.
IOx is configured as an output.
†
The GPIO5 pin is available on the BGA package only.
40
SPRS245C
April 2004 − Revised January 2005
Functional Overview
15
8
7
6
5
4
3
2
1
0
IO5D
(BGA)
Reserved
IO7D
IO6D
IO4D
IO3D
IO2D
IO1D
IO0D
R−00000000
R/W−pin
R/W−pin
R/W−pin
R/W−pin
R/W−pin
R/W−pin
R/W−pin
R/W−pin
LEGEND: R = Read, W = Write, pin = value present on the pin (IO7−IO0 default to inputs after reset)
Figure 3−9. I/O Data Register (IODATA) Bit Layout
Table 3−7. I/O Data Register (IODATA) Bit Functions
FUNCTION
BIT
NO.
BIT
NAME
RESET
VALUE
15−8
Reserved
0
These bits are reserved and are unaffected by writes.
IOx Data Bit.
If IOx is configured as an input (IOxDIR = 0 in IODIR):
IOxD = 0
IOxD = 1
The signal on the IOx pin is low.
The signal on the IOx pin is high.
†‡
7−0
IOxD
pin
If IOx is configured as an output (IOxDIR = 1 in IODIR):
IOxD = 0
IOxD = 1
Drive the signal on the IOx pin low.
Drive the signal on the IOx pin high.
†
‡
The GPIO5 pin is available on the BGA package only.
pin = value present on the pin (IO7−IO0 default to inputs after reset)
3.6.2 Address Bus General-Purpose I/O
The 16 address signals, EMIF.A[15−0], can also be individually enabled as GPIO when the Parallel Port Mode
bit field of the External Bus Selection Register is set for Data EMIF (00) or Multiplexed EHPI mode (11). These
pins are controlled by three registers: the enable register, AGPIOEN, determines if the pins serve as GPIO
or address (Figure 3−10); the direction register, AGPIODIR, determines if the GPIO enabled pin is an input
or output (Figure 3−11); and the data register, AGPIODATA, determines the logic states of the pins in
general-purpose I/O mode (Figure 3−12).
15
14
13
12
11
10
9
8
AIOEN15
(BGA)
AIOEN14
(BGA)
AIOEN13
R/W, 0
AIOEN12
R/W, 0
AIOEN11
R/W, 0
AIOEN10
R/W, 0
AIOEN9
R/W, 0
AIOEN8
R/W, 0
R/W, 0
R/W, 0
7
6
5
4
3
2
1
0
AIOEN7
R/W, 0
AIOEN6
R/W, 0
AIOEN5
R/W, 0
AIOEN4
R/W, 0
AIOEN3
R/W, 0
AIOEN2
R/W, 0
AIOEN1
R/W, 0
AIOEN0
R/W, 0
LEGEND: R = Read, W = Write, n = value after reset
Figure 3−10. Address/GPIO Enable Register (AGPIOEN) Bit Layout
Table 3−8. Address/GPIO Enable Register (AGPIOEN) Bit Functions
BIT
NO.
BIT
NAME
RESET
VALUE
FUNCTION
Enable or disable GPIO function of Address Bus of EMIF. AIOEN15 and AIOEN14 are only available in
BGA package.
15−0
AIOENx
0
AIOENx = 0
AIOENx = 1
GPIO function of Ax line is disabled; i.e., Ax has address function.
GPIO function of Ax line is enabled; i.e., Ax has GPIO function.
41
April 2004 − Revised January 2005
SPRS245C
Functional Overview
15
14
13
12
11
10
9
8
AIODIR15
(BGA)
AIODIR14
(BGA)
AIODIR13
R/W, 0
AIODIR12
R/W, 0
AIODIR11
R/W, 0
AIODIR10
R/W, 0
AIODIR9
R/W, 0
AIODIR8
R/W, 0
R/W, 0
R/W, 0
7
6
5
4
3
2
1
0
AIODIR7
R/W, 0
AIODIR6
R/W, 0
AIODIR5
R/W, 0
AIODIR4
R/W, 0
AIODIR3
R/W, 0
AIODIR2
R/W, 0
AIODIR1
R/W, 0
AIODIR0
R/W, 0
LEGEND: R = Read, W = Write, n = value after reset
Figure 3−11. Address/GPIO Direction Register (AGPIODIR) Bit Layout
Table 3−9. Address/GPIO Direction Register (AGPIODIR) Bit Functions
BIT
NO.
BIT
NAME
RESET
VALUE
FUNCTION
Data direction bits that configure the Address Bus configured as I/O pins as either input or output pins.
AIODIR15 and AIODIR14 are only available in BGA package.
15−0
AIODIRx
0
AIODIRx = 0
AIODIRx = 1
Configure corresponding pin as an input.
Configure corresponding pin as an output.
15
14
13
12
11
10
9
8
AIOD15 (BGA) AIOD14 (BGA)
AIOD13
R/W, 0
AIOD12
R/W, 0
AIOD11
R/W, 0
AIOD10
R/W, 0
AIOD9
R/W, 0
AIOD8
R/W, 0
R/W, 0
R/W, 0
7
6
5
4
3
2
1
0
AIOD7
R/W, 0
AIOD6
R/W, 0
AIOD5
R/W, 0
AIOD4
R/W, 0
AIOD3
R/W, 0
AIOD2
R/W, 0
AIOD1
R/W, 0
AIOD0
R/W, 0
LEGEND: R = Read, W = Write, n = value after reset
Figure 3−12. Address/GPIO Data Register (AGPIODATA) Bit Layout
Table 3−10. Address/GPIO Data Register (AGPIODATA) Bit Functions
BIT
NO.
BIT
NAME
RESET
VALUE
FUNCTION
Data bits that are used to control the level of the Address Bus configured as I/O output pins, and to monitor
the level of the Address Bus configured as I/O input pins. AIOD15 and AIOD14 are only available in BGA
package.
If AIODIRn = 0, then:
AIODx = 0
AIODx = 1
Corresponding I/O pin is read as a low.
Corresponding I/O pin is read as a high.
15−0
AIODx
0
If AIODIRn = 1, then:
AIODx = 0
AIODx = 1
Set corresponding I/O pin to low.
Set corresponding I/O pin to high.
42
SPRS245C
April 2004 − Revised January 2005
Functional Overview
3.6.3 EHPI General-Purpose I/O
Six control lines of the External Parallel Bus can also be set as general-purpose I/O when the Parallel Port
Mode bit field of the External Bus Selection Register is set to Nonmultiplexed EHPI (10) or Multiplexed EHPI
mode (11). These pins are controlled by three registers: the enable register, EHPIGPIOEN, determines if the
pins serve as GPIO or address (Figure 3−13); the direction register, EHPIGPIODIR, determines if the GPIO
enabled pin is an input or output (Figure 3−14); and the data register, EHPIGPIODATA, determines the logic
states of the pins in GPIO mode (Figure 3−15).
15
6
5
4
3
2
1
0
Reserved
GPIOEN13
R/W, 0
GPIOEN12
R/W, 0
GPIOEN11
R/W, 0
GPIOEN10
R/W, 0
GPIOEN9
R/W, 0
GPIOEN8
R/W, 0
R, 0000 0000 00
LEGEND: R = Read, W = Write, n = value after reset
Figure 3−13. EHPI GPIO Enable Register (EHPIGPIOEN) Bit Layout
Table 3−11. EHPI GPIO Enable Register (EHPIGPIOEN) Bit Functions
BIT
NO.
BIT
NAME
RESET
VALUE
FUNCTION
15−6
Reserved
0
Reserved
Enable or disable GPIO function of EHPI Control Bus.
GPIOENx = 0 GPIO function of GPIOx line is disabled
GPIOENx = 1 GPIO function of GPIOx line is enabled
GPIOEN13−
GPIOEN8
5−0
0
15
6
5
4
3
2
1
0
Reserved
R, 0000 0000 00
GPIODIR13
R/W, 0
GPIODIR12
R/W, 0
GPIODIR11
R/W, 0
GPIODIR10
R/W, 0
GPIODIR9
R/W, 0
GPIODIR8
R/W, 0
LEGEND: R = Read, W = Write, n = value after reset
Figure 3−14. EHPI GPIO Direction Register (EHPIGPIODIR) Bit Layout
Table 3−12. EHPI GPIO Direction Register (EHPIGPIODIR) Bit Functions
BIT
NO.
BIT
NAME
RESET
VALUE
FUNCTION
15−6
5−0
Reserved
0
0
Reserved
Data direction bits that configure the EHPI Control Bus configured as I/O pins as either input or output
pins.
GPIODIRx = 0 Configure corresponding pin as an input.
GPIODIRx = 1 Configure corresponding pin as an output.
GPIODIR13−
GPIODIR8
43
April 2004 − Revised January 2005
SPRS245C
Functional Overview
15
6
5
4
3
2
1
0
Reserved
R, 0000 0000 00
GPIOD13
R/W, 0
GPIOD12
R/W, 0
GPIOD11
R/W, 0
GPIOD10
R/W, 0
GPIOD9
R/W, 0
GPIOD8
R/W, 0
LEGEND: R = Read, W = Write, n = value after reset
Figure 3−15. EHPI GPIO Data Register (EHPIGPIODATA) Bit Layout
Table 3−13. EHPI GPIO Data Register (EHPIGPIODATA) Bit Functions
BIT
NO.
BIT
NAME
RESET
VALUE
FUNCTION
15−6
Reserved
0
Reserved
Data bits that are used to control the level of the EHPI Control Bus configured as I/O output pins, and to
monitor the level of the EHPI Control Bus configured as I/O input pins.
If GPIODIRn = 0, then:
GPIODx = 0
GPIODx = 1
Corresponding I/O pin is read as a low.
Corresponding I/O pin is read as a high.
GPIOD13−
GPIOD8
5−0
0
If GPIODIRn = 1, then:
GPIODx = 0
GPIODx = 1
Set corresponding I/O pin to low.
Set corresponding I/O pin to high.
44
SPRS245C
April 2004 − Revised January 2005
Functional Overview
3.7 System Register
The system register (SYSR) provides control over certain device-specific functions. The register is located
at port address 07FDh.
15
8
Reserved
7
3
2
0
Reserved
CLKDIV
R/W
LEGEND: R = Read, W = Write, n = value after reset
Figure 3−16. System Register Bit Locations
Table 3−14. System Register Bit Fields
BIT
FUNCTION
NUMBER
NAME
Reserved
CLKDIV
15−3
These bits are reserved and are unaffected by writes.
CLKOUT Divide Factor. Allows the clock present on the CLKOUT pin to be a divided-down version
of the internal CPU clock. This field does not affect the programming of the PLL.
CLKDIV 000 = CLKOUT represents the CPU clock divided by 1
CLKDIV 001 = CLKOUT represents the CPU clock divided by 2
CLKDIV 010 = CLKOUT represents the CPU clock divided by 4
CLKDIV 011 = CLKOUT represents the CPU clock divided by 6
CLKDIV 100 = CLKOUT represents the CPU clock divided by 8
CLKDIV 101 = CLKOUT represents the CPU clock divided by 10
CLKDIV 110 = CLKOUT represents the CPU clock divided by 12
CLKDIV 111 = CLKOUT represents the CPU clock divided by 14
2−0
45
April 2004 − Revised January 2005
SPRS245C
Functional Overview
3.8 Memory-Mapped Registers
The 5503 has 78 memory-mapped CPU registers that are mapped in data memory space address 0h to 4Fh.
Table 3−15 provides a list of the CPU memory-mapped registers (MMRs) available. The corresponding
TMS320C54x (C54x) CPU registers are also indicated where applicable.
Table 3−15. CPU Memory-Mapped Registers
C55x
REGISTER
C54x
REGISTER
WORD ADDRESS
(HEX)
DESCRIPTION
Interrupt Enable Register 0
BIT FIELD
IER0
IFR0
ST0_55
ST1_55
ST3_55
−
IMR
IFR
−
00
01
02
03
04
05
06
07
08
09
0A
OB
0C
0D
0E
0F
10
11
[15−0]
[15−0]
[15−0]
[15−0]
[15−0]
[15−0]
[15−0]
[15−0]
[15−0]
[31−16]
[39−32]
[15−0]
[31−16]
[39−32]
[15−0]
[15−0]
[15−0]
[15−0]
[15−0]
[15−0]
[15−0]
[15−0]
[15−0]
[15−0]
[15−0]
[15−0]
[15−0]
[15−0]
[15−0]
[15−0]
[7−0]
Interrupt Flag Register 0
Status Register 0 for C55x
Status Register 1 for C55x
Status Register 3 for C55x
Reserved
−
−
−
ST0
ST0
ST1
AL
Status Register ST0
Status Register ST1
Accumulator 0
ST1
AC0L
AC0H
AC0G
AC1L
AC1H
AC1G
T3
AH
AG
BL
Accumulator 1
BH
BG
TREG
TRN
AR0
AR1
AR2
AR3
AR4
AR5
AR6
AR7
SP
BK
BRC
RSA
REA
PMST
XPC
−
Temporary Register
TRN0
AR0
Transition Register
Auxiliary Register 0
AR1
Auxiliary Register 1
AR2
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
20
21
22
23
24
25
26
Auxiliary Register 2
AR3
Auxiliary Register 3
AR4
Auxiliary Register 4
AR5
Auxiliary Register 5
AR6
Auxiliary Register 6
AR7
Auxiliary Register 7
SP
Stack Pointer Register
Circular Buffer Size Register
Block Repeat Counter
Block Repeat Start Address
Block Repeat End Address
Processor Mode Status Register
Program Counter Extension Register
Reserved
BK03
BRC0
RSA0L
REA0L
PMST
XPC
−
[15−0]
[15−0]
[15−0]
[15−0]
[15−0]
[15−0]
[31−16]
[39−32]
T0
−
Temporary Data Register 0
Temporary Data Register 1
Temporary Data Register 2
Temporary Data Register 3
Accumulator 2
T1
−
T2
−
T3
−
AC2L
AC2H
AC2G
−
−
−
TMS320C54x and C54x are trademarks of Texas Instruments.
46
SPRS245C
April 2004 − Revised January 2005
Functional Overview
Table 3−15. CPU Memory-Mapped Registers (Continued)
C55x
REGISTER
C54x
REGISTER
WORD ADDRESS
DESCRIPTION
(HEX)
BIT FIELD
CDP
AC3L
AC3H
AC3G
DPH
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
27
28
29
2A
2B
2C
2D
2E
2F
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
Coefficient Data Pointer
Accumulator 3
[15−0]
[15−0]
[31−16]
[39−32]
[6−0]
Extended Data Page Pointer
MDP05
MDP67
DP
Reserved
[6−0]
Reserved
[6−0]
Memory Data Page Start Address
Peripheral Data Page Start Address
Circular Buffer Size Register for AR[4−7]
Circular Buffer Size Register for CDP
Circular Buffer Start Address Register for AR[0−1]
Circular Buffer Start Address Register for AR[2−3]
Circular Buffer Start Address Register for AR[4−5]
Circular Buffer Start Address Register for AR[6−7]
Circular Buffer Coefficient Start Address Register
[15−0]
[8−0]
PDP
BK47
[15−0]
[15−0]
[15−0]
[15−0]
[15−0]
[15−0]
[15−0]
BKC
BSA01
BSA23
BSA45
BSA67
BSAC
BIOS
Data Page Pointer Storage Location for 128-word Data Table
Transition Register 1
[15−0]
[15−0]
[15−0]
[15−0]
[15−0]
[23−16]
[15−0]
[23−16]
[15−0]
[23−16]
[15−0]
[23−16]
[15−0]
[15−0]
[15−0]
[15−0]
[15−0]
[15−0]
[15−0]
[15−0]
[15−0]
[15−0]
[15−0]
[6−0]
TRN1
BRC1
BRS1
CSR
Block Repeat Counter 1
Block Repeat Save 1
Computed Single Repeat
RSA0H
RSA0L
REA0H
REA0L
RSA1H
RSA1L
REA1H
REA1L
RPTC
IER1
Repeat Start Address 0
Repeat End Address 0
Repeat Start Address 1
Repeat End Address 1
Repeat Counter
Interrupt Enable Register 1
Interrupt Flag Register 1
Debug IER0
IFR1
DBIER0
DBIER1
IVPD
Debug IER1
Interrupt Vector Pointer DSP
Interrupt Vector Pointer HOST
Status Register 2 for C55x
System Stack Pointer
IVPH
ST2_55
SSP
SP
User Stack Pointer
SPH
Extended Data Page Pointer for the SP and the SSP
Main Data Page Pointer for the CDP
CDPH
[6−0]
47
April 2004 − Revised January 2005
SPRS245C
Functional Overview
3.9 Peripheral Register Description
Each 5503 device has a set of memory-mapped registers associated with peripherals as listed in Table 3−16
through Table 3−29. Some registers use less than 16 bits. When reading these registers, unused bits are
always read as 0.
NOTE: The CPU access latency to the peripheral memory-mapped registers is 6 CPU cycles.
Following peripheral register update(s), the CPU must wait at least 6 CPU cycles before
attempting to use that peripheral. When more than one peripheral register is updated in a
sequence, the CPU only needs to wait following the final register write. For example, if the
EMIF is being reconfigured, the CPU must wait until the very last EMIF register update takes
effect before trying to access the external memory. The users should consult the respective
peripheral user’s guide to determine if a peripheral requires additional time to initialize itself
to the new configuration after the register updates take effect.
Table 3−16. Idle Control, Status, and System Registers
†
WORD ADDRESS
0x0001
REGISTER NAME
ICR[7:0]
DESCRIPTION
RESET VALUE
xxxx xxxx 0000 0100
xxxx xxxx 0000 0000
0000 0000 0000 0000
Idle Control Register
Idle Status Register
System Register
0x0002
ISTR[7:0]
0x07FD
SYSR[15:0]
†
Hardware reset; x denotes a “don’t care.”
Table 3−17. External Memory Interface Registers
†
WORD ADDRESS
0x0800
0x0801
0x0802
0x0803
0x0804
0x0805
0x0806
0x0807
0x0808
0x0809
0x080A
0x080B
0x080C
0x080D
0x080E
0x080F
0x0810
0x0811
REGISTER NAME
DESCRIPTION
EMIF Global Control Register
RESET VALUE
EGCR[15:0]
EMI_RST
xxxx xxxx 0010 xx00
xxxx xxxx xxxx xxxx
xx00 0000 0000 0000
x010 1111 1111 1111
0100 1111 1111 1111
xxxx xxxx 0000 0000
x010 1111 1111 1111
0100 1111 1111 1111
xxxx xxxx 0000 0000
x010 1111 1111 1111
0101 1111 1111 1111
xxxx xxxx 0000 0000
x010 1111 1111 1111
0101 1111 1111 1111
xxxx xxxx 0000 0000
1111 1001 0100 1000
xxxx 0000 1000 0000
xxxx 0000 1000 0000
xxxx xxxx xxxx xxxx
xxxx xx11 1111 1111
0000 0000 0000 0111
EMIF Global Reset Register
EMI_BE[13:0]
CE0_1[14:0]
CE0_2[15:0]
CE0_3[7:0]
CE1_1[14:0]
CE1_2[15:0]
CE1_3[7:0]
CE2_1[14:0]
CE2_2[15:0]
CE2_3[7:0]
CE3_1[14:0]
CE3_2[15:0]
CE3_3[7:0]
SDC1[15:0]
SDPER[11:0]
SDCNT[11:0]
INIT
EMIF Bus Error Status Register
EMIF CE0 Space Control Register 1
EMIF CE0 Space Control Register 2
EMIF CE0 Space Control Register 3
EMIF CE1 Space Control Register 1
EMIF CE1 Space Control Register 2
EMIF CE1 Space Control Register 3
EMIF CE2 Space Control Register 1
EMIF CE2 Space Control Register 2
EMIF CE2 Space Control Register 3
EMIF CE3 Space Control Register 1
EMIF CE3 Space Control Register 2
EMIF CE3 Space Control Register 3
EMIF SDRAM Control Register 1
EMIF SDRAM Period Register
EMIF SDRAM Counter Register
EMIF SDRAM Init Register
0x0812
0x0813
0x0814
SDC2[9:0]
SDC3
EMIF SDRAM Control Register 2
EMIF SDRAM Control Register 3
†
Hardware reset; x denotes a “don’t care.”
48
SPRS245C
April 2004 − Revised January 2005
Functional Overview
Table 3−18. DMA Configuration Registers
PORT ADDRESS
(WORD)
†
REGISTER NAME
DESCRIPTION
GLOBAL REGISTER
RESET VALUE
0x0E00
0x0E02
0x0E03
DMA_GCR[2:0]
DMA_GSCR
DMA_GTCR
DMA Global Control Register
DMA Software Compatibility Register
DMA Timeout Control Register
CHANNEL #0 REGISTERS
xxxx xxxx xxxx x000
0x0C00
DMA_CSDP0
DMA Channel 0 Source Destination
Parameters Register
0000 0000 0000 0000
0x0C01
0x0C02
0x0C03
0x0C04
DMA_CCR0[15:0]
DMA_CICR0[5:0]
DMA_CSR0[6:0]
DMA_CSSA_L0
DMA Channel 0 Control Register
DMA Channel 0 Interrupt Control Register
DMA Channel 0 Status Register
0000 0000 0000 0000
xxxx xxxx xx00 0011
xxxx xxxx xx00 0000
Undefined
DMA Channel 0 Source Start Address Register
(lower bits)
0x0C05
0x0C06
0x0C07
DMA_CSSA_U0
DMA_CDSA_L0
DMA_CDSA_U0
DMA Channel 0 Source Start Address Register
(upper bits)
Undefined
Undefined
Undefined
DMA Channel 0 Source Destination Address Register
(lower bits)
DMA Channel 0 Source Destination Address Register
(upper bits)
0x0C08
0x0C09
0x0C0A
0x0C0B
0x0C0C
0x0C0D
0x0C0E
DMA_CEN0
DMA_CFN0
DMA_CSFI0
DMA_CSEI0
DMA_CSAC0
DMA_CDAC0
DMA_CDEI0
DMA_CDFI0
DMA Channel 0 Element Number Register
DMA Channel 0 Frame Number Register
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
DMA Channel 0 Source Frame Index Register
DMA Channel 0 Source Element Index Register
DMA Channel 0 Source Address Counter
DMA Channel 0 Destination Address Counter
DMA Channel 0 Destination Element Index Register
DMA Channel 0 Destination Frame Index Register
0x0C0F
†
Hardware reset: x denotes a “don’t care.”
49
April 2004 − Revised January 2005
SPRS245C
Functional Overview
Table 3−18. DMA Configuration Registers (Continued)
PORT ADDRESS
(WORD)
†
REGISTER NAME
DESCRIPTION
CHANNEL #1 REGISTERS
RESET VALUE
0x0C20
DMA_CSDP1
DMA Channel 1 Source Destination
Parameters Register
0000 0000 0000 0000
0x0C21
0x0C22
0x0C23
0x0C24
DMA_CCR1[15:0]
DMA_CICR1[5:0]
DMA_CSR1[6:0]
DMA_CSSA_L1
DMA Channel 1 Control Register
DMA Channel 1 Interrupt Control Register
DMA Channel 1 Status Register
0000 0000 0000 0000
xxxx xxxx xx00 0011
xxxx xxxx xx00 0000
Undefined
DMA Channel 1 Source Start Address Register
(lower bits)
0x0C25
0x0C26
0x0C27
DMA_CSSA_U1
DMA_CDSA_L1
DMA_CDSA_U1
DMA Channel 1 Source Start Address Register
(upper bits)
Undefined
Undefined
Undefined
DMA Channel 1 Source Destination Address Register
(lower bits)
DMA Channel 1 Source Destination Address Register
(upper bits)
0x0C28
0x0C29
0x0C2A
0x0C2B
0x0C2C
0x0C2D
0x0C2E
0x0C2F
DMA_CEN1
DMA_CFN1
DMA_CSFI1
DMA_CSEI1
DMA_CSAC1
DMA_CDAC1
DMA_CDEI1
DMA_CDFI1
DMA Channel 1 Element Number Register
DMA Channel 1 Frame Number Register
DMA Channel 1 Source Frame Index Register
DMA Channel 1 Source Element Index Register
DMA Channel 1 Source Address Counter
DMA Channel 1 Destination Address Counter
DMA Channel 1 Destination Element Index Register
DMA Channel 1 Destination Frame Index Register
CHANNEL #2 REGISTERS
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
0x0C40
DMA_CSDP2
DMA Channel 2 Source Destination
Parameters Register
0000 0000 0000 0000
0x0C41
0x0C42
0x0C43
0x0C44
DMA_CCR2[15:0]
DMA_CICR2[5:0]
DMA_CSR2[6:0]
DMA_CSSA_L2
DMA Channel 2 Control Register
DMA Channel 2 Interrupt Control Register
DMA Channel 2 Status Register
0000 0000 0000 0000
xxxx xxxx xx00 0011
xxxx xxxx xx00 0000
Undefined
DMA Channel 2 Source Start Address Register
(lower bits)
0x0C45
0x0C46
0x0C47
DMA_CSSA_U2
DMA_CDSA_L2
DMA_CDSA_U2
DMA Channel 2 Source Start Address Register
(upper bits)
Undefined
Undefined
Undefined
DMA Channel 2 Source Destination Address Register
(lower bits)
DMA Channel 2 Source Destination Address Register
(upper bits)
0x0C48
0x0C49
0x0C4A
0x0C4B
0x0C4C
0x0C4D
0x0C4E
DMA_CEN2
DMA_CFN2
DMA_CSFI2
DMA_CSEI2
DMA_CSAC2
DMA_CDAC2
DMA_CDEI2
DMA_CDFI2
DMA Channel 2 Element Number Register
DMA Channel 2 Frame Number Register
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
DMA Channel 2 Source Frame Index Register
DMA Channel 2 Source Element Index Register
DMA Channel 2 Source Address Counter
DMA Channel 2 Destination Address Counter
DMA Channel 2 Destination Element Index Register
DMA Channel 2 Destination Frame Index Register
0x0C4F
†
Hardware reset: x denotes a “don’t care.”
50
SPRS245C
April 2004 − Revised January 2005
Functional Overview
Table 3−18. DMA Configuration Registers (Continued)
PORT ADDRESS
(WORD)
†
REGISTER NAME
DESCRIPTION
CHANNEL #3 REGISTERS
RESET VALUE
0x0C60
DMA_CSDP3
DMA Channel 3 Source Destination
Parameters Register
0000 0000 0000 0000
0x0C61
0x0C62
0x0C63
0x0C64
DMA_CCR3[15:0]
DMA_CICR3[5:0]
DMA_CSR3[6:0]
DMA_CSSA_L3
DMA Channel 3 Control Register
DMA Channel 3 Interrupt Control Register
DMA Channel 3 Status Register
0000 0000 0000 0000
xxxx xxxx xx00 0011
xxxx xxxx xx00 0000
Undefined
DMA Channel 3 Source Start Address Register
(lower bits)
0x0C65
0x0C66
0x0C67
DMA_CSSA_U3
DMA_CDSA_L3
DMA_CDSA_U3
DMA Channel 3 Source Start Address Register
(upper bits)
Undefined
Undefined
Undefined
DMA Channel 3 Source Destination Address Register
(lower bits)
DMA Channel 3 Source Destination Address Register
(upper bits)
0x0C68
0x0C69
0x0C6A
0x0C6B
0x0C6C
0x0C6D
0x0C6E
0x0C6F
DMA_CEN3
DMA_CFN3
DMA_CSFI3
DMA_CSEI3
DMA_CSAC3
DMA_CDAC3
DMA_CDEI3
DMA_CDFI3
DMA Channel 3 Element Number Register
DMA Channel 3 Frame Number Register
DMA Channel 3 Source Frame Index Register
DMA Channel 3 Source Element Index Register
DMA Channel 3 Source Address Counter
DMA Channel 3 Destination Address Counter
DMA Channel 3 Destination Element Index Register
DMA Channel 3 Destination Frame Index Register
CHANNEL #4 REGISTERS
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
0x0C80
DMA_CSDP4
DMA Channel 4 Source Destination
Parameters Register
0000 0000 0000 0000
0x0C81
0x0C82
0x0C83
0x0C84
DMA_CCR4[15:0]
DMA_CICR4[5:0]
DMA_CSR4[6:0]
DMA_CSSA_L4
DMA Channel 4 Control Register
DMA Channel 4 Interrupt Control Register
DMA Channel 4 Status Register
0000 0000 0000 0000
xxxx xxxx xx00 0011
xxxx xxxx xx00 0000
Undefined
DMA Channel 4 Source Start Address Register
(lower bits)
0x0C85
0x0C86
0x0C87
DMA_CSSA_U4
DMA_CDSA_L4
DMA_CDSA_U4
DMA Channel 4 Source Start Address Register
(upper bits)
Undefined
Undefined
Undefined
DMA Channel 4 Source Destination Address Register
(lower bits)
DMA Channel 4 Source Destination Address Register
(upper bits)
0x0C88
0x0C89
0x0C8A
0x0C8B
0x0C8C
0x0C8D
0x0C8E
DMA_CEN4
DMA_CFN4
DMA_CSFI4
DMA_CSEI4
DMA_CSAC4
DMA_CDAC4
DMA_CDEI4
DMA_CDFI4
DMA Channel 4 Element Number Register
DMA Channel 4 Frame Number Register
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
DMA Channel 4 Source Frame Index Register
DMA Channel 4 Source Element Index Register
DMA Channel 4 Source Address Counter
DMA Channel 4 Destination Address Counter
DMA Channel 4 Destination Element Index Register
DMA Channel 4 Destination Frame Index Register
0x0C8F
†
Hardware reset: x denotes a “don’t care.”
51
April 2004 − Revised January 2005
SPRS245C
Functional Overview
Table 3−18. DMA Configuration Registers (Continued)
PORT ADDRESS
(WORD)
†
REGISTER NAME
DESCRIPTION
CHANNEL #5 REGISTERS
RESET VALUE
0x0CA0
DMA_CSDP5
DMA Channel 5 Source Destination
Parameters Register
0000 0000 0000 0000
0x0CA1
0x0CA2
0x0CA3
0x0CA4
DMA_CCR5[15:0]
DMA_CICR5[5:0]
DMA_CSR5[6:0]
DMA_CSSA_L5
DMA Channel 5 Control Register
DMA Channel 5 Interrupt Control Register
DMA Channel 5 Status Register
0000 0000 0000 0000
xxxx xxxx xx00 0011
xxxx xxxx xx00 0000
Undefined
DMA Channel 5 Source Start Address Register
(lower bits)
0x0CA5
0x0CA6
0x0CA7
DMA_CSSA_U5
DMA_CDSA_L5
DMA_CDSA_U5
DMA Channel 5 Source Start Address Register
(upper bits)
Undefined
Undefined
Undefined
DMA Channel 5 Source Destination Address Register
(lower bits)
DMA Channel 5 Source Destination Address Register
(upper bits)
0x0CA8
0x0CA9
0x0CAA
0x0CAB
0x0CAC
0x0CAD
0x0CAE
DMA_CEN5
DMA_CFN5
DMA_CSFI5
DMA_CSEI5
DMA_CSAC5
DMA_CDAC5
DMA_CDEI5
DMA_CDFI5
DMA Channel 5 Element Number Register
DMA Channel 5 Frame Number Register
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
DMA Channel 5 Source Frame Index Register
DMA Channel 5 Source Element Index Register
DMA Channel 5 Source Address Counter
DMA Channel 5 Destination Address Counter
DMA Channel 5 Destination Element Index Register
DMA Channel 5 Destination Frame Index Register
0x0CAF
†
Hardware reset: x denotes a “don’t care.”
Table 3−19. Real-Time Clock Registers
†
WORD ADDRESS
REGISTER NAME
DESCRIPTION
Seconds Register
RESET VALUE
0x1800
RTCSEC
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 1000 0000
0000 0000 0000 0000
0x1801
RTCSECA
RTCMIN
Seconds Alarm Register
Minutes Register
0x1802
0x1803
RTCMINA
RTCHOUR
RTCHOURA
RTCDAYW
RTCDAYM
RTCMONTH
RTCYEAR
RTCPINTR
RTCINTEN
RTCINTFL
Minutes Alarm Register
Hours Register
0x1804
0x1805
Hours Alarm Register
Day of the Week Register
Day of the Month (date) Register
Month Register
0x1806
0x1807
0x1808
0x1809
Year Register
0x180A
0x180B
0x180C
0x180D−0x1BFF
Periodic Interrupt Selection Register
Interrupt Enable Register
Interrupt Flag Register
Reserved
†
Hardware reset; x denotes a “don’t care.”
52
SPRS245C
April 2004 − Revised January 2005
Functional Overview
Table 3−20. Clock Generator
†
WORD ADDRESS
REGISTER NAME
CLKMD[14:0]
DESCRIPTION
RESET VALUE
0x1C00
Clock Mode Register
0010 0000 0000 0010 DIV1 mode
†
Hardware reset; x denotes a “don’t care.”
Table 3−21. Timers
†
WORD ADDRESS
REGISTER NAME
TIM0[15:0]
DESCRIPTION
RESET VALUE
1111 1111 1111 1111
1111 1111 1111 1111
0x1000
0x1001
0x1002
0x1003
0x2400
0x2401
0x2402
0x2403
Timer Count Register, Timer #0
Period Register, Timer #0
PRD0[15:0]
TCR0[15:0]
PRSC0[15:0]
TIM1[15:0]
Timer Control Register, Timer #0
Timer Prescaler Register, Timer #0
Timer Count Register, Timer #1
Period Register, Timer #1
0000 0000 0001 0000
xxxx 0000 xxxx 0000
1111 1111 1111 1111
1111 1111 1111 1111
0000 0000 0001 0000
xxxx 0000 xxxx 0000
PRD1[15:0]
TCR1[15:0]
PRSC1[15:0]
Timer Control Register, Timer #1
Timer Prescaler Register, Timer #1
†
Hardware reset; x denotes a “don’t care.”
53
April 2004 − Revised January 2005
SPRS245C
Functional Overview
Table 3−22. Multichannel Serial Port #0
PORT ADDRESS
(WORD)
†
REGISTER NAME
DESCRIPTION
RESET VALUE
0x2800
0x2801
0x2802
0x2803
0x2804
0x2805
0x2806
0x2807
0x2808
0x2809
0x280A
0x280B
0x280C
0x280D
0x280E
0x280F
0x2810
0x2811
0x2812
0x2813
0x2814
0x2815
0x2816
0x2817
0x2818
0x2819
0x281A
0x281B
0x281C
0x281D
DRR2_0[15:0]
DRR1_0[15:0]
DXR2_0[15:0]
DXR1_0[15:0]
SPCR2_0[15:0]
SPCR1_0[15:0]
RCR2_0[15:0]
RCR1_0[15:0]
XCR2_0[15:0]
XCR1_0[15:0]
SRGR2_0[15:0]
SRGR1_0[15:0]
MCR2_0[15:0]
MCR1_0[15:0]
RCERA_0[15:0]
RCERB_0[15:0]
XCERA_0[15:0]
XCERB_0[15:0]
PCR0[15:0]
Data Receive Register 2, McBSP #0
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0020 0000 0000 0000
0000 0000 0000 0001
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
Data Receive Register 1, McBSP #0
Data Transmit Register 2, McBSP #0
Data Transmit Register 1, McBSP #0
Serial Port Control Register 2, McBSP #0
Serial Port Control Register 1, McBSP #0
Receive Control Register 2, McBSP #0
Receive Control Register 1, McBSP #0
Transmit Control Register 2, McBSP #0
Transmit Control Register 1, McBSP #0
Sample Rate Generator Register 2, McBSP #0
Sample Rate Generator Register 1, McBSP #0
Multichannel Control Register 2, McBSP #0
Multichannel Control Register 1, McBSP #0
Receive Channel Enable Register Partition A, McBSP #0
Receive Channel Enable Register Partition B, McBSP #0
Transmit Channel Enable Register Partition A, McBSP #0
Transmit Channel Enable Register Partition B, McBSP #0
Pin Control Register, McBSP #0
RCERC_0[15:0]
RCERD_0[15:0]
XCERC_0[15:0]
XCERD_0[15:0]
RCERE_0[15:0]
RCERF_0[15:0]
XCERE_0[15:0]
XCERF_0[15:0]
RCERG_0[15:0]
RCERH_0[15:0]
XCERG_0[15:0]
XCERH_0[15:0]
Receive Channel Enable Register Partition C, McBSP #0
Receive Channel Enable Register Partition D, McBSP #0
Transmit Channel Enable Register Partition C, McBSP #0
Transmit Channel Enable Register Partition D, McBSP #0
Receive Channel Enable Register Partition E, McBSP #0
Receive Channel Enable Register Partition F, McBSP #0
Transmit Channel Enable Register Partition E, McBSP #0
Transmit Channel Enable Register Partition F, McBSP #0
Receive Channel Enable Register Partition G, McBSP #0
Receive Channel Enable Register Partition H, McBSP #0
Transmit Channel Enable Register Partition G, McBSP #0
Transmit Channel Enable Register Partition H, McBSP #0
0x281E
†
Hardware reset; x denotes a “don’t care.”
54
SPRS245C
April 2004 − Revised January 2005
Functional Overview
Table 3−23. Multichannel Serial Port #1
PORT ADDRESS
(WORD)
†
REGISTER NAME
DESCRIPTION
RESET VALUE
0x2C00
0x2C01
0x2C02
0x2C03
0x2C04
0x2C05
0x2C06
0x2C07
0x2C08
0x2C09
0x2C0A
0x2C0B
0x2C0C
0x2C0D
0x2C0E
0x2C0F
0x2C10
0x2C11
0x2C12
0x2C13
0x2C14
0x2C15
0x2C16
0x2C17
0x2C18
0x2C19
0x2C1A
0x2C1B
0x2C1C
0x2C1D
DRR2_1[15:0]
DRR1_1[15:0]
DXR2_1[15:0]
DXR1_1[15:0]
SPCR2_1[15:0]
SPCR1_1[15:0]
RCR2_1[15:0]
RCR1_1[15:0]
XCR2_1[15:0]
XCR1_1[15:0]
SRGR2_1[15:0]
SRGR1_1[15:0]
MCR2_1[15:0]
MCR1_1[15:0]
RCERA_1[15:0]
RCERB_1[15:0]
XCERA_1[15:0]
XCERB_1[15:0]
PCR1[15:0]
Data Receive Register 2, McBSP #1
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0020 0000 0000 0000
0000 0000 0000 0001
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
Data Receive Register 1, McBSP #1
Data Transmit Register 2, McBSP #1
Data Transmit Register 1, McBSP #1
Serial Port Control Register 2, McBSP #1
Serial Port Control Register 1, McBSP #1
Receive Control Register 2, McBSP #1
Receive Control Register 1, McBSP #1
Transmit Control Register 2, McBSP #1
Transmit Control Register 1, McBSP #1
Sample Rate Generator Register 2, McBSP #1
Sample Rate Generator Register 1, McBSP #1
Multichannel Control Register 2, McBSP #1
Multichannel Control Register 1, McBSP #1
Receive Channel Enable Register Partition A, McBSP #1
Receive Channel Enable Register Partition B, McBSP #1
Transmit Channel Enable Register Partition A, McBSP #1
Transmit Channel Enable Register Partition B, McBSP #1
Pin Control Register, McBSP #1
RCERC_1[15:0]
RCERD_1[15:0]
XCERC_1[15:0]
XCERD_1[15:0]
RCERE_1[15:0]
RCERF_1[15:0]
XCERE_1[15:0]
XCERF_1[15:0]
RCERG_1[15:0]
RCERH_1[15:0]
XCERG_1[15:0]
XCERH_1[15:0]
Receive Channel Enable Register Partition C, McBSP #1
Receive Channel Enable Register Partition D, McBSP #1
Transmit Channel Enable Register Partition C, McBSP #1
Transmit Channel Enable Register Partition D, McBSP #1
Receive Channel Enable Register Partition E, McBSP #1
Receive Channel Enable Register Partition F, McBSP #1
Transmit Channel Enable Register Partition E, McBSP #1
Transmit Channel Enable Register Partition F, McBSP #1
Receive Channel Enable Register Partition G, McBSP #1
Receive Channel Enable Register Partition H, McBSP #1
Transmit Channel Enable Register Partition G, McBSP #1
Transmit Channel Enable Register Partition H, McBSP #1
0x2C1E
†
Hardware reset; x denotes a “don’t care.”
55
April 2004 − Revised January 2005
SPRS245C
Functional Overview
Table 3−24. Multichannel Serial Port #2
PORT ADDRESS
(WORD)
†
REGISTER NAME
DESCRIPTION
RESET VALUE
0x3000
0x3001
0x3002
0x3003
0x3004
0x3005
0x3006
0x3007
0x3008
0x3009
0x300A
0x300B
0x300C
0x300D
0x300E
0x300F
0x3010
0x3011
0x3012
0x3013
0x3014
0x3015
0x3016
0x3017
0x3018
0x3019
0x301A
0x301B
0x301C
0x301D
0x301E
DRR2_2[15:0]
DRR1_2[15:0]
DXR2_2[15:0]
DXR1_2[15:0]
SPCR2_2[15:0]
SPCR1_2[15:0]
RCR2_2[15:0]
RCR1_2[15:0]
XCR2_2[15:0]
XCR1_2[15:0]
SRGR2_2[15:0]
SRGR1_2[15:0]
MCR2_2[15:0]
MCR1_2[15:0]
RCERA_2[15:0]
RCERB_2[15:0]
XCERA_2[15:0]
XCERB_2[15:0]
PCR2[15:0]
Data Receive Register 2, McBSP #2
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0020 0000 0000 0000
0000 0000 0000 0001
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
Data Receive Register 1, McBSP #2
Data Transmit Register 2, McBSP #2
Data Transmit Register 1, McBSP #2
Serial Port Control Register 2, McBSP #2
Serial Port Control Register 1, McBSP #2
Receive Control Register 2, McBSP #2
Receive Control Register 1, McBSP #2
Transmit Control Register 2, McBSP #2
Transmit Control Register 1, McBSP #2
Sample Rate Generator Register 2, McBSP #2
Sample Rate Generator Register 1, McBSP #2
Multichannel Control Register 2, McBSP #2
Multichannel Control Register 1, McBSP #2
Receive Channel Enable Register Partition A, McBSP #2
Receive Channel Enable Register Partition B, McBSP #2
Transmit Channel Enable Register Partition A, McBSP #2
Transmit Channel Enable Register Partition B, McBSP #2
Pin Control Register, McBSP #2
RCERC_2[15:0]
RCERD_2[15:0]
XCERC_2[15:0]
XCERD_2[15:0]
RCERE_2[15:0]
RCERF_2[15:0]
XCERE_2[15:0]
XCERF_2[15:0]
RCERG_2[15:0]
RCERH_2[15:0]
XCERG_2[15:0]
XCERH_2[15:0]
Receive Channel Enable Register Partition C, McBSP #2
Receive Channel Enable Register Partition D, McBSP #2
Transmit Channel Enable Register Partition C, McBSP #2
Transmit Channel Enable Register Partition D, McBSP #2
Receive Channel Enable Register Partition E, McBSP #2
Receive Channel Enable Register Partition F, McBSP #2
Transmit Channel Enable Register Partition E, McBSP #2
Transmit Channel Enable Register Partition F, McBSP #2
Receive Channel Enable Register Partition G, McBSP #2
Receive Channel Enable Register Partition H, McBSP #2
Transmit Channel Enable Register Partition G, McBSP #2
Transmit Channel Enable Register Partition H, McBSP #2
†
Hardware reset; x denotes a “don’t care.”
56
SPRS245C
April 2004 − Revised January 2005
Functional Overview
Table 3−25. GPIO
WORD
ADDRESS
REGISTER
NAME
†
PIN
DESCRIPTION
RESET VALUE
0x3400
0x3401
0x4400
0x4401
0x4402
0x4403
0x4404
IODIR[7:0]
GPIO[7:0]
GPIO[7:0]
A[15:0]
General-purpose I/O Direction Register 0000 0000 0000 0000
IODATA[7:0]
General-purpose I/O Data Register
Address/GPIO Enable Register
Address/GPIO Direction Register
Address/GPIO Data Register
EHPI/GPIO Enable Register
EHPI/GPIO Direction Register
EHPI/GPIO Data Register
0000 0000 xxxx xxxx
0000 0000 0000 0000
0000 0000 0000 0000
xxxx xxxx xxxx xxxx
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 00xx xxxx
AGPIOEN[15:0]
AGPIODIR[15:0]
AGPIODATA[15:0]
EHPIGPIOEN[5:0]
EHPIGPIODIR[5:0]
EHPIGPIODATA[5:0]
A[15:0]
A[15:0]
GPIO[13:8]
GPIO[13:8]
GPIO[13:8]
0x4405
†
Hardware reset; x denotes a “don’t care.”
Table 3−26. Device Revision ID
‡
WORD ADDRESS
REGISTER NAME
DESCRIPTION
VALUE
0x3803
Rev ID[4:1]
Silicon Revision Identification
Rev. 1.0: xxxx xxxx xxx0 001x
‡
x denotes a “don’t care.”
2
Table 3−27. I C Module Registers
†
WORD ADDRESS
REGISTER NAME
DESCRIPTION
RESET VALUE
§
2
0x3C00
0x3C01
0x3C02
0x3C03
0x3C04
0x3C05
0x3C06
0x3C07
0x3C08
0x3C09
0x3C0A
0x3C0B
0x3C0C
0x3C0D
0x3C0E
0x3C0F
−
I2COAR[9:0]
I2CIMR
I C Own Address Register
0000 0000 0000 0000
0000 0000 0000 0000
0000 0001 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0011 1111 1111
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
2
I C Interrupt Mask Register
2
I2CSTR
I C Status Register
2
I2CCLKL[15:0]
I2CCLKH[15:0]
I2CCNT[15:0]
I2CDRR[7:0]
I2CSAR[9:0]
I2CDXR[7:0]
I2CMDR[14:0]
I2CIVR
I C Clock Divider Low Register
2
I C Clock Divider High Register
2
I C Data Count
2
I C Data Receive Register
2
I C Slave Address Register
2
I C Data Transmit Register
2
I C Mode Register
2
I C Interrupt Vector Register
−
Reserved
2
I2CPSC
I C Prescaler Register
0000 0000 0000 0000
0000 0000 0000 0000
−
Reserved
Reserved
−
2
I2CMDR2
I2CRSR
I C Mode Register 2
2
I C Receive Shift Register (not accessible to the CPU)
2
−
I2CXSR
I C Transmit Shift Register (not accessible to the CPU)
†
Hardware reset; x denotes a “don’t care.”
§
2
This register must be set by the user. The user may program the I C’s own address to any value, as long as the value does not conflict with
2
2
the I C addresses of other components connected to the I C bus.
2
NOTE: I C protocol compatible, no fail-safe buffer.
57
April 2004 − Revised January 2005
SPRS245C
Functional Overview
Table 3−28. Watchdog Timer Registers
†
WORD ADDRESS
REGISTER NAME
DESCRIPTION
WD Timer Counter Register
RESET VALUE
1111 1111 1111 1111
1111 1111 1111 1111
0000 0011 1100 1111
0001 0000 0000 0000
0x4000
0x4001
0x4002
0x4003
WDTIM[15:0]
WDPRD[15:0]
WDTCR[13:0]
WDTCR2[15:0]
WD Timer Period Register
WD Timer Control Register
WD Timer Control Register 2
†
Hardware reset; x denotes a “don’t care.”
Table 3−29. External Bus Selection Register
†
WORD ADDRESS
REGISTER NAME
EBSR[15:0]
Hardware reset; x denotes a “don’t care.”
DESCRIPTION
RESET VALUE
‡
0x6C00
External Bus Selection Register
0000 0000 0000 0011
†
‡
The reset value is 0000 0000 0000 0001 if GPIO0 = 1; the value is 0000 0000 0000 0011 if GPIO0 = 0.
58
SPRS245C
April 2004 − Revised January 2005
Functional Overview
3.10 Interrupts
Vector-relative locations and priorities for all internal and external interrupts are shown in Table 3−30.
Table 3−30. Interrupt Table
SOFTWARE
(TRAP)
EQUIVALENT
RELATIVE
LOCATION
(HEX BYTES)
†
NAME
RESET
PRIORITY
FUNCTION
SINT0
0
0
Reset (hardware and software)
Nonmaskable interrupt
‡
NMI
SINT1
8
1
BERR
INT0
SINT24
SINT2
C0
10
80
18
20
28
88
30
38
40
90
48
50
58
98
60
68
A0
A8
70
78
B0
B8
C8
D0
D8
E0
E8
F0
F8
2
Bus Error interrupt
3
External interrupt #0
INT1
SINT16
SINT3
4
External interrupt #1
INT2
5
External interrupt #2
TINT0
RINT0
XINT0
RINT1
XINT1
−
SINT4
6
Timer #0 interrupt
SINT5
7
McBSP #0 receive interrupt
McBSP #0 transmit interrupt
McBSP #1 receive interrupt
McBSP #1 transmit interrupt
Software interrupt #8
SINT17
SINT6
8
9
SINT7
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
SINT8
DMAC0
DMAC1
DSPINT
INT3/WDTINT
SINT18
SINT9
DMA Channel #0 interrupt
DMA Channel #1 interrupt
Interrupt from host
SINT10
SINT11
SINT19
SINT12
SINT13
SINT20
SINT21
SINT14
SINT15
SINT22
SINT23
SINT25
SINT26
SINT27
SINT28
SINT29
SINT30
SINT31
External interrupt #3 or Watchdog timer interrupt
External interrupt #4 or RTC interrupt
McBSP #2 receive interrupt
McBSP #2 transmit interrupt
DMA Channel #2 interrupt
DMA Channel #3 interrupt
DMA Channel #4 interrupt
DMA Channel #5 interrupt
Timer #1 interrupt
§
INT4/RTC
RINT2
XINT2
DMAC2
DMAC3
DMAC4
DMAC5
TINT1
IIC
2
I C interrupt
DLOG
RTOS
−
Data Log interrupt
Real-time Operating System interrupt
Software interrupt #27
Software interrupt #28
Software interrupt #29
Software interrupt #30
Software interrupt #31
−
−
−
−
†
Absolute addresses of the interrupt vector locations are determined by the contents of the IVPD and IVPH registers. Interrupt vectors for
interrupts 0−15 and 24−31 are relative to IVPD. Interrupt vectors for interrupts 16−23 are relative to IVPH.
The NMI pin is internally tied high. However, NMI interrupt vector can be used for SINT1 and Watchdog Timer Interrupt.
It is recommended that either the INT4 or RTC interrupt be used. If both INT4 and RTC interrupts are used, one interrupt event can potentially
hold off the other interrupt. For example, if INT4 is asserted first and held low, the RTC interrupt will not be recognized until the INT4 pin is back
to high-logic state again. The INT4 pin must be pulled high if only the RTC interrupt is used.
‡
§
59
April 2004 − Revised January 2005
SPRS245C
Functional Overview
3.10.1 IFR and IER Registers
The IFR0 (Interrupt Flag Register 0) and IER0 (Interrupt Enable Register 0) bit layouts are shown in
Figure 3−17.
15
14
13
12
11
10
9
8
INT3/
WDTINT
DMAC5
R/W
DMAC4
R/W
XINT2
R/W
RINT2
R/W
DSPINT
R/W
DMAC1
R/W
Reserved
R/W
7
6
5
4
3
2
1
0
XINT1
R/W
RINT1
R/W
RINT0
R/W
TINT0
R/W
INT2
R/W
INT0
R/W
Reserved
LEGEND: R = Read, W = Write, n = value after reset
Figure 3−17. IFR0 and IER0 Bit Locations
Table 3−31. IFR0 and IER0 Register Bit Fields
BIT
FUNCTION
NUMBER
NAME
DMAC5
DMAC4
XINT2
15
14
13
12
DMA channel 5 interrupt flag/mask bit
DMA channel 4 interrupt flag/mask bit
This bit is used as the McBSP2 transmit interrupt flag/mask bit.
McBSP2 receive interrupt flag/mask bit.
RINT2
This bit is used as either the external user interrupt 3 flag/mask bit, or the watchdog timer interrupt
flag/mask bit.
11
INT3/WDTINT
†
10
9
DSPINT
DMAC1
−
HPI host-to-DSP interrupt flag/mask.
DMA channel 1 interrupt flag/mask bit
Reserved. This bit should always be written with 0.
This bit is used as the McBSP1 transmit interrupt flag/mask bit.
McBSP1 receive interrupt flag/mask bit.
McBSP0 receive interrupt flag bit
8
7
XINT1
RINT1
RINT0
TINT0
INT2
6
5
4
Timer 0 interrupt flag bit
3
External interrupt 2 flag bit
2
INT0
External interrupt 0 flag bit
1−0
−
Reserved for future expansion. These bits should always be written with 0.
†
It is possible to have active interrupts simultaneously from both the external INT3 source and the watchdog timer. When an interrupt is detected
in this bit, the watchdog timer status register should be polled to determine if the watchdog timer is the interrupt source.
60
SPRS245C
April 2004 − Revised January 2005
Functional Overview
The IFR1 (Interrupt Flag Register 1) and IER1 (Interrupt Enable Register 1) bit layouts are shown in
Figure 3−18.
NOTE: It is possible to have active interrupts simultaneously from both the external interrupt 4
(INT4) and the real-time clock (RTC). When an interrupt is detected in this bit, the real-time
clock status register should be polled to determine if the real-time clock is the source of the
interrupt.
15
11
10
9
8
Reserved
RTOS
R/W−0
DLOG
R/W−0
BERR
R/W−0
†
R/W−00000
7
6
5
4
3
2
1
0
I2C
TINT1
R/W−0
DMAC3
R/W−0
DMAC2
R/W−0
INT4/RTC
R/W−0
DMAC0
R/W−0
XINT0
R/W−0
INT1
R/W−0
R/W−0
LEGEND: R = Read, W = Write, n = value after reset
†
Always write zeros.
Figure 3−18. IFR1 and IER1 Bit Locations
Table 3−32. IFR1 and IER1 Register Bit Fields
BIT
FUNCTION
NUMBER
NAME
−
15−11
Reserved for future expansion. These bits should always be written with 0.
Real-time operating system interrupt flag/mask bit
Data log interrupt flag/mask bit
10
9
RTOS
DLOG
BERR
I2C
8
Bus error interrupt flag/mask bit
7
I2C interrupt flag/mask bit
6
TINT1
DMAC3
DMAC2
Timer 1 interrupt flag/mask bit
5
DMA channel 3 interrupt flag/mask bit
DMA channel 2 interrupt flag/mask bit
4
This bit can be used as either the external user interrupt 4 flag/mask bit, or the real-time clock
interrupt flag/mask bit.
3
INT4/RTC
2
1
0
DMAC0
XINT0
INT1
DMA channel 0 interrupt flag/mask bit
McBSP transmit 0 interrupt flag/mask bit
External user interrupt 1 flag/mask bit
61
April 2004 − Revised January 2005
SPRS245C
Functional Overview
3.10.2 Interrupt Timing
The external interrupts (INT[4:0]) are synchronized to the CPU by way of a two-flip-flop synchronizer. The
interrupt inputs are sampled on falling edges of the CPU clock. A sequence of 1-1-0-0-0 on consecutive cycles
on the interrupt pin is required for an interrupt to be detected. Therefore, the minimum low pulse duration on
the external interrupts on the 5503 is three CPU clock periods.
3.10.3 Waking Up From IDLE Condition
One of the following four events can wake up the CPU from IDLE:
•
•
•
Hardware Reset
External Interrupt
RTC Interrupt
3.10.3.1 Waking Up From IDLE With Oscillator Disabled
With an external interrupt or an RTC interrupt, the clock generation circuit wakes up the oscillator. In the case
of the interrupt being disabled by clearing the associated bit in the Interrupt Enable Register (IERx), the CPU
is not “woken up”. If the external interrupt serves as the wake-up event, the interrupt line must stay low for a
minimum of 3 CPU cycles after the oscillator is stabilized to wake up the CPU. Otherwise, only the clock
domain will wake up and another external interrupt will be needed to wake up the CPU.
3.10.4 Idling Clock Domain When External Parallel Bus Operating in EHPI Mode
The clock domain cannot be idled when the External Parallel Bus is operating in EHPI mode to ensure host
access to the DSP memory. To work around this restriction, use the HIDL bit of the External Bus Selection
Register (EBSR) with the CLKGENI bit of the Idle Control Register (ICR) to idle the clock domain.
62
SPRS245C
April 2004 − Revised January 2005
Support
4
Support
4.1 Notices Concerning JTAG (IEEE 1149.1) Boundary Scan Test Capability
4.1.1 Initialization Requirements for Boundary Scan Test
The TMS320VC5503 uses the JTAG port for boundary scan tests, emulation capability and factory test
purposes. To use boundary scan test, the EMU0 and EMU1/OFF pins must be held HIGH through a rising edge
of the TRST signal prior to the first scan. This operation selects the appropriate TAP control for boundary scan.
If at any time during a boundary scan test a rising edge of TRST occurs when EMU0 or EMU1/OFF are not
high, a factory test mode may be selected preventing boundary scan test from being completed. For this
reason, it is recommended that EMU0 and EMU1/OFF be pulled or driven high at all times during boundary
scan test.
4.1.2 Boundary Scan Description Language (BSDL) Model
BSDL models are available on the web in the TMS320VC5503 product folder under the “simulation models”
section.
4.2 Documentation Support
Extensive documentation supports all TMS320 DSP family of devices from product announcement through
applications development. The following types of documentation are available to support the design and use
of the TMS320C5000 platform of DSPs:
•
•
•
•
•
TMS320C55x DSP Functional Overview (literature number SPRU312)
Device-specific data sheets and data manuals
Complete user’s guides
Development support tools
Hardware and software application reports
TMS320C55x reference documentation includes, but is not limited to, the following:
•
•
•
•
•
•
•
•
•
TMS320C55x DSP CPU Reference Guide (literature number SPRU371)
TMS320C55x DSP Mnemonic Instruction Set Reference Guide (literature number SPRU374)
TMS320C55x DSP Algebraic Instruction Set Reference Guide (literature number SPRU375)
TMS320C55x DSP Programmer’s Guide (literature number SPRU376)
TMS320C55x DSP Peripherals Overview Reference Guide (literature number SPRU317)
TMS320C55x Optimizing C/C++ Compiler User’s Guide (literature number SPRU281)
TMS320C55x Assembly Language Tools User’s Guide (literature number SPRU280)
TMS320C55x DSP Library Programmer’s Reference (literature number SPRU422)
Using the TMS320VC5503/VC5507/VC5509/VC5509A Bootloader application report (literature number
SPRA375)
The reference guides describe in detail the TMS320C55x DSP products currently available and the
hardware and software applications, including algorithms, for fixed-point TMS320 DSP family of devices.
A series of DSP textbooks is published by Prentice-Hall and John Wiley & Sons to support digital signal
processing research and education. The TMS320 DSP newsletter, Details on Signal Processing, is
published quarterly and distributed to update TMS320 DSP customers on product information.
Information regarding TI DSP products is also available on the Worldwide Web at http://www.ti.com uniform
resource locator (URL).
TMS320 and TMS320C5000 are trademarks of Texas Instruments.
63
April 2004 − Revised January 2005
SPRS245C
Support
4.3 Device and Development-Support Tool Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all DSP
devices and support tools. Each DSP commercial family member has one of three prefixes: TMX, TMP, or TMS
(e.g., TMS320C6412GDK600). Texas Instruments recommends two of three possible prefix designators for
its support tools: TMDX and TMDS. These prefixes represent evolutionary stages of product development
from engineering prototypes (TMX/TMDX) through fully qualified production devices/tools (TMS/TMDS).
Device development evolutionary flow:
TMX Experimental device that is not necessarily representative of the final device’s electrical specifications
TMP Final silicon die that conforms to the device’s electrical specifications but has not completed quality
and reliability verification
TMS Fully qualified production device
Support tool development evolutionary flow:
TMDX Development-support product that has not yet completed Texas Instruments internal qualification
testing.
TMDS Fully qualified development-support product
TMX and TMP devices and TMDX development-support tools are shipped against the following disclaimer:
“Developmental product is intended for internal evaluation purposes.”
TMS devices and TMDS development-support tools have been characterized fully, and the quality and
reliability of the device have been demonstrated fully. TI’s standard warranty applies.
Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard
production devices. Texas Instruments recommends that these devices not be used in any production system
because their expected end-use failure rate still is undefined. Only qualified production devices are to be used.
4.4 TMS320VC5503 Device Nomenclature
TMS 320 VC 5503 GHH
PREFIX
TMX = Experimental device
TMP = Prototype device
TMS = Qualified device
†
SMJ = MIL-STD-883C
PACKAGE TYPE
SM
= High Rel (non-883C)
GHH
=
=
179-terminal plastic BGA
144-pin plastic LQFP
PGE
DEVICE FAMILY
320 = TMS320 family
DEVICE
55x DSP:
5503
TECHNOLOGY
VC
= Dual-Supply CMOS
†
BGA
=
Ball Grid Array
LQFP = Low-Profile Quad Flatpack
Figure 4−1. Device Nomenclature for the TMS320VC5503
64
SPRS245C
April 2004 − Revised January 2005
Electrical Specifications
5
Electrical Specifications
This section provides the absolute maximum ratings and the recommended operating conditions for the
TMS320VC5503 DSP.
All electrical and switching characteristics in this data manual are valid over the recommended operating
conditions unless otherwise specified.
5.1 Absolute Maximum Ratings
The list of absolute maximum ratings are specified over operating case temperature. Stresses beyond those
listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any other conditions beyond those indicated
under Section 5.2 is not implied. Exposure to absolute-maximum-rated conditions for extended periods may
affect device reliability. All voltage values are with respect to V . Figure 5−1 provides the test load circuit
SS
values for a 3.3-V I/O.
Supply voltage I/O range, DV
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 0.3 V to 4.0 V
DD
Supply voltage core range, CV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 0.3 V to 2.0 V
DD
Input voltage range, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 0.3 V to 4.5 V
I
Output voltage range, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 0.3 V to 4.5 V
O
Operating case temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 40°C to 85°C
C
Storage temperature range T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 55°C to 150°C
stg
65
April 2004 − Revised January 2005
SPRS245C
Electrical Specifications
5.2 Recommended Operating Conditions
5.2.1 Recommended Operating Conditions for CVDD = 1.2 V (108 MHz)
MIN
NOM
MAX
UNIT
Core
CV
Device supply voltage
1.14
1.2
1.26
V
DD
Peripherals
RCV
RDV
RTC module supply voltage, core
1.14
1.14
2.7
1.2
1.2
3.3
1.26
1.26
3.6
V
V
V
DD
DD
RTC module supply voltage, I/O (RTCINX1 and RTCINX2)
†
DV
Device supply voltage, I/O (except SDA and SCL)
DD
Grounds
V
V
Supply voltage, GND, I/O, and core
0
V
V
SS
IH
SDA & SCL: V related input
DD
0.7*DV
2.0
DV (max) +0.5
DD
DD
†
levels
High-level input voltage, I/O
Low-level input voltage, I/O
All other inputs
(including hysteresis inputs)
DV + 0.3
DD
SDA &SCL: V related input
levels
DD
−0.5
−0.3
0.3 * DV
0.8
DD
†
V
V
V
IL
All other inputs
(including hysteresis inputs)
Hysteresis level
Inputs with hysteresis only
All outputs
0.1*DV
V
hys
DD
I
High-level output current
−4
3
mA
OH
†
SDA and SCL
I
Low-level output current
mA
OL
All other outputs
4
T
Operating case temperature
−40
85
_C
C
†
2
The I C pins SDA and SCL do not feature fail-safe I/O buffers. These pins could potentially draw current when the device is powered down.
Due to the fact that different voltage devices can be connected to the I C bus, the level of logic 0 (low) and logic 1 (high) are not fixed and
2
depends on the associated V
.
DD
66
SPRS245C
April 2004 − Revised January 2005
Electrical Specifications
5.2.2 Recommended Operating Conditions for CVDD = 1.35 V (144 MHz)
MIN
NOM
MAX
UNIT
Core
CV
Device supply voltage
1.28
1.35
1.42
V
DD
Peripherals
RCV
RDV
RTC module supply voltage, core
1.28
1.28
2.7
1.35
1.35
3.3
1.42
1.42
3.6
V
V
V
DD
DD
RTC module supply voltage, I/O (RTCINX1 and RTCINX2)
†
DV
Device supply voltage, I/O (except SDA and SCL)
DD
Grounds
V
V
Supply voltage, GND, I/O, and core
0
V
V
SS
IH
SDA & SCL: V related input
DD
0.7*DV
2.0
DV (max) +0.5
DD
DD
†
levels
High-level input voltage, I/O
Low-level input voltage, I/O
All other inputs
(including hysteresis inputs)
DV + 0.3
DD
SDA &SCL: V related input
levels
DD
−0.5
−0.3
0.3 * DV
0.8
DD
†
V
V
V
IL
All other inputs
(including hysteresis inputs)
Hysteresis level
Inputs with hysteresis only
All outputs
0.1*DV
V
hys
DD
I
High-level output current
−4
3
mA
OH
†
SDA and SCL
I
Low-level output current
mA
OL
All other outputs
4
T
Operating case temperature
−40
85
_C
C
†
2
The I C pins SDA and SCL do not feature fail-safe I/O buffers. These pins could potentially draw current when the device is powered down.
Due to the fact that different voltage devices can be connected to the I C bus, the level of logic 0 (low) and logic 1 (high) are not fixed and
2
depends on the associated V
.
DD
67
April 2004 − Revised January 2005
SPRS245C
Electrical Specifications
5.2.3 Recommended Operating Conditions for CVDD = 1.6 V (200 MHz)
MIN
NOM
MAX
UNIT
Core
CV
Device supply voltage
1.55
1.6
1.65
V
DD
Peripherals
RCV
RDV
RTC module supply voltage, core
1.55
1.55
2.7
1.6
1.6
3.3
1.65
1.65
3.6
V
V
V
DD
DD
RTC module supply voltage, I/O (RTCINX1 and RTCINX2)
†
DV
Device supply voltage, I/O (except SDA and SCL)
DD
Grounds
V
V
Supply voltage, GND, I/O, and core
0
V
V
SS
IH
SDA & SCL: V related input
DD
0.7*DV
2.0
DV (max) +0.5
DD
DD
†
levels
High-level input voltage, I/O
Low-level input voltage, I/O
All other inputs
(including hysteresis inputs)
DV + 0.3
DD
SDA & SCL: V related input
levels
DD
−0.5
−0.3
0.3 * DV
0.8
DD
†
V
V
V
IL
All other inputs
(including hysteresis inputs)
Hysteresis level
Inputs with hysteresis only
All outputs
0.1*DV
V
hys
DD
I
High-level output current
−4
3
mA
OH
†
SDA and SCL
I
Low-level output current
mA
OL
All other outputs
4
T
Operating case temperature
−40
85
_C
C
†
2
The I C pins SDA and SCL do not feature fail-safe I/O buffers. These pins could potentially draw current when the device is powered down.
Due to the fact that different voltage devices can be connected to the I C bus, the level of logic 0 (low) and logic 1 (high) are not fixed and
2
depends on the associated V
.
DD
68
SPRS245C
April 2004 − Revised January 2005
Electrical Specifications
5.3 Electrical Characteristics
5.3.1
Electrical Characteristics Over Recommended Operating Case Temperature
Range for CVDD = 1.2 V (108 MHz) (Unless Otherwise Noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
DV = 2.7 V−3.6 V,
DD
V
V
High-level output voltage
All outputs
0.75 * DV
V
OH
OL
DD
I
= MAX
OH
†
SDA & SCL
At 3 mA sink current
= MAX
0
0.4
Low-level output voltage
V
All other outputs
I
0.4
OL
Output-only or
I/O pins with bus
keepers (enabled)
DV
= MAX,
DD
−300
−5
300
µA
5
V
= V to DV
SS
O
DD
DD
Input current for outputs in
high-impedance
I
IZ
All other output-only
or I/O pins
DV
= MAX
DD
V
= V to DV
SS
O
Input pins with
internal pulldown
(enabled)
DV
= MAX,
DD
30
300
V = V to DV
I
SS
DD
Input pins with
internal pullup
(enabled)
DV
= MAX,
DD
−300
−30
V = V to DV
I
SS
DD
I
Input current
µA
I
DV
= MAX,
DD
X2/CLKIN
−50
−5
50
5
V = V to DV
I
SS
DD
DD
All other input-only
pins
DV
= MAX,
DD
V = V to DV
I
SS
CV = 1.2 V
CPU clock = 108 MHz
DD
mA/
MHz
‡
I
I
I
I
CV supply current, CPU + internal memory access
0.45
5.5
100
10
DDC
DDP
DDC
DDP
DD
T
= 25_C
C
DV = 3.3 V
DD
§
DV supply current, pins active
CPU clock = 108 MHz
mA
µA
µA
DD
T
= 25_C
C
Oscillator disabled. CV = 1.2 V
DD
¶
CV supply current, standby
DD
All domains in
T
= 25_C
C
low-power state
(Nominal Process)
Oscillator disabled. DV = 3.3 V
DD
DV supply current, standby
All domains in
No I/O activity
DD
low-power state.
T
= 25_C
C
C
C
Input capacitance
Output capacitance
3
3
pF
pF
i
o
†
‡
2
The I C pins SDA and SCL do not feature fail-safe I/O buffers. These pins could potentially draw current when the device is powered down.
CPU executing 75% Dual MAC + 25% ADD with moderate data bus activity (table of sine values). CPU and CLKGEN (DPLL) domain are active.
All other domains are idled.
§
¶
One word of a table of a 16-bit sine value is written to the EMIF every 250 ns (64 Mbps). Each EMIF output pin is connected to a 10-pF load.
In CLKGEN domain idle mode, X2/CLKIN becomes output and is driven low to stop external crystals (if used) from oscillating. Standby current
will be higher if an external clock source tries to drive the X2/CLKIN pin during this time.
69
April 2004 − Revised January 2005
SPRS245C
Electrical Specifications
5.3.2 Electrical Characteristics Over Recommended Operating Case Temperature
Range for CVDD = 1.35 V (144 MHz) (Unless Otherwise Noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
DV = 2.7 V−3.6 V,
DD
V
V
High-level output voltage
All outputs
0.75 * DV
V
OH
OL
DD
I
= MAX
OH
†
SDA & SCL
At 3 mA sink current
= MAX
0
0.4
Low-level output voltage
V
All other outputs
I
0.4
OL
Output-only or
I/O pins with bus
keepers (enabled)
DV
= MAX,
DD
−300
−5
300
µA
5
V
= V to DV
SS
O
DD
DD
Input current for outputs in
high-impedance
I
IZ
All other output-only
or I/O pins
DV
= MAX
DD
V
= V to DV
SS
O
Input pins with
internal pulldown
(enabled)
DV
= MAX,
DD
30
300
V = V to DV
I
SS
DD
Input pins with
internal pullup
(enabled)
DV
= MAX,
DD
−300
−30
V = V to DV
I
SS
DD
I
Input current
µA
I
DV
= MAX,
DD
X2/CLKIN
−50
−5
50
5
V = V to DV
I
SS
DD
DD
All other input-only
pins
DV
= MAX,
DD
V = V to DV
I
SS
CV = 1.35 V
CPU clock = 144 MHz
DD
mA/
MHz
‡
I
I
I
I
CV supply current, CPU + internal memory access
0.51
5.5
125
10
DDC
DDP
DDC
DDP
DD
T
= 25_C
C
DV = 3.3 V
DD
§
DV supply current, pins active
CPU clock = 144 MHz
mA
µA
µA
DD
T
= 25_C
C
Oscillator disabled. CV = 1.35 V
DD
¶
CV supply current, standby
DD
All domains in
T
= 25_C
C
low-power state
(Nominal Process)
Oscillator disabled. DV = 3.3 V
DD
DV supply current, standby
All domains in
No I/O activity
DD
low-power state.
T
= 25_C
C
C
C
Input capacitance
Output capacitance
3
3
pF
pF
i
o
†
‡
2
The I C pins SDA and SCL do not feature fail-safe I/O buffers. These pins could potentially draw current when the device is powered down.
CPU executing 75% Dual MAC + 25% ADD with moderate data bus activity (table of sine values). CPU and CLKGEN (DPLL) domain are active.
All other domains are idled.
§
¶
One word of a table of a 16-bit sine value is written to the EMIF every 250 ns (64 Mbps). Each EMIF output pin is connected to a 10-pF load.
In CLKGEN domain idle mode, X2/CLKIN becomes output and is driven low to stop external crystals (if used) from oscillating. Standby current
will be higher if an external clock source tries to drive the X2/CLKIN pin during this time.
70
SPRS245C
April 2004 − Revised January 2005
Electrical Specifications
5.3.3
Electrical Characteristics Over Recommended Operating Case Temperature
Range for CVDD = 1.6 V (200 MHz) (Unless Otherwise Noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
DV = 2.7 V−3.6 V,
DD
V
V
High-level output voltage
All outputs
0.75 * DV
V
OH
OL
DD
I
= MAX
OH
†
SDA & SCL
At 3 mA sink current
= MAX
0
0.4
Low-level output voltage
V
All other outputs
I
0.4
OL
Output-only or
I/O pins with bus
keepers (enabled)
DV
= MAX,
DD
−300
−5
300
µA
5
V
= V to DV
SS
O
DD
DD
Input current for outputs in
high-impedance
I
IZ
All other output-only
or I/O pins
DV
= MAX
DD
V
= V to DV
SS
O
Input pins with
internal pulldown
(enabled)
DV
= MAX,
DD
30
300
V = V to DV
I
SS
DD
Input pins with
internal pullup
(enabled)
DV
= MAX,
DD
−300
−30
V = V to DV
I
SS
DD
I
Input current
µA
I
DV
= MAX,
DD
X2/CLKIN
−50
−5
50
5
V = V to DV
I
SS
DD
DD
All other input-only
pins
DV
= MAX,
DD
V = V to DV
I
SS
CV = 1.6 V
CPU clock = 200 MHz
DD
mA/
MHz
‡
I
I
I
I
CV supply current, CPU + internal memory access
0.60
5.5
150
10
DDC
DDP
DDC
DDP
DD
T
= 25_C
C
DV = 3.3 V
DD
§
DV supply current, pins active
CPU clock = 200 MHz
mA
µA
µA
DD
T
= 25_C
C
Oscillator disabled. CV = 1.6 V
DD
¶
CV supply current, standby
DD
All domains in
T
= 25_C
C
low-power state
(Nominal Process)
Oscillator disabled. DV = 3.3 V
DD
DV supply current, standby
All domains in
No I/O activity
DD
low-power state.
T
= 25_C
C
C
C
Input capacitance
Output capacitance
3
3
pF
pF
i
o
†
‡
2
The I C pins SDA and SCL do not feature fail-safe I/O buffers. These pins could potentially draw current when the device is powered down.
CPU executing 75% Dual MAC + 25% ADD with moderate data bus activity (table of sine values). CPU and CLKGEN (DPLL) domain are active.
All other domains are idled.
§
¶
One word of a table of a 16-bit sine value is written to the EMIF every 250 ns (64 Mbps). Each EMIF output pin is connected to a 10-pF load.
In CLKGEN domain idle mode, X2/CLKIN becomes output and is driven low to stop external crystals (if used) from oscillating. Standby current
will be higher if an external clock source tries to drive the X2/CLKIN pin during this time.
71
April 2004 − Revised January 2005
SPRS245C
Electrical Specifications
Tester Pin Electronics
Transmission Line
Data Manual Timing Reference Point
Output
Under
Test
42 Ω
3.5 nH
Z0 = 50 Ω
(see note)
Device Pin
(see note)
4.0 pF
1.85 pF
NOTE: The data manual provides timing at the device pin. For output timing analysis, the tester pin electronics and its transmission line effects
must be taken into account. A transmission line with a delay of 2 ns or longer can be used to produce the desired transmission line effect.
The transmission line is intended as a load only. It is not necessary to add or subtract the transmission line delay (2 ns or longer) from
the data manual timings.
Input requirements in this data manual are tested with an input slew rate of < 4 Volts per nanosecond (4 V/ns) at the device
pin.
Figure 5−1. 3.3-V Test Load Circuit
5.4 ESD Performance
ESD stress levels were performed in compliance with the following JEDEC standards with the results indicated
below:
•
•
Charged Device Model (CDM), based on JEDEC Specification JESD22-C101, passed at 500 V
Human Body Model (HBM), based on JEDEC Specification JESD22-A114, passed at 1500 V
NOTE:
According to industry research publications, ESD-CDM testing results show better correlation
to manufacturing line and field failure rates than ESD-HBM testing. 500-V CDM is commonly
considered as a safe passing level.
5.5 Timing Parameter Symbology
Timing parameter symbols used in the timing requirements and switching characteristics tables are created
in accordance with JEDEC Standard 100. To shorten the symbols, some of the pin names and other related
terminology have been abbreviated as follows:
Lowercase subscripts and their meanings:
Letters and symbols and their meanings:
a
access time
H
L
High
c
cycle time (period)
delay time
Low
d
V
Z
Valid
dis
en
f
disable time
High-impedance
enable time
fall time
h
hold time
r
rise time
su
t
setup time
transition time
valid time
v
w
X
pulse duration (width)
Unknown, changing, or don’t care level
72
SPRS245C
April 2004 − Revised January 2005
Electrical Specifications
5.6 Clock Options
The frequency of the reference clock provided at the X2/CLKIN pin can be divided by a factor of two or four
or multiplied by one of several values to generate the internal machine cycle.
5.6.1 Internal System Oscillator With External Crystal
The internal oscillator is always enabled following a device reset. The oscillator requires an external crystal
connected across the X1 and X2/CLKIN pins. If the internal oscillator is not used, an external clock source
must be applied to the X2/CLKIN pin and the X1 pin should be left unconnected. Since the internal oscillator
can be used as a clock source to the PLLs, the crystal oscillation frequency can be multiplied to generate the
CPU clock, if desired.
The crystal should be in fundamental-mode operation, and parallel resonant, with a maximum effective series
resistance (ESR) specified in Table 5−1. The connection of the required circuit is shown in Figure 5−2. Under
some conditions, all the components shown are not required. The capacitors, C and C , should be chosen
1
2
such that the equation below is satisfied. C in the equation is the load specified for the crystal that is also
L
specified in Table 5−1.
C1C2
CL +
(C1 ) C2)
X2/CLKIN
X1
R
S
Crystal
C1
C2
Figure 5−2. Internal System Oscillator With External Crystal
Table 5−1. Recommended Crystal Parameters
FREQUENCY RANGE (MHz)
MAX ESR (Ω)
TYP C
(pF)
MAX C
(pF)
R (Ω)
S
LOAD
SHUNT
20−15
15−12
12−10
10−8
8−6
20
30
40
60
80
80
10
7
0
16
16
18
18
18
7
7
7
7
7
0
100
470
1.5k
2.2k
6−5
Although the recommended ESR presented in Table 5−1 is maximum, theoretically a crystal with a lower
maximum ESR might seem to meet the requirement. It is recommended that crystals which meet the
maximum ESR specification in Table 5−1 are used.
73
April 2004 − Revised January 2005
SPRS245C
Electrical Specifications
5.6.2 Layout Considerations
Since parasitic capacitance, inductance and resistance can be significant in any circuit, good PC board layout
practices should always be observed when planning trace routing to the discrete components used in the
oscillator circuit. Specifically, the crystal and the associated discrete components should be located as close
to the DSP as physically possible. Also, X1 and X2/CLKIN traces should be separated as soon as possible
after routing away from the DSP to minimize parasitic capacitance between them, and a ground trace should
be run between these two signal lines. This also helps to minimize stray capacitance between these two
signals.
74
SPRS245C
April 2004 − Revised January 2005
Electrical Specifications
5.6.3 Clock Generation in Bypass Mode (DPLL Disabled)
The frequency of the reference clock provided at the X2/CLKIN pin can be divided by a factor of one, two, or
four to generate the internal CPU clock cycle. The divide factor (D) is set in the BYPASS_DIV field of the clock
mode register. The contents of this field only affect clock generation while the device is in bypass mode. In
this mode, the digital phase-locked loop (DPLL) clock synthesis is disabled.
Table 5−2 and Table 5−3 assume testing over recommended operating conditions and H = 0.5t
Figure 5−3).
(see
c(CO)
Table 5−2. CLKIN Timing Requirements
CV = 1.2 V
DD
CV = 1.6 V
DD
CV = 1.35 V
DD
NO.
UNIT
MIN
MAX
MIN
MAX
†
†
C1
C2
t
t
t
t
t
Cycle time, X2/CLKIN
Fall time, X2/CLKIN
20
400
20
400
ns
ns
ns
ns
ns
c(CI)
4
4
4
4
f(CI)
C3
Rise time, X2/CLKIN
r(CI)
C10
C11
Pulse duration, CLKIN low
Pulse duration, CLKIN high
6
6
6
6
w(CIL)
w(CIH)
†
This device utilizes a fully static design and therefore can operate with t
time is limited by the crystal frequency range listed in Table 5−1.
approaching ∞. If an external crystal is used, the X2/CLKIN cycle
c(CI)
Table 5−3. CLKOUT Switching Characteristics
CV = 1.2 V
DD
CV = 1.6 V
DD
CV = 1.35 V
DD
NO.
UNIT
PARAMETER
MIN
TYP
MAX
MIN
TYP
MAX
‡
§
†
‡
§
†
C4
C5
t
t
Cycle time, CLKOUT
20
D*t
1600
20
D*t
c(CI)
1600
ns
ns
c(CO)
c(CI)
Delay time, X2/CLKIN high to CLKOUT
high/low
5
15
25
5
15
25
d(CI-CO)
C6
C7
C8
C9
t
t
t
t
Fall time, CLKOUT
1
1
ns
ns
ns
ns
f(CO)
Rise time, CLKOUT
1
1
r(CO)
Pulse duration, CLKOUT low
Pulse duration, CLKOUT high
H − 1
H − 1
H + 1
H + 1
H − 1
H − 1
H + 1
H + 1
w(COL)
w(COH)
†
This device utilizes a fully static design and therefore can operate with t
time is limited by the crystal frequency range listed in Table 5−1.
It is recommended that the DPLL synthesised clocking option be used to obtain maximum operating frequency.
D = 1/(PLL Bypass Divider)
approaching ∞. If an external crystal is used, the X2/CLKIN cycle
c(CO)
‡
§
C2
C1
C11
C3
C10
X2/CLKIN
CLKOUT
C4
C9
C7
C5
C6
C8
NOTE A: The relationship of X2/CLKIN to CLKOUT depends on the PLL bypass divide factor chosen for the CLKMD register. The waveform
relationship shown in Figure 5−3 is intended to illustrate the timing parameters based on CLKOUT = 1/2(CLKIN) configuration.
Figure 5−3. Bypass Mode Clock Timings
75
April 2004 − Revised January 2005
SPRS245C
Electrical Specifications
5.6.4 Clock Generation in Lock Mode (DPLL Synthesis Enabled)
The frequency of the reference clock provided at the X2/CLKIN pin can be multiplied by a synthesis factor of
N to generate the internal CPU clock cycle. The synthesis factor is determined by:
M
DL
N=
where: M = the multiply factor set in the PLL_MULT field of the clock mode register
D = the divide factor set in the PLL_DIV field of the clock mode register
L
Valid values for M are (multiply by) 2 to 31. Valid values for D are (divide by) 1, 2, 3, and 4.
L
For detailed information on clock generation configuration, see the TMS320C55x DSP Peripherals Overview
Reference Guide (literature number SPRU317).
Table 5−4 and Table 5−5 assume testing over recommended operating conditions and H = 0.5t
Figure 5−4).
(see
c(CO)
Table 5−4. Multiply-By-N Clock Option Timing Requirements
CV = 1.2 V
DD
CV = 1.6 V
DD
CV = 1.35 V
DD
NO.
UNIT
MIN
MAX
MIN
MAX
400
4
†
†
C1
C2
t
t
t
t
t
Cycle time, X2/CLKIN
Fall time, X2/CLKIN
DPLL synthesis enabled
20
400
4
20
ns
ns
ns
ns
ns
c(CI)
f(CI)
C3
Rise time, X2/CLKIN
4
4
r(CI)
C10
C11
Pulse duration, CLKIN low
Pulse duration, CLKIN high
6
6
6
6
w(CIL)
w(CIH)
†
The clock frequency synthesis factor and minimum X2/CLKIN cycle time should be chosen such that the resulting CLKOUT cycle time is within
the specified range (t ). If an external crystal is used, the X2/CLKIN cycle time is limited by the crystal frequency range listed in Table 5−1.
c(CO)
Table 5−5. Multiply-By-N Clock Option Switching Characteristics
CV = 1.2 V
CV = 1.35 V
CV = 1.6 V
DD
DD
DD
NO.
C4
C6
C7
C8
C9
PARAMETER
UNIT
ns
MIN
TYP
MAX
MIN
TYP
MAX
MIN
TYP
MAX
Cycle time,
CLKOUT
‡
‡
‡
t
t
t
t
t
9.26
t
N
c(CI)*
1600
6.95
t
N
c(CI)*
1600
5
t
N
c(CI)*
1600
c(CO)
f(CO)
Fall time,
CLKOUT
1
1
1
1
ns
Rise time,
CLKOUT
1
1
ns
r(CO)
Pulse duration,
CLKOUT low
H − 1
H − 1
H + 1
H + 1
H − 1
H − 1
H + 1
H + 1
H − 1
H − 1
H + 1
H + 1
ns
w(COL)
w(COH)
Pulse duration,
CLKOUT high
ns
Delay time,
X2/CLKIN high/
low to CLKOUT
high/low
C12
t
5
15
25
5
15
25
5
15
25
ns
d(CI–CO)
‡
N = Clock frequency synthesis factor
76
SPRS245C
April 2004 − Revised January 2005
Electrical Specifications
C2
C3
C11
C10
C1
X2/CLKIN
CLKOUT
C9
C8
C6
C12
C4
C7
Bypass Mode
NOTE A: The relationship of X2/CLKIN to CLKOUT depends on the PLL multiply and divide factor chosen for the CLKMD register. The waveform
relationship shown in Figure 5−3 is intended to illustrate the timing parameters based on CLKOUT = 1xCLKIN configuration.
Figure 5−4. External Multiply-by-N Clock Timings
5.6.5 Real-Time Clock Oscillator With External Crystal
The real-time clock module includes an oscillator circuit. The oscillator requires an external 32.768-kHz crystal
connected across the RTCINX1 and RTCINX2 pins. The connection of the required circuit, consisting of the
crystal and two load capacitors, is shown in Figure 5−5. The load capacitors, C and C , should be chosen
1
2
such that the equation below is satisfied. C in the equation is the load specified for the crystal.
L
C1C2
CL +
(C1 ) C2)
RTCINX1
RTCINX2
Crystal
32.768 kHz
C1
C2
Figure 5−5. Real-Time Clock Oscillator With External Crystal
NOTE: The RTC can be idled by not supplying its 32-kHz oscillator signal. In order to keep
RTC power dissipation to a minimum when the RTC module is not used, it is recommended
that the RTC module be powered up, the RTC input pin (RTCINX1) be pulled low, and the RTC
output pin (RTCINX2) be left floating.
Table 5−6. Recommended RTC Crystal Parameters
PARAMETER
MIN
NOM
MAX UNIT
†
f
Frequency of oscillation
32.768
kHz
o
†
ESR
Series resistance
30
60
kΩ
pF
C
L
Load capacitance
Crystal drive level
12.5
DL
1
µW
†
ESR must be 200 kΩ or greater at frequencies other than 32.768kHz. Otherwise, oscillations at overtone frequencies may occur.
77
April 2004 − Revised January 2005
SPRS245C
Electrical Specifications
5.7 Memory Interface Timings
5.7.1 Asynchronous Memory Timings
Table 5−7 and Table 5−8 assume testing over recommended operating conditions (see Figure 5−6 and
Figure 5−7).
Table 5−7. Asynchronous Memory Cycle Timing Requirements
CV = 1.2 V
DD
CV = 1.6 V
DD
CV = 1.35 V
DD
NO.
UNIT
MIN
6
MAX
MIN
5
MAX
†
M1
M2
M3
M4
t
t
t
t
Setup time, read data valid before CLKOUT high
Hold time, read data valid after CLKOUT high
ns
ns
ns
ns
su(DV-COH)
h(COH-DV)
0
0
†
Setup time, ARDY valid before CLKOUT high
10
0
7
su(ARDY-COH)
h(COH-ARDY)
Hold time, ARDY valid after CLKOUT high
0
†
To ensure data setup time, simply program the strobe width wide enough. ARDY is internally synchronized. If ARDY does meet setup or hold
time, it may be recognized in the current cycle or the next cycle. Thus, ARDY can be an asynchronous input.
Table 5−8. Asynchronous Memory Cycle Switching Characteristics
CV = 1.2 V
DD
CV = 1.6 V
DD
CV = 1.35 V
DD
NO.
PARAMETER
UNIT
MIN
−2
MAX
MIN
−2
MAX
M5
M6
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Delay time, CLKOUT high to CEx valid
Delay time, CLKOUT high to CEx invalid
Delay time, CLKOUT high to BEx valid
Delay time, CLKOUT high to BEx invalid
Delay time, CLKOUT high to address valid
Delay time, CLKOUT high to address invalid
Delay time, CLKOUT high to AOE valid
Delay time, CLKOUT high to AOE invalid
Delay time, CLKOUT high to ARE valid
Delay time, CLKOUT high to ARE invalid
Delay time, CLKOUT high to data valid
Delay time, CLKOUT high to data invalid
Delay time, CLKOUT high to AWE valid
Delay time, CLKOUT high to AWE invalid
4
4
4
4
4
4
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
d(COH-CEV)
d(COH-CEIV)
d(COH-BEV)
d(COH-BEIV)
d(COH-AV)
−2
−2
M7
M8
−2
−2
M9
4
4
M10
M11
M12
M13
M14
M15
M16
M17
M18
−2
−2
−2
−2
−2
−2
−2
−2
−2
−2
d(COH-AIV)
4
4
4
4
4
4
4
4
4
4
d(COH-AOEV)
d(COH-AOEIV)
d(COH-AREV)
d(COH-AREIV)
d(COH-DV)
−2
−2
−2
−2
−2
−2
d(COH-DIV)
4
4
4
4
d(COH-AWEV)
d(COH-AWEIV)
78
SPRS245C
April 2004 − Revised January 2005
Electrical Specifications
Hold
= 1
Extended
Hold = 2
Setup = 2
M5
Strobe = 5
Not Ready = 2
†
CLKOUT
M6
‡
CEx
M7
M8
BEx
M9
M10
§
A[20:0]
M2
M1
D[15:0]
AOE
M11
M12
M13
M14
ARE
AWE
M4
M4
M3
M3
ARDY
†
‡
§
CLKOUT is equal to CPU clock
CEx becomes active depending on the memory address space being accessed
A[13:0] for LQFP
Figure 5−6. Asynchronous Memory Read Timings
79
April 2004 − Revised January 2005
SPRS245C
Electrical Specifications
Extended
Hold = 2
Setup = 2
Strobe = 5
Not Ready = 2
Hold = 1
†
CLKOUT
M5
M7
M9
M6
M8
‡
CEx
BEx
M10
M16
§
A[20:0]
M15
D[15:0]
AOE
ARE
M17
M18
AWE
M4
M3
M4
M3
ARDY
†
CLKOUT is equal to CPU clock
CEx becomes active depending on the memory address space being accessed
A[13:0] for LQFP
‡
§
Figure 5−7. Asynchronous Memory Write Timings
80
SPRS245C
April 2004 − Revised January 2005
Electrical Specifications
5.7.2 Synchronous DRAM (SDRAM) Timings
Table 5−9 and Table 5−10 assume testing over recommended operating conditions (see Figure 5−8 through
Figure 5−14).
Table 5−9. Synchronous DRAM Cycle Timing Requirements
CV = 1.2 V
DD
CV = 1.6 V
DD
CV = 1.35 V
DD
NO.
UNIT
MIN
MAX
MIN
MAX
M19
M20
M21
t
t
t
Setup time, read data valid before CLKMEM high
Hold time, read data valid after CLKMEM high
Cycle time, CLKMEM
3
3
ns
ns
ns
su(DV-CLKMEMH)
h(CLKMEMH-DV)
c(CLKMEM)
2
2
†
‡
9.26
7.52
†
‡
Maximum SDRAM operating frequency = 108 MHz. Actual attainable maximum operating frequency will depend on the quality of the PC board
design and the memory chip timing requirement.
Maximum SDRAM operating frequency = 133 MHz. Actual attainable maximum operating frequency will depend on the quality of the PC board
design and the memory chip timing requirement.
Table 5−10. Synchronous DRAM Cycle Switching Characteristics
CV = 1.2 V
DD
CV = 1.6 V
DD
CV = 1.35 V
DD
NO.
PARAMETER
UNIT
MIN
1.2
1.2
1.2
1.2
1.2
1.2
1.2
1.2
1.2
1.2
1.2
1.2
1.2
1.2
1.2
1.2
MAX
7
MIN
1.2
1.2
1.2
1.2
1.2
1.2
1.2
1.2
1.2
1.2
1.2
1.2
1.2
1.2
1.2
1.2
MAX
M22
M23
M24
M25
M26
M27
M28
M29
M30
M31
M32
M33
M34
M35
M36
M37
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Delay time, CLKMEM high to CEx low
Delay time, CLKMEM high to CEx high
Delay time, CLKMEM high to BEx valid
Delay time, CLKMEM high to BEx invalid
Delay time, CLKMEM high to address valid
Delay time, CLKMEM high to address invalid
Delay time, CLKMEM high to SDCAS low
Delay time, CLKMEM high to SDCAS high
Delay time, CLKMEM high to data valid
Delay time, CLKMEM high to data invalid
Delay time, CLKMEM high to SDWE low
Delay time, CLKMEM high to SDWE high
Delay time, CLKMEM high to SDA10 valid
Delay time, CLKMEM high to SDA10 invalid
Delay time, CLKMEM high to SDRAS low
Delay time, CLKMEM high to SDRAS high
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
d(CLKMEMH-CEL)
7
d(CLKMEMH-CEH)
d(CLKMEMH-BEV)
7
7
d(CLKMEMH-BEIV)
d(CLKMEMH-AV)
7
7
d(CLKMEMH-AIV)
7
d(CLKMEMH-SDCASL)
d(CLKMEMH-SDCASH)
d(CLKMEMH-DV)
7
7
7
d(CLKMEMH-DIV)
7
d(CLKMEMH-SDWEL)
d(CLKMEMH-SDWEH)
d(CLKMEMH-SDA10V)
d(CLKMEMH-SDA10IV)
d(CLKMEMH-SDRASL)
d(CLKMEMH-SDRASH)
7
7
7
7
7
M38
M39
t
t
Delay time, CLKMEM high to CKE low
Delay time, CLKMEM high to CKE high
1.2
1.2
7
7
1.2
1.2
5
5
ns
ns
d(CLKMEMH–CKEL)
d(CLKMEMH–CKEH)
81
April 2004 − Revised January 2005
SPRS245C
Electrical Specifications
READ
READ
READ
M21
CLKMEM
M22
M23
M27
†
CEx
M24
M26
‡
BEx
CA1
CA2
CA3
EMIF.A[13:0]
M19
M20
D[15:0]
SDA10
SDRAS
SDCAS
D1
D2
D3
M34
M28
M35
M29
SDWE
†
The chip enable that becomes active depends on the address being accessed.
All BE[1:0] signals are driven low (active) during reads. Byte manipulation of the read data is performed inside the EMIF. These signals remain
active until the next access that is not an SDRAM read occurs.
‡
Figure 5−8. Three SDRAM Read Commands
82
SPRS245C
April 2004 − Revised January 2005
Electrical Specifications
WRITE
WRITE
WRITE
CLKMEM
M22
M24
M26
M23
†
CEx
M25
M27
M31
‡
BEx
BE1
CA1
D1
BE2
CA2
D2
BE3
CA3
EMIF.A[13:0]
M30
M34
D[15:0]
SDA10
SDRAS
SDCAS
SDWE
D3
M35
M28
M32
M29
M33
†
‡
The chip enable that becomes active depends on the address being accessed.
All BE[1:0] signals are driven low (active) during reads. Byte manipulation of the read data is performed inside the EMIF. These signals remain
active until the next access that is not an SDRAM read occurs.
Figure 5−9. Three SDRAM WRT Commands
83
April 2004 − Revised January 2005
SPRS245C
Electrical Specifications
ACTV
CLKMEM
M22
M26
M23
†
CEx
‡
BEx
EMIF.A[13:0]
D[15:0]
Bank Activate/Row Address
M34
M36
SDA10
M37
SDRAS
SDCAS
SDWE
†
The chip enable that becomes active depends on the address being accessed.
All BE[1:0] signals are driven low (active) during reads. Byte manipulation of the read data is performed inside the EMIF. These signals remain
active until the next access that is not an SDRAM read occurs.
‡
Figure 5−10. SDRAM ACTV Command
84
SPRS245C
April 2004 − Revised January 2005
Electrical Specifications
DCAB
CLKMEM
M22
M23
†
CEx
‡
BEx
EMIF.A[13:0]
D[15:0]
M35
M37
M34
M36
SDA10
SDRAS
SDCAS
M33
M32
SDWE
†
‡
The chip enable that becomes active depends on the address being accessed.
All BE[1:0] signals are driven low (active) during reads. Byte manipulation of the read data is performed inside the EMIF. These signals remain
active until the next access that is not an SDRAM read occurs.
Figure 5−11. SDRAM DCAB Command
85
April 2004 − Revised January 2005
SPRS245C
Electrical Specifications
REFR
CLKMEM
M22
M23
†
CEx
‡
BEx
EMIF.A[13:0]
D[15:0]
SDA10
M37
M29
M36
M28
SDRAS
SDCAS
SDWE
†
The chip enable that becomes active depends on the address being accessed.
All BE[1:0] signals are driven low (active) during reads. Byte manipulation of the read data is performed inside the EMIF. These signals
remain active until the next access that is not an SDRAM read occurs.
‡
Figure 5−12. SDRAM REFR Command
86
SPRS245C
April 2004 − Revised January 2005
Electrical Specifications
MRS
CLKMEM
M22
M23
†
CEx
‡
BEx
M26
M27
§
EMIF.A[13:0]
D[15:0]
MRS Value 0x30
SDA10
M37
M29
M33
M36
M28
M32
SDRAS
SDCAS
SDWE
†
The chip enable that becomes active depends on the address being accessed.
All BE[1:0] signals are driven low (active) during reads. Byte manipulation of the read data is performed inside the EMIF. These signals remain
‡
active until the next access that is not an SDRAM read occurs.
Write burst length = 1
§
Read latency = 3
Burst type = 0 (serial)
Burst length = 1
Figure 5−13. SDRAM MRS Command
87
April 2004 − Revised January 2005
SPRS245C
Electrical Specifications
Exit Self-Refresh
Enter Self-Refresh
CLKMEM
M38
M22
M39
M23
CKE
(XF or GPIO4)
CEx
M36
M28
SDRAS
SDCAS
SDWE
SDA10
Figure 5−14. SDRAM Self-Refresh Command
88
SPRS245C
April 2004 − Revised January 2005
Electrical Specifications
5.8 Reset Timings
5.8.1 Power-Up Reset (On-Chip Oscillator Active)
Table 5−11 assumes testing over recommended operating conditions (see Figure 5−15).
Table 5−11. Power-Up Reset (On-Chip Oscillator Active) Timing Requirements
CV = 1.2 V
DD
CV = 1.6 V
DD
CV = 1.35 V
DD
NO.
UNIT
MIN
MAX
MIN
MAX
†
‡
‡
R1
t
Hold time, RESET low after oscillator stable
3P
3P
ns
h(SUPSTBL-RSTL)
†
‡
Oscillator stable time depends on the crystal characteristic (i.e., frequency, ESR, etc.) which varies from one crystal manufacturer to another.
Based on the crystal characteristics, the oscillator stable time can be in the range of a few to 10s of ms. A reset circuit with 100 ms or more delay
time will ensure the oscillator stabilized before the RESET goes high.
P = 1/(input clock frequency) in ns. For example, when input clock is 12 MHz, P = 83.33 ns.
CLKOUT
CV
DV
DD
DD
R1
RESET
Figure 5−15. Power-Up Reset (On-Chip Oscillator Active) Timings
89
April 2004 − Revised January 2005
SPRS245C
Electrical Specifications
5.8.2 Power-Up Reset (On-Chip Oscillator Inactive)
Table 5−12 and Table 5−13 assume testing over recommended operating conditions (see Figure 5−16).
Table 5−12. Power-Up Reset (On-Chip Oscillator Inactive) Timing Requirements
CV = 1.2 V
DD
CV = 1.6 V
DD
CV = 1.35 V
DD
NO.
UNIT
MIN
MAX
MIN
MAX
†
†
R2
t
Hold time, CLKOUT valid to RESET low
3P
3P
ns
h(CLKOUTV-RSTL)
†
P = 1/(input clock frequency) in ns. For example, when input clock is 12 MHz, P = 83.33 ns.
Table 5−13. Power-Up Reset (On-Chip Oscillator Inactive) Switching Characteristics
CV = 1.2 V
DD
CV = 1.6 V
DD
CV = 1.35 V
DD
NO.
PARAMETER
UNIT
MIN
MAX
MIN
MAX
30
R3
t
Delay time, CLKIN valid to CLKOUT valid
30
ns
d(CLKINV-CLKOUTV)
X2/CLKIN
CLKOUT
R3
CV
DV
DD
DD
R2
RESET
Figure 5−16. Power-Up Reset (On-Chip Oscillator Inactive) Timings
90
SPRS245C
April 2004 − Revised January 2005
Electrical Specifications
5.8.3 Warm Reset
Table 5−14 and Table 5−15 assume testing over recommended operating conditions (see Figure 5−17).
Table 5−14. Reset Timing Requirements
CV = 1.2 V
DD
CV = 1.6 V
DD
CV = 1.35 V
DD
NO.
UNIT
MIN
MAX
MIN
MAX
†
†
R4
t
Pulse width, reset low
3P
3P
ns
w(RSL)
†
P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
†
Table 5−15. Reset Switching Characteristics
CV = 1.2 V
DD
CV = 1.6 V
DD
CV = 1.35 V
DD
NO.
PARAMETER
UNIT
MIN
MAX
MIN
MAX
‡
R5
R6
R7
R8
t
t
t
t
Delay time, reset high to BK group valid
38P + 15
38P + 15
1P + 15
38P + 15
38P + 15
1P + 15
ns
ns
ns
ns
d(RSTH-BKV)
d(RSTH-HIGHV)
d(RSTL-ZIV)
§
Delay time, reset high to High group valid
¶
Delay time, reset low to Z group invalid
¶
Delay time, reset high to Z group valid
38P + 15
38P + 15
d(RSTH-ZV)
†
‡
P = 1/CPU clock frequency in ns. For example, when CPU is running at 200 MHz, P = 5 ns.
BK group: Pins with bus keepers, holds previous state during reset. Following low-to-high transition of RESET, these pins go to their post-reset
logic state.
BK group pins: A’[0], A[15:0], D[15:0], C[14:2], C0, GPIO5, DX1, and DX2
High group: Following low-to-high transition of RESET, these pins go to logic-high state.
High group pins: C1[HPI.HINT], XF
Z group: Bidirectional pins which become input or output pins. Following low-to-high transition of RESET, these pins go to high-impedance state.
Z group pins: C1[EMIF.AOE], GPIO[7:6, 4:0], TIN/TOUT0, SDA, SCL, CLKR0, FSR0, CLKX0, DX0, FSX0, FSX2, CLKX2, FSR2, DR2, CLKR2,
FSX1, CLKX1, FSR1, DR1, CLKR1, A[20:16]
§
¶
RESET
R5
†
BK Group
R6
‡
High Group
R7
R8
§
Z Group
†
BK group pins: A’[0], A[15:0], D[15:0], C[14:2], C0, GPIO5, DX1, and DX2
High group pins: C1[HPI.HINT], XF
Z group pins: C1[EMIF.AOE], GPIO[7:6, 4:0], TIN/TOUT0, SDA, SCL, CLKR0, FSR0, CLKX0, DX0, FSX0, FSX2, CLKX2, FSR2, DR2, CLKR2,
FSX1, CLKX1, FSR1, DR1, CLKR1, A[20:16]
‡
§
Figure 5−17. Reset Timings
91
April 2004 − Revised January 2005
SPRS245C
Electrical Specifications
5.9 External Interrupt Timings
Table 5−16 assumes testing over recommended operating conditions (see Figure 5−18).
†
Table 5−16. External Interrupt Timing Requirements
CV = 1.2 V
DD
CV = 1.6 V
DD
CV = 1.35 V
DD
NO.
UNIT
MIN
MAX
MIN
MAX
I1
I2
t
t
Pulse width, interrupt low, CPU active
Pulse width, interrupt high, CPU active
3P
3P
ns
ns
w(INTL)A
w(INTH)A
2P
2P
†
P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
I1
INTn
I2
Figure 5−18. External Interrupt Timings
5.10 Wake-Up From IDLE
Table 5−17 assumes testing over recommended operating conditions (see Figure 5−19).
†
Table 5−17. Wake-Up From IDLE Switching Characteristics
CV = 1.2 V
DD
CV = 1.6 V
DD
CV = 1.35 V
DD
NO.
PARAMETER
UNIT
MIN
TYP
MAX
MIN
TYP
MAX
Delay time, wake-up event low to clock
generation enable
‡
‡
ID1
t
1.25
1.25
ms
d(WKPEVTL-CLKGEN)
(CPU and clock domain idle)
Hold time, clock generation enable to
wake-up event low
(CPU and clock domain in idle)
§
§
ID2
ID3
t
t
3P
3P
ns
ns
h(CLKGEN-WKPEVTL)
w(WKPEVTL)
Pulse width, wake-up event low
(for CPU idle only)
3P
3P
†
‡
P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
Estimated data based on 12-MHz crystal used with on-chip oscillator at 25°C. This number will vary based on the actual crystal characteristics
operating condition and the PC board layout and the parasitics.
Following the clock generation domain idle, the INTx becomes level-sensitive and stays that way until the low-to-high transition of INTx following
the CPU wake-up. Holding the INTx low longer than minimum requirement will send more than one interrupt to the CPU. The number of interrupts
sent to the CPU depends on the INTx-low time following the CPU wake-up from IDLE.
§
ID1
X1
ID2
ID3
RESET,
INTx
Figure 5−19. Wake-Up From IDLE Timings
92
SPRS245C
April 2004 − Revised January 2005
Electrical Specifications
5.11 XF Timings
Table 5−18 assumes testing over recommended operating conditions (see Figure 5−20).
Table 5−18. XF Switching Characteristics
CV = 1.2 V
DD
CV = 1.6 V
DD
CV = 1.35 V
DD
NO.
PARAMETER
UNIT
MIN
−1
MAX
MIN
−1
MAX
Delay time, CLKOUT high to XF high
3
3
3
3
X1
t
ns
d(XF)
Delay time, CLKOUT high to XF low
−1
−1
†
CLKOUT
X1
XF
†
CLKOUT reflects the CPU clock.
Figure 5−20. XF Timings
93
April 2004 − Revised January 2005
SPRS245C
Electrical Specifications
5.12 General-Purpose Input/Output (GPIOx) Timings
Table 5−19 and Table 5−20 assume testing over recommended operating conditions (see Figure 5−21).
Table 5−19. GPIO Pins Configured as Inputs Timing Requirements
CV = 1.2 V
DD
CV = 1.6 V
DD
CV = 1.35 V
DD
NO.
UNIT
MIN
4
MAX
MIN
4
MAX
GPIO
Setup time, IOx input valid before CLKOUT
high
†
AGPIO
8
8
G1
t
t
ns
su(GPIO-COH)
h(COH-GPIO)
‡
‡
EHPIGPIO
GPIO
8
8
0
0
Hold time, IOx input valid after CLKOUT
high
†
G2
AGPIO
0
0
0
0
ns
EHPIGPIO
†
‡
AGPIO pins: A[15:0]
EHPIGPIO pins: C13, C10, C7, C5, C4, and C0
Table 5−20. GPIO Pins Configured as Outputs Switching Characteristics
CV = 1.2 V
DD
CV = 1.6 V
DD
CV = 1.35 V
DD
NO.
PARAMETER
UNIT
MIN
MAX
MIN
MAX
GPIO
0
6
0
6
11
13
Delay time, CLKOUT high to IOx output
change
†
G3
t
AGPIO
0
0
11
13
0
0
ns
d(COH-GPIO)
‡
EHPIGPIO
†
‡
AGPIO pins: A[15:0]
EHPIGPIO pins: C13, C10, C7, C5, C4, and C0
†
CLKOUT
G1
G2
IOx
Input Mode
G3
IOx
Output Mode
†
CLKOUT reflects the CPU clock.
Figure 5−21. General-Purpose Input/Output (IOx) Signal Timings
94
SPRS245C
April 2004 − Revised January 2005
Electrical Specifications
5.13 TIN/TOUT Timings (Timer0 Only)
Table 5−21 and Table 5−22 assume testing over recommended operating conditions (see Figure 5−22 and
Figure 5−23).
†‡
Table 5−21. TIN/TOUT Pins Configured as Inputs Timing Requirements
CV = 1.2 V
DD
CV = 1.6 V
DD
CV = 1.35 V
DD
NO.
UNIT
MIN
2P + 1
2P + 1
MAX
MIN
2P + 1
2P + 1
MAX
T4
T5
t
t
Pulse width, TIN/TOUT low
Pulse width, TIN/TOUT high
ns
ns
w(TIN/TOUTL)
w(TIN/TOUTH)
†
‡
P = 1/CPU clock frequency. For example, when running parts at 200 MHz, use P = 5 ns.
Only the Timer0 signal is externally available. The Timer1 signal is internally terminated and is not available for external use.
†‡§
Table 5−22. TIN/TOUT Pins Configured as Outputs Switching Characteristics
CV = 1.2 V
DD
CV = 1.6 V
DD
CV = 1.35 V
DD
NO.
PARAMETER
UNIT
MIN
−1
MAX
MIN
−1
MAX
T1
T2
T3
t
t
t
Delay time, CLKOUT high to TIN/TOUT high
Delay time, CLKOUT high to TIN/TOUT low
Pulse duration, TIN/TOUT (output)
3
3
3
3
ns
ns
ns
d(COH-TIN/TOUTH)
d(COH-TIN/TOUTL)
w(TIN/TOUT)
−1
−1
P − 1
P − 1
†
‡
§
P = 1/CPU clock frequency. For example, when running parts at 200 MHz, use P = 5 ns.
Only the Timer0 signal is externally available. The Timer1 signal is internally terminated and is not available for external use.
For proper operation of the TIN/TOUT pin configured as an output, the timer period must be configured for at least 4 cycles.
T5
T4
TIN/TOUT
as Input
Figure 5−22. TIN/TOUT Timings When Configured as Inputs
CLKOUT
T2
T3
T1
TIN/TOUT
as Output
Figure 5−23. TIN/TOUT Timings When Configured as Outputs
95
April 2004 − Revised January 2005
SPRS245C
Electrical Specifications
5.14 Multichannel Buffered Serial Port (McBSP) Timings
5.14.1 McBSP0 Timings
Table 5−23 and Table 5−24 assume testing over recommended operating conditions (see Figure 5−24 and
Figure 5−25).
†
Table 5−23. McBSP0 Timing Requirements
CV = 1.2 V
DD
CV = 1.6 V
DD
CV = 1.35 V
DD
NO.
UNIT
MIN
MAX
MIN
MAX
‡
‡
MC1
MC2
t
t
Cycle time, CLKR/X
CLKR/X ext
CLKR/X ext
2P
2P
ns
ns
c(CKRX)
w(CKRX)
‡
‡
Pulse duration, CLKR/X high or CLKR/X low
P–1
P–1
MC3
MC4
t
t
Rise time, CLKR/X
Fall time, CLKR/X
CLKR/X ext
6
6
6
6
ns
ns
r(CKRX)
f(CKRX)
CLKR/X ext
CLKR int
CLKR ext
CLKR int
CLKR ext
CLKR int
CLKR ext
CLKR int
CLKR ext
CLKX int
CLKX ext
CLKX int
CLKX ext
10
2
7
2
MC5
MC6
MC7
MC8
MC9
MC10
t
t
t
t
t
t
Setup time, external FSR high before CLKR low
Hold time, external FSR high after CLKR low
Setup time, DR valid before CLKR low
ns
ns
ns
ns
ns
ns
su(FRH-CKRL)
h(CKRL-FRH)
su(DRV-CKRL)
h(CKRL-DRV)
su(FXH-CKXL)
h(CKXL-FXH)
−3
1
−3
1
10
2
7
2
−2
3
−2
3
Hold time, DR valid after CLKR low
13
3
8
Setup time, external FSX high before CLKX low
Hold time, external FSX high after CLKX low
2
−3
1
−3
1
†
‡
Polarity bits CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that signal are
also inverted.
P = 1/CPU clock frequency. For example, when running parts at 200 MHz, use P = 5 ns.
96
SPRS245C
April 2004 − Revised January 2005
Electrical Specifications
†‡
Table 5−24. McBSP0 Switching Characteristics
CV = 1.2 V
DD
CV = 1.6 V
DD
CV = 1.35 V
DD
NO.
PARAMETER
UNIT
MIN
MAX
MIN
MAX
MC1
MC3
t
t
t
t
t
Cycle time, CLKR/X
CLKR/X int
CLKR/X int
CLKR/X int
CLKR/X int
CLKR/X int
CLKR int
2P
2P
ns
ns
ns
ns
ns
c(CKRX)
r(CKRX)
Rise time, CLKR/X
1
1
MC4
Fall time, CLKR/X
1
1
f(CKRX)
§
§
§
§
MC11
MC12
Pulse duration, CLKR/X high
Pulse duration, CLKR/X low
D−2
D+2
D−1
D+1
w(CKRXH)
w(CKRXL)
§
§
§
§
C−2
C+2
C−1
C+1
−2
4
1
13
2
−2
4
1
8
MC13
MC14
MC15
t
t
t
Delay time, CLKR high to internal FSR valid
Delay time, CLKX high to internal FSX valid
ns
ns
ns
d(CKRH-FRV)
d(CKXH-FXV)
dis(CKXH-DXHZ)
CLKR ext
CLKX int
−2
4
−2
4
2
CLKX ext
CLKX int
15
5
9
0
−5
3
1
Disable time, DX high-impedance from CLKX high
following last data bit
CLKX ext
CLKX int
10
18
5
11
4
Delay time, CLKX high to DX valid.
This applies to all bits except the first bit transmitted.
CLKX ext
15
9
Delay time, CLKX high to DX
valid
CLKX int
CLKX ext
CLKX int
CLKX ext
4
13
2
7
¶
DXENA = 0
DXENA = 1
MC16
t
ns
d(CKXH-DXV)
2P + 1
2P + 4
2P + 1
2P + 3
Only applies to first bit transmitted
when in Data Delay
1 or 2
(XDATDLY = 01b or 10b) modes
Enable time, DX driven from CLKX
high
CLKX int
CLKX ext
CLKX int
CLKX ext
−1
6
−3
3
¶
DXENA = 0
DXENA = 1
MC17
MC18
t
t
t
ns
ns
ns
en(CKXH-DX)
d(FXH-DXV)
en(FXH-DX)
P − 1
P + 6
P − 3
P + 3
Only applies to first bit transmitted
when in Data Delay
1
or
2
(XDATDLY= 01b or 10b) modes
¶
Delay time, FSX high to DX valid
FSX int
FSX ext
FSX int
FSX ext
2
13
2
8
DXENA = 0
DXENA = 1
Only applies to first bit transmitted
when in Data Delay 0 (XDATDLY=
00b) mode.
2P + 1
2P + 10
2P + 1
2P + 10
Enable time, DX driven from FSX
FSX int
FSX ext
FSX int
FSX ext
0
8
0
3
¶
high
DXENA = 0
DXENA = 1
MC19
P − 3
P + 8
P − 3
P + 4
Only applies to first bit transmitted
when in Data Delay 0 (XDATDLY=
00b) mode
†
Polarity bits CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that signal are
also inverted.
P = 1/CPU clock frequency. For example, when running parts at 200 MHz, use P = 5 ns.
T=CLKRX period = (1 + CLKGDV) * P
‡
§
C=CLKRX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * P when CLKGDV is even
D=CLKRX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) * P when CLKGDV is even
See the TMS320C55x DSP Peripherals Overview Reference Guide (literature number SPRU317) for a description of the DX enable (DXENA)
and data delay features of the McBSP.
¶
97
April 2004 − Revised January 2005
SPRS245C
Electrical Specifications
5.14.2 McBSP1 and McBSP2 Timings
Table 5−25 and Table 5−26 assume testing over recommended operating conditions (see Figure 5−24 and
Figure 5−25).
†
Table 5−25. McBSP1 and McBSP2 Timing Requirements
CV = 1.2 V
DD
CV = 1.6 V
DD
CV = 1.35 V
DD
NO.
UNIT
MIN
MAX
MIN
MAX
‡
‡
MC1
MC2
t
t
Cycle time, CLKR/X
CLKR/X ext
CLKR/X ext
2P
2P
ns
ns
c(CKRX)
w(CKRX)
‡
‡
Pulse duration, CLKR/X high or CLKR/X low
P–1
P–1
MC3
MC4
t
t
Rise time, CLKR/X
Fall time, CLKR/X
CLKR/X ext
6
6
6
6
ns
ns
r(CKRX)
f(CKRX)
CLKR/X ext
CLKR int
CLKR ext
CLKR int
CLKR ext
CLKR int
CLKR ext
CLKR int
CLKR ext
CLKX int
CLKX ext
CLKX int
CLKX ext
11
3
7
3
MC5
MC6
MC7
MC8
MC9
MC10
t
t
t
t
t
t
Setup time, external FSR high before CLKR low
Hold time, external FSR high after CLKR low
Setup time, DR valid before CLKR low
ns
ns
ns
ns
ns
ns
su(FRH-CKRL)
h(CKRL-FRH)
su(DRV-CKRL)
h(CKRL-DRV)
su(FXH-CKXL)
h(CKXL-FXH)
−3
1
−3
1
11
3
7
3
−2
3
−2
3
Hold time, DR valid after CLKR low
14
4
9
Setup time, external FSX high before CLKX low
Hold time, external FSX high after CLKX low
3
−3
1
−3
1
†
‡
Polarity bits CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that signal are
also inverted.
P = 1/CPU clock frequency. For example, when running parts at 200 MHz, use P = 5 ns.
98
SPRS245C
April 2004 − Revised January 2005
Electrical Specifications
†‡
Table 5−26. McBSP1 and McBSP2 Switching Characteristics
CV = 1.2 V
DD
CV = 1.6 V
DD
CV = 1.35 V
DD
NO.
PARAMETER
UNIT
MIN
MAX
MIN
MAX
MC1
MC3
t
t
t
t
t
Cycle time, CLKR/X
CLKR/X int
CLKR/X int
CLKR/X int
CLKR/X int
CLKR/X int
CLKR int
2P
2P
ns
ns
ns
ns
ns
c(CKRX)
r(CKRX)
Rise time, CLKR/X
2
2
MC4
Fall time, CLKR/X
2
2
f(CKRX)
§
§
§
§
MC11
MC12
Pulse duration, CLKR/X high
Pulse duration, CLKR/X low
D − 2
D + 2
D − 2
D + 2
w(CKRXH)
w(CKRXL)
§
§
§
§
C − 2
C + 2
C − 2
C + 2
−3
3
2
14
2
−3
3
2
9
MC13
MC14
MC15
t
t
t
Delay time, CLKR high to internal FSR valid
Delay time, CLKX high to internal FSX valid
ns
ns
ns
d(CKRH-FRV)
d(CKXH-FXV)
dis(CKXH-DXHZ)
CLKR ext
CLKX int
−3
4
−3
4
2
CLKX ext
CLKX int
15
3
9
−3
10
−5
3
1
Disable time, DX high-impedance from CLKX high
following last data bit
CLKX ext
CLKX int
19
5
12
3
Delay time, CLKX high to DX valid.
This applies to all bits except the first bit transmitted.
CLKX ext
15
9
¶
Delay time, CLKX high to DX valid
CLKX int
CLKX ext
CLKX int
CLKX ext
4
15
2
9
DXENA = 0
MC16
t
ns
d(CKXH-DXV)
Only applies to first bit transmitted
2P + 1
2P + 5
2P + 1
2P + 3
when in Data Delay
(XDATDLY=01b or 10b) modes
1 or 2
DXENA = 1
DXENA = 0
DXENA = 1
Enable time, DX driven from CLKX
CLKX int
CLKX ext
CLKX int
CLKX ext
−2
9
−4
4
¶
high
MC17
MC18
t
t
t
ns
ns
ns
en(CKXH-DX)
d(FXH-DXV)
en(FXH-DX)
P − 2
P + 9
P − 4
P + 4
Only applies to first bit transmitted
when in Data Delay
(XDATDLY=01b or 10b) modes
1 or 2
¶
Delay time, FSX high to DX valid
FSX int
FSX ext
FSX int
FSX ext
3
13
2
8
DXENA = 0
DXENA = 1
Only applies to first bit transmitted
when in Data Delay
(XDATDLY=00b) mode.
2P + 1
2P + 12
2P + 1
2P + 7
0
Enable time, DX driven from FSX
FSX int
FSX ext
FSX int
FSX ext
1
8
0
4
¶
high
DXENA = 0
DXENA = 1
MC19
P − 1
P + 8
P − 3
P + 5
Only applies to first bit transmitted
when
in
Data
Delay
0
(XDATDLY=00b) mode
†
Polarity bits CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that signal are
also inverted.
P = 1/CPU clock frequency. For example, when running parts at 200 MHz, use P = 5 ns.
T = CLKRX period = (1 + CLKGDV) * P
‡
§
C = CLKRX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * P when CLKGDV is even
D = CLKRX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) * P when CLKGDV is even
See the TMS320C55x DSP Peripherals Overview Reference Guide (literature number SPRU317) for a description of the DX enable (DXENA)
and data delay features of the McBSP.
¶
99
April 2004 − Revised January 2005
SPRS245C
Electrical Specifications
MC1
MC2, MC11
MC3
MC2, MC12
CLKR
FSR (Int)
FSR (Ext)
MC13
MC4
MC13
MC5
MC7
MC6
MC8
DR
Bit (n−1)
MC7
(n−2)
(n−3)
(n−2)
(n−4)
(n−3)
(n−2)
(RDATDLY=00b)
MC8
DR
Bit (n−1)
(RDATDLY=01b)
MC7
MC8
DR
Bit (n−1)
(RDATDLY=10b)
Figure 5−24. McBSP Receive Timings
MC1
MC2, MC11
MC2, MC12
MC3
MC4
CLKX
MC14
MC14
FSX (Int)
MC9
MC10
FSX (Ext)
MC18
MC16
(n−3)
MC16
MC19
DX
Bit 0
Bit (n−1)
MC17
(n−2)
(n−4)
(XDATDLY=00b)
DX
Bit 0
Bit (n−1)
MC17
(n−2)
(n−3)
(n−2)
(XDATDLY=01b)
MC16
MC15
Bit 0
DX
Bit (n−1)
(XDATDLY=10b)
Figure 5−25. McBSP Transmit Timings
100
SPRS245C
April 2004 − Revised January 2005
Electrical Specifications
5.14.3 McBSP as SPI Master or Slave Timings
Table 5−27 to Table 5−34 assume testing over recommended operating conditions (see Figure 5−26 through
Figure 5−29).
‡
†
Table 5−27. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0)
CV = 1.2 V
DD
CV = 1.6 V
DD
CV = 1.35 V
DD
NO.
UNIT
MASTER
SLAVE
MIN MAX
MASTER
SLAVE
MIN
MAX
MIN
MAX
MIN
MAX
Setup time, DR valid before
CLKX low
MC23
MC24
t
t
15
3 − 6P
3 + 6P
10
3 − 6P
ns
ns
su(DRV-CKXL)
h(CKXL-DRV)
Hold time, DR valid after
CLKX low
0
0
3 + 6P
Setup time, FSX low before
CLKX high
MC25
MC26
t
t
5
5
ns
ns
su(FXL-CKXH)
c(CKX)
Cycle time, CLKX
2P
16P
2P
16P
†
‡
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
P = 1/CPU clock frequency. For example, when running parts at 200 MHz, use P = 5 ns.
‡
†
Table 5−28. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 0)
CV = 1.2 V
DD
CV = 1.6 V
DD
CV = 1.35 V
DD
NO.
PARAMETER
UNIT
§
§
MASTER
SLAVE
MIN
MASTER
SLAVE
MIN
MAX
MAX
MIN
MAX
MIN
MAX
Delay time, CLKX low
to FSX low
MC27
MC28
MC29
t
t
t
T − 5
T + 5
T − 4
T + 4
ns
ns
ns
d(CKXL-FXL)
d(FXL-CKXH)
d(CKXH-DXV)
¶
Delay time, FSX low to
C − 5
−4
C + 5
6
C − 4
−3
C + 4
3
#
CLKX high
Delay time, CLKX high
to DX valid
3P + 3 5P + 15
3P + 3
5P + 8
Disable time, DX high-
impedance following
last data bit from CLKX
low
MC30
t
C − 4
C + 4
C − 3
C + 1
ns
dis(CKXL-DXHZ)
Disable time, DX high-
impedance following
last data bit from FSX
high
MC31
MC32
t
t
3P+ 4 3P + 19
3P + 4 3P + 18
3P+ 3 3P + 11
3P + 4 3P + 10
ns
ns
dis(FXH-DXHZ)
d(FXL-DXV)
Delay time, FSX low to
DX valid
†
‡
§
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
P = 1/CPU clock frequency. For example, when running parts at 200 MHz, use P = 5 ns.
T
=
CLKX period = (1 + CLKGDV) * 2P
C = CLKX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * 2P when CLKGDV is even
FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX
and FSR is inverted before being used internally.
¶
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock
(CLKX).
#
101
April 2004 − Revised January 2005
SPRS245C
Electrical Specifications
MC25
MC28
MC26
LSB
MSB
CLKX
MC29
MC27
FSX
MC31
MC30
MC32
DX
DR
Bit 0
Bit (n−1)
Bit (n−1)
(n−2)
MC24
(n−2)
(n−3)
(n−3)
(n−4)
(n−4)
MC23
Bit 0
Figure 5−26. McBSP Timings as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0
102
SPRS245C
April 2004 − Revised January 2005
Electrical Specifications
‡
†
Table 5−29. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 0)
CV = 1.2 V
DD
CV = 1.6 V
DD
CV = 1.35 V
DD
NO.
UNIT
MASTER
SLAVE
MIN MAX
MASTER
SLAVE
MIN
MAX
MIN
MAX
MIN
MAX
Setup time, DR valid before
CLKX high
MC33
MC34
t
t
15
3 − 6P
3 + 6P
10
3 − 6P
ns
ns
su(DRV-CKXH)
h(CKXH-DRV)
Hold time, DR valid after CLKX
high
0
0
3 + 6P
Setup time, FSX low before
CLKX high
MC25
MC26
t
t
5
5
ns
ns
su(FXL-CKXH)
c(CKX)
Cycle time, CLKX
2P
16P
2P
16P
†
‡
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
P = 1/CPU clock frequency. For example, when running parts at 200 MHz, use P = 5 ns.
‡
†
Table 5−30. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 0)
CV = 1.2 V
DD
CV = 1.6 V
DD
CV = 1.35 V
DD
NO.
PARAMETER
UNIT
§
§
MASTER
SLAVE
MIN
MASTER
SLAVE
MIN
MAX
MAX
MIN
MAX
MIN
MAX
Delay time, CLKX low to
FSX low
MC27
MC28
MC35
t
t
t
C − 5
C + 5
C − 4
C + 4
ns
ns
ns
d(CKXL-FXL)
d(FXL-CKXH)
d(CKXL-DXV)
¶
Delay time, FSX low to
T − 5
−4
T + 5
6
T − 4
−3
T + 4
3
#
CLKX high
Delay time, CLKX low to
DX valid
3P + 3 5P + 15
3P + 4 3P + 19
3P + 4 3P + 18
3P + 3
5P + 8
Disable time, DX high-
impedance
following
MC30
MC32
t
t
−4
4
−3
1
3P + 3 3P + 12
3P + 4 3P + 10
ns
ns
dis(CKXL-DXHZ)
d(FXL-DXV)
last data bit from CLKX
low
Delay time, FSX low to
DX valid
D − 4
D + 4
D − 3
D + 3
†
‡
§
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
P = 1/CPU clock frequency. For example, when running parts at 200 MHz, use P = 5 ns.
T
=
CLKX period = (1 + CLKGDV) * P
C = CLKX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * P when CLKGDV is even
D = CLKX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) * P when CLKGDV is even
¶
#
FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX
and FSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock
(CLKX).
103
April 2004 − Revised January 2005
SPRS245C
Electrical Specifications
MC25
MC28
MC26
LSB
MSB
CLKX
MC35
MC27
FSX
MC32
MC30
DX
DR
Bit 0
Bit 0
Bit (n−1)
(n−2)
(n−3)
(n−4)
(n−4)
MC33
MC34
(n−2)
Bit (n−1)
(n−3)
Figure 5−27. McBSP Timings as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0
104
SPRS245C
April 2004 − Revised January 2005
Electrical Specifications
‡
†
Table 5−31. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 1)
CV = 1.2 V
DD
CV = 1.6 V
DD
CV = 1.35 V
DD
NO.
UNIT
MASTER
SLAVE
MIN MAX
MASTER
SLAVE
MIN
MAX
MIN
MAX
MIN
MAX
Setup time, DR valid before CLKX
high
MC33
MC34
t
t
15
3 − 6P
3 + 6P
10
3 − 6P
ns
ns
su(DRV-CKXH)
h(CKXH-DRV)
Hold time, DR valid after CLKX
high
0
0
3 + 6P
Setup time, FSX low before CLKX
low
MC36
MC26
t
t
5
5
ns
ns
su(FXL-CKXL)
c(CKX)
Cycle time, CLKX
2P
16P
2P
16P
†
‡
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
P = 1/CPU clock frequency. For example, when running parts at 200 MHz, use P = 5 ns.
‡
†
Table 5−32. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 1)
CV = 1.2 V
DD
CV = 1.6 V
DD
CV = 1.35 V
DD
NO.
PARAMETER
UNIT
§
§
MASTER
SLAVE
MIN
MASTER
SLAVE
MIN
MAX
MAX
MIN
MAX
MIN
MAX
Delay time, CLKX high
to FSX low
MC37
MC38
MC35
t
t
t
T − 5
T + 5
T − 4
T + 4
ns
ns
ns
d(CKXH-FXL)
d(FXL-CKXL)
d(CKXL-DXV)
¶
Delay time, FSX low to
D − 5
−4
D + 5
6
D − 4
−3
D + 4
3
#
CLKX low
Delay time, CLKX low to
DX valid
3P + 3 5P + 15
3P + 3
5P + 8
Disable time, DX high-
impedance
last data bit from CLKX
high
following
MC39
t
D − 4
D + 4
D − 3
D + 1
ns
dis(CKXH-DXHZ)
Disable time, DX high-
impedance
last data bit from FSX
high
following
MC31
MC32
t
t
3P + 4 3P +19
3P + 4 3P + 18
3P + 3 3P +11
3P + 4 3P + 10
ns
ns
dis(FXH-DXHZ)
d(FXL-DXV)
Delay time, FSX low to
DX valid
†
‡
§
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
P = 1/CPU clock frequency. For example, when running parts at 200 MHz, use P = 5 ns.
T
=
CLKX period = (1 + CLKGDV) * P
C = CLKX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * P when CLKGDV is even
D = CLKX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) * P when CLKGDV is even
¶
#
FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX
and FSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock
(CLKX).
105
April 2004 − Revised January 2005
SPRS245C
Electrical Specifications
MC36
MC38
LSB
MSB
MC26
CLKX
MC35
(n−2)
MC37
FSX
MC31
MC39
MC32
DX
DR
Bit 0
Bit (n−1)
(n−3)
(n−4)
(n−4)
MC33
MC34
(n−2)
Bit 0
Bit (n−1)
(n−3)
Figure 5−28. McBSP Timings as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1
106
SPRS245C
April 2004 − Revised January 2005
Electrical Specifications
‡
†
Table 5−33. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 1)
CV = 1.2 V
DD
CV = 1.6 V
DD
CV = 1.35 V
DD
NO.
UNIT
MASTER
SLAVE
MIN MAX
MASTER
SLAVE
MIN
MAX
MIN
MAX
MIN
MAX
Setup time, DR valid before CLKX
low
MC23
MC24
t
t
15
3 − 6P
3 + 6P
10
3 − 6P
ns
ns
su(DRV-CKXL)
h(CKXL-DRV)
Hold time, DR valid after CLKX
low
0
0
3 + 6P
Setup time, FSX low before CLKX
low
MC36
MC26
t
t
5
5
ns
ns
su(FXL-CKXL)
c(CKX)
Cycle time, CLKX
2P
16P
2P
16P
†
‡
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
P = 1/CPU clock frequency. For example, when running parts at 200 MHz, use P = 5 ns.
‡
†
Table 5−34. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 1)
CV = 1.2 V
DD
CV = 1.6 V
DD
CV = 1.35 V
DD
NO.
PARAMETER
UNIT
§
§
MASTER
SLAVE
MIN
MASTER
SLAVE
MIN
MAX
MAX
MIN
MAX
MIN
MAX
Delay time, CLKX high
to FSX low
MC37
MC38
MC29
t
t
t
D − 5
D + 5
D − 4
D + 4
ns
ns
ns
d(CKXH-FXL)
d(FXL-CKXL)
d(CKXH-DXV)
¶
Delay time, FSX low to
T − 5
−4
T + 5
6
T − 4
−3
T + 4
3
#
CLKX low
Delay time, CLKX high
to DX valid
3P + 3 5P + 15
3P + 4 3P + 19
3P + 4 3P + 18
3P + 3
5P + 8
Disable time, DX high-
impedance
following
MC39
MC32
t
t
−4
4
−3
1
3P + 3 3P + 12
3P + 4 3P + 10
ns
ns
dis(CKXH-DXHZ)
d(FXL-DXV)
last data bit from CLKX
high
Delay time, FSX low to
DX valid
C − 4
C + 4
C − 3
C + 3
†
‡
§
For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
P = 1/CPU clock frequency. For example, when running parts at 200 MHz, use P = 5 ns.
T
=
CLKX period = (1 + CLKGDV) * P
C = CLKX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * P when CLKGDV is even
D = CLKX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) * P when CLKGDV is even
¶
#
FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX
and FSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock
(CLKX).
107
April 2004 − Revised January 2005
SPRS245C
Electrical Specifications
MC36
MC38
LSB
MSB
MC26
CLKX
MC29
MC37
FSX
MC32
MC39
DX
DR
Bit 0
Bit 0
Bit (n−1)
Bit (n−1)
(n−2)
(n−3)
(n−4)
MC23
MC24
(n−2)
(n−3)
(n−4)
Figure 5−29. McBSP Timings as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1
108
SPRS245C
April 2004 − Revised January 2005
Electrical Specifications
5.14.4 McBSP General-Purpose I/O Timings
Table 5−35 and Table 5−36 assume testing over recommended operating conditions (see Figure 5−30).
Table 5−35. McBSP General-Purpose I/O Timing Requirements
CV = 1.2 V
DD
CV = 1.6 V
DD
CV = 1.35 V
DD
NO.
UNIT
MIN
7
MAX
MIN
7
MAX
†
MC20
MC21
t
t
Setup time, MGPIOx input mode before CLKOUT high
ns
ns
su(MGPIO-COH)
h(COH-MGPIO)
†
Hold time, MGPIOx input mode after CLKOUT high
0
0
†
MGPIOx refers to CLKRx, FSRx, DRx, CLKXx, or FSXx when configured as a general-purpose input.
Table 5−36. McBSP General-Purpose I/O Switching Characteristics
CV = 1.2 V
DD
CV = 1.6 V
DD
CV = 1.35 V
DD
NO.
UNIT
PARAMETER
MIN
MAX
MIN
MAX
‡
MC22
t
Delay time, CLKOUT high to MGPIOx output mode
0
7
0
7
ns
d(COH-MGPIO)
‡
MGPIOx refers to CLKRx, FSRx, CLKXx, FSXx, or DXx when configured as a general-purpose output.
MC20
†
CLKOUT
MC22
MC21
‡
MGPIO
Input Mode
§
MGPIO
Output Mode
†
‡
§
CLKOUT reflects the CPU clock.
MGPIOx refers to CLKRx, FSRx, DRx, CLKXx, or FSXx when configured as a general-purpose input.
MGPIOx refers to CLKRx, FSRx, CLKXx, FSXx, or DXx when configured as a general-purpose output.
Figure 5−30. McBSP General-Purpose I/O Timings
109
April 2004 − Revised January 2005
SPRS245C
Electrical Specifications
5.15 Enhanced Host-Port Interface (EHPI) Timings
Table 5−37 and Table 5−38 assume testing over recommended operating conditions (see Figure 5−31
through Figure 5−36).
Table 5−37. EHPI Timing Requirements
CV = 1.2 V
DD
CV = 1.6 V
DD
CV = 1.35 V
DD
NO.
UNIT
MIN
4
MAX
MIN
4
MAX
E11
E12
t
t
Setup time, HAS low before HDS low
Hold time, HAS low after HDS low
ns
ns
su(HASL-HDSL)
h(HDSL-HASL)
3
3
Setup time, (HR/W, HA[13:0], HBE[1:0], HCNTL[1:0]) valid
before HDS low
E13
E14
t
t
2
4
2
4
ns
ns
su(HCNTLV-HDSL)
h(HDSL-HCNTLIV)
Hold time, (HR/W, HA[13:0], HBE[1:0], HCNTL[1:0]) invalid
after HDS low
†
†
E15
E16
E17
E18
t
t
t
t
Pulse duration, HDS low
4P
4P
ns
ns
ns
ns
w(HDSL)
†
†
Pulse duration, HDS high
4P
4P
w(HDSH)
Setup time, HD bus write data valid before HDS high
Hold time, HD bus write data invalid after HDS high
3
4
3
4
su(HDV-HDSH)
h(HDSH-HDIV)
Setup time, (HR/W, HBE[1:0], HCNTL[1:0]) valid before
HAS low
E19
E20
t
t
3
4
3
4
ns
ns
su(HCNTLV-HASL)
Hold time, (HR/W, HBE[1:0], HCNTL[1:0]) valid after HAS low
h(HASL-HCNTLIV)
†
P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
Table 5−38. EHPI Switching Characteristics
CV = 1.2 V
DD
CV = 1.6 V
DD
CV = 1.35 V
DD
NO.
PARAMETER
UNIT
MIN
MAX
MIN
MAX
Enable time, HDS low to HD bus enabled
(memory access)
E1
E2
E4
E5
t
t
t
t
6
26
6
19
ns
ns
ns
ns
en(HDSL-HDD)M
d(HDSL-HDV)M
en(HDSL-HDD)R
d(HDSL-HDV)R
Delay time, HDS low to HD bus read data valid
(memory access)
†‡
†‡
14P
14P
Enable time, HDS low to HD enabled
(register access)
6
26
26
6
19
19
Delay time, HDS low to HD bus read data valid
(register access)
E6
E7
t
t
Disable time, HDS high to HD bus read data invalid
Delay time, HDS low to HRDY low (during reads)
6
2
26
18
6
2
19
15
ns
ns
dis(HDSH-HDIV)
d(HDSL-HRDYL)
Delay time, HD bus valid to HRDY high
(during reads)
E8
ns
t
d(HDV-HRDYH)
E9
t
t
t
Delay time, HDS high to HRDY low (during writes)
Delay time, HDS high to HRDY high (during writes)
Delay time, CLKOUT high to HINT high/low
18
11
15
8
ns
ns
ns
d(HDSH-HRDYL)
d(HDSH-HRDYH)
†‡
†‡
14P
14P
E10
E21
0
0
d(COH-HINT)
†
‡
P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
EHPI latency is dependent on the number of DMA channels active, their priorities and their source/destination ports. The latency shown assumes
no competing CPU or DMA activity to the memory resource being accessed by the EHPI.
110
SPRS245C
April 2004 − Revised January 2005
Electrical Specifications
†
CLKOUT
E21
HINT
†
CLKOUT reflects the CPU clock.
Figure 5−31. HINT Timings
Read
E15
Write
HCS
HDS
E16
E13
E15
E14
E14
E13
HR/W
HBE[1:0]
HCNTL0
HA[13:0]
Valid
Valid
Valid
Valid
Valid
Valid
E2
E1
E6
HD[15:0]
(read)
Read Data
E17
E18
HD[15:0]
(write)
Write Data
E10
E7
E8
E9
HRDY
NOTES: A. Any non-multiplexed access with HCNTL0 low will result in HPIC register access. For data read or write, HCNTL0 must stay high
during the EHPI access.
B. The falling edge of HCS must occur concurrent with or before the falling edge of HDS. The rising edge of HCS must occur
concurrent with or after the rising edge of HDS. If HDS1 and/or HDS2 are tied permanently active and HCS is used as a strobe,
the timing requirements shown for HDS apply to HCS. HRDY is always driven to the same value as its internal state.
Figure 5−32. EHPI Nonmultiplexed Read/Write Timings
111
April 2004 − Revised January 2005
SPRS245C
Electrical Specifications
Read
Write
E12
HCS
E11
E12
E11
HAS
E15
E16
E19
E15
E14
HDS
E19
E20
E20
E13
E14
E13
HR/W
Valid
Valid
HBE[1:0]
Valid (11)
Valid (11)
HCNTL[1:0]
E2
E6
E1
HD[15:0]
(read)
Read Data
E17
E18
HD[15:0]
(write)
Write Data
E9
E10
E7
E8
HRDY
NOTE: The falling edge of HCS must occur concurrent with or before the falling edge of HDS. The rising edge of HCS must occur concurrent
with or after the rising edge of HDS. If HDS1 and/or HDS2 are tied permanently active and HCS is used as a strobe, the timing
requirements shown for HDS apply to HCS. HRDY is always driven to the same value as its internal state.
Figure 5−33. EHPI Multiplexed Memory (HPID) Read/Write Timings Without Autoincrement
112
SPRS245C
April 2004 − Revised January 2005
Electrical Specifications
HCS
HAS
E11
E12
E15
E16
HDS
E19
E20
E13
E14
HR/W
HBE[1:0]
Valid
Valid
HCNTL[1:0]
Valid (01)
E1
Valid (01)
E1
E2
E2
E6
E6
HD[15:0]
(read)
Read Data
Read Data
E7
E8
E7
E8
HRDY
HPIA contents
n
n + 1
n + 2
NOTES: A. During autoincrement mode, although the EHPI internally increments the memory address, reads of the HPIA register by the host
will always indicate the base address.
B. In autoincrement mode, if HBE[1:0] are used to access the data as 8-bit-wide units, the HPIA increments only following each high
byte (HBE1 low) access.
C. The falling edge of HCS must occur concurrent with or before the falling edge of HDS. The rising edge of HCS must occur
concurrent with or after the rising edge of HDS. If HDS1 and/or HDS2 are tied permanently active and HCS is used as a strobe,
the timing requirements shown for HDS apply to HCS. HRDY is always driven to the same value as its internal state.
Figure 5−34. EHPI Multiplexed Memory (HPID) Read Timings With Autoincrement
113
April 2004 − Revised January 2005
SPRS245C
Electrical Specifications
HCS
E11
E12
E15
HAS
E16
HDS
E19
E20
E13
E14
HR/W
HBE[1:0]
Valid
Valid
HCNTL[1:0]
Valid (01)
Valid (01)
E17
E18
E10
HD[15:0]
(write)
Write Data
Write Data
E10
E9
E9
HRDY
n
HPIA contents
n + 1
NOTES: A. During autoincrement mode, although the EHPI internally increments the memory address, reads of the HPIA register by the host
will always indicate the base address.
B. The falling edge of HCS must occur concurrent with or before the falling edge of HDS. The rising edge of HCS must occur
concurrent with or after the rising edge of HDS. If HDS1 and/or HDS2 are tied permanently active and HCS is used as a strobe,
the timing requirements shown for HDS apply to HCS. HRDY is always driven to the same value as its internal state.
Figure 5−35. EHPI Multiplexed Memory (HPID) Write Timings With Autoincrement
114
SPRS245C
April 2004 − Revised January 2005
Electrical Specifications
Read
E12
Write
E12
HCS
HAS
E11
E11
E15
E16
E15
HDS
E20
E19
E19
E20
E14
E13
E14
E13
HR/W
Valid
Valid
HBE[1:0]
Valid (10 or 00)
E4
Valid (10 or 00)
HCNTL[1:0]
E5
E6
HD[15:0]
(read)
Read Data
E17
E18
HD[15:0]
(write)
Write Data
HRDY
NOTES: A. During autoincrement mode, although the EHPI internally increments the memory address, reads of the HPIA register by the host
will always indicate the base address.
B. The falling edge of HCS must occur concurrent with or before the falling edge of HDS. The rising edge of HCS must occur
concurrent with or after the rising edge of HDS. If HDS1 and/or HDS2 are tied permanently active and HCS is used as a strobe,
the timing requirements shown for HDS apply to HCS. HRDY is always driven to the same value as its internal state.
Figure 5−36. EHPI Multiplexed Register Read/Write Timings
115
April 2004 − Revised January 2005
SPRS245C
Electrical Specifications
5.16 I2C Timings
Table 5−39 and Table 5−40 assume testing over recommended operating conditions (see Figure 5−37 and
Figure 5−38).
2
Table 5−39. I C Signals (SDA and SCL) Timing Requirements
CV = 1.2 V
DD
CV = 1.6 V
DD
CV = 1.35 V
DD
STANDARD
MODE
FAST
MODE
STANDARD
MODE
FAST
MODE
NO.
UNIT
MIN MAX
MIN
MAX
MIN MAX
MIN
MAX
IC1
IC2
t
Cycle time, SCL
10
2.5
10
2.5
µs
µs
c(SCL)
Setup time, SCL high
before SDA low for a
repeated START condition
t
4.7
0.6
4.7
0.6
su(SCLH-SDAL)
Hold time, SCL low after
SDA low for a START and
a repeated START
condition
IC3
t
4
0.6
4
0.6
µs
h(SCLL-SDAL)
IC4
IC5
t
Pulse duration, SCL low
Pulse duration, SCL high
4.7
4
1.3
0.6
4.7
4
1.3
0.6
µs
µs
w(SCLL)
t
w(SCLH)
Setup time, SDA valid
before SCL high
†
†
IC6
IC7
t
t
250
100
250
100
ns
su(SDA-SCLH)
h(SDA-SCLL)
Hold time, SDA valid after
SCL low
‡
‡
§
‡
‡
§
0
0
0.9
0
0
0.9
µs
Pulse duration, SDA high
IC8
t
between
STOP
and
4.7
1.3
4.7
1.3
µs
w(SDAH)
START conditions
Rise time, SDA
Rise time, SCL
Fall time, SDA
Fall time, SCL
¶
¶
¶
¶
¶
¶
¶
¶
IC9
t
t
t
t
1000 20 + 0.1C
1000 20 + 0.1C
300 20 + 0.1C
300 20 + 0.1C
300
300
300
300
1000 20 + 0.1C
1000 20 + 0.1C
300 20 + 0.1C
300 20 + 0.1C
300
300
300
300
ns
ns
ns
ns
r(SDA)
r(SCL)
f(SDA)
f(SCL)
b
b
b
b
b
b
b
b
IC10
IC11
IC12
Setup time, SCL high be-
fore SDA high (for STOP
condition)
IC13
t
t
4.0
0.6
0
4.0
0.6
µs
su(SCLH-SDAH)
Pulse duration, spike
(must be suppressed)
IC14
IC15
50
0
50
ns
w(SP)
¶
Capacitive load for each
bus line
C
400
400
400
400
pF
b
†
‡
2
2
A Fast-mode I C-bus device can be used in a Standard-mode I C-bus system, but the requirement t
≥ 250 ns must then be met.
su(SDA-SCLH)
This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period
of the SCL signal, it must output the next data bit to the SDA line t max + t
I C-Bus Specification) before the SCL line is released.
A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the V
region of the falling edge of SCL.
= 1000 + 250 = 1250 ns (according to the Standard-mode
r
su(SDA-SCLH)
2
of the SCL signal) to bridge the undefined
IHmin
§
¶
The maximum t
has only to be met if the device does not stretch the LOW period [t
] of the SCL signal.
w(SCLL)
h(SDA-SCLL)
C = total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed.
b
2
I C Bus is a trademark of Koninklijke Philips Electronics N.V.
116
SPRS245C
April 2004 − Revised January 2005
Electrical Specifications
IC11
IC9
SDA
SCL
IC6
IC8
IC14
IC13
IC4
IC5
IC10
IC1
IC3
IC12
IC3
IC2
IC7
Stop
Start
Repeated
Start
Stop
2
Figure 5−37. I C Receive Timings
117
April 2004 − Revised January 2005
SPRS245C
Electrical Specifications
2
Table 5−40. I C Signals (SDA and SCL) Switching Characteristics
CV = 1.2 V
DD
CV = 1.6 V
DD
CV = 1.35 V
DD
STANDARD
MODE
FAST
MODE
STANDARD
MODE
FAST
MODE
NO.
PARAMETER
UNIT
MIN MAX
MIN
MAX
MIN MAX
MIN
MAX
IC16
IC17
t
t
Cycle time, SCL
10
2.5
10
2.5
µs
µs
c(SCL)
Delay time, SCL high to
SDA low for a repeated
START condition
4.7
0.6
4.7
0.6
d(SCLH-SDAL)
Delay time, SDA low to
SCL low for a START and
a repeated START
condition
IC18
t
4
0.6
4
0.6
µs
d(SDAL-SCLL)
IC19
IC20
t
t
Pulse duration, SCL low
Pulse duration, SCL high
4.7
4
1.3
0.6
4.7
4
1.3
0.6
µs
µs
w(SCLL)
w(SCLH)
Delay time, SDA valid to
SCL high
IC21
IC22
t
t
250
0
100
0
250
0
100
0
ns
d(SDA-SCLH)
v(SCLL-SDAV)
Valid time, SDA valid
after SCL low
0.9
0.9
µs
Pulse duration, SDA high
between STOP and
START conditions
IC23
t
4.7
1.3
4.7
1.3
µs
w(SDAH)
†
†
†
†
†
†
†
†
IC24
IC25
IC26
IC27
t
t
t
t
Rise time, SDA
Rise time, SCL
Fall time, SDA
Fall time, SCL
1000 20 + 0.1C
1000 20 + 0.1C
300 20 + 0.1C
300 20 + 0.1C
300
300
300
300
1000 20 + 0.1C
1000 20 + 0.1C
300 20 + 0.1C
300 20 + 0.1C
300
300
300
300
ns
ns
ns
ns
r(SDA)
r(SCL)
f(SDA)
f(SCL)
b
b
b
b
b
b
b
b
Delay time, SCL high to
SDA high for a STOP
condition
IC28
IC29
t
4
0.6
4
0.6
µs
d(SCLH-SDAH)
Capacitance for each
C
10
10
10
10
pF
p
2
I C pin
†
C = total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed.
b
IC26
IC24
SDA
IC21
IC23
IC19
IC28
IC20
IC27
IC25
SCL
IC16
IC18
IC18
IC17
IC22
Stop
Start
Repeated
Start
Stop
2
Figure 5−38. I C Transmit Timings
118
SPRS245C
April 2004 − Revised January 2005
Mechanical Data
6
Mechanical Data
6.1 Package Thermal Resistance Characteristics
Table 6−1 and Table 6−2 provide the estimated thermal resistance characteristics for the TMS320VC5503
DSP package types.
Table 6−1. Thermal Resistance Characteristics (Ambient)
†
PACKAGE
R
Θ
(°C/W)
BOARD TYPE
AIRFLOW (LFM)
JA
37.1
High-K
0
35.1
33.7
32.2
70.3
61.6
56.5
49.3
71.2
61.8
58.9
54.8
103.6
84.2
77.8
69.4
High-K
High-K
High-K
Low-K
Low-K
Low-K
Low-K
High-K
High-K
High-K
High-K
Low-K
Low-K
Low-K
Low-K
150
250
500
0
GHH
150
250
500
0
150
250
500
0
PGE
150
250
500
†
Board types are as defined by JEDEC. Reference JEDEC Standard JESD51-9, Test Boards for Area
Array Surface Mount Package Thermal Measurements.
Table 6−2. Thermal Resistance Characteristics (Case)
†
PACKAGE
R
Θ
(°C/W)
BOARD TYPE
JC
GHH
13.8
13.8
2s JEDEC Test Card
PGE
2s JEDEC Test Card
†
Board types are as defined by JEDEC. Reference JEDEC Standard JESD51-9, Test Boards for Area Array
Surface Mount Package Thermal Measurements.
6.2 Packaging Information
The following packaging information reflects the most current released data available for the designated
device(s). This data is subject to change without notice and without revision of this document.
119
April 2004 − Revised January 2005
SPRS245C
PACKAGE OPTION ADDENDUM
www.ti.com
5-Apr-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
TMS320VC5503GHH
TMS320VC5503PGE
ACTIVE
ACTIVE
BGA
GHH
179
144
160
60
TBD
TBD
SNPB
Level-3-220C-168HR
LQFP
PGE
CU NIPDAU Level-4-220C-72HR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS
&
no Sb/Br)
-
please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MPBG058B – JANUARY 1998 – REVISED MAY 2002
GHH (S–PBGA–N179)
PLASTIC BALL GRID ARRAY
12,10
11,90
10,40 TYP
SQ
0,80
0,40
P
N
M
L
K
J
H
G
F
E
D
C
B
A
A1 Corner
1
2
3
4
5
6
7
8
9 10 11 12 13 14
Bottom View
0,95
0,85
1,40 MAX
Seating Plane
0,10
0,55
0,45
0,08
0,45
0,35
4173504-3/C 12/01
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. MicroStar BGAt configuration.
MicroStar BGA is a trademark of Texas Instruments.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MTQF017A – OCTOBER 1994 – REVISED DECEMBER 1996
PGE (S-PQFP-G144)
PLASTIC QUAD FLATPACK
108
73
109
72
0,27
M
0,08
0,17
0,50
0,13 NOM
144
37
1
36
Gage Plane
17,50 TYP
20,20
SQ
19,80
0,25
0,05 MIN
22,20
SQ
0°–7°
21,80
0,75
0,45
1,45
1,35
Seating Plane
0,08
1,60 MAX
4040147/C 10/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,
enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
orders and should verify that such information is current and complete. All products are sold subject to TI’s terms
and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty. Except where mandated by government requirements, testing of all
parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for
their products and applications using TI components. To minimize the risks associated with customer products
and applications, customers should provide adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,
copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process
in which TI products or services are used. Information published by TI regarding third-party products or services
does not constitute a license from TI to use such products or services or a warranty or endorsement thereof.
Use of such information may require a license from a third party under the patents or other intellectual property
of the third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of information in TI data books or data sheets is permissible only if reproduction is without
alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction
of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for
such altered documentation.
Resale of TI products or services with statements different from or beyond the parameters stated by TI for that
product or service voids all express and any implied warranties for the associated TI product or service and
is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.
Following are URLs where you can obtain information on other Texas Instruments products and application
solutions:
Products
Applications
Audio
Amplifiers
amplifier.ti.com
www.ti.com/audio
Data Converters
dataconverter.ti.com
Automotive
www.ti.com/automotive
DSP
dsp.ti.com
Broadband
Digital Control
Military
www.ti.com/broadband
www.ti.com/digitalcontrol
www.ti.com/military
Interface
Logic
interface.ti.com
logic.ti.com
Power Mgmt
Microcontrollers
power.ti.com
Optical Networking
Security
www.ti.com/opticalnetwork
www.ti.com/security
www.ti.com/telephony
www.ti.com/video
microcontroller.ti.com
Telephony
Video & Imaging
Wireless
www.ti.com/wireless
Mailing Address:
Texas Instruments
Post Office Box 655303 Dallas, Texas 75265
Copyright 2005, Texas Instruments Incorporated
相关型号：
©2020 ICPDF网 联系我们和版权申明