TMS370C742 [TI]
CMOS EEPROM/EPROM Technologies on a Single Device; 在单台设备的CMOS EEPROM / EPROM技术型号: | TMS370C742 |
厂家: | TEXAS INSTRUMENTS |
描述: | CMOS EEPROM/EPROM Technologies on a Single Device |
文件: | 总69页 (文件大小:860K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
TMS370Cx4x
8-BIT MICROCONTROLLER
SPNS016C -- NOVEMBER 1992 -- REVISED FEBRUARY 1997
FN AND FZ PACKAGES
(TOP VIEW)
D
D
CMOS/EEPROM/EPROM Technologies on a
Single Device
-- Mask-ROM Devices for High Volume
Production
-- One-Time-Programmable (OTP) Devices
for Low-Volume Production
-- Reprogrammable EPROM Devices for
Prototyping Purposes
6
5
4
3
2
1
44 43 42 41 40
39
MC
INT1
INT2
INT3
7
8
9
XTAL2/CLKIN
XTAL1
T1IC/CR
T1PWM
T1EVT
AN7
AN6
AN5
AN4
38
37
36
35
34
33
32
31
30
29
V
10
11
12
13
14
15
16
17
CC
Flexible Operating Features
V
CC3
A7
A6
-- Low-Power Modes: STANDBY and HALT
-- Commercial, Industrial, and Automotive
Temperature Ranges
V
SS
A5
A4
A3
-- Clock Options:
V
SS3
18 19 20 21 22 23 24 25 26 27 28
-- Divide-by-1 (2 MHz--5 MHz SYSCLK)
Phase-Locked Loop (PLL)
-- Divide-by-4 (0.5 MHz--5 MHz SYSCLK)
-- Vo l t a g e ( V CC) 5 V 10%
Internal System Memory Configurations
-- On-Chip Program Memory Versions
-- ROM: 4K Bytes or 8K Bytes
-- EPROM: 8K Bytes
-- Data EEPROM: 256 Bytes
-- Static RAM: 256 Bytes Usable as
Registers
Two 16-Bit General-Purpose Timers
-- Software Configurable as
Two 16-Bit Event Counters, or
Two 16-Bit Pulse Accumulators, or
Three 16-Bit Input Capture Functions, or
Four Compare Registers, or
Two Self-Contained
JC, JD, N, AND NJ PACKAGES
(TOP VIEW)
D
D
B2
T2AEVT
T2AIC2/PWM
T2AIC1/CR
RESET
INT1
1
2
3
4
5
6
7
8
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
B1
B0
SCITXD
SCIRXD
SCICLK
D5
INT2
INT3
MC
XTAL2/CLKIN
XTAL1
T1IC/CR
T1PWM
T1EVT
AN7
V
9
CC
A7
A6
10
11
12
13
14
15
16
17
18
19
20
V
SS
A5
A4
A3
A2
A1
A0
D7
D4
AN6
V
V
CC3
SS3
AN3
AN2
D6
D3
Pulse-Width-Modulation (PWM)
Functions
D
D
Serial Communications Interface 1 (SCI1)
-- Asynchronous and Isosynchronous†
Modes
-- Full Duplex, Double Buffered RX and TX
-- Two Multiprocessor Communications
Formats
CMOS/Package/TTL Compatible I/O Pins
-- All Peripheral Function Pins Software
Configurable for Digital I/O
-- 40-Pin Plastic and Ceramic Dual-In-Line
Packages/27 Bidirectional, 5 Input Pins
-- 44-Pin Plastic and Ceramic Leaded Chip
Carrier Packages/27 Bidirectional, 9
Input Pins
D
Eight-Bit ADC1
-- Four Channels in 40-Pin Packages
-- Eight Channels in 44-Pin Packages
Flexible Interrupt Handling
TMS370 Series Compatibility
Workstation/PC-Based Development
System
-- C Compiler Support
-- Real-Time In-Circuit Emulation
-- C Source Debug
-- Extensive Breakpoint/Trace Capability
-- Software Performance Analysis
-- Multi-Window User Interface
-- EEPROM/EPROM Programming
D
D
D
D
On-Chip 24-Bit Watchdog Timer
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
†
Isosynchronous = Isochronous
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright 1997, Texas Instruments Incorporated
1
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251--1443
TMS370Cx4x
8-BIT MICROCONTROLLER
SPNS016C -- NOVEMBER 1992 -- REVISED FEBRUARY 1997
Pin Descriptions
PIN
†
NO.
DESCRIPTION
TYPE
DIP (40) LCC (44)
A0
A1
A2
A3
A4
A5
A6
A7
18
17
16
15
14
13
11
10
20
19
18
17
16
15
13
12
I/O
Port A pins are general-purpose bidirectional I/O ports.
Port B pins are general-purpose bidirectional I/O ports.
B0
B1
B2
39
40
1
44
1
2
I/O
I/O
D3
D4
D5
D6
D7
21
20
35
22
19
23
22
40
24
21
Port D pins are general-purpose bidirectional I/O ports.
D3 is also configurable as SYSCLK.
AN0/E0
AN1/E1
AN2/E2
AN3/E3
AN4/E4
AN5/E5
AN6/E6
AN7/E7
—
—
23
24
—
—
27
28
25
26
27
28
30
31
32
33
Analog-to-digital converter 1 (ADC1) analog input channels or positive reference pins; any
ADC1 channel can be programmed as general-purpose input pin (E port) if not used as an
analog input or reference channel.
I
V
V
26
25
11
29
ADC1 converter positive supply voltage and optional positive reference input pin
ADC1 converter ground supply and low reference input pin
CC3
SS3
INT1
INT2
INT3
6
7
8
7
8
9
I
External (non-maskable or maskable) interrupt/general-purpose input pin
External maskable interrupt input/general-purpose bidirectional pin
External maskable interrupt input/general-purpose bidirectional pin
I/O
I/O
T1IC/CR
T1PWM
T1EVT
31
30
29
36
35
34
Timer 1 input capture/counter reset input pin/general-purpose bidirectional pin
Timer 1 pulse-width-modulation output pin/general-purpose bidirectional pin
Timer 1 external event input pin/general-purpose bidirectional pin
I/O
I/O
I/O
T2AIC1/CR
T2AIC2/PWM
T2AEVT
4
3
2
5
4
3
Timer 2A input capture/counter reset input pin/general-purpose bidirectional pin
Timer 2A input capture 2/PWM output pin/general-purpose bidirectional pin
Timer 2A external event input pin/general-purpose bidirectional pin
‡
SCITXD
SCIRXD
SCICLK
38
37
36
43
42
41
SCI transmit data output pin/general-purpose bidirectional pin
SCI receive data input pin/general-purpose bidirectional pin
SCI bidirectional serial clock pin/general-purpose bidirectional pin
System reset bidirectional pin. As input, RESET initializes microcontroller; as open-drain
RESET
MC
5
6
I/O
I
output, RESET indicates detection of an internal fault by the watchdog or oscillator fault cir-
cuit.
Mode control input pin; enables the EEPROM write-protection-override (WPO) mode, also
34
39
EPROM V
.
PP
XTAL1
XTAL2/CLKIN
32
33
37
38
I
O
Internal-oscillator output for crystal
Internal-oscillator crystal input/external clock source input
V
V
9
12
10
14
Positive supply voltage
Ground reference
CC
SS
†
‡
I = input, O = output
The three-pin configuration SCI is referred to as SCI1.
2
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251--1443
TMS370Cx4x
8-BIT MICROCONTROLLER
SPNS016C -- NOVEMBER 1992 -- REVISED FEBRUARY 1997
functional block diagram
XTAL2/
INT1 INT2 INT3 XTAL1 CLKIN MC
RESET
AN0--AN7
40-PIN DIP: AN2, AN3,
AN6, AN7
44-PIN PLCC:AN0--AN7
Clock Options
Divide-by-4 or
Divide-by-1(PLL)
V
V
CC3
SS3
System
Control
A-to-D
Converter 1
Interrupts
(40-Pin: 4 CH)
(44-Pin: 8 CH)
RAM
256 Bytes
(Usable as Registers)
CPU
Serial
Communications
Interface 1
SCIRXD
SCITXD
SCICLK
Program Memory
ROM: 4K or 8K Bytes
EPROM:8K Bytes
Data EEPROM
0 or 256 Bytes
T2AIC1/CR
T2AEVT
T2AIC2/PWM
Timer 2A
Timer 1
T1IC/CR
T1EVT
T1PWM
Watchdog
V
CC
V
SS
Port A
8
Port B
3
Port D
5
description
The TMS370C040A, TMS370C042A, TMS370C340A, TMS370C342A, TMS370C742A, and SE370C742A
devices are members of the TMS370 family of single-chip 8-bit microcontrollers. Unless otherwise noted, the
term TMS370Cx4x refers to these devices. TMS370 family provides cost-effective real-time system control
through integration of advanced peripheral function modules and various on-chip memory configurations.
The TMS370Cx4x family is implemented using high-performance silicon-gate CMOS EPROM and EEPROM
technology. The low-operating power, wide-operating temperature range, and noise immunity of CMOS
technology coupled with the high performance and extensive on-chip peripheral functions make the
TMS370Cx4x devices attractive in system designs for automotive electronics, industrial motor, computer
peripheral control, telecommunications, and consumer applications.
The TMS370Cx4x devices contain the following on-chip peripheral modules:
D
Eight-channel (for 44 pin device) or four-channel (for 40-pin device) 8-bit analog-to-digital converter 1
(ADC1)
D
D
Serial communications interface 1 (SCI1)
Two 16-bit general-purpose timers (one with an 8-bit prescaler)
All trademarks are the property of their respective owners.
3
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251--1443
TMS370Cx4x
8-BIT MICROCONTROLLER
SPNS016C -- NOVEMBER 1992 -- REVISED FEBRUARY 1997
description (continued)
D
One 24-bit general-purpose watchdog timer
Table 1 provides an overview of the various memory configurations of the TMS370Cx4x devices.
Table 1. Memory Configurations
PACKAGES
44 PIN/PLCC/CLCC OR
40 PIN PDIP/CDIP/PSDIP/CSDIP
PROGRAM MEMORY (BYTES)
DATA MEMORY (BYTES)
DEVICE
ROM
EPROM
RAM
EEPROM
FN-PLCC
N-PDIP
NJ-PSDIP
TMS370C040A
TMS370C042A
TMS370C340A
TMS370C342A
TMS370C742A
4K
—
256
256
†
FN-PLCC
N-PDIP
8K
4K
8K
—
—
—
256
256
256
256
256
256
—
†
NJ-PSDIP
FN-PLCC
N-PDIP
†
NJ-PSDIP
FN-PLCC
N-PDIP
—
—
†
NJ-PSDIP
FN-PLCC
N-PDIP
8K
8K
256
256
†
NJ-PSDIP
FZ-CLCC
JD-CDIP
JC-CSDIP
‡
SE370C742A
—
†
‡
The NJ designator for the 40-pin plastic shrink DIP package was known formerly as the N2. The mechanical drawing of the NJ is identical to the
N2 package and did not need to be requalified.
System evaluators and development tools are for use only in a prototype environment, and their reliability has not been characterized.
The suffix letter (A) appended to the device name (shown in the first column of Table 1) indicates the
configuration of the device. ROM and EPROM devices have different configurations as indicated in Table 2.
ROM devices with the suffix letter A are configured through a programmable contact during manufacture.
Table 2. Suffix Letter Configuration
DEVICE
WATCHDOG TIMER
Standard
CLOCK
LOW-POWER MODE
EPROM A
Divide-by-4 (standard oscillator)
Enabled
Standard
Divide-by-4 (standard oscillator)
or Divide-by-1 (PLL)
Hard
ROM A
Enabled or disabled
Simple
The 4K bytes and 8K bytes of mask-programmable ROM in the TMS370C040A, TMS370C042A,
TMS370C340A and TMS370C342A are replaced in the TMS370C742 with 8K bytes of EPROM while all other
available memory and on-chip peripherals are identical, with the exception of no data EEPROM on the
TMS370C340A and TMS370C342A devices. The OTP (TMS370C742A) device and the reprogrammable
device (SE370C742A) are available.
TMS370C742A (OTP) devices are available in plastic packages. This microcontroller is effective to use for
immediate production updates for other members of the TMS370Cx4x family or for low-volume production runs
when the mask charge or cycle time for the low-cost mask ROM devices is not practical.
4
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251--1443
TMS370Cx4x
8-BIT MICROCONTROLLER
SPNS016C -- NOVEMBER 1992 -- REVISED FEBRUARY 1997
description (continued)
The SE370C742A has a windowed ceramic package to allow reprogramming of the program EPROM memory
during the development/prototyping phase of design. The SE370C742A device allows quick updates to
breadboards and prototype systems while iterating initial designs.
The TMS370Cx4x family provides two low-power modes (STANDBY and HALT) for applications where
low-power consumption is critical. Both modes stop all central processing unit (CPU) activity (that is, no
instructions are executed). In the STANDBY mode, the internal oscillator and the general-purpose timer remain
active. In the HALT mode, all device activity is stopped. The device retains all RAM data and peripheral
configuration bits throughout both low-power modes.
The TMS370Cx4x features advanced register-to-register architecture that allows arithmetic and logical
operations withoutrequiringanaccumulator (e.g., ADD R24, R47;add the contents ofregister 24 to thecontents
of register 47 and store the result in register 47). The TMS370Cx4x family is fully instruction-set-compatible,
allowing easy transition between members of the TMS370 8-bit microcontroller family.
The TMS370Cx4x family offers an 8-channel ADC1 with 8-bit accuracy for the 44-pin PLCC packages and also
offers a 4-channel ADC1 for the 40-pin DIP packages. The 33-s conversion time at 5-MHz SYSCLK and the
variable sample period, combined with selectable positive reference voltage sources, turn analog signals into
digital data.
The serial communications interface 1 (SCI1) module is a built-in serial interface that can be programmed to
be asynchronous or isosynchronous to give two methods of serial communications. The SCI allows standard
RS-232-C communications with other common data transmission equipment. The CPU takes no part in serial
communications except to write data to be transmitted to a register and to read data received from a register.
The TMS370Cx4x family provides the system designer with very economical, efficient solutions to real-time
control applications. The TMS370 family extended development system (XDS) and compact development
tool (CDT) solve the challenge of efficiently developing the software and hardware required to design the
TMS370Cx4x into an ever-increasing number of complex applications. The application source code can be
written in assembly and C languages, and the output code can be generated by the linker. The TMS370 family
XDS communicates through a standard RS-232-C interface with a personal computer, allowing use of the
personal computer editors and software utilities already familiar to the designer. The TMS370 family XDS
emphasizes ease-of-use through extensive use of menus and screen windowing so that a system designer with
minimal training can begin developing software. Precise real-time in-circuit emulation and extensive symbolic
debug and analysis tools ensure efficient software and hardware implementation, as well as reduced
time-to-market cycle.
The TMS370Cx4x family together with the TMS370 family XDS, CDT370, starter kit, software tools, the
SE370C742A reprogrammable devices, comprehensive product documentation, and customer support
provide a complete solution for the needs of the system designer.
XDS and CDT are trademarks of Texas Instruments Incorporated.
5
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251--1443
TMS370Cx4x
8-BIT MICROCONTROLLER
SPNS016C -- NOVEMBER 1992 -- REVISED FEBRUARY 1997
central processing unit (CPU)
The CPU used on the TMS370Cx4x device is the high-performance 8-bit TMS370 CPU module. The ’x4x
implements an efficient register-to-register architecture that eliminates the conventional accumulator
bottleneck. The complete ’x4x instruction map is shown in Table 17 in the TMS370Cx4x instruction set overview
section.
The ’370Cx4x CPU architecture provides the following components:
D
CPU registers:
-- A stack pointer (SP) that points to the last entry in the memory stack
-- A status register (ST) that monitors the operation of the instructions and contains the
global-interrupt-enable bits
-- A program counter (PC) that points to the memory location of the next instruction to be executed
Figure 1 illustrates the CPU registers and memory blocks.
Program Counter
0
15
7
0
Legend:
C=Carry
Stack Pointer (SP)
N=Negative
Status Register (ST)
Z=Zero
C
7
N
6
Z
5
V
4
IE2 IE1
V=Overflow
IE2=Level 2 interrupts Enable
IE1=Level 1 interrupts Enable
3
2
1
0
RAM (Includes up to 256-Byte Registers File)
0000h
0000h
R0(A)
R1(B)
256-Byte RAM (0000h--00FFh)
0001h
0002h
0003h
00FFh
0100h
†
Reserved
R2
R3
0FFFh
1000h
10FFh
1100h
Peripheral File
†
Reserved
1EFFh
1F00h
256-Byte Data EEPROM
1FFFh
2000h
‡
Not Available
5FFFh
6000h
R127
007Fh
8K-Byte ROM/EPROM (6000h--6FFFh)
4K-Byte ROM (7000h--7FFFh)
6FFFh
7000h
7FBFh
7FC0h
Interrupts and Reset Vectors;
Trap Vectors
R255
7FFFh
00FFh
†
‡
Reserved means the address space is reserved for future expansion.
Not available means the address space is not accessible.
Figure 1. Programmer’s Model
6
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251--1443
TMS370Cx4x
8-BIT MICROCONTROLLER
SPNS016C -- NOVEMBER 1992 -- REVISED FEBRUARY 1997
central processing unit (CPU) (continued)
A memory map that includes:
D
-- 256-byte general-purpose RAM that can be used for data memory storage, program instructions,
general-purpose registers, or the stack
-- A peripheral file that provides access to all internal peripheral modules, system-wide control functions
and EEPROM/EPROM programming control
-- 256-byte EEPROM module that provides in-circuit programmability and data retention in power-off
conditions
-- 4K- or 8K-byte ROM or 8K-byte EPROM program memory
stack pointer (SP)
The SP is an 8-bit CPU register. The stack operates as a last-in, first-out, read/write memory. The stack is used
typically to store the return address on subroutine calls as well as the status-register contents during interrupt
sequences.
The SP points to the last entry or top of the stack. The SP is incremented automatically before data is pushed
onto the stack and decremented after data is popped from the stack. The stack can be placed anywhere in the
on-chip RAM memory.
status register (ST)
The ST monitors the operation of the instructions and contains the global interrupt-enable bits. The ST includes
four status bits (condition flags) and two interrupt-enable bits:
D
The four status bits indicate the outcome of the previous instruction; conditional instructions (for example,
the conditional jump instructions) use the status bits to determine program flow.
D
The two interrupt-enable bits control the two interrupt levels.
The ST register, status-bit notation, and status-bit definitions are shown in Table 3.
Table 3. Status Registers
7
C
6
N
5
Z
4
V
3
2
1
0
IE2
IE1
Reserved
Reserved
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
R = read, W = write, 0 = value after reset
program counter (PC)
The contents of the PC point to the memory location of the next instruction to be executed. The PC consists
of two 8-bit registers in the CPU: the program counter high (PCH) and program counter low (PCL). These
registers contain the most significant byte (MSbyte) and least significant byte (LSbyte) of a 16-bit address.
The contents of the reset vector (7FFEh, 7FFFh) are loaded into the program counter during reset. The PCH
(MSbyte of the PC) is loaded with the contents of memory location 7FFEh, and the PCL (LSbyte of the PC) is
loaded with the contents of memory location 7FFFh. Figure 2 shows this operation using an example value of
6000h as the contents of memory locations 7FFEh and 7FFFh (reset vector).
7
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251--1443
TMS370Cx4x
8-BIT MICROCONTROLLER
SPNS016C -- NOVEMBER 1992 -- REVISED FEBRUARY 1997
program counter (PC) (continued)
Program Counter (PC)
Memory
0000h
PCH
60
PCL
00
60
00
7FFEh
7FFFh
Figure 2. Program Counter After Reset
memory map
The TMS370Cx4x family architecture is based on the Von Neumann architecture, where the program memory
and data memory share a common address space. All peripheral input/output is memory mapped in this same
commonaddress space. As showninFigure 3, theTMS370Cx4x family provides memory-mapped RAM, ROM,
data EEPROM, EPROM, input/output pins, peripheral functions, and system interrupt vectors.
The peripheral file contains all input/output port control, peripheral status and control, EPROM and EEPROM
memory programming, and system-wide control functions. The peripheral file is located between 1010h and
107Fh and is logically divided into seven peripheral file frames of 16 bytes each. Each on-chip peripheral is
assigned to a separate frame through which peripheral control and data information is passed.
8
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251--1443
TMS370Cx4x
8-BIT MICROCONTROLLER
SPNS016C -- NOVEMBER 1992 -- REVISED FEBRUARY 1997
memory map (continued)
Reserved
1000h -- 100Fh
1010h -- 101Fh
1020h -- 102Fh
1030h -- 103Fh
1040h -- 104Fh
1050h -- 105Fh
1060h -- 106Fh
1070h -- 107Fh
0000h
System Control
256-Byte RAM (Register File/Stack)
Digital Port Control
Reserved
00FFh
0100h
Reserved
Timer 1 Peripheral Control
SCI1 Peripheral Control
Timer 2A Peripheral Control
ADC1 Peripheral Control
0FFFh
1000h
Peripheral File
10FFh
1100h
Reserved
1EFFh
1F00h
Reserved
1080h -- 10FFh
256-Byte Data EEPROM
1FFFh
2000h
Vectors
Not Available
Trap 15-0
7FC0h -- 7FDFh
7FE0h -- 7FEBh
7FECh -- 7FEDh
7FEEh -- 7FEFh
7FF0h -- 7FF1h
7FF2h -- 7FF3h
7FF4h -- 7FF5h
7FF6h -- 7FF7h
7FF8h -- 7FF9h
7FFAh -- 7FFBh
7FFCh -- 7FFDh
7FFEh -- 7FFFh
5FFFh
6000h
Reserved
A-D Converter 1
Timer 2A
8K-Byte ROM or EPROM
(0000h--7FFFh)
6FFFh
7000h
4K-Byte ROM
(7000h--7FFFh)
Serial Comm I/F TX
Serial Comm I/F RX
Timer 1
7FBFh
7FC0h
Interrupts and Reset
Vectors; Trap Vectors
7FFFh
8000h
Reserved
Not Available
Interrupt 3
FFFFh
Interrupt 2
Interrupt 1
Reset
Figure 3. TMS370Cx4x Memory Map
RAM/register file (RF)
Locations within the RAM address space can serve as the RF, general-purpose read/write memory, program
memory, or the stack instructions. The TMS370Cx4x devices contain 256 bytes of internal RAM memory
mapped beginning at location 0000h (R0) and continuing through location 00FFh (R255).
The first two registers, R0 and R1, are also called register A and B, respectively. Some instructions implicitly
use register A or B; for example, the instruction LDSP (load SP) assumes that the value to be loaded into the
stack pointer is contained in register B. Registers A and B are the only registers cleared on reset.
peripheral file (PF)
The TMS370Cx4x control registers contain all the registers necessary to operate the system and peripheral
modules on the device. The instruction set includes some instructions that access the PF directly. These
instructions designate the register by the number of the PF relative to 1000h, preceded by P0 for a hexadecimal
designator or P for a decimal designator. For example, the system control register 0 (SCCR0) is located at
address 1010h; its peripheral file hexadecimal designator is P010, and its decimal designator is P16. Table 4
shows the TMS370Cx4x PF address map.
9
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251--1443
TMS370Cx4x
8-BIT MICROCONTROLLER
SPNS016C -- NOVEMBER 1992 -- REVISED FEBRUARY 1997
peripheral file (PF) (continued)
Table 4. TMS370Cx4x Peripheral File Address Map
PERIPHERAL FILE
DESIGNATOR
ADDRESS RANGE
DESCRIPTION
1000h--100Fh
1010h--101Fh
1020h--102Fh
1030h--103Fh
1040h--104Fh
1050h--105Fh
1060h--106Fh
1070h--107Fh
1080h--10FFh
P000--P00F
P010--P01F
P020--P02F
P030--P03F
P040--P04F
P050--P05F
P060--P06F
P070--P07F
P080--P0FF
Reserved for factory test
System and EPROM/EEPROM control registers
Digital I/O port control registers
Reserved
Timer 1 registers
Serial communications interface 1 registers
Timer 2A registers
Analog-to-digital converter 1 registers
Reserved
data EEPROM
TheTMS370Cx4x devices, containing256 bytes of dataEEPROM, havememory mappedbeginning atlocation
1F00h and continuing through location 1FFFh. Writing to the data EEPROM module is controlled by the data
EEPROM control register (DEECTL) and the write-protection register (WPR). Programming algorithm
examples are available in the TMS370 Family User’s Guide (literature number SPNU127) or the TMS370
Family Data Manual (literature number SPNS014B). The data EEPROM features include the following:
D
Programming:
-- Bit-, byte-, and block-write/erase modes
-- Internal charge pump circuitry. No external EEPROM programming voltage supply is needed.
-- Control register: Data EEPROM programming is controlled by the DEECTL located in the PF frame
beginning at location P01A (see Table 5).
-- In-circuit programming capability. There is no need to remove the device to program it.
Write protection. Writes to the data EEPROM are disabled during the following conditions.
-- Reset. All programming of the data EEPROM module is halted.
-- Write protection active. There is one write-protect bit per 32-byte EEPROM block.
-- Low-power mode operation
D
D
Write protection can be overridden by applying 12 V to MC.
Table 5. Data EEPROM and PROGRAM EPROM Control Register Memory Map
ADDRESS
P01A
SYMBOL
DEECTL
—
NAME
DATA EEPROM Control Register
Reserved
P01B
P01C
EPCTL
Program EPROM Control Register
10
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TMS370Cx4x
8-BIT MICROCONTROLLER
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program EPROM
The TMS370C742A device contains 8K bytes of EPROM mapped, beginning at location 6000h and continuing
through location 7FFFh. Memory addresses 7FE0h through 7FEBh are reserved for Texas Instruments (TI),
and memory addresses 7FECh through 7FFFh are reserved for interrupt and reset vectors. Trap vectors, used
with TRAP0 through TRAP15 instructions, are located between addresses 7FC0h and 7FDFh. Reading the
program EPROM modules is identical to reading other internal memory. During programming, the EPROM is
controlled by the EPROM control register (EPCTL). The program EPROM module features include:
D
Programming
-- In-circuit programming capability if VPP is applied to MC
-- Control register: EPROM programming is controlled by the EPROM control register (EPCTL) located in
the peripheral file (PF) frame at location P01C as shown in Table 5.
D
Write protection: writes to the program EPROM are disabled under the following conditions:
-- Reset: All programming to the EPROM module is halted.
-- Low-power modes
-- 13 V not applied to MC
program ROM
The program ROM consists of 4K or 8K bytes of mask-programmable read-only memory. The program ROM
is used for permanent storage of data or instructions. Memory addresses 7FE0h through 7FEBh are reserved
for TI, and memory addresses 7FECh through 7FFFh are reserved for interrupt and reset vectors. Trap vectors,
used with TRAP0 through TRAP15 instructions, are located between addresses 7FC0h and 7FDFh.
Programming of the mask ROM is performed at the time of device fabrication.
system reset
The system-reset operation ensures an orderly start-up sequence for the TMS370Cx4x CPU-based device.
There are up to three different actions that can cause a system reset to the device. Two of these actions are
generated internally, while one (RESET pin) is controlled externally. These actions are as follows:
D
Watchdog (WD) timer. A watchdog-generated reset occurs if an improper value is written to the WD key
register, or if the re-initialization does not occur before the watchdog timer timeout . See the TMS370 Family
User’s Guide (literature number SPNU127) for more information.
D
D
Oscillator reset. Reset occurs when the oscillator operates outside of the recommended operating range.
See the TMS370 Family User’s Guide (literature number SPNU127) for more information.
External RESET pin. A low level signal can trigger an external reset. To ensure a reset, the external signal
should be held low for one SYSCLK cycle. Signals of less than one SYSCLK can generate a reset. See the
TMS370 Family User’s Guide (literature number SPNU127) for more information.
Once a reset source is activated, the external RESET pin is driven (active) low for a minimum of eight SYSCLK
cycles. This allows the ’x4x device to reset external system components. Additionally, if a cold start (VCC is off
for several hundred milliseconds) condition or oscillator failure occurs or the RESET pin is held low, then the
reset logic holds the device in a reset state for as long as these actions are active.
After a reset, the program can check the oscillator-fault flag (OSC FLT FLAG, SCCR0.4), the cold-start flag
(COLD START, SCCR0.7) and the watchdog reset (WD OVRFL INT FLAG, T1CTL2.5) to determine the source
of the reset. A reset does not clear these flags. Table 6 lists the reset sources.
TI is a trademark of Texas Instruments Incorporated.
11
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system reset (continued)
Table 6. Reset Sources
REGISTER
SCCR0
ADDRESS
1010h
PF
BIT NO.
CONTROL BIT
SOURCE OF RESET
Cold (power-up)
P010
P010
P04A
7
4
5
COLD START
OSC FLT FLAG
SCCR0
1010h
Oscillator out of range
Watchdog timer timeout
T1CTL2
104Ah
WD OVRFL INT FLAG
Once a reset is activated, the following sequence of events occurs:
1. The CPU registers are initialized: ST = 00h, SP = 01h (reset state).
2. Registers A and B are initialized to 00h (no other RAM is changed).
3. The contents of the LSbyte of the reset vector (07FFh) are read and stored in the PCL.
4. The contents of the MSbyte of the reset vector (07FEh) are read and stored in the PCH.
5. Program execution begins with an opcode fetch from the address pointed to the PC.
The reset sequence takes 20 SYSCLK cycles from the time the reset pulse is released until the first opcode
fetch. During a reset, RAM contents (except for registers A and B) remain unchanged, and the module control
register bits are initialized to their reset state.
12
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interrupts
The TMS370 family software-programmable interrupt structure supports flexible on-chip and external interrupt
configurations to meet real-time interrupt-driven application requirements. The hardware interrupt structure
incorporates two priority levels as shown in Figure 4. Interrupt level 1 has a higher priority than interrupt
level 2. The two priority levels can be independently enabled by the global-interrupt enable bits (IE1 and IE2)
of the status register.
EXT INT 3
INT 3
EXT INT 2
INT 2
TIMER 2A
TIMER 1
Overflow
INT3 PRI
Overflow
Compare1
Ext Edge
Compare2
Compare1
Ext Edge
INT2 PRI
EXT INT1
CPU
Compare2
Input Capture 1
Watchdog
INT1
Input Capture 1
Input Capture 2
NMI
T2A PRI
T1 PRI
Priority
Logic
INT1 PRI
STATUS REG
IE1
Level 1 INT
Level 2 INT
IE2
Enable
AD INT
AD PRI
SCI INT
TX
RX
TXPRI
RXPRI
BRKDT
TXRDY
RXRDY
A/D
Figure 4. Interrupt Control
Each system interrupt is configured independently on either the high- or low-priority chain by the application
program during system initialization. Within each interrupt chain, the interrupt priority is fixed by the position of
the system interrupt. However, since each system interrupt is configured selectively on either the high- or
low-priority interrupt chain, the application program can elevate any system interrupt to the highest priority.
Arbitration between the two priority levels is performed within the CPU. Arbitration within each of the priority
13
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interrupts (continued)
chains is performed within the peripheral modules to support interrupt expansion to future modules. Pending
interrupts are serviced upon completion of current instruction execution, depending on their interrupt mask and
priority conditions.
The TMS370Cx4x has eight hardware system interrupts (plus RESET) as shown in Table 7. Each system
interrupt has a dedicated interrupt vector located in program memory through which control is passed to the
interrupt service routines. A system interrupt can have multiple interrupt sources (e.g., SCI RXNT has two
interrupt sources). All of the interrupt sources are individually maskable by local interrupt-enable control bits in
the associated peripheral file. Each interrupt source FLAG bit is individually readable for software polling or for
determining which interrupt source generated the associated system interrupt.
Five of the system interrupts are generated by on-chip peripheral functions, and three external interrupts are
supported. Software configuration of the external interrupts is performed through the INT1, INT2, and INT3
control registers in peripheral file frame 1. Each external interrupt is individually software-configurable for input
polarity (rising or falling) for ease of system interface. External interrupt INT1 is software-configurable as either
a maskable or non-maskable interrupt. When INT1 is configured as non-maskable, it cannot be masked by the
individual- or global-enable mask bits. The INT1 NMI bit is protected during non-privileged operation and,
therefore, should be configured during the initialization sequence following reset. To maximize pin flexibility,
external interrupts INT2 and INT3 can be software-configured as general-purpose input/output pins if the
interrupt function is not required (INT1 can be configured similarly as an input pin).
Table 7. Hardware System Interrupts
SYSTEM
INTERRUPT
VECTOR
ADDRESS
†
INTERRUPT SOURCE
INTERRUPT FLAG
PRIORITY
External RESET
Watchdog Overflow
Oscillator Fault Detect
COLD START
WD OVRFL INT FLAG
OSC FLT FLAG
‡
RESET
7FFEh, 7FFFh
1
‡
External INT1
External INT2
External INT3
INT1 FLAG
INT2 FLAG
INT3 FLAG
INT1
7FFCh, 7FFDh
7FFAh, 7FFBh
7FF8h, 7FF9h
2
3
4
‡
INT2
†
INT3
Timer 1 Overflow
T1 OVRFL INT FLAG
T1C1 INT FLAG
T1C2 INT FLAG
T1EDGE INT FLAG
T1IC INT FLAG
WD OVRFL INT FLAG
Timer 1 Compare 1
Timer 1 Compare 2
Timer 1 External Edge
Timer 1 Input Capture
Watchdog Overflow
§
T1INT
7FF4h, 7FF5h
5
SCI RX Data Register Full
SCI RX Break Detect
RXRDY FLAG
BRKDT FLAG
‡
RXINT
7FF2h, 7FF3h
7FF0h, 7FF1h
6
7
SCI TX Data Register Empty
TXRDY FLAG
TXINT
T2AINT
ADINT
Timer 2A Overflow
T2A OVRFL INT FLAG
T2AC1 INT FLAG
T2AC2 INT FLAG
T2AEDGE INT FLAG
T2AIC1 INT FLAG
T2AIC2 INT FLAG
Timer 2A Compare 1
Timer 2A Compare 2
Timer 2A External Edge
Timer 2A Input Capture 1
Timer 2A Input Capture 2
7FEEh, 7FEFh
7FECh, 7FEDh
8
9
A-D Conversion Complete
AD INT FLAG
†
‡
§
Relative priority within an interrupt level.
Releases microcontroller from STANDBY and HALT low-power modes.
Releases microcontroller from STANDBY low-power mode.
14
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TMS370Cx4x
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privileged operation and EEPROM write-protection override
The TMS370Cx4x family has significant flexibility to enable the designer to software-configure the system and
peripherals to meet the requirements of a broad variety of applications. The nonprivileged mode of operation
ensures the integrity of the system configuration, once defined for an end application. Following a hardware
reset, the TMS370Cx4x operates in the privileged mode, where all peripheral file registers have unrestricted
read/write access and the application program configures the system during the initialization sequence
following reset. As the last step of system initialization, the PRIVILEGE DISABLE bit (SCCR2.0) is set to 1,
entering the nonprivileged mode and disabling write operations to specific configuration control bits within the
peripheral file. The system-configuration bits listed in Table 8 are write-protected during the nonprivileged mode
and must be configured by software prior to exiting the privileged mode.
Table 8. Privilege Bits
†
REGISTER
CONTROL BIT
NAME
LOCATION
P010.5
P010.6
PF AUTO WAIT
OSC POWER
SCCR0
P011.2
P011.4
MEMORY DISABLE
AUTOWAIT DISABLE
SCCR1
SCCR2
P012.0
P012.1
P012.3
P012.4
P012.6
P012.7
PRIVILEGE DISABLE
INT1 NMI
CPU STEST
BUS STEST
PWRDWN/IDLE
HALT/STANDBY
P05F.4
P05F.5
P05F.6
P05F.7
SCI ESPEN
SCI RX PRIORITY
SCI TX PRIORITY
SCI STEST
SCIPRI
P04F.6
P04F.7
T1 PRIORITY
T1 STEST
T1PRI
P06F.6
P06F.7
T2A PRIORITY
T2A STEST
T2APRI
P07F.5
P07F.6
P07F.7
AD ESPEN
AD PRIORITY
AD STEST
ADPRI
†
The privileged bits are shown in a bold typeface in the peripheral file frames of the
following sections.
The WPO mode provides an external hardware method for overriding the write protection registers (WPR) of
data EEPROM on the TMS370Cx4x. Applying a 12-V input to the MC pin after the RESET pin input goes high
causes the device to enter WPO mode. The high voltage on the MC pin during the WPO mode is not the
programming voltage for the data EEPROM or program EPROM. All EEPROM programming voltages are
generated on-chip. The WPO mode provides hardware system level capability to modify the content of data
EEPROM while the device remains in the application but only while requiring a 12-V external input on the MC
pin (normally not available in the end application except in a service or diagnostic environment).
low-power and IDLE modes
The TMS370Cx4x devices have two low-power modes (STANDBY and HALT) and an IDLE mode. For
mask-ROM devices, low-power modes can be disabled permanently through a programmable contact at the
time the mask is manufactured.
15
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low-power and IDLE modes (continued)
The STANDBY and HALT low-power modes significantly reduce power consumption by reducing or stopping
the activity of the various on-chip peripherals when processing is not required. Each of the low-power modes
is entered by executing the IDLE instruction when the PWRDWN/IDLE bit in SCCR2 has been set to 1. The
HALT/STANDBY bit in SCCR2 controls which low-power mode is entered.
In the STANDBY mode (HALT/STANDBY = 0 ), all CPU activity and most peripheral module activity is stopped;
however, the oscillator, internal clocks, Timer 1, and the receive start-bit-detection circuit of the SCI1 remain
active. System processing is suspended until a qualified interrupt (hardware RESET, external interrupt on INT1,
INT2, INT3, Timer 1 interrupt, or a low level on the receive pin of the serial communications interface 1) is
detected.
In the HALT mode (HALT/STANDBY=1 ), the TMS370Cx4x is placed in its lowest power-consumption mode.
The oscillator and internal clocks are stopped, causing all internal activity to be halted. System activity is
suspended until a qualified interrupt (hardware RESET external interrupt on INT1, INT2, INT3, or low level on
the receive pin of the SCI1) is detected. The power-down mode selection bits are sumarized in Table 9.
Table 9. Low-Power/Idle Control Bits
POWER-DOWN CONTROL BITS
PWRDWN/IDLE
(SCCR2.6)
HALT/STANDBY
(SCCR2.7)
MODE SELECTED
1
0
1
X
STANDBY
HALT
1
0
IDLE
X = don’t care
When low-power modes are disabled through a programmable contact in the mask-ROM devices, writing to the
SCCR2.6--7 bits is ignored. In addition, if an idle instruction is executed when low-power modes are disabled
through a programmable contact, the device always enters the IDLE mode.
To provide a method of always exiting low-power modes for mask-ROM devices, INT1 is automatically enabled
as a nonmaskable interrupt (NMI) during low-power modes when the hard watchdog mode is selected. This
means that the NMI is always generated, regardless of the interrupt enable flags.
The following information is preserved throughout both the STANDBY and HALT modes: RAM (register file),
CPU registers (stack pointer, program counter, and status register), I/O pin direction and output data, and status
registers of all on-chip peripheral functions. Since all CPU-instruction processing is stopped during the
STANDBY and HALT modes, the clocking of the WD timer is inhibited.
clock modules
The ’x4x family provides two clock options that are referred to as divide-by-1 (phase-locked loop) and
divide-by-4 (standard oscillator). Both the divide-by-1 and divide-by-4 options are configurable during the
manufacturing process of a TMS370 microcontroller. The ’x4x ROM-masked devices offer both options to meet
system engineering requirements. Only one of the two clock options is allowed on each ROM device. The ’742A
EPROM has only the divide-by-4.
The divide-by-1 clock module optionprovides thecapability for reduced electromagnetic interference (EMI) with
no added cost.
The divide-by-1 clock module option provides a one-to-one match of the external resonator frequency (CLKIN)
to the internal system clock (SYSCLK) frequency. The divide-by-4 option produces a SYSCLK which is
one-fourth of the frequency of the external resonator. Inside of the divide-by-1 module, the frequency of the
external resonator is multiplied by four, and the clock module then divides the resulting signal by four to provide
the four-phased internal system clock signals. The resulting SYSCLK is equal to the resonator frequency.
16
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clock modules (continued)
These are formulated as follows:
external resonator frequency
4
CLKIN
Divide-by-4 : SYSCLK =
Divide-by-1 : SYSCLK =
=
4
external resonator frequency × 4
= CLKIN
4
The main advantage of choosing a divide-by-1 oscillator is the reduction of EMI. The harmonics of low-speed
resonators extend through less of the emissions spectrum than the harmonics of faster resonators. The
divide-by-1 option provides the capability of reducing the resonator speed by four times, resulting in a steeper
decay of emissions produced by the oscillator.
system configuration registers
Table 10 contains system configuration and control functions and registers for controlling EEPROM
programming. The privileged bits are shown in a bold typeface.
Table 10. Peripheral File Frame 1: System Configuration Registers
PF
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
REG
COLD
START
OSC
POWER
PF AUTO
WAIT
OSC FLT
FLAG
MC PIN
WPO
MC PIN
DATA
P/C
MODE
P010
—
SCCR0
AUTOWAIT
DISABLE
MEMORY
DISABLE
P011
P012
—
—
—
—
—
—
—
SCCR1
SCCR2
HALT/
STANDBY
PWRDWN/
IDLE
BUS
STEST
CPU
STEST
INT1
NMI
PRIVILEGE
DISABLE
—
P013
to
Reserved
P016
INT1
FLAG
INT1
PIN DATA
INT1
POLARITY
INT1
PRIORITY
INT1
ENABLE
P017
P018
P019
—
—
—
—
INT1
INT2
INT2
FLAG
INT2
PIN DATA
INT2
DATA DIR
INT2
DATA OUT
INT2
POLARITY
INT2
PRIORITY
INT2
ENABLE
INT3
FLAG
INT3
PIN DATA
INT3
DATA DIR
INT3
DATA OUT
INT3
POLARITY
INT3
PRIORITY
INT3
ENABLE
INT3
—
—
P01A
P01B
P01C
BUSY
BUSY
—
—
—
—
AP
—
W1W0
W0
EXE
EXE
DEECTL
Reserved
VPPS
—
—
EPCTL
P01D
P01E
P01F
Reserved
17
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digital port control registers
Peripheral file frame 2 contains the digital I/O pin configuration and control registers. Table 11 and Table 12
detail the specific addresses, registers, and control bits within the peripheral file frame.
Table 11. Peripheral File Frame 2: Digital Port Control Registers
PF
P020
P021
P022
P023
P024
P025
P026
P027
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
Reserved
BIT 2
BIT 1
BIT 0
REG
APORT1
APORT2
ADATA
ADIR
Port A Control Register 2 (must be 0)
Port A Data
Port A Direction
Reserved
BPORT1
BPORT2
BDATA
BDIR
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Port B Control Register 2 (must be 0)
Port B Data
Port B Direction
P028
to
Reserved
P02B
P02C
P02D
P02E
P02F
Port D Control Register 1 (must be 0)
Port D Control Register 2 (must be 0)
Port D Data
—
—
—
—
—
—
—
—
—
—
—
—
DPORT1
DPORT2
DDATA
DDIR
†
Port D Direction
†
To configure pin D3 as SYSCLK, set port D control register 2 = 08h.
Table 12. Port Configuration Register Setup
abcd
00q1
abcd
00y0
PORT
PIN
A
B
D
0 -- 7
0 -- 2
3 -- 7
Data Out q
Data Out q
Data Out q
Data In y
Data In y
Data In y
a = Port Control Register 1
b = Port Control Register 2
c = Data
d = Direction
18
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timer 1 module
The programmable Timer 1 (T1) module of the TMS370Cx4x provides the designer with the enhanced timer
resources required to perform real-time system control. The T1 module contains the general-purpose timer and
the watchdog (WD) timer. The two independent 16-bit timers, T1 and WD, allow program selection of input clock
sources (real-time, external event, or pulse accumulate) with multiple 16-bit registers (input capture and
compare) for special timer function control. The T1 module includes three external device pins that can be used
for multiple counter functions (operation-mode dependent), or used as general-purpose I/O pins. The T1
module block diagram is shown in Figure 5.
Edge
Select
16-Bit
Capt/Comp
T1IC/CR
Register
16-Bit
Counter
PWM
Toggle
MUX
T1PWM
16
16-Bit
Compare
Register
Interrupt
Logic
8-Bit
Prescaler
T1EVT
Interrupt
Logic
16-Bit
Watchdog Counter
(Aux. Timer)
MUX
Figure 5. Timer 1 Block Diagram
D
D
Three T1 I/O pins
-- T1IC/CR: T1 input capture / counter-reset input pin, or general-purpose bidirectional I/O pin
-- T1PWM: T1 pulse-width-modulation (PWM) output pin, or general-purpose bidirectional I/O pin
-- T1EVT: T1 event input pin, or general-purpose bidirectional I/O pin
Two operational modes:
-- Dual-compare mode: Provides PWM signal
-- Capture/compare mode: Provides input capture pin
D
D
D
One 16-bit general-purpose resettable counter
One 16-bit compare register with associated compare logic
One 16-bit capture/compare register, which, depending on the mode of operation, operates as either a
capture or compare register.
D
D
One 16-bit WD counter can be used as an event counter, a pulse accumulator, or an interval timer if WD
feature is not needed.
Prescaler/clock sources that determine one of eight clock sources for general-purpose timer
19
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timer 1 module (continued)
D
Selectable edge-detection circuitry that, depending on the mode of operation, senses active transitions on
the input capture pins (T1IC/CR)
D
Interrupts that can be generated on the occurrence of:
-- A capture
-- A compare equal
-- A counter overflow
-- An external edge detection
D
Sixteen T1 module control registers located in the PF frame, beginning at address P040
The T1 module control registers are illustrated in Table 13.
20
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timer 1 module (continued)
Table 13. Timer 1 Module Registers Memory Map†
PF
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
REG
Modes: Dual-Compare and Capture/Compare
P040 Bit 15
P041 Bit 7
P042 Bit 15
P043 Bit 7
P044 Bit 15
P045 Bit 7
P046 Bit 15
P047 Bit 7
T1 Counter MSB
Bit 8
Bit 0
Bit 8
Bit 0
Bit 8
Bit 0
Bit 8
Bit 0
Bit 0
T1CNTR
T1C
T1 Counter LSB
Compare Register MSB
Compare Register LSB
Capture/Compare Register MSB
Capture/Compare Register LSB
Watchdog Counter MSB
Watchdog Counter LSB
Watchdog Reset Key
T1CC
WDCNTR
WDRST
T1CTL1
P048
Bit 7
WD OVRFL
TAP SEL
WD INPUT
SELECT2
WD INPUT
SELECT1
WD INPUT
SELECT0
T1INPUT
SELECT2
T1INPUT
SELECT1
T1INPUT
SELECT0
P049
—
†
†
†
†
WD OVRFL
RST ENA
WD OVRFL
INT ENA
WD OVRFL
INT FLAG
T1 OVRFL
INT ENA
T1 OVRFL
INT FLAG
T1 SW
RESET
P04A
—
—
T1CTL2
†
Mode: Dual-Compare
T1EDGE
INT FLAG
T1C2
INT FLAG
T1C1
INT FLAG
T1EDGE
INT ENA
T1C2
INT ENA
T1C1
INT ENA
P04B
P04C
—
—
T1CTL3
T1CTL4
T1
T1C1
OUT ENA
T1C2
OUT ENA
T1C1
RST ENA
T1CR
OUT ENA
T1EDGE
POLARITY
T1CR
RST ENA
T1EDGE
DET ENA
MODE = 0
Mode: Capture/Compare
T1EDGE
—
T1C1
INT FLAG
T1EDGE
INT ENA
T1C1
INT ENA
P04B
P04C
—
—
—
—
—
T1CTL3
T1CTL4
INT FLAG
T1
T1C1
T1C1
RST ENA
T1EDGE
POLARITY
T1EDGE
DET ENA
—
MODE = 1
OUT ENA
Modes: Dual-Compare and Capture/Compare
T1EVT
DATA IN
T1EVT
DATA OUT
T1EVT
FUNCTION
T1EVT
DATA DIR
P04D
P04E
P04F
—
—
—
—
T1PC1
T1PC2
T1PRI
T1PWM
DATA IN
T1PWM
DATA OUT
T1PWM
FUNCTION
T1PWM
DATA DIR
T1IC/CR
DATA IN
T1IC/CR
DATA OUT
T1IC/CR
FUNCTION
T1IC/CR
DATA DIR
T1
STEST
T1
—
—
—
—
—
—
PRIORITY
†
Once the WD OVRFL RST ENA bit is set, these bits cannot be changed until a reset; this applies only to the standard
watchdog and to simple counter. In the hard watchdog, these bits can be modified at any time; the WD INPUT SELECT2
bits are ignored.
21
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251--1443
TMS370Cx4x
8-BIT MICROCONTROLLER
SPNS016C -- NOVEMBER 1992 -- REVISED FEBRUARY 1997
timer 1 module (continued)
Figure 6 shows the T1 dual-compare mode block diagram. The annotations on the diagram identify the register
and the bits in the peripheral frame. For example, the actual address of T1CTL2.0 is 104Ah, bit 0, in the T1CTL2
register.
T1CC.15-0
16-Bit
Capt/Comp
Register
T1C2 INT FLAG
LSB
Prescaler
Clock
T1CTL3.6
MSB
Output
Enable
Source
T1CTL3.1
T1C2 INT ENA
T1CTL4.5
Compare=
T1CNTR.15-0
T1PC2.7-4
T1C2 OUT ENA
LSB
MSB
16-Bit
Counter
16
T1PWM
T1CTL4.6
T1C1 INT FLAG
T1CTL3.5
Reset
Compare=
T1C1 OUT ENA
T1CTL3.0
T1C1 INT ENA
T1C1
RST ENA
T1C.15-0
T1CTL4.3
T1 SW
RESET
16-Bit
Compare
Register
LSB
T1CTL4.4
T1CR OUT ENA
T1CTL2.0
MSB
T1 OVRFL INT FLAG
T1CTL2.3
T1CTL2.4
T1 OVRFL INT ENA
T1CTL4.1
T1CR
RST ENA
T1PC2.3-0
Edge
Select
T1 PRIORITY
T1IC/CR
T1CTL4.0
T1EDGE DET ENA
0
1
Level 1 Int
Level 2 Int
T1EDGE INT FLAG
T1CTL3.7
T1CTL3.2
T1EDGE INT ENA
T1PRI.6
T1CTL4.2
T1EDGE POLARITY
Figure 6. Timer 1: Dual-Compare Mode
22
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251--1443
TMS370Cx4x
8-BIT MICROCONTROLLER
SPNS016C -- NOVEMBER 1992 -- REVISED FEBRUARY 1997
timer 1 module (continued)
Figure 7 shows the T1 capture/compare mode block diagram. The annotations on the diagram identify the
register and the bits in the peripheral frame. For example, the actual address of T1CTL2.0 is 104Ah, bit 0, in
the T1CTL2 register.
T1CC.15-0
16-Bit
LSB
T1C1
OUT ENA
Capt/Comp
Register
Prescale
Clock
Source
MSB
T1PC2.7-4
T1CTL4.6
T1PWM
T1CNTR.15-0
LSB
MSB
16-Bit
Counter
16
T1 PRIORITY
0
1
T1C1 INT FLAG
T1PRI.6
Level 1 Int
Level 2 Int
Compare=
T1CTL3.5
Reset
T1CTL3.0
T1C.15-0
T1 SW
RESET
T1C1 INT ENA
16-Bit
LSB
T1C1
RST ENA
Compare
Register
T1CTL2.0
MSB
T1 OVRFL INT FLAG
T1CTL4.4
T1CTL2.3
T1CTL2.4
T1 OVRFL INT ENA
T1PC2.3-0
T1EDGE DET ENA
T1EDGE INT FLAG
T1IC/CR
Edge
Select
T1CTL3.7
T1CTL4.0
T1CTL3.2
T1EDGE INT ENA
T1CTL4.2
T1EDGE POLARITY
Figure 7. Timer 1: Capture/Compare Mode
23
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251--1443
TMS370Cx4x
8-BIT MICROCONTROLLER
SPNS016C -- NOVEMBER 1992 -- REVISED FEBRUARY 1997
timer 1 module (continued)
The TMS370Cx4x device includes a 24-bit WD timer, contained in the T1 module, which can be programmed
as an event counter, pulse accumulator, or interval timer if the WD function is not used. The WD function is to
monitor software and hardware operation and to implement a system reset when the WD counter is not properly
serviced (WD counter overflow or WD counter is re-initialized by an incorrect value). The WD can be configured
as one of three mask options as follows:
D
Standard WD configuration (see Figure 8) for ’C742A EPROM and mask-ROM devices:
-- Watchdog mode
-- Ten different WD overflow rates ranging from 6.55 ms to 3.35 s at 5-MHz SYSCLK
-- AWD resetkey (WDRST) register is usedtoclear thewatchdogcounter (WDCNTR) whenacorrect
value is written
-- Generates a system reset if an incorrect value is written to the WD reset key or if the counter
overflows
-- A WD overflow flag (WD OVRFL INT FLAG) bit that indicates whether the WD timer initiated a
system reset
-- Non-watchdog mode
-- Watchdog timer can be configured as an event counter, pulse accumulator, or an interval timer
WDCNTR.15-0
WD OVRFL
INT FLAG
T1CTL2.6
16-Bit
Watchdog Counter
T1CTL2.5
Interrupt
WD OVRFL
INT ENA
Reset
Clock
Prescaler
T1CTL1.7
T1CTL2.7
WD OVRFL
TAP SEL
System Reset
WD OVRFL
RST ENA
Watchdog Reset Key
WDRST.7-0
Figure 8. Standard Watchdog
24
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251--1443
TMS370Cx4x
8-BIT MICROCONTROLLER
SPNS016C -- NOVEMBER 1992 -- REVISED FEBRUARY 1997
timer 1 module (continued)
Hard watchdog configuration (see Figure 9) for mask-ROM devices only:
-- Eight different WD overflow rates ranging from 26.2 ms to 3.35 s at 5-MHz SYSCLK
D
-- A WD reset key (WDRST) register is used to clear the watchdog counter (WDCNTR) when a correct
value is written.
-- Generates a system reset if an incorrect value is written to the WDRST or if the counter overflows
-- A WD overflow flag (WD OVRFL INT FLAG) bit that indicates whether the WD timer initiated a system
reset
-- Automatic activation of the WD timer upon power-up reset
-- INT1 is enabled as a nonmaskable interrupt during low power modes.
WDCNTR.15-0
WD OVRFL
INT FLAG
16-Bit
Watchdog Counter
T1CTL2.5
Reset
Clock
Prescaler
T1CTL1.7
System Reset
WD OVRFL
TAP SEL
Watchdog Reset Key
WDRST.7-0
Figure 9. Hard Watchdog
25
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251--1443
TMS370Cx4x
8-BIT MICROCONTROLLER
SPNS016C -- NOVEMBER 1992 -- REVISED FEBRUARY 1997
timer 1 module (continued)
D
Simple counter configuration (see Figure 10) for mask-ROM devices only
-- Simple counter can be configured as an event counter, pulse accumulator, or an internal timer.
WDCNTR.15-0
WD OVFL
INT FLAG
16-Bit
Watchdog Counter
T1CTL2.6
Interrupt
T1CTL2.5
WD OVRFL
INT ENA
Reset
Clock
Prescaler
T1CTL1.7
WD OVRFL
TAP SEL
Watchdog Reset Key
WDRST.7-0
Figure 10. Simple Counter
26
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251--1443
TMS370Cx4x
8-BIT MICROCONTROLLER
SPNS016C -- NOVEMBER 1992 -- REVISED FEBRUARY 1997
timer 2A module
The 16-bit general-purpose timer 2A (T2A) module is composed of a 16-bit resettable counter, 16-bit compare
register with associated compare logic, 16-bit capture register, and a 16-bit register that functions as a capture
register in one mode and as a compare register in the other mode. The T2A module adds an additional timer
that provides an event count, input capture, and compare function. The T2A module includes three external
device pins that can be dedicated as timer functions or used as general-purpose I/O pins. The T2A module is
shown in Figure 11.
Edge
T2AIC1/CR
Detect
16--Bit
Edge
Detect
Capt/Comp
Register
T2AIC2/PWM
(Dual-Capture Mode)
PWM
Toggle
T2AIC2/PWM
16--Bit
Capture
Register
INT
Logic
(Dual-Compare Mode)
16
16--Bit
Compare
Register
Clock
Select
16--Bit
Counter
T2AEVT
Figure 11. Timer 2A Module Block Diagram
The T2A module features include the following:
D
Three T2A I/O pins:
-- T2AIC1/CR: T2A input-capture 1/counter-reset input pin, or general-purpose bidirectional I/O pin
-- T2AIC2/PWM: T2A input-capture 2/pulse-width-modulation (PWM) output pin, or general-purpose
bidirectional I/O pin
-- T2AEVT: Timer 2A event-input pin, or general-purpose bidirectional I/O pin
Two operational modes:
D
-- Dual-compare mode: Provides PWM signal
-- Dual-capture mode: Provides input-capture pin
One 16-bit general-purpose resettable counter
D
D
D
D
One 16-bit compare register with associated compare logic
One 16-bit capture register with associated capture logic
One 16-bit capture/compare register, which, depending on the mode of operation, operates as either a
capture or compare register
27
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251--1443
TMS370Cx4x
8-BIT MICROCONTROLLER
SPNS016C -- NOVEMBER 1992 -- REVISED FEBRUARY 1997
timer 2A module (continued)
D
T2A clock sources can be any of the following:
-- System clock
-- No clock (the counter is stopped)
-- External clock synchronized to the system clock (event counter)
-- System clock while external input is high (pulse accumulation)
D
D
Selectable edge-detection circuitry that, depending on the mode of operation, senses active transitions on
the input capture pins (T2AIC1/CR)
Interrupts that can be generated on the occurrence of:
-- A compare equal to dedicated-compare register
-- A compare equal to capture-compare register
-- A counter overflow
-- An external edge 1 detection
-- An external edge 2 detection
D
Fourteen T2A module-control registers: Located in the PF frame beginning at address P060
28
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251--1443
TMS370Cx4x
8-BIT MICROCONTROLLER
SPNS016C -- NOVEMBER 1992 -- REVISED FEBRUARY 1997
timer 2A module (continued)
The T2A module-control registers are shown in Table 14.
Table 14. T2A Module Register Memory Map†
PF
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
REG
Modes: Dual-Compare and Dual-Capture
P060 Bit 15
P061 Bit 7
P062 Bit 15
P063 Bit 7
P064 Bit 15
P065 Bit 7
P066 Bit 15
P067 Bit 7
T2A Counter MSB
T2A Counter LSB
Bit 8
T2ACNTR
T2AC
Bit 0
Bit 8
Bit 0
Bit 8
Bit 0
Bit 8
Bit 0
Compare Register MSB
Compare Register LSB
Capture/Compare Register MSB
Capture/Compare Register LSB
Capture Register 2 MSB
Capture Register 2 LSB
T2ACC
T2AIC
P068
P069
Reserved
T2A OVRFL
INT ENA
T2A OVRFL T2A INPUT T2A INPUT
T2A
SW RESET
P06A
—
—
—
T2ACTL1
INT FLAG
SELECT1
SELECT0
Mode: Dual-Compare
T2AEDGE1
INT FLAG
T2AC2
INT FLAG
T2AC1
INT FLAG
T2AEDGE1
INT ENA
T2AC2
INT ENA
T2AC1
INT ENA
P06B
P06C
—
—
T2ACTL2
T2ACTL3
T2A
MODE = 0
T2AC1
OUT ENA
T2AC1
OUT ENA
T2AC1
RST ENA
T2AEDGE1 T2AEDGE1 T2AEDGE1 T2AEDGE1
OUT ENA
POLARITY
RST ENA
DET ENA
Mode: Dual-Capture
T2AEDGE1
INT FLAG
T2AEDGE2
INT FLAG
T2AC1
INT FLAG
T2AEDGE1 T2AEDGE2
INT ENA INT ENA
T2AC1
INT ENA
P06B
P06C
—
—
T2ACTL2
T2ACTL3
T2A
MODE = 1
T2AC1
RST ENA
T2AEDGE2 T2AEDGE1 T2AEDGE2 T2AEDGE1
—
—
POLARITY
POLARITY
DET ENA
DET ENA
Modes: Dual-Compare and Dual-Capture
T2AEVT
DATA IN
T2AEVT
DATA OUT FUNCTION
T2AEVT
T2AEVT
DATA DIR
P06D
P06E
P06F
—
—
—
—
T2APC1
T2APC2
T2APRI
T2AIC2/PWM T2AIC2/PWM T2AIC2/PWM T2AIC2/PWM
DATA IN
T2AIC1/CR T2AIC1/CR T2AIC1/CR T2AIC1/CR
DATA IN
DATA OUT
FUNCTION
DATA DIR
DATA OUT FUNCTION
DATA DIR
T2A
STEST
T2A
PRIORITY
—
—
—
—
—
—
†
Privileged bits are shown in bold typeface.
29
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251--1443
TMS370Cx4x
8-BIT MICROCONTROLLER
SPNS016C -- NOVEMBER 1992 -- REVISED FEBRUARY 1997
timer 2A module (continued)
The T2A dual-compare mode block diagram is illustrated in Figure 12. The annotations on the diagram identify
the register and the bit(s) in the peripheral frame. For example, the actual address of T2ACTL2.0 is 106Bh,
bit 0, in the T2ACTL2 register.
T2ACC.15-0
16-Bit
Capt/Comp
LSB
Register
MSB
Output
Enable
Clock
Source
T2AC2 INT FLAG
T2ACTL2.6
T2ACTL2.1
T2AC2 INT ENA
T2ACTL3.5
Compare=
16
T2ACNTR.15-0
T2APC2.7-4
T2AC2 OUT ENA
LSB
MSB
16-Bit
Counter
T2ACTL3.6
T2AIC2/PWM
T2AC1 INT FLAG
T2ACTL2.5
T2ACTL2.0
T2AC1 INT ENA
Reset
Compare=
T2AC.15-0
T2AC1 OUT ENA
T2ACTL3.3
T2A SW
RESET
T2AC1
RST ENA
T2ACTL3.4
16-Bit
Compare
Register
LSB
T2ACTL1.0
T2AEDGE1
OUT ENA
MSB
T2A OVRFL INT FLAG
T2ACTL1.3
T2ACTL3.1
T2AEDGE1
RST ENA
T2ACTL1.4
T2APC2.3-0
T2A OVRFL INT ENA
Edge 1
Select
T2AIC1/CR
T2A PRIORITY
T2ACTL3.0
T2APRI.6
0
1
T2AEDGE1 INT FLAG
Level 1 Int
Level 2 Int
T2AEDGE1 DET ENA
T2ACTL2.7
T2ACTL3.2
T2ACTL2.2
T2AEDGE1 POLARITY
T2AEDGE1 INT ENA
Figure 12. Timer 2A: Dual-Compare Mode
30
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251--1443
TMS370Cx4x
8-BIT MICROCONTROLLER
SPNS016C -- NOVEMBER 1992 -- REVISED FEBRUARY 1997
timer 2A module (continued)
The T2A dual-capture mode block diagram is illustrated in Figure 13. The annotations on the diagram identify
the register and the bit(s) in the peripheral frame. For example, the actual address of T2ACTL2.0 is 106Bh,
bit 0, in the T2ACTL2 register.
T2AIC.15-0
T2ACC.15-0
16-Bit
Capture
Register 2
16-Bit
LSB
MSB
LSB
MSB
Capt/Comp
Register 1
Clock
Source
T2ACNTR.15-0
LSB
16-Bit
Counter
16
MSB
T2A PRIORITY
0
1
T2AC1 INT FLAG
T2ACTL2.5
T2APRI.6
Level 1 Int
Level 2 Int
Compare =
Reset
T2ACTL2.0
T2AC1 INT ENA
T2AC.15-0
T2A SW
T2A OVRFL INT FLAG
16-Bit
Compare
Register
LSB
MSB
RESET
T2AC1
RST ENA
T2ACTL1.3
T2ACTL1.0
T2ACTL1.4
T2A OVRFL INT ENA
T2ACTL3.4
T2ACTL3.0
T2AEDGE1 DET ENA
T2AEDGE1 INT FLAG
T2ACTL2.7
T2APC2.3-0
Edge1
Select
T2ACTL2.2
T2AEDGE1 INT ENA
T2AIC1/CR
T2ACTL3.2
T2AEDGE1 POLARITY
T2ACTL3.1
T2AEDGE2 INT FLAG
T2APC2.7-4
T2ACTL2.6
Edge 2
Select
T2AIC2/PWM
T2AEDGE2 DET ENA
T2ACTL3.3
T2ACTL2.1
T2AEDGE2 POLARITY
T2AEDGE2 INT ENA
Figure 13. Timer 2A: Dual-Capture Mode
31
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251--1443
TMS370Cx4x
8-BIT MICROCONTROLLER
SPNS016C -- NOVEMBER 1992 -- REVISED FEBRUARY 1997
serial communications interface 1 (SCI1)
The TMS370Cx4x devices include a serial communications interface 1 (SCI1) module. The SCI1 module
supports digital communications between the TMS370 devices and other asynchronous peripherals and uses
the standard non return-to-zero format (NRZ) format. The SCI1’s receiver and transmitter are double buffered,
and each has its own separate enable and interrupt bits. Both can be operated independently or simultaneously
in the full duplex mode. To ensure data integrity, the SCI1 checks received data for break detection, parity,
overrun, and framing errors. The bit rate (baud) is programmable to over 65,000 different rates through a 16-bit
baud-select register.
Features of the SCI1 module include:
D
Three external pins:
-- SCITXD: SCI transmit-output pin or general purpose bidirectional I/O pin.
-- SCIRXD: SCI receive-input pin or general purpose bidirectional I/O pin.
-- SCICLK: SCI bidirectional serial-clock pin, or general-purpose bidirectional I/O pin.
Two communications modes: asynchronous and isosynchronous
Baud rate: 64K different programmable rates
D
D
-- Asynchronous mode: 3 bps to 156K bps at 5 MHz SYSCLK
SYSCLK
(BAUD REG + 1) × 32
Asynchronous Baud =
-- Isosynchronous mode: 39 bps to 2.5 Mbps at 5 MHz SYSCLK
SYSCLK
(BAUD REG + 1) × 2
Isosynchronous Baud =
D
Data word format:
-- O n e s t a r t b i t
-- Data word length programmable from one to eight bits
-- Optional even/odd/no parity bit
-- One or two stop bits
D
D
D
D
D
Four error-detection flags: parity, overrun, framing, and break detection
Two wake-up multiprocessor modes: Idle-line and address bit
Half or full-duplex operation
Double-buffered receiver and transmitter operations
Transmitter and receiver operations can be accomplished through either interrupt-driven or
polled-algorithms with status flags:
-- Transmitter: TXRDY flag (transmitter buffer register is ready to receive another character) and TX
EMPTY flag (Transmitter shift register is empty)
-- Receiver: RXRDY flag (receive buffer register ready to receive another character), BRKDT flag (break
condition occurred), and RX ERROR monitoring four interrupt conditions
-- Separate enable bits for transmitter and receiver interrupts
-- NRZ (non return-to-zero) format
D
Eleven SCI1 module control registers, located in control register frame beginning at address P050h
32
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251--1443
TMS370Cx4x
8-BIT MICROCONTROLLER
SPNS016C -- NOVEMBER 1992 -- REVISED FEBRUARY 1997
serial communications interface 1 (SCI1) (continued)
Table 15 lists the SCI1 module control registers.
Table 15. SCI1 Module Control Register Memory Map
PF
P050 STOP BITS
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
REG
EVEN/ODD
PARITY
PARITY
ENABLE
ASYNC/
ISOSYNC
ADDRESS/
IDLE WUP
SCI CHAR2 SCI CHAR1 SCI CHAR0 SCICCR
SCI SW
RESET
P051
P052
P053
P054
P055
—
—
CLOCK
BAUDC
BAUD4
—
TXWAKE
BAUDB
BAUD3
—
SLEEP
BAUDA
BAUD2
—
TXENA
BAUD9
BAUD1
—
RXENA
BAUD8
SCICTL
BAUDF
(MSB)
BAUDE
BAUD6
TX EMPTY
RXRDY
BAUDD
BAUD5
—
BAUD MSB
BAUD LSB
TXCTL
BAUD0
(LSB)
BAUD7
TXRDY
SCI TX
INT ENA
RX
ERROR
SCI RX
INT ENA
BRKDT
FE
OE
PE
RXWAKE
RXCTL
P056
P057
P058
Reserved
RXDT7
TXDT7
RXDT6
TXDT6
RXDT5
TXDT5
RXDT4
RXDT3
RXDT2
TXDT2
RXDT1
TXDT1
RXDT0
TXDT0
RXBUF
TXBUF
RESERVED
P059
P05A
P05B
P05C
TXDT4
TXDT3
Reserved
SCICLK
DATA IN
SCICLK
SCICLK
SCICLK
DATA DIR
P05D
P05E
—
—
—
—
SCIPC1
SCIPC2
SCIPRI
DATA OUT FUNCTION
SCIRXD SCIRXD
DATA OUT FUNCTION
SCITXD
DATA IN
SCITXD
DATA OUT
SCITXD
FUNCTION
SCITXD
DATA DIR
SCIRXD
DATA IN
SCIRXD
DATA DIR
SCITX
PRIORITY
SCIRX
PRIORITY
SCI
ESPEN
P05F SCI STEST
—
—
—
—
33
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251--1443
TMS370Cx4x
8-BIT MICROCONTROLLER
SPNS016C -- NOVEMBER 1992 -- REVISED FEBRUARY 1997
serial communications interface 1 (SCI1) (continued)
Figure 14 shows the SCI1 module block diagram.
TXBUF.7-0
TXWAKE
SCICTL.3
Frame Format and Mode
SCI TX Interrupt
SCITX PRIORITY
Transmit Data
Buffer Reg.
PARITY
EVEN/ODD ENABLE
1
0
1
SCIPRI.6
SCI TX INT ENA
TXRDY
TXCTL.7
Level 1 INT
Level 2 INT
SCICCR.6 SCICCR.5
WUT
TXCTL.0
8
TX EMPTY
TXCTL.6
SCIPC2.7-4
TXENA
SCITXD
TXSHF Reg.
BAUD MSB. 7-0
SCITXD
SCICTL.1
Baud Rate
MSbyte Reg.
CLOCK
SCIPC1.3-0
SYSCLK
SCICLK
SCICTL.4
BAUD LSB. 7-0
Baud Rate
LSbyte Reg.
SCIPC2.3-0
SCIRXD
RXSHF Reg.
SCIRXD
RXWAKE
RXCTL.1
SCIRX PRIORITY
SCI RX Interrupt
RXENA
0
1
SCIPRI.5
SCI RX INT ENA
RXCTL.0
RXRDY
RXCTL.6
Level 1 INT
Level 2 INT
RX ERROR
SCICTL.0
8
RXCTL.4-2
FE OE PE
RXCTL.7
ERR
BRKDT
Receive Data
Buffer Reg.
RXCTL.5
RXBUF.7-0
Figure 14. SCI1 Block Diagram
34
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251--1443
TMS370Cx4x
8-BIT MICROCONTROLLER
SPNS016C -- NOVEMBER 1992 -- REVISED FEBRUARY 1997
analog-to-digital converter 1 (ADC1) module
The analog-to-digital converter 1 (ADC1) module is an 8-bit, successive approximation converter with internal
sample-and-hold circuitry. The module has eight multiplexed analog input channels for the 44-pin device and
four multiplexed analog input channels for the 40-pin device that allow the processor to convert the voltage
levels from up to eight different sources. The ADC1 module features include the following:
D
D
Minimum conversion time: 32.8 s at 5-MHz SYSCLK
Up to ten external pins:
-- Four (AN2, AN3, AN6, AN7) or eight (AN0-AN7) analog input channels, any of which can be software
configured as digital inputs (E2, E3, E6, E7) or (E0--E7), respectively, if not needed as analog channels
-- AN1--AN7 can also be configured as positive-input voltage reference.
--
--
V
V
CC3: ADC1 module high-voltage reference input
SS3: ADC1 module low-voltage reference input
D
D
D
The ADDATA register, which contains the digital result of the last A/D conversion
A/D operations can be accomplished through either interrupt driven or polled algorithms.
Six ADC1 module control registers are located in the control-register frame beginning at address 1070h.
The ADC1 module control registers are illustrated in Table 16.
Table 16. ADC1 Module Control Register Memory Map†
PF
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
REG
CONVERT
START
SAMPLE
START
REF VOLT
SELECT2
REF VOLT
SELECT1
REF VOLT
SELECT0
AD INPUT
SELECT2
AD INPUT
SELECT1
AD INPUT
SELECT0
P070
ADCTL
AD INT
FLAG
AD INT
ENA
P071
P072
—
—
—
—
—
AD READY
ADSTAT
ADDATA
A-to-D Conversion Data Register
Reserved
P073
to
P07C
P07D
P07E
Port E Data Input Register
Port E Input Enable Register
ADIN
ADENA
AD
PRIORITY
P07F AD STEST
AD ESPEN
—
—
—
—
—
ADPRI
†
Privileged bits are shown in bold typeface.
35
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251--1443
TMS370Cx4x
8-BIT MICROCONTROLLER
SPNS016C -- NOVEMBER 1992 -- REVISED FEBRUARY 1997
analog-to-digital converter 1 (ADC1) module (continued)
The ADC1 module block diagram is illustrated in Figure 15.
Port E Input
Port E Data
ENA 0
AN 0
ADENA.0
SAMPLE
START
CONVERT
START
ADIN.0
2
1
0
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
ADCTL.2-0
ADCTL.6
ADCTL.7
Port E Input
ENA 1
Port E Data
AN 1
AD INPUT SELECT
ADENA.1
ADIN.1
Port E Input
ENA 2
Port E Data
AN 2
ADENA.2
ADIN.2
Port E Input
ENA 3
Port E Data
AN 3
ADENA.3
ADIN.3
A/D
Port E Input
ENA 4
Port E Data
AN 4
ADENA.4
ADIN.4
ADDATA.7-0
Port E Input
ENA 5
Port E Data
AN 5
A-to-D
Conversion
ADENA.5
ADIN.5
Data Register
Port E Input
ENA 6
AD READY
ADSTAT.2
Port E Data
AN 6
ADENA.6
ADIN.6
5
4
3
AD PRIORITY
ADCTL.5-3
Port E Input
ENA 7
Port E Data
AN 7
0
1
Level 1 INT
Level 2 INT
ADPRI.6
REF VOLTS SELECT
ADENA.7
ADIN.7
V
CC3
AD INT FLAG
ADSTAT.1
V
SS3
ADSTAT.0
AD INT ENA
Figure 15. ADC1 Converter Block Diagram
36
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251--1443
TMS370Cx4x
8-BIT MICROCONTROLLER
SPNS016C -- NOVEMBER 1992 -- REVISED FEBRUARY 1997
instruction set overview
Table 17 provides an opcode-to-instruction cross-reference of all 73 instructions and 274 opcodes of the
‘370Cx4x instruction set. The numbers at the top of this table represent the most significant nibble (MSN) of the
opcode while the numbers at the left side of the table represent the least significant nibble (LSN). The
instructions for these two opcode nibbles contain the mnemonic, operands, and byte/cycle particular to that
opcode.
For example, the opcode B5h points to the CLR A instruction. This instruction contains one byte and executes
in eight SYSCLK cycles.
37
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251--1443
Template Release Date: 7--11--94
TMS370Cx4x
8-BIT MICROCONTROLLER
SPNS016C -- NOVEMBER 1992 -- REVISED FEBRUARY 1997
38
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251--1443
TMS370Cx4x
8-BIT MICROCONTROLLER
SPNS016C -- NOVEMBER 1992 -- REVISED FEBRUARY 1997
POST OFFICE BOX 1443
39
HOUSTON, TEXAS 77251--1443
TMS370Cx4x
8-BIT MICROCONTROLLER
SPNS016C -- NOVEMBER 1992 -- REVISED FEBRUARY 1997
development system support
The TMS370 family development support tools include an assembler, a C compiler, a linker, an in-circuit
emulator (XDS/22), compact development tool (CDT) and an EEPROM/UVEPROM programmer.
D
Assembler/linker (Part No. TMDS3740850-02 for PC)
— Includes extensive macro capability
— Provides high-speed operation
— Offers format conversion utilities available for popular formats
D
ANSI C compiler (Part No. TMDS3740855-02 for PC, Part No. TMDS3740555-09 for HP700, Sun-3
or Sun-4)
— Generates assembly code of the TMS370 that can be inspected easily
— Improves code execution speed and reduces code size with optional optimizer pass
— Enables the user to directly reference the TMS370’s port registers by using a naming convention
— Provides flexibility in specifying the storage for data objects
— Interfaces C functions and assembly functions easily
— Includes assembler and linker
D
CDT370 (compact development tool) real-time in-circuit emulation
-- Base (Part Number EDSCDT370 -- for PC, requires cable)
-- Cable for 44-pin PLCC (Part No. EDSTRG44PLCC)
-- Cable for 40-pin DIP (Part No. EDSTRG40DIL)
-- Cable for 40-pin SDIP (Part No. EDSTRG40SDIL)
-- Provides EEPROM and EPROM programming support
-- Allows inspection and modification of memory locations
-- Allows uploading anddownloading of program and data memory
-- Provides capability to execute programs and software routines
-- Includes 1024-sample trace buffer
-- Includes single-step executable instructions
-- Allows uses of software breakpoints to halt program execution at selected address
XDS/22 (extended development support) in-circuit emulator
— Base (Part No. TMDS3762210 For PC, requires cable)
-- Cable for 44-pin PLCC, 40-pin DIP, or shrink DIP (Part No. TMDS3788844)
D
— Contains all the features of the CDT370 described above but does not have the capability to program
the data EEPROM and program EPROM
— Contains sophisticated breakpoint trace and timing hardware that provides up to 2047 qualified trace
samples with symbolic disassembly
— Allows breakpoints to be qualified by address and/or data on any type of memory acquisition. Up to four
levels of events can be combined to cause a breakpoint.
HP700 is a trademark of Hewlett-Packard Company.
Sun-3 and Sun-4 are trademarks of Sun Microsystems, Inc.
40
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251--1443
TMS370Cx4x
8-BIT MICROCONTROLLER
SPNS016C -- NOVEMBER 1992 -- REVISED FEBRUARY 1997
development system support (continued)
— Provides timers for analyzing total and average time in routines
— Contains an eight-line logic probe for adding external signal visibility to the breakpoint qualifier and
to the trace display
D
D
Microcontroller programmer
— Base (Part No. TMDS3760500A -- For PC, requires programming head)
-- Single unit head for 44-pin PLCC (Part No. TMDS3780510A)
-- Single unit head for 40-pin DIP or shrink DIP (Part No. TMDS3780511A)
— PC-based, window/function-key oriented user interface for ease of use and a rapid learning
environment
Starter kit (Part No. TMDS37000 -- For PC)
-- Includes TMS370 Assembler diskette and documentation
-- Includes TMS370 Simulator
-- Includes programming adapter board and programming software
-- Does not include -- (to be supplied by the user):
-- + 5 V power supply
ZIF sockets
9-pin RS-232 cable
41
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251--1443
TMS370Cx4x
8-BIT MICROCONTROLLER
SPNS016C -- NOVEMBER 1992 -- REVISED FEBRUARY 1997
device numbering conventions
Figure 16 illustrates the numbering and symbol nomenclature for the TMS370Cx4x family.
TMS 370 C
3
4 0 A FN L
Prefix: TMS
SE
=
=
Standard prefix for fully qualified devices
System evaluator (window EPROM) that is used for
prototyping purpose.
Family: 370
=
=
TMS370 8-Bit Microcontroller Family
CMOS
Technology:
C
Program Memory Types:
0
3
7
=
=
=
Mask ROM
Mask ROM, No Data EEPROM
EPROM
Device Type:
4
=
x4x devices containing the following modules:
-- T i m e r 1
-- T i m e r 2 A
-- Serial Communications Interface 1
-- Analog-to-Digital Converter 1
Memory Size:
0
2
=
=
4K bytes
8K bytes
Temperature Ranges:
A
L
T
=
=
=
--40C to
0C to
--40C to 105C
85C
70C
Packages:
FN
FZ
JC
JD
N
=
=
=
=
=
=
Plastic Leaded Chip Carrier
Ceramic Leaded Chip Carrier
Ceramic Shrink Dual-In-Line
Ceramic Dual-In-Line
Plastic Dual-In-Line
Plastic Shrink Dual-In-Line
NJ
ROM and EPROM Option:
A
=
For ROM device, the watchdog timer can be configured
as one of the three different mask options:
-- A standard watchdog
-- A hard watchdog
-- A simple watchdog
The clock can be either:
-- Divide-by-4 clock
-- Divide-by-1 (PLL) clock
The low-power modes can be either:
-- E n a b l e d
-- Disabled
A
=
For EPROM device, a standard watchdog, a divide-by-4
clock, and low-power modes are enabled
Figure 16. TMS370Cx4x Family Nomenclature
42
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251--1443
TMS370Cx4x
8-BIT MICROCONTROLLER
SPNS016C -- NOVEMBER 1992 -- REVISED FEBRUARY 1997
device part numbers
Table 18 lists all the ‘x4x devices available at present. The device part-number nomenclature is designed to
assist ordering. Upon ordering, the customer must specify not only the device part number, but also the clock
and watchdog timer options desired. Each device can have only one of the possible three watchdog timer
options and one of the two clock options. The options to be specified pertain solely to orders involving ROM
devices.
Table 18. Device Part Numbers
DEVICE PART NUMBERS
FOR 44 PINS (LCC)
DEVICE PART NUMBERS
FOR 40 PINS (DIP)
DEVICE PART NUMBERS
FOR 40 PINS (SDIP)
†
TMS370C040AFNA
TMS370C040AFNL
TMS370C040AFNT
TMS370C040ANA
TMS370C040ANL
TMS370C040ANT
TMS370C040ANJA
TMS370C040ANJL
TMS370C040ANJT
†
†
†
TMS370C042AFNA
TMS370C042AFNL
TMS370C042AFNT
TMS370C042ANA
TMS370C042ANL
TMS370C042ANT
TMS370C042ANJA
TMS370C042ANJL
TMS370C042ANJT
†
†
†
TMS370C340AFNA
TMS370C340AFNL
TMS370C340AFNT
TMS370C340ANA
TMS370C340ANL
TMS370C340ANT
TMS370C340ANJA
TMS370C340ANJL
TMS370C340ANJT
†
†
†
TMS370C342AFNA
TMS370C342AFNL
TMS370C342AFNT
TMS370C342ANA
TMS370C342ANL
TMS370C342ANT
TMS370C342ANJA
TMS370C342ANJL
TMS370C342ANJT
†
†
†
TMS370C742AFNT
TMS370C742ANT
TMS370C742ANJT
‡
‡
‡
SE370C742AFZT
SE370C742AJDT
SE370C742AJCT
†
‡
The NJ designator for the 40-pin plastic shrink DIP package was known formerly as the N2. The mechanical drawing of the NJ is identical to the
N2 package and did not need to be requalified.
System evaluators and development tools are for use only in a prototype environment, and their reliability has not been characterized.
43
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251--1443
TMS370Cx4x
8-BIT MICROCONTROLLER
SPNS016C -- NOVEMBER 1992 -- REVISED FEBRUARY 1997
new code release form
Figure 17 shows a sample of the new code release form.
NEW CODE RELEASE FORM
TEXAS INSTRUMENTS
TMS370 MICROCONTROLLER PRODUCTS
DATE:
To release a new customer algorithm to TI incorporated into a TMS370 family microcontroller, complete this form and submit with the following information:
1. A ROM description in object form on Floppy Disk, Modem XFR, or EPROM (Verification file will be returned via same media)
2. An attached specification if not using TI standard specification as incorporated in TI’s applicable device data book.
Company Name:
Street Address:
Street Address:
City:
Contact Mr./Ms.:
Phone: (
)
Ext.:
State
Zip
Customer Purchase Order Number:
Customer Print Number *Yes:
No:
*If Yes: Customer must provide ”print” to TI w/NCRF for approval before ROM
code processing starts.
#
Customer Part Number:
Customer Application:
(Std. spec to be followed)
TMS370 Device:
TI Customer ROM Number:
(provided by Texas Instruments)
CONTACT OPTIONS FOR THE ’A’ VERSION TMS370 MICROCONTROLLERS
OSCILLATOR FREQUENCY
Low Power Modes
[] Enabled
[] Disabled
Watchdog counter
[] Standard
[] Hard Enabled
[] Simple Counter
Clock Type
[] Standard (/4)
[] PLL (/1)
MIN
TYP
MAX
[] External Drive (CLKIN)
[] Crystal
[] Ceramic Resonator
NOTE:
Non ’A’ version ROM devices of the TMS370 microcontrollers will have the
“Low-powermodesEnabled”, “Divide-by-4”Clock, and“Standard”Watchdog
options. See the TMS370 Family User’s Guide (literature number SPNU127)
or the TMS370 Family Data Manual (literature number SPNS014B).
[] Supply Voltage MIN:
(std range: 4.5V to 5.5V)
MAX:
TEMPERATURE RANGE
PACKAGE TYPE
[] ’L’:
[] ’A’:
[] ’T’:
0 to 70C (standard)
--40 to 85C
--40 to 105C
[] ’N’ 28-pin PDIP
[] “FN” 28-pin PLCC
[] “N” 40-pin PDIP
[] “FN” 44-pin PLCC
[] “FN” 68-pin PLCC
[] “NM” 64-pin PSDIP
[] “NJ” 40-pin PSDIP (formerly known as N2)
SYMBOLIZATION
BUS EXPANSION
[] TI standard symbolization
[] YES
[] NO
[] TI standard w/customer part number
[] Customer symbolization
(per attached spec, subject to approval)
NON-STANDARD SPECIFICATIONS:
ALL NON-STANDARDS SPECIFICATIONS MUST BE APPROVED BY THE TI ENGINEERING STAFF: If the customer requires expedited production material
(i.e., product which must be started in process prior to prototype approval and full production release) and non-standard spec issues are not resolved to the
satisfaction of both the customer and TI in time for a scheduled shipment, the specification parameters in question will be processed/tested to the standard
TI spec. Any such devices which are shipped without conformance to a mutually approved spec, will be identified by a ’P’ in the symbolization preceding the
TI part number.
RELEASE AUTHORIZATION:
This document, including any referenced attachments, is and will be the controlling document for all orders placed for this TI custom device. Any changes must
be in writing and mutually agreed to by both the customer and TI. The prototype cycletime commences when this document is signed off and the verification
code is approved by the customer.
1. Customer:
Date:
2. TI: Field Sales:
Marketing:
Prod. Eng.:
Proto. Release:
Figure 17. Sample New Code Release Form
44
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251--1443
TMS370Cx4x
8-BIT MICROCONTROLLER
SPNS016C -- NOVEMBER 1992 -- REVISED FEBRUARY 1997
Table 19 is a collection of all the peripheral file frames using the ’Cx4x (provided for a quick reference).
Table 19. Peripheral File Frame Compilation
PF
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
REG
SYSTEM CONFIGURATION REGISTERS
COLD
START
OSC
POWER
PF AUTO
WAIT
OSC FLT
FLAG
MC PIN
WPO
MC PIN
DATA
P/C
MODE
P010
P011
P012
—
—
SCCR0
SCCR1
SCCR2
AUTOWAIT
DISABLE
MEMORY
DISABLE
—
—
—
—
—
HALT/
STANDBY
PWRDWN/
IDLE
BUS
STEST
CPU
STEST
INT1
NMI
PRIVILEGE
DISABLE
—
P013
to
Reserved
P016
INT1
FLAG
INT1
PIN DATA
INT1
POLARITY
INT1
PRIORITY
INT1
ENABLE
P017
P018
P019
—
—
—
—
INT1
INT2
INT2
FLAG
INT2
PIN DATA
INT2
DATA DIR
INT2
DATA OUT
INT2
POLARITY
INT2
PRIORITY
INT2
ENABLE
INT3
FLAG
INT3
PIN DATA
INT3
DATA DIR
INT3
DATA OUT
INT3
POLARITY
INT3
PRIORITY
INT3
ENABLE
—
—
INT3
P01A
P01B
P01C
BUSY
BUSY
—
—
—
—
AP
—
W1W0
W0
EXE
EXE
DEECTL
Reserved
VPPS
—
—
EPCTL
P01D
to
Reserved
P01F
DIGITAL PORT CONTROL REGISTERS
Reserved
P020
P021
P022
P023
P024
P025
P026
P027
APORT1
APORT2
ADATA
ADIR
Port A Control Register 2 (must be 0)
Port A Data
Port A Direction
Reserved
BPORT1
BPORT2
BDATA
BDIR
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Port B Control Register 2 (must be 0)
Port B Data
Port B Direction
P028
to
Reserved
P02B
P02C
P02D
P02E
P02F
Port D Control Register 1 (must be 0)
Port D Control Register 2 (must be 0)
Port D Data
—
—
—
—
—
—
—
—
—
—
—
—
DPORT1
DPORT2
DDATA
DDIR
†
Port D Direction
TIMER 1 MODULE REGISTER
Modes: Dual-Compare and Capture/Compare
P040 Bit 15
P041 Bit 7
P042 Bit 15
P043 Bit 7
T1 Counter MSbyte
T1 Counter LSbyte
Bit 8 T1CNTR
Bit 0
Compare-Register MSbyte
Compare-Register LSbyte
Bit 8 T1C
Bit 0
†
To configure pin D3 as CLKOUT, set port D control register 2 = 08h.
45
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251--1443
TMS370Cx4x
8-BIT MICROCONTROLLER
SPNS016C -- NOVEMBER 1992 -- REVISED FEBRUARY 1997
Table 19. Peripheral File Frame Compilation (Continued)
PF
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
REG
TIMER 1 MODULE REGISTER (CONTINUED)
Capture/Compare-Register MSbyte
Capture/Compare-Register LSbyte
Watchdog-Counter MSbyte
P044 Bit 15
P045 Bit 7
P046 Bit 15
P047 Bit 7
P048 Bit 7
Bit 8 T1CC
Bit 0
Bit 8 WDCNTR
Bit 0
Watchdog-Counter LSbyte
Watchdog-Reset Key
Bit 0 WDRST
WD
INPUT
SELECT2
WD
INPUT
SELECT1
WD
INPUT
SELECT0
T1
INPUT
SELECT2
T1
INPUT
SELECT1
WD OVRFL
TAP SEL
T1 INPUT
SELECT0
P049
P04A
—
T1CTL1
T1CTL2
†
†
†
†
WD OVRFL
WD OVRFL
INT ENA
WD OVRFL
INT FLAG
T1 OVRFL
INT ENA
T1 OVRFL
INT FLAG
T1 SW
RESET
—
—
†
RST ENA
Mode: Dual-Compare
T1EDGE
INT FLAG
T1C2
INT FLAG
T1C1
INT FLAG
T1EDGE
INT ENA
T1C2
INT ENA
T1C1
INT ENA
P04B
P04C
—
—
T1CTL3
T1CTL4
T1
T1C1
OUT ENA
T1C2
OUT ENA
T1C1
RST ENA
T1CR
OUT ENA
T1EDGE
POLARITY
T1CR
RST ENA
T1EDGE
DET ENA
MODE = 0
Mode: Capture/Compare
T1EDGE
—
T1C1
INT FLAG
T1EDGE
INT ENA
T1C1
INT ENA
P04B
P04C
—
—
—
—
—
T1CTL3
T1CTL4
INT FLAG
T1
T1C1
T1C1
RST ENA
T1EDGE
POLARITY
T1EDGE
DET ENA
—
MODE = 1
OUT ENA
Modes: Dual-Compare and Capture/Compare
T1EVT
DATA IN
T1EVT
DATA OUT
T1EVT
FUNCTION
T1EVT DATA
DIR
P04D
P04E
P04F
—
—
—
—
T1PC1
T1PC2
T1PRI
T1PWM
DATA IN
T1PWM
DATA OUT
T1PWM
FUNCTION
T1PWM
DATA DIR
T1IC/CR
DATA IN
T1IC/CR
DATA OUT
T1IC/CR
FUNCTION
T1IC/CR DATA
DIR
T1
T1 STEST
—
—
—
—
—
—
PRIORITY
SCI1 MODULE CONTROL REGISTER
EVEN/ODD
PARITY
PARITY
ENABLE
ASYNC/
ISOSYNC
ADDRESS/
IDLE WUP
P050 STOP BITS
SCI CHAR2
SLEEP
BAUDA
BAUD2
—
SCI CHAR1
TXENA
BAUD9
BAUD1
—
SCI CHAR0
RXENA
SCICCR
SCICTL
SCI SW RE-
SET
P051
P052
P053
P054
P055
—
—
CLOCK
BAUDC
BAUD4
—
TXWAKE
BAUDB
BAUD3
—
BAUDF
(MSB)
BAUD
MSB
BAUDE
BAUD6
TX EMPTY
RXRDY
BAUDD
BAUD5
—
BAUD8
BAUD0
(LSB)
BAUD
LSB
BAUD7
TXRDY
SCI TX
INT ENA
TXCTL
RXCTL
RX
ERROR
SCI RX
INT ENA
BRKDT
FE
OE
PE
RXWAKE
P056
P057
P058
P059
Reserved
RXDT7
TXDT7
RXDT6
TXDT6
RXDT5
TXDT5
RXDT4
TXDT4
RXDT3
RXDT2
TXDT2
RXDT1
TXDT1
RXDT0
TXDT0
RXBUF
TXBUF
Reserved
TXDT3
†
Once the WD OVRFL RST ENA bit is set, these bits cannot be changed until after a full power-down cycle has been completed.
46
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251--1443
TMS370Cx4x
8-BIT MICROCONTROLLER
SPNS016C -- NOVEMBER 1992 -- REVISED FEBRUARY 1997
Table 19. Peripheral File Frame Compilation (Continued)
PF
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
REG
SCI1 MODULE CONTROL REGISTER (CONTINUED)
P05A
P05B
P05C
Reserved
SCICLK
DATA IN
SCICLK
DATA OUT
SCICLK
FUNCTION
SCICLK
DATA DIR
P05D
P05E
P05F
—
—
—
—
SCIPC1
SCIPC2
SCIPRI
SCITXD
DATA IN
SCITXD
DATA OUT
SCITXD
FUNCTION
SCITXD
DATA DIR
SCIRXD
DATA IN
SCIRXD
DATA OUT
SCIRXD
FUNCTION
SCIRXD
DATA DIR
SCITX
PRIORITY
SCIRX
PRIORITY
SCI
ESPEN
SCI STEST
—
—
—
—
T2A MODULE REGISTER
Modes: Dual-Capture and Dual-Compare
P060 Bit 15
P061 Bit 7
P062 Bit 15
P063 Bit 7
P064 Bit 15
P065 Bit 7
P066 Bit 15
P067 Bit 7
T2A Counter MSbyte
T2A Counter LSbyte
Bit 8
T2ACNTR
T2AC
Bit 0
Bit 8
Bit 0
Bit 8
Bit 0
Bit 8
Bit 0
Compare Register MSbyte
Compare Register LSbyte
Capture/Compare Register MSbyte
Capture/Compare Register LSbyte
Capture Register 2 MSbyte
Capture Register 2 LSbyte
T2ACC
T2AIC
P068
P069
Reserved
T2A
INPUT
SELECT1
T2A OVRFL-
INT ENA
T2A OVRFL
INT FLAG
T2A INPUT
SELECT0
T2A SW
RESET
P06A
—
—
—
T2ACTL1
Mode: Dual-Compare
T2AEDGE1
INT FLAG
T2AC2
INT FLAG
T2AC1
INT FLAG
T2AEDGE1
INT ENA
T2AC2
INT ENA
T2AC1
INT ENA
P06B
P06C
—
—
T2ACTL2
T2ACTL3
T2A
MODE = 0
T2AC1
OUT ENA
T2AC2
OUT ENA
T2AC1
RST ENA
T2AEDGE1
OUT ENA
T2AEDGE1
POLARITY
T2AEDGE1
RST ENA
T2AEDGE1
DET ENA
Mode: Dual-Capture
T2AEDGE1
INT FLAG
T2AEDGE2
INT FLAG
T2AC1
INT FLAG
T2AEDGE1
INT ENA
T2AEDGE2
INT ENA
T2AC1
INT ENA
P06B
P06C
—
—
T2ACTL2
T2ACTL3
T2A
MODE = 1
T2AC1
RST ENA
T2AEDGE2
POLARITY
T2AEDGE1
POLARITY
T2AEDGE2
DET ENA
T2AEDGE1
DET ENA
—
—
Modes: Dual-Capture and Dual-Compare
T2AEVT
DATA IN
T2AEVT
DATA OUT
T2AEVT
FUNCTION
T2AEVT
DATA DIR
P06D
P06E
P06F
—
—
—
—
T2APC1
T2APC2
T2APRI
T2AIC2/PWM T2AIC2/PWM T2AIC2/PWM T2AIC2/PWM T2AIC1/CR
T2AIC1/CR
DATA OUT
T2AIC1/CR
FUNCTION
T2AIC1/CR
DATA DIR
DATA IN
DATA OUT
FUNCTION
DATA DIR
DATA IN
T2A
PRIORITY
T2A STEST
—
—
—
—
—
—
47
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251--1443
TMS370Cx4x
8-BIT MICROCONTROLLER
SPNS016C -- NOVEMBER 1992 -- REVISED FEBRUARY 1997
Table 19. Peripheral File Frame Compilation (Continued)
PF
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
REG
ADC1 MODULE CONTROL REGISTER
CONVERT
START
SAMPLE
START
REF VOLT
SELECT2
REF VOLT
SELECT1
REF VOLT
SELECT0
AD INPUT
SELECT2
AD INPUT
SELECT1
AD INPUT
SELECT0
P070
ADCTL
AD INT
FLAG
P071
P072
—
—
—
—
—
AD READY
AD INT ENA ADSTAT
ADDATA
A-to-D Conversion Data Register
Reserved
P073
to
P07C
P07D
P07E
Port E Data Input Register
Port E Input Enable Register
ADIN
ADENA
AD
PRIORITY
P07F
AD STEST
AD ESPEN
—
—
—
—
—
ADPRI
48
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251--1443
TMS370Cx4x
8-BIT MICROCONTROLLER
SPNS016C -- NOVEMBER 1992 -- REVISED FEBRUARY 1997
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage, VCC, VCC3 (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . --0.6 V to 7 V
Input voltage range, All pins except MC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . --0.6 V to 7 V
MC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . --0.6 V to 14 V
Input clamp current, IIK (VI 0 or VI VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Output clamp current, IOK (VO 0 or VO VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
‡
Continuous output current per buffer, IO (VO = 0 to VCC
)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 mA
Maximum ICC current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 mA
Maximum ISS current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -- 170 mA
Continuous power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 W
Operating free-air temperature, TA: L version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to 70C
A version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . --40C to 85C
T version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . --40C to 105C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -- 6 5 C to 150C
†
‡
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Electrical characteristics are specified with all output buffers loaded with the specified I current. Exceeding the specified I current in any buffer
O
O
can affect the levels on other buffers.
NOTE 1: Unless otherwise noted, all voltage values are with respect to V
.
SS
recommended operating conditions (see Note 1)
MIN
4.5
NOM
MAX
5.5
5.5
5.5
0.3
0.8
0.3
UNIT
V
V
V
V
Supply voltage (see Note 1)
5
V
V
V
V
CC
RAM data retention supply voltage (see Note 2)
Analog supply voltage (see Note 1)
Analog supply ground
3
CC
4.5
5
0
CC3
SS3
-- 0 . 3
All pins except MC
MC, normal operation
V
V
SS
V
Low-level input voltage
V
IL
SS
All pins except MC, XTAL2/CLKIN, and RESET
XTAL2/CLKIN
2
V
V
V
CC
CC
0.8 V
0.7 V
11.7
V
High-level input voltage
V
CC
CC
IH
RESET
CC
EEPROM write protect override
Microcomputer
12
13
V
0.3
13.5
70
V
MC (mode control) voltage
V
SS
MC
EPROM programming voltage (V
)
PP
13
0
13.2
L version
A version
T version
T
A
Operating free-air temperature
-- 4 0
-- 4 0
85
C
105
NOTES: 1. Unless otherwise noted, all voltage values are with respect to V
.
SS
2. RESET must be externally activated when V or SYSCLK is out of the recommended operating range.
CC
49
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251--1443
TMS370Cx4x
8-BIT MICROCONTROLLER
SPNS016C -- NOVEMBER 1992 -- REVISED FEBRUARY 1997
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V
V
Low-level digital output voltage
I
= 1.4 mA
= --50 A
= --2 mA
0.4
V
OL
OL
I
0.9 V
CC
OH
High-level output voltage
Input current
V
OH
I
2.4
OH
0 V < V 0.3 V
10
I
A
0.3 V < V 13
650
I
I
MC
I
I
12 V V 13 V
(see Note 3)
I
50
mA
I
I
Input current
I/O pins
0 V V V
10
A
mA
A
I
CC
Low-level output current
V
= 0.4 V
OL
1.4
-- 5 0
-- 2
OL
V
= 0.9 V
CC
OH
I
High-level output current
OH
V
= 2.4 V
mA
OH
SYSCLK = 5 MHz
(see Notes 4 and 5)
30
20
7
45
30
11
SYSCLK = 3 MHz
(see Notes 4 and 5)
Supply current (Operating mode)
OSC POWER bit = 0 (see Note 6)
mA
mA
SYSCLK = 0.5 MHz
(see Notes 4 and 5)
SYSCLK = 5 MHz
(see Notes 4 and 5)
10
8
17
11
SYSCLK = 3 MHz
(see Notes 4 and 5)
Supply current (STANDBY mode)
OSC POWER bit = 0 (see Note 7)
I
CC
SYSCLK = 0.5 MHz
(see Notes 4 and 5)
2
3.5
8.6
3.0
30
SYSCLK = 3 MHz
(see Notes 4 and 5)
6
Supply current (STANDBY mode)
OSC POWER bit = 1 (see Note 8)
mA
SYSCLK = 0.5 MHz
(see Notes 4 and 5)
2
XTALK2/CLKIN < 0.2 V
(see Note 4)
Supply current (HALT mode)
2
A
NOTES: 3. Microcontroller-single chip mode, ports configured as inputs, or outputs with no load. All inputs 0.2 V or V -- 0 . 2 V.
CC
4. XTAL2/CLKIN is driven with an external square wave signal with 50% duty cycle and rise and fall times less than 10 ns. Current
can be higher with a crystal oscillator. At 5-MHz SYSCLK this extra current = 0.01 mA (total load capacitance + crystal capacitance
in pF).
5. Maximum operating current = 7.6 (SYSCLK) + 7 mA.
6. Maximum standby current =3 (SYSCLK) + 2 mA. (Osc power bit = 0.)
7. Maximum standby current = 2.24 (SYSCLK) + 1.9 mA. (Osc power bit = 1 and valid up to 3-MHz SYSCLK.)
8. Input current I is a maximum of 50 mA only when EPROM is being programmed.
PP
50
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251--1443
TMS370Cx4x
8-BIT MICROCONTROLLER
SPNS016C -- NOVEMBER 1992 -- REVISED FEBRUARY 1997
RECOMMENDED CRYSTAL/CLOCK CONNECTIONS
XTAL2/CLKIN
XTAL1
XTAL2/CLKIN
XTAL1
†
C3
†
†
C1
C2
Crystal/Ceramic
External
Clock Signal
‡
Resonator
†
‡
The values of C1 and C2 are typically 15 pF and C3 value is typically 50 pF. See the manufacturer’s recommendations for ceramic resonators.
The crystal/ceramic resonator frequency is four times the reciprocal of the system clock period.
TYPICAL OUTPUT LOAD CIRCUIT§
Load Voltage
1.2 k
V
O
20 pF
Case 1: V = V = 2.4 V; Load Voltage = 0 V
O
OH
Case 2: V = V = 0.4 V; Load Voltage = 2.1
O
OL
§
All measurements are made with the pin loading as shown unless otherwise noted. All measurements are made with XTAL2/CLKIN driven by
an external square wave signal with a 50% duty cycle and rise and fall times less than 10 ns unless otherwise stated.
TYPICAL INPUT BUFFERS
V
V
CC
CC
Pin Data
300
6 k
30
20
Output
Enable
I/O
INT 1
20
GND
GND
51
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251--1443
TMS370Cx4x
8-BIT MICROCONTROLLER
SPNS016C -- NOVEMBER 1992 -- REVISED FEBRUARY 1997
PARAMETER MEASUREMENT INFORMATION
timing parameter symbology
Timing parameter symbols have been created in accordance with JEDEC Standard 100. In order to shorten the
symbols, some of the pin names and other related terminology have been abbreviated as follows:
A
AR
B
CI
D
Address
Array
Byte
XTAL2/CLKIN
Data
Program
R
RXD
SC
SCC
TXD
W
Read
SCIRXD
SYSCLK
SCICLK
SCITXD
Write
PGM
Lowercase subscripts and their meanings are:
c
d
f
cycle time (period)
delay time
fall time
r
su
v
rise time
setup time
valid time
pulse duration (width)
h
hold time
w
The following additional letters are used with these meanings:
H
L
High
Low
V
Z
Valid
High Impedance
All timings are measured between high and low measurement points as indicated in the figures below.
0.8 V V (High)
2 V (High)
CC
0.8 V (Low)
0.8 V (Low)
XTAL2/CLKIN Measurement Points
General Measurement Points
52
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251--1443
TMS370Cx4x
8-BIT MICROCONTROLLER
SPNS016C -- NOVEMBER 1992 -- REVISED FEBRUARY 1997
external clocking requirements for clock divided by 4†
NO.
1
PARAMETER
Pulse duration, XTAL2/CLKIN (see Note 9)
Rise time, XTAL2/CLKIN
MIN
MAX
UNIT
ns
t
t
t
t
20
w(Cl)
2
30
30
ns
r(Cl)
3
Fall time, XTAL2/CLKIN
ns
f(CI)
4
Delay time, XTAL2/CLKIN rise to SYSCLK fall
Crystal operating frequency
100
20
ns
d(CIH-SCL)
CLKIN
2
MHz
MHz
‡
SYSCLK
System clock
0.5
5
†
‡
For V and V , refer to recommended operating conditions.
SYSCLK = CLKIN/4
IL
IH
NOTE 9: This pulse can be either a high pulse, which extends from the earliest valid high to the final valid high in an XTAL2/CLKIN cycle or a
low pulse, which extends from the earliest valid low to the final valid low in an XTAL2/CLKIN cycle.
1
XTAL2/CLKIN
2
3
4
SYSCLK
Figure 18. External Clock Timing for Divide-by-4
external clocking requirements for clock divided by 1 (PLL)†
§
NO.
1
PARAMETER
Pulse duration, XTAL2/CLKIN (see Note 9)
Rise time, XTAL2/CLKIN
MIN
MAX
UNIT
ns
t
t
t
t
20
w(Cl)
2
30
30
100
5
ns
r(Cl)
3
Fall time, XTAL2/CLKIN
ns
f(CI)
4
Delay time, XTAL2/CLKIN rise to SYSCLK rise
Crystal operating frequency
ns
d(CIH-SCH)
CLKIN
2
2
MHz
MHz
§
SYSCLK
System clock
5
†
§
For V and V , refer to recommended operating conditions.
SYSCLK = CLKIN/1
IL
IH
NOTE 9: This pulse can be either a high pulse, which extends from the earliest valid high to the final valid high in an XTAL2/CLKIN cycle or a
low pulse, which extends from the earliest valid low to the final valid low in an XTAL2/CLKIN cycle.
1
XTAL2/CLKIN
4
2
3
SYSCLK
Figure 19. External Clock Timing for Divide-by-1
53
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251--1443
TMS370Cx4x
8-BIT MICROCONTROLLER
SPNS016C -- NOVEMBER 1992 -- REVISED FEBRUARY 1997
switching characteristics and timing requirements (see Note 10 and Figure 20)
NO.
PARAMETER
MIN
200
200
MAX
2000
500
0.5 t
UNIT
ns
Divide-by-4
Divide-by-1
5
t
Cycle time, SYSCLK (system clock)
c
ns
6
7
t
t
Pulse duration, SYSCLK low
Pulse duration, SYSCLK high
0.5 t -- 2 0
ns
w(SCL)
w(SCH)
c
c
0.5 t
0.5 t + 20
ns
c
c
NOTE 10: t = system-clock cycle time = 1/SYSCLK.
c
5
7
6
SYSCLK
Figure 20. SYSCLK Timing
general-purpose output signal-switching time requirements
MIN
TYP
30
MAX
UNIT
t
t
Rise time
Fall time
ns
ns
r
f
30
t
r
t
f
recommended EEPROM timing requirements for programming
MIN
MAX
UNIT
ms
t
t
Pulse duration, programming signal to be certain valid data is stored (byte mode)
Pulse duration, programming signal to be certain valid data is stored (array mode)
10
20
w(PGM)B
ms
w(PGM)AR
recommended EPROM operating conditions for programming
MIN
TYP
5.5
MAX
6
UNIT
V
V
V
Supply voltage
4.75
13
CC
PP
Supply voltage at MC pin
13.2
30
13.5
50
5
V
I
Supply current at MC pin during programming (V = 13 V)
mA
PP
PP
Divide-by-4
Divide-by-1
0.5
2
SYSCLK
System clock
MHz
5
recommended EPROM timing requirements for programming
MIN
TYP
MAX
UNIT
t
Pulse duration, programming signal (see Note 11)
0.40
0.50
3
ms
w(EPGM)
NOTE 11: Programming pulse is active when both EXE (EPCTL.0) and V
(EPCTL.6) are set.
PPS
54
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251--1443
TMS370Cx4x
8-BIT MICROCONTROLLER
SPNS016C -- NOVEMBER 1992 -- REVISED FEBRUARY 1997
SERIAL COMMUNICATIONS INTERFACE 1 (SCI1) INTERNAL CLOCK
ISOSYNCHRONOUS MODE I/O TIMING
SCI1 isosynchronous mode timing characteristics and requirements for internal clock
(see Note 10 and Figure 21)
NO.
24
25
26
27
28
29
30
PARAMETER
Cycle time, SCICLK
MIN
2t
MAX
UNIT
ns
t
t
t
t
t
t
t
131,072t
c
c(SCC)
c
Pulse duration, SCICLK low
t -- 4 5
0.5t
0.5t
+45
+45
ns
w(SCCL)
c
c(SCC)
Pulse duration, SCICLK high
t -- 4 5
ns
w(SCCH)
c
c(SCC)
Delay time, SCITXD valid after SCICLK low
Valid time, SCITXD data after SCICLK high
Setup time, SCIRXD to SCICLK high
Valid time, SCIRXD data after SCICLK high
-- 5 0
60
ns
d(SCCL-TXDV)
v(SCCH-TXD)
su(RXD-SCCH)
v(SCCH-RXD)
t
-- 5 0
ns
w(SCCH)
0.25t + 145
ns
c
0
ns
NOTE 10: t = system-clock cycle time = 1/SYSCLK.
c
24
26
25
SCICLK
SCITXD
27
28
Data Valid
29
30
Data Valid
SCIRXD
Figure 21. SCI1 Isosynchronous Mode Timing Diagram for Internal Clock
55
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251--1443
TMS370Cx4x
8-BIT MICROCONTROLLER
SPNS016C -- NOVEMBER 1992 -- REVISED FEBRUARY 1997
SERIAL COMMUNICATIONS INTERFACE 1 (SCI1) EXTERNAL CLOCK
ISOSYNCHRONOUS MODE I/O TIMING
SCI1 isosynchronous mode timing characteristics and requirements for external clock
(see Note 10 and Figure 22)
NO.
31
PARAMETER
Cycle time, SCICLK
MIN
10t
MAX
UNIT
ns
t
t
c(SCC)
c
32
Pulse duration, SCICLK low
4.25t + 120
ns
w(SCCL)
c
33
34
35
36
37
t
t
t
t
t
Pulse duration, SCICLK high
t + 120
ns
ns
ns
ns
ns
w(SCCH)
c
Delay time, SCITXD valid after SCICLK low
Valid time, SCITXD data after SCICLK high
Setup time, SCIRXD to SCICLK high
Valid time, SCIRXD data after SCICLK high
4.25t + 145
c
d(SCCL-TXDV)
v(SCCH-TXD)
su(RXD-SCCH)
v(SCCH-RXD)
t
w(SCCH)
40
2t
c
NOTE 10: t = system-clock cycle time = 1/SYSCLK.
c
31
33
32
SCICLK
SCITXD
34
35
Data Valid
36
37
Data Valid
SCIRXD
Figure 22. SCI1 Isosynchronous Mode Timing Diagram for External Clock
56
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251--1443
TMS370Cx4x
8-BIT MICROCONTROLLER
SPNS016C -- NOVEMBER 1992 -- REVISED FEBRUARY 1997
ADC1
The ADC1 has a separate power bus for its analog circuitry. These pins are referred to as VCC3 and VSS3. Their
purpose is to enhance ADC1 performance by preventing digital switching noise on the logic circuitry that could
be present on VSS and VCC from coupling into the ADC1 analog stage. All ADC1 specifications are given with
respect to VSS3 unless otherwise noted.
Resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 bits (256 values)
Monotonic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Yes
Output conversion code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 00h to FFh (00h for VI VSS3; FFh for VI Vref
)
Conversion time (excluding sample time) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164tc
recommended operating conditions
MIN
NOM
MAX
UNIT
4.5
5
5.5
V
Analog supply voltage
V
CC3
V
-- 0 . 3
V
+ 0.3
CC
CC
V
V
Analog ground
V
-- 0 . 3
V
+ 0.3
+ 0.1
V
V
V
SS3
SS
SS
†
Non-V
reference
2.5
V
V
CC3
ref
CC3
CC3
Analog input for conversion
must be stable, within 1/2 LSB of the required resolution, during the entire conversion time.
V
V
SS3
ref
†
V
ref
operating characteristics over ranges of recommended operating conditions
PARAMETER
Absolute accuracy (see Note 12)
TEST CONDITIONS
MIN
MAX
+1.5
0.9
2
UNIT
LSB
LSB
mA
A
V
V
= 5.5 V, V = 5.1 V
CC3
CC3
ref
Differential/integral linearity error (see Notes 12 and 13)
= 5.5 V, V = 5.1 V
ref
Converting
I
I
Analog supply current
Input current, AN0-AN7
CC3
I
Nonconverting
5
0 V V 5.5 V
2
A
I
V
input charge current
1
mA
k
ref
SYSCLK 3 MHz
24
10
Z
ref
Source impedance V
ref
3 MHz < SYSCLK 5 MHz
k
NOTES: 12. Absolute resolution = 20 mV. At V = 5 V, this is 1 LSB. As V decreases, LSB size decreases and thus absolute accuracy and
ref
ref
differential / integral linearity errors in terms of LSBs increases.
13. Excluding quantization error of 1/2 LSB.
57
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251--1443
TMS370Cx4x
8-BIT MICROCONTROLLER
SPNS016C -- NOVEMBER 1992 -- REVISED FEBRUARY 1997
ADC1 (continued)
The ADC1 module allows complete freedom in design of the sources for the analog inputs. The period of the
sample time is user-defined such that high-impedance sources can be accommodated without penalty to
low-impedance sources. The sample period begins when the SAMPLE START bit of the ADC1 control register
(ADCTL) is set to 1. The end of the signal sample period occurs when the conversion bit (CONVERT START)
of the ADCTL is set to 1. After a hold time, the converter resets the SAMPLE START and CONVERT START
bits, signaling that a conversion has started and the analog signal can be removed.
analog timing requirements
MIN
MAX
UNIT
t
t
t
Setup time, analog input to sample command
0
ns
su(S)
h(AN)
w(S)
Hold time, analog input from start of conversion
18t
ns
c
Pulse duration, sample time per kilohm of source impedance (see Note 14)
1
s/k
NOTE 14: The value given is valid for a signal with a source impedance > 1 k. If the source impedance is < 1 k, use a minimum sampling time
of 1 s.
Analog Stable
Analog
In
t
su(S)
Sample
Start
t
h(AN)
t
w(S)
Convert
Start
Figure 23. Analog Timing
58
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251--1443
TMS370Cx4x
8-BIT MICROCONTROLLER
SPNS016C -- NOVEMBER 1992 -- REVISED FEBRUARY 1997
Table 20 is designed to aid the user in referencing a device part number to a mechanical drawing. The table
shows a cross-reference of the device part number to the TMS370 generic package name and the associated
mechanical drawing by drawing number and name.
Table 20. TMS370Cx4x Family Package Type and Mechanical Cross-Reference
PKG TYPE
(mil pin spacing)
PKG TYPE NO. AND
MECHANICAL NAME
TMS370 GENERIC NAME
DEVICE PART NUMBERS
TMS370C040AFNA
TMS370C040AFNL
TMS370C040AFNT
TMS370C042AFNA
TMS370C042AFNL
TMS370C042AFNT
TMS370C340AFNA
TMS370C340AFNL
TMS370C340AFNT
TMS370C342AFNA
TMS370C342AFNL
TMS370C342AFNT
TMS370C742AFNT
FN -- 44 pin
(50-mil pin spacing)
PLASTIC LEADED CHIP CARRIER
(PLCC)
FN(S-PQCC-J**) PLASTIC J-LEADED
CHIP CARRIER
FZ -- 44 pin
(50-mil pin spacing)
CERAMIC LEADED CHIP CARRIER
(CLCC)
FZ(S-CQCC-J**) J-LEADED CERAMIC
CHIP CARRIER
SE370C742AFZT
SE370C742AJDT
JD -- 40 pin
(100-mil pin spacing) (CDIP)
CERAMIC DUAL-IN-LINE PACKAGE
JD(R-CDIP-T**) CERAMIC SIDE-BRAZE
DUAL-IN-LINE PACKAGE
TMS370C040ANA
TMS370C040ANL
TMS370C040ANT
TMS370C042ANA
TMS370C042ANL
TMS370C042ANT
TMS370C340ANA
TMS370C340ANL
TMS370C340ANT
TMS370C342ANA
TMS370C342ANL
TMS370C342ANT
TMS370C742ANT
N -- 40 pin
(100-mil pin spacing) (PDIP)
PLASTIC DUAL-IN-LINE PACKAGE
N(R-PDIP-T**) PLASTIC DUAL-IN-LINE
PACKAGE
JC -- 40 pin
(70-mil pin spacing)
CERAMIC SHRINK DUAL-IN-LINE
PACKAGE (CSDIP)
JC(R-CDIP-T40) CERAMIC SIDE-BRAZE
DUAL-IN-LINE PACKAGE
SE370C742AJCT
TMS370C040ANJA
TMS370C040ANJL
TMS370C040ANJT
TMS370C042ANJA
TMS370C042ANJL
TMS370C042ANJT
TMS370C340ANJA
TMS370C340ANJL
TMS370C340ANJT
TMS370C342ANJA
TMS370C342ANJL
TMS370C342ANJT
TMS370C742ANJT
NJ -- 40 pin
(70-mil pin spacing)
PLASTIC SHRINK DUAL--IN--LINE
PACKAGE (PSDIP)
NJ(R--PDIP--T**) PLASTIC SHRINK
DUAL-IN-LINE PACKAGE
†
†
NJ formerly known as N2; the mechanical drawing of the NJ is identical to the N2 package and did not need to be requalified.
59
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251--1443
TMS370Cx4x
8-BIT MICROCONTROLLER
SPNS016C -- NOVEMBER 1992 -- REVISED FEBRUARY 1997
MECHANICAL DATA
The following packaging information and addendum reflect the most current data available for the designated
device(s). This data is subject to change without notice and without revision of this document.
60
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251--1443
MECHANICAL DATA
MPLC004A – OCTOBER 1994
FN (S-PQCC-J**)
PLASTIC J-LEADED CHIP CARRIER
20 PIN SHOWN
Seating Plane
0.004 (0,10)
0.180 (4,57) MAX
0.120 (3,05)
D
0.090 (2,29)
D1
0.020 (0,51) MIN
3
1
19
0.032 (0,81)
0.026 (0,66)
4
18
D2/E2
D2/E2
E
E1
8
14
0.021 (0,53)
0.013 (0,33)
0.050 (1,27)
9
13
0.007 (0,18)
M
0.008 (0,20) NOM
D/E
D1/E1
D2/E2
NO. OF
PINS
**
MIN
0.385 (9,78)
MAX
MIN
MAX
MIN
MAX
0.395 (10,03)
0.350 (8,89)
0.356 (9,04)
0.141 (3,58)
0.191 (4,85)
0.291 (7,39)
0.341 (8,66)
0.169 (4,29)
0.219 (5,56)
0.319 (8,10)
0.369 (9,37)
20
28
44
52
68
84
0.485 (12,32) 0.495 (12,57) 0.450 (11,43) 0.456 (11,58)
0.685 (17,40) 0.695 (17,65) 0.650 (16,51) 0.656 (16,66)
0.785 (19,94) 0.795 (20,19) 0.750 (19,05) 0.756 (19,20)
0.985 (25,02) 0.995 (25,27) 0.950 (24,13) 0.958 (24,33) 0.441 (11,20) 0.469 (11,91)
1.185 (30,10) 1.195 (30,35) 1.150 (29,21) 1.158 (29,41) 0.541 (13,74) 0.569 (14,45)
4040005/B 03/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-018
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MJLC003A – FEBRUARY 1995
FZ (S-CQCC-J**)
J-LEADED CERAMIC CHIP CARRIER
28 LEAD SHOWN
0.040 (1,02)
45°
Seating Plane
0.180 (4,57)
0.155 (3,94)
0.140 (3,55)
0.120 (3,05)
A
B
1
4
26
25
5
0.050 (1,27)
C
(at Seating
Plane)
A
B
0.032 (0,81)
0.026 (0,66)
0.020 (0,51)
0.014 (0,36)
19
11
18
12
0.025 (0,64) R TYP
0.040 (1,02) MIN
0.120 (3,05)
0.090 (2,29)
A
B
C
JEDEC
NO. OF
PINS**
OUTLINE
MIN
MAX
MIN
MAX
MIN
MAX
0.485
0.495
0.430
0.455
0.410
0.430
MO-087AA
MO-087AB
MO-087AC
MO-087AD
28
44
52
68
(12,32)
(12,57)
(10,92)
(11,56)
(10,41)
(10,92)
0.685
0.695
0.630
0.655
0.610
0.630
(17,40)
(17,65)
(16,00)
(16,64)
(15,49)
(16,00)
0.785
0.795
0.730
0.765
0.680
0.740
(19,94)
(20,19)
(18,54)
(19,43)
(17,28)
(18,79)
0.985
0.995
0.930
0.955
0.910
0.930
(25,02)
(25,27)
(23,62)
(24,26)
(23,11)
(23,62)
4040219/B 03/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a ceramic lid using glass frit.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MCDI006 – OCTOBER 1994
JC (R-CDIP-T40)
CERAMIC SIDE-BRAZE DUAL-IN-LINE PACKAGE
1.414 (35,92)
1.386 (35,20)
40
21
0.600 (15,24)
0.580 (14,73)
1
20
0.032 (0,81) TYP
0.610 (15,49)
0.590 (14,99)
0.093 (2,38)
0.077 (1,96)
0.060 (1,52)
0.040 (1,02)
Seating Plane
0.175 (4,46) TYP
0.020 (0,51)
0.016 (0,41)
0.012 (0,31)
0.009 (0,23)
0.070 (1,78)
1.335 (33,91)
1.325 (33,66)
4040223-2/B 04/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a metal lid.
D. The terminals are gold plated.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MCDI005 – JANUARY 1998
JD (R-CDIP-T**)
CERAMIC SIDE-BRAZE DUAL-IN-LINE PACKAGE
24 PINS SHOWN
A
24
13
0.590 (15,00)
TYP
1
12
0.065 (1,65)
0.045 (1,14)
0.175 (4,45)
0.140 (3,56)
0.620 (15,75)
0.590 (14,99)
0.075 (1,91) MAX (4 Places)
Seating Plane
0.020 (0,51) MIN
0°–15°
0.021 (0,53)
0.015 (0,38)
0.125 (3,18) MIN
0.100 (2,54)
0.012 (0,30)
0.008 (0,20)
PINS **
24
28
1.450
40
48
52
DIM
1.250
2.050
2.435
2.650
A MAX
(31,75) (36,83) (52,07) (61,85) (67,31)
4040087/B 04/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package is hermetically sealed with a metal lid.
D. The terminals are gold-plated.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MPDI008 – OCTOBER 1994
N (R-PDIP-T**)
PLASTIC DUAL-IN-LINE PACKAGE
24 PIN SHOWN
A
24
13
0.560 (14,22)
0.520 (13,21)
1
12
0.060 (1,52) TYP
0.200 (5,08) MAX
0.020 (0,51) MIN
0.610 (15,49)
0.590 (14,99)
Seating Plane
0.100 (2,54)
0.125 (3,18) MIN
0.010 (0,25) NOM
0°–15°
0.021 (0,53)
0.015 (0,38)
0.010 (0,25)
PINS **
M
24
28
32
40
48
52
DIM
1.270
1.450
1.650
2.090
2.450
2.650
A MAX
(32,26) (36,83) (41,91) (53,09) (62,23) (67,31)
1.230
1.410
1.610
2.040
2.390
2.590
A MIN
(31,24) (35,81) (40,89) (51,82) (60,71) (65,79)
4040053/B 04/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-011
D. Falls within JEDEC MS-015 (32 pin only)
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MSDI005 – OCTOBER 1994
NJ (R-PDIP-T**)
PLASTIC SHRINK DUAL-IN-LINE PACKAGE
40 PIN SHOWN
A
PINS **
40
54
DIM
40
21
1.425
(36,20)
2.031
(51,60)
A MAX
0.560 (14,22) MAX
1
20
0.048 (1,216)
0.032 (0,816)
0.200 (5,08) MAX
0.020 (0,51) MIN
0.600 (15,24)
Seating Plane
0.070 (1,78)
0.010 (0,25)
0°–15°
0.125 (3,18) MIN
0.022 (0,56)
0.014 (0,36)
M
0.010 (0,25) NOM
4040034/B 04/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
Samples
Drawing
Qty
(1)
(2)
(3)
(4)
SE370C742AFZT
SE370C742AJCT
OBSOLETE
JLCC
FZ
44
40
40
44
44
44
44
TBD
TBD
TBD
TBD
TBD
TBD
Call TI
Call TI
Call TI
Call TI
OBSOLETE CDIP SB
OBSOLETE CDIP SB
JC
SE370C742AJDT
JD
Call TI
Call TI
TMS370C042AFNA
TMS370C042AFNL
TMS370C742AFNT
TMS370C742AFNTG4
NRND
NRND
PLCC
PLCC
PLCC
PLCC
FN
Call TI
Call TI
FN
Call TI
Call TI
OBSOLETE
OBSOLETE
FN
Call TI
Call TI
-40 to 105
-40 to 105
TMS370C742AFNT
TMS370C742AFNT
FN
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
TMS370C742AN2T
OBSOLETE
XCEPT
N2
40
TBD
Call TI
Call TI
-40 to 105
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
IMPORTANT NOTICE
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