TMS418160P-70DZ [TI]
1MX16 FAST PAGE DRAM, 70ns, PDSO42, 0.400 INCH, PLASTIC, SOJ-42;
| 型号： | TMS418160P-70DZ |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 1MX16 FAST PAGE DRAM, 70ns, PDSO42, 0.400 INCH, PLASTIC, SOJ-42 动态存储器 光电二极管 内存集成电路 |
| 文件： | 总28页 (文件大小：685K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TMS416160, TMS416160P, TMS418160, TMS418160P
TMS426160, TMS426160P, TMS428160, TMS428160P
1048576-WORD BY 16-BIT HIGH-SPEED DRAMS
SMKS160C – MAY 1995–REVISED NOVEMBER 1995
DGE PACKAGE
(TOP VIEW)
DZ PACKAGE
(TOP VIEW)
Organization . . . 1048576 × 16
Single Power Supply (5 V or 3.3 V)
Performance Ranges:
1
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
V
V
V
V
SS
1
50
49
48
47
46
45
44
43
42
41
40
CC
SS
CC
ACCESS ACCESS ACCESS READ OR
2
DQ0
DQ1
DQ2
DQ3
DQ15
DQ14
DQ13
DQ12
DQ0
DQ1
DQ2
DQ3
DQ15
DQ14
DQ13
DQ12
2
TIME
TIME
TIME
WRITE
CYCLE
MIN
110 ns
130 ns
150 ns
t
t
t
3
3
RAC
CAC
AA
MAX
’4xx160/P-60 60 ns
’4xx160/P-70 70 ns
’4xx160/P-80 80 ns
MAX
15 ns
18 ns
20 ns
MAX
30 ns
35 ns
40 ns
4
4
5
5
6
V
V
V
V
6
CC
SS
CC
SS
7
DQ4
DQ5
DQ6
DQ7
NC
DQ11
DQ10
DQ9
DQ8
NC
DQ4
DQ5
DQ6
DQ7
NC
DQ11
DQ10
DQ9
DQ8
NC
LCAS
UCAS
OE
7
Enhanced Page-Mode Operation With
CAS-Before-RAS (CBR) Refresh
Long Refresh Period and Self-Refresh
Option (TMS4xx160P)
3-State Unlatched Output
Low Power Dissipation
High-Reliability Plastic 42-Lead (DZ Suffix)
400-Mil-Wide Surface-Mount (SOJ) Package
and 44/50-Lead (DGE Suffix) Surface-Mount
Thin Small-Outline Package (TSOP)
8
8
9
9
10
11
12
13
14
15
16
17
18
19
20
21
10
11
NC
W
RAS
†
15
16
17
18
19
20
21
22
23
24
25
36
35
34
33
32
31
30
29
28
27
26
NC
NC
W
NC
LCAS
UCAS
OE
A9
A11
A10
A9
A8
A7
A6
A5
A4
†
A0
A1
A2
A3
Operating Free-Air Temperature Range
RAS
0°C to 70°C
†
A11
A10
Fabricated Using the Texas Instruments
Enhanced Performance Implanted CMOS
(EPIC ) Technology
†
A8
A7
A0
A1
A2
A3
V
V
SS
CC
A6
A5
A4
V
AVAILABLE OPTIONS
SELF
POWER
SUPPLY
REFRESH
CYCLES
REFRESH,
BATTERY
BACKUP
V
DEVICE
CC
SS
†
A10 and A11 are NC for TMS4x8160 and TMS4x8160P.
TMS416160
TMS416160P
TMS418160
TMS418160P
TMS426160
TMS426160P
TMS428160
TMS428160P
5 V
5 V
5 V
—
Yes
—
Yes
—
Yes
—
Yes
4096 in 64 ms
4096 in 128 ms
1024 in 16 ms
1024 in 128 ms
4096 in 64 ms
4096 in 128 ms
1024 in 16 ms
1024 in 128 ms
PIN NOMENCLATURE
5 V
A0–A11
DQ0–DQ15
LCAS
UCAS
NC
Address Inputs
3.3 V
3.3 V
3.3 V
3.3 V
Data In/Data Out
Lower Column-Address Strobe
Upper Column-Address Strobe
No Internal Connection
Output Enable
OE
RAS
description
Row-Address Strobe
‡
V
V
W
5-V or 3.3-V Supply
Ground
CC
SS
The TMS4xx160 series is a set of high-speed,
16777216-bit dynamic random-access memo-
ries (DRAMs) organized as 1048576 words of 16
bits each. The TMS4xx160P series is a similar
set of high-speed, low-power, self-refresh,
Write Enable
‡
See Available Options Table.
16777216-bit DRAMs organized as 1048576 words of 16 bits each. Both sets employ state-of-the-art
enhanced performance implanted CMOS (EPIC ) technology for high performance, reliability, and low power
at low cost.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
Copyright 1995, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS416160, TMS416160P, TMS418160, TMS418160P
TMS426160, TMS426160P, TMS428160, TMS428160P
1048576-WORD BY 16-BIT HIGH-SPEED DRAMS
SMKS160C – MAY 1995–REVISED NOVEMBER 1995
description (continued)
These devices feature maximum RAS access times of 60 ns, 70 ns, and 80 ns. All addresses and data-in lines
are latched on chip to simplify system design. Data out is unlatched to allow greater system flexibility.
The TMS4xx160 and TMS4xx160P are offered in a 44/50-lead plastic surface-mount TSOP (DGE suffix) and
a 42-lead plastic surface-mount SOJ (DZ suffix) package. These packages are characterized for operation from
0°C to 70°C.
2
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS416160, TMS416160P, TMS418160, TMS418160P
TMS426160, TMS426160P, TMS428160, TMS428160P
1048576-WORD BY 16-BIT HIGH-SPEED DRAMS
SMKS160C – MAY 1995–REVISED NOVEMBER 1995
†
logic symbol
RAM 1M × 16
17
18
19
20
23
24
25
26
27
28
16
15
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
20D8/21D0
0
A
1 048 575
20D15/21D7
20D16
20D17
‡
A10
A11
20D18
‡
20D19
C20[ROW]
G23/[REFRESH ROW]
14
31
RAS
24[PWR DWN]
C21
G24
LCAS
&
23C22
31
C21
G34
30
&
UCAS
23C32
31
Z31
24,25EN27
34,25EN37
13
29
23,21D
25
W
OE
2
DQ0
A,22D
26,27
A, Z26
3
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
4
5
7
8
9
10
33
A,32D
36,37
A, Z36
34
35
36
38
39
40
41
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
†
‡
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
The pin numbers shown correspond to the DZ package.
A10 and A11 are NC for TMS4x8160 and TMS4x8160P.
3
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS416160, TMS416160P, TMS418160, TMS418160P
TMS426160, TMS426160P, TMS428160, TMS428160P
1048576-WORD BY 16-BIT HIGH-SPEED DRAMS
SMKS160C – MAY 1995–REVISED NOVEMBER 1995
functional block diagrams (TMS4x6160/P)
RAS UCAS LCAS
W
OE
Timing and Control
A0
A1
8
Column Decode
Sense Amplifiers
32
Column-
Address
Buffers
256K Array
256K Array
256K Array
Data-
In
Reg.
R
o
16
256K Array
A7
32
I/O
Buffers
w
D
e
c
o
d
e
16
16 of 32
Selection
32
32
Data-
Out
Reg.
Row-
Address
Buffers
12
DQ0–DQ15
4
256K Array
12
256K Array
A8–
A11
(a) TMS4x6160, TMS4x6160P
functional block diagram (TMS4x8160/P)
RAS UCAS LCAS
W
OE
Timing and Control
A0
10
A1
Column Decode
Sense Amplifiers
32
Column-
Address
Buffers
256K Array
256K Array
256K Array
Data-
In
R
o
16
16
256K Array
A9
32
I/O
Reg.
w
Buffers
D
e
c
o
d
e
16 of 32
Selection
32
32
Data-
Out
Reg.
Row-
Address
Buffers
10
DQ0–DQ15
256K Array
10
256K Array
(b) TMS4x8160, TMS4x8160P
4
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS416160, TMS416160P, TMS418160, TMS418160P
TMS426160, TMS426160P, TMS428160, TMS428160P
1048576-WORD BY 16-BIT HIGH-SPEED DRAMS
SMKS160C – MAY 1995–REVISED NOVEMBER 1995
operation
dual CAS
Two CAS pins (LCAS and UCAS) are provided to give independent control of the 16 data-I/O pins
(DQ0–DQ15), with LCAS corresponding to DQ0–DQ7 and UCAS corresponding to DQ8–DQ15. For read or
write cycles, the column address is latched on the first xCAS falling edge. Each xCAS going low enables its
corresponding DQx pin with data associated with the column address latched on the first falling xCAS edge.
All address setup and hold parameters are referenced to the first falling xCAS edge.The delay time from xCAS
low to valid data out (see parameter t
) is measured from each individual xCAS to its corresponding DQx pin.
CAC
In order to latch in a new column address, both xCAS pins must be brought high. The column-precharge time
(see parameter t ) is measured from the last xCAS rising edge to the first xCAS falling edge of the new cycle.
CP
Keeping a column address valid while toggling xCAS requires a minimum setup time, t
least one xCAS must be brought low before the other xCAS is taken high.
. During t
, at
CLCH
CLCH
For early-write cycles, the data is latched on the first xCAS falling edge. Only the DQs that have the
corresponding xCAS low are written into. Each xCAS must meet t minimum in order to ensure writing
CAS
into the storage cell. To latch a new address and new data, all xCAS pins must be high and meet t
.
CP
enhanced page mode
Page-mode operation allows faster memory access by keeping the same row address while selecting random
column addresses. The time for row-address setup and hold and address multiplex is eliminated. The maximum
number of columns that can be accessed is determined by the maximum RAS low time and the xCAS
page-mode cycle time used. With minimum xCAS page-cycle time, all columns can be accessed without
intervening RAS cycles.
Unlike conventional page-mode DRAMs, the column-address buffers in this device are activated on the falling
edge of RAS. The buffers act as transparent or flow-through latches while xCAS is high. The falling edge of the
first xCAS latches the column addresses. This feature allows the devices to operate at a higher data bandwidth
than conventional page-mode parts because data retrieval begins as soon as the column address is valid rather
than when xCAS transitions low. This performance improvement is referred to as enhanced page mode. A valid
column address may be presented immediately after t
well in advance of the falling edge of xCAS. In this case, data is obtained after t
(row-address hold time) has been satisfied, usually
RAH
maximum (access time from
CAC
xCAS low) if t
maximum (access time from column address) has been satisfied. In the event that column
AA
addresses for the next page cycle are valid at the time xCAS goes high, minimum access time for the next cycle
is determined by t (access time from rising edge of the last xCAS).
CPA
address: A0–A11 (TMS4x6160, TMS4x6160P) and A0–A9 (TMS4x8160, TMS4x8160P)
Twenty address bits are required to decode 1 of 1048576 storage cell locations. For the TMS4x6160 and
TMS4x6160P, 12 row-address bits are set up on A0 through A11 and latched onto the chip by RAS. Eight
column-address bits are set up on A0 through A7 and latched onto the chip by the first xCAS. For the
TMS4x8160 and TMS4x8160P, 10 row-address bits are set up on A0–A9 and latched onto the chip by RAS.
Ten column-address bits are set up on A0–A9 and latched onto the chip by the first xCAS. All addresses must
be stable on or before the falling edge of RAS and xCAS. RAS is similar to a chip enable in that it activates the
sense amplifiers as well as the row decoder. xCAS is used as a chip select, activating its corresponding output
buffer and latching the address bits into the column-address buffers.
write enable (W)
The read or write mode is selected through W. A logic high on W selects the read mode and a logic low selects
the write mode. The data inputs are disabled when the read mode is selected. When W goes low prior to xCAS
(early write), data out remains in the high-impedance state for the entire cycle, permitting a write operation with
OE grounded.
5
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS416160, TMS416160P, TMS418160, TMS418160P
TMS426160, TMS426160P, TMS428160, TMS428160P
1048576-WORD BY 16-BIT HIGH-SPEED DRAMS
SMKS160C – MAY 1995–REVISED NOVEMBER 1995
data in (DQ0–DQ15)
Data is written during a write or read-modify-write cycle. Depending on the mode of operation, the falling edge
of xCAS or W strobes data into the on-chip data latch. In an early-write cycle, W is brought low prior to xCAS
and the data is strobed in by the first occurring xCAS with setup and hold times referenced to this signal. In a
delayed-write or read-modify-write cycle, xCAS is already low and the data is strobed in by W with setup and
hold times referenced to this signal. In a delayed-write or read-modify-write cycle, OE must be high to bring the
output buffers to the high-impedance state prior to applying data to the I/O lines.
data out (DQ0–DQ15)
Data out is the same polarity as data in. The output is in the high-impedance (floating) state until xCAS and OE
are brought low. In a read cycle, the output becomes valid after the access time interval t
(which begins with
CAC
the negative transition of xCAS) as long as t
and t are satisfied.
RAC
AA
output enable (OE)
OE controls the impedance of the output buffers. When OE is high, the buffers remain in the high-impedance
state. Bringing OE low during a normal cycle activates the output buffers, putting them in the low-impedance
state. It is necessary for both RAS and xCAS to be brought low for the output buffers to go into the
low-impedance state, and they remain in the low-impedance state until either OE or xCAS is brought high.
RAS-only refresh
TMS4x6160, TMS4x6160P
A refresh operation must be performed at least once every 64 ms (128 ms for TMS4x6160P) to retain data. This
can be achieved by strobing each of the 4096 rows (A0–A11). A normal read or write cycle refreshes all bits
in each row that is selected. A RAS-only operation can be used by holding both xCAS at the high (inactive) level,
conserving power as the output buffers remain in the high-impedance state. Externally generated addresses
must be used for a RAS-only refresh.
TMS4x8160, TMS4x8160P
A refresh operation must be performed at least once every 16 ms (128 ms for TMS4x8160P) to retain data. This
can be achieved by strobing each of the 1024 rows (A0–A9). A normal read or write cycle refreshes all bits in
each row that is selected. A RAS-only operation can be used by holding both xCAS at the high (inactive) level,
conserving power as the output buffers remain in the high-impedance state. Externally generated addresses
must be used for a RAS-only refresh.
hidden refresh
Hidden refresh can be performed while maintaining valid data at the output pin. This is accomplished by holding
xCAS at V after a read operation and cycling RAS after a specified precharge period, similar to a RAS-only
IL
refresh cycle. The external address is ignored and the refresh address is generated internally.
xCAS-before-RAS (xCBR) refresh
xCBR refresh is utilized by bringing at least one xCAS low earlier than RAS (see parameter t
) and holding
CSR
it low after RAS falls (see parameter t
). For successive xCBR refresh cycles, xCAS can remain low while
CHR
cycling RAS. The external address is ignored and the refresh address is generated internally.
battery-backup refresh
TMS4x6160P
A low-power battery-backup refresh mode that requires less than 600 µA (5 V) or 350 µA (3.3 V) refresh current
is available on the TMS4x6160P. Data integrity is maintained using xCBR refresh with a period of 31.25 µs while
holding RAS low for less than 300 ns. To minimize current consumption, all input levels must be at CMOS levels
( V < 0.2 V, V > V – 0.2 V).
IL
IH
CC
6
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS416160, TMS416160P, TMS418160, TMS418160P
TMS426160, TMS426160P, TMS428160, TMS428160P
1048576-WORD BY 16-BIT HIGH-SPEED DRAMS
SMKS160C – MAY 1995–REVISED NOVEMBER 1995
TMS4x8160P
A low-power battery-backup refresh mode that requires less than 600 µA (5 V) or 350 µA (3.3 V) refresh current
is available on the TMS4x8160P. Data integrity is maintained using xCBR refresh with a period of 125 µs while
holding RAS low for less than 300 ns. To minimize current consumption, all input levels must be at CMOS levels
(V < 0.2 V, V > V – 0.2 V).
IL
IH
CC
self refresh (TMS4xx160P)
The self-refresh mode is entered by dropping xCAS low prior to RAS going low. Then xCAS and RAS are both
held low for a minimum of 100 µs. The chip is then refreshed internally by an on-board oscillator. No external
address is required because the CBR counter is used to keep track of the address. To exit the self-refresh mode,
both RAS and xCAS are brought high to satisfy t
. Upon exiting self-refresh mode, a burst refresh (refresh
CHS
a full set of row addresses) must be executed before continuing with normal operation. The burst refresh
ensures the DRAM is fully refreshed.
power up
To achieve proper device operation, an initial pause of 200 µs followed by a minimum of eight initialization cycles
is required after power up to the full V level. These eight initialization cycles must include at least one refresh
CC
(RAS-only or xCBR) cycle.
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
:
TMS41x160, TMS41x160P . . . . . . . . . . . . . . . . . . . . . . . – 1 V to 7 V
TMS42x160, TMS42x160P . . . . . . . . . . . . . . . . . . . . – 0.5 V to 4.6 V
CC
Voltage range on any pin (see Note 1): TMS41x160, TMS41x160P . . . . . . . . . . . . . . . . . . . . . . . – 1 V to 7 V
TMS42x160, TMS42x160P . . . . . . . . . . . . . . . . . . . . – 0.5 V to 4.6 V
Short-circuit output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 W
Operating free-air temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
A
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 125°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to V
.
SS
recommended operating conditions
TMS41x160
MIN NOM
TMS42x160
UNIT
MAX
MIN
NOM
3.3
0
MAX
V
V
V
V
T
Supply voltage
4.5
5
0
5.5
3
3.6
V
V
V
V
CC
SS
IH
Supply voltage
High-level input voltage
Low-level input voltage (see Note 2)
Operating free-air temperature
2.4
– 1
0
6.5
0.8
70
2
– 0.3
0
V
CC
+ 0.3
0.8
70
IL
°C
A
NOTE 2: The algebraic convention, where the more negative (less positive) limit is designated as minimum, is used for logic-voltage levels only.
7
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS416160, TMS416160P, TMS418160, TMS418160P
TMS426160, TMS426160P, TMS428160, TMS428160P
1048576-WORD BY 16-BIT HIGH-SPEED DRAMS
SMKS160C – MAY 1995–REVISED NOVEMBER 1995
TMS416160/P
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
’416160-60
’416160-70
’416160-80
’416160P-60
’416160P-70
’416160P-80
†
PARAMETER
UNIT
TEST CONDITIONS
MIN
MAX
MIN
MAX
MIN
MAX
High-level output
voltage
V
V
I
I
= – 5 mA
2.4
2.4
2.4
V
V
OH
OH
Low-level output
voltage
= 4.2 mA
0.4
± 10
± 10
90
0.4
± 10
± 10
80
0.4
± 10
± 10
70
OL
OL
Input current
(leakage)
V
= 5.5 V,
V = 0 V to 6.5 V,
I
CC
CC
All others = 0 V to V
I
I
I
µA
µA
mA
I
V
= 5.5 V,
V
= 0 V to V
O CC
,
Output current
(leakage)
CC
xCAS high
O
Read- or write-cycle
current
‡§
V
V
= 5.5 V,
Minimum cycle
CC1
CC
= 2.4 V (TTL),
IH
After 1 memory cycle,
RAS and xCAS high
2
2
2
mA
I
Standby current
CC2
V
= V
– 0.2 V (CMOS),
CC
’416160
1
1
1
mA
IH
After 1 memory cycle,
RAS and xCAS high
’416160P
500
500
500
µA
V
= 5.5 V,
Minimum cycle,
CC
RAS cycling,
Average refresh
current (RAS-only
refresh or CBR)
§
I
90
80
70
mA
CC3
xCAS high (RAS only),
RAS low after xCAS low (CBR)
V
= 5.5 V,
t
= MIN,
CC
PC
‡¶
#
I
I
Average page current
Self-refresh current
90
80
70
mA
CC4
RAS low,
xCAS cycling
xCAS < 0.2 V,
Measured after t
RAS < 0.2 V,
500
500
500
µA
CC6
min
RASS
Battery back-up
operating current
(equivalent refresh
time is 128 ms); CBR
only
t
V
= 31.25 µs,
t
≤ 300 ns,
RC
RAS
– 0.2 V ≤ V ≤ 6.5 V,
CC
IH
#
I
600
600
600
µA
CC10
0 V ≤ V ≤ 0.2 V, W and OE = V
Address and data stable
,
IH
IL
†
For conditions shown as MIN/MAX, use the appropriate value specified in the timing requirements.
Measured with outputs open
‡
§
¶
#
Measured with a maximum of one address change while RAS = V
IL
Measured with a maximum of one address change while xCAS = V
For TMS416160P only
IH
8
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS416160, TMS416160P, TMS418160, TMS418160P
TMS426160, TMS426160P, TMS428160, TMS428160P
1048576-WORD BY 16-BIT HIGH-SPEED DRAMS
SMKS160C – MAY 1995–REVISED NOVEMBER 1995
TMS418160/P
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
’418160-60
’418160-70
’418160-80
’418160P-60
’418160P-70
’418160P-80
†
PARAMETER
UNIT
TEST CONDITIONS
MIN
MAX
MIN
MAX
MIN
MAX
High-level output
voltage
V
V
I
I
= – 5 mA
2.4
2.4
2.4
V
V
OH
OH
Low-level output
voltage
= 4.2 mA
0.4
± 10
± 10
190
0.4
± 10
± 10
180
0.4
± 10
± 10
170
OL
OL
Input current
(leakage)
V
= 5.5 V,
V = 0 V to 6.5 V,
I
CC
CC
All others = 0 V to V
I
I
I
µA
µA
mA
I
V
= 5.5 V,
V
= 0 V to V
O CC
,
Output current
(leakage)
CC
xCAS high
O
Read- or
write-cycle current
‡§
V
V
= 5.5 V,
Minimum cycle
CC1
CC
= 2.4 V (TTL),
IH
After 1 memory cycle,
RAS and xCAS high
2
2
2
mA
I
Standby current
CC2
V
= V
– 0.2 V (CMOS),
CC
’418160
1
1
1
mA
IH
After 1 memory cycle,
RAS and xCAS high
’418160P
500
500
500
µA
V
= 5.5 V,
Minimum cycle,
xCAS high (RAS only),
RAS low after xCAS low (CBR)
= 5.5 V, = MIN,
Average refresh
current (RAS-only
refresh or CBR)
CC
RAS cycling,
§
I
190
180
170
mA
CC3
V
CC
t
PC
Average page
current
‡¶
#
I
I
100
500
90
80
mA
CC4
RAS low,
xCAS cycling
xCAS < 0.2 V,
Measured after t
RAS < 0.2 V,
Self-refresh current
500
500
µA
CC6
min
RASS
Battery back-up
operating current
(equivalent refresh
time is 128 ms);
CBR only
t
= 125 µs,
t
≤ 300 ns,
RC
RAS
– 0.2 V ≤ V ≤ 6.5 V,
V
CC
IH
#
I
600
600
600
µA
CC10
0 V ≤ V ≤ 0.2 V, W and OE = V
,
IH
IL
Address and data stable
†
For conditions shown as MIN/MAX, use the appropriate value specified in the timing requirements.
Measured with outputs open
‡
§
¶
#
Measured with a maximum of one address change while RAS = V
Measured with a maximum of one address change while xCAS = V
For TMS418160P only
IL
IH
9
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS416160, TMS416160P, TMS418160, TMS418160P
TMS426160, TMS426160P, TMS428160, TMS428160P
1048576-WORD BY 16-BIT HIGH-SPEED DRAMS
SMKS160C – MAY 1995–REVISED NOVEMBER 1995
TMS426160/P
electrical characteristics over recommended ranges of supply voltage and operating free-air
conditions (unless otherwise noted) (continued)
’426160-60
’426160-70
’426160-80
’426160P-60
’426160P-70
’426160P-80
†
PARAMETER
UNIT
TEST CONDITIONS
MIN
MAX
MIN
MAX
MIN
MAX
High-level
output
voltage
I
I
= – 2 mA
LVTTL
2.4
2.4
2.4
OH
V
V
V
OH
= – 100 µA
LVCMOS
V
–0.2
V
–0.2
V
–0.2
OH
CC
CC
CC
I
I
= 2 mA
LVTTL
0.4
0.2
0.4
0.2
0.4
0.2
Low-level
output voltage
OL
V
OL
= 100 µA
LVCMOS
OL
Input current
(leakage)
V
= 3.6 V,
V = 0 V to 3.9 V,
CC
All others = 0 V to V
I
I
I
I
± 10
± 10
90
± 10
± 10
80
± 10
± 10
70
µA
µA
mA
I
CC
V
= 3.6 V,
V
= 0 V to V
O CC
,
Output current
(leakage)
CC
xCAS high
O
Read- or write-
cycle current
‡§
V
V
= 3.6 V,
Minimum cycle
CC1
CC
= 2 V (LVTTL),
IH
After 1 memory cycle,
RAS and xCAS high
1
1
1
mA
Standby
current
I
CC2
V
= V
– 0.2 V
CC
IH
(LVCMOS),
’426160
500
200
500
200
500
200
µA
µA
After 1 memory cycle,
RAS and xCAS high
’426160P
Average
V
= 3.6 V,
Minimum cycle,
CC
RAS cycling,
xCAS high (RAS-only refresh)
RAS low after xCAS low (CBR)
refresh current
(RAS-only
refresh
§
I
90
80
70
mA
CC3
or CBR)
V
= 3.6 V,
t
= MIN,
Average page
current
CC
PC
‡¶
#
I
I
90
80
70
mA
CC4
RAS low,
xCAS cycling
Self-refresh
current
xCAS < 0.2 V,
Measured after t
RAS < 0.2 V,
250
250
250
µA
CC6
min
RASS
t
Battery
back-up
t
= 31.25 µs,
≤ 300 ns,
operating
current
(equivalent
refresh time is
128 ms),
CBR only
RC
RAS
V
CC
– 0.2 V ≤ V ≤ 3.9 V,
IH
#
I
350
350
350
µA
CC10
0 V ≤ V ≤ 0.2 V, W and OE = V
,
IH
IL
Address and data stable
†
For conditions shown as MIN/MAX, use the appropriate value specified in the timing requirements.
Measured with outputs open
‡
§
¶
#
Measured with a maximum of one address change while RAS = V
Measured with a maximum of one address change while xCAS = V
For TMS426160P only
IL
IH
10
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS416160, TMS416160P, TMS418160, TMS418160P
TMS426160, TMS426160P, TMS428160, TMS428160P
1048576-WORD BY 16-BIT HIGH-SPEED DRAMS
SMKS160C – MAY 1995–REVISED NOVEMBER 1995
TMS428160/P
electrical characteristics over recommended ranges of supply voltage and operating free-air
conditions (unless otherwise noted) (continued)
’428160-60
’428160-70
’428160-80
’428160P-60
’428160P-70
’428160P-80
†
PARAMETER
UNIT
TEST CONDITIONS
MIN
MAX
MIN
MAX
MIN
MAX
High-level
output
voltage
I
I
= – 2 mA
LVTTL
2.4
2.4
2.4
OH
V
V
V
OH
= – 100 µA
LVCMOS
V
–0.2
V
–0.2
V
–0.2
OH
CC
CC
CC
I
I
= 2 mA
LVTTL
0.4
0.2
0.4
0.2
0.4
0.2
Low-level
output voltage
OL
V
OL
= 100 µA
LVCMOS
OL
Input current
(leakage)
V
= 3.6 V,
V = 0 V to 3.9 V,
CC
All others = 0 V to V
I
I
I
I
± 10
± 10
190
± 10
± 10
180
± 10
± 10
170
µA
µA
mA
I
CC
V
= 3.6 V,
V
= 0 V to V
O CC
,
Output current
(leakage)
CC
xCAS high
O
Read- or write-
cycle current
‡§
V
V
= 3.6 V,
Minimum cycle
CC1
CC
= 2 V (LVTTL),
IH
After 1 memory cycle,
RAS and xCAS high
1
1
1
mA
Standby
current
I
CC2
V
= V
– 0.2 V
CC
IH
(LVCMOS),
’428160
500
200
500
200
500
200
µA
µA
After 1 memory cycle,
RAS and xCAS high
’428160P
Average
V
= 3.6 V,
Minimum cycle,
CC
RAS cycling,
xCAS high (RAS-only refresh)
RAS low after xCAS low (CBR)
refresh current
(RAS-only
refresh
§
I
190
180
170
mA
CC3
or CBR)
V
= 3.6 V,
t
= MIN,
Average page
current
CC
PC
‡¶
#
I
I
100
250
90
80
mA
CC4
RAS low,
xCAS cycling
Self-refresh
current
xCAS < 0.2 V,
Measured after t
RAS < 0.2 V,
250
250
µA
CC6
min
RASS
t
Battery
back-up
t
= 125 µs,
≤ 300 ns,
operating
current
(equivalent
refresh time is
128 ms),
CBR only
RC
RAS
V
CC
– 0.2 V ≤ V ≤ 3.9 V,
IH
#
I
350
350
350
µA
CC10
0 V ≤ V ≤ 0.2 V, W and OE = V
,
IH
IL
Address and data stable
†
For conditions shown as MIN/MAX, use the appropriate value specified in the timing requirements.
Measured with outputs open
‡
§
¶
#
Measured with a maximum of one address change while RAS = V
Measured with a maximum of one address change while xCAS = V
For TMS428160P only
IL
IH
11
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS416160, TMS416160P, TMS418160, TMS418160P
TMS426160, TMS426160P, TMS428160, TMS428160P
1048576-WORD BY 16-BIT HIGH-SPEED DRAMS
SMKS160C – MAY 1995–REVISED NOVEMBER 1995
capacitance over recommended ranges of supply voltage and operating free-air temperature,
f = 1 MHz (see Note 3)
PARAMETER
MIN
MAX
UNIT
pF
C
C
C
C
C
Input capacitance, A0–A11
Input capacitance, OE
5
7
7
7
7
i(A)
pF
i(OE)
i(RC)
i(W)
O
Input capacitance, xCAS and RAS
Input capacitance, W
pF
pF
Output capacitance
pF
NOTE 3:
V
= 5 V ± 0.5 V or 3.3 V ÷ 0.3 V (see Table 1), and the bias on pins under test is 0 V.
CC
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature
’4xx160-60
’4xx160-70
’4xx160-80
’4xx160P-60
’4xx160P-70
’4xx160P-80
PARAMETER
UNIT
MIN
MAX
30
MIN
MAX
35
MIN
MAX
40
t
t
t
t
t
t
t
t
t
t
Access time from column address (see Note 4)
Access time from xCAS low (see Note 4)
Access time from column precharge (see Note 4)
Access time from RAS low (see Note 4)
Access time from OE low (see Note 4)
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AA
15
18
20
CAC
CPA
RAC
OEA
CLZ
OH
35
40
45
60
70
80
15
18
20
Delay time, xCAS low to output in low-impedance state
Output data hold time (from xCAS)
0
3
3
0
0
0
3
3
0
0
0
3
3
0
0
Output data hold time (from OE)
OHO
OFF
OEZ
Output disable time after xCAS high (see Note 5)
Output disable time after OE high (see Note 5)
15
15
18
18
20
20
NOTES: 4. Access times for TMS42x160 are measured with output reference levels of V
OH
= 2 V and V = 0.8 V.
OL
5.
t
and t are specified when the output is no longer driven.
OEZ
OFF
12
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS416160, TMS416160P, TMS418160, TMS418160P
TMS426160, TMS426160P, TMS428160, TMS428160P
1048576-WORD BY 16-BIT HIGH-SPEED DRAMS
SMKS160C – MAY 1995–REVISED NOVEMBER 1995
timing requirements over recommended ranges of supply voltage and operating free-air
temperature
’4xx160-60
’4xx160-70
’4xx160-80
’4xx160P-60
’4xx160P-70
’4xx160P-80
UNIT
MIN
110
110
155
40
MAX
MIN
130
130
181
45
MAX
MIN
150
150
205
50
MAX
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Cycle time, read (see Note 6)
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
RC
Cycle time, write (see Note 6)
WC
Cycle time, read-write (see Note 6)
RWC
PC
Cycle time, page-mode read or write (see Notes 6 and 7)
Cycle time, page-mode read-write (see Note 6)
Pulse duration, RAS low, page mode (see Note 8)
Pulse duration, RAS low, nonpage mode (see Note 8)
Pulse duration, xCAS low (see Note 9)
Pulse duration, RAS high (precharge)
Pulse duration, W low
85
96
105
PRWC
RASP
RAS
CAS
RP
60 100 000
70 100 000
80 100 000
60
15
40
10
0
10 000
10 000
70
18
50
10
0
10 000
10 000
80
20
60
10
0
10 000
10 000
WP
Setup time, column address before xCAS low
Setup time, row address before RAS low
Setup time, data (see Note 9)
ASC
ASR
DS
0
0
0
0
0
0
Setup time, W high before xCAS low
0
0
0
RCS
CWL
RWL
WCS
CAH
DH
Setup time, W low before xCAS high
15
15
0
18
18
0
20
20
0
Setup time, W low before RAS high
Setup time, W low before xCAS low (early-write operation only)
Hold time, column address after xCAS low
Hold time, data (see Note 10)
10
10
10
0
15
15
10
0
15
15
10
0
Hold time, row address after RAS low
Hold time, W high after xCAS high (see Note 11)
Hold time, W high after RAS high (see Note 11)
Hold time, W low after xCAS low (early-write operation only)
Hold time, xCAS low to xCAS high
RAH
RCH
RRH
WCH
CLCH
RHCP
OEH
ROH
CHS
CP
0
0
0
10
5
15
5
15
5
Hold time, RAS high from xCAS precharge
Hold time, OE command
35
15
10
– 50
10
40
18
10
– 50
10
45
20
10
– 50
10
Hold time, RAS referenced to OE
Hold time, xCAS low after RAS high (self refresh)
Delay time, xCAS high (precharge)
Delay time, column address to W low (read-write operation
only)
t
55
63
70
ns
AWD
t
t
t
t
t
t
Delay time, RAS low to xCAS high (xCBR refresh only)
Delay time, xCAS high to RAS low
10
5
10
5
10
5
ns
ns
ns
ns
ns
ns
CHR
CRP
CSH
CSR
CWD
OED
Delay time, RAS low to xCAS high
60
5
70
5
80
5
Delay time, xCAS low to RAS low (xCBR refresh only)
Delay time, xCAS low to W low (read-write operation only)
Delay time, OE to data
40
15
46
18
50
20
NOTES: 6. All cycle times assume t = 5 ns.
T
ASC
7. To assure t
min, t
should be ≥ to t
.
CP
PC
8. In a read-write cycle, t
9. In a read-write cycle, t
and t
and t
must be observed.
must be observed.
RWD
CWD
RWL
CWL
10. Referenced to the later of xCAS or W in write operations
11. Either t or t must be satisfied for a read cycle.
RRH
RCH
13
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS416160, TMS416160P, TMS418160, TMS418160P
TMS426160, TMS426160P, TMS428160, TMS428160P
1048576-WORD BY 16-BIT HIGH-SPEED DRAMS
SMKS160C – MAY 1995–REVISED NOVEMBER 1995
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (continued)
’4xx160-60
’4xx160-70
’4xx160-80
’4xx160P-60
’4xx160P-70
’4xx160P-80
UNIT
MIN
15
30
30
20
0
MAX
MIN
15
MAX
MIN
15
MAX
t
t
t
t
t
t
t
t
t
t
Delay time, RAS low to column address (see Note 12)
Delay time, column address to RAS high
Delay time, column address to xCAS high
Delay time, RAS low to xCAS low (see Note 12)
Delay time, RAS high to xCAS low
30
35
40
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
RAD
35
40
RAL
35
40
CAL
45
20
52
20
60
RCD
RPC
RSH
RWD
CPW
RASS
RPS
0
0
Delay time, xCAS low to RAS high
15
85
60
100
110
18
20
Delay time, RAS low to W low (read-write operation only)
Delay time, W low after xCAS precharge (read-write operation only)
Pulse duration, self-refresh entry from RAS low
Pulse duration, RAS precharge after self refresh
’4x6160
98
110
75
68
100
130
100
150
64
128
16
64
128
16
64
128
16
ms
’4x6160P
t
Refresh time interval
’4x8160
REF
ms
ns
’4x8160P
128
30
128
30
128
30
t
T
Transition time
3
3
3
NOTE 12: The maximum value is specified only to assure access time.
PARAMETER MEASUREMENT INFORMATION
V
TH
V
CC
R
R1
R2
L
Output Under Test
Output Under Test
C
= 100 pF
L
C
= 100 pF
L
(a) LOAD CIRCUIT
(b) ALTERNATE LOAD CIRCUIT
(V) (Ω)
DEVICE
41x160/P
42x160/P
V
CC
(V)
R1 (Ω)
828
R2 (Ω)
295
V
TH
R
L
5
1.31
1.4
218
500
3.3
1178
868
Figure 1. Load Circuits for Timing Parameters
14
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS416160, TMS416160P, TMS418160, TMS418160P
TMS426160, TMS426160P, TMS428160, TMS428160P
1048576-WORD BY 16-BIT HIGH-SPEED DRAMS
SMKS160C – MAY 1995–REVISED NOVEMBER 1995
PARAMETER MEASUREMENT INFORMATION
t
RC
t
RAS
RAS
t
T
t
t
RP
t
RCD
t
CAS
UCAS
t
CLCH
(see Note A)
CP
t
CRP
LCAS
t
CSH
t
RSH
t
RAD
t
RAH
t
ASC
t
CAL
t
ASR
t
RAL
Row
Column
Don’t Care
Address
t
RRH
t
CAH
t
RCS
t
RCH
t
CAC
(see Note B)
Don’t Care
Don’t Care
W
t
OFF
t
AA
t
OH
Valid Data Out
t
CLZ
See Note D
See Note C
DQ0–DQ15
t
RAC
t
OHO
t
OEZ
t
ROH
Don’t Care
Don’t Care
t
OE
OEA
NOTES: A. To hold the address latched by the first xCAS going low, the parameter t
must be met.
CLCH
B.
t
is measured from xCAS to its corresponding DQx.
CAC
C. Output can go from the high-impedance state to an invalid-data state prior to the specified access time.
D. xCAS order is arbitrary.
Figure 2. Read-Cycle Timing
15
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS416160, TMS416160P, TMS418160, TMS418160P
TMS426160, TMS426160P, TMS428160, TMS428160P
1048576-WORD BY 16-BIT HIGH-SPEED DRAMS
SMKS160C – MAY 1995–REVISED NOVEMBER 1995
PARAMETER MEASUREMENT INFORMATION
t
WC
t
RAS
RAS
CAS
t
T
t
RP
t
RCD
t
UCAS
t
CLCH
(see Note A)
t
CP
LCAS
t
ASR
t
CRP
t
CSH
t
RSH
t
RAH
t
ASC
t
CAL
t
RAL
Address
Row
Column
Don’t Care
t
CAH
t
CWL
t
RAD
t
RWL
Don’t Care
Don’t Care
W
t
WP
t
DH
(see Note B)
Valid Data In
(see Note B)
Don’t Care
Don’t Care
DQ0–DQ15
t
DS
t
OED
t
OEH
Don’t Care
OE
NOTES: A. To hold the address latched by the first xCAS going low, the parameter t
B. Referenced to the first xCAS or W, whichever occurs last
C. xCAS order is arbitrary.
must be met.
CLCH
Figure 3. Write-Cycle Timing
16
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS416160, TMS416160P, TMS418160, TMS418160P
TMS426160, TMS426160P, TMS428160, TMS428160P
1048576-WORD BY 16-BIT HIGH-SPEED DRAMS
SMKS160C – MAY 1995–REVISED NOVEMBER 1995
PARAMETER MEASUREMENT INFORMATION
t
WC
t
RAS
RAS
t
T
t
RP
t
RCD
t
CSH
t
CRP
t
CAS
UCAS
t
RSH
t
CLCH
(see Note A)
LCAS
t
RAD
t
CP
t
ASR
t
RAH
t
ASC
t
CAL
t
RAL
Column
Address
Row
Don’t Care
t
CAH
t
WCS
t
WCH
W
t
CWL
t
RWL
t
WP
Don’t Care
DQ0–DQ15
Don’t Care
Valid Data In
t
DH
t
DS
OE
Don’t Care
NOTES: A. To hold the address latched by the first xCAS going low, the parameter t
B. xCAS order is arbitrary.
must be met.
CLCH
Figure 4. Early-Write-Cycle Timing
17
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS416160, TMS416160P, TMS418160, TMS418160P
TMS426160, TMS426160P, TMS428160, TMS428160P
1048576-WORD BY 16-BIT HIGH-SPEED DRAMS
SMKS160C – MAY 1995–REVISED NOVEMBER 1995
PARAMETER MEASUREMENT INFORMATION
t
RWC
t
RAS
RAS
t
RP
t
T
t
RCD
t
CAS
UCAS
t
CSH
t
CRP
t
CLCH
(see Note A)
t
CP
t
RSH
t
LCAS
RAD
t
RAH
t
ASC
t
ASR
Address
Row
Column
Don’t Care
t
t
CWL
CAH
t
AWD
t
RWL
t
CWD
t
RCS
t
WP
W
Don’t Care
Don’t Care
t
RWD
t
CLZ
See Note B
DQ8–DQ15
Valid Out
Don’t Care
DH
t
AA
t
t
OHO
t
CAC
(see Note C)
t
DS
t
RAC
t
OEZ
t
OEA
OE
Don’t Care
t
OED
See Note B
Don’t Care
Valid Out
Valid In
must be met.
DQ0–DQ7
NOTES: A. To hold the address latched by the first xCAS going low, the parameter t
CLCH
B. Output can go from a the high-impedance state to an invalid-data state prior to the specified access time.
C. is measured from xCAS to its corresponding DQx.
D. xCAS order is arbitrary.
t
CAC
Figure 5. Read-Modify-Write-Cycle Timing
18
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS416160, TMS416160P, TMS418160, TMS418160P
TMS426160, TMS426160P, TMS428160, TMS428160P
1048576-WORD BY 16-BIT HIGH-SPEED DRAMS
SMKS160C – MAY 1995–REVISED NOVEMBER 1995
PARAMETER MEASUREMENT INFORMATION
t
RP
t
RASP
RAS
t
RCD
t
CRP
UCAS
t
RHCP
t
RSH
t
CLCH
(see Note A)
t
PC
t
CSH
t
CAS
t
CP
t
LCAS
ASR
t
RAH
t
CAL
t
ASC
t
RAL
t
CAH
Address
W
Row
RAD
Column
Don’t Care
Column
Don’t Care
t
RRH
t
t
RCH
Don’t
Care
Don’t
Care
t
CAC
(see Note B)
t
OH
t
AA
t
CPA
(see Note C)
t
RCS
t
RAC
t
CLZ
t
OFF
See Note D
See Note D
Valid
Out
DQ8–DQ15
DQ0–DQ7
t
OEZ
t
AA
Valid
Out
Valid
Out
t
OEA
t
OHO
t
OHO
t
OEA
Don’t Care
Don’t Care
OE
NOTES: A. To hold the address latched by the first xCAS going low, the parameter t
must be met.
CLCH
B.
t
is measured from xCAS to its corresponding DQx.
CAC
C. Access time is t
or t
dependent.
AA
CPA
D. Output can go from the high-impedance state to an invalid-data state prior to the specified access time.
E. A write cycle or read-modify-write cycle can be mixed with the read cycles as long as the write- and read-modify-write-timing
specifications are not violated.
F. xCAS order is arbitrary.
Figure 6. Enhanced-Page-Mode Read-Cycle Timing
19
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS416160, TMS416160P, TMS418160, TMS418160P
TMS426160, TMS426160P, TMS428160, TMS428160P
1048576-WORD BY 16-BIT HIGH-SPEED DRAMS
SMKS160C – MAY 1995–REVISED NOVEMBER 1995
PARAMETER MEASUREMENT INFORMATION
t
RP
t
RAS
RASP
t
RSH
UCAS
t
RHCP
t
CLCH
t
PC
t
(see Note A)
RCD
t
t
CP
CRP
t
CSH
t
LCAS
CAS
t
ASR
t
CAH
t
ASC
t
CAL
t
RAH
t
RAL
Address
Row
RAD
Column
Don’t Care
Column
Don’t Care
t
t
CWL
t
CWL
t
WP
t
RWL
See Note B
t
DS
t
WCH
W
Don’t Care
Don’t Care
Don’t Care
DQ8–
DQ15
Valid In
Don’t Care
t
DH
See Note B
DQ0–
DQ7
Valid In
Valid In
Don’t Care
t
OED
OE
NOTES: A. To hold the address latched by the first xCAS going low, the parameter t
B. Referenced to the first xCAS or W, whichever occurs last
must be met.
CLCH
C. A read cycle or read-modify-write cycle can be mixed with the write cycles as long as the read- and read-modify-write-timing
specifications are not violated.
D. xCAS order is arbitrary.
Figure 7. Enhanced-Page-Mode Write-Cycle Timing
20
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS416160, TMS416160P, TMS418160, TMS418160P
TMS426160, TMS426160P, TMS428160, TMS428160P
1048576-WORD BY 16-BIT HIGH-SPEED DRAMS
SMKS160C – MAY 1995–REVISED NOVEMBER 1995
PARAMETER MEASUREMENT INFORMATION
t
RP
t
RASP
RAS
UCAS
LCAS
t
CSH
t
RSH
t
RCD
t
CRP
t
PRWC
t
CAS
t
CP
t
CLCH
(see Note A)
t
ASR
ASC
t
t
t
CAH
RAD
Address
Row
Column
Column
t
t
CWD
t
RAH
CWL
t
WP
t
AWD
t
RWL
t
RWD
W
t
CAC
t
AA
t
RCS
t
OEH
t
t
DS
CPA
t
AA
(see Note B)
t
RAC
CLZ
t
DH
Valid Out
(see Note C)
t
Valid In
Valid In
DQ0–DQ15
Valid Out
t
OEH
t
OEA
t
OEZ
t
OED
OE
NOTES: A. To hold the address latched by the first xCAS going low, the parameter t
must be met.
CLCH
B. Access time is t
or t
dependent.
CPA
AA
C. Output can go from the high-impedance state to an invalid-data state prior to the specified access time.
D. xCAS order is arbitrary.
E. A read or write cycle can be intermixed with read-modify-write cycles as long as the read- and write-cycle timing specifications are
not violated.
F.
t
is measured from xCAS to its corresponding DQx.
CAC
Figure 8. Enhanced-Page-Mode Read-Modify-Write-Cycle Timing
21
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS416160, TMS416160P, TMS418160, TMS418160P
TMS426160, TMS426160P, TMS428160, TMS428160P
1048576-WORD BY 16-BIT HIGH-SPEED DRAMS
SMKS160C – MAY 1995–REVISED NOVEMBER 1995
PARAMETER MEASUREMENT INFORMATION
t
RC
t
RAS
RAS
xCAS
t
RP
t
CRP
t
RPC
t
T
See Note A
Don’t Care
t
ASR
t
RAH
Don’t Care
Row
Don’t Care
Row
Address
Don’t Care
W
Hi-Z
DQ0–DQ15
Don’t Care
OE
NOTE A: All xCAS must be high.
Figure 9. RAS-Only Refresh-Cycle Timing
22
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS416160, TMS416160P, TMS418160, TMS418160P
TMS426160, TMS426160P, TMS428160, TMS428160P
1048576-WORD BY 16-BIT HIGH-SPEED DRAMS
SMKS160C – MAY 1995–REVISED NOVEMBER 1995
PARAMETER MEASUREMENT INFORMATION
Refresh Cycle
Memory Cycle
t
Refresh Cycle
t
RP
RAS
t
RAS
RAS
t
t
RP
CHR
t
CAS
xCAS
t
ASR
RAH
t
t
ASC
t
CAH
Address
W
Row Col
Don’t Care
t
RRH
t
RCS
Don’t Care
t
t
CAC
AA
t
OFF
t
RAC
DQ0–DQ15
OE
Valid Data
t
OEZ
t
CLZ
t
OEA
Figure 10. Hidden-Refresh-Cycle Timing
23
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS416160, TMS416160P, TMS418160, TMS418160P
TMS426160, TMS426160P, TMS428160, TMS428160P
1048576-WORD BY 16-BIT HIGH-SPEED DRAMS
SMKS160C – MAY 1995–REVISED NOVEMBER 1995
PARAMETER MEASUREMENT INFORMATION
t
RC
t
RP
t
RAS
RAS
t
CSR
t
t
CHR
RPC
t
T
xCAS
Don’t Care
Don’t Care
Don’t Care
W
Address
OE
DQ0–DQ15
Hi-Z
NOTE A: Any xCAS can be used.
Figure 11. Automatic-CBR-Refresh-Cycle Timing
24
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS416160, TMS416160P, TMS418160, TMS418160P
TMS426160, TMS426160P, TMS428160, TMS428160P
1048576-WORD BY 16-BIT HIGH-SPEED DRAMS
SMKS160C – MAY 1995–REVISED NOVEMBER 1995
PARAMETER MEASUREMENT INFORMATION
t
RASS
RAS
t
t
RPC
RPS
t
CSR
t
CHS
xCAS
t
CP
Address
W
Don’t Care
Don’t Care
Don’t Care
OE
t
OFF
DQ0–DQ15
Hi-Z
Figure 12. Self-Refresh-Cycle Timing
25
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS416160, TMS416160P, TMS418160, TMS418160P
TMS426160, TMS426160P, TMS428160, TMS428160P
1048576-WORD BY 16-BIT HIGH-SPEED DRAMS
SMKS160C – MAY 1995–REVISED NOVEMBER 1995
MECHANICAL DATA
DGE (R-PDSO-G44/50)
PLASTIC SMALL-OUTLINE PACKAGE
0.018 (0,45)
0.006 (0,16)
M
0.031 (0,80)
0.012 (0,30)
50
26
0.471 (11,96)
0.455 (11,56)
0.404 (10,26)
0.396 (10,06)
1
25
0.006 (0,15) NOM
0.829 (21,05)
0.821 (20,85)
Gage Plane
0.010 (0,25)
0°–5°
0.024 (0,60)
0.016 (0,40)
Seating Plane
0.004 (0,10)
0.047 (1,20) MAX
0.002 (0,05) MIN
4040070-4/C 4/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion.
26
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS416160, TMS416160P, TMS418160, TMS418160P
TMS426160, TMS426160P, TMS428160, TMS428160P
1048576-WORD BY 16-BIT HIGH-SPEED DRAMS
SMKS160C – MAY 1995–REVISED NOVEMBER 1995
MECHANICAL DATA
DZ (R-PDSO-J42)
PLASTIC SMALL-OUTLINE J-LEAD PACKAGE
1.080 (27,43)
1.070 (27,18)
42
22
0.445 (11,30)
0.435 (11,05)
0,405 (10,29)
0.395 (10,03)
1
21
0.032 (0,81)
0.026 (0,66)
0.148 (3,76)
0.128 (3,25)
0.106 (2,69) NOM
Seating Plane
0.004 (0,10)
0.380 (9,65)
0.020 (0,51)
0.016 (0,41)
0.007 (0,18)
M
0.360 (9,14)
0.008 (0,20) NOM
0.050 (1,27)
4040094-6/C 4/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Plastic body dimensions do not include mold protrusion. Maximum mold protrusion is 0.005 (0,125).
device symbolization (TMS416160P illustrated)
TI
P -SS
Speed ( -60, - 70, -80)
Low-Power/Self-Refresh Designator (Blank or P)
Package Code
TMS416160 DZ
W
B
Y
M LLLL P
Assembly Site Code
Lot Traceability Code
Month Code
Year Code
Die Revision Code
Wafer Fab Code
27
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
IMPORTANT NOTICE
Texas Instruments (TI) reserves the right to make changes to its products or to discontinue any semiconductor
product or service without notice, and advises its customers to obtain the latest version of relevant information
to verify, before placing orders, that the information being relied on is current.
TI warrants performance of its semiconductor products and related software to the specifications applicable at
the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are
utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each
device is not necessarily performed, except those mandated by government requirements.
Certain applications using semiconductor products may involve potential risks of death, personal injury, or
severe property or environmental damage (“Critical Applications”).
TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR WARRANTED
TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS.
Inclusion of TI products in such applications is understood to be fully at the risk of the customer. Use of TI
products in such applications requires the written approval of an appropriate TI officer. Questions concerning
potential risk applications should be directed to TI through a local SC sales office.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards should be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance, customer product design, software performance, or
infringement of patents or services described herein. Nor does TI warrant or represent that any license, either
express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property
right of TI covering or relating to any combination, machine, or process in which such semiconductor products
or services might be or are used.
Copyright 1996, Texas Instruments Incorporated
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