TMS626162-12A [TI]
1MX16 SYNCHRONOUS DRAM, PDSO50, 0.400 INCH, PLASTIC, TSOP-50;
| 型号： | TMS626162-12A |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 1MX16 SYNCHRONOUS DRAM, PDSO50, 0.400 INCH, PLASTIC, TSOP-50 动态存储器 光电二极管 内存集成电路 |
| 文件： | 总44页 (文件大小：655K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TMS626162
524288 BY 16-BIT BY 2-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY
SMOS683E – FEBRUARY 1995 – REVISED APRIL 1997
DGE PACKAGE
( TOP VIEW )
Organization . . . 512K × 16 × 2 Banks
3.3-V Power Supply (±10% Tolerance)
Two Banks for On-Chip Interleaving
(Gapless Accesses)
1
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
V
V
SS
DQ15
DQ14
CC
2
DQ0
DQ1
High Bandwidth – Up to 83-MHz Data Rates
3
CAS Latency (CL) Programmable to 2 or 3
Cycles From Column-Address Entry
4
V
V
SSQ
DQ13
DQ12
SSQ
DQ2
5
Burst Sequence Programmable to Serial or
Interleave
6
DQ3
7
V
V
CCQ
DQ11
DQ10
CCQ
DQ4
Burst Length Programmable to 1, 2, 4, 8, or
Full Page
8
9
DQ5
Chip Select and Clock Enable for
Enhanced-System Interfacing
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
V
V
SSQ
DQ9
DQ8
SSQ
DQ6
DQ7
Cycle-by-Cycle DQ-Bus Mask Capability
With Upper and Lower Byte Control
V
V
CCQ
CCQ
DQML
NC
DQMU
CLK
CKE
NC
A9
Auto-Refresh and Self-Refresh Capability
4K Refresh (Total for Both Banks)
W
CAS
RAS
CS
High-Speed, Low-Noise, Low-Voltage TTL
(LVTTL) Interface
Power-Down Mode
A11
A10
A0
Compatible With JEDEC Standards
Pipeline Architecture
A8
A7
Temperature Ranges:
Operating, 0°C to 70°C
Storage, – 55°C to 150°C
A1
A6
A2
A5
A3
A4
V
V
SS
CC
SYNCHRONOUS
CLOCK CYLE
TIME
ACCESS TIME
CLOCK TO
OUTPUT
REFRESH
INTERVAL
PIN NOMENCLATURE
A0–A10
Address Inputs
t
t
t
t
t
REF
CK3
CK2
AC3
AC2
‡
(CL = 3) (CL = 2)
(CL = 3)
(CL = 2)
A0–A10 Row Addresses
A0–A7 Column Addresses
A10 Automatic-Precharge Select
Bank Select
Column-Address Strobe
Clock Enable
†
’626162-12A
12 ns
12 ns
15 ns
18 ns
9 ns
9 ns
64 ms
64 ms
’626162-12
9 ns
10 ns
A11
CAS
CKE
†
–12A speed device is supported only at –5/+10% V
CL = CAS latency
CC
‡
CLK
CS
System Clock
Chip Select
description
DQ0–DQ15
DQML, DQMU Data/Output Mask Enables
NC
RAS
SDRAM Data Input/Output
The TMS626162 device is
a
high-speed
16777216-bit synchronous dynamic random-
access memory (SDRAM) organized as two
banks of 524288 words with 16 bits per word.
No Connect
Row-Address Strobe
Power Supply (3.3-V Typ)
Power Supply for Output Drivers (3.3-V Typ)
Ground
Ground for Output Drivers
Write Enable
V
CC
V
CCQ
All inputs and outputs of the TMS626162 series
are compatible with the LVTTL interface.
V
SS
V
W
SSQ
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 1997, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS626162
524288 BY 16-BIT BY 2-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY
SMOS683E – FEBRUARY 1995 – REVISED APRIL 1997
description (continued)
The SDRAM employs state-of-the-art technology for high performance, reliability, and low power. All inputs and
outputs are synchronized with the CLK input to simplify system design and enhance use with high-speed
microprocessors and caches.
The TMS626162 SDRAM is available in a 400-mil, 50-pin surface-mount TSOP package (DGE suffix).
functional block diagram
CLK
CKE
AND
Array Bank T
CS
DQMx
RAS
CAS
W
DQ
Buffer
Control
DQ0–DQ15
16
Array Bank B
A0–A11
12
Mode Register
operation
All inputs to the ’626162 SDRAM are latched on the rising edge of the system (synchronous) clock. The outputs,
DQ0–DQ15, also are referenced to the rising edge of CLK. The ’626162 has two banks that are accessed
independently. A bank must be activated before it can be accessed (read from or written to). Refresh cycles
refresh both banks alternately.
Five basic commands or functions control most operations of the ’626162:
Bank activate/row-address entry
Column-address entry/write operation
Column-address entry/read operation
Bank deactivate
Auto-refresh
Self-refresh
Additionally, operations can be controlled by three methods: using chip select (CS) to select/deselect the
devices, using DQMx to enable/mask the DQ signals on a cycle-by-cycle basis, or using CKE to suspend (or
gate) the CLK input. The device contains a mode register that must be programmed for proper operation.
Table 1 through Table 3 show the various operations that are available on the ’626162. These truth tables
identify the command and/or operations and their respective mnemonics. Each truth table is followed by a
legend that explains the abbreviated symbols. An access operation refers to any read or write command in
progress at cycle n. Access operations include the cycle upon which the read or write command is entered and
all subsequent cycles through the completion of the access burst.
2
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS626162
524288 BY 16-BIT BY 2-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY
SMOS683E – FEBRUARY 1995 – REVISED APRIL 1997
operation (continued)
†
Table 1. Basic Command Truth Table
STATE OF
BANK(S)
‡
COMMAND
CS
RAS
CAS
W
A11
A10
A9–A0
MNEMONIC
A9=V
A8 –A7 = 0
A6–A0 = V
T = deac
B = deac
Mode register set
L
L
L
L
X
X
MRS
Bank deactivate (precharge)
Deactivate all banks
X
L
L
L
L
L
L
H
H
H
L
L
L
BS
X
L
H
V
L
X
X
V
V
DEAC
DCAB
ACTV
WRT
X
Bank activate/row-address entry
Column-address entry/write operation
SB = deac
SB = actv
L
H
L
BS
BS
H
Column-address entry/write operation
with auto-deactivate
SB = actv
SB = actv
SB = actv
L
L
L
H
H
H
L
L
L
L
H
H
BS
BS
BS
H
L
V
V
V
WRT-P
READ
Column-address entry/read operation
Column-address entry/read operation
with auto-deactivate
H
READ-P
Burst stop
SB = actv
L
L
H
H
X
H
H
X
L
H
X
X
X
X
X
X
X
X
X
X
STOP
NOOP
DESL
No operation
X
X
Control-input inhibit/no operation
H
T = deac
B = deac
§
Auto refresh
L
L
L
H
X
X
X
REFR
†
For execution of these commands on cycle n:
– CKE (n–1) must be high, or
– t
– t
– t
must be satisfied for power-down exit, or
CESP
CESP
CES
and t
must be satisfied for self-refresh exit, or
RC
and nCLE must be satisfied for clock-suspend exit.
DQMx(n) is a don’t care.
‡
§
All other unlisted commands are considered vendor-reserved commands or illegal commands.
Auto-refresh or self-refresh entry requires that all banks be deactivated or in an idle state prior to the command entry.
Legend:
n
L
H
X
V
T
B
actv
deac
BS
SB
=
=
=
=
=
=
=
=
=
=
=
CLK cycle number
Logic low
Logic high
Don’t care, either logic low or logic high
Valid
Bank T
Bank B
Activated
Deactivated
Logic high to select bank T; logic low to select bank B
Bank selected by A11 at cycle n
3
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS626162
524288 BY 16-BIT BY 2-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY
SMOS683E – FEBRUARY 1995 – REVISED APRIL 1997
operation (continued)
†
Table 2. Clock Enable (CKE) Command Truth Table
CKE
(n–1)
CKE
(n)
CS
(n)
RAS
(n)
CAS
(n)
W
(n)
‡
COMMAND
STATE OF BANK(S)
MNEMONIC
SLFR
T = deac
B = deac
Self-refresh entry
H
H
L
L
L
L
L
H
X
¶
¶
T = no access operation
B = no access operation
§
Power-down entry on cycle (n + 1)
X
X
X
PDE
L
L
H
H
L
H
X
H
X
H
X
—
—
T = self refresh
B = self refresh
Self-refresh exit
H
T = power down
B = power down
#
Power-down exit
L
H
L
H
L
X
X
X
X
X
X
X
X
X
X
X
X
—
HOLD
—
¶
¶
T = access operation
B = access operation
CLK suspend on cycle (n + 1)
¶
¶
T = access operation
B = access operation
CLK suspend exit on cycle (n + 1)
H
†
‡
§
¶
For execution of these commands, A0–A11 (n) and DQMx (n) are don’t cares.
All other unlisted commands are considered vendor-reserved commands or illegal commands.
On cycle n, the device executes the respective command (listed in Table 1). On cycle (n + 1), the device enters power-down mode.
A bank is no longer in an access operation one cycle after the last data-out cycle of a read operation, and two cycles after the last data-in cycle
of a write operation. Neither the PDE nor the HOLD command is allowed on the cycle immediately following the last data-in cycle of a write
operation.
#
If setup time from CKE high to the next CLK high satisfies t
, the device executes the respective command (listed in Table 1). Otherwise,
CESP
either DESL or NOOP command must be applied before any other command.
Legend:
n
L
H
X
T
B
deac
=
=
=
=
=
=
=
CLK cycle number
Logic low
Logic high
Don’t care, either logic low or logic high
Bank T
Bank B
Deactivated
4
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS626162
524288 BY 16-BIT BY 2-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY
SMOS683E – FEBRUARY 1995 – REVISED APRIL 1997
operation (continued)
†
Table 3. Data-Mask (DQM) Command Truth Table
DQML
DQMU
(n)
STATE OF
BANK(S)
DATA IN
(n)
DATA OUT
(n + 2)
‡
§
COMMAND
MNEMONIC
T = deac
and
B = deac
—
X
X
N/A
N/A
Hi-Z
Hi-Z
—
T = actv
and
B = actv
—
—
¶
(no access operation)
T = write
or
B = write
Data-in enable
L
H
L
V
N/A
N/A
V
ENBL
MASK
ENBL
MASK
T = write
or
B = write
Data-in mask
M
T = read
or
B = read
Data-out enable
Data-out mask
N/A
N/A
T = read
or
H
Hi-Z
B = read
†
For execution of these commands on cycle n:
– CKE (n) must be high, or
– t
– t
– t
must be satisfied for power-down exit, or
CESP
CESP
CES
and t
must be satisfied for self-refresh exit, or
must be satisfied for clock suspend exit.
RC
and n
CLE
CS(n), RAS(n), CAS(n), W(n), and A0–A11 are don’t cares.
‡
§
All other unlisted commands are considered vendor-reserved commands or illegal commands.
DQML controls D0 –D7 and Q0 –Q7.
DQMU controls D8 –D15 and Q8–Q15.
¶
A bank is no longer in an access operation one cycle after the last data-out cycle of a read operation, and two cycles after the last data-in cycle
of a write operation. Neither the PDE nor the HOLD command is allowed on the cycle immediately following the last data-in cycle of a write
operation.
Legend:
n
L
H
X
V
M
N/A
T
B
actv
deac
write
read
=
=
=
=
=
=
=
=
=
=
=
=
=
CLK cycle number
Logic low
Logic high
Don’t care, either logic low or logic high
Valid
Masked input data
Not applicable
Bank T
Bank B
Activated
Deactivated
Activated and accepting data inputs on cycle n
Activated and delivering data outputs on cycle (n + 2)
5
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS626162
524288 BY 16-BIT BY 2-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY
SMOS683E – FEBRUARY 1995 – REVISED APRIL 1997
burst sequence
All data for the ’626162 is written or read in a burst fashion, that is, a single starting address is entered into the
device and then the ’626162 internally accesses a sequence of locations based on that starting address. After
thefirstaccesssomeofthesubsequentaccessescanbeatprecedingaswellassucceedingcolumnaddresses,
depending on the starting address entered. This sequence can be programmed to follow either a serial burst
or an interleave burst (see Table 4 through Table 6). The length of the burst can be programmed to be 1, 2, 4,
8, or full-page (256) accesses (see the section on setting the mode register, page 9). After a read burst is
complete (as determined by the programmed-burst length), the outputs are in the high-impedance state until
the next read access is initiated.
Table 4. 2-Bit Burst Sequences
INTERNAL COLUMN ADDRESS A0
DECIMAL
BINARY
START
2ND
START
2ND
0
1
0
1
1
0
1
0
0
1
0
1
1
0
1
0
Serial
Interleave
Table 5. 4-Bit Burst Sequences
INTERNAL COLUMN ADDRESS A1–A0
DECIMAL BINARY
START
2ND
3RD
2
4TH
3
START
00
2ND
3RD
10
11
4TH
11
0
1
2
3
0
1
2
3
1
2
3
0
1
0
3
2
01
10
11
00
01
00
11
10
3
0
01
00
01
10
11
Serial
0
1
10
00
01
10
11
1
2
11
2
3
00
3
2
01
10
01
00
Interleave
0
1
10
00
01
1
0
11
6
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS626162
524288 BY 16-BIT BY 2-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY
SMOS683E – FEBRUARY 1995 – REVISED APRIL 1997
burst sequence (continued)
Table 6. 8-Bit Burst Sequences
INTERNAL COLUMN ADDRESS A2–A0
DECIMAL
BINARY
START 2ND 3RD 4TH 5TH 6TH 7TH 8TH START 2ND 3RD 4TH 5TH 6TH 7TH 8TH
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
1
2
3
4
5
6
7
0
1
0
3
2
5
4
7
6
2
3
4
5
6
7
0
1
2
3
0
1
6
7
4
5
3
4
5
6
7
0
1
2
3
2
1
0
7
6
5
4
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
5
6
7
0
1
2
3
4
5
4
7
6
1
0
3
2
6
7
0
1
2
3
4
5
6
7
4
5
2
3
0
1
7
0
1
2
3
4
5
6
7
6
5
4
3
2
1
0
000
001
010
011
100
101
110
111
000
001
010
011
100
101
110
111
001
010
011
100
101
110
111
000
001
000
011
010
101
100
111
110
010 011 100 101 110 111
011 100 101 110 111 000
100 101 110 111 000 001
101 110 111 000 001 010
Serial
110
111
111 000 001 010 011
000 001 010 011 100
000 001 010 011 100 101
001 010 011 100 101 110
010 011 100 101 110 111
011 010 101 100 111 110
000 001 110 111 100 101
001 000 111 110 101 100
Interleave
110
111
111 000 001 010 011
110 001 000 011 010
100 101 010 011 000 001
101 100 011 010 001 000
latency
The beginning data-out cycle of a read burst can be programmed to occur two or three CLK cycles after the read
command (see the section on setting the mode register, page 9). This feature allows adjustment of the device
so that it operates using the capability to latch the data output. The delay between the READ command and
the beginning of the output burst is known as CAS latency. After the initial output cycle begins, the data burst
occurs at the CLK frequency without any intervening gaps. Use of minimum read latencies is restricted, based
on the maximum frequency rating of the ’626162.
There is no latency for data-in cycles (write latency). The first data-in cycle of a write burst is entered at the same
rising edge of CLK on which the WRT command is entered. The write latency is fixed and is not determined by
the mode-register contents.
two-bank operation
The ’626162 contains two independent banks that can be accessed individually or in an interleaved fashion.
Eachbank must be activated with a row address before it can be accessed. Each bank then must be deactivated
before it can be activated again with a new row address. The bank-activate/row-address-entry command
(ACTV) is entered by holding RAS low, CAS high, W high, and A11 valid on the rising edge of CLK. A bank can
be deactivated either automatically during a READ-P or a WRT-P command or by use of the deactivate-bank
(DEAC) command. Both banks can be deactivated at once by use of the DCAB command (see Table 1 and the
section on bank deactivation, page 8).
7
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS626162
524288 BY 16-BIT BY 2-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY
SMOS683E – FEBRUARY 1995 – REVISED APRIL 1997
two-bank row-access operation
The two-bank feature allows access of information on random rows at a higher rate of operation than is possible
with a standard DRAM, by activating one bank with a row address and, while the data stream is being accessed
to/from that bank, activating the second bank with another row address. When the data stream to or from the
first bank is complete, the data stream to or from the second bank can begin without interruption. After the
second bank is activated, the first bank can be deactivated to allow the entry of a new row address for the next
round of accesses. In this manner, operation can continue in an interleaved fashion. Figure 28 is an example
of two-bank row-interleaving read bursts with automatic deactivate for a CAS latency of three and burst length
of eight.
two-bank column-access operation
The availability of two banks allows the access of data from random starting columns between banks at a higher
rate of operation. After activating each bank with a row address (ACTV command), A11 can be used to alternate
READ or WRT commands between the banks to provide gapless accesses at the CLK frequency, provided all
specified timing requirements are met. Figure 29 is an example of two-bank column-interleaving read bursts
for a CAS latency of three and burst length of two.
bank deactivation (precharge)
Both banks can be deactivated (placed in precharge) simultaneously by using the DCAB command. A single
bank can be deactivated by using the DEAC command. The DEAC command is entered identically to the DCAB
command except that A10 must be low and A11 used to select the bank to be precharged as shown in Table 1.
A bank can be deactivated automatically by using A10 during a read or write command. If A10 is held high during
the entry of a read or write command, the accessed bank (selected by A11) is deactivated automatically upon
completion of the access burst. If A10 is held low during the entry of a read or write command, that bank remains
active following the burst. The read and write commands with automatic deactivation are signified as READ-P
and WRT-P.
chip select (CS)
CS can be used to select or deselect the ’626162 for command entry, which might be required for
multiple-memory-device decoding. If CS is held high on the rising edge of CLK (DESL command), the device
does not respond to RAS, CAS, or W until the device is selected again by holding CS low on the rising edge
of CLK. Any other valid command can be entered simultaneously on the same rising CLK edge of the select
operation. The device can be selected/deselected on a cycle-by-cycle basis (see Table 1 and Table 2). The use
of CS does not affect an access burst that is in progress; the DESL command can only restrict RAS, CAS, and
W input to the ’626162.
data mask
The mask command or its opposite, the data-in enable (ENBL) command (see Table 3), is performed on a
cycle-by-cycle basis to gate any data cycle within a read burst or a write burst. DQML controls DQ0–DQ7, and
DQMU controls DQ8–DQ15. The application of DQMx to a write burst has no latency (n
= 0 cycle), but the
DID
application of DQMx to a read burst has a latency of n
= 2 cycles. During a write burst, if DQMx is held high
DOD
on the rising edge of CLK, the data-input is ignored on that cycle. During a read burst, if DQMx is held high on
the rising edge of CLK and n cycles after that rising edge of CLK, the data-output is in the high-impedance
DOD
state. Figure 18 and Figure 32 through Figure 35 show examples of data-mask operation.
8
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS626162
524288 BY 16-BIT BY 2-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY
SMOS683E – FEBRUARY 1995 – REVISED APRIL 1997
CLK-suspend/power-down mode
For normal device operation, CKE should be held high to enable CLK. If CKE goes low during the execution
of a READ (READ-P) or WRT (WRT-P) operation, the DQ bus occurring at the immediate next rising edge of
CLK is frozen at its current state, and no further inputs are accepted until CKE returns high. This is known as
a CLK-suspend operation, and its execution indicates a HOLD command. The device resumes operation from
the point when it was placed in suspension, beginning with the second rising edge of CLK after CKE returns
high.
If CKE is brought low when no read or write command is in progress, the device enters power-down mode. If
both banks are deactivated when power-down mode is entered, power consumption is reduced to the minimum.
Power-down mode can be used during row-active or auto-refresh periods to reduce input-buffer power. After
power-down mode is entered, no further inputs are accepted until CKE returns high. To ensure that data in the
device remains valid during the power-down mode, the self-refresh command (SLFR) must be executed
concurrently with the power-down entry (PDE) command. When exiting power-down mode, new commands
can be entered on the first CLK edge after CKE returns high, provided that the setup time (t
) is satisfied.
CESP
Table 2 shows the command configuration for a CLK-suspend/power-down operation. Figure 19, Figure 20,
and Figure 38 show examples of the procedure.
setting the mode register
The ’626162 contains a mode register that must be programmed with the CAS latency, the burst type, and the
burst length. This is accomplished by executing a mode-register set (MRS) command with the information
entered on the address lines A0–A9. A logic 0 must be entered on A7 and A8, but A10 and A11 are don’t-care
entries for the ’626162. When A9 = 1, the write-burst length is always 1. When A9 = 0, the write-burst length
is defined by A0–A2. Figure 1 shows the valid combinations for a successful MRS command. Only valid
addresses allow the mode register to be changed. If the addresses are not valid, the previous contents of the
mode register remain unaffected. The MRS command is executed by holding RAS, CAS, and W low and the
input mode word valid on A0–A9 on the rising edge of CLK (see Table 1). The MRS command can be executed
only when both banks are deactivated.
A11
A10
A9
A8
0
A7
0
A6
A5
A4
A3
A2
A1
A0
Reserved
0 = Serial
1 = Interleave
(burst type)
REGISTER
BITS
REGISTER
BITS
†
†
REGISTER
BIT A9
Write Burst
Length
CAS
latency
BURST LENGTH
‡
A6
A5
A4
A2
A1
A0
0
0
0
0
1
0
0
1
1
1
0
1
0
1
1
1
2
4
8
256
0
1
A2–A0
1
0
0
1
1
0
1
2
3
†
‡
All other combinations are reserved.
See timing requirements for minimum valid read latencies based on maximum frequency rating.
Figure 1. Mode-Register Programming
9
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TMS626162
524288 BY 16-BIT BY 2-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY
SMOS683E – FEBRUARY 1995 – REVISED APRIL 1997
refresh
The ’626162 must be refreshed at intervals not exceeding t
(see timing requirements) or data cannot be
REF
retained. Refresh can be accomplished by performing a read or write access to every row in both banks, 4096
auto-refresh (REFR) commands, or by placing the device in self-refresh mode. Regardless of the method used,
refresh must be accomplished before t
has expired.
REF
auto refresh (REFR)
Before performing a REFR, both banks must be deactivated (placed in precharge). To enter a REFR command,
RAS and CAS must be low and W must be high upon the rising edge of CLK (see Table 1). The refresh address
is generated internally such that, after 4096 REFR commands, both banks of the ’626162 have been refreshed.
The external address and bank select (A11) are ignored. The execution of a REFR command automatically
deactivates both banks upon completion of the internal auto-refresh cycle, allowing consecutive REFR-only
commands to be executed, if desired, without any intervening DEAC commands. The REFR commands do not
necessarily have to be consecutive, but all 4096 must be completed before t
expires.
REF
self refresh (SLFR)
To enter self refresh, both banks of the ’626162 must be deactivated and then a self-refresh (SLFR) command
must be executed (see Table 2). The SLFR command is identical to the REFR command, except that CKE is
low. For proper entry of the SLFR command, CKE is brought low for the same rising edge of CLK that RAS and
CAS are low and W is high. CKE must be held low to stay in self-refresh mode. In the self-refresh mode, all
refreshing signals are generated internally for both banks with all external signals (except CKE) being ignored.
Data is retained by the device automatically for an indefinite period when power is maintained, and power
consumption is reduced to a minimum. To exit self-refresh mode, CKE must be brought high. New commands
are issued after t
has expired. If CLK is made inactive during self refresh, it must be returned to an active and
RC
stable condition before CKE is brought high to exit self refresh (see Figure 21).
Upon exiting self refresh, the device must begin the normal-refresh scheme immediately. If the burst-refresh
scheme is used, then 4096 REFR commands must be executed before continuing with normal device
operations. If a distributed-refresh scheme utilizing auto refresh is used (for example, two rows every 32 µs),
the first set of refreshes must be performed before continuing with normal device operation. This ensures that
the SDRAM is fully refreshed.
interrupted bursts
A read burst or write burst can be interrupted before the burst sequence has been completed with no adverse
effects to the operation. This is accomplished by entering certain superseding commands as listed in Table 7
and Table 8, provided that all timing requirements are met. A DEAC command is considered an interrupt only
if it is issued to the same bank as the preceding READ or WRT command. The interruption of READ-P orWRT-P
operations is not supported.
10
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TMS626162
524288 BY 16-BIT BY 2-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY
SMOS683E – FEBRUARY 1995 – REVISED APRIL 1997
interrupted bursts (continued)
Table 7. Read-Burst Interruption
INTERRUPTING
COMMAND
EFFECT OR NOTE ON USE DURING READ BURST
Current output cycles continue until the programmed latency from the superseding-READ (READ-P) command is met
and new output cycles begin (see Figure 2).
READ, READ-P
WRT, WRT-P
DEAC, DCAB
STOP
TheWRT (WRT-P)commandimmediatelysupersedesthereadburstinprogress. Toavoiddatacontention, DQMxmust
be held high before the WRT (WRT-P) command to mask output of the read burst on cycles (n
CCD
-1), n , and
CCD
(n
CCD
+1), assuming that there is any output on these cycles (see Figure 3).
TheDQbusisinthehigh-impedancestatewhenn
occurs first (see Figure 4).
cyclesaresatisfiedorwhenthereadburstcompletes, whichever
HZP
TheDQ busisinthehigh-impedancestatewhenn
occurs first. The bank remains active. A new read or write command cannot be entered for at least two cycles after the
STOP command (see Figure 5).
cyclesaresatisfiedorwhenthereadburstcompletes, whichever
BSD
n
CCD
= One Cycle
CLK
Output Burst for the
Interrupting READ
Command Begins Here
READ Command
at Column Address C0
Interrupting
READ Command
at Column Address C1
DQ
C0
C1
C1 + 1
C1 + 2
a) INTERRUPTED ON ODD CYCLES
n
CCD
= Two Cycles
CLK
Interrupting
READ Command
at Column Address C1
READ Command
at Column Address C0
Output Burst for the
Interrupting READ
Command Begins Here
DQ
C0
C0 + 1
C1
C1 + 1
b) INTERRUPTED ON EVEN CYCLES
NOTE A: For these examples, assume CAS latency = 3, and burst length = 4.
Figure 2. Read Burst Interrupted by Read Command
11
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TMS626162
524288 BY 16-BIT BY 2-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY
SMOS683E – FEBRUARY 1995 – REVISED APRIL 1997
interrupted bursts (continued)
n
CCD
= Five Cycles
CLK
Interrupting
READ Command
WRT Command
DQ
Q
D
D
See Note B
DQMx
NOTES: A. For the purposes of this example, assume CAS latency = 3, and burst length = 4.
B. DQMx must be high to mask output of the read burst on cycles (n – 1), n
, and (n
CCD CDD
+ 1).
CCD
Figure 3. Read Burst Interrupted by Write Command
n
CCD
= Two Cycles
n
HZP
CLK
Interrupting
DEAC/DCAB
Command
READ Command
DQ
Q
Q
NOTE A: For this example, assume CAS latency = 3 and burst length = 4.
Figure 4. Read Burst Interrupted by DEAC Command
n
CCD
= Two Cycles
n
BSD
CLK
Interrupting
STOP Command
READ Command
DQ
NEW Command
Q
NOTE A: For this example, assume CAS latency = 3 and burst length = 4.
Figure 5. Read Burst Interrupt by STOP Command
12
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524288 BY 16-BIT BY 2-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY
SMOS683E – FEBRUARY 1995 – REVISED APRIL 1997
interrupted bursts (continued)
Table 8. Write-Burst Interruption
INTERRUPTING
COMMAND
EFFECT OR NOTE ON USE DURING WRITE BURST
READ, READ-P
WRT, WRT-P
Data in on previous cycle is written. No further data in is accepted (see Figure 6).
The new WRT (WRT-P) command and data in immediately supersede the write burst in progress
(see Figure 7).
The DEAC/DCAB command immediately supersedes the write burst in progress. DQMx must be used to
DEAC, DCAB
STOP
mask the DQ bus so that an interrupt does not violate the write-recovery specification (t
) (see Figure 8).
WR
The data on the input pins at the time of the burst-STOP command is not written; no further data is accepted.
The bank remains active. A new read or write command cannot be entered for at least n
STOP command (see Figure 9).
cycles after the
BSD
n
CCD
= One Cycle
CLK
WRT
Command
READ
Command
DQ
D
Q
Q
Q
a) INTERRUPTED ON ODD CYCLES
= Two Cycles
n
CCD
CLK
WRT Command
READ Command
DQ
D
D
Q
Q
b) INTERRUPTED ON EVEN CYCLES
NOTE A: For these examples, assume CAS latency = 3, burst length = 4.
Figure 6. Write Burst Interrupted by Read Command
13
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TMS626162
524288 BY 16-BIT BY 2-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY
SMOS683E – FEBRUARY 1995 – REVISED APRIL 1997
interrupted bursts (continued)
n
CCD
= Two Cycles
CLK
WRT Command
at Column
Address C0
Interrupting
WRT Command
at Column Address C1
C0
C0 + 1
C1
C1 + 1
C1 + 2
C1 + 3
DQ
NOTE A: For this example, assume burst length = 4.
Figure 7. Write Burst Interrupted by Write Command
n
CCD
= Three Cycles
CLK
WRT Command
Interrupting
DEAC or DCAB
Command
Ignored
DQ
D
D
Ignored
t
WR
DQMx
NOTE A: For this example, assume burst length = 4.
Figure 8. Write Burst Interrupted by DEAC/DCAB Command
n
CCD
= Two Cycles
n
BSD
CLK
WRT Command
Interrupting
STOP Command
New Command
Ignored
DQ
D
D
Ignored
NOTE A: For this example, assume burst length = 4.
Figure 9. Write Burst Interrupted by STOP Command
14
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TMS626162
524288 BY 16-BIT BY 2-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY
SMOS683E – FEBRUARY 1995 – REVISED APRIL 1997
power up
Device initialization should be performed after a power up to the full V
level. After power is established, a
CC
200-µs interval is required (with no inputs other than CLK). After this interval, both banks of the device must be
deactivated. Eight REFR commands must be performed, and the mode register must be set to complete the
device initialization.
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
Supply voltage range for output drivers, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 4.6 V
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 4.6 V
CCQ
Voltage range on any pin (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 4.6 V
Short-circuit output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 W
Operating free-air temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
A
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to V
.
SS
recommended operating conditions
MIN
3
NOM
3.3
3.3
0
MAX
3.6
UNIT
V
V
V
V
V
V
V
Supply voltage
CC
CCQ
SS
Supply voltage for output drivers
Supply voltage
3
3.6
V
V
Supply voltage for output drivers
High-level input voltage
0
V
SSQ
IH
2
– 0.3
0
V
+ 0.3
V
CC
0.8
70
Low-level input voltage (see Note 2)
Operating free-air temperature
V
IL
T
A
°C
NOTE 2:
V
IL
MIN = 1.5 V ac (pulsewidth
5 ns)
15
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
electrical characteristics over recommended ranges of supply voltage and free-air temperature (unless otherwise noted)
(see Note 3)
†
’626162-12A
’626162-12
PARAMETER
TEST CONDITIONS
UNIT
MIN
MAX
MIN
MAX
V
V
High-level output voltage
Low-level output voltage
Input current (leakage)
Output current (leakage)
I
I
= –2 mA
= 2 mA
2.4
2.4
V
OH
OH
0.4
±10
±10
85
105
2
0.4
±10
±10
80
105
2
V
OL
OL
I
I
0 V ≤ V ≤ V
+ 0.3 V,
All other pins = 0 V to V
CC
µA
I
CC
I
O
0 V ≤ V ≤ V
+ 0.3 V, Output disabled
µA
O
CC
CAS latency = 2
CAS latency = 3
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
µA
Burst length = 1, t
t
MIN
RC
RC
= 0 mA, one bank activated (see Note 4)
I
Operating current
CC1
I
/I
OH OL
I
I
I
I
I
I
I
I
CKE
V
MAX, t
= 15 ns (see Note 5)
CC2P
Precharge standby current in power-down
mode
IL
CK
MAX, t = ∞ (see Note 6)
CK
CKE & CLK
V
2
2
CC2PS
CC2N
IL
MIN, t
CK
CKE
CKE
V
V
= 15 ns (see Note 5)
30
2
30
2
Precharge standby current in
non-power-down mode
IH
IL
CC2NS
CC3P
MAX, t
= 15 ns (see Note 5)
8
8
Precharge standby current in power-down
mode
CK
MAX, t
CKE & CLK
V
= ∞ (see Note 6)
8
8
CC3PS
CC3N
IL
MIN, t
CK
= 15 ns (see Note 5)
CKE
CKE
V
V
35
10
140
170
75
85
2
35
10
130
170
70
85
2
Precharge standby current in
non-power-down mode
IH
IH
CK
MIN, CLK
V
MAX t
= ∞ (see Note 6)
CC3NS
IL
CK
CAS latency = 2
CAS latency = 3
CAS latency = 2
CAS latency = 3
Page burst, I
OH OL
All banks activated, n
/I
= 0 mA
I
Burst current
CC4
= one cycle (see Note 7)
CCD
I
I
Auto-refresh current
Self-refresh current
t
t
MIN
CC5
RC
RC
CKE
V
MAX
CC6
IL
†
–12A-speed device is supported only at –5/+10% V
CC
.
NOTES: 3. All specifications apply to the device after power-up initialization. All control and address inputs must be stable and valid.
4. Control, DQ, and address inputs change state only twice during t
.
RC
5. Control, DQ, and address inputs change state only once every 30 ns.
6. Control, DQ, and address inputs do not change (stable).
7. Control, DQ, and address inputs change state only once every cycle.
TMS626162
524288 BY 16-BIT BY 2-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY
SMOS683E – FEBRUARY 1995 – REVISED APRIL 1997
capacitance over recommended ranges of supply voltage and operating free-air temperature,
f = 1 MHz (see Note 8)
MIN
MAX
UNIT
pF
C
C
C
C
Input capacitance, CLK input
5
5
5
8
i(S)
i(AC)
i(E)
o
Input capacitance, address and control inputs: A0–A11, CS, DQMx, RAS, CAS, W
Input capacitance, CKE input
pF
pF
Output capacitance
pF
NOTE 8:
V
CC
= 3.3 ± 0.3 V and bias on pins under test is 0 V.
ac timing requirements over recommended ranges of supply voltage and operating free-air
†‡
temperature
§
’626162-12A
’626162-12
UNIT
PARAMETER
MIN MAX
MIN MAX
t
t
t
t
t
t
t
t
t
t
t
t
t
Cycle time, CLK
Cycle time, CLK
CAS latency = 2
CAS latency = 3
15
18
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CK2
CK3
CH
12
12
Pulse duration, CLK high
4
4
Pulse duration, CLK low
4
4
CL
Access time, CLK high to data out (see Note 9)
Access time, CLK high to data out (see Note 9)
Hold time, CLK high to data out
CAS latency = 2
CAS latency = 3
9
10
AC2
AC3
OH
LZ
9
9
3
3
Delay time, CLK high to DQ in low-impedance state (see Note 10)
3
3
Delay time, CLK high to DQ in high-impedance state (see Note 11)
Setup time, address, control, and data input
10
10
HZ
3
3
IS
Hold time, address, control, and data input
1
1.5
IH
Power down/self-refresh exit time (see Note 12)
Delay time, ACTV command to DEAC or DCAB command
10
10
CESP
RAS
60 100000
72 100000
Delay time, ACTV, MRS, REFR, or SLFR to ACTV, MRS, REFR, or SLFR
command
t
t
90
30
108
30
ns
ns
RC
Delay time ACTV command to READ, READ-P, WRT, or WRT-P command
(see Note 13)
RCD
t
t
t
t
t
t
t
Delay time, DEAC or DCAB command to ACTV, MRS, REFR, or SLFR command
Delay time, ACTV command in one banki to ACTV command in the other bank
Delay time, MRS command to ACTV, MRS, REFR, or SLFR command
Final data out of READ-P operation to ACTV, MRS, SLFR, or REFR command
Final data in of WRT-P operation to ACTV, MRS, SLFR, or REFR command
Delay time, final data in of WRT operation to DEAC or DCAB command
Transition time
30
24
24
36
24
24
ns
ns
ns
ns
ns
ns
ns
RP
RRD
RSA
APR
APW
WR
T
t
– (CL –1)
t
RP
* CK
60
15
1
60
20
1
5
5
†
‡
§
See Parameter Measurement Information for load circuits.
All references are made to the rising transition of CLK, unless otherwise noted.
–12A-speed device is supported only at –5/+10% V
.
CC
is referenced from the rising transition of CLK that is previous to the data-out cycle. For example, the first data out t
NOTES: 9. t
is
AC
AC
referenced from the rising transition of CLK that is CAS latency – one cycle after the READ command. An access time is measured
at output reference level 1.4 V.
10.
11.
t
is measured from the rising transition of CLK that is CAS latency – one cycle after the READ command.
MAX defines the time at which the outputs are no longer driven and is not referenced to output voltage levels.
LZ
t
HZ
12. See Figure 20 and Figure 21.
13. For read or write operations with automatic deactivate, t
must be set to satisfy minimum t
.
RAS
RCD
17
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TMS626162
524288 BY 16-BIT BY 2-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY
SMOS683E – FEBRUARY 1995 – REVISED APRIL 1997
ac timing requirements over recommended ranges of supply voltage and operating free-air
†‡
temperature (continued)
§
’626162-12A
’626162-12
UNIT
PARAMETER
MIN
MAX
MIN
MAX
t
Refresh interval
64
64
ms
REF
n
n
n
n
n
n
Delay time, READ or WRT command to an interrupting command
Delay time, CS low or high to input enabled or inhibited
1
0
1
1
0
2
1
0
1
1
0
2
cycle
cycle
cycle
cycle
cycle
cycle
CCD
CDD
CLE
CWL
DID
0
1
0
1
Delay time, CKE high or low to CLK enabled or disabled
Delay time, final data in of WRT operation to READ, READ-P, WRT, or WRT-P
Delay time, ENBL or MASK command to enabled or masked data in
Delay time, ENBL or MASK command to enabled or masked data out
Delay time, DEAC or DCAB, command to DQ in high-impedance
0
2
0
2
DOD
n
n
CAS latency = 2
2
3
2
3
cycle
cycle
HZP2
HZP3
state
Delay time, DEAC or DCAB, command to DQ in high-impedance
state
CAS latency = 3
n
n
Delay time, WRT command to first data in
0
0
1
0
0
1
cycle
cycle
WCD
Delay time, STOP command to READ or WRT command
BSD
†
‡
§
See Parameter Measurement Information for load circuits.
All references are made to the rising transition of CLK, unless otherwise noted.
–12A-speed device is supported only at –5/+10% V
.
CC
18
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TMS626162
524288 BY 16-BIT BY 2-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY
SMOS683E – FEBRUARY 1995 – REVISED APRIL 1997
PARAMETER MEASUREMENT INFORMATION
general information for ac timing measurements
The ac timing measurements are based on signal rise and fall times equal to 1 ns (t = 1 ns) and a midpoint
T
reference level of 1.4 V for LVTTL. For signal rise and fall times greater than 1 ns, the reference level should
be changed to V MIN and V MAX instead of the midpoint level. All specifications referring to READ
IH
IL
commands are also valid for READ-P commands unless otherwise noted. All specifications referring to WRT
commands are also valid for WRT-P commands unless otherwise noted. All specifications referring to
consecutive commands are specified as consecutive commands for the same bank unless otherwise noted.
1.4 V
R
C
= 50 Ω
L
L
Z
O
= 50 Ω
Output
Under Test
= 50 pF
Figure 10. LVTTL-Load Circuit
t
CK
t
CH
CLK
t
T
t
CL
t
iS
t
T
t
iH
DQ, A0–A11, CS, RAS,
CAS, W, DQMx, CKE
t
T
t
iH
t
, t
iS CESP
DQ, A0–A11, CS, RAS,
CAS, W, DQMx, CKE
t
T
Figure 11. Input-Attribute Parameters
19
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TMS626162
524288 BY 16-BIT BY 2-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY
SMOS683E – FEBRUARY 1995 – REVISED APRIL 1997
PARAMETER MEASUREMENT INFORMATION
CAS latency
CLK
t
ACTV
READ
AC
Command
Command
t
HZ
t
LZ
t
OH
DQ
Figure 12. Output Parameters
READ, WRT
DESL
READ, READ-P, WRT, WRT-P, DEAC, DCAB
Command Disable
n
CCD
n
t
CDD
ACTV
DEAC, DCAB
RAS
ACTV, REFR, SELF-REFRESH EXIT
ACTV, MRS, REFR, SLFR
READ, READ-P, WRT, WRT-P
ACTV, MRS, REFR, SLFR
ACTV (different bank)
ACTV, MRS
t
RC
ACTV
DEAC, DCAB
ACTV
t
t
RCD
t
RP
RRD
MRS
t
RSA
Figure 13. Command-to-Command Parameters
n
HZP
CLK
DEAC or
DCAB
Command
READ
Command
t
HZ
DQ
Q
Q
Q
NOTE A: For this example, assume CAS latency = 3, and burst length = 4.
Figure 14. Read Followed by Deactivate
20
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TMS626162
524288 BY 16-BIT BY 2-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY
SMOS683E – FEBRUARY 1995 – REVISED APRIL 1997
PARAMETER MEASUREMENT INFORMATION
t
APR
CLK
DQ
ACTV, MRS,
REFR, or SLFR
Command
READ-P
Command
Final Data Out
Q
NOTE A: For this example, assume CAS latency = 3, and burst length = 1.
Figure 15. Read With Auto-Deactivate
n
CWL
t
WR
CLK
DQ
DEAC or DCAB
Command
WRT
Command
WRT
Command
D
D
NOTE A: For this example, assume burst length = 1.
Figure 16. Write Followed By Deactivate
n
CWL
t
APW
CLK
DQ
ACTV, MRS,
REFR, or SLFR
Command
WRT
Command
WRT-P
Command
D
D
Figure 17. Write With Auto-Deactivate
21
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS626162
524288 BY 16-BIT BY 2-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY
SMOS683E – FEBRUARY 1995 – REVISED APRIL 1997
PARAMETER MEASUREMENT INFORMATION
n
DOD
t
RWL
n
DOD
CLK
DEAC or
DCAB
Command
WRT
Command
READ
Command
DQ
Q
D
Ignored
MASK
Ignored
Ignored
ENBL
MASK
MASK
MASK
ENBL
MASK
Command
Command
Command
Command
Command
Command Command
DQMx
NOTE A: For this example, assume CAS latency = 3, and burst length = 4.
Figure 18. DQ Masking
n
CLE
n
CLE
CLK
DQ
DQ
DQ
DQ
DQ
t
iS
t
iS
t
iH
t
iH
CKE
Figure 19. CLK-Suspend Operation
22
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS626162
524288 BY 16-BIT BY 2-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY
SMOS683E – FEBRUARY 1995 – REVISED APRIL 1997
PARAMETER MEASUREMENT INFORMATION
CLK
Last Data-In
WRT
(WRT-P)
Operation
Exit
Power-Down
ModeIft
Is
CESP
Satisfied (New
Command)
CLK Is
Don’t Care,
But Must Be
Stable
Before CKE
High
Last
Data-Out
READ
(READ-P)
Operation
Enter
Power-Down
Mode
CKE
CLK
t
t
iH
CESP
t
iS
DESL or
NOOP
Last Data-In
WRT
Command
(WRT-P)
Operation
Only If t
CESP
Is Not
CLK Is
Don’t Care,
But Must Be
Stable
Before CKE
High
Satisfied
Last
Data-Out
READ
(READ-P)
Operation
Exit Power-Down
Mode (New
Command)
Enter
Power-Down
Mode
CKE
t
iH
t
CESP
t
iS
Figure 20. Power-Down Operation
23
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS626162
524288 BY 16-BIT BY 2-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY
SMOS683E – FEBRUARY 1995 – REVISED APRIL 1997
PARAMETER MEASUREMENT INFORMATION
CLK
Exit SLFR
if t Is
SLFR Command
ACTV, MRS,
or REFR
Command
CLK Is Don’t
Care, But
Must
CESP
Satisfied
Both Banks
Deactivated
Be Stable
Before
CKE high
DESL or NOOP
Command
Only Until
tRC Is Satisfied
CKE
t
RC
t
CESP
t
iH
t
iS
CLK
SLFR Command
t NotYet
CESP
Satisfied
Exit
SLFR
ACTV, MRS,
or REFR
Command
CLK is Don’t
Care, But
Must
Both Banks
Deactivated
Be Stable
Before
CKE High
DESL or
NOOP
Only Until
tRC Is
Satisfied
CKE
t
RC
t
CESP
t
iH
t
iS
Figure 21. Self-Refresh Operation
24
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
ACTV T
READ T
DEAC T
CLK
DQ
a
b
c
d
DQMx
RAS
CAS
W
A10
R0
R0
A11
A0–A9
CS
C0
CKE
BURST
TYPE
†
BURST CYCLE
BANK
ROW
(D/Q)
(B/T)
ADDR
a
b
c
d
Q
T
R0
C0
C0 + 1
C0 + 2
C0 + 3
†
Column-address sequence depends on programmed burst type and starting column address C0 (see Table 5).
NOTE A: This example illustrates minimum t for the ’626162-12 at 83 MHz.
RCD
Figure 22. Read Burst (CAS latency = 3, burst length = 4)
ACTV T
WRT T
DEAC T
CLK
DQ
a
b
c
d
e
f
g
h
DQMx
RAS
CAS
W
R0
R0
A10
A11
C0
A0–A9
CS
CKE
BURST
TYPE
†
BURST CYCLE
BANK
ROW
(D/Q)
(B/T)
ADDR
a
b
c
d
e
f
g
h
D
T
R0
C0
C0 + 1
C0 + 2
C0 + 3
C0 + 4
C0 + 5
C0 + 6
C0 + 7
†
Column-address sequence depends on programmed burst type and starting column address C0 (see Table 6).
NOTE A: This example illustrates minimum t and t for the ’626162-12 at 83 MHz.
RCD
WR
Figure 23. Write Burst (burst length = 8)
ACTV B
WRT B
READ B
DEAC B
CLK
DQ
a
b
c
d
DQMx
RAS
CAS
W
A10
R0
R0
A11
A0–A9
CS
C0
C1
CKE
BURST
TYPE
†
BANK
ROW
BURST CYCLE
(D/Q)
(B/T)
ADDR
a
b
c
d
D
Q
B
B
R0
R0
C0
C0 + 1
C1
C1 + 1
†
Column-address sequence depends on programmed burst type and starting column address C0 and C1 (see Table 4).
NOTE A: This example illustrates minimum t for the ’626162-12 at 83 MHz.
RCD
Figure 24. Write-Read Burst (CAS latency = 3, burst length = 2)
ACTV T
READ T
WRT-P T
i
CLK
DQ
a
b
c
d
e
f
g
h
j
k
l
m
n
o
p
DQMx
RAS
CAS
W
A10
R0
R0
A11
A0–A9
CS
C0
C1
CKE
BURST
TYPE
†
BURST CYCLE
BANK
ROW
(D/Q)
(B/T)
ADDR
a
b
c
d
e
f
g
h
i
j
k
l
m
n
o
p
Q
D
T
T
R0
R0
C0
C0+1 C0+2 C0+3 C0+4 C0+5 C0+6 C0+7
C1
C1+1 C1+2 C1+3 C1+4 C1+5 C1+6 C1+7
†
Column-address sequence depends on programmed burst type and starting column address C0 and C1 (see Table 6).
NOTE A: This example illustrates minimum t for the ’626162-12 at 83 MHz.
RCD
Figure 25. Read-Write Burst With Automatic Deactivate (CAS latency = 3, burst length = 8)
ACTV T
READ T
WRT-P T
i
CLK
DQ
a
b
c
d
e
f
g
h
DQMx
RAS
CAS
W
A10
R0
R0
A11
A0–A9
CS
C0
C1
CKE
BURST
TYPE
†
f
BANK
(B/T)
ROW
BURST CYCLE
(D/Q)
ADDR
a
b
c
d
e
g
h
i
Q
D
T
T
R0
R0
C0
C0+1 C0+2 C0+3 C0+4 C0+5 C0+6 C0+7
C1
†
Column-address sequence depends on programmed burst type and starting column address C0 and C1 (see Table 6).
NOTE A: This example illustrates minimum t for the ’626162-12 at 83 MHz.
RCD
Figure 26. Read Burst – Single Write With Automatic Deactivate (CAS latency = 3, burst length = 8)
ACTV B
READ-P B
CLK
DQ0–DQ15
DQMx
RAS
n
n+1
n+2
n+3
n+4
n+5
n+6
n+7
n+8
n+9 n+10 n+11 n+12 n+13 n+14
n+253 n+254 n+255
CAS
W
A10
R0
R0
A11
A0–A9
CS
C0
CKE
BURST
BANK ROW
BURST CYCLE
TYPE
(D/Q)
Q
(B/T) ADDR
R0
a
b
c
d
e
f
g
h
i
j
k
l
m
n
o
p
q
r
s
.
.
†
B
C0 C0+1 C0+2 C0+3 C0+4 C0+5 C0+6 C0+7
255
†
Column-address sequence depends on programmed burst type and starting column address C0.
NOTE A: This example illustrates minimum t for the ’626162-12 at 83 MHz.
RCD
Figure 27. Read Burst – Full Page (CAS latency = 3, burst length = 256)
ACTV T
READ-P T
ACTV T
ACTV B
READ-P B
ACTV B
READ-P B
CLK
DQ
a
b
c
d
e
f
g
h
i
j
k
l
m
n
o
p
q
r
s
DQMx
RAS
CAS
W
R0
R0
R1
R1
R2
R2
R3
R3
A10
A11
C0
C1
C2
A0–A9
CS
CKE
BURST
TYPE
†
BURST CYCLE
BANK ROW
(B/T) ADDR
(D/Q)
a
b
c
d
e
f
g
h
i
j
k
l
m
n
o
p
q
r
s
.
.
Q
Q
Q
B
T
B
R0
R1
R2
C0 C0+1 C0+2 C0+3 C0+4 C0+5 C0+6 C0+7
C1 C1+1 C1+2 C1+3 C1+4 C1+5 C1+6 C1+7
C2 C2+1 C2+2
.
.
†
Column-address sequence depends on programmed burst type and starting column address C0, C1, and C2 (see Table 6).
NOTE A: This example illustrates minimum t for the ’626162-12 at 83 MHz.
RCD
Figure 28. Two-Bank Row-Interleaving Read Bursts With Automatic Deactivate (CAS latency = 3, burst length = 8)
ACTV T
READ T
READ T
ACTV B
READ B
READ B
READ B
CLK
DQ
a
b
c
d
e
f
DQMx
RAS
CAS
W
A10
R0
R0
R1
R1
A11
A0–A9
CS
C0
C1
C2
C3
C4
CKE
BURST
TYPE
†
BURST CYCLE
BANK
(B/T)
ROW
(D/Q)
ADDR
a
b
c
d
e
f
. . .
. . .
Q
Q
Q
.
B
T
B
R0
R1
R0
. . .
C0
C0 + 1
C1
C1 + 1
C2
C2 + 1
. . .
. . .
. . .
†
Column-address sequence depends on programmed burst type and starting column address C0, C1, and C2 (see Table 4).
Figure 29. Two-Bank Column-Interleaving Read Bursts (CAS latency = 3, burst length = 2)
ACTV T
WRT T
DEAC T
ACTV B
READ B
DEAC B
CLK
DQ
a
b
c
d
e
f
g
h
DQMx
RAS
CAS
W
A10
R0
R0
R1
R1
A11
A0–A9
CS
C0
C1
CKE
BURST
TYPE
†
BURST CYCLE
BANK
(B/T)
ROW
(D/Q)
ADDR
a
b
c
d
e
f
g
h
Q
D
B
T
R0
R1
C0
C0 +1
C0 + 2
C0 + 3
C1
C1 + 1
C1 +2
C1+ 3
†
Column-address sequence depends on programmed burst type and starting column address C0 and C1. (Refer to Table 5.)
NOTE A: This example illustrates minimum t and t for the ’626162-12 at 83 MHz.
RCD
WR
Figure 30. Read-Burst Bank B, Write-Burst Bank T (CAS latency = 3, burst length = 4)
ACTV T
WRT-P T
ACTV B
READ-P B
CLK
DQ
a
b
c
d
e
f
g
DQMx
RAS
CAS
W
R0
R0
R1
R1
A10
A11
A0–A9
CS
C0
C1
CKE
BURST
TYPE
†
BANK
(B/T)
ROW
BURST CYCLE
(D/Q)
ADDR
a
C0
b
c
d
e
f
g
h
D
Q
T
B
R0
R1
C0 +1
C0 + 2
C0 + 3
C1
C1 + 1
C1 + 2
C1 + 3
†
Column-address sequence depends on programmed burst type and starting column address C0 and C1 (see Table 5).
NOTE A: This example illustrates minimum n for the ’626162-12 at 83 MHz.
CWL
Figure 31. Write-Burst Bank T, Read-Burst Bank B With Automatic Deactivate (CAS latency = 3, burst length = 4)
ACTV T
READ T
WRT T
e
DCAB
CLK
DQ
g
a
b
c
d
f
h
DQMx
RAS
CAS
W
R0
R0
A10
A11
C0
C1
A0–A9
CS
CKE
BURST
TYPE
†
BURST CYCLE
BANK
(B/T)
ROW
(D/Q)
ADDR
a
b
c
d
e
f
g
h
Q
D
T
T
R0
R1
C0
C0+1
C0+2
C0+3
C1
C1+1
C1+2
C1+3
†
Column-address sequence depends on programmed burst type and starting column address C0 and C1 (see Table 5).
NOTE A: This example illustrates minimum t for the ’626162-12 at 83 MHz.
RCD
Figure 32. Data Mask (CAS latency = 3, burst length = 4)
ACTV B
ACTV T
READ B
READ T
READ B
READ T
READ B
CLK
DQ0–DQ7
a
b
c
d
e
f
DQML
High Impedance
DQ8–DQ15
DQMU
RAS
CAS
W
R0
R0
R1
R1
A10
A11
A0–A9
CS
C0
C1
C2
C3
C4
CKE
BURST
TYPE
†
BURST CYCLE
BANK
(B/T)
ROW
(D/Q)
ADDR
a
b
c
d
e
f
g
h
Q
Q
Q
Q
T
B
T
B
R0
R1
R0
R1
C0
C0+1
C1
C1+1
C2
C1+1
C3
C3+1
†
Column-address sequence depends on programmed burst type and starting column address C0 and C1 (see Table 4).
Figure 33. Data Mask With Byte Control (CAS latency = 3, burst length = 2)
ACTV T
ACTV B
READ B
DEAC B
WRT T
e
DEAC T
CLK
DQ0–DQ7
DQML
f
g
h
a
b
c
d
DQ8–DQ15
DQMU
RAS
CAS
W
A10
R0
R0
R1
R1
A11
A0–A9
CS
C0
C1
CKE
BURST
TYPE
†
BURST CYCLE
BANK
(B/T)
ROW
(D/Q)
ADDR
a
b
c
d
e
f
g
h
Q
D
T
B
R0
R1
C0
C0+1
C0+2
C0+3
C1
C1+1
C1+2
C1+3
†
Column-address sequence depends on programmed burst type and starting column address C0 and C1 (see Table 5).
NOTE A: This example illustrates minimum t read burst, and a minimum t write burst for the ’626162-12 at 83 MHz
RCD
WR
Figure 34. Data Mask With Byte Control (CAS latency = 3, burst length = 4)
ACTV T
READ T
ACTV B
c
WRT B
DCAB
CLK
DQ0–DQ7
DQML
b
b
a
a
d
d
f
f
h
h
c
e
g
DQ8–DQ15
DQMU
RAS
CAS
W
R0
R0
R1
R1
A10
A11
C0
C1
A0–A9
CS
CKE
BURST
TYPE
†
BURST CYCLE
BANK
(B/T)
ROW
(D/Q)
ADDR
a
b
c
d
e
f
g
h
Q
D
T
B
R0
R1
C0
C0+1
C0+2
C0+3
C1
C1+1
C1+2
C1+3
†
Column-address sequence depends on programmed burst type and starting column address C0 and C1 (see Table 5).
NOTE A: This example illustrates minimum t and t for the ’626162-12 at 83 MHz.
RCD
WR
Figure 35. Data Mask With Cycle-by-Cycle Byte Control (CAS latency = 3, burst length = 4)
REFR
ACTV T
READ T
DEAC T
b
REFR
CLK
DQ
a
c
d
DQMx
RAS
CAS
W
R0
R0
A10
A11
A0–A9
CS
C0
CKE
BURST
TYPE
BANK
ROW
BURST CYCLE†
(D/Q)
(B/T)
ADDR
a
b
c
d
Q
T
R0
C0
C0+1
C0+2
C0+3
†
Column-address sequence depends on programmed burst type and starting column address C0 (see Table 5).
NOTE A: This example illustrates minimuim t and t for the ’626162-12 at 83 MHz.
RC
RCD
Figure 36. Refresh Cycles (CAS latency = 3, burst length = 4)
DCAB
MRS
ACTV B
WRT-P B
CLK
DQ
a
b
c
d
DQMx
RAS
CAS
W
R0
R0
A10
See Note B
See Note B
See Note B
A11
A0–A9
C0
CS
CKE
BURST
TYPE
†
BANK
ROW
BURST CYCLE
(D/Q)
(B/T)
ADDR
a
b
c
d
D
B
R0
C0
C0+1
C0+2
C0+3
†
Column-address sequence depends on programmed burst type and starting column address C0 (see Table 5).
NOTES: A. This example illustrates minimum t , t , and t for the ’626162-12 at 83 MHz.
RP RSA
RCD
B. Refer to Figure 1.
Figure 37. Set Mode Register (deactivate all, set mode register, write burst with automatic deactivate)
(CAS latency = 2, burst length = 4)
ACTV T
READ T
WRT-P T
HOLD
PDE
HOLD
b
CLK
DQ0
a
d
e
f
g
h
c
DQMx
RAS
CAS
W
R0
R0
A10
A11
C1
C0
A0–A9
CS
CKE
BURST-
TYPE
BANK
(B/T)
ROW
BURST CYCLE†
(D/Q)
ADDR
a
b
c
d
e
f
g
h
Q
D
T
T
R0
R1
C0
C0+1
C0+2
C0+3
C1
C1+1
C1+2
C1+3
†
Column-address sequence depends on programmed burst type and starting column address C0 and C1 (see Table 5).
Figure 38. CLK Suspend (HOLD) During Read Burst and Write Burst (CAS latency = 3, burst length = 4)
TMS626162
524288 BY 16-BIT BY 2-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY
SMOS683E – FEBRUARY 1995 – REVISED APRIL 1997
device symbolization
TI
-SS
Speed Code (-12A, -12)
Package Code
TMS626162 DGE
W
B
Y
M
LLLL
P
Assembly Site Code
Lot Traceability Code
Month Code
Year Code
Die Revision Code
Wafer Fab Code
42
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS626162
524288-WORD BY 16-BIT BY 2-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY
SMOS683E – FEBRUARY 1995 – REVISED APRIL 1997
MECHANICAL DATA
DGE (R-PDSO-G50)
PLASTIC SMALL-OUTLINE PACKAGE
0.018 (0,45)
0.006 (0,16)
M
0.031 (0,80)
50
0.012 (0,30)
26
0.471 (11,96)
0.455 (11,56)
0.404 (10,26)
0.396 (10,06)
1
25
0.006 (0,15) NOM
0.829 (21,05)
0.821 (20,85)
Gage Plane
0.010 (0,25)
0°–5°
0.024 (0,60)
0.016 (0,40)
Seating Plane
0.004 (0,10)
0.047 (1,20) MAX
0.000 (0,00) MIN
4040070-5/C 12/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion.
43
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
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Copyright 1998, Texas Instruments Incorporated
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