TMS626812A-10 [TI]
2MX8 SYNCHRONOUS DRAM, PDSO44, 0.400 INCH, PLASTIC, TSOP-44;
| 型号： | TMS626812A-10 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 2MX8 SYNCHRONOUS DRAM, PDSO44, 0.400 INCH, PLASTIC, TSOP-44 动态存储器 光电二极管 内存集成电路 |
| 文件： | 总40页 (文件大小：561K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TMS626812
1048576 BY 8-BIT BY 2-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY
SMOS687A –JULY 1996 – REVISED APRIL 1997
Organization . . . 1M × 8 × 2 Banks
DGE PACKAGE
( TOP VIEW )
3.3-V Power Supply (±10% Tolerance)
Two Banks for On-Chip Interleaving
(Gapless Accesses)
1
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
V
V
SS
DQ7
CC
2
DQ0
High Bandwidth – Up to 83-MHz Data Rates
3
V
V
SSQ
DQ6
SSQ
DQ1
CAS Latency Programmable to 2 or 3
Cycles From Column-Address Entry
4
5
V
V
CCQ
DQ5
CCQ
DQ2
Burst Sequence Programmable to Serial or
Interleave
6
7
V
V
SSQ
DQ4
SSQ
DQ3
Burst Length Programmable to 1, 2, 4, or 8
8
Chip Select and Clock Enable for
Enhanced-System Interfacing
9
V
V
CCQ
CCQ
NC
10
11
12
13
14
15
16
17
18
19
20
21
22
NC
NC
DQM
CLK
CKE
NC
A9
Cycle-by-Cycle DQ-Bus Mask Capability
Auto-Refresh and Self-Refresh Capability
4K Refresh (Total for Both Banks)
NC
W
CAS
RAS
CS
High-Speed, Low-Noise Low-Voltage TTL
(LVTTL) Interface
Power-Down Mode
A11
A10
A0
A8
Compatible With JEDEC Standards
Pipeline Architecture
A7
A1
A6
Temperature Ranges
Operating, 0°C to 70°C
Storage, – 55°C to 150°C
A2
A5
A3
A4
V
V
SS
CC
Performance Ranges:
SYNCHRONOUS
CLOCK CYCLE
TIME
ACCESS TIME
CLOCK TO
OUTPUT
REFRESH
INTERVAL
PIN NOMENCLATURE
A0–A10 Address Inputs
t
t
t
t
CK2
CK3
CK2
CK3
(CL = 3) (CL = 2) (CL = 3) (CL = 2)
A0–A10 Row Addresses
A0–A8 Column Addresses
A10 Automatic-Precharge Select
Bank Select
Column-Address Strobe
Clock Enable
†
’626812-12A
12 ns
12 ns
15 ns
18 ns
9 ns
9 ns
9 ns
64 ms
64 ms
’626812-12
10 ns
†
A11
CAS
CKE
CLK
CS
–12A speed device is supported only at –5/+10% V
CC
description
System Clock
Chip Select
The TMS626812 is a high-speed 16777216-bit
synchronous dynamic random access memory
(SDRAM) device organized as two banks of
1048576 words with eight bits per word.
DQ0–DQ7
SDRAM Data Input/Output
Data/Output Mask Enable
No External Connect
DQM
NC
RAS
Row-Address Strobe
Power Supply (3.3-V Typ)
Power Supply for Output Drivers (3.3-V Typ)
Ground
Ground for Output Drivers
Write Enable
V
V
V
V
CC
CCQ
SS
SSQ
All inputs and outputs of the TMS626812 series
are compatible with the LVTTL interface.
W
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 1997, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS626812
1048576 BY 8-BIT BY 2-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY
SMOS687A –JULY 1996 – REVISED APRIL 1997
description (continued)
The SDRAM employs state-of-the-art technology for high performance, reliability, and low power. All inputs and
outputs are synchronized with the CLK input to simplify system design and enhance use with high-speed
microprocessors and caches.
The TMS626812 SDRAM is available in a 400-mil, 44-pin surface-mount TSOP package (DGE suffix).
functional block diagram
CLK
CKE
AND
Array Bank T
CS
DQM
RAS
CAS
W
DQ
Buffer
Control
DQ0–DQ7
8
Array Bank B
A0–A11
12
Mode Register
operation
All inputs of the ’626812 SDRAM are latched on the rising edge of the system (synchronous) clock. The outputs,
DQ0–DQ7, also are referenced to the rising edge of CLK. The ’626812 has two banks that are accessed
independently. A bank must be activated before it can be accessed (read from or written to). Refresh cycles
refresh both banks alternately.
Five basic commands or functions control most operations of the ’626812:
Bank activate/row-address entry
Column-address entry/write operation
Column-address entry/read operation
Bank deactivate
Auto-refresh
Self-refresh
Additionally, operations can be controlled by three methods: using chip select (CS) to select/deselect the
devices, using DQM to enable/mask the DQ signals on a cycle-by-cycle basis, or using CKE to suspend (or
gate) the CLK input. The device contains a mode register that must be programmed for proper operation.
Table 1 through Table 3 show the various operations that are available on the ’626812. These truth tables
identify the command and/or operations and their respective mnemonics. Each truth table is followed by a
legend that explains the abbreviated symbols. An access operation refers to any read or write command in
progress at cycle n. Access operations include the cycle upon which the read or write command is entered and
all subsequent cycles through the completion of the access burst.
2
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS626812
1048576 BY 8-BIT BY 2-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY
SMOS687A –JULY 1996 – REVISED APRIL 1997
operation (continued)
†
Table 1. Basic-Command Truth Table
STATE OF
BANK(S)
‡
COMMAND
CS
RAS
CAS
W
A11
A10
A9–A0
MNEMONIC
A9 = V
A8–A7 = 0
A6–A0 = V
T = deac
B = deac
Mode register set
L
L
L
L
X
X
MRS
Bank deactivate (precharge)
Deactivate all banks
X
L
L
L
L
L
L
H
H
H
L
L
L
BS
X
L
H
V
L
X
X
V
V
DEAC
DCAB
ACTV
WRT
X
Bank activate/row-address entry
Column-address entry/write operation
SB = deac
SB = actv
L
H
L
BS
BS
H
Column-address entry/write operation
with automatic deactivate
SB = actv
SB = actv
SB = actv
L
L
L
H
H
H
L
L
L
L
H
H
BS
BS
BS
H
L
V
V
V
WRT-P
READ
Column-address entry/read operation
Column-address entry/read operation
with automatic deactivate
H
READ-P
No operation
X
X
L
H
X
H
X
H
X
X
X
X
X
X
X
NOOP
DESL
Control-input inhibit /no operation
H
T = deac
B = deac
§
Auto-refresh
L
L
L
H
X
X
X
REFR
†
For exception of these commands on cycle n:
– CKE(n–1) must be high, or
– t
– t
– t
must be satisfied for power-down exit, or
CESP
CESP
CES
and t
and n
must be satisfied for self-refresh exit, or
must be satisfied for clock-suspend exit.
RC
CLE
DQM(n) is a don’t care.
‡
§
All other unlisted commands are considered vendor-reserved commands or illegal commands.
Auto-refresh or self-refresh entry requires that all banks be deactivated or in an idle state prior to the command entry.
Legend:
n
L
H
X
V
T
B
actv
deac
BS
SB
=
=
=
=
=
=
=
=
=
=
=
CLK cycle number
Logic low
Logic high
Don’t care, either logic low or logic high
Valid
Bank T
Bank B
Activated
Deactivated
Logic high to select bank T; logic low to select bank B
Bank selected by A11 at cycle n
3
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS626812
1048576 BY 8-BIT BY 2-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY
SMOS687A –JULY 1996 – REVISED APRIL 1997
operation (continued)
†
Table 2. Clock-Enable (CKE) Command Truth Table
CKE
(n–1)
CKE
(n)
CS
(n)
RAS
(n)
CAS
(n)
W
(n)
‡
COMMAND
STATE OF BANK(S)
MNEMONIC
SLFR
T = deac
B = deac
Self-refresh entry
H
H
L
L
L
L
L
H
X
¶
¶
T = no access operation
B = no access operation
§
Power-down entry on cycle (n+1)
Self-refresh exit
X
X
X
PDE
L
L
H
H
L
H
X
H
X
H
X
—
—
T = self refresh
B = self refresh
H
T = power down
B = power down
#
Power-down exit
L
H
L
H
L
X
X
X
X
X
X
X
X
X
X
X
X
—
HOLD
—
¶
¶
T = access operation
B = access operation
CLK suspend on cycle (n+1)
¶
¶
T = access operation
B = access operation
CLK suspend exit on cycle (n+1)
H
†
‡
§
¶
For execution of these commands, A0–A11 (n) and DQM (n) are don’t cares.
All other unlisted commands are considered vendor-reserved commands or illegal commands.
On cycle n, the device executes the respective command (listed in Table 1). On cycle (n+1), the device enters power-down mode.
A bank is no longer in an access operation one cycle after the last data-out cycle of a read operation, and two cycles after the last data-in cycle
of a write operation. Neither the PDE nor the HOLD command is allowed on the cycle immediately following the last data-in cycle of a write
operation.
#
If setup time from CKE high to the next CLK high satisfies t
, the device executes the respective command (listed in Table 1). Otherwise,
CESP
either DESL or NOOP command must be applied before any other command.
Legend:
n
L
H
X
T
B
deac
=
=
=
=
=
=
=
CLK cycle number
Logic low
Logic high
Don’t care, either logic low or logic high
Bank T
Bank B
Deactivated
4
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS626812
1048576 BY 8-BIT BY 2-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY
SMOS687A –JULY 1996 – REVISED APRIL 1997
operation (continued)
†
Table 3. Data-Mask (DQM) Command Truth Table
DQM
(n)
DATA IN
DATA OUT
(n+2)
‡
COMMAND
STATE OF BANK(S)
MNEMONIC
(n)
T = deac
and
B = deac
—
—
X
N/A
Hi-Z
Hi-Z
—
T = actv
and
B = actv
X
N/A
—
§
(no access operation)
T = write
or
B = write
Data-in enable
Data-in mask
L
H
L
V
N/A
N/A
V
ENBL
MASK
ENBL
MASK
T = write
or
B = write
M
T = read
or
B = read
Data-out enable
Data-out mask
N/A
N/A
T = read
or
H
Hi-Z
B = read
†
For exception of these commands on cycle n:
– CKE(n–1) must be high, or
– t
– t
– t
must be satisfied for power-down exit, or
CESP
CESP
CES
and t
must be satisfied for self-refresh exit, or
must be satisfied for clock-suspend exit.
RC
and n
CLE
CS(n), RAS(n), CAS(n), W(n), and A0–A11(n) are don’t cares.
‡
§
All other unlisted commands are considered vendor-reserved commands or illegal commands.
A bank is no longer in an access operation one cycle after the last data-out cycle of a read operation, and two cycles after the last data-in cycle
of a write operation. Neither the PDE nor the HOLD command is allowed on the cycle immediately following the last data-in cycle of a write
operation.
Legend:
n
L
H
X
V
M
N/A
T
B
actv
deac
write
read
=
=
=
=
=
=
=
=
=
=
=
=
=
CLK cycle number
Logic low
Logic high
Don’t care, either logic low or logic high
Valid
Masked input data
Not applicable
Bank T
Bank B
Activated
Deactivated
Activated and accepting data inputs on cycle n
Activated and delivering data outputs on cycle (n + 2)
5
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS626812
1048576 BY 8-BIT BY 2-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY
SMOS687A –JULY 1996 – REVISED APRIL 1997
burst sequence
All data for the ’626812 are written or read in a burst fashion that is, a single starting address is entered into the
device and the ’626812 internally accesses a sequence of locations based on that starting address. After the
first access, some subsequent accesses can be at preceding as well as succeeding column addresses,
depending on the starting address entered. This sequence can be programmed to follow either a serial burst
or an interleave burst (see Table 4 through Table 6). The length of the burst can be programmed to be 1, 2, 4,
or 8 accesses (see the section on setting the mode register, page 9). After a read burst is complete (as
determined by the programmed-burst length), the outputs are in the high-impedance state until the next read
access is initiated.
Table 4. 2-Bit Burst Sequences
INTERNAL COLUMN ADDRESS A0
DECIMAL
BINARY
START
2ND
START
2ND
0
1
0
1
1
0
1
0
0
1
0
1
1
0
1
0
Serial
Interleave
Table 5. 4-Bit Burst Sequences
INTERNAL COLUMN ADDRESS A1–A0
DECIMAL BINARY
START
2ND
3RD
2
4TH
3
START
00
2ND
3RD
10
11
4TH
11
0
1
2
3
0
1
2
3
1
2
3
0
1
0
3
2
01
10
11
00
01
00
11
10
3
0
01
00
01
10
11
Serial
0
1
10
00
01
10
11
1
2
11
2
3
00
3
2
01
10
01
00
Interleave
0
1
10
00
01
1
0
11
6
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS626812
1048576 BY 8-BIT BY 2-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY
SMOS687A –JULY 1996 – REVISED APRIL 1997
burst sequence (continued)
Table 6. 8-Bit Burst Sequences
INTERNAL COLUMN ADDRESS A2–A0
DECIMAL
BINARY
START 2ND 3RD 4TH 5TH 6TH 7TH 8TH START 2ND 3RD 4TH 5TH 6TH 7TH 8TH
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
1
2
3
4
5
6
7
0
1
0
3
2
5
4
7
6
2
3
4
5
6
7
0
1
2
3
0
1
6
7
4
5
3
4
5
6
7
0
1
2
3
2
1
0
7
6
5
4
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
5
6
7
0
1
2
3
4
5
4
7
6
1
0
3
2
6
7
0
1
2
3
4
5
6
7
4
5
2
3
0
1
7
0
1
2
3
4
5
6
7
6
5
4
3
2
1
0
000
001
010
011
100
101
110
111
000
001
010
011
100
101
110
111
001
010
011
100
101
110
111
000
001
000
011
010
101
100
111
110
010 011 100 101 110 111
011 100 101 110 111 000
100 101 110 111 000 001
101 110 111 000 001 010
Serial
110
111
111 000 001 010 011
000 001 010 011 100
000 001 010 011 100 101
001 010 011 100 101 110
010 011 100 101 110 111
011 010 101 100 111 110
000 001 110 111 100 101
001 000 111 110 101 100
Interleave
110
111
111 000 001 010 011
110 001 000 011 010
100 101 010 011 000 001
101 100 011 010 001 000
latency
The beginning data-out cycle of a read burst can be programmed to occur two or three CLK cycles after the read
command (see the section on setting the mode register, page 9). This feature allows adjustment of the device
so that it operates using the capability to latch the data output from the ’626812. The delay between the READ
command and the beginning of the output burst is known as CAS latency. After the initial output cycle begins,
the data burst occurs at the CLK frequency without any intervening gaps. Use of minimum read latencies is
restricted, based on the maximum frequency rating of the ’626812.
There is no latency for data-in cycles (write latency). The first data-in cycle of a write burst is entered at the same
rising edge of CLK on which the WRT command is entered. The write latency is fixed and is not determined by
the mode-register contents.
two-bank operation
The ’626812 contains two independent banks that can be accessed individually or in an interleaved fashion.
Eachbank must be activated with a row address before it can be accessed. Each bank must then be deactivated
before it can be activated again with a new row address. The bank-activate/row-address-entry command
(ACTV) is entered by holding RAS low, CAS high, W high, and A11 valid on the rising edge of CLK. A bank can
be deactivated either automatically during a READ-P or a WRT-P command or by use of the deactivate-bank
(DEAC) command. Both banks can be deactivated at once by use of the DCAB command (see Table 1 and the
section on bank deactivation description, page 8).
7
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS626812
1048576 BY 8-BIT BY 2-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY
SMOS687A –JULY 1996 – REVISED APRIL 1997
two-bank row-access operation
The two-bank feature allows access of information on random rows at a higher rate of operation than is possible
with a standard DRAM by activating one bank with a row address and, while the data stream is being accessed
to/from that bank, activating the second bank with another row address. When the data stream to or from the
first bank is completed, the data stream to or from the second bank can begin without interruption. After the
second bank is activated, the first bank can be deactivated to allow the entry of a new row address for the next
round of accesses. In this manner, operation can continue in an interleaved fashion. Figure 24 shows an
example of two-bank row-interleaving read bursts with automatic deactivate for a CAS latency of 3 and burst
length of 8.
two-bank column-access operation
The availability of two banks allows the access of data from random starting columns between banks at a higher
rate of operation. After activating each bank with a row address (ACTV command), A11 can be used to alternate
READ or WRT commands between the banks to provide gapless accesses at the CLK frequency, provided all
specified timing requirements are met. Figure 25 is an example of two-bank column interleaving read bursts
for a CAS latency of three and burst length of two.
bank deactivation (precharge)
Both banks can be simultaneously deactivated (placed in precharge) by using the DCAB command. A single
bank can be deactivated by using the DEAC command. The DEAC command is entered identically to the DCAB
command except that A10 must be low and A11 used to select the bank to be precharged as shown in
Table 1. A bank can also be deactivated automatically by using A10 during a read or write command. If A10 is
held high during the entry of a read or write command, the accessed bank (selected by A11) is automatically
deactivated upon completion of the access burst. If A10 is held low during the entry of a read or write command,
that bank remains active following the burst. The read and write commands with automatic deactivation are
signified as READ-P and WRT-P.
chip select (CS)
CS can be used to select or deselect the ’626812 for command entry, which might be required for multiple
memory-device decoding. If CS is held high on the rising edge of CLK (DESL command), the device does not
respond to RAS, CAS, or W until the device is selected again by holding CS low on the rising edge of CLK. Any
other valid command can be entered simultaneously on the same rising CLK edge of the select operation. The
device can be selected/deselected on a cycle-by-cycle basis (see Table 1 and Table 2). The use of CS does
not affect an access burst that is in progress; the DESL command can restrict only RAS, CAS, and W inputs
to the ’626812.
data mask
The MASK command or its opposite, the data-in enable (ENBL) command (see Table 3), is performed on a
cycle-by-cycle basis to gate any data cycle within a read burst or a write burst. The application of DQM to a write
bursthasnolatency(n
=0cycle), buttheapplicationofDQMtoareadbursthasalatencyofn
=2cycles.
DID
DOD
During a write burst, if DQM is held high on the rising edge of CLK, the data input is ignored on that cycle. During
a read burst, if DQM is held high on the rising edge of CLK, then n cycles after that rising edge of CLK, the
DOD
data output is in the high-impedance state. Figure 16 and Figure 28 show examples of data-mask operations.
CLK suspend/power-down mode
For normal device operation, CKE should be held high to enable CLK. If CKE goes low during the execution
of a READ (READ-P) or WRT (WRT-P) operation, the state of the DQ bus at the immediate next rising edge
of CLK is frozen at its current state, and no further inputs are accepted until CKE returns high. This is known
8
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS626812
1048576 BY 8-BIT BY 2-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY
SMOS687A –JULY 1996 – REVISED APRIL 1997
CLK suspend/power-down mode (continued)
asaCLK-suspendoperationanditsexecutionindicatesaHOLDcommand. Thedeviceresumesoperationfrom
the point when it was placed in suspension, beginning with the second rising edge of CLK after CKE returns
high.
If CKE is brought low when no read or write command is in progress, the device enters power-down mode. If
both banks are deactivated when power-down mode is entered, power consumption is reduced to the minimum.
Power-down mode can be used during row-active or auto-refresh periods to reduce input buffer power. After
power-down mode is entered, no further inputs are accepted until CKE returns high. To ensure that data in the
device remains valid during the power-down mode, the self-refresh command (SLFR) must be executed
concurrently with the power-down entry (PDE) command. When exiting power-down mode, new commands
can be entered on the first CLK edge after CKE returns high, provided that the setup time (t
) is satisfied.
CESP
Table 2 shows the command configuration for a CLK suspend/power-down operation. Figure 17, Figure 18,
and Figure 31 show an example of the procedure.
setting the mode register
The ’626812 contains a mode register that must be programmed with the CAS latency, the burst type, and the
burst length. This is accomplished by executing a mode-register set (MRS) command with the information
enteredonaddresslinesA0–A9. Alogic0mustbeenteredonA7andA8, butA10andA11aredon’t-careentries
for the ’626812. When A9=1, the write-burst length is always 1. When A9=0, the write-burst length is defined
by A0–A2. Figure 1 shows the valid combinations for a successful MRS command. Only valid addresses allow
the mode register to be changed. If the addresses are not valid, the previous contents of the mode register
remain unaffected. The MRS command is executed by holding RAS, CAS, and W low, and the input-mode word
valid on A0–A9 on the rising edge of CLK (see Table 1). The MRS command can be executed only when both
banks are deactivated.
A11
A10
A9
A8
0
A7
0
A6
A5
A4
A3
A2
A1
A0
Reserved
0 = Serial
1 = Interleave
(burst type)
†
§
REGISTER BITS
REGISTER BITS
REGISTER
BIT A9
WRITE-BURST
LENGTH
CAS
‡
BURST
LENGTH
LATENCY
A6
A5
A4
A2
A1
A0
0
0
0
0
0
0
1
1
0
1
0
1
1
2
4
8
0
1
A2–A0
1
0
0
1
1
0
1
2
3
†
‡
§
All other combinations are reserved.
Refer to timing requirements for
minimum valid-read latencies based
on maximum frequency rating.
All other combinations are reserved
.
Figure 1. Mode-Register Programming
9
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TMS626812
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SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY
SMOS687A –JULY 1996 – REVISED APRIL 1997
refresh
The ’626812 must be refreshed at intervals not exceeding t
(see timing requirements) or data cannot be
REF
retained. Refresh can be accomplished by performing a read or write access to every row in both banks, by
performing 4096 auto-refresh (REFR) commands, or by placing the device in self-refresh mode. Regardless
of the method used, refresh must be accomplished before t
has expired.
REF
Auto-refresh (REFR)
Before performing a REFR, both banks must be deactivated (placed in precharge). To enter a REFR command,
RAS and CAS must be low and W must be high upon the rising edge of CLK (see Table 1). The refresh address
is generated internally such that after 4096 REFR commands, both banks of the ’626812 have been refreshed.
The external address and bank select (A11) are ignored. The execution of a REFR command automatically
deactivates both banks upon completion of the internal auto-refresh cycle allowing consecutive REFR-only
commands to be executed, if desired, without any intervening DEAC commands. The REFR commands do not
necessarily have to be consecutive, but all 4096 must be completed before t
expires.
REF
self refresh (SLFR)
To enter self refresh, both banks of the ’626812 first must be deactivated and a SLFR command must be
executed (see Table 2). The SLFR command is identical to the REFR command except that CKE is low. For
proper entry of the SLFR command, CKE is brought low for the same rising edge of CLK that RAS and CAS
are low and W is high. CKE must be held low to stay in self-refresh mode. In the self-refresh mode, all refreshing
signals are generated internally for both banks with all external signals (except CKE) being ignored. Data is
retained by the device automatically for an indefinite period when power is maintained and power consumption
is reduced to a minimum. To exit self-refresh mode, CKE must be brought high. New commands are issued after
t
has expired. If CLK is made inactive during self refresh, it must be returned to an active and stable condition
RC
before CKE is brought high to exit self refresh (see Figure 19).
Upon exiting self refresh, the device must begin the normal refresh scheme immediately. If the burst-refresh
scheme is used, 4096 REFR commands must be executed before continuing with normal device operations.
If a distributed-refresh scheme utilizing auto-refresh is used (for example, two rows every 32 µs), the first set
of refreshes must be performed before continuing with normal device operation. This ensures that the SDRAM
is fully refreshed.
interrupted bursts
A read burst or write burst can be interrupted before the burst sequence has been completed with no adverse
effects to the operation. This is accomplished by entering certain superseding commands as listed in Table 7
and Table 8, provided that all timing requirements are met. A DEAC command is considered an interrupt only
if it is issued to the same bank as the preceding READ or WRT command. The interruption of READ-P orWRT-P
operations is not supported.
10
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interrupted bursts (continued)
Table 7. Read-Burst Interruption
INTERRUPTING
COMMAND
EFFECT OR NOTE ON USE DURING READ BURST
Current output cycles continue until the programmed latency from the superseding READ (READ-P) command is
met and new output cycles begin (see Figure 2).
READ, READ-P
WRT, WRT-P
DEAC, DCAB
The WRT (WRT-P) command immediately supersedes the read burst in progress. To avoid data contention, DQM
must be high before the WRT (WRT-P) command to mask output of the read burst on cycles (n
CCD
–1), n , and
CCD
(n
CCD
+1) assuming that there is any output on these cycles. (see Figure 3).
The DQ bus is in the high-impedance state when n
whichever occurs first (see Figure 4).
cycles are satisfied or when the read burst completes,
HZP
n
CCD
= One Cycle
CLK
Output Burst for the
Interrupting READ
Command Begins Here
READ Command
at Column Address C0
Interrupting
READ Command
at Column Address C1
DQ
C0
C1
C1 + 1
C1 + 2
a) INTERRUPTED ON ODD CYCLES
n
CCD
= Two cycles
CLK
Interrupting
READ Command
at Column Address C1
READ Command
at Column Address C0
Output Burst for the
Interrupting READ
Command Begins Here
DQ
C0
C0 + 1
C1
C1 + 1
b) INTERRUPTED ON EVEN CYCLES
NOTE A: For these examples assume CAS latency = 3, and burst length = 4.
Figure 2. Read Burst Interrupted by Read Command
11
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interrupted bursts (continued)
n
CCD
= Five Cycles
CLK
Interrupting
READ Command
WRT Command
DQ
Q
D
D
See Note B
DQM
NOTES: A. For this example, assume CAS latency = 3 and burst length = 4.
B. DQM must be high to mask output of the read burst on cycles (n
– 1), n
, and (n + 1).
CCD
CCD
CCD
Figure 3. Read Burst Interrupted by Write Command
n
CCD
= Two Cycles
n
HZP
CLK
Interrupting
DEAC/DCAB
Command
READ Command
Q
Q
DQ
NOTE A: For this example, assume CAS latency = 3 and burst length = 4.
Figure 4. Read Burst Interrupted by DEAC Command
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interrupted bursts (continued)
Table 8. Write-Burst Interruption
INTERRUPTING
COMMAND
EFFECT OR NOTE ON USE DURING WRITE BURST
READ, READ-P
WRT, WRT-P
Data in on the previous cycle is written; however no further data in is accepted (see Figure 5).
The new WRT (WRT-P) command and data in immediately supersede the write burst in progress (see Figure 6).
The DEAC/DCAB command immediately supersedes the write burst in progress. DQM must be used to mask the
DEAC, DCAB
DQ bus such that the write recovery specification (t
WR
) is not violated by the interrupt (see Figure 7).
n
CCD
= One Cycle
CLK
WRT
Command
READ
Command
DQ
D
Q
Q
Q
a) INTERRUPTED ON ODD CYCLES
n
CCD
= Two Cycles
CLK
WRT Command
READ Command
DQ
D
D
Q
Q
b) INTERRUPTED ON EVEN CYCLES
NOTE A: For these examples assume CAS latency = 3, burst length = 4.
Figure 5. Write Burst Interrupted by Read Command
13
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interrupted bursts (continued)
n
CCD
= Two Cycles
CLK
WRT Command
at Column
Interrupting
WRT Command
Address C0
at Column Address C1
C0
C0 + 1
C1
C1 + 1
C1 + 2
C1 + 3
DQ
NOTE A: For this example, assume burst length = 4.
Figure 6. Write Burst Interrupted by Write Command
n
CCD
= Three Cycles
CLK
WRT Command
Interrupting
DEAC or DCAB
Command
Ignored
DQ
D
D
Ignored
t
WR
DQM
NOTE A: For this example assume burst length = 4.
Figure 7. Write Burst Interrupted by DEAC/DCAB Command
power up
Device initialization should be performed after a power up to the full V
level. After power is established, a
CC
200-µs interval is required (with no inputs other than CLK). After this interval, both banks of the device must be
deactivated. Eight REFR commands must be performed and the mode register must be set to complete the
device initialization.
14
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TMS626812
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SMOS687A –JULY 1996 – REVISED APRIL 1997
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
Supply voltage range for output drivers, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 4.6 V
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 4.6 V
CCQ
Voltage range on any pin (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 4.6 V
Short-circuit output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 W
Operating free-air temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
A
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to V
.
SS
recommended operating conditions
MIN
NOM
MAX
UNIT
V
V
V
V
V
V
Supply voltage
3
3
3.3
3.3
0
3.6
3.6
V
V
CC
CCQ
SS
Supply voltage for output drivers
Supply voltage
V
Supply voltage for output drivers
High-level input voltage
0
V
SSQ
IH
2
– 0.3
0
V
+ 0.3
V
CC
Low-level input voltage (see Note 2)
Operating free-air temperature
0.8
70
V
IL
T
A
°C
NOTE 2:
V
IL
MIN = –1.5 V AC (pulse width
5 ns)
15
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electrical characteristics over recommended ranges of supply voltage and free-air temperature (unless otherwise noted)
(see Note 3)
’626812-12A
’626812-12
PARAMETER
TEST CONDITIONS
UNIT
MIN
MAX
MIN
MAX
V
V
High-level output voltage
Low-level output voltage
Input current (leakage)
Output current (leakage)
I
I
= –2 mA
= 2 mA
2.4
2.4
V
OH
OH
0.4
±10
±10
85
95
2
0.4
±10
±10
75
95
2
V
OL
OL
I
I
0 V ≤ V ≤ V
+ 0.3 V,
All other pins = 0 V to V
Output disabled
µA
µA
mA
mA
mA
mA
mA
I
CC
CC
I
O
0 V ≤ V ≤ V
+ 0.3 V,
O
CC
CAS latency = 2
CAS latency = 3
Burst length = 1, t
t
MIN
RC
RC
= 0 mA, 1 bank activated (see Note 4)
I
Operating current
CC1
I
/I
OH OL
I
I
I
CKE
V
MAX, t
= 15 ns (see Note 5)
CC2P
CC2PS
CC2N
Precharge standby current in power down
mode
IL
CK
MAX, t
CKE & CLK
V
= infinity (see Note 6)
2
2
IL
MIN, t
CK
= 15 ns (see Note 5)
CKE
CKE
V
V
30
30
IH
IH
CK
MIN, CLK
Precharge standby current in non-power
down mode
V
MAX, t
= infinity
CK
IL
I
2
2
mA
CC2NS
(see Note 6)
CKE MAX, t
CKE & CLK
I
I
I
V
= 15 ns (see Note 5)
8
8
8
8
mA
mA
mA
CC3P
CC3PS
CC3N
IL
CK
MAX, t
Active standby current in power down mode
V
= infinity (see Note 6)
IL
MIN, t
CK
= 15 ns (see Note 5)
CKE
CKE
V
V
35
35
IH
IH
CK
MIN, CLK
Active standby current in non-power down
mode
V
MAX, t
= infinity
CK
IL
I
10
10
mA
CC3NS
CC4
(see Note 6)
CAS latency = 2
CAS latency = 3
CAS latency = 2
CAS latency = 3
130
155
75
85
2
110
155
70
85
2
mA
mA
mA
mA
mA
Page burst, I
All banks activated, n
/I
OH OL
= 0 mA
= 1 cycle (see Note 7)
I
Burst current
CCD
I
I
Auto-refresh current
Self-refresh current
t
t MIN
RC
CC5
RC
CKE
V
MAX
CC6
IL
NOTES: 3. All specifications apply to the device after power-up initialization. All control and address inputs must be stable and valid.
4. Control, DQ, and address inputs change state only twice during t
.
RC
5. Control, DQ, and address inputs change state only once every 30 ns.
6. Control, DQ, and address inputs do not change (stable).
7. Control, DQ, and address inputs change state only once every cycle.
TMS626812
1048576 BY 8-BIT BY 2-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY
SMOS687A –JULY 1996 – REVISED APRIL 1997
capacitance over recommended ranges of supply voltage and operating free-air temperature,
f = 1 MHz (see Note 8)
MIN
MAX
UNIT
pF
C
C
C
C
Input capacitance, CLK
5
5
5
8
i(S)
i(AC)
i(E)
o
Input capacitance, A0–A11, CS, DQM, RAS, CAS, W
Input capacitance, CKE
pF
pF
Output capacitance
pF
NOTE 8:
V
CC
= 3.3 ± 0.3 V and bias on pins under test is 0 V.
ac timing requirements over recommended ranges of supply voltage and operating free-air
†‡
temperature
§
’626812-12A
’626812-12
UNIT
MIN MAX
MIN MAX
t
t
t
t
t
t
t
t
t
t
t
t
t
Cycle time, CLK, CAS latency = 2
15
18
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CK2
CK3
CH
Cycle time, CLK, CAS latency = 3
12
12
Pulse duration, CLK high
4
4
Pulse duration, CLK low
4
4
CL
Access time, CLK high to data out, CAS latency = 2 (see Note 9)
Access time, CLK high to data out, CAS latency = 2 (see Note 9)
Hold time, CLK high to data out
9
10
AC2
AC3
OH
LZ
9
9
3
3
Delay time, CLK high to DQ in low-impedance state (see Note 10)
Delay time, CLK high to DQ in high-impedance state (see Note 11)
Setup time, address, control, and data input
Hold time, address, control, and data input
Power down/self-refresh exit time (see Note 12)
Delay time, ACTV command to DEAC or DCAB command
3
3
10
10
HZ
3
3
IS
1
1.5
IH
10
10
CESP
RAS
60 100000
72 100000
Delay time, ACTV, MRS, REFR, or SLFR to ACTV, MRS, REFR, or SLFR
command
t
t
90
30
108
30
ns
ns
RC
Delay time, ACTV command to READ, READ-P, WRT, or WRT-P command
(see Note 13)
RCD
t
t
t
t
Delay time, DEAC or DCAB command to ACTV, MRS, REFR, or SLFR command
Delay time, ACTV command in one bank to ACTV command in the other bank
Delay time, MRS command to ACTV, MRS, REFR, or SLFR command
Final data out of READ-P operation to ACTV, MRS, SLFR, or REFR command
30
24
24
36
24
24
ns
ns
ns
ns
RP
RRD
RSA
APR
*
– (CL –1) t
CK
t
RP
†
See Parameter Measurement Information for load circuits.
‡
§
All references are made to the rising transition of CLK, unless otherwise noted.
–12A speed device is supplied only at – 5%/+ 10% V
CC
is referenced from the rising transition of CLK that is previous to the data-out cycle. For example, the first data out t
NOTES: 9. t
is
AC
AC
referenced from the rising transition of CLK0 that is CAS latency – one cycle after the READ command. An access time is measured
at output reference level 1.4 V.
10.
11.
t
is measured from the rising transition of CLK that is CAS latency – one cycle after the READ command.
MAX defines the time at which the outputs are no longer driven and is not referenced to output voltage levels.
LZ
t
HZ
12. See Figure 18 and Figure 19
13. For read or write operations with automatic deactivate, t
must be set to satisfy minimum t
.
RAS
RCD
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ac timing requirements over recommended ranges of supply voltage and operating free-air
†‡
temperature (continued)
’626812-12A
’626812-12
UNIT
MIN
60
15
1
MAX
MIN
60
20
1
MAX
t
t
t
t
Final data in of WRT-P operation to ACTV, MRS, SLFR, or REFR command
Delay time, final data in of WRT operation to DEAC or DCAB command
Transition time (see Note 14)
ns
APW
WR
T
ns
5
5
ns
Refresh interval
64
64
ms
REF
n
n
n
n
n
n
Delay time, READ or WRT command to an interrupting command
Delay time, CS low or high to input enabled or inhibited
Delay time, CKE high or low to CLK enabled or disabled
Delay time, final data in of WRT operation to READ, READ-P, WRT, WRT-P
Delay time, ENBL or MASK command to enabled or masked data in
Delay time, ENBL or MASK command to enabled or masked data out
1
0
1
1
0
2
1
0
1
1
0
2
cycle
cycle
cycle
cycle
cycle
cycle
CCD
CDD
CLE
CWL
DID
0
1
0
1
0
2
0
2
DOD
Delay time, DEAC or DCAB, command to DQ in high-impedance state,
CAS latency = 2
n
2
2
cycle
HZP2
Delay time, DEAC or DCAB, command to DQ in high-impedance state,
CAS latency = 3
n
n
3
0
3
0
cycle
cycle
HZP3
Delay time, WRT command to first data in
0
0
WCD
†
‡
See Parameter Measurement Information for load circuits.
All references are made to the rising transition of CLK, unless otherwise noted.
NOTE 14: Transition time, t , is measured between V and V
IH
.
IL
T
18
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TMS626812
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SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY
SMOS687A –JULY 1996 – REVISED APRIL 1997
PARAMETER MEASUREMENT INFORMATION
general information for ac timing measurements
The ac timing measurements are based on signal rise and fall times equal to 1 ns (t = 1 ns) and a midpoint
T
reference level of 1.4 V for LVTTL. For signal rise and fall times greater than 1 ns, the reference level should
be changed to V MIN and V MAX instead of the midpoint level. All specifications referring to READ
IH
IL
commands are also valid for READ-P commands unless otherwise noted. All specifications referring to WRT
commands are also valid for WRT-P commands unless otherwise noted. All specifications referring to
consecutive commands are specified as consecutive commands for the same bank unless otherwise noted.
1.4 V
R
C
= 50 Ω
L
L
Output
Under Test
Z
O
= 50 Ω
= 50 pF
Figure 8. LVTTL-Load Circuit
t
CK
t
CH
CLK
t
T
t
CL
t
IS
t
T
t
IH
DQ, A0–A11, CS, RAS,
CAS, W, DQM, CKE
t
T
t
IH
t
, t
IS CESP
DQ, A0–A11, CS, RAS,
CAS, W, DQM, CKE
t
T
Figure 9. Input-Attribute Parameters
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TMS626812
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SMOS687A –JULY 1996 – REVISED APRIL 1997
PARAMETER MEASUREMENT INFORMATION
CAS latency
CLK
t
ACTV
READ
AC
Command
Command
t
HZ
t
LZ
t
OH
DQ
Figure 10. Output Parameters
READ, WRT
DESL
READ, READ-P, WRT, WRT-P, DEAC, DCAB
Command Disable
n
CCD
n
t
CDD
ACTV
DEAC, DCAB
RAS
ACTV, REFR, SELF-REFRESH EXIT
ACTV, MRS, REFR, SLFR
READ, READ-P, WRT, WRT-P
ACTV, MRS, REFR, SLFR
ACTV (different bank)
ACTV, MRS
t
RC
ACTV
DEAC, DCAB
ACTV
t
t
RCD
t
RP
RRD
MRS
t
RSA
Figure 11. Command-to-Command Parameters
n
HZP
CLK
DEAC or
DCAB
Command
READ
Command
t
HZ
DQ
Q
Q
Q
NOTE A: For this example, assume CAS latency = 3, and burst length = 4.
Figure 12. Read Followed by Deactivate
20
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SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY
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PARAMETER MEASUREMENT INFORMATION
t
APR
CLK
DQ
ACTV, MRS,
REFR, or SLFR
Command
READ-P
Command
Final Data Out
Q
NOTE A: For this example, assume CAS latency = 3, and burst length = 1.
Figure 13. Read With Auto-Deactivate
n
CWL
t
WR
CLK
DQ
DEAC or DCAB
Command
WRT
Command
WRT
Command
D
D
NOTE A: For this example, assume burst length = 1.
Figure 14. Write Followed By Deactivate
n
CWL
t
APW
CLK
DQ
ACTV, MRS,
REFR, or SLFR
Command
WRT
Command
WRT-P
Command
D
D
Figure 15. Write With Auto-Deactivate
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PARAMETER MEASUREMENT INFORMATION
n
DOD
t
WR
n
DOD
CLK
DEAC or
DCAB
Command
WRT
Command
READ
Command
DQ
Q
D
Ignored
MASK
Ignored
Ignored
ENBL
MASK
MASK
MASK
ENBL
MASK
Command
Command
Command
Command
Command
Command Command
DQM
NOTE A: For this example assume CAS latency = 3, and burst length = 4.
Figure 16. DQ Masking
n
CLE
n
CLE
CLK
DQ
DQ
DQ
DQ
DQ
t
iS
t
iS
t
iH
t
iH
CKE
Figure 17. CLK-Suspend Operation
22
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TMS626812
1048576 BY 8-BIT BY 2-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY
SMOS687A –JULY 1996 – REVISED APRIL 1997
PARAMETER MEASUREMENT INFORMATION
CLK
Last Data-In
WRT
(WRT-P)
Operation
Exit
Power-Down
ModeIft
CESP
Is Satisfied
(New
CLK Is
Don’t Care,
But Must Be
Stable
Before CKE
High
Command)
Last
Data-Out
READ
(READ-P)
Operation
Enter
Power-Down
Mode
CKE
CLK
t
t
iH
CESP
t
iS
DESL or
NOOP
Last Data-In
WRT
Command
Only If t
Is Not
Satisfied
(WRT-P)
Operation
CESP
CLK Is
Don’t Care,
But Must Be
Stable
Before CKE
High
Last
Data-Out
READ
(READ-P)
Operation
Exit Power-Down
Mode (New
Enter
Power-Down
Mode
Command)
CKE
t
iH
t
CESP
t
iS
Figure 18. Power-Down Operation
23
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TMS626812
1048576 BY 8-BIT BY 2-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY
SMOS687A –JULY 1996 – REVISED APRIL 1997
PARAMETER MEASUREMENT INFORMATION
CLK
Exit SLFR
If t is
ACTV,
MRS, or
REFR
SLFR
Command
CESP
Satisfied
DESL or
NOOP
Command
Command
Both Banks
Deactivated
CLK Is
Don’t Care,
But Must
Be Stable
Before
Only Until t
Is Satisfied
RC
CKE
CKE High
t
RC
t
iH
t
iS
t
CESP
CLK
t
Not
Exit SLFR
ACTV, MRS, or
REFR Command
CESP
Yet
SLFR
Command
Satisfied
DESL or
Both Banks
Deactivated
NOOP
Command
Only Until t
Is Satisfied
CLK Is
Don’t Care,
But Must
Be Stable
Before
RC
CKE
CKE High
t
RC
t
iS
t
iH
t
CESP
Figure 19. Self-Refresh Operation
24
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
ACTV T
READ T
DEAC T
CLK
DQ
a
b
c
d
DQM
RAS
CAS
W
A10
R0
R0
A11
A0–A9
CS
C0
CKE
BURST
TYPE
†
BANK
ROW
BURST CYCLE
(D/Q)
(B/T)
ADDR
a
b
c
d
Q
T
R0
C0
C0 + 1
C0 + 2
C0 + 3
†
Column-address sequence depends on programmed burst type and starting column address C0 (see Table 5).
NOTE A: This example illustrates minimum t for the ’626812-12 at 83 MHz.
RCD
Figure 20. Read Burst (CAS latency = 3, burst length = 4)
ACTV T
WRT T
DEAC T
CLK
DQ
a
b
c
d
e
f
g
h
DQM
RAS
CAS
W
R0
R0
A10
A11
C0
A0–A9
CS
CKE
BURST
TYPE
†
BURST CYCLE
BANK
ROW
(D/Q)
(B/T)
ADDR
a
b
c
d
e
f
g
h
D
T
R0
C0
C0 + 1
C0 + 2
C0 + 3
C0 + 4
C0 + 5
C0 + 6
C0 + 7
†
Column-address sequence depends on programmed burst type and starting column address C0 (see Table 6).
NOTE A: This example illustrates minimum t for the ’626812-12 at 83 MHz.
RCD
Figure 21. Write Burst (burst length = 8)
ACTV B
WRT B
READ B
DEAC B
CLK
DQ
a
b
c
d
DQM
RAS
CAS
W
A10
R0
R0
A11
A0–A9
CS
C0
C1
CKE
BURST
TYPE
†
BANK
ROW
BURST CYCLE
(D/Q)
(B/T)
ADDR
a
b
c
d
D
Q
B
B
R0
R0
C0
C0 + 1
C1
C1 + 1
†
Column-address sequence depends on programmed burst type and starting column address C0 and C1 (see Table 4).
NOTE A: This example illustrates minimum t and n for the ’626812-12 at 83 MHz.
RCD
CWL
Figure 22. Write-Read Burst (CAS latency = 3, burst length = 2)
ACTV T
READ T
WRT-P T
i
CLK
DQ
a
b
c
d
e
f
g
h
j
k
l
m
n
o
p
DQM
RAS
CAS
W
A10
R0
R0
A11
A0–A9
CS
C0
C1
CKE
BURST
TYPE
†
BURST CYCLE
BANK
(B/T)
ROW
(D/Q)
ADDR
a
b
c
d
e
f
g
h
i
j
k
l
m
n
o
p
Q
D
T
T
R0
R0
C0
C0+1 C0+2 C0+3 C0+4 C0+5 C0+6 C0+7
C1
C1+1 C1+2 C1+3 C1+4 C1+5 C1+6 C1+7
†
Column-address sequence depends on programmed burst type and starting column address C0 and C1 (see Table 6).
NOTE A: This example illustrates minimum t for the ’626812-12 at 83 MHz.
RCD
Figure 23. Read-Write Burst With Automatic Deactivate (CAS latency = 3, burst length = 8)
ACTV T
READ-P T
ACTV T
ACTV B
READ-P B
ACTV B
READ-P B
CLK
DQ
a
b
c
d
e
f
g
h
i
j
k
l
m
n
o
p
q
r
s
DQM
RAS
CAS
W
R0
R0
R1
R1
R2
R2
R3
R3
A10
A11
C0
C1
C2
A0–A9
CS
CKE
BURST
TYPE
†
BURST CYCLE
BANK ROW
(B/T) ADDR
(D/Q)
a
b
c
d
e
f
g
h
i
j
k
l
m
n
o
p
q
r
s
.
.
Q
Q
Q
B
T
B
R0
R1
R2
C0 C0+1 C0+2 C0+3 C0+4 C0+5 C0+6 C0+7
C1 C1+1 C1+2 C1+3 C1+4 C1+5 C1+6 C1+7
C2 C2+1 C2+2
.
.
†
Column-address sequence depends on programmed burst type and starting column address C0, C1, and C2 (see Table 6).
NOTE A: This example illustrates minimum t for the ’626812-12 at 83 MHz.
RCD
Figure 24. Two-Bank Row-Interleaving Read Bursts With Automatic Deactivate (CAS latency = 3, burst length = 8)
ACTV T
READ T
READ T
ACTV B
READ B
READ B
READ B
CLK
DQ
a
b
c
d
e
f
DQM
RAS
CAS
W
A10
R0
R0
R1
R1
A11
A0–A9
CS
C0
C1
C2
C3
C4
CKE
BURST
TYPE
†
BURST CYCLE
BANK
(B/T)
ROW
(D/Q)
ADDR
a
b
c
d
e
f
. . .
. . .
Q
Q
Q
.
B
T
B
R0
R1
R0
. . .
C0
C0 + 1
C1
C1 + 1
C2
C2 + 1
. . .
. . .
. . .
†
Column-address sequence depends on programmed burst type and starting column addresses C0, C1 and C2 (see Table 4).
Figure 25. Two-Bank Column-Interleaving Read Bursts (CAS latency = 3, burst length = 2)
ACTV T
WRT T
DEAC T
ACTV B
READ B
DEAC B
CLK
DQ
a
b
c
d
e
f
g
h
DQM
RAS
CAS
W
A10
A11
R0
R0
R1
R1
C0
C1
A0–A9
CS
CKE
BURST
TYPE
†
BANK
(B/T)
ROW
BURST CYCLE
(D/Q)
ADDR
a
b
c
d
e
f
g
h
C1+ 3
Q
D
B
T
R0
R1
C0
C0 +1
C0 + 2
C0 + 3
C1
C1 + 1
C1 +2
†
Column-address sequence depends on programmed burst type and starting column addresses C0 and C1. (see Table 5).
NOTE A: This example illustrates a minimum t and t for the ’626812-12 at 83 MHz.
RCD
WR
Figure 26. Read-Burst Bank B, Write-Burst Bank T (CAS latency = 3, burst length = 4)
ACTV T
WRT-P T
ACTV B
READ-P B
CLK
DQ
a
b
c
d
e
f
g
DQM
RAS
CAS
W
R0
R0
R1
R1
A10
A11
A0–A9
CS
C0
C1
CKE
BURST
TYPE
†
BANK
(B/T)
ROW
BURST CYCLE
(D/Q)
ADDR
a
C0
b
c
d
e
f
g
h
D
Q
T
B
R0
R1
C0 +1
C0 + 2
C0 + 3
C1
C1 + 1
C1 + 2
C1 + 3
†
Column-address sequence depends on programmed burst type and starting column address C0 and C1 (see Table 5).
NOTE A: This example illustrates minimum n for the ’626812-12 at 83 MHz.
CWL
Figure 27. Write-Burst Bank T, Read-Burst Bank B With Automatic Deactivate (CAS latency = 3, burst length = 4)
ACTV T
READ T
WRT T
e
DCAB
CLK
DQ
g
a
b
c
d
f
h
DQM
RAS
CAS
W
R0
R0
A10
A11
C0
C1
A0–A9
CS
CKE
BURST
TYPE
†
BURST CYCLE
BANK
(B/T)
ROW
(D/Q)
ADDR
a
C0
b
c
d
e
f
g
h
C1+3
Q
D
T
T
R0
R1
C0+1
C0+2
C0+3
C1
C1+1
C1+2
†
Column-address sequence depends on programmed burst type and starting column address C0 and C1 (see Table 5).
NOTE A: This example illustrates minimum t for the ’626812-12 at 83 MHz.
RCD
Figure 28. Data Mask (CAS latency = 3, burst length = 4)
REFR
ACTV T
READ T
DEAC T
b
REFR
CLK
DQ
a
c
d
DQM
RAS
CAS
W
R0
R0
A10
A11
C0
A0–A9
CS
CKE
BURST
TYPE
BANK
ROW
BURST CYCLE†
(D/Q)
(B/T)
ADDR
a
b
c
d
Q
T
R0
C0
C0+1
C0+2
C0+3
†
Column-address sequence depends on programmed burst type and starting column address C0 (see Table 5).
NOTE A: This example illustrates minimuim t and t for the ’626812-12 at 83 MHz.
RC
RCD
Figure 29. Refresh Cycles (CAS latency = 3, burst length = 4)
DCAB
MRS
ACTV B
WRT-P B
CLK
DQ
a
b
c
d
DQM
RAS
CAS
W
R0
R0
A10
See Note B
See Note B
See Note B
A11
A0–A9
C0
CS
CKE
BURST
TYPE
†
BANK
ROW
BURST CYCLE
(D/Q)
(B/T)
ADDR
a
b
c
d
D
B
R0
C0
C0+1
C0+2
C0+3
†
Column-address sequence depends on programmed burst type and starting column address C0 (see Table 5).
NOTES: A. This example illustrates minimum t , t , and t for the ’626812-12 at 83 MHz.
RP RSA
RCD
B. Refer to Figure 1
Figure 30. Set Mode Register (deactivate all, set mode register, write burst with automatic deactivate)
(burst length = 4)
ACTV T
READ T
WRT-P T
HOLD
PDE
HOLD
b
CLK
DQ0
a
d
e
f
g
h
c
DQM
RAS
CAS
W
R0
R0
A10
A11
C1
C0
A0–A9
CS
CKE
BURST-
TYPE
†
BURST CYCLE
BANK
(B/T)
ROW
(D/Q)
ADDR
a
b
c
d
e
f
g
h
Q
D
T
T
R0
R1
C0
C0+1
C0+2
C0+3
C1
C1+1
C1+2
C1+3
†
Column-address sequence depends on programmed burst type and starting column address C0 and C1 (see Table 5).
Figure 31. CLK Suspend (HOLD) During Read Burst and Write Burst (CAS latency = 3, burst length = 4)
TMS626812
1048576 BY 8-BIT BY 2-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY
SMOS687A –JULY 1996 – REVISED APRIL 1997
device symbolization
TI
TMS626812 DGE
-SS
Speed Code (-12A, -12)
Package Code
W
B
Y
M
LLLL P
Assembly Site Code
Lot Traceability Code
Month Code
Year Code
Die Revision Code
Wafer Fab Code
37
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS626812
1048576-WORD BY 8-BIT BY 2-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY
SMOS687A –JULY 1996 – REVISED MARCH 1997
MECHANICAL DATA
DGE (R-PDSO-G44)
PLASTIC SMALL-OUTLINE PACKAGE
0.018 (0,45)
0.006 (0,16)
0.031 (0,80)
M
0.012 (0,30)
44
23
0.471 (11,96)
0.455 (11,56)
0.404 (10,26)
0.396 (10,06)
0.006 (0,15) NOM
Gage Plane
0.010 (0,25)
1
22
0°–5°
0.729 (18,51)
0.721 (18,31)
0.024 (0,60)
0.016 (0,40)
Seating Plane
0.004 (0,10)
0.047 (1,20) MAX
0.002 (0,05) MIN
4040070-3/C 4/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion.
38
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TMS626812
1048576-WORD BY 8-BIT BY 2-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY
SMOS687A –JULY 1996 – REVISED MARCH 1997
39
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
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