TMSC6701_技术文档

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SPRS067E – MAY 1998 – REVISED MAY 2000

D

Highest Performance Floating-Point Digital

Signal Processor (DSP) TMS320C6701

– 8.3-, 6.7-, 6-ns Instruction Cycle Time

– 120-, 150-, 167-MHz Clock Rate

– Eight 32-Bit Instructions/Cycle

– 1 GFLOPS

GJC (352-PIN BGA) PACKAGE

(BOTTOM VIEW)

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– TMS320C6201 Fixed-Point DSP

Pin-Compatible

VelociTI Advanced Very Long Instruction

Word (VLIW) ’C67x CPU Core

– Eight Highly Independent Functional

Units:

R

T

U

V

W

Y

AA

AB

AC

AD

AE

AF

– Four ALUs (Floating- and Fixed-Point)

– Two ALUs (Fixed-Point)

– Two Multipliers (Floating- and

Fixed-Point)

– Load-Store Architecture With 32 32-Bit

General-Purpose Registers

– Instruction Packing Reduces Code Size

– All Instructions Conditional

D

Instruction Set Features

– Hardware Support for IEEE

Single-Precision Instructions

– Hardware Support for IEEE

Double-Precision Instructions

– Byte-Addressable (8-, 16-, 32-Bit Data)

– 8-Bit Overflow Protection

– Saturation

D

16-Bit Host-Port Interface (HPI)

– Access to Entire Memory Map

D

Two Multichannel Buffered Serial Ports

(McBSPs)

– Direct Interface to T1/E1, MVIP, SCSA

Framers

– Bit-Field Extract, Set, Clear

– Bit-Counting

– Normalization

– ST-Bus-Switching Compatible

– Up to 256 Channels Each

– AC97-Compatible

– Serial-Peripheral-Interface (SPI)

Compatible (Motorola )

D

1M-Bit On-Chip SRAM

– 512K-Bit Internal Program/Cache

(16K 32-Bit Instructions)

– 512K-Bit Dual-Access Internal Data

(64K Bytes)

D

Two 32-Bit General-Purpose Timers

Flexible Phase-Locked-Loop (PLL) Clock

Generator

32-Bit External Memory Interface (EMIF)

– Glueless Interface to Synchronous

Memories: SDRAM and SBSRAM

– Glueless Interface to Asynchronous

Memories: SRAM and EPROM

– 52M-Byte Addressable External Memory

Space

†

IEEE-1149.1 (JTAG )

Boundary-Scan-Compatible

352-Pin Ball Grid Array (BGA) Package

(GJC Suffix)

0.18-µm/5-Level Metal Process

– CMOS Technology

D

Four-Channel Bootloading

Direct-Memory-Access (DMA) Controller

With an Auxiliary Channel

D

3.3-V I/Os, 1.8-V Internal (120-, 150-MHz)

3.3-V I/Os, 1.9-V Internal (167-MHz Only)

D

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

VelociTI is a trademark of Texas Instruments.

Motorola is a trademark of Motorola, Inc.

†

IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.

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SPRS067E – MAY 1998 – REVISED MAY 2000

Table of Contents

description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

device characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

functional block and CPU diagram . . . . . . . . . . . . . . . . . . . . . 4

CPU description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

signal groups description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

documentation support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

clock PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

parameter measurement information . . . . . . . . . . . . . . . 29

signal-transition levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

input and output clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

asynchronous memory timing . . . . . . . . . . . . . . . . . . . . . 33

synchronous-burst memory timing . . . . . . . . . . . . . . . . . 35

synchronous DRAM timing . . . . . . . . . . . . . . . . . . . . . . . . 39

HOLD/HOLDA timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

external interrupt timing . . . . . . . . . . . . . . . . . . . . . . . . . . 46

host-port interface timing . . . . . . . . . . . . . . . . . . . . . . . . . 47

multichannel buffered serial port timing . . . . . . . . . . . . . 50

DMAC, timer, power-down timing . . . . . . . . . . . . . . . . . . 61

JTAG test-port timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

absolute maximum ratings over operating case

temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

recommended operating conditions . . . . . . . . . . . . . . . . . . . 27

electrical characteristics over recommended ranges of

supply voltage and operating case temperature . . . . 28

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P R O C E S S O R

SPRS067E – MAY 1998 – REVISED MAY 2000

description

The TMS320C67x DSPs are the floating-point DSP family in the TMS320C6000 DSP platform. The

TMS320C6701 (’C6701) device is based on the high-performance, advanced VelociTI

very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making this DSP an

excellent choice for multichannel and multifunction applications. With performance of up to 1 giga floating-point

operations per second (GFLOPS) at a clock rate of 167 MHz, the ’C6701 offers cost-effective solutions to

high-performance DSP programming challenges. The ’C6701 DSP possesses the operational flexibility of

high-speed controllers and the numerical capability of array processors. This processor has 32 general-purpose

registers of 32-bit word length and eight highly independent functional units. The eight functional units provide

four floating-/fixed-point ALUs, two fixed-point ALUs, and two floating-/fixed-point multipliers. The ’C6701 can

produce two multiply-accumulates (MACs) per cycle for a total of 334 million MACs per second (MMACS). The

’C6701 DSP also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals.

The ’C6701 includes a large bank of on-chip memory and has a powerful and diverse set of peripherals.

Program memory consists of a 64K-byte block that is user-configurable as cache or memory-mapped program

space. Data memory consists of two 32K-byte blocks of RAM. The peripheral set includes two multichannel

buffered serial ports (McBSPs), two general-purpose timers, a host-port interface (HPI), and a glueless external

memory interface (EMIF) capable of interfacing to SDRAM or SBSRAM and asynchronous peripherals.

The ’C6701 has a complete set of development tools which includes: a new C compiler, an assembly optimizer

to simplify programming and scheduling, and a Windows debugger interface for visibility into source code

execution.

device characteristics

Table 1 provides an overview of the ’C6701 DSP. The table shows significant features of each device, including

the capacity of on-chip RAM, the peripherals, the execution time, and the package type with pin count, etc.

Table 1. Characteristics of the ’C6701 Processors

HARDWARE FEATURES

’C6701

EMIF

DMA

1

4-Channel

Host-Port Interface (HPI)

1

Peripherals

McBSPs

2

32-Bit Timers

Size (Bytes)

Organization

Size (Bytes)

Organization

MHz

2

64K

Internal Program Memory

Internal Data Memory

64K Bytes Cache/Mapped Program

64K

2 Blocks: Eight 16-Bit Banks per Block 50/50 Split

Frequency

Cycle Time

120, 150, 167

ns

6 ns (’6701-167); 6.7 ns (’6701-150); 8.3 ns (’6701-120)

1.8 (’6701-120, -150)

1.9 (’6701-167 only)

3.3

Core (V)

Voltage

I/O (V)

PLL Options

CLKIN frequency multiplier

Bypass (x1), x4

352-pin GJC

0.18 µm

BGA Package

35 x 35 mm

Process Technology

µm

Product Preview (PP)

Advance Information (AI)

Production Data (PD)

Product Status

PD

TMS320C6000 is a trademark of Texas Instruments.

Windows is a registered trademark of Microsoft Corporation.

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P R O C E S S O R

SPRS067E – MAY 1998 – REVISED MAY 2000

functional block and CPU diagram

’C6701 Digital Signal Processor

SDRAM

SBSRAM

32

SRAM

Internal Program Memory

1 Block Program/Cache

(64K Bytes)

Program

Access/Cache

Controller

External Memory

Interface (EMIF)

ROM/FLASH

I/O Devices

’C67x CPU

Timer 0

Timer 1

Instruction Fetch

Control

Registers

Instruction Dispatch

Instruction Decode

Control

Logic

Multichannel

Buffered Serial

Port 0

Framing Chips:

H.100, MVIP,

SCSA, T1, E1

AC97 Devices,

SPI Devices,

Codecs

Data Path A

A Register File

Data Path B

Test

B Register File

In-Circuit

Emulation

Multichannel

Buffered Serial

Port 1

Interrupt

Control

†

.L1 .S1 .M1 .D1

.D2 .M2 .S2 .L2

Direct Memory

Access Controller

(DMA)

Internal Data

Memory

(64K Bytes)

2 Blocks of 8 Banks

Each

HOST CONNECTION

MC68360 Glueless

MPC860 Glueless

PCI9050 Bridge + Inverter

MC68302 + PAL

Data

Access

Controller

Power-

Down

Logic

(4 Channels)

Host Port

Interface

(HPI)

16

PLL

(x1, x4)

MPC750 + PAL

MPC960 (Jx/Rx) + PAL

†

These functional units execute floating-point instructions.

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SPRS067E – MAY 1998 – REVISED MAY 2000

CPU description

The CPU fetches VelociTI advanced very-long instruction words (VLIW) (256 bits wide) to supply up to eight

32-bit instructions to the eight functional units during every clock cycle. The VelociTI VLIW architecture features

controls by which all eight units do not have to be supplied with instructions if they are not ready to execute. The

first bit of every 32-bit instruction determines if the next instruction belongs to the same execute packet as the

previous instruction, or whether it should be executed in the following clock as a part of the next execute packet.

Fetch packets are always 256 bits wide; however, the execute packets can vary in size. The variable-length

execute packets are a key memory-saving feature, distinguishing the ’C67x CPU from other VLIW architectures.

The CPU features two sets of functional units. Each set contains four units and a register file. One set contains

functional units .L1, .S1, .M1, and .D1; the other set contains units .D2, .M2, .S2, and .L2. The two register files

contain 16 32-bit registers each for the total of 32 general-purpose registers. The two sets of functional units,

along with two register files, compose sides A and B of the CPU (see the Functional and CPU Block diagram

and Figure 1). The four functional units on each side of the CPU can freely share the 16 registers belonging to

that side. Additionally, each side features a single data bus connected to all registers on the other side, by which

the two sets of functional units can access data from the register files on opposite sides. While register access

by functional units on the same side of the CPU as the register file can service all the units in a single clock cycle,

register access using the register file across the CPU supports one read and one write per cycle.

The ’C67x CPU executes all TMS320C62x DSP fixed-point instructions. In addition to the ’C62x DSP

fixed-point instructions, the six out of eight functional units (.L1, .M1, .D1, .D2, .M2, and .L2) also execute

floating-point instructions. The remaining two functional units (.S1 and .S2) also execute the new LDDW

instruction which loads 64 bits per CPU side for a total of 128 bits per cycle.

Another key feature of the ’C67x CPU is the load/store architecture, where all instructions operate on registers

(as opposed to data in memory). Two sets of data-addressing units (.D1 and .D2) are responsible for all data

transfers between the register files and the memory. The data address driven by the .D units allows data

addresses generated from one register file to be used to load or store data to or from the other register file. The

’C67x CPU supports a variety of indirect-addressing modes using either linear- or circular-addressing modes

with 5- or 15-bit offsets. All instructions are conditional, and most can access any one of the 32 registers. Some

registers, however, are singled out to support specific addressing or to hold the condition for conditional

instructions (if the condition is not automatically “true”). The two .M functional units are dedicated for multiplies.

The two .S and .L functional units perform a general set of arithmetic, logical, and branch functions with results

available every clock cycle.

The processing flow begins when a 256-bit-wide instruction fetch packet is fetched from a program memory.

The 32-bit instructions destined for the individual functional units are “linked” together by “1” bits in the least

significant bit (LSB) position of the instructions. The instructions that are “chained” together for simultaneous

execution (up to eight in total) compose an execute packet. A “0” in the LSB of an instruction breaks the chain,

effectively placing the instructions that follow it in the next execute packet. If an execute packet crosses the

fetch-packet boundary (256 bits wide), the assembler places it in the next fetch packet, while the remainder of

the current fetch packet is padded with NOP instructions. The number of execute packets within a fetch packet

can vary from one to eight. Execute packets are dispatched to their respective functional units at the rate of one

per clock cycle and the next 256-bit fetch packet is not fetched until all the execute packets from the current fetch

packet have been dispatched. After decoding, the instructions simultaneously drive all active functional units

for a maximum execution rate of eight instructions every clock cycle. While most results are stored in 32-bit

registers, they can be subsequently moved to memory as bytes or half-words as well. All load and store

instructions are byte-, half-word, or word-addressable.

TMS320C62x is a trademark of Texas Instruments.

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SPRS067E – MAY 1998 – REVISED MAY 2000

CPU description (continued)

src1

†

.L1

src2

dst

8

long dst

long src

8

32

LD1 32 MSB

ST1

Register

File A

(A0–A15)

long src

long dst

dst

8

Data Path A

†

.S1

src1

src2

dst

†

.M1

src1

src2

LD1 32 LSB

DA1

dst

src1

src2

.D1

2X

1X

src2

src1

dst

DA2

.D2

.M2

LD2 32 LSB

src2

†

src1

dst

src2

Register

File B

(B0–B15)

src1

dst

†

.S2

Data Path B

8

long dst

long src

8

32

LD2 32 MSB

ST2

long src

long dst

dst

8

†

.L2

src2

src1

Control

Register File

†

These functional units execute floating-point instructions.

Figure 1. TMS320C67x CPU Data Paths

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P R O C E S S O R

SPRS067E – MAY 1998 – REVISED MAY 2000

signal groups description

CLKIN

CLKOUT2

CLKOUT1

CLKMODE1

CLKMODE0

BOOTMODE4

BOOTMODE3

BOOTMODE2

BOOTMODE1

BOOTMODE0

Boot Mode

CLOCK/PLL

PLLFREQ3

PLLFREQ2

PLLFREQ1

PLLV

RESET

NMI

EXT_INT7

PLLG

PLLF

EXT_INT6

EXT_INT5

EXT_INT4

IACK

Reset and

Interrupts

INUM3

INUM2

INUM1

INUM0

TMS

TDO

TDI

IEEE Standard

1149.1

(JTAG)

Emulation

TCK

TRST

EMU1

EMU0

Little ENDIAN

Big ENDIAN

LENDIAN

RSV9

RSV8

RSV7

RSV6

RSV5

RSV4

RSV3

RSV2

RSV1

RSV0

DMAC3

DMAC2

DMAC1

DMAC0

DMA Status

Reserved

Power-Down

Status

PD

Control/Status

HPI

16

(Host-Port Interface)

HD[15:0]

Data

HAS

HR/W

HCS

HDS1

HDS2

HRDY

HINT

HCNTL0

HCNTL1

Register Select

Control

HHWIL

HBE1

HBE0

Half-Word/Byte

Select

Figure 2. CPU and Peripheral Signals

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SPRS067E – MAY 1998 – REVISED MAY 2000

signal groups description (continued)

32

ED[31:0]

Data

ARE

Asynchronous

Memory

AOE

AWE

ARDY

Control

CE3

CE2

CE1

CE0

Memory Map

Space Select

SSADS

SSOE

SSWE

SSCLK

SBSRAM

Control

20

EA[21:2]

Word Address

Byte Enables

BE3

BE2

BE1

BE0

SDA10

SDRAS

SDCAS

SDWE

SDRAM

Control

SDCLK

HOLD

HOLD/

HOLDA

EMIF

(External Memory Interface)

TOUT1

TINP1

TOUT0

TINP0

Timer 1

Timer 0

Timers

McBSP1

Receive

McBSP0

Receive

CLKX1

FSX1

DX1

CLKX0

FSX0

DX0

CLKR1

FSR1

DR1

CLKR0

FSR0

DR0

Transmit

Clock

Transmit

Clock

CLKS1

CLKS0

McBSPs

(Multichannel Buffered Serial Ports)

Figure 3. Peripheral Signals

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P R O C E S S O R

SPRS067E – MAY 1998 – REVISED MAY 2000

Signal Descriptions

SIGNAL

NAME

†

TYPE

DESCRIPTION

NO.

CLOCK/PLL

CLKIN

C10

AF22

AF20

C6

I

Clock Input

CLKOUT1

O

Clock output at full device speed

Clock output at half of device speed

Clock mode select

CLKOUT2

CLKMODE1

CLKMODE0

PLLFREQ3

PLLFREQ2

PLLFREQ1

I

C5

•

Selects whether the output clock frequency = input clock frequency x4 or x1

A9

PLL frequency range (3, 2, and 1)

The target range for CLKOUT1 frequency is determined by the 3-bit value of the PLLFREQ pins.

D11

B10

D12

C12

A11

I

•

‡

§

A

§

A

§

A

PLLV

PLL analog V connection for the low-pass filter

CC

‡

PLLG

PLLF

PLL analog GND connection for the low-pass filter

PLL low-pass filter connection to external components and a bypass capacitor

JTAG EMULATION

TMS

TDO

TDI

L3

W2

R4

R3

T1

I

JTAG test-port mode select (features an internal pullup)

JTAG test-port data out

O/Z

I

JTAG test-port data in (features an internal pullup)

JTAG test-port clock

TCK

TRST

EMU1

EMU0

JTAG test-port reset (features an internal pulldown)

¶

Y1

W3

I/O/Z

Emulation pin 1, pullup with a dedicated 20-kΩ resistor

Emulation pin 0, pullup with a dedicated 20-kΩ resistor

CONTROL

RESET

NMI

K2

L2

I

Device reset

Nonmaskable interrupt

•

Edge-driven (rising edge)

EXT_INT7

EXT_INT6

EXT_INT5

EXT_INT4

IACK

U3

V2

External interrupts

Edge-driven (rising edge)

I

•

W1

U4

Y2

O

Interrupt acknowledge for all active interrupts serviced by the CPU

Active interrupt identification number

INUM3

AA1

W4

AA2

AB1

INUM2

•

Valid during IACK for all active interrupts (not just external)

Encoding order follows the interrupt-service fetch-packet ordering

O

INUM1

INUM0

If high, LENDIAN selects little-endian byte/half-word addressing order within a word

If low, LENDIAN selects big-endian addressing

LENDIAN

H3

I

PD

D3

O

Power-down mode 3 (active if high)

†

‡

I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground

PLLV and PLLG are not part of external voltage supply or ground. See the CLOCK/PLL documentation for information on how to connect these

pins.

§

¶

A = Analog Signal (PLL Filter)

For emulation and normal operation, pull up EMU1 and EMU0 with a dedicated 20-kΩ resistor. For boundary scan, pull down EMU1 and EMU0

with a dedicated 20-kΩ resistor.

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Signal Descriptions (Continued)

SIGNAL

†

TYPE

DESCRIPTION

NAME

NO.

HOST-PORT INTERFACE (HPI)

HINT

H26

F23

D25

C26

E23

D24

C23

B13

B14

C14

B15

D15

B16

A17

B17

D16

B18

A19

C18

B19

C19

B20

B21

C22

B23

D22

A24

J24

O

I

Host interrupt (from DSP to host)

HCNTL1

HCNTL0

HHWIL

HBE1

HBE0

HR/W

HD15

HD14

HD13

HD12

HD11

HD10

HD9

Host control – selects between control, address, or data registers

Host half-word select – first or second half-word (not necessarily high or low order)

Host byte select within word or half-word

I

Host byte select within word or half-word

I

Host read or write select

HD8

I/O/Z

Host-port data (used for transfer of data, address, and control)

HD7

HD6

HD5

HD4

HD3

HD2

HD1

HD0

HAS

I

Host address strobe

Host chip select

HCS

HDS1

HDS2

HRDY

I

Host data strobe 1

Host data strobe 2

Host ready (from DSP to host)

BOOT MODE

I

O

BOOTMODE4

BOOTMODE3

BOOTMODE2

BOOTMODE1

BOOTMODE0

D8

B4

A3

D5

C4

I

Boot mode

†

I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground

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SPRS067E – MAY 1998 – REVISED MAY 2000

Signal Descriptions (Continued)

SIGNAL

NAME

†

TYPE

DESCRIPTION

NO.

EMIF – CONTROL SIGNALS COMMON TO ALL TYPES OF MEMORY

CE3

AE22

AD26

AB24

AC26

AB25

AA24

Y23

O/Z

CE2

CE1

CE0

BE3

BE2

BE1

BE0

Memory space enables

•

Enabled by bits 24 and 25 of the word address

Only one asserted during any external data access

Byte-enable control

•

Decoded from the two lowest bits of the internal address

Byte-write enables for most types of memory

Can be directly connected to SDRAM read and write mask signal (SDQM)

EMIF – ADDRESS

AA26

EA21

EA20

EA19

EA18

EA17

EA16

EA15

EA14

EA13

EA12

EA11

EA10

EA9

J26

K25

L24

K26

M26

M25

P25

P24

R25

T26

R23

U26

U25

T23

V26

V25

W26

V24

W25

Y26

O/Z

External address (word address)

EA8

EA7

EA6

EA5

EA4

EA3

EA2

†

I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground

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SPRS067E – MAY 1998 – REVISED MAY 2000

Signal Descriptions (Continued)

SIGNAL

†

TYPE

DESCRIPTION

NAME

NO.

EMIF – DATA

ED31

AB2

AC1

ED30

ED29

ED28

ED27

ED26

ED25

ED24

ED23

ED22

ED21

ED20

ED19

ED18

ED17

ED16

ED15

ED14

ED13

ED12

ED11

ED10

ED9

AA4

AD1

AC3

AD4

AF3

AE4

AD5

AF4

AE5

AD6

AE6

AD7

AC8

AF7

I/O/Z

External data

AD9

AD10

AF9

AC11

AE10

AE11

AF11

AE14

AF15

AE15

AF16

AC15

AE17

AF18

AF19

AC17

ED8

ED7

ED6

ED5

ED4

ED3

ED2

ED1

ED0

EMIF – ASYNCHRONOUS MEMORY CONTROL

Asynchronous memory read enable

ARE

Y24

AC24

AD23

W23

O/Z

I

AOE

AWE

ARDY

Asynchronous memory output enable

Asynchronous memory write enable

Asynchronous memory ready input

†

I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground

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SPRS067E – MAY 1998 – REVISED MAY 2000

Signal Descriptions (Continued)

SIGNAL

NAME

†

TYPE

DESCRIPTION

NO.

EMIF – SYNCHRONOUS BURST SRAM CONTROL

SBSRAM address strobe

SSADS

AC20

AF21

AD19

AD17

O/Z

O

SSOE

SSWE

SSCLK

SBSRAM output enable

SBSRAM write enable

SBSRAM clock

EMIF – SYNCHRONOUS DRAM CONTROL

SDRAM address 10 (separate for deactivate command)

SDRAM row-address strobe

SDRAM column-address strobe

SDRAM write enable

SDA10

SDRAS

SDCAS

SDWE

SDCLK

AD21

AF24

AD22

AF23

AE20

O/Z

O

SDRAM clock

EMIF – BUS ARBITRATION

Hold request from the host

HOLD

AA25

A7

I

HOLDA

O

Hold-request-acknowledge to the host

TIMERS

TOUT1

TINP1

TOUT0

TINP0

H24

K24

M4

O

I

Timer 1 or general-purpose output

Timer 1 or general-purpose input

Timer 0 or general-purpose output

Timer 0 or general-purpose input

DMA ACTION COMPLETE

O

I

K4

DMAC3

DMAC2

DMAC1

DMAC0

D2

F4

D1

E2

O

I

DMA action complete

MULTICHANNEL BUFFERED SERIAL PORT 1 (McBSP1)

CLKS1

CLKR1

CLKX1

DR1

E25

H23

F26

D26

G23

E26

F25

External clock source (as opposed to internal)

Receive clock

I/O/Z

I

Transmit clock

Receive data

DX1

O/Z

I/O/Z

Transmit data

FSR1

FSX1

Receive frame sync

Transmit frame sync

†

I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground

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SPRS067E – MAY 1998 – REVISED MAY 2000

Signal Descriptions (Continued)

SIGNAL

†

TYPE

DESCRIPTION

NAME

NO.

MULTICHANNEL BUFFERED SERIAL PORT 0 (McBSP0)

External clock source (as opposed to internal)

Receive clock

CLKS0

L4

M2

L1

J1

I

CLKR0

CLKX0

DR0

I/O/Z

I

Transmit clock

Receive data

DX0

R1

P4

P3

O/Z

I/O/Z

Transmit data

FSR0

FSX0

Receive frame sync

Transmit frame sync

RESERVED FOR TEST

RSV0

RSV1

RSV2

RSV3

RSV4

RSV5

RSV6

RSV7

RSV8

RSV9

T2

G2

I

Reserved for testing, pullup with a dedicated 20-kΩ resistor

Reserved for testing, pulldown with a dedicated 20-kΩ resistor

Reserved (leave unconnected, do not connect to power or ground)

Reserved for testing, pullup with a dedicated 20-kW resistor

Reserved (leave unconnected, do not connect to power or ground)

SUPPLY VOLTAGE PINS

C11

B9

I

A6

I

C8

O

I

C21

B22

A23

E4

I

O

A10

A15

A18

A21

A22

B7

C1

D17

F3

G24

G25

H25

J25

L25

M3

DV

S

3.3-V supply voltage

DD

N3

N23

R26

T24

U24

W24

†

I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground

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SPRS067E – MAY 1998 – REVISED MAY 2000

Signal Descriptions (Continued)

SIGNAL

NAME

†

TYPE

DESCRIPTION

SUPPLY VOLTAGE PINS (CONTINUED)

NO.

Y4

AB3

AB4

AB26

AC6

AC10

AC19

AC21

AC22

AC25

AD11

AD13

AD15

AD18

AE18

AE21

AF5

AF6

AF17

A5

DV

S

3.3-V supply voltage

DD

A12

A16

A20

B2

B6

B11

B12

B25

C3

1.8-V supply voltage (for ’6701-120, -150)

1.9-V supply voltage (for ’6701-167 only)

CV

S

DD

C15

C20

C24

D4

D6

D7

D9

D14

D18

D20

†

I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground

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SPRS067E – MAY 1998 – REVISED MAY 2000

Signal Descriptions (Continued)

SIGNAL

†

TYPE

DESCRIPTION

SUPPLY VOLTAGE PINS (CONTINUED)

NAME

NO.

D23

E1

F1

H4

J4

J23

K1

K23

M1

M24

N4

N25

P2

P23

T3

T4

U1

1.8-V supply voltage (for ’6701-120, -150)

1.9-V supply voltage (for ’6701-167 only)

CV

S

DD

V4

V23

AC4

AC9

AC12

AC13

AC18

AC23

AD3

AD8

AD14

AD24

AE2

AE8

AE12

AE25

AF12

†

I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground

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SPRS067E – MAY 1998 – REVISED MAY 2000

Signal Descriptions (Continued)

SIGNAL

NAME

†

TYPE

DESCRIPTION

NO.

GROUND PINS

A1

A2

A4

A13

A14

A25

A26

B1

B3

B5

B24

B26

C2

C7

C13

C16

C17

C25

D13

D19

E3

V

SS

GND

Ground pins

E24

F2

F24

G3

G4

G26

J3

L23

L26

M23

N1

N2

N24

N26

P1

P26

R24

T25

†

I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground

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SPRS067E – MAY 1998 – REVISED MAY 2000

Signal Descriptions (Continued)

SIGNAL

†

TYPE

DESCRIPTION

GROUND PINS (CONTINUED)

NAME

NO.

U2

U23

V1

V3

Y3

Y25

AA3

AA23

AB23

AC2

AC5

AC7

AC14

AC16

AD2

AD12

AD16

AD20

AD25

AE1

V

SS

GND

Ground pins

AE3

AE7

AE9

AE13

AE16

AE19

AE23

AE24

AE26

AF1

AF2

AF8

AF10

AF13

AF14

AF25

AF26

†

I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground

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SPRS067E – MAY 1998 – REVISED MAY 2000

Signal Descriptions (Continued)

SIGNAL

NAME

†

TYPE

DESCRIPTION

REMAINING UNCONNECTED PINS

NO.

A8

B8

C9

D10

D21

G1

H1

H2

J2

NC

Unconnected pins

K3

R2

†

I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground

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development support

TI offers an extensive line of development tools for the TMS320C6000t DSP platform, including tools to

evaluate the performance of the processors, generate code, develop algorithm implementations, and fully

integrate and debug software and hardware modules.

The following products support development of C6000t DSP-based applications:

Software Development Tools:

Code Composer Studiot Integrated Development Environment (IDE): including Editor

C/C++/Assembly Code Generation, and Debug plus additional development tools

Scalable, Real-Time Foundation Software (DSP BIOS), which provides the basic run-time target software

needed to support any DSP application.

Hardware Development Tools:

Extended Development System (XDS ) Emulator (supports C6000t DSP multiprocessor system debug)

EVM (Evaluation Module)

The TMS320 DSP Development Support Reference Guide (SPRU011) contains information about

development-support products for all TMS320t DSP family member devices, including documentation. See

this document for further information on TMS320t DSP documentation or any TMS320t DSP support

products from Texas Instruments. An additional document, the TMS320 Third-Party Support Reference Guide

(SPRU052), contains information about TMS320t DSP-related products from other companies in the industry.

To receive TMS320t DSP literature, contact the Literature Response Center at 800/477-8924.

For a complete listing of development-support tools for the TMS320C6000t DSP platform, visit the Texas

Instruments web site on the Worldwide Web at http://www.ti.com uniform resource locator (URL) and under

“Development Tools”, select “Digital Signal Processors”. For information on pricing and availability, contact the

nearest TI field sales office or authorized distributor.

Code Composer Studio, XDS, and TMS320 are trademarks of Texas Instruments.

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device and development-support tool nomenclature

To designate the stages in the product-development cycle, TI assigns prefixes to the part numbers of all

TMS320 DSP devices and support tools. Each TMS320 DSP family member has one of three prefixes: TMX,

TMP, or TMS. Texas Instruments recommends two of three possible prefix designators for support tools: TMDX

and TMDS. These prefixes represent evolutionary stages of product development from engineering prototypes

(TMX/TMDX) through fully qualified production devices/tools (TMS/TMDS).

Device development evolutionary flow:

TMX

TMP

TMS

Experimental device that is not necessarily representative of the final device’s electrical

specifications

Final silicon die that conforms to the device’s electrical specifications but has not completed

quality and reliability verification

Fully qualified production device

Support tool development evolutionary flow:

TMDX

Development-support product that has not yet completed Texas Instruments internal qualification

testing.

TMDS

Fully qualified development-support product

TMX and TMP devices and TMDX development-support tools are shipped against the following disclaimer:

“Developmental product is intended for internal evaluation purposes.”

TMS devices and TMDS development-support tools have been characterized fully, and the quality and reliability

of the device have been demonstrated fully. TI’s standard warranty applies.

Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard production

devices. Texas Instruments recommends that these devices not be used in any production system because their

expected end-use failure rate still is undefined. Only qualified production devices are to be used.

TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package type

(for example, GJC), the temperature range (for example, blank is the default commercial temperature range),

and the device speed range in megahertz (for example, -167 is 167 MHz). Table 2 identifies the available

TMS320C6701 devices by their associated orderable part numbers (P/Ns) and gives device-specific ordering

information (for example, device speeds, core and I/O supply voltage values, and device operating temperature

ranges). Figure 4 provides a legend for reading the complete device name for any TMS320 DSP family

member.

Table 2. TMS320C6701 Device P/Ns and Ordering Information

OPERATING CASE

TEMPERATURE

RANGE

CV

DV

DD

DEVICE ORDERABLE P/N

DEVICE SPEED

(CORE VOLTAGE)

(I/O VOLTAGE)

TMSC6701GJC16719V

TMS320C6701GJC150

TMS320C6701GJCA120

167 MHz/1 GFLOPS

150 MHz/900 MFLOPS

120 MHz/720 MFLOPS

1.9 V

1.8 V

3.3 V

0_C to 90_C

–40_C to 105_C

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SPRS067E – MAY 1998 – REVISED MAY 2000

device and development-support tool nomenclature (continued)

(A)

TMS 320

C

6701 GJC

167

PREFIX

DEVICE SPEED RANGE

100 MHz

120 MHz

150 MHz

167 MHz

200 MHz

233 MHz

250 MHz

300 MHz

TMX= Experimental device

TMP= Prototype device

TMS= Qualified device

SMJ = MIL-PRF-38535 (QML)

SM = Commercial processing

DEVICE FAMILY

320 = TMS320 DSP family

TEMPERATURE RANGE (DEFAULT: 0°C TO 90°C)

Blank = 0°C to 90°C, commercial temperature

A

= –40°C to 105°C, extended temperature

†

PACKAGE TYPE

N

=

Plastic DIP

J

Ceramic DIP

TECHNOLOGY

JD

GB

FZ

FN

FD

PJ

PQ

PZ

Ceramic DIP side-brazed

Ceramic PGA

Ceramic CC

Plastic leaded CC

Ceramic leadless CC

100-pin plastic EIAJ QFP

132-pin plastic bumpered QFP

100-pin plastic TQFP

C

E

F

=

CMOS

CMOS EPROM

CMOS Flash EEPROM

PBK = 128-pin plastic TQFP

PGE = 144-pin plastic TQFP

GFN = 256-pin plastic BGA

GGU = 144-pin plastic BGA

GGP = 352-pin plastic BGA

GJC = 352-pin plastic BGA

GJL = 352-pin plastic BGA

GLS = 384-pin plastic BGA

GLW = 340-pin plastic BGA

GHK = 288-pin plastic MicroStar BGAt

DEVICE

’1x DSP:

10

14

15

16

17

’2x DSP:

’2xx DSP:

’3x DSP:

25

26

203

204

206

209

240

30

31

32

’4x DSP:

’5x DSP:

40

44

50

51

52

53

56

57

†

DIP

PGA

CC

=

Dual-In-Line Package

Pin Grid Array

Chip Carrier

’54x DSP:

’6x DSP:

541

542

543

545

546

548

=

QFP

Quad Flat Package

TQFP = Thin Quad Flat Package

BGA Ball Grid Array

6201

6202

6202B

6203

6204

6205

6211

6701

6711

=

Figure 4. TMS320 DSP Device Nomenclature (Including TMS320C6701)

MicroStar BGA is a trademark of Texas Instruments.

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documentation support

Extensive documentation supports all TMS320

DSP family generations of devices from product

announcement through applications development. The types of documentation available include: data sheets,

such as this document, with design specifications; complete user’s reference guides for all devices; technical

briefs; development-support tools; and hardware and software applications. The following is a brief, descriptive

list of support documentation specific to the ’C6x devices:

The TMS320C6000 CPU and Instruction Set Reference Guide (literature number SPRU189) describes the

C6000 DSP CPU architecture, instruction set, pipeline, and associated interrupts.

The TMS320C6000 Peripherals Reference Guide (literature number SPRU190) describes the functionality of

the peripherals available on ’C6x devices, such as the external memory interface (EMIF), host-port interface

(HPI), multichannel buffered serial ports (McBSPs), direct-memory-access (DMA), enhanced

direct-memory-access (EDMA) controller, expansion bus (XB), clocking and phase-locked loop (PLL); and

power-down modes. This guide also includes information on internal data and program memories.

The TMS320C6000 Technical Brief (literature number SPRU197) gives an introduction to the ’C62x/C67x

devices, associated development tools, and third-party support.

The tools support documentation is electronically available within the Code Composer Studio Integrated

Development Environment (IDE). For a complete listing of C6000 DSP latest documentation, visit the Texas

Instruments web site on the Worldwide Web at http://www.ti.com uniform resource locator (URL).

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SPRS067E – MAY 1998 – REVISED MAY 2000

clock PLL

All of the internal ’C67x clocks are generated from a single source through the CLKIN pin. This source clock

either drives the PLL, which multiplies the source clock in frequency to generate the internal CPU clock, or

bypasses the PLL to become the internal CPU clock.

To use the PLL to generate the CPU clock, the external PLL filter circuit must be properly designed. Table 3,

Table 4, and Figure 5 show the external PLL circuitry for either x1 (PLL bypass) or x4 PLL multiply modes.

Table 3 and Figure 6 show the external PLL circuitry for a system with ONLY x1 (PLL bypass) mode.

To minimize the clock jitter, a single clean power supply should power both the ’C67x device and the external

clock oscillator circuit. Noise coupling into PLLF will directly impact PLL clock jitter. The minimum CLKIN rise

and fall times should also be observed. For the input clock timing requirements, see the input and output clocks

electricals section.

†

Table 3. CLKOUT1 Frequency Ranges

PLLFREQ3

(A9)

PLLFREQ2

(D11)

PLLFREQ1

(B10)

CLKOUT1 Frequency Range

(MHz)

0

1

0

1

0

50–140

65–167

130–167

†

Due to overlap of frequency ranges when choosing the PLLFREQ, more than one frequency range can contain

the CLKOUT1 frequency. Choose the lowest frequency range that includes the desired frequency. For example,

for CLKOUT1 = 133 MHz, choose PLLFREQ value of 000b. For CLKOUT1 = 167 MHz, choose PLLFREQ value

of 001b. PLLFREQ values other than 000b, 001b, and 010b are reserved.

Table 4. ’C6701 PLL Component Selection Table

CPU CLOCK

FREQUENCY

(CLKOUT1)

CLKIN

RANGE

(MHz)

CLKOUT2

RANGE

(MHz)

TYPICAL

R1

(Ω)

C1

(nF)

C2

(pF)

CLKMODE

LOCK TIME

‡

(µs)

RANGE (MHz)

x4

12.5–41.7

50–167

25–83.5

60.4

27

560

75

‡

Under some operating conditions, the maximum PLL lock time may vary as much as 150% from the specified typical value. For example, if the

typical lock time is specified as 100 µs, the maximum value may be as long as 250 µs.

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SPRS067E – MAY 1998 – REVISED MAY 2000

clock PLL (continued)

PLLFREQ3

PLLFREQ2

PLLFREQ1

(see Table 3)

3.3V

PLLV

Internal to ’C6701

PLL

CLKMODE0

PLLMULT

CLKIN

CLKMODE1

C4

C3

PLLCLK

0.1 mF

10 mF

CLKIN

1

0

CPU

CLOCK

LOOP FILTER

Available Multiply Factors

PLL Multiply

C2

CPU Clock

Frequency

f(CPUCLOCK)

CLKMODE1

CLKMODE0

Factors

C1

R1

0

1

0

1

0

1

x1(BYPASS)

Reserved

x4

1 x f(CLKIN)

Reserved

4 x f(CLKIN)

NOTES: A. Keep the lead length and the number of vias between the PLLF pin, the PLLG pin, and R1, C1, and C2 to a minimum. In addition,

place all PLL external components (R1, C1, C2, C3, C4, and the EMI Filter) as close to the C6000 DSP device as possible. For

the best performance, TI recommends that all the PLL external components be on a single side of the board without jumpers,

switches, or components other than the ones shown.

B. For reduced PLL jitter, maximize the spacing between switching signals and the PLL external components (R1, C1, C2, C3, C4,

and the EMI Filter).

C. The 3.3-V supply for the EMI filter must be from the same 3.3-V power plane supplying the I/O voltage, DV

D. EMI filter manufacturer: TDK part number ACF451832-333, 223, 153, 103. Panasonic part number EXCCET103U.

.

DD

Figure 5. External PLL Circuitry for Either PLL x4 Mode or x1 (Bypass) Mode

PLLFREQ3

PLLFREQ2

PLLFREQ1

(see Table 3)

3.3V

PLLV

Internal to ’C6701

CLKMODE0

CLKMODE1

PLL

PLLMULT

CLKIN

PLLCLK

CLKIN

1

0

LOOP FILTER

CPU

CLOCK

NOTES: A. For a system with ONLY PLL x1 (bypass) mode, short the PLLF terminal to the PLLG terminal.

B. The 3.3-V supply for the EMI filter must be from the same 3.3-V power plane supplying the I/O voltage, DV

.

DD

Figure 6. External PLL Circuitry for x1 (Bypass) Mode Only

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SPRS067E – MAY 1998 – REVISED MAY 2000

†

absolute maximum ratings over operating case temperature range (unless otherwise noted)

Supply voltage range, CV

Supply voltage range, DV

(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 2.3 V

(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 4 V

DD

Input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 4 V

Output voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 4 V

Operating case temperature range, T (Default) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0_C to 90_C

C

(A Version) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40_C to 105_C

Storage temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55_C to 150_C

stg

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 1: All voltage values are with respect to V

SS

.

recommended operating conditions

MIN NOM

MAX UNIT

’6701-120, -150

’6701-167 only

1.71

1.81

3.14

0

1.8

1.9

3.30

0

1.89

1.99

3.46

0

V

‡

Supply voltage, Core

CV

DV

DD

‡

Supply voltage, I/O

V

Supply ground

V

SS

High-level input voltage

Low-level input voltage

High-level output current

Low-level output current

2.0

V

IH

IL

0.8

–12

12

V

I

mA

_C

OH

OL

I

Default

0

90

T

C

Case temperature

A Version

–40

105

‡

TI DSP’s do not require specific power sequencing between the core supply and the I/O supply. However, systems should be designed to ensure

that neither supply is powered up for extended periods of time if the other supply is below the proper operating voltage. Excessive exposure to

these conditions can adversely affect the long term reliability of the device. System-level concerns such as bus contention may require supply

sequencing to be implemented. In this case, the core supply should be powered up at the same time as, or prior to (and powered down after),

the I/O buffers. For additional power supply sequencing information, see the Power Supply Sequencing Solutions For Dual Supply Voltage DSPs

application report (literature number SLVA073).

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SPRS067E – MAY 1998 – REVISED MAY 2000

electrical characteristics over recommended ranges of supply voltage and operating case

temperature (unless otherwise noted)

PARAMETER

High-level output voltage

Low-level output voltage

TEST CONDITIONS

MIN

TYP

MAX UNIT

V

DV

= MIN,

I

= MAX

2.4

V

OH

DD

OH

0.6

±10

V

OL

†

I

Input current

V = V

I SS

to DV

DD

uA

I

Off-state output current

V

O

= DV or 0 V

DD

OZ

CV

DV

= NOM, CPU clock = 150 MHz

= NOM, CPU clock = 120 MHz

= NOM, CPU clock = 150 MHz

= NOM, CPU clock = 120 MHz

= NOM, CPU clock = 150 MHz

= NOM, CPU clock = 120 MHz

470

380

250

200

85

DD

‡

I

Supply current, CPU + CPU memory access

mA

DD2V

‡

Supply current, peripherals

DD2V

DD3V

‡

Supply current, I/O pins

70

C

Input capacitance

Output capacitance

10

pF

i

o

†

TMS and TDI are not included due to internal pullups.

TRST is not included due to internal pulldown.

Measured with average activity (50% high / 50% low power). For more detailed information on CPU/peripheral/I/O activity, see the TMS320C6000

Power Consumption Summary application report (literature number SPRA486).

‡

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SPRS067E – MAY 1998 – REVISED MAY 2000

PARAMETER MEASUREMENT INFORMATION

I

OL

Tester Pin

Electronics

Output

Under

Test

50 Ω

V

ref

†

= 30 pF

C

T

I

OH

†

Typical distributed load circuit capacitance.

signal-transition levels

All input and output timing parameters are referenced to 1.5 V for both “0” and “1” logic levels.

V

ref

= 1.5 V

Figure 7. Input and Output Voltage Reference Levels for ac Timing Measurements

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SPRS067E – MAY 1998 – REVISED MAY 2000

INPUT AND OUTPUT CLOCKS

†‡

timing requirements for CLKIN (’C6701-150, -167 devices only) (see Figure 8)

’C6701-150

CLKMODE = x4 CLKMODE = x1

’C6701-167

CLKMODE = x4 CLKMODE = x1

NO.

UNIT

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

1

2

t

Cycle time, CLKIN

26.7

6.7

24

6

ns

c(CLKIN)

Pulse duration,

CLKIN high

0.4C

0.45C

0.4C

0.45C

w(CLKINH)

Pulse duration,

CLKIN low

3

4

t

ns

w(CLKINL)

Transition time, CLKIN

5

0.6

5

0.6

t(CLKIN)

†

‡

The reference points for the rise and fall transitions are measured at 20% and 80%, respectively, of V

C = CLKIN cycle time in ns. For example, when CLKIN frequency is 10 MHz, use C = 100 ns.

.

IH

†‡

timing requirements for CLKIN (’C6701-120 device only) (see Figure 8)

’C6701-120

CLKMODE = x4 CLKMODE = x1

NO.

UNIT

MIN

33.3

0.4C

MAX

MIN

8.3

MAX

1

2

3

4

t

Cycle time, CLKIN

ns

c(CLKIN)

w(CLKINH)

w(CLKINL)

t(CLKIN)

Pulse duration, CLKIN high

Pulse duration, CLKIN low

Transition time, CLKIN

0.45C

5

0.6

†

‡

The reference points for the rise and fall transitions are measured at 20% and 80%, respectively, of V

C = CLKIN cycle time in ns. For example, when CLKIN frequency is 10 MHz, use C = 100 ns.

.

IH

1

4

2

CLKIN

3

4

Figure 8. CLKIN Timings

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SPRS067E – MAY 1998 – REVISED MAY 2000

INPUT AND OUTPUT CLOCKS (CONTINUED)

†‡

switching characteristics for CLKOUT1 (see Figure 9)

’C6701-120

’C6701-150

’C6701-167

NO.

PARAMETER

UNIT

CLKMODE = x4

CLKMODE = x1

MIN

MAX

MIN

MAX

P + 0.7

1

2

3

4

t

Cycle time, CLKOUT1

P – 0.7

P + 0.7

P – 0.7

ns

c(CKO1)

w(CKO1H)

w(CKO1L)

t(CKO1)

Pulse duration, CLKOUT1 high

Pulse duration, CLKOUT1 low

Transition time, CLKOUT1

(P/2) – 0.5 (P/2) + 0.5 PH – 0.5 PH + 0.5

(P/2) – 0.5 (P/2) + 0.5 PL – 0.5 PL + 0.5

0.6

†

‡

P = 1/CPU clock frequency in nanoseconds (ns).

PH is the high period of CLKIN in ns and PL is the low period of CLKIN in ns.

1

4

2

CLKOUT1

3

4

Figure 9. CLKOUT1 Timings

§

switching characteristics for CLKOUT2 (see Figure 10)

’C6701-120

’C6701-150

’C6701-167

NO.

PARAMETER

UNIT

MIN

MAX

1

2

3

4

t

Cycle time, CLKOUT2

2P – 0.7

P – 0.7

2P + 0.7

P + 0.7

0.6

ns

c(CKO2)

w(CKO2H)

w(CKO2L)

t(CKO2)

Pulse duration, CLKOUT2 high

Pulse duration, CLKOUT2 low

Transition time, CLKOUT2

§

P = 1/CPU clock frequency in ns.

1

4

2

CLKOUT2

3

4

Figure 10. CLKOUT2 Timings

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SPRS067E – MAY 1998 – REVISED MAY 2000

INPUT AND OUTPUT CLOCKS (CONTINUED)

SDCLK, SSCLK timing parameters

SDCLK timing parameters are the same as CLKOUT2 parameters.

SSCLK timing parameters are the same as CLKOUT1 or CLKOUT2 parameters, depending on SSCLK

configuration.

switching characteristics for the relation of SSCLK, SDCLK, and CLKOUT2 to CLKOUT1

(see Figure 11)

’C6701-120

’C6701-150

’C6701-167

NO.

PARAMETER

UNIT

MIN

–0.8

–1.0

–1.5

MAX

1

2

3

t

Delay time, CLKOUT1 edge to SSCLK edge

3.4

3.0

2.5

ns

d(CKO1-SSCLK)

d(CKO1-SSCLK1/2)

d(CKO1-CKO2)

Delay time, CLKOUT1 edge to SSCLK edge (1/2 clock rate)

Delay time, CLKOUT1 edge to CLKOUT2 edge

4

t

Delay time, CLKOUT1 edge to SDCLK edge

–1.5

1.9

ns

d(CKO1-SDCLK)

CLKOUT1

1

2

3

4

SSCLK

SSCLK (1/2rate)

CLKOUT2

SDCLK

Figure 11. Relation of CLKOUT2, SDCLK, and SSCLK to CLKOUT1

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SPRS067E – MAY 1998 – REVISED MAY 2000

ASYNCHRONOUS MEMORY TIMING

†

timing requirements for asynchronous memory cycles (see Figure 12 and Figure 13)

’C6701-120

’C6701-150

’C6701-167

NO.

UNIT

MIN MAX

6

7

t

Setup time, read EDx valid before CLKOUT1 high

Hold time, read EDx valid after CLKOUT1 high

Setup time, ARDY valid before CLKOUT1 high

Hold time, ARDY valid after CLKOUT1 high

4.5

1.5

3.5

1.5

ns

su(EDV-CKO1H)

h(CKO1H-EDV)

su(ARDY-CKO1H)

h(CKO1H-ARDY)

10

11

†

To ensure data setup time, simply program the strobe width wide enough. ARDY is internally synchronized. If ARDY does meet setup or hold

time, it may be recognized in the current cycle or the next cycle. Thus, ARDY can be an asynchronous input.

‡

switching characteristics for asynchronous memory cycles (see Figure 12 and Figure 13)

’C6701-120

’C6701-150

’C6701-167

NO.

PARAMETER

UNIT

MIN

MAX

1

2

t

Delay time, CLKOUT1 high to CEx valid

Delay time, CLKOUT1 high to BEx valid

Delay time, CLKOUT1 high to BEx invalid

Delay time, CLKOUT1 high to EAx valid

Delay time, CLKOUT1 high to EAx invalid

Delay time, CLKOUT1 high to AOE valid

Delay time, CLKOUT1 high to ARE valid

Delay time, CLKOUT1 high to EDx valid

Delay time, CLKOUT1 high to EDx invalid

Delay time, CLKOUT1 high to AWE valid

–1.0

4.5

ns

d(CKO1H-CEV)

d(CKO1H-BEV)

d(CKO1H-BEIV)

d(CKO1H-EAV)

d(CKO1H-EAIV)

d(CKO1H-AOEV)

d(CKO1H-AREV)

d(CKO1H-EDV)

d(CKO1H-EDIV)

d(CKO1H-AWEV)

3

–1.0

4

4.5

5

–1.0

–0.5

8

4.5

9

12

13

14

–1.0

4.5

‡

The minimum delay is also the minimum output hold after CLKOUT1 high.

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SPRS067E – MAY 1998 – REVISED MAY 2000

ASYNCHRONOUS MEMORY TIMING (CONTINUED)

Not ready = 2

Setup = 2

Strobe = 5

HOLD = 1

CLKOUT1

CEx

1

2

4

1

3

BE[3:0]

EA[21:2]

ED[31:0]

AOE

5

7

6

8

9

ARE

AWE

11

10

ARDY

Figure 12. Asynchronous Memory Read Timing

Not ready = 2

Setup = 2

Strobe = 5

HOLD = 1

CLKOUT1

1

2

4

1

3

5

CEx

BE[3:0]

EA[21:2]

12

13

14

ED[31:0]

AOE

ARE

14

AWE

11

10

ARDY

Figure 13. Asynchronous Memory Write Timing

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SPRS067E – MAY 1998 – REVISED MAY 2000

SYNCHRONOUS-BURST MEMORY TIMING

timing requirements for synchronous-burst SRAM cycles (full-rate SSCLK)

(see Figure 14)

’C6701-150

’C6701-167

’C6701-120

NO.

UNIT

MIN

2.0

MAX

MIN

2.0

MAX

7

8

t

Setup time, read EDx valid before SSCLK high

Hold time, read EDx valid after SSCLK high

ns

su(EDV-SSCLKH)

2.9

2.1

h(SSCLKH-EDV)

†

switching characteristics for synchronous-burst SRAM cycles (full-rate SSCLK)

(see Figure 14 and Figure 15)

’C6701-150

’C6701-167

’C6701-120

NO.

PARAMETER

UNIT

MIN

MAX

MIN

MAX

1

2

t

Output setup time, CEx valid before SSCLK high

Output hold time, CEx valid after SSCLK high

Output setup time, BEx valid before SSCLK high

Output hold time, BEx invalid after SSCLK high

Output setup time, EAx valid before SSCLK high

Output hold time, EAx invalid after SSCLK high

Output setup time, SSADS valid before SSCLK high

Output hold time, SSADS valid after SSCLK high

Output setup time, SSOE valid before SSCLK high

Output hold time, SSOE valid after SSCLK high

Output setup time, EDx valid before SSCLK high

Output hold time, EDx invalid after SSCLK high

Output setup time, SSWE valid before SSCLK high

0.5P – 1.3

0.5P – 2.9

0.5P – 1.3

0.5P – 2.9

0.5P – 1.3

0.5P – 2.9

0.5P – 1.3

0.5P – 2.9

0.5P – 1.3

0.5P – 2.9

0.5P – 1.3

0.5P – 2.9

0.5P – 1.3

0.5P – 2.3

0.5P – 1.6

0.5P – 2.3

0.5P – 1.7

0.5P – 2.3

0.5P – 1.3

0.5P – 2.3

0.5P – 1.3

0.5P – 2.3

0.5P – 1.3

0.5P – 2.3

0.5P – 1.3

ns

osu(CEV-SSCLKH)

oh(SSCLKH-CEV)

osu(BEV-SSCLKH)

oh(SSCLKH-BEIV)

osu(EAV-SSCLKH)

oh(SSCLKH-EAIV)

osu(ADSV-SSCLKH)

oh(SSCLKH-ADSV)

osu(OEV-SSCLKH)

oh(SSCLKH-OEV)

osu(EDV-SSCLKH)

oh(SSCLKH-EDIV)

osu(WEV-SSCLKH)

3

4

5

6

9

10

11

12

13

14

15

16

t

Output hold time, SSWE valid after SSCLK high

0.5P – 2.9

0.5P – 2.3

ns

oh(SSCLKH-WEV)

†

When the PLL is used (CLKMODE x4), P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns.

For CLKMODE x1, 0.5P is defined as PH (pulse duration of CLKIN high) for all output setup times; 0.5P is defined as PL (pulse duration of CLKIN

low) for all output hold times.

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SPRS067E – MAY 1998 – REVISED MAY 2000

SYNCHRONOUS-BURST MEMORY TIMING (CONTINUED)

SSCLK

CEx

1

2

3

5

4

BE[3:0]

BE1

A1

BE2

BE3

BE4

6

EA[21:2]

A2

7

A3

8

A4

Q1

Q2

Q3

Q4

ED[31:0]

SSADS

9

10

11

12

SSOE

SSWE

Figure 14. SBSRAM Read Timing (Full-Rate SSCLK)

SSCLK

1

3

2

CEx

BE[3:0]

4

BE1

A1

BE2

A2

BE3

A3

BE4

5

6

EA[21:2]

A4

13

14

D4

ED[31:0]

D1

D2

D3

9

10

SSADS

SSOE

15

16

SSWE

Figure 15. SBSRAM Write Timing (Full-Rate SSCLK)

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SPRS067E – MAY 1998 – REVISED MAY 2000

SYNCHRONOUS-BURST MEMORY TIMING (CONTINUED)

timing requirements for synchronous-burst SRAM cycles (half-rate SSCLK) (see Figure 16)

’C6701-120

’C6701-150

’C6701-167

NO.

UNIT

MIN

3.6

MAX

7

8

t

Setup time, read EDx valid before SSCLK high

Hold time, read EDx valid after SSCLK high

ns

su(EDV-SSCLKH)

1.5

h(SSCLKH-EDV)

†

switching characteristics for synchronous-burst SRAM cycles (half-rate SSCLK)

(see Figure 16 and Figure 17)

’C6701-150

’C6701-167

’C6701-120

NO.

PARAMETER

UNIT

MIN

MAX

MIN

MAX

1

2

t

Output setup time, CEx valid before SSCLK high

Output hold time, CEx valid after SSCLK high

Output setup time, BEx valid before SSCLK high

Output hold time, BEx invalid after SSCLK high

Output setup time, EAx valid before SSCLK high

Output hold time, EAx invalid after SSCLK high

Output setup time, SSADS valid before SSCLK high

Output hold time, SSADS valid after SSCLK high

Output setup time, SSOE valid before SSCLK high

Output hold time, SSOE valid after SSCLK high

Output setup time, EDx valid before SSCLK high

Output hold time, EDx invalid after SSCLK high

Output setup time, SSWE valid before SSCLK high

1.5P – 4.5

0.5P – 2.5

1.5P – 4.5

0.5P – 2.5

1.5P – 4.5

0.5P – 2.5

1.5P – 4.5

0.5P – 2.5

1.5P – 4.5

0.5P – 2.5

1.5P – 4.5

0.5P – 2.5

1.5P – 4.5

0.5P – 2

ns

osu(CEV-SSCLKH)

oh(SSCLKH-CEV)

osu(BEV-SSCLKH)

oh(SSCLKH-BEIV)

osu(EAV-SSCLKH)

oh(SSCLKH-EAIV)

osu(ADSV-SSCLKH)

oh(SSCLKH-ADSV)

osu(OEV-SSCLKH)

oh(SSCLKH-OEV)

osu(EDV-SSCLKH)

oh(SSCLKH-EDIV)

osu(WEV-SSCLKH)

3

1.5P – 4.5

0.5P – 2

4

5

1.5P – 4.5

0.5P – 2

6

9

1.5P – 4.5

0.5P – 2

10

11

12

13

14

15

1.5P – 4.5

0.5P – 2

1.5P – 4.5

0.5P – 2

1.5P – 4.5

16

t

Output hold time, SSWE valid after SSCLK high

0.5P – 2.5

0.5P – 2

ns

oh(SSCLKH-WEV)

†

When the PLL is used (CLKMODE x4), P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns.

For CLKMODE x1:

1.5P = P + PH, where P = 1/CPU clock frequency, and PH = pulse duration of CLKIN high.

0.5P = PL, where PL = pulse duration of CLKIN low.

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P R O C E S S O R

SPRS067E – MAY 1998 – REVISED MAY 2000

SYNCHRONOUS-BURST MEMORY TIMING (CONTINUED)

SSCLK

CEx

1

2

3

4

6

BE[3:0]

BE1

BE2

A2

BE3

A3

BE4

5

A1

A4

8

EA[21:2]

ED[31:0]

SSADS

7

Q1

Q2

Q3

10

Q4

9

11

12

SSOE

SSWE

Figure 16. SBSRAM Read Timing (1/2 Rate SSCLK)

SSCLK

1

3

2

CEx

BE[3:0]

4

6

BE1

BE2

A2

BE3

A3

BE4

A4

5

EA[21:2]

A1

13

14

10

Q1

Q2

Q3

Q4

ED[31:0]

9

SSADS

SSOE

15

16

SSWE

Figure 17. SBSRAM Write Timing (1/2 Rate SSCLK)

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P R O C E S S O R

SPRS067E – MAY 1998 – REVISED MAY 2000

SYNCHRONOUS DRAM TIMING

timing requirements for synchronous DRAM cycles (see Figure 18)

’C6701-120

’C6701-150

’C6701-167

NO.

UNIT

MIN MAX

7

8

t

Setup time, read EDx valid before SDCLK high

Hold time, read EDx valid after SDCLK high

1.8

3

ns

su(EDV-SDCLKH)

h(SDCLKH-EDV)

†

switching characteristics for synchronous DRAM cycles (see Figure 18–Figure 23)

’C6701-150

’C6701-167

’C6701-120

NO.

PARAMETER

UNIT

MIN

MAX

MIN

MAX

1

2

3

4

5

6

t

Output setup time, CEx valid before SDCLK high

Output hold time, CEx valid after SDCLK high

Output setup time, BEx valid before SDCLK high

Output hold time, BEx invalid after SDCLK high

Output setup time, EAx valid before SDCLK high

Output hold time, EAx invalid after SDCLK high

1.5P – 4

0.5P – 1.9

1.5P – 4

0.5P – 1.9

1.5P – 4

0.5P – 1.9

1.5P – 4

0.5P – 1.5

1.5P – 4

0.5P – 1.5

1.5P – 4

0.5P – 1.5

ns

osu(CEV-SDCLKH)

oh(SDCLKH-CEV)

osu(BEV-SDCLKH)

oh(SDCLKH-BEIV)

osu(EAV-SDCLKH)

oh(SDCLKH-EAIV)

Output setup time, SDCAS valid before SDCLK

high

9

t

1.5P – 4

ns

osu(SDCAS-SDCLKH)

10

11

12

13

14

15

16

t

Output hold time, SDCAS valid after SDCLK high

Output setup time, EDx valid before SDCLK high

Output hold time, EDx invalid after SDCLK high

Output setup time, SDWE valid before SDCLK high

Output hold time, SDWE valid after SDCLK high

Output setup time, SDA10 valid before SDCLK high

Output hold time, SDA10 invalid after SDCLK high

0.5P – 1.9

1.5P – 4

0.5P – 1.5

1.5P – 4

ns

oh(SDCLKH-SDCAS)

osu(EDV-SDCLKH)

oh(SDCLKH-EDIV)

0.5P – 1.9

1.5P – 4

0.5P – 1.5

1.5P – 4

osu(SDWE-SDCLKH)

oh(SDCLKH-SDWE)

osu(SDA10V-SDCLKH)

oh(SDCLKH-SDA10IV)

0.5P – 1.9

1.5P – 4

0.5P – 1.5

1.5P – 4

0.5P – 1.9

0.5P – 1.5

Output setup time, SDRAS valid before SDCLK

high

17

18

t

1.5P – 4

ns

osu(SDRAS-SDCLKH)

oh(SDCLKH-SDRAS)

t

Output hold time, SDRAS valid after SDCLK high

0.5P – 1.9

0.5P – 1.5

†

When the PLL is used (CLKMODE x4), P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns.

For CLKMODE x1:

1.5P = P + PH, where P = 1/CPU clock frequency, and PH = pulse duration of CLKIN high.

0.5P = PL, where PL = pulse duration of CLKIN low.

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P R O C E S S O R

SPRS067E – MAY 1998 – REVISED MAY 2000

SYNCHRONOUS DRAM TIMING (CONTINUED)

READ

SDCLK

1

5

2

CEx

3

4

BE[3:0]

BE1

BE2

CA3

BE3

7

6

CA1

CA2

EA[15:2]

ED[31:0]

8

D1

D2

D3

15

9

16

10

SDA10

SDRAS

SDCAS

SDWE

Figure 18. Three SDRAM Read Commands

WRITE

SDCLK

CEx

1

2

3

4

BE1

CA1

BE2

CA2

D2

BE3

CA3

D3

BE[3:0]

EA[15:2]

ED[31:0]

5

6

11

12

D1

15

16

SDA10

SDRAS

9

10

14

SDCAS

SDWE

13

Figure 19. Three SDRAM Write Commands

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P R O C E S S O R

SPRS067E – MAY 1998 – REVISED MAY 2000

SYNCHRONOUS DRAM TIMING (CONTINUED)

ACTV

SDCLK

1

2

CEx

BE[3:0]

5

Bank Activate/Row Address

EA[15:2]

ED[31:0]

15

Row Address

SDA10

17

18

SDRAS

SDCAS

SDWE

Figure 20. SDRAM ACTV Command

DCAB

SDCLK

1

2

CEx

BE[3:0]

EA[15:2]

ED[31:0]

15

16

SDA10

17

18

SDRAS

SDCAS

13

14

SDWE

Figure 21. SDRAM DCAB Command

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P R O C E S S O R

SPRS067E – MAY 1998 – REVISED MAY 2000

SYNCHRONOUS DRAM TIMING (CONTINUED)

REFR

SDCLK

1

2

CEx

BE[3:0]

EA[15:2]

ED[31:0]

SDA10

SDRAS

17

18

9

10

SDCAS

SDWE

Figure 22. SDRAM REFR Command

MRS

SDCLK

1

2

6

CEx

BE[3:0]

5

MRS Value

EA[15:2]

ED[31:0]

SDA10

SDRAS

17

18

10

14

9

SDCAS

SDWE

13

Figure 23. SDRAM MRS Command

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P R O C E S S O R

SPRS067E – MAY 1998 – REVISED MAY 2000

HOLD/HOLDA TIMING

†

timing requirements for the hold/hold acknowledge cycles (see Figure 24)

’C6701-120

’C6701-150

’C6701-167

NO.

UNIT

MIN MAX

1

2

t

Setup time, HOLD high before CLKOUT1 high

Hold time, HOLD low after CLKOUT1 high

5

2

ns

su(HOLDH-CKO1H)

h(CKO1H-HOLDL)

†

HOLD is synchronized internally. Therefore, if setup and hold times are not met, it will either be recognized in the current cycle or in the next cycle.

Thus, HOLD can be an asynchronous input.

‡

switching characteristics for the hold/hold acknowledge cycles (see Figure 24)

’C6701-120

’C6701-150

’C6701-167

NO.

PARAMETER

UNIT

MIN

MAX

§

3

4

5

6

7

8

9

t

Response time, HOLD low to EMIF high impedance

Response time, EMIF high impedance to HOLDA low

Response time, HOLD high to HOLDA high

4P

ns

R(HOLDL-EMHZ)

R(EMHZ-HOLDAL)

R(HOLDH-HOLDAH)

d(CKO1H-HOLDAL)

d(CKO1H-BHZ)

2P

7P

8

4P

1

Delay time, CLKOUT1 high to HOLDA valid

¶

Delay time, CLKOUT1 high to EMIF Bus high impedance

1

8

¶

Delay time, CLKOUT1 high to EMIF Bus low impedance

1

12

6P

d(CKO1H-BLZ)

¶

Response time, HOLD high to EMIF Bus low impedance

3P

R(HOLDH-BLZ)

‡

§

P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns.

All pending EMIF transactions are allowed to complete before HOLDA is asserted. The worst cases for this is an asynchronous read or write

with external ARDY used or a minimum of eight consecutive SDRAM reads or writes when RBTR8 = 1. If no bus transactions are occurring, then

the minimum delay time can be achieved. Also, bus hold can be indefinitely delayed by setting the NOHOLD = 1.

¶

EMIF Bus consists of CE[3:0], BE[3:0], ED[31:0], EA[21:2], ARE, AOE, AWE, SSADS, SSOE, SSWE, SDA10, SDRAS, SDCAS, and SDWE.

DSP Owns Bus

External Requester

DSP Owns Bus

5

4

9

2

3

CLKOUT1

HOLD

2

1

6

HOLDA

7

8

†

EMIF Bus

’C6701

Ext Req

’C6701

†

EMIF Bus consists of CE[3:0], BE[3:0], ED[31:0], EA[21:2], ARE, AOE, AWE, SSADS, SSOE, SSWE, SDA10, SDRAS, SDCAS, and SDWE.

Figure 24. HOLD/HOLDA Timing

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SPRS067E – MAY 1998 – REVISED MAY 2000

RESET TIMING

timing requirements for reset (see Figure 25)

’C6701-120

’C6701-150

’C6701-167

NO.

UNIT

MIN

MAX

CLKOUT1

cycles

†

Width of the RESET pulse (PLL stable)

10

1

t

w(RESET)

‡

Width of the RESET pulse (PLL needs to sync up)

250

µs

†

‡

This parameter applies to CLKMODE x1 when CLKIN is stable and applies to CLKMODE x4 when CLKIN and PLL are stable.

This parameter only applies to CLKMODE x4. The RESET signal is not connected internally to the clock PLL circuit. The PLL, however, may

need up to 250 µs to stabilize following device powerup or after PLL configuration has been changed. During that time, RESET must be asserted

to ensure proper device operation. See the clock PLL section for PLL lock times.

§¶

switching characteristics during reset (see Figure 25)

’C6701-120

’C6701-150

’C6701-167

NO.

PARAMETER

UNIT

MIN

MAX

CLKOUT1

cycles

2

t

Response time to change of value in RESET signal

1

R(RESET)

3

4

t

Delay time, CLKOUT1 high to CLKOUT2 invalid

Delay time, CLKOUT1 high to CLKOUT2 valid

Delay time, CLKOUT1 high to SDCLK invalid

Delay time, CLKOUT1 high to SDCLK valid

Delay time, CLKOUT1 high to SSCLK invalid

Delay time, CLKOUT1 high to SSCLK valid

Delay time, CLKOUT1 high to low group invalid

Delay time, CLKOUT1 high to low group valid

Delay time, CLKOUT1 high to high group invalid

Delay time, CLKOUT1 high to high group valid

Delay time, CLKOUT1 high to Z group high impedance

Delay time, CLKOUT1 high to Z group valid

–1

ns

d(CKO1H-CKO2IV)

d(CKO1H-CKO2V)

d(CKO1H-SDCLKIV)

d(CKO1H-SDCLKV)

d(CKO1H-SSCKIV)

d(CKO1H-SSCKV)

d(CKO1H-LOWIV)

d(CKO1H-LOWV)

d(CKO1H-HIGHIV)

d(CKO1H-HIGHV)

d(CKO1H-ZHZ)

10

5

–1

6

7

8

9

10

11

12

13

14

d(CKO1H-ZV)

§

¶

Low group consists of:

High group consists of:

Z group consists of:

IACK, INUM[3:0], DMAC[3:0], PD, TOUT0, and TOUT1.

HINT.

EA[21:2], ED[31:0], CE[3:0], BE[3:0], ARE, AWE, AOE, SSADS, SSOE, SSWE, SDA10, SDRAS, SDCAS,

SDWE, HD[15:0], CLKX0, CLKX1, FSX0, FSX1, DX0, DX1, CLKR0, CLKR1, FSR0, and FSR1.

HRDY is gated by input HCS.

If HCS = 0 at device reset, HRDY belongs to the high group.

If HCS = 1 at device reset, HRDY belongs to the low group.

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P R O C E S S O R

SPRS067E – MAY 1998 – REVISED MAY 2000

RESET TIMING (CONTINUED)

CLKOUT1

1

2

RESET

CLKOUT2

SDCLK

3

5

4

6

7

8

SSCLK

9

10

12

14

†‡

LOW GROUP

HIGH GROUP

Z GROUP

11

13

†‡

†

‡

Low group consists of:

High group consists of:

Z group consists of:

IACK, INUM[3:0], DMAC[3:0], PD, TOUT0, and TOUT1.

HINT.

EA[21:2], ED[31:0], CE[3:0], BE[3:0], ARE, AWE, AOE, SSADS, SSOE, SSWE, SDA10, SDRAS, SDCAS,

SDWE, HD[15:0], CLKX0, CLKX1, FSX0, FSX1, DX0, DX1, CLKR0, CLKR1, FSR0, and FSR1.

HRDY is gated by input HCS.

If HCS = 0 at device reset, HRDY belongs to the high group.

If HCS = 1 at device reset, HRDY belongs to the low group.

Figure 25. Reset Timing

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SPRS067E – MAY 1998 – REVISED MAY 2000

EXTERNAL INTERRUPT TIMING

†‡

timing requirements for interrupt response cycles (see Figure 26)

’C6701-120

’C6701-150

’C6701-167

NO.

UNIT

MIN

2P

MAX

2

3

t

Width of the interrupt pulse low

Width of the interrupt pulse high

ns

w(ILOW)

2P

w(IHIGH)

†

‡

Interrupt signals are synchronized internally and are potentially recognized one cycle later if setup and hold times are violated. Thus, they can

be connected to asynchronous inputs.

P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns.

§

switching characteristics during interrupt response cycles (see Figure 26)

’C6701-120

’C6701-150

’C6701-167

NO.

PARAMETER

UNIT

MIN

9P

MAX

1

4

5

6

t

Response time, EXT_INTx high to IACK high

Delay time, CLKOUT2 low to IACK valid

Delay time, CLKOUT2 low to INUMx valid

Delay time, CLKOUT2 low to INUMx invalid

ns

R(EINTH-IACKH)

d(CKO2L-IACKV)

d(CKO2L-INUMV)

d(CKO2L-INUMIV)

–0.5P 13 – 0.5P

10 – 0.5P

–0.5P

§

P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns.

When the PLL is used (CLKMODE x4), 0.5P = 1/(2 × CPU clock frequency).

For CLKMODE x1: 0.5P = PH, where PH is the high period of CLKIN.

1

CLKOUT2

3

2

EXT_INTx, NMI

Intr Flag

4

IACK

6

5

Interrupt Number

INUMx

Figure 26. Interrupt Timing

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SPRS067E – MAY 1998 – REVISED MAY 2000

HOST-PORT INTERFACE TIMING

†‡

timing requirements for host-port interface cycles (see Figure 27, Figure 28, Figure 29, and

Figure 30)

’C6701-120

’C6701-150

’C6701-167

NO.

UNIT

MIN

4

MAX

§

1

2

t

Setup time, select signals valid before HSTROBE low

ns

su(SEL-HSTBL)

h(HSTBL-SEL)

w(HSTBL)

§

Hold time, select signals valid after HSTROBE low

2

3

Pulse duration, HSTROBE low

2P

4

Pulse duration, HSTROBE high between consecutive accesses

w(HSTBH)

§

Setup time, select signals valid before HAS low

10

11

12

13

su(SEL-HASL)

h(HASL-SEL)

su(HDV-HSTBH)

h(HSTBH-HDV)

§

Hold time, select signals valid after HAS low

2

Setup time, host data valid before HSTROBE high

Hold time, host data valid after HSTROBE high

3

2

Hold time, HSTROBE low after HRDY low. HSTROBE should not be inacti-

vated until HRDY is active (low); otherwise, HPI writes will not complete

properly.

14

t

1

ns

h(HRDYL-HSTBL)

18

19

t

Setup time, HAS low before HSTROBE low

Hold time, HAS low after HSTROBE low

2

ns

su(HASL-HSTBL)

h(HSTBL-HASL)

†

‡

§

HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.

P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns.

Select signals include: HCNTRL[1:0], HR/W, and HHWIL.

†‡

switching characteristics during host-port interface cycles (see Figure 27, Figure 28, Figure 29,

and Figure 30)

’C6701-120

’C6701-150

’C6701-167

NO.

PARAMETER

UNIT

MIN MAX

¶

5

6

t

Delay time, HCS to HRDY

1

4

12

ns

d(HCS-HRDY)

#

Delay time, HSTROBE low to HRDY high

d(HSTBL-HRDYH)

d(HSTBL-HDLZ)

d(HDV-HRDYL)

oh(HSTBH-HDV)

d(HSTBH-HDHZ)

d(HSTBL-HDV)

d(HSTBH-HRDYH)

d(HASL-HRDYH)

7

Delay time, HSTROBE low to HD low impedance for an HPI read

Delay time, HD valid to HRDY low

8

P – 3 P + 3

9

Output hold time, HD valid after HSTROBE high

Delay time, HSTROBE high to HD high impedance

Delay time, HSTROBE low to HD valid

3

1

3

12

15

16

17

20

||

Delay time, HSTROBE high to HRDY high

Delay time, HAS low to HRDY high

†

‡

¶

HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.

P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns.

HCS enables HRDY, and HRDY is always low when HCS is high. The case where HRDY goes high when HCS falls indicates that HPI is busy

completing a previous HPID write or READ with autoincrement.

#

||

This parameter is used during an HPID read. At the beginning of the first half-word transfer on the falling edge of HSTROBE, the HPI sends the

request to the DMA auxiliary channel, and HRDY remains high until the DMA auxiliary channel loads the requested data into HPID.

This parameter is used after the second half-word of an HPID write or autoincrement read. HRDY remains low if the access is not an HPID write

or autoincrement read. Reading or writing to HPIC or HPIA does not affect the HRDY signal.

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P R O C E S S O R

SPRS067E – MAY 1998 – REVISED MAY 2000

HOST-PORT INTERFACE TIMING (CONTINUED)

HAS

HCNTL[1:0]

HR/W

1

2

1

HHWIL

4

3

†

HSTROBE

HCS

15

9

15

9

7

16

HD[15:0] (output)

HRDY (case 1)

HRDY (case 2)

5

1st half-word

2nd half-word

5

8

17

6

†

HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.

Figure 27. HPI Read Timing (HAS Not Used, Tied High)

HAS

19

11

19

11

10

HCNTL[1:0]

HR/W

11

10

HHWIL

4

3

†

HSTROBE

18

HCS

15

7

9

16

9

17

HD[15:0] (output)

HRDY (case 1)

HRDY (case 2)

1st half-word

2nd half-word

5

8

5

20

†

HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.

Figure 28. HPI Read Timing (HAS Used)

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P R O C E S S O R

SPRS067E – MAY 1998 – REVISED MAY 2000

HOST-PORT INTERFACE TIMING (CONTINUED)

HAS

1

2

HCNTL[1:0]

HBE[1:0]

12

13

1

2

HR/W

HHWIL

3

4

14

†

HSTROBE

HCS

HD[15:0] (input)

HRDY

12

13

2nd half-word

13

17

1st half-word

5

†

HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.

Figure 29. HPI Write Timing (HAS Not Used, Tied High)

HAS

HBE[1:0]

12

19

13

19

13

11

10

HCNTL[1:0]

10

HR/W

HHWIL

3

4

14

†

HSTROBE

18

12

18

HCS

HD[15:0] (input)

HRDY

12

13

1st half-word

2nd half-word

5

17

†

HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.

Figure 30. HPI Write Timing (HAS Used)

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SPRS067E – MAY 1998 – REVISED MAY 2000

MULTICHANNEL BUFFERED SERIAL PORT TIMING

†‡

timing requirements for McBSP (see Figure 31)

’C6701-120

’C6701-150

’C6701-167

NO.

UNIT

MIN

MAX

§

2

3

t

Cycle time, CLKR/X

CLKR/X ext

CLKR int

CLKR ext

CLKR int

CLKR ext

CLKR int

CLKR ext

CLKR int

CLKR ext

CLKX int

CLKX ext

CLKX int

CLKX ext

2P

ns

c(CKRX)

¶

Pulse duration, CLKR/X high or CLKR/X low

P – 1

w(CKRX)

13

4

5

6

t

Setup time, external FSR high before CLKR low

Hold time, external FSR high after CLKR low

Setup time, DR valid before CLKR low

ns

su(FRH-CKRL)

h(CKRL-FRH)

su(DRV-CKRL)

h(CKRL-DRV)

su(FXH-CKXL)

h(CKXL-FXH)

7

4

10

1

7

4

8

Hold time, DR valid after CLKR low

4

13

4

10

11

Setup time, external FSX high before CLKX low

Hold time, external FSX high after CLKX low

7

3

†

‡

§

P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns.

CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also inverted.

The maximum McBSP bit rate is 50 MHz; therefore, the minimum CLKR/X clock cycle is either twice the CPU cycle time (2P), or 20 ns (50 MHz),

whichever value is larger. For example, when running parts at 167 MHz (P = 6 ns), use 20 ns as the minimum CLKR/X clock cycle (by setting

the appropriate CLKGDV ratio or external clock source). When running parts at 80 MHz (P = 12.5 ns), use 2P = 25 ns (40 MHz) as the minimum

CLKR/X clock cycle. The maximum McBSP bit rate applies when the serial port is a master of clock and frame syncs and the other device the

McBSP communicates to is a slave.

The minimum CLKR/X pulse duration is either (P–1) or 9 ns, whichever is larger. For example, when running parts at 167 MHz (P = 6 ns), use

9 ns as the minimum CLKR/X pulse duration. When running parts at 80 MHz (P = 12.5 ns), use (P–1) = 11.5 ns as the minimum CLKR/X pulse

duration.

¶

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P R O C E S S O R

SPRS067E – MAY 1998 – REVISED MAY 2000

MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)

†‡

switching characteristics for McBSP (see Figure 31)

’C6701-120

’C6701-150

’C6701-167

NO.

PARAMETER

UNIT

MIN

MAX

Delay time, CLKS high to CLKR/X high for internal

CLKR/X generated from CLKS input

1

t

3

15

ns

d(CKSH-CKRXH)

§¶

2

3

4

t

Cycle time, CLKR/X

CLKR/X int

CLKR int

CLKX int

CLKX ext

CLKX int

CLKX ext

CLKX int

CLKX ext

FSX int

2P

ns

c(CKRX)

#

Pulse duration, CLKR/X high or CLKR/X low

Delay time, CLKR high to internal FSR valid

C – 1

C + 1

w(CKRX)

–4

3

4

5

d(CKRH-FRV)

9

t

Delay time, CLKX high to internal FSX valid

ns

d(CKXH-FXV)

dis(CKXH-DXHZ)

d(CKXH-DXV)

d(FXH-DXV)

16

2

–3

2

Disable time, DX high impedance following last data bit from

CLKX high

12

13

14

9

–2

3

4

Delay time, CLKX high to DX valid.

16

4

–2

2

Delay time, FSX high to DX valid.

ONLY applies when in data delay 0 (XDATDLY = 00b) mode.

FSX ext

10

†

‡

§

¶

CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also inverted.

Minimum delay times also represent minimum output hold times.

P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns.

The maximum McBSP bit rate is 50 MHz; therefore, the minimum CLKR/X clock cycle is either twice the CPU cycle time (2P), or 20 ns (50 MHz),

whichever value is larger. For example, when running parts at 167 MHz (P = 6 ns), use 20 ns as the minimum CLKR/X clock cycle (by setting

the appropriate CLKGDV ratio or external clock source). When running parts at 80 MHz (P = 12.5 ns), use 2P = 25 ns (40 MHz) as the minimum

CLKR/X clock cycle. The maximum McBSP bit rate applies when the serial port is a master of clock and frame syncs and the other device the

McBSP communicates to is a slave.

#

C = H or L

S = sample rate generator input clock = P if CLKSM = 1 (P = 1/CPU clock frequency)

=

sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)

H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even

= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero

L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even

= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero

CLKGDV should be set appropriately to ensure the McBSP bit rate does not exceed the 50 MHz limit.

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P R O C E S S O R

SPRS067E – MAY 1998 – REVISED MAY 2000

MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)

CLKS

1

2

3

CLKR

4

FSR (int)

5

6

FSR (ext)

7

8

DR

Bit(n-1)

(n-2)

(n-3)

2

3

CLKX

9

FSX (int)

11

10

FSX (ext)

FSX (XDATDLY=00b)

13

(n-2)

14

13

12

DX

Bit 0

Bit(n-1)

(n-3)

Figure 31. McBSP Timings

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P R O C E S S O R

SPRS067E – MAY 1998 – REVISED MAY 2000

MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)

timing requirements for FSR when GSYNC = 1 (see Figure 32)

’C6701-120

’C6701-150

’C6701-167

NO.

UNIT

MIN

4

MAX

1

2

t

Setup time, FSR high before CLKS high

Hold time, FSR high after CLKS high

ns

su(FRH-CKSH)

4

h(CKSH-FRH)

CLKS

1

2

FSR external

CLKR/X (no need to resync)

CLKR/X(needs resync)

Figure 32. FSR Timing When GSYNC = 1

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P R O C E S S O R

SPRS067E – MAY 1998 – REVISED MAY 2000

MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)

†‡

timing requirements for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 0 (see Figure 33)

’C6701-120

’C6701-150

’C6701-167

NO.

UNIT

MASTER

SLAVE

MIN

12

4

MAX

4

5

t

Setup time, DR valid before CLKX low

Hold time, DR valid after CLKX low

2 – 3P

5 + 6P

ns

su(DRV-CKXL)

h(CKXL-DRV)

†

‡

P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns.

For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.

†‡

switching characteristics for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 0

(see Figure 33)

’C6701-120

’C6701-150

’C6701-167

NO.

PARAMETER

UNIT

§

MASTER

SLAVE

MIN

MIN MAX

MAX

¶

1

2

3

t

Hold time, FSX low after CLKX low

T – 4 T + 4

L – 4 L + 4

ns

h(CKXL-FXL)

d(FXL-CKXH)

d(CKXH-DXV)

#

Delay time, FSX low to CLKX high

Delay time, CLKX high to DX valid

–4

4

3P + 1 5P + 17

Disable time, DX high impedance following last data bit from

CLKX low

6

t

L – 2 L + 3

ns

dis(CKXL-DXHZ)

Disable time, DX high impedance following last data bit from FSX

high

7

8

t

P + 4 3P + 17

2P + 1 4P + 13

ns

dis(FXH-DXHZ)

Delay time, FSX low to DX valid

d(FXL-DXV)

†

‡

§

P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns.

For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.

S = sample rate generator input clock = P if CLKSM = 1 (P = 1/CPU clock frequency)

=

sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)

T = CLKX period = (1 + CLKGDV) * S

H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even

= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero

L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even

= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero

FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX

and FSR is inverted before being used internally.

CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP

CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP

¶

#

FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock

(CLKX).

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P R O C E S S O R

SPRS067E – MAY 1998 – REVISED MAY 2000

MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)

CLKX

FSX

1

2

8

7

6

3

DX

DR

Bit 0

Bit(n-1)

(n-2)

(n-3)

(n-4)

4

5

Bit 0

(n-2)

(n-3)

(n-4)

Figure 33. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0

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P R O C E S S O R

SPRS067E – MAY 1998 – REVISED MAY 2000

MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)

†‡

timing requirements for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 0 (see Figure 34)

’C6701-120

’C6701-150

’C6701-167

NO.

UNIT

MASTER

SLAVE

MIN

12

4

MAX

4

5

t

Setup time, DR valid before CLKX high

Hold time, DR valid after CLKX high

2 – 3P

5 + 6P

ns

su(DRV-CKXH)

h(CKXH-DRV)

†

‡

P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns.

For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.

†‡

switching characteristics for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 0

(see Figure 34)

’C6701-120

’C6701-150

’C6701-167

NO.

PARAMETER

UNIT

§

MASTER

SLAVE

MIN

MIN MAX

MAX

¶

1

2

3

t

Hold time, FSX low after CLKX low

L – 4 L + 4

T – 4 T + 4

ns

h(CKXL-FXL)

d(FXL-CKXH)

d(CKXL-DXV)

#

Delay time, FSX low to CLKX high

Delay time, CLKX low to DX valid

–4

4

3P + 1 5P + 17

3P + 4 5P + 17

Disable time, DX high impedance following last data bit from

CLKX low

6

t

–2

4

ns

dis(CKXL-DXHZ)

7

t

Delay time, FSX low to DX valid

H – 2 H + 3

2P + 1 4P + 13

d(FXL-DXV)

†

‡

§

P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns.

For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.

S = sample rate generator input clock = P if CLKSM = 1 (P = 1/CPU clock frequency)

=

sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)

T = CLKX period = (1 + CLKGDV) * S

H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even

= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero

L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even

= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero

FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX

and FSR is inverted before being used internally.

CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP

CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP

¶

#

FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock

(CLKX).

CLKX

1

2

7

FSX

DX

6

3

Bit 0

Bit(n-1)

(n-2)

(n-3)

(n-4)

4

5

DR

Bit 0

(n-2)

(n-4)

Figure 34. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0

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P R O C E S S O R

SPRS067E – MAY 1998 – REVISED MAY 2000

MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)

†‡

timing requirements for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 1 (see Figure 35)

’C6701-120

’C6701-150

’C6701-167

NO.

UNIT

MASTER

SLAVE

MIN

12

4

MAX

4

5

t

Setup time, DR valid before CLKX high

Hold time, DR valid after CLKX high

2 – 3P

5 + 6P

ns

su(DRV-CKXH)

h(CKXH-DRV)

†

‡

P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns.

For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.

†‡

switching characteristics for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 1

(see Figure 35)

’C6701-120

’C6701-150

’C6701-167

NO.

PARAMETER

UNIT

§

MASTER

SLAVE

MIN

MIN MAX

MAX

¶

1

2

3

t

Hold time, FSX low after CLKX high

T – 4 T + 4

H – 4 H + 4

ns

h(CKXH-FXL)

d(FXL-CKXL)

d(CKXL-DXV)

#

Delay time, FSX low to CLKX low

Delay time, CLKX low to DX valid

–4

4

3P + 1 5P + 17

Disable time, DX high impedance following last data bit from

CLKX high

6

t

H – 2 H + 3

ns

dis(CKXH-DXHZ)

Disable time, DX high impedance following last data bit from

FSX high

7

8

t

P + 4 3P + 17

2P + 1 4P + 13

ns

dis(FXH-DXHZ)

Delay time, FSX low to DX valid

d(FXL-DXV)

†

‡

§

P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns.

For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.

S = sample rate generator input clock = P if CLKSM = 1 (P = 1/CPU clock frequency)

=

sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)

T = CLKX period = (1 + CLKGDV) * S

H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even

= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero

L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even

= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero

FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX

and FSR is inverted before being used internally.

CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP

CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP

¶

#

FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock

(CLKX).

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P R O C E S S O R

SPRS067E – MAY 1998 – REVISED MAY 2000

MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)

CLKX

FSX

1

2

8

7

6

3

DX

DR

Bit 0

Bit(n-1)

(n-2)

(n-3)

(n-4)

4

5

Bit 0

(n-2)

(n-3)

(n-4)

Figure 35. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1

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P R O C E S S O R

SPRS067E – MAY 1998 – REVISED MAY 2000

MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)

†‡

timing requirements for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 1 (see Figure 36)

’C6701-120

’C6701-150

’C6701-167

NO.

UNIT

MASTER

SLAVE

MIN

12

4

MAX

4

5

t

Setup time, DR valid before CLKX low

Hold time, DR valid after CLKX low

2 – 3P

5 + 6P

ns

su(DRV-CKXL)

h(CKXL-DRV)

†

‡

P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns.

For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.

†‡

switching characteristics for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 1

(see Figure 36)

’C6701-120

’C6701-150

’C6701-167

NO.

PARAMETER

UNIT

§

MASTER

SLAVE

MIN

MIN MAX

MAX

¶

1

2

3

t

Hold time, FSX low after CLKX high

H – 4 H + 4

T – 4 T + 4

ns

h(CKXH-FXL)

d(FXL-CKXL)

d(CKXH-DXV)

#

Delay time, FSX low to CLKX low

Delay time, CLKX high to DX valid

–4

4

3P + 1 5P + 17

3P + 4 5P + 17

Disable time, DX high impedance following last data bit from

CLKX high

6

t

–2

4

ns

dis(CKXH-DXHZ)

7

t

Delay time, FSX low to DX valid

L – 2 L + 3

2P + 1 4P + 13

d(FXL-DXV)

†

‡

§

P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns.

For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.

S = sample rate generator input clock = P if CLKSM = 1 (P = 1/CPU clock frequency)

=

sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)

T = CLKX period = (1 + CLKGDV) * S

H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even

= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero

L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even

= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero

FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX

and FSR is inverted before being used internally.

CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP

CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP

¶

#

FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock

(CLKX).

58

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

T MS3 20 C6 70 1

A

F

L

O

AT

I

N

G

Ć

P

O

I

N

T

D

I

G

I

TA

L

S

I

G

N

L

P R O C E S S O R

SPRS067E – MAY 1998 – REVISED MAY 2000

MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)

CLKX

FSX

DX

1

2

7

6

3

Bit 0

Bit(n-1)

(n-2)

(n-3)

(n-4)

4

5

DR

(n-2)

(n-3)

(n-4)

Figure 36. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1

59

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

T M S3 2 0 C6 7 01

I

F

L

O

A

T

N

G

Ć

P

O

I

N

T

D

I

G

I

TA

L

S

I

G

N

A

L

P R O C E S S O R

SPRS067E – MAY 1998 – REVISED MAY 2000

DMAC, TIMER, POWER-DOWN TIMING

switching characteristics for DMAC outputs (see Figure 37)

’C6701-120

’C6701-150

’C6701-167

NO.

PARAMETER

UNIT

MIN

MAX

11

1

t

Delay time, CLKOUT1 high to DMAC valid

2

ns

d(CKO1H-DMACV)

CLKOUT1

DMAC[0:3]

1

Figure 37. DMAC Timing

†

timing requirements for timer inputs (see Figure 38)

’C6701-120

’C6701-150

’C6701-167

NO.

UNIT

MIN

MAX

1

t

Pulse duration, TINP high

2P

ns

w(TINPH)

†

P = 1/CPU clock frequency in ns. For example, when running parts at 167 MHz, use P = 6 ns.

switching characteristics for timer outputs (see Figure 38)

’C6701-120

’C6701-150

’C6701-167

NO.

PARAMETER

UNIT

MIN

MAX

10

2

t

Delay time, CLKOUT1 high to TOUT valid

1

ns

d(CKO1H-TOUTV)

CLKOUT1

TINP

1

2

TOUT

Figure 38. Timer Timing

60

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

T MS3 20 C6 70 1

A

F

L

O

AT

I

N

G

Ć

P

O

I

N

T

D

I

G

I

TA

L

S

I

G

N

L

P R O C E S S O R

SPRS067E – MAY 1998 – REVISED MAY 2000

DMAC, TIMER, POWER-DOWN TIMING (CONTINUED)

switching characteristics for power-down outputs (see Figure 39)

’C6701-120

’C6701-150

’C6701-167

NO.

PARAMETER

UNIT

MIN

MAX

1

t

Delay time, CLKOUT1 high to PD valid

1

9

ns

d(CKO1H-PDV)

CLKOUT1

PD

1

Figure 39. Power-Down Timing

61

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

T M S3 2 0 C6 7 01

I

F

L

O

A

T

N

G

Ć

P

O

I

N

T

D

I

G

I

TA

L

S

I

G

N

A

L

P R O C E S S O R

SPRS067E – MAY 1998 – REVISED MAY 2000

JTAG TEST-PORT TIMING

timing requirements for JTAG test port (see Figure 40)

’C6701-120

’C6701-150

’C6701-167

NO.

UNIT

MIN

35

10

9

MAX

1

3

4

t

Cycle time, TCK

ns

c(TCK)

Setup time, TDI/TMS/TRST valid before TCK high

Hold time, TDI/TMS/TRST valid after TCK high

su(TDIV-TCKH)

h(TCKH-TDIV)

switching characteristics for JTAG test port (see Figure 40)

’C6701-120

’C6701-150

’C6701-167

NO.

PARAMETER

UNIT

MIN

MAX

12

2

t

Delay time, TCK low to TDO valid

–3

ns

d(TCKL-TDOV)

1

TCK

TDO

2

4

3

TDI/TMS/TRST

Figure 40. JTAG Test-Port Timing

62

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

T MS3 20 C6 70 1

A

F

L

O

AT

I

N

G

Ć

P

O

I

N

T

D

I

G

I

TA

L

S

I

G

N

L

P R O C E S S O R

SPRS067E – MAY 1998 – REVISED MAY 2000

MECHANICAL DATA

GJC (S-PBGA-N352)

PLASTIC BALL GRID ARRAY

35,20

34,80

SQ

33,20

32,80

31,75 TYP

1,27

21,00 NOM

0,635

AF

AE

AD

AC

AB

AA

Y

W

V

U

T

R

P

N

M

L

K

J

H

G

F

E

D

C

B

A

1

3

5

7

9

11 13 15 17 19 21 23 25

10 12 14 16 18 20 22 24 26

2

4

6

8

Heat Slug

See Note E

3,50 MAX

1,00 NOM

Seating Plane

0,15

0,90

0,60

M

0,10

0,50 MIN

4173506-2/D 07/99

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Thermally enhanced plastic package with heat slug (HSL).

D. Flip chip application only

E. Possible protrusion in this area, but within 3,50 max package height specification

F. Falls within JEDEC MO-151/BAR-2

thermal resistance characteristics (S-PBGA package)

†

NO

°C/W

0.74

11.31

9.60

8.34

7.30

Air Flow LFPM

1

2

3

4

5

RΘ

Junction-to-case

N/A

0

JC

JA

Junction-to-free air

100

250

500

†

LFPM = Linear Feet Per Minute

63

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

IMPORTANT NOTICE

Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue

any product or service without notice, and advise customers to obtain the latest version of relevant information

to verify, before placing orders, that information being relied on is current and complete. All products are sold

subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those

pertaining to warranty, patent infringement, and limitation of liability.

TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in

accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent

TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily

performed, except those mandated by government requirements.

Customers are responsible for their applications using TI components.

In order to minimize risks associated with the customer’s applications, adequate design and operating

safeguards must be provided by the customer to minimize inherent or procedural hazards.

TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent

that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other

intellectual property right of TI covering or relating to any combination, machine, or process in which such

semiconductor products or services might be or are used. TI’s publication of information regarding any third

party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.


型号：	TMSC6701
厂家：	TEXAS INSTRUMENTS
描述：	FLOATING POINT DIGITAL SIGNAL PROCESSOR 浮点数字信号处理器数字信号处理器
文件：	总64页 (文件大小：860K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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