TMUX1072RUTR [TI]
具有断电保护功能的 5V、2:1 (SPDT)、2 通道模拟开关 | RUT | 12 | -40 to 125;
| 型号： | TMUX1072RUTR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有断电保护功能的 5V、2:1 (SPDT)、2 通道模拟开关 | RUT | 12 | -40 to 125 开关 光电二极管 |
| 文件： | 总31页 (文件大小：1283K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TMUX1072
ZHCSHZ3C –APRIL 2018–REVISED AUGUST 2019
具有过压检测和保护功能的 TMUX1072 双通道 2:1 模拟多路复用器
1 特性
3 说明
1
•
电源电压范围为 2.3V 至 5.5V
TMUX1072 是一款高速双通道 2:1 模拟开关，具有集
成的高压检测和断电保护功能。该器件是一款双向器
件，可用作 2:1 或 1:2 开关，同时支持高于 VCC（最高
可达 5.5V）的信号。
•
关断保护：当
VCC = 0V 时，I/O 引脚处于高阻抗状态
•
•
•
•
•
•
•
•
•
借助故障指示引脚进行 6V 过压和过热检测
通用引脚上具有 18V 过压保护 (OVP)
支持高于 VCC 且高达 5.5V 的信号
低至 6Ω 的 RON
TMUX1072 的 I/O 引脚上的保护功能可承受最高 18V
的电压，并配备自动关闭电路，以防止开关后面的系统
组件受损。该保护功能用于电源定序。系统中的某些电
路板可能会在其他电路板准备好接收信号之前通电。该
器件可检测过压和过热事件，并通过 FLT 引脚提供开
漏输出信号。
典型带宽为 1.2GHz
典型 CON 为 4.5pF
低功耗禁用模式
1.8V 兼容型逻辑输入
器件信息(1)
ESD 保护性能超出 JESD22 标准
器件型号
TMUX1072
封装
UQFN (12)
VSSOP (10)
封装尺寸（标称值）
2.00mm × 1.70mm
3.00mm x 5.00mm
–
2000V 人体放电模型 (HBM)
•
提供小型 2.00mm x 1.70mm QFN 封装
2 应用
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
•
•
•
•
•
数据采集 (DAQ)
现场仪器
视频监控
HVAC 系统
后置摄像头
简化原理图
TMUX1072
VCC
OVP
NC1
COM1
COM2
NO1
NC2
NO2
SEL1
SEL2
Logic
Control
OE
FLT
GND
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SCDS382
TMUX1072
ZHCSHZ3C –APRIL 2018–REVISED AUGUST 2019
www.ti.com.cn
目录
8.3 Feature Description................................................. 15
8.4 Device Functional Modes........................................ 16
Application and Implementation ........................ 17
9.1 Application Information............................................ 17
9.2 Typical Application .................................................. 17
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 5
6.5 Electrical Characteristics........................................... 5
6.6 Dynamic Characteristics ........................................... 8
6.7 Timing Requirements................................................ 8
6.8 Typical Characteristics.............................................. 9
Parameter Measurement Information ................ 10
Detailed Description ............................................ 14
8.1 Overview ................................................................. 14
8.2 Functional Block Diagram ....................................... 14
9
10 Power Supply Recommendations ..................... 18
11 Layout................................................................... 18
11.1 Layout Guidelines ................................................. 18
11.2 Layout Example .................................................... 19
12 器件和文档支持 ..................................................... 20
12.1 文档支持................................................................ 20
12.2 接收文档更新通知 ................................................. 20
12.3 社区资源................................................................ 20
12.4 商标....................................................................... 20
12.5 静电放电警告......................................................... 20
12.6 Glossary................................................................ 20
13 机械、封装和可订购信息....................................... 20
7
8
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from Revision B (June 2019) to Revision C
Page
•
•
已添加 Typical Characteristics curves for AC parameters .................................................................................................... 9
Added the Application Curves section.................................................................................................................................. 18
Changes from Revision A (August 2018) to Revision B
Page
•
将特性 从“通用引脚上具有 0V 至 18V 过压保护 (OVP)”更改为“通用引脚上具有 0V 至 6V 过压保护 (OVP)” ........................ 1
Changes from Original (April 2018) to Revision A
Page
•
将器件状态从预告信息 更改为生产数据.................................................................................................................................. 1
2
Copyright © 2018–2019, Texas Instruments Incorporated
TMUX1072
www.ti.com.cn
ZHCSHZ3C –APRIL 2018–REVISED AUGUST 2019
5 Pin Configuration and Functions
RUT Package
12-Pin UQFN
Top View
DGS Package
10-Pin VSSOP
Top View
SEL1
NO1
GND
NO2
SEL2
1
2
3
4
5
10
9
COM1
NC1
SEL1
NO1
GND
NO2
SEL2
1
2
3
4
5
11
10
9
COM1
NC1
12
8
VCC
VCC
7
NC2
6
8
NC2
6
COM2
7
COM2
Not to scale
Not to scale
Pin Functions
PIN
I/O
DESCRIPTION
NAME
SEL1
NO1
GND
NO2
SEL2
OE
RUT
1
DGS
1
2
3
4
5
-
I
I/O
GND
I/O
I
Switch select 1
2
Signal path NO1
Ground
3
4
Signal path NO2
Switch select 2
5
6
I
Output enable (Active low)
Common signal path 2
Signal path NC2
Supply Voltage
COM2
NC2
7
6
7
8
9
10
-
I/O
I/O
PWR
I/O
I/O
O
8
VCC
NC1
9
10
11
12
Signal path NC1
Common signal path 1
COM1
FLT
Fault indicator output pin (Active low) - open drain. If feature is unused, pin may be
left floating or connected to ground
Copyright © 2018–2019, Texas Instruments Incorporated
3
TMUX1072
ZHCSHZ3C –APRIL 2018–REVISED AUGUST 2019
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
(2)
MIN
–0.5
–0.5
–0.5
–0.5
–0.5
MAX
UNIT
VCC
VI/O
Supply voltage(3)
6
20
6
V
V
V
V
V
Input/Output DC voltage (COM1, COM2)(3)
Input/Output DC voltage (NC1, NO1, NC2, NO2)
Digital input voltage (SEL1, SEL2, OE)
Digital output voltage (FLT)
(3)
VI
6
VO
6
Input-output port diode current (COM1,
COM2,NC1, NO1, NC2, NO2)
IK
VIN < 0
VI < 0
–50
–50
mA
mA
Digital logic input clamp current (SEL1,
IIK
(3)
SEL2, OE)
ICC
IGND
Tstg
TJ
Continuous current through VCC
Continuous current through GND
Storage temperature
100
mA
mA
°C
–100
–65
150
150
Operating Junction Temperature
–65
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The algebraic convention, whereby the most negative value is a minimum and the most positive value is a maximum.
(3) All voltages are with respect to ground, unless otherwise specified.
6.2 ESD Ratings
VALUE
±2000
±1000
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
Electrostatic
discharge
V(ESD)
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
MIN
MAX
5.5
18
UNIT
VCC
VI/O
VI/O
II/O
II/O
VI
Supply voltage
2.3
0
V
V
COM1, COM2
(NC1, NO1, NC2, NO2)
COM1, COM2
0
5.5
50
V
Analog input/output
-50
-50
0
mA
mA
V
(NC1, NO1, NC2, NO2)
SEL1, SEL2, OE
FLT
50
Digital input voltage
5.5
5.5
VO
Digital output voltage
0
V
Analog input/output port continuous current
(COM1, COM2, NC1, NO1,
NC2, NO2)
II/O
-50
50
mA
IOL
TA
TJ
Digital output current
3
125
125
mA
ºC
Operating free-air temperature
Junction temperature
–40
–40
ºC
4
Copyright © 2018–2019, Texas Instruments Incorporated
TMUX1072
www.ti.com.cn
ZHCSHZ3C –APRIL 2018–REVISED AUGUST 2019
6.4 Thermal Information
TMUX1072
(1)
THERMAL METRIC
RUT (UQFN)
12 PINS
127
DGS (VSSOP)
10 PINS
175
UNIT
RθJA
RθJC(top)
RθJB
ψJT
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
55.5
61.2
67.7
96.9
Junction-to-top characterization parameter
Junction-to-board characterization parameter
1.6
8.2
ψJB
67.3
95.1
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
TA = –40°C to +125°C , VCC = 2.3 V to 5.5 V, GND = 0V, Typical values are at VCC = 3.3 V, TA = 25°C, (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
SUPPLY
VCC
Power supply voltage
2.3
5.5
V
OE = 0 V
Active supply current
SEL1, SEL2 = 0 V, 1.8 V or VCC
0 V < VI/O < 3.6 V
75
65
3
110
µA
ICC
OE = 0 V
SEL1, SEL2 = 0 V, 1.8 V or VCC
VI/O > VPOS_THLD
Supply current during OVP
condition
98
10
µA
OE = 1.8 V or VCC
SEL1 = 0 V, 1.8 V, or VCC
SEL2 = 0 V, 1.8 V, or VCC
Standby powered down
supply current
(1)
ICC_PD
µA
V
UVLO
Under Voltage Lock Out
VCC = rising and falling
1.65
DC Characteristics
VI/O = 0 V to VCC
RON
ON-state resistance
ISINK = 8 mA
Refer to ON-State Resistance Figure
6
0.07
2.5
18
0.5
7
Ω
Ω
Ω
VI/O = 0 V to VCC
ISINK = 8 mA
Refer to ON-State Resistance Figure
ON-state resistance match
between channels
ΔRON
VI/O = 0 V to VCC
RON (FLAT)
ON-state resistance flatness ISINK = 8 mA
Refer to ON-State Resistance Figure
(1) Not tested for DGS package due to absence of FLT and OE pin.
Copyright © 2018–2019, Texas Instruments Incorporated
5
TMUX1072
ZHCSHZ3C –APRIL 2018–REVISED AUGUST 2019
www.ti.com.cn
Electrical Characteristics (continued)
TA = –40°C to +125°C , VCC = 2.3 V to 5.5 V, GND = 0V, Typical values are at VCC = 3.3 V, TA = 25°C, (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
(2)
VCOM1/2 = 0 V to 5.5 V
VCC = 2.3 V to 5.5 V
VNC1/2 or VNO1/2 = 5.5 V or 0 V
Refer to Off Leakage Figure
3.6
10
3
µA
µA
µA
µA
uA
uA
µA
µA
(2)
VCOM1/2 = 5.5 V
VCC = 5.5 V
VNC1/2 or VNO1/2 = 5.5 V
Refer to Off Leakage Figure
(2)
VCOM1/2 = 3.6 V
VCC = 3.3 V
VNC1/2 or VNO1/2 = 3.6 V
Refer to Off Leakage Figure
2
VCOM1/2 = 5.5 V
VCC = 0 V
VNC1/2 or VNO1/2 = 5.5 V
Refer to Off Leakage Figure
IOFF
I/O pin OFF leakage current
15
10
2
VCOM1/2 = 3.6 V
VCC = 0 V
VNC1/2 or VNO1/2 = 3.6 V
Refer to Off Leakage Figure
VCOM1/2 = 1 V
VCC = 0 V
VNC1/2 or VNO1/2 = 1 V
Refer to Off Leakage Figure
VCOM1/2 = 18 V
VCC = 0 V, 5.5 V
VNC1/2 or VNO1/2 = 0 V
Refer to Off Leakage Figure
165
1.2
185
3.5
VCOM1/2 = 5.5 V
VCC = 5.5 V
VNC1/2 and VNO1/2 = high-Z
Refer to On Leakage Figure
ION
ON leakage current
VCOM1/2 = 0 V to 5.5 V
VCC = 2.3-5.5 V
VNC1/2 and VNO1/2 = high-Z
Refer to On Leakage Figure
11.5
µA
Digital Characteristics
VIH
VIL
Input logic high
Input logic low
SEL1, SEL2, OE
SEL1, SEL2, OE
1.45
V
V
0.5
0.3
FLT
IOL = 3 mA
VOL
Output logic low
V
IIH
IIL
Input high leakage current
Input low leakage current
SEL1, SEL2, OE = 1.8 V, VCC
SEL1, SEL2, OE = 0 V
SEL1, SEL2
-1
-1
2
±0.2
6
5
1
μA
μA
12
6
MΩ
MΩ
Internal pull-down resistor on
digital input pins
RPD
OE
3
SEL1, SEL2 = 0 V, 1.8 V or VCC
f = 1 MHz
(3)
CI
Digital input capacitance
8
pF
Protection and Detection
VOVP_TH
OVP positive threshold
5.55
40
5.8
6.0
V
(3)
VOVP_HYST
OVP threshold hysteresis
100
300
mV
(2) Not tested on COM1/2 pins for DGS package due to the absence of OE pin
(3) Specified by design, not tested in production.
6
Copyright © 2018–2019, Texas Instruments Incorporated
TMUX1072
www.ti.com.cn
ZHCSHZ3C –APRIL 2018–REVISED AUGUST 2019
Electrical Characteristics (continued)
TA = –40°C to +125°C , VCC = 2.3 V to 5.5 V, GND = 0V, Typical values are at VCC = 3.3 V, TA = 25°C, (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
Thermal Shutdown
Hysteresis
(3)
TSD_HYST
3
8
°C
°C
Overtemperature detection
threshold
(3)
TOTD_TH
135
165
VCOM1/2 = 0 to 18 V
tRISE and tFALL(10% to 90 %) = 100 ns
RL = Open
Switch on or off
0
9.6
9.0
V
V
Maximum voltage to appear
on NC1/2 and NO1/2 pins
during OVP scenario
OE = 0 V
(3)
VCLAMP_V
VCOM1/2 = 0 to 18 V
tRISE and tFALL(10% to 90 %) = 100 ns
RL = 50Ω
0
Switch on or off
OE = 0 V
RPU = 10 kΩ to VCC (FLT)
CL = 35 pF
Refer to OVP Timing Diagram Figure
(3)
tEN_OVP
OVP enable time
0.6
1.5
3
5
μs
μs
RPU = 10 kΩ to VCC (FLT)
CL = 35 pF
(3)
tREC_OVP
OVP recovery time
Refer to OVP Timing Diagram Figure
Copyright © 2018–2019, Texas Instruments Incorporated
7
TMUX1072
ZHCSHZ3C –APRIL 2018–REVISED AUGUST 2019
www.ti.com.cn
6.6 Dynamic Characteristics
TA = –40°C to +125°C , VCC = 2.3 V to 5.5V, GND = 0V, Typical values are at VCC = 3.3 V, TA = 25°C, (unless otherwise
noted)
PARAMETER(1)
TEST CONDITIONS
MIN
TYP
MAX UNIT
VCOM1/2 = 0 or 3.3 V,
OE = VCC
COM1, COM2 off capacitance
Switch OFF
1.2
4.0
6.2
pF
f = 240 MHz
COFF
VCOM1/2 = 0 or 3.3 V,
OE = VCC or OE = 0V with SEL1,
SEL2 (switch not selected)
f = 240 MHz
NC1, NO1, NC2, NO2 off
capacitance
Switch OFF or
not selected
1.2
1.4
4.0
4.0
-80
6.2
6.2
pF
pF
dB
VCOM1/2 = 0 or 3.3 V,
f = 240 MHz
COM1, COM2, NC1, NO1, NC2,
NO2 on capacitance
CON
Switch ON
RL = 50 Ω
CL = 5 pF
f = 100 kHz
Switch OFF
Refer to Off Isolation Figure
OISO
Differential off isolation
RL = 50 Ω
CL = 5 pF
f = 240 MHz
Refer to Off Isolation Figure
Switch OFF
Switch ON
-22
-90
dB
dB
RL = 50 Ω
CL = 5 pF
f = 100 kHz
XTALK
Channel to Channel crosstalk
Refer to Crosstalk Figure
RL = 50 Ω; Refer to BW and
Insertion Loss Figure
BW
Bandwidth
Switch ON
Switch ON
1.2
GHz
dB
RL = 50 Ω
f = TBD MHz; Refer to BW and
Insertion Loss Figure
ILOSS
Insertion loss
-0.8
(1) Specified by design, not tested in production.
6.7 Timing Requirements
TA = –40°C to +125°C , VCC = 2.3 V to 5.5V, GND = 0V, Typical values are at VCC = 3.3 V, TA = 25°C, (unless otherwise
noted)
PARAMETER(1)
TEST CONDITIONS
MIN NOM
MAX UNIT
VNC = 0.8 V
Refer to Tswitch Timing Figure
Switching time between channels
(SEL1, SEL2 to output)
tswitch
ton
0.9
1
250
10
µs
µs
µs
VNC = 0.8 V
Refer to Ton and Toff Figure
Device turn on time (OE to output)
Device turn off time (OE to output)
200
1
RL = 50 Ω,
CL = 5 pF,
VCC = 2.3 V to 5.5 V
VNC = 0.8 V
Refer to Ton and Toff Figure
toff
VNC = 0.8 V
Refer to Ton and Toff Figure
Device turn off time VCC to Switch
off
toff_Vcc
250
µs
Ramp rate VCC = 2.3 V to 0 V
250µs
RL = 50 Ω,
CL = 1 pF,
VCC = 2.3 V to 5.5 V
Skew of opposite transitions of
same output (between COM1 and
COM2)(1)
VCOM1/2 = VCC
Refer to Tsk Figure
tSK(P)
9
50
ps
ps
RL = 50 Ω,
CL = 5 pF,
VCC = 2.3 V to 5.5 V
VCOM1/2 = VCC
Refer to Tpd Figure
tpd
Propagation delay(1)
130
200
(1) Specified by design, not tested in production.
8
Copyright © 2018–2019, Texas Instruments Incorporated
TMUX1072
www.ti.com.cn
ZHCSHZ3C –APRIL 2018–REVISED AUGUST 2019
6.8 Typical Characteristics
10
0
-60
-65
-70
-75
-80
-85
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
100k
1M
10M 100M
Frequency (Hz)
1G
10G
1M
10M
Frequency (Hz)
TDM0U0X3
TDM0U0X1
图 1. Off-Isolation vs Frequency
图 2. Xtalk vs Frequency
0
-1
-2
-3
-4
-5
-6
1M
10M
100M
1G
Frequency (Hz)
TDM0U0X1
图 3. Bandwidth and Insertion Loss vs Frequency
版权 © 2018–2019, Texas Instruments Incorporated
9
TMUX1072
ZHCSHZ3C –APRIL 2018–REVISED AUGUST 2019
www.ti.com.cn
7 Parameter Measurement Information
V
V
I/O
I
Switch
SINK
Channel ON, RON = V/ISINK
图 4. ON-State Resistance (RON
)
VNC/NO
VCOM
A
A
Switch
图 5. Off Leakage
VCOM
A
Switch
图 6. On Leakage
VNC
VNO
VCOM
SEL
CL
RL
VSEL
1.8 V
0 V
0.8 V
1.2 V
VSEL
tSWITCH
tSWITCH
VCOM
V
NC
90 %
10 %
0 V
(1) All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr < 500
ps, tf < 500 ps.
(2) CL includes probe and jig capacitance.
图 7. tSWITCH Timing
10
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TMUX1072
www.ti.com.cn
ZHCSHZ3C –APRIL 2018–REVISED AUGUST 2019
Parameter Measurement Information (接下页)
2.3 V
VNC
VNO
V
CC
OE
VCOM
1.8 V
0 V
0.8 V
1.2 V
V
CL
RL
OE
t
t
OFF
ON
V
NC/NO
0 V
90 %
V
OE
V
COM
10 %
(1) All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr < 500
ps, tf < 500 ps.
(2) CL includes probe and jig capacitance.
图 8. tON, tOFF for OE
Network Analyzer
Switch
50 O
V
COM1
50 O
Source
Signal
50 O
V
COM2
50 O
Source
Signal
50 O
50 O
图 9. Off Isolation
Network Analyzer
50 ꢀ
Switch
V
V
COM1
50 ꢀ
Source
Signal
50 ꢀ
COM2
50 ꢀ
50 ꢀ
50 ꢀ
图 10. Cross Talk
版权 © 2018–2019, Texas Instruments Incorporated
11
TMUX1072
ZHCSHZ3C –APRIL 2018–REVISED AUGUST 2019
www.ti.com.cn
Parameter Measurement Information (接下页)
Network Analyzer
Switch
50 ꢀ
V
COM1
50 ꢀ
Source
Signal
50 ꢀ
V
COM2
50 ꢀ
Source
Signal
50 ꢀ
50 ꢀ
图 11. BW and Insertion Loss
18 V
0 V
VPOS_THLD
VCOM
OE
VCOM
CL
RL
tEN_OVP
FLT
tREC_OVP
VOE
VCC
0 V
10 %
10 %
图 12. tEN_OVP and tDIS_OVP Timing Diagram
Switch
V
COM
50 ꢀ
0.4 V
50 %
50 %
V
COM
0 V
0.4 V
0 V
50 ꢀ
t
PD
t
PD
50 %
50 %
V
NC/NO
(1) All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr < 500
ps, tf < 500 ps.
(2) CL includes probe and jig capacitance.
图 13. tPD
12
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TMUX1072
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Parameter Measurement Information (接下页)
Switch
VNC1
0.4 V
VCOM1
50 O
50 O
VCOM1/2
0 V
50 O
0.4 V
50 %
50 %
VNC2
VNC1
VNC2
0 V
0.4 V
0 V
VCOM2
tSK
tSK
50 %
50 %
50 O
(1) All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr < 500
ps, tf < 500 ps.
(2) CL includes probe and jig capacitance.
图 14. tSK
版权 © 2018–2019, Texas Instruments Incorporated
13
TMUX1072
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www.ti.com.cn
8 Detailed Description
8.1 Overview
The TMUX1072 is a high speed, 2-channel 2:1 analog switch with overvoltage protection. The device is
bidirectional and can be used as a dual 2:1 or 1:2 switch, but OVP only applies to the COM pins. The device also
contains a fault indicator pin which can signal to the system of either an over voltage or over temperature event.
The device maintains excellent signal integrity through the optimization of both RON and BW while protecting the
system with up to 18 V OVP protection. The OVP implementation is designed to protect sensitive system
components behind the switch that cannot survive fault conditions.
8.2 Functional Block Diagram
VCC
SEL1
6 Mꢀ
SEL2
Control
Logic
FLT
6 Mꢀ
OE
3 Mꢀ
VOVP
OVP
VNC1
VCOM1
VNC2
VNO1
VCOM2
VNO2
Switches
14
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TMUX1072
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8.3 Feature Description
8.3.1 Powered-off Protection
When the TMUX1072 is powered off the I/Os of the device remain in a high-Z state. The crosstalk, off-isolation,
and leakage remain within the Electrical Specifications
This prevents errant voltages from reaching the rest of the system and maintains isolation when the system is
powering up.
8.3.2 Overvoltage Detection
When a voltage on the COM pin exceeds the VOVP_TH, the open drain output FLTpin pulls the pin low to indicate
an overvoltage event has been detected. The open drain output will release the FLT pin when the voltage on the
COM pin returns below the VOVP_TH
.
8.3.3 Overtemperature Detection
When the junction temperature of the device exceeds the overtemperature detection threshold TOTD_TH, the open
drain output FLT pin pulls the pin low to indicate an overtemperature event has been detected. The open drain
output releases the FLT pin when the junction temperature returns below the TOTD_TH
.
8.3.4 Overvoltage Protection
The OVP of the TMUX1072 is designed to protect the system from overvoltage conditions up to 18 V on the
COM1 and COM2 pins. This protection is valid even if Vcc = 0V. 图 15 depicts an event where up to 18 V could
appear on COM1 and COM2 that could pass through the device and damage components behind the device.
Device 1
Existing Solutions
NC1
COM1
NO1
NC2
COM2
NO2
Device 2
图 15. Existing Solution Being Damaged by a Short, 18 V
The TMUX1072 opens the switches and protect the rest of the system by blocking the 18 V as depicted in 图 16.
版权 © 2018–2019, Texas Instruments Incorporated
15
TMUX1072
ZHCSHZ3C –APRIL 2018–REVISED AUGUST 2019
www.ti.com.cn
Feature Description (接下页)
18 V does not reach
rest of system
Device 1
NC1
COM1
COM2
NO1
NC2
NO2
USB
Device 2
图 16. Protecting During a 18-V Short
图 17 is a waveform showing the voltage on the pins during an overvoltage scenario.
18 V
VOVP_THLD
COM1/COM2
0 V
NO1/NO2 or
NC1/NC2
0 V
FLT
图 17. Overvoltage Protection Waveform, 18 V
8.4 Device Functional Modes
8.4.1 Pin Functions
表 1. Function Table
OE
H
L
SEL1
SEL2
COM1 Connection
High-Z
COM2 Connection
X
L
X
L
High-Z
COM1 to NC1
COM1 to NC1
COM1 to NO1
COM1 to NO1
COM2 to NC2
COM2 to NO2
COM2 to NC2
COM2 to NO2
L
L
H
L
L
H
H
L
H
16
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TMUX1072
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ZHCSHZ3C –APRIL 2018–REVISED AUGUST 2019
9 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
There are many applications in which processors and microcontrollers have a limited number of I/Os. This IC can
effectively expand the limited number of I/Os by switching between multiple signal paths in order to interface
them to a single processor or microcontroller. The device can also be used to connect a single microcontroller to
two signal paths. With independent control of the two switches using SEL1 and SEL2, TMUX1072 can be used
to cross switch single ended signals.
9.2 Typical Application
The TMUX1072 is used to switch signals between the high speed signal paths that may be exposed to a
connector or near a bus which could experience an overvoltage condition. The TMUX1072 has internal pull-down
resistors on SEL1, SEL2, and OE. The pull-down on SEL1 and SEL2 pins ensure the NC1/NC2 channel is
selected by default. The pull-down on OE enables the switch when power is applied.
TMUX1072
Device 1
VCC
OVP
NC1
COM1
COM2
NO1
NC2
NO2
SEL1
SEL2
Device 2
Logic
Control
OE
FLT
GND
图 18. Typical TMUX1072 Application
9.2.1 Design Requirements
The TMUX1072 has internal pull-down resistors on SEL1, SEL2, and OE, so no external resistors are required
on the logic pins. The internal pull-down resistor on SEL1 and SEL2 pins ensures the NC1 and NC2 channels
are selected by default. The internal pull-down resistor on OE enables the switch when power is applied to VCC.
The FLT indicator output pin is an open drain output that will require an external pull-up resistor for the
overvoltage and overtemperature condition to be detected. If feature is unused, FLT pin may be left floating or
connected to ground
9.2.2 Detailed Design Procedure
The TMUX1072 can be properly operated without any external components. However, TI recommends that
unused signal pins must be connected to ground through a 50-Ω resistor to prevent signal reflections back into
the device. TI does recommend a 100-nF bypass capacitor placed close to TMUX1072 VCC pin.
版权 © 2018–2019, Texas Instruments Incorporated
17
TMUX1072
ZHCSHZ3C –APRIL 2018–REVISED AUGUST 2019
www.ti.com.cn
Typical Application (接下页)
9.2.3 Application Curves
Bandwidth is defined as the range of frequencies that are attenuated by less than 3 dB when the input is applied
to the source pin of an on-channel, and the output is measured at the drain pin of the TMUX1072. 图 19 shows
the bandwidth of TMUX1072.
0
-1
-2
-3
-4
-5
-6
1M
10M
100M
1G
Frequency (Hz)
TDM0U0X1
图 19. Bandwidth and Insertion Loss vs Frequency
10 Power Supply Recommendations
Power to the device is supplied through the VCC pin. TI recommends placing a 100-nF bypass capacitor as
close to the supply pin VCC as possible to help smooth out lower frequency noise to provide better load
regulation across the frequency spectrum.
11 Layout
11.1 Layout Guidelines
1. Place supply bypass capacitors as close to VCC pin as possible and avoid placing the bypass caps near the
signal traces.
2. The high-speed traces should always be of equal length and must be no more than 4 inches; otherwise, the
eye diagram performance may be degraded.
3. Route the high-speed signals using a minimum of vias and corners which will reduce signal reflections and
impedance changes. When a via must be used, increase the clearance size around it to minimize its
capacitance. Each via introduces discontinuities in the transmission line of the signal and increases the
chance of picking up interference from the other layers of the board. Be careful when designing test points
on twisted pair lines; through-hole pins are not recommended.
4. When it becomes necessary to turn 90°, use two 45° turns or an arc instead of making a single 90° turn. This
reduces reflections on the signal traces by minimizing impedance discontinuities.
5. Do not route signal traces under or near crystals, oscillators, clock signal generators, switching regulators,
mounting holes, magnetic devices, or IC’s that use or duplicate clock signals.
6. Avoid stubs on the high-speed signals because they cause signal reflections.
7. Route all high-speed signal traces over continuous planes (VCC or GND), with no interruptions.
8. Avoid crossing over anti-etch, commonly found with plane splits.
9. For high frequency systems, a printed circuit board with at least four layers is recommended: two signal
layers separated by a ground layer and a power layer. The majority of signal traces should run on a single
layer, preferably Signal 1. Immediately next to this layer should be the GND plane, which is solid with no
cuts. Avoid running signal traces across a split in the ground or power plane. When running across split
planes is unavoidable, sufficient decoupling must be used. Minimizing the number of signal vias reduces EMI
by reducing inductance at high frequencies. For more information on layout guidelines, see High Speed
Layout Guidelines (SCAA082)
18
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TMUX1072
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ZHCSHZ3C –APRIL 2018–REVISED AUGUST 2019
11.2 Layout Example
LEGEND
Polygonal Copper Pour
VIAto Power Plane
VIAto GND Plane
12
SEL1
NO1
COM1
1
2
3
4
5
11
FLT
10
9
NC1
VCC
Vcc
GND
NO2
SEL2
Bypass Capacitor
NC2
8
7
COM2
OE
6
Not to scale
图 20. Layout Example
版权 © 2018–2019, Texas Instruments Incorporated
19
TMUX1072
ZHCSHZ3C –APRIL 2018–REVISED AUGUST 2019
www.ti.com.cn
12 器件和文档支持
12.1 文档支持
12.1.1 相关文档
请参阅如下相关文档：
•
•
应用报告《高速布局指南》
《高速接口布局指南》
12.2 接收文档更新通知
要接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我 进行注册，即可每周接收产
品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
12.3 社区资源
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.4 商标
E2E is a trademark of Texas Instruments.
12.5 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。
20
版权 © 2018–2019, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TMUX1072DGSR
TMUX1072RUTR
ACTIVE
ACTIVE
VSSOP
UQFN
DGS
RUT
10
12
2500 RoHS & Green
3000 RoHS & Green
NIPDAUAG
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
1A9
1BU
NIPDAUAG
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Jun-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TMUX1072DGSR
TMUX1072RUTR
VSSOP
UQFN
DGS
RUT
10
12
2500
3000
330.0
180.0
12.4
9.5
5.3
1.9
3.4
2.2
1.4
0.7
8.0
4.0
12.0
8.0
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Jun-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TMUX1072DGSR
TMUX1072RUTR
VSSOP
UQFN
DGS
RUT
10
12
2500
3000
364.0
189.0
364.0
185.0
27.0
36.0
Pack Materials-Page 2
PACKAGE OUTLINE
DGS0010A
VSSOP - 1.1 mm max height
S
C
A
L
E
3
.
2
0
0
SMALL OUTLINE PACKAGE
C
SEATING PLANE
0.1 C
5.05
4.75
TYP
PIN 1 ID
AREA
A
8X 0.5
10
1
3.1
2.9
NOTE 3
2X
2
5
6
0.27
0.17
10X
3.1
2.9
1.1 MAX
0.1
C A
B
B
NOTE 4
0.23
0.13
TYP
SEE DETAIL A
0.25
GAGE PLANE
0.15
0.05
0.7
0.4
0 - 8
DETAIL A
TYPICAL
4221984/A 05/2015
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-187, variation BA.
www.ti.com
EXAMPLE BOARD LAYOUT
DGS0010A
VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE
10X (1.45)
(R0.05)
TYP
SYMM
10X (0.3)
1
5
10
SYMM
6
8X (0.5)
(4.4)
LAND PATTERN EXAMPLE
SCALE:10X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
4221984/A 05/2015
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DGS0010A
VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE
10X (1.45)
SYMM
(R0.05) TYP
10X (0.3)
8X (0.5)
1
5
10
SYMM
6
(4.4)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:10X
4221984/A 05/2015
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
RUT0012A
UQFN - 0.55 mm max height
SCALE 6.800
PLASTIC QUAD FLATPACK - NO LEAD
1.8
1.6
A
B
0.6
0.4
PIN 1 INDEX AREA
0.25
(0.15)
0.15
2.1
1.9
PIN 1 ID
OPTIONAL TERMINAL & PIN 1 ID
C
0.55 MAX
SEATING PLANE
0.08 C
0.05
0.00
SYMM
6
(0.15) TYP
10X 0.4
5
7
2X
SYMM
1.6
11
1
0.25
0.15
12
12X
PIN 1 ID
(OPTIONAL)
0.6
0.4
12X
0.1
C B A
C
0.05
4220310/A 11/2016
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
RUT0012A
UQFN - 0.55 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
SYMM
12
12X (0.7)
(R0.05) TYP
11
1
12X (0.2)
SYMM
(1.7)
8X (0.4)
7
5
6
(1.4)
LAND PATTERN EXAMPLE
SCALE:30X
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
METAL
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4220310/A 11/2016
NOTES: (continued)
3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).
www.ti.com
EXAMPLE STENCIL DESIGN
RUT0012A
UQFN - 0.55 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
SYMM
12
12X (0.7)
(R0.05) TYP
11
1
12X (0.2)
SYMM
(1.7)
8X (0.4)
7
5
6
(1.4)
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
SCALE: 30X
4220310/A 11/2016
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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