TMUX1208QRSVRQ1 [TI]
具有 1.8V 逻辑电平的汽车类 5V、8:1、单通道多路复用器 | RSV | 16 | -40 to 125;
| 型号： | TMUX1208QRSVRQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有 1.8V 逻辑电平的汽车类 5V、8:1、单通道多路复用器 | RSV | 16 | -40 to 125 复用器 |
| 文件： | 总31页 (文件大小：1452K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ZHCSK56A – AUGUST 2019 – REVISED JULY 2020
TMUX1208-Q1
具有 1.8V 逻辑的 TMUX1208-Q1 5V 双向 8:1 多路复用器
1 特性
3 说明
•
符合面向汽车应用的 AEC-Q100 标准
TMUX1208-Q1 是一款通用互补金属氧化物半导体
(CMOS) 多路复用器 (MUX)。TMUX1208-Q1 采用 8:1
多路复用器配置，允许将 8 个不同的信号路径切换到
公共输出引脚。1.08V 至 5.5V 的宽工作电源电压范围
使其适用于具有各种电源要求的汽车应用。该器件可在
源极 (Sx) 和漏极 (D) 引脚上支持从 GND 到 VDD 范围
的双向模拟和数字信号。
– 温度等级 1：–40°C 至 125°C，TA
低导通电阻：5Ω
宽电源电压范围：1.08V 至 5.5V
轨到轨运行
•
•
•
•
•
•
•
•
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双向信号路径
兼容 1.8V 逻辑电平
失效防护逻辑
TMUX1208-Q1 采用小型 QFN 封装，以满足更小的系
统尺寸要求。该器件具有 5Ω 典型值的低导通电阻，
从而在器件未连接至高阻抗信号路径时将失真和信号完
整性问题的影响降至更低。
低电源电流：10nA
转换时间：14ns
先断后合开关
所有逻辑输入均具有{3}兼容 1.8V 逻辑{4}的阈值，当
器件在有效电源电压范围内运行时，这些阈值可确保
TTL 和 CMOS 逻辑兼容性。{5}失效防护逻辑{6}电路
允许先在控制引脚上施加电压，然后在电源引脚上施加
电压，从而保护器件免受潜在的损害。
• ESD 保护 HBM：2000V
小型 QFN 封装
•
2 应用
•
•
•
•
•
•
•
•
模拟和数字多路复用/多路信号分离
器件信息
汽车音响主机
器件型号(1)
封装尺寸（标称值）
封装
远程信息处理控制单元
紧急呼叫 (eCall)
TMUX1208-Q1
QFN (16)
2.60mm x 1.80mm
信息娱乐系统
(1) 如需了解所有可用封装，请参阅数据表末尾的封装选项附录。
车身控制模块 (BCM)
车身电子装置和照明
电池管理系统 (BMS)
空白
• HVAC 控制器模块
• ADAS 域控制器
VDD
TMUX1208-Q1
VDD
VI/O
VDD
LDO #1
S1
S2
S3
EN
MCU
S1
S2
S3
S4
S5
S6
S7
S8
LDO #2
LDO #3
RAM
FLASH
S4
D
S5
D
Integrated
12-bit ADC
S6
S7
S8
LM20
Analog Temp.
Sensor
LM20
Analog Temp.
Sensor
Port I/O
TIMERS
1-OF-8
A2
A1
LM20
Analog Temp.
Sensor
A0
DECODER
GND
1.8V Logic
I/O
System Inputs &
Sensors
A0 A1 A2 EN
TMUX1208-Q1 方框图
应用示例
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SCDS415
TMUX1208-Q1
ZHCSK56A – AUGUST 2019 – REVISED JULY 2020
www.ti.com.cn
Table of Contents
7.6 tON(EN) and tOFF(EN) .................................................. 15
7.7 Charge Injection........................................................16
7.8 Off Isolation...............................................................16
7.9 Crosstalk...................................................................17
7.10 Bandwidth............................................................... 17
8 Detailed Description......................................................18
8.1 Overview...................................................................18
8.2 Functional Block Diagram.........................................18
8.3 Feature Description...................................................18
9 Power Supply Recommendations................................21
10 Layout...........................................................................22
10.1 Layout Guidelines................................................... 22
10.2 Layout Example...................................................... 23
11 Device and Documentation Support..........................24
11.1 Third-Party Products Disclaimer............................. 24
11.2 Documentation Support.......................................... 24
11.3 Receiving Notification of Documentation Updates..24
11.4 Support Resources................................................. 24
11.5 Trademarks............................................................. 24
12 Electrostatic Discharge Caution................................ 24
13 Glossary....................................................................... 24
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
Pin Functions.................................................................... 3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................4
6.4 Thermal Information....................................................4
6.5 Electrical Characteristics (VDD = 5 V ±10 %).............5
6.6 Electrical Characteristics (VDD = 3.3 V ±10 %)..........7
6.7 Electrical Characteristics (VDD = 1.8 V ±10 %)..........9
6.8 Electrical Characteristics (VDD = 1.2 V ±10 %)........ 11
7 Parameter Measurement Information..........................13
7.1 On-Resistance.......................................................... 13
7.2 Off-Leakage Current................................................. 13
7.3 On-Leakage Current................................................. 14
7.4 Transition Time......................................................... 14
7.5 Break-Before-Make...................................................15
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision * (August, 2019) to Revision A (July, 2020)
Page
•
将数据表发布为“生产数据”.............................................................................................................................1
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5 Pin Configuration and Functions
N.C.
S1
1
12
11
10
9
GND
VDD
S5
2
3
4
S2
S3
S6
Not to scale
图 5-1. RSV Package 16-Pin QFN Top View
Pin Functions
PIN
TYPE(1)
DESCRIPTION
NAME
UQFN
A0
15
16
I
I
Address line 0. Controls the switch configuration as shown in 表 8-1.
Active high logic input. When this pin is low, all switches are turned off. When this pin is high, the A[2:0]
address inputs determine which switch is turned on.
EN
N.C.
S1
S2
S3
S4
D
1
2
Not Connected
Not Connected
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Source pin 1. Can be an input or output.
Source pin 2. Can be an input or output.
Source pin 3. Can be an input or output.
Source pin 4. Can be an input or output.
Drain pin. Can be an input or output.
Source pin 8. Can be an input or output.
Source pin 7. Can be an input or output.
Source pin 6. Can be an input or output.
Source pin 5. Can be an input or output.
3
4
5
6
S8
S7
S6
S5
7
8
9
10
Positive power supply. This pin is the most positive power-supply potential. For reliable operation,
connect a decoupling capacitor ranging from 0.1 µF to 10 µF between VDD and GND.
VDD
11
P
GND
A2
12
13
14
P
I
Ground (0 V) reference
Address line 2. Controls the switch configuration as shown in 表 8-1.
Address line 1. Controls the switch configuration as shown in 表 8-1.
A1
I
(1) I = input, O = output, I/O = input and output, P = power
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1) (2) (3)
MIN
–0.3
–0.3
–30
–0.5
–30
–30
–65
MAX
UNIT
V
VDD
Supply voltage
6
6
VLOGIC
ILOGIC
VS or VD
IS or ID (CONT)
IIK
Logic control input pin voltage (EN, A0, A1, A2)
Logic control input pin current (EN, A0, A1, A2)
Source or drain voltage (Sx, D)
Source or drain continuous current (Sx, D)
Diode clamp current(4)
V
30
mA
V
VDD+0.5
30
mA
mA
°C
°C
30
Tstg
Storage temperature
150
150
TJ
Junction temperature
(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) The algebraic convention, whereby the most negative value is a minimum and the most positive value is a maximum.
(3) All voltages are with respect to ground, unless otherwise specified.
(4) Signal path pins are diode-clamped to the power-supply rails. Over voltage signals must be voltage and current limited to maximum
ratings.
6.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per AEC Q100-002(1)
HBM ESD Classification Level 2
±2000
Electrostatic
discharge
V(ESD)
V
Charged device model (CDM), per AEC Q100-011
CDM ESD Classification Level C4B
±750
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
1.08
0
NOM
MAX
5.5
UNIT
V
VDD
Supply voltage
VS or VD
VLOGIC
TA
Signal path input/output voltage (source or drain pin) (Sx, D)
Logic control input pin voltage (EN, A0, A1, A2)
Ambient temperature
VDD
5.5
V
0
V
125
°C
–40
6.4 Thermal Information
TMUX1208-Q1
RSV (QFN)
16 PINS
134.6
THERMAL METRIC(1)
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
74.3
62.8
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
4.3
ΨJT
61.1
ΨJB
RθJC(bot)
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Electrical Characteristics (VDD = 5 V ±10 %)
at TA = 25°C, VDD = 5 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX UNIT
ANALOG SWITCH
25°C
5
Ω
VS = 0 V to VDD
ISD = 10 mA
Refer to 图 7-1
7
RON
On-resistance
–40°C to +85°C
–40°C to +125°C
25°C
Ω
9
Ω
0.15
Ω
VS = 0 V to VDD
ISD = 10 mA
Refer to 图 7-1
On-resistance matching between
channels
1
–40°C to +85°C
–40°C to +125°C
25°C
ΔRON
Ω
1
Ω
1.5
2
Ω
Ω
VS = 0 V to VDD
ISD = 10 mA
Refer to 图 7-1
RON
On-resistance flatness
–40°C to +85°C
–40°C to +125°C
25°C
FLAT
3
Ω
VDD = 5 V
±75
nA
Switch Off
-150
-175
150
175
nA
nA
–40°C to +85°C
IS(OFF) Source off leakage current(1)
VD = 4.5 V / 1 V
VS = 1 V / 4.5 V
Refer to 图 7-2
–40°C to +125°C
VDD = 5 V
Switch Off
VD = 4.5 V / 1 V
VS = 1 V / 4.5 V
Refer to 图 7-2
25°C
±200
±200
nA
nA
-500
-750
500
750
–40°C to +85°C
ID(OFF) Drain off leakage current(1)
nA
–40°C to +125°C
VDD = 5 V
Switch On
VD = VS = 4.5 V / 1 V
Refer to 图 7-3
25°C
nA
nA
nA
ID(ON)
-500
-750
500
750
Channel on leakage current
IS(ON)
–40°C to +85°C
–40°C to +125°C
LOGIC INPUTS (EN, A0, A1, A2)
VIH
VIL
Input logic high
Input logic low
-40°C to 125°C
-40°C to 125°C
1.49
0
5.5
V
V
0.87
IIH
IIL
Input leakage current
Input leakage current
25°C
±0.005
1
µA
µA
IIH
IIL
±0.10
2
–40°C to +125°C
CIN
CIN
Logic input capacitance
Logic input capacitance
25°C
pF
pF
–40°C to +125°C
POWER SUPPLY
25°C
0.02
µA
µA
IDD
VDD supply current
Logic inputs = 0 V or 5.5 V
2.7
–40°C to +125°C
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at TA = 25°C, VDD = 5 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX UNIT
DYNAMIC CHARACTERISTICS
25°C
14
ns
VS = 3 V
33
33
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tTRAN
Transition time between channels
RL = 200 Ω, CL = 15 pF
Refer to 图 7-4
–40°C to +85°C
–40°C to +125°C
25°C
8
14
11
VS = 3 V
RL = 200 Ω, CL = 15 pF
Refer to 图 7-5
tOPEN
1
1
Break before make time
–40°C to +85°C
–40°C to +125°C
25°C
(BBM)
VS = 3 V
RL = 200 Ω, CL = 15 pF
Refer to 图 7-6
20
20
tON(EN) Enable turn-on time
tOFF(EN) Enable turn-off time
–40°C to +85°C
–40°C to +125°C
25°C
VS = 3 V
RL = 200 Ω, CL = 15 pF
Refer to 图 7-6
20
20
–40°C to +85°C
–40°C to +125°C
VS = VDD/2
QC
Charge Injection
Off Isolation
RS = 0 Ω, CL = 1 nF
Refer to 图 7-7
25°C
25°C
25°C
25°C
-8
-62
-42
-62
pC
dB
dB
dB
RL = 50 Ω, CL = 5 pF
f = 1 MHz
Refer to 图 7-8
OISO
RL = 50 Ω, CL = 5 pF
f = 10 MHz
Refer to 图 7-8
RL = 50 Ω, CL = 5 pF
f = 1 MHz
Refer to 图 7-9
XTALK
Crosstalk
RL = 50 Ω, CL = 5 pF
f = 10 MHz
Refer to 图 7-9
25°C
25°C
-42
65
dB
RL = 50 Ω, CL = 5 pF
Refer to 图 7-10
BW
Bandwidth
MHz
CSOFF Source off capacitance
CDOFF Drain off capacitance
f = 1 MHz
f = 1 MHz
25°C
25°C
13
76
pF
pF
CSON
On capacitance
CDON
f = 1 MHz
25°C
85
pF
(1) When VS is 4.5 V, VD is 1.5 V or when VS is 1.5 V, VD is 4.5 V.
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6.6 Electrical Characteristics (VDD = 3.3 V ±10 %)
at TA = 25°C, VDD = 3.3 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX UNIT
ANALOG SWITCH
25°C
9
Ω
VS = 0 V to VDD
ISD = 10 mA
Refer to 图 7-1
15
RON
On-resistance
–40°C to +85°C
–40°C to +125°C
25°C
Ω
17
Ω
0.15
Ω
VS = 0 V to VDD
ISD = 10 mA
Refer to 图 7-1
On-resistance matching between
channels
1
–40°C to +85°C
–40°C to +125°C
25°C
ΔRON
Ω
1
Ω
3
5
Ω
Ω
VS = 0 V to VDD
ISD = 10 mA
Refer to 图 7-1
RON
On-resistance flatness
–40°C to +85°C
–40°C to +125°C
25°C
FLAT
6
Ω
VDD = 3.3 V
Switch Off
VD = 3 V / 1 V
VS = 1 V / 3 V
Refer to 图 7-2
±75
nA
-150
-175
150
175
nA
nA
–40°C to +85°C
IS(OFF) Source off leakage current(1)
–40°C to +125°C
VDD = 3.3 V
Switch Off
VD = 3 V / 1 V
VS = 1 V / 3 V
Refer to 图 7-2
25°C
±200
±200
nA
nA
-500
-750
500
750
–40°C to +85°C
ID(OFF) Drain off leakage current(1)
nA
–40°C to +125°C
VDD = 3.3 V
Switch On
VD = VS = 3 V / 1 V
Refer to 图 7-3
25°C
nA
nA
nA
ID(ON)
-500
-750
500
750
Channel on leakage current
IS(ON)
–40°C to +85°C
–40°C to +125°C
LOGIC INPUTS (EN, A0, A1, A2)
VIH
VIL
Input logic high
Input logic low
-40°C to 125°C
-40°C to 125°C
1.35
0
5.5
0.8
V
V
IIH
IIL
Input leakage current
Input leakage current
25°C
±0.005
1
µA
µA
IIH
IIL
±0.10
2
–40°C to +125°C
CIN
CIN
Logic input capacitance
Logic input capacitance
25°C
pF
pF
–40°C to +125°C
POWER SUPPLY
25°C
0.01
µA
µA
IDD
VDD supply current
Logic inputs = 0 V or 5.5 V
1.5
–40°C to +125°C
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at TA = 25°C, VDD = 3.3 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX UNIT
DYNAMIC CHARACTERISTICS
25°C
14
ns
VS = 2 V
25
25
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tTRAN
Transition time between channels
RL = 200 Ω, CL = 15 pF
Refer to 图 7-4
–40°C to +85°C
–40°C to +125°C
25°C
8
17
7
VS = 2 V
RL = 200 Ω, CL = 15 pF
Refer to 图 7-5
tOPEN
1
1
Break before make time
–40°C to +85°C
–40°C to +125°C
25°C
(BBM)
VS = 2 V
RL = 200 Ω, CL = 15 pF
Refer to 图 7-6
25
25
tON(EN) Enable turn-on time
tOFF(EN) Enable turn-off time
–40°C to +85°C
–40°C to +125°C
25°C
VS = 2 V
RL = 200 Ω, CL = 15 pF
Refer to 图 7-6
13
13
–40°C to +85°C
–40°C to +125°C
VS = VDD/2
QC
Charge Injection
Off Isolation
RS = 0 Ω, CL = 1 nF
Refer to 图 7-7
25°C
25°C
25°C
25°C
±7
-62
-42
-62
pC
dB
dB
dB
RL = 50 Ω, CL = 5 pF
f = 1 MHz
Refer to 图 7-8
OISO
RL = 50 Ω, CL = 5 pF
f = 10 MHz
Refer to 图 7-8
RL = 50 Ω, CL = 5 pF
f = 1 MHz
Refer to 图 7-9
XTALK
Crosstalk
RL = 50 Ω, CL = 5 pF
f = 10 MHz
Refer to 图 7-9
25°C
25°C
-42
65
dB
RL = 50 Ω, CL = 5 pF
Refer to 图 7-10
BW
Bandwidth
MHz
CSOFF Source off capacitance
CDOFF Drain off capacitance
f = 1 MHz
f = 1 MHz
25°C
25°C
13
76
pF
pF
CSON
On capacitance
CDON
f = 1 MHz
25°C
85
pF
(1) When VS is 3 V, VD is 1 V or when VS is 1 V, VD is 3 V.
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6.7 Electrical Characteristics (VDD = 1.8 V ±10 %)
at TA = 25°C, VDD = 1.8 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX UNIT
ANALOG SWITCH
25°C
40
Ω
VS = 0 V to VDD
ISD = 10 mA
Refer to 图 7-1
80
RON
On-resistance
–40°C to +85°C
–40°C to +125°C
25°C
Ω
80
Ω
0.15
±75
Ω
VS = 0 V to VDD
ISD = 10 mA
Refer to 图 7-1
On-resistance matching between
channels
1.5
–40°C to +85°C
–40°C to +125°C
25°C
ΔRON
Ω
1.5
Ω
VDD = 1.98 V
Switch Off
VD = 1.8 V / 1 V
VS = 1 V / 1.8 V
Refer to 图 7-2
nA
-150
-175
150
175
nA
nA
–40°C to +85°C
IS(OFF) Source off leakage current(1)
–40°C to +125°C
VDD = 1.98 V
Switch Off
VD = 1.8 V / 1 V
VS = 1 V / 1.8 V
Refer to 图 7-2
25°C
±200
±200
nA
nA
-500
-750
500
750
–40°C to +85°C
ID(OFF) Drain off leakage current(1)
nA
–40°C to +125°C
VDD = 1.98 V
Switch On
VD = VS = 1.8 V / 1 V
Refer to 图 7-3
25°C
nA
nA
nA
ID(ON)
-500
-750
500
750
Channel on leakage current
IS(ON)
–40°C to +85°C
–40°C to +125°C
LOGIC INPUTS (EN, A0, A1, A2)
VIH
VIL
Input logic high
Input logic low
1.07
0
5.5
V
V
–40°C to +125°C
–40°C to +125°C
0.68
IIH
IIL
Input leakage current
Input leakage current
25°C
±0.005
1
µA
µA
IIH
IIL
±0.10
2
–40°C to +125°C
25°C
pF
pF
CIN
Logic input capacitance
–40°C to +125°C
POWER SUPPLY
25°C
0.006
µA
µA
IDD
VDD supply current
Logic inputs = 0 V or 5.5 V
0.95
–40°C to +125°C
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at TA = 25°C, VDD = 1.8 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX UNIT
DYNAMIC CHARACTERISTICS
25°C
28
ns
VS = 1 V
48
48
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tTRAN
Transition time between channels
RL = 200 Ω, CL = 15 pF
Refer to 图 7-4
–40°C to +85°C
–40°C to +125°C
25°C
16
28
16
VS = 1 V
RL = 200 Ω, CL = 15 pF
Refer to 图 7-5
tOPEN
1
1
Break before make time
–40°C to +85°C
–40°C to +125°C
25°C
(BBM)
VS = 1 V
RL = 200 Ω, CL = 15 pF
Refer to 图 7-6
48
48
tON(EN) Enable turn-on time
tOFF(EN) Enable turn-off time
–40°C to +85°C
–40°C to +125°C
25°C
VS = 1 V
RL = 200 Ω, CL = 15 pF
Refer to 图 7-6
27
27
–40°C to +85°C
–40°C to +125°C
VS = VDD/2
QC
Charge Injection
Off Isolation
RS = 0 Ω, CL = 1 nF
Refer to 图 7-7
25°C
25°C
25°C
25°C
-2
-62
-42
-62
pC
dB
dB
dB
RL = 50 Ω, CL = 5 pF
f = 1 MHz
Refer to 图 7-8
OISO
RL = 50 Ω, CL = 5 pF
f = 10 MHz
Refer to 图 7-8
RL = 50 Ω, CL = 5 pF
f = 1 MHz
Refer to 图 7-9
XTALK
Crosstalk
RL = 50 Ω, CL = 5 pF
f = 10 MHz
Refer to 图 7-9
25°C
25°C
-42
65
dB
RL = 50 Ω, CL = 5 pF
Refer to 图 7-10
BW
Bandwidth
MHz
CSOFF Source off capacitance
CDOFF Drain off capacitance
f = 1 MHz
f = 1 MHz
25°C
25°C
13
76
pF
pF
CSON
On capacitance
CDON
f = 1 MHz
25°C
85
pF
(1) When VS is 1.8 V, VD is 1 V or when VS is 1 V, VD is 1.8 V.
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6.8 Electrical Characteristics (VDD = 1.2 V ±10 %)
at TA = 25°C, VDD = 1.2 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX UNIT
ANALOG SWITCH
25°C
70
Ω
VS = 0 V to VDD
ISD = 10 mA
Refer to 图 7-1
105
RON
On-resistance
–40°C to +85°C
–40°C to +125°C
25°C
Ω
105
Ω
0.15
±75
Ω
VS = 0 V to VDD
ISD = 10 mA
Refer to 图 7-1
On-resistance matching between
channels
1.5
–40°C to +85°C
–40°C to +125°C
25°C
ΔRON
Ω
1.5
Ω
VDD = 1.32 V
Switch Off
VD = 1.2 V / 1 V
VS = 1 V / 1.2 V
Refer to 图 7-2
nA
-150
-175
150
175
nA
nA
–40°C to +85°C
IS(OFF) Source off leakage current(1)
–40°C to +125°C
VDD = 1.32 V
Switch Off
VD = 1.2 V / 1 V
VS = 1 V / 1.2 V
Refer to 图 7-2
25°C
±200
±200
nA
nA
-500
-750
500
750
–40°C to +85°C
ID(OFF) Drain off leakage current(1)
nA
–40°C to +125°C
VDD = 1.32 V
Switch On
VD = VS = 1.2 V / 1 V
Refer to 图 7-3
25°C
nA
nA
nA
ID(ON)
-500
-750
500
750
Channel on leakage current
IS(ON)
–40°C to +85°C
–40°C to +125°C
LOGIC INPUTS (EN, A0, A1, A2)
VIH
VIL
Input logic high
Input logic low
0.96
0
5.5
V
V
–40°C to +125°C
–40°C to +125°C
0.36
IIH
IIL
Input leakage current
Input leakage current
25°C
±0.005
1
µA
µA
IIH
IIL
±0.10
2
–40°C to +125°C
25°C
pF
pF
CIN
Logic input capacitance
–40°C to +125°C
POWER SUPPLY
25°C
0.005
µA
µA
IDD
VDD supply current
Logic inputs = 0 V or 5.5 V
0.8
–40°C to +125°C
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at TA = 25°C, VDD = 1.2 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA
MIN
TYP
MAX UNIT
DYNAMIC CHARACTERISTICS
25°C
60
ns
VS = 1 V
210
210
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tTRAN
Transition time between channels
RL = 200 Ω, CL = 15 pF
Refer to 图 7-4
–40°C to +85°C
–40°C to +125°C
25°C
32
60
45
VS = 1 V
RL = 200 Ω, CL = 15 pF
Refer to 图 7-5
tOPEN
1
1
Break before make time
–40°C to +85°C
–40°C to +125°C
25°C
(BBM)
VS = 1 V
RL = 200 Ω, CL = 15 pF
Refer to 图 7-6
190
190
tON(EN) Enable turn-on time
tOFF(EN) Enable turn-off time
–40°C to +85°C
–40°C to +125°C
25°C
VS = 1 V
RL = 200 Ω, CL = 15 pF
Refer to 图 7-6
150
150
–40°C to +85°C
–40°C to +125°C
VS = VDD/2
QC
Charge Injection
Off Isolation
RS = 0 Ω, CL = 1 nF
Refer to 图 7-7
25°C
25°C
25°C
25°C
-2
-62
-42
-62
pC
dB
dB
dB
RL = 50 Ω, CL = 5 pF
f = 1 MHz
Refer to 图 7-8
OISO
RL = 50 Ω, CL = 5 pF
f = 10 MHz
Refer to 图 7-8
RL = 50 Ω, CL = 5 pF
f = 1 MHz
Refer to 图 7-9
XTALK
Crosstalk
RL = 50 Ω, CL = 5 pF
f = 10 MHz
Refer to 图 7-9
25°C
25°C
-42
65
dB
RL = 50 Ω, CL = 5 pF
Refer to 图 7-10
BW
Bandwidth
MHz
CSOFF Source off capacitance
CDOFF Drain off capacitance
f = 1 MHz
f = 1 MHz
25°C
25°C
13
76
pF
pF
CSON
On capacitance
CDON
f = 1 MHz
25°C
85
pF
(1) When VS is 1.2 V, VD is 1 V or when VS is 1 V, VD is 1.2 V.
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7 Parameter Measurement Information
7.1 On-Resistance
The on-resistance of a device is the ohmic resistance between the source (Sx) and drain (D) pins of the device.
The on-resistance varies with input voltage and supply voltage. The symbol RON is used to denote on-
resistance. The measurement setup used to measure RON is shown below. Voltage (V) and current (ISD) are
measured using this setup, and RON is computed as shown in 图 7-1 with RON = V / ISD
:
V
ISD
Sx
D
VS
图 7-1. On-Resistance Measurement Setup
7.2 Off-Leakage Current
There are two types of leakage currents associated with a switch during the off state:
1. Source off-leakage current
2. Drain off-leakage current
Source leakage current is defined as the leakage current flowing into or out of the source pin when the switch is
off. This current is denoted by the symbol IS(OFF)
.
Drain leakage current is defined as the leakage current flowing into or out of the drain pin when the switch is off.
This current is denoted by the symbol ID(OFF)
.
The setup used to measure both off-leakage currents is shown in 图 7-2.
VDD
VDD
VDD
VDD
Is (OFF)
S1
S2
S1
A
ID (OFF)
S2
D
D
A
VS
S8
S8
VS
VD
VD
GND
GND
图 7-2. Off-Leakage Measurement Setup
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7.3 On-Leakage Current
Source on-leakage current is defined as the leakage current flowing into or out of the source pin when the switch
is on. This current is denoted by the symbol IS(ON)
.
Drain on-leakage current is defined as the leakage current flowing into or out of the drain pin when the switch is
on. This current is denoted by the symbol ID(ON)
.
Either the source pin or drain pin is left floating during the measurement. 图 7-3 shows the circuit used for
measuring the on-leakage current, denoted by IS(ON) or ID(ON)
.
VDD
VDD
VDD
VDD
IS (ON)
S1
S1
S2
A
N.C.
ID (ON)
S2
D
D
A
N.C.
S8
S8
Vs
VS
VS
VD
GND
GND
图 7-3. On-Leakage Measurement Setup
7.4 Transition Time
Transition time is defined as the time taken by the output of the device to rise or fall 10% after the address signal
has risen or fallen past the logic threshold. The 10% transition measurement is utilized to provide the timing of
the device, system level timing can then account for the time constant added from the load resistance and load
capacitance. 图 7-4 shows the setup used to measure transition time, denoted by the symbol tTRANSITION
.
VDD
0.1…F
VDD
VDD
ADDRESS
DRIVE
(VSEL
tf < 5ns
tr < 5ns
VIH
S1
)
VS
OUTPUT
VIL
D
0 V
S2
S8
RL
CL
tTRANSITION
tTRANSITION
A0
A1
A2
90%
OUTPUT
VSEL
10%
GND
0 V
图 7-4. Transition-Time Measurement Setup
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7.5 Break-Before-Make
Break-before-make delay is a safety feature that prevents two inputs from connecting when the device is
switching. The output first breaks from the on-state switch before making the connection with the next on-state
switch. The time delay between the break and the make is known as break-before-make delay. 图 7-5 shows the
setup used to measure break-before-make delay, denoted by the symbol tOPEN(BBM)
.
VDD
0.1…F
VDD
VDD
S1
ADDRESS
DRIVE
VS
OUTPUT
D
tr < 5ns
tf < 5ns
(VSEL
)
S2-S7
0 V
RL
CL
S8
90%
Output
A0
A1
A2
tBBM
1
tBBM 2
0 V
VSEL
tOPEN (BBM) = min ( tBBM 1, tBBM 2)
GND
图 7-5. Break-Before-Make Delay Measurement Setup
7.6 tON(EN) and tOFF(EN)
Turn-on time is defined as the time taken by the output of the device to rise to 10% after the enable has risen
past the logic threshold. The 10% measurement is utilized to provide the timing of the device, system level timing
can then account for the time constant added from the load resistance and load capacitance. 图 7-6 shows the
setup used to measure transition time, denoted by the symbol tON(EN)
.
Turn-off time is defined as the time taken by the output of the device to fall to 90% after the enable has fallen
past the logic threshold. The 90% measurement is utilized to provide the timing of the device, system level timing
can then account for the time constant added from the load resistance and load capacitance. 图 7-6 shows the
setup used to measure transition time, denoted by the symbol tOFF(EN)
.
VDD
0.1…F
VDD
VDD
tf < 5ns
tr < 5ns
ENABLE
DRIVE
S1
VS
OUTPUT
VIH
(VEN
)
D
VIL
S2
S8
0 V
RL
CL
tOFF
tON
(EN)
(EN)
A0
A1
A2
EN
90%
OUTPUT
0 V
VEN
10%
GND
图 7-6. Turn-On and Turn-Off Time Measurement Setup
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7.7 Charge Injection
The TMUX1208-Q1 has a transmission-gate topology. Any mismatch in capacitance between the NMOS and
PMOS transistors results in a charge injected into the drain or source during the falling or rising edge of the gate
signal. The amount of charge injected into the source or drain of the device is known as charge injection, and is
denoted by the symbol QC. 图 7-7 shows the setup used to measure charge injection from source (Sx) to drain
(D).
VDD
0.1…F
VDD
VDD
S1
VS
OUTPUT
D
VOUT
0 V
S2
S8
CL
Output
VOUT
VS
QC = CL
×
VOUT
A0
A1
A2
EN
VEN
GND
图 7-7. Charge-Injection Measurement Setup
7.8 Off Isolation
Off isolation is defined as the ratio of the signal at the drain pin (D) of the device when a signal is applied to the
source pin (Sx) of an off-channel. 图 7-8 shows the setup used to measure, and the equation to compute off
isolation.
0.1µF
NETWORK
VDD
ANALYZER
VS
S
50Q
VSIG
D
VOUT
RL
SX/DX
50Q
GND
RL
50Q
图 7-8. Off Isolation Measurement Setup
≈
∆
«
’
VOUT
VS
Off Isolation = 20 ∂ Log
÷
◊
(1)
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7.9 Crosstalk
Crosstalk is defined as the ratio of the signal at the drain pin (D) of a different channel, when a signal is applied
at the source pin (Sx) of an on-channel. 图 7-9 shows the setup used to measure, and the equation used to
compute crosstalk.
0.1µF
NETWORK
VDD
ANALYZER
S1
VOUT
RL
D
50Q
VS
RL
S2
50Q
50Q
VSIG
SX
RL
GND
50Q
图 7-9. Channel-to-Channel Crosstalk Measurement Setup
≈
∆
«
’
÷
◊
VOUT
VS
Channel-to-Channel Crosstalk = 20 ∂ Log
(2)
7.10 Bandwidth
Bandwidth is defined as the range of frequencies that are attenuated by less than 3 dB when the input is applied
to the source pin (Sx) of an on-channel, and the output is measured at the drain pin (D) of the device. 图 7-10
shows the setup used to measure bandwidth.
0.1µF
NETWORK
VDD
ANALYZER
VS
S
50Q
VSIG
D
VOUT
RL
50Q
GND
图 7-10. Bandwidth Measurement Setup
≈
∆
«
’
÷
◊
V2
Attenuation = 20 ∂ Log
V
1
(3)
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8 Detailed Description
8.1 Overview
The TMUX1208-Q1 is an 8:1, single-ended (1-channel), mux. Each channel is turned on or off based on the
state of the address lines and enable pin.
8.2 Functional Block Diagram
TMUX1208-Q1
S1
S2
S3
S4
D
S5
S6
S7
S8
1-OF-8
DECODER
A0 A1 A2 EN
8.3 Feature Description
8.3.1 Bidirectional Operation
The TMUX1208-Q1 conducts equally well from source (Sx) to drain (D) or from drain (D) to source (Sx). Each
channel has very similar characteristics in both directions and supports both analog and digital signals.
8.3.2 Rail to Rail Operation
The valid signal path input/output voltage for TMUX1208-Q1 ranges from GND to VDD
.
8.3.3 1.8 V Logic Compatible Inputs
The TMUX1208-Q1 has 1.8-V logic compatible control for all logic control inputs. The logic input thresholds scale
with supply but still provide 1.8-V logic control when operating at 5.5 V supply voltage. 1.8-V logic level inputs
allows the multiplexers to interface with processors that have lower logic I/O rails and eliminates the need for an
external translator, which saves both space and BOM cost. For more information on 1.8 V logic implementations
refer to Simplifying Design with 1.8 V logic Muxes and Switches
8.3.4 Fail-Safe Logic
The TMUX1208-Q1 has Fail-Safe Logic on the control input pins (EN, A0. A1, A2) allowing for operation up to
5.5 V, regardless of the state of the supply pin. This feature allows voltages on the control pins to be applied
before the supply pin, protecting the device from potential damage. Fail-Safe Logic minimizes system complexity
by removing the need for power supply sequencing on the logic control pins. For example, the Fail-Safe Logic
feature allows the select pins of the TMUX1208-Q1 to be ramped to 5.5 V while VDD = 0 V. Additionally, the
feature enables operation of the multiplexers with VDD = 1.2 V while allowing the select pins to interface with a
logic level of another device up to 5.5 V.
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8.3.5 Device Functional Modes
When the EN pin of the TMUX1208-Q1 is pulled high, one of the switches is closed based on the state of the
address lines. When the EN pin is pulled low, all the switches are in an open state regardless of the state of the
address lines.
The TMUX1208-Q1 can be operated without any external components except for the supply decoupling
capacitors. Unused logic control pins should be tied to GND or VDD in order to ensure the device does not
consume additional current as highlighted in Implications of Slow or Floating CMOS Inputs. Unused signal path
inputs (Sx or D) should be connected to GND.
8.3.6 Truth Tables
表 8-1 shows the truth tables for the TMUX1208-Q1.
表 8-1. TMUX1208-Q1 Truth Table
EN A2 A1 A0 Selected Inputs Connected To Drain (D) Pin
0
1
1
1
1
1
1
1
1
X(1) X(1) X(1)
All channels are off
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
S1
S2
S3
S4
S5
S6
S7
S8
(1) X denotes don't care.
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Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
9.1 Application Information
The TMUX12xx family offers good system performance across a wide operating supply (1.08 V to 5.5 V). These
devices include 1.8 V logic compatible control input pins that enable operation in systems with 1.8 V I/O rails.
Additionally, the control input pins support Fail-Safe Logic which allows for operation up to 5.5 V, regardless of
the state of the supply pin. This protection stops the logic pins from back-powering the supply rail. These
features make the TMUX12xx a family of general purpose multiplexers and switches that can reduce system
complexity, board size, and overall system cost.
9.2 Typical Application
One useful application to take advantage of the TMUX1208-Q1 features is multiplexing various signals into an
ADC that is integrated into a MCU. Using an integrated ADC in a MCU allows a system to minimize cost with a
potential tradeoff of system performance when compared to an external ADC. The multiplexer allows for multiple
inputs/sensors to be monitored with a single ADC pin of the device, which is critical in systems with limited I/O.
VDD
VDD
VI/O
VDD
EN
LDO #1
MCU
S1
S2
S3
S4
S5
S6
S7
S8
LDO #2
LDO #3
RAM
FLASH
D
Integrated
12-bit ADC
LM20
Analog Temp.
Sensor
LM20
Analog Temp.
Sensor
Port I/O
TIMERS
A2
A1
LM20
Analog Temp.
Sensor
A0
GND
1.8V Logic
I/O
System Inputs &
Sensors
图 9-1. Multiplexing Signals to Integrated ADC
9.3 Design Requirements
For this design example, use the parameters listed in 表 9-1.
表 9-1. Design Parameters
PARAMETERS
Supply (VDD
VALUES
5.0 V
)
I/O signal range
0 V to VDD (Rail to Rail)
1.8 V compatible
Control logic thresholds
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9.4 Detailed Design Procedure
The TMUX1208-Q1 can be operated without any external components except for the supply decoupling
capacitors. If the parts desired power-up state is disabled, the enable pin should have a weak pull-down resistor
and be controlled by the MCU via GPIO. All inputs being muxed to the ADC of the MCU must fall within the
recommend operating conditions of the TMUX1208-Q1 including signal range and continuous current. For this
design with a supply of 5 V, the signal range can be 0 V to 5 V and the max continuous current can be 30 mA.
9.5 Application Curve
80
VDD= 1.08V
60
40
VDD= 1.62V
20
VDD= 3V
VDD= 4.5V
0
0
0.5
1
1.5
2
2.5
3
3.5
Source or Drain Voltage (V)
4
4.5
5
D001
TA = 25°C
图 9-2. On-Resistance vs Source or Drain Voltage
9 Power Supply Recommendations
The TMUX1208-Q1 operate across a wide supply range of 1.08 V to 5.5 V. Do not exceed the absolute
maximum ratings because stresses beyond the listed ratings can cause permanent damage to the devices.
Power-supply bypassing improves noise margin and prevents switching noise propagation from the VDD supply
to other components. Good power-supply decoupling is important to achieve optimum performance. For
improved supply noise immunity, use a supply decoupling capacitor ranging from 0.1 μF to 10 μF from VDD to
ground. Place the bypass capacitors as close to the power supply pins of the device as possible using low-
impedance connections. TI recommends using multi-layer ceramic chip capacitors (MLCCs) that offer low
equivalent series resistance (ESR) and inductance (ESL) characteristics for power-supply decoupling purposes.
For very sensitive systems, or for systems in harsh noise environments, avoiding the use of vias for connecting
the capacitors to the device pins may offer superior noise immunity. The use of multiple vias in parallel lowers
the overall inductance and is beneficial for connections to ground planes.
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10 Layout
10.1 Layout Guidelines
10.1.1 Layout Information
When a PCB trace turns a corner at a 90° angle, a reflection can occur. A reflection occurs primarily because of
the change of width of the trace. At the apex of the turn, the trace width increases to 1.414 times the width. This
increase upsets the transmission-line characteristics, especially the distributed capacitance and self–inductance
of the trace which results in the reflection. Not all PCB traces can be straight and therefore some traces must
turn corners. 图 10-1 shows progressively better techniques of rounding corners. Only the last example (BEST)
maintains constant trace width and minimizes reflections.
WORST
BETTER
BEST
2W
1W min.
W
图 10-1. Trace Example
Route high-speed signals using a minimum of vias and corners which reduces signal reflections and impedance
changes. When a via must be used, increase the clearance size around it to minimize its capacitance. Each via
introduces discontinuities in the signal’s transmission line and increases the chance of picking up interference
from the other layers of the board. Be careful when designing test points, through-hole pins are not
recommended at high frequencies.
10.1.2
图 10-2 illustrates an example of a PCB layout with the TMUX1208-Q1. Some key considerations are:
• Decouple the VDD pin with a 0.1-µF capacitor, placed as close to the pin as possible. Make sure that the
capacitor voltage rating is sufficient for the VDD supply.
• Keep the input lines as short as possible.
• Use a solid ground plane to help reduce electromagnetic interference (EMI) noise pickup.
• Do not run sensitive analog traces in parallel with digital traces. Avoid crossing digital and analog traces if
possible, and only make perpendicular crossings when necessary.
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10.2 Layout Example
Via to
ground plane
A0
EN
A1
A2
Wide (low inductance)
trace for power
C
GND
VDD
N.C.
Via to
ground plane
S1
S2
S3
S4
D
S5
S6
S7
S8
TMUX1208-Q1
图 10-2. TMUX1208-Q1 Layout Example
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ZHCSK56A – AUGUST 2019 – REVISED JULY 2020
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11 Device and Documentation Support
11.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
11.2 Documentation Support
11.2.1 Related Documentation
Texas Instruments, Simplifying Design with 1.8 V logic Muxes and Switches.
Texas Instruments, QFN/SON PCB Attachment.
Texas Instruments, Quad Flatpack No-Lead Logic Packages.
11.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.4 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.5 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
12 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
13 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TMUX1208QRSVRQ1
ACTIVE
UQFN
RSV
16
3000 RoHS & Green
NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
208Q
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Jun-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TMUX1208QRSVRQ1
UQFN
RSV
16
3000
178.0
13.5
2.1
2.9
0.75
4.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Jun-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
UQFN RSV 16
SPQ
Length (mm) Width (mm) Height (mm)
189.0 185.0 36.0
TMUX1208QRSVRQ1
3000
Pack Materials-Page 2
PACKAGE OUTLINE
RSV0016A
UQFN - 0.55 mm max height
S
C
A
L
E
5
.
0
0
0
ULTRA THIN QUAD FLATPACK - NO LEAD
1.85
1.75
A
B
PIN 1 INDEX AREA
2.65
2.55
C
0.55
0.45
SEATING PLANE
0.05 C
0.05
0.00
2X 1.2
SYMM
℄
(0.13) TYP
5
8
0.45
0.35
15X
4
9
SYMM
℄
2X 1.2
12X 0.4
1
0.25
16X
12
0.15
0.07
0.05
C A B
13
16
0.55
0.45
PIN 1 ID
(45° X 0.1)
4220314/C 02/2020
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
RSV0016A
UQFN - 0.55 mm max height
ULTRA THIN QUAD FLATPACK - NO LEAD
SYMM
℄
(0.7)
16
SEE SOLDER MASK
DETAIL
13
12
16X (0.2)
1
SYMM
℄
12X (0.4)
(2.4)
(R0.05) TYP
9
4
15X (0.6)
5
8
(1.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 25X
0.05 MIN
ALL AROUND
0.05 MAX
ALL AROUND
METAL UNDER
SOLDER MASK
METAL EDGE
EXPOSED METAL
SOLDER MASK
OPENING
EXPOSED
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4220314/C 02/2020
NOTES: (continued)
3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).
www.ti.com
EXAMPLE STENCIL DESIGN
RSV0016A
UQFN - 0.55 mm max height
ULTRA THIN QUAD FLATPACK - NO LEAD
(0.7)
16
13
16X (0.2)
1
12
SYMM
℄
12X (0.4)
(2.4)
(R0.05) TYP
4
9
15X (0.6)
5
8
SYMM
℄
(1.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 MM THICK STENCIL
SCALE: 25X
4220314/C 02/2020
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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