TMUX1219DCKR [TI]

具有 1.8V 输入逻辑的 5V、2:1 (SPDT)、单通道通用模拟开关 | DCK | 6 | -40 to 125;


型号：	TMUX1219DCKR
厂家：	TEXAS INSTRUMENTS
描述：	具有 1.8V 输入逻辑的 5V、2:1 (SPDT)、单通道通用模拟开关 \| DCK \| 6 \| -40 to 125 开关光电二极管
文件：	总34页 (文件大小：1633K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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TMUX1219

ZHCSJR5 –MAY 2019

TMUX1219 5V 双向、2:1 通用开关

1 特性

3 说明

•

轨至轨运行

TMUX1219 是一款通用互补金属氧化物半导体

(CMOS) 单极双投 (SPDT) 开关。TMUX1219 可根据

SEL 引脚的状态在两个输入电源之间切换。1.08V 至

5.5V 的宽电源电压工作范围可支持从个人电子设备到

楼宇自动化的各种应用。该器件可在源极 (Sx) 和漏极

(D) 引脚上支持从 GND 到 V_DD范围的双向模拟和数字

信号。4nA 的低电源电流可用于便携式应用。

双向信号路径

1.8V 逻辑兼容

失效防护逻辑

低导通电阻：3Ω

宽电源电压范围：1.08V 至 5.5V

-40°C 至 +125°C 的工作温度

低电源电流：4nA

转换时间：14ns

所有逻辑输入均具有兼容 1.8V 逻辑的阈值，当器件在

有效电源电压范围内运行时，这些阈值可确保 TTL 和

CMOS 逻辑兼容性。失效防护逻辑电路允许在电源引

脚之前的控制引脚上施加电压，从而保护器件免受潜在

的损害。

先断后合开关

ESD 保护 HBM：2000V

2 应用

器件信息⁽¹⁾

•

模拟和数字开关

器件型号

TMUX1219

封装

SC70 (6)

SOT-23 (6)⁽²⁾

封装尺寸（标称值）

2.00mm × 1.25mm

2.90mm x 1.60mm

I2C 和 SPI 总线多路复用

远程无线电单元

条形码扫描仪

电机驱动器

(1) 如需了解所有可用封装，请参阅数据表末尾的封装选项附录。

(2) 产品预览

楼宇自动化

模拟输入模块

电力输送

空白

视频监控

电子销售终端

电器

空白

消费类音频

应用示例

方框图

TMUX1219

Input

Output

Unity Gain

Inverting

TLV9001

1.8 V

SEL

TMUX1219

本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确

性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SCDS409

TMUX1219

ZHCSJR5 –MAY 2019

www.ti.com.cn

7.8 Crosstalk ................................................................. 17

7.9 Bandwidth ............................................................... 18

Detailed Description ............................................ 19

8.1 Functional Block Diagram ....................................... 19

8.2 Feature Description................................................. 19

8.3 Device Functional Modes........................................ 19

8.4 Truth Tables............................................................ 19

Application and Implementation ........................ 20

9.1 Application Information............................................ 20

9.2 Typical Application ................................................. 20

特性.......................................................................... 1

应用.......................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

Pin Configuration and Functions......................... 3

Specifications......................................................... 4

6.1 Absolute Maximum Ratings ...................................... 4

6.2 ESD Ratings.............................................................. 4

6.3 Recommended Operating Conditions....................... 4

6.4 Thermal Information.................................................. 4

6.5 Electrical Characteristics (V_DD= 5 V ±10 %)............ 5

6.6 Electrical Characteristics (V_DD= 3.3 V ±10 %)......... 7

6.7 Electrical Characteristics (V_DD= 1.8 V ±10 %)......... 9

6.8 Electrical Characteristics (V_DD= 1.2 V ±10 %)....... 11

6.9 Typical Characteristics............................................ 13

Parameter Measurement Information ................ 14

7.1 On-Resistance ........................................................ 14

7.2 Off-Leakage Current ............................................... 14

7.3 On-Leakage Current ............................................... 15

7.4 Transition Time ....................................................... 15

7.5 Break-Before-Make................................................. 16

7.6 Charge Injection...................................................... 16

7.7 Off Isolation............................................................. 17

10 Power Supply Recommendations ..................... 22

11 Layout................................................................... 23

11.1 Layout Guidelines ................................................. 23

11.2 Layout Example .................................................... 23

12 器件和文档支持 ..................................................... 24

12.1 文档支持................................................................ 24

12.2 接收文档更新通知 ................................................. 24

12.3 社区资源................................................................ 24

12.4 商标....................................................................... 24

12.5 静电放电警告......................................................... 24

12.6 Glossary................................................................ 24

13 机械、封装和可订购信息....................................... 24

4 修订历史记录

注：之前版本的页码可能与当前版本有所不同。

日期

修订版本

说明

2019 年 5 月

初始发行版。

TMUX1219

www.ti.com.cn

ZHCSJR5 –MAY 2019

5 Pin Configuration and Functions

DCK Package

6-Pin SC70

Top View

DBV Package

6-Pin SOT-23

Top View

SEL

VDD

GND

SEL

VDD

GND

Not to scale

Product Preview

Pin Functions

TYPE⁽¹⁾

DESCRIPTION

NAME

NO.

SEL

Select pin: controls state of the switch according to 表 1. (Logic Low = S1 to D, Logic High = S2 to D)

Positive power supply. This pin is the most positive power-supply potential. For reliable operation, connect

a decoupling capacitor ranging from 0.1 µF to 10 µF between V_DDand GND.

VDD

GND

Ground (0 V) reference

I/O

Source pin 1. Can be an input or output.

Drain pin. Can be an input or output.

Source pin 2. Can be an input or output.

(1) I = input, O = output, I/O = input and output, P = power

TMUX1219

ZHCSJR5 –MAY 2019

www.ti.com.cn

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾⁽²⁾

MIN

–0.5

–30

–0.5

–30

–65

MAX

UNIT

V_DD

Supply voltage

V_SEL

Logic control input pin voltage (SEL)

Logic control input pin current (SEL)

Source or drain voltage (Sx, D)

Source or drain continuous current (Sx, D)

Storage temperature

I_SEL

V_Sor V_D

I_Sor I_{D (CONT)}

T_stg

V_DD+0.5

°C

150

T_J

Junction temperature

150

(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) The algebraic convention, whereby the most negative value is a minimum and the most positive value is a maximum.

6.2 ESD Ratings

VALUE

UNIT

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins⁽¹⁾

±2000

V_(ESD)

Electrostatic discharge

Charged device model (CDM), per JEDEC specification JESD22-C101

or ANSI/ESDA/JEDEC JS-002, all pins⁽²⁾

±750

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

1.08

NOM

MAX

5.5

UNIT

V_DD

Supply voltage

V_Sor V_D

V_SEL

T_A

Signal path input/output voltage (source or drain pin) (Sx, D)

Logic control input pin voltage (SEL)

Ambient temperature

V_DD

5.5

–40

125

°C

6.4 Thermal Information

TMUX1219

THERMAL METRIC⁽¹⁾

SC70 (DCK)

6 PINS

243.1

UNIT

R_θJA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

°C/W

R_θJC(top)

R_θJB

206.0

128.3

Ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

107.8

Ψ_JB

128.0

R_θJC(bot)

N/A

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

TMUX1219

www.ti.com.cn

ZHCSJR5 –MAY 2019

6.5 Electrical Characteristics (V_DD= 5 V ±10 %)

at T_A= 25°C, V_DD= 5 V (unless otherwise noted)

PARAMETER

ANALOG SWITCH

TEST CONDITIONS

MIN

TYP

MAX UNIT

25°C

V_S= 0 V to V_DD

R_ON

On-resistance

I_SD= 10 mA

Refer to On-Resistance

–40°C to +85°C

–40°C to +125°C

25°C

0.15

V_S= 0 V to V_DD

I_SD= 10 mA

Refer to On-Resistance

On-resistance matching between

channels

ΔR_ON

–40°C to +85°C

–40°C to +125°C

25°C

0.4

1.5

V_S= 0 V to V_DD

I_SD= 10 mA

Refer to On-Resistance

R_ON

FLAT

On-resistance flatness

–40°C to +85°C

–40°C to +125°C

25°C

V_DD= 5 V

Switch Off

V_D= 4.5 V / 1.5 V

V_S= 1.5 V / 4.5 V

Refer to Off-Leakage Current

±5

–40°C to +85°C

–25

–40

I_S(OFF)

Source off leakage current⁽¹⁾

–40°C to +125°C

V_DD= 5 V

Switch On

V_D= V_S= 4.5 V / 1.5 V

Refer to On-Leakage Current

25°C

±15

I_D(ON)

I_S(ON)

–40°C to +85°C

–50

–80

Channel on leakage current

–40°C to +125°C

LOGIC INPUTS (SEL)

V_IH

V_IL

Input logic high

Input logic low

–40°C to +125°C

1.49

5.5

0.87

I_IH

I_IL

Input leakage current

25°C

±0.005

µA

I_IH

I_IL

–40°C to +125°C

±0.05

C_IN

Logic input capacitance

25°C

–40°C to +125°C

POWER SUPPLY

25°C

0.003

µA

I_DDV_DDsupply current

Logic inputs = 0 V or 5.5 V

–40°C to +125°C

1.5

(1) When V_Sis 4.5 V, V_Dis 1.5 V or when V_Sis 1.5 V, V_Dis 4.5 V.

TMUX1219

ZHCSJR5 –MAY 2019

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Electrical Characteristics (V_DD= 5 V ±10 %) (continued)

at T_A= 25°C, V_DD= 5 V (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

DYNAMIC CHARACTERISTICS

25°C

V_S= 3 V

t_TRAN

Switching time between channels R_L= 200 Ω, C_L= 15 pF

–40°C to +85°C

–40°C to +125°C

25°C

Refer to Transition Time

V_S= 3 V

t_OPEN

(BBM)

Break before make time

Charge Injection

R_L= 200 Ω, C_L= 15 pF

Refer to Break-Before-Make

–40°C to +85°C

–40°C to +125°C

V_D= 1 V

R_S= 0 Ω, C_L= 1 nF

Refer to Charge Injection

Q_C

25°C

–10

–65

–45

–65

–45

R_L= 50 Ω, C_L= 5 pF

f = 1 MHz

Refer to Off Isolation

O_ISO

Off Isolation

Crosstalk

R_L= 50 Ω, C_L= 5 pF

f = 10 MHz

Refer to Off Isolation

R_L= 50 Ω, C_L= 5 pF

f = 1 MHz

Refer to Crosstalk

X_TALK

R_L= 50 Ω, C_L= 5 pF

f = 10 MHz

Refer to Crosstalk

R_L= 50 Ω, C_L= 5 pF

Refer to Bandwidth

Bandwidth

25°C

250

MHz

C_SOFF

Source off capacitance

On capacitance

f = 1 MHz

C_SON

C_DON

f = 1 MHz

TMUX1219

www.ti.com.cn

ZHCSJR5 –MAY 2019

6.6 Electrical Characteristics (V_DD= 3.3 V ±10 %)

at T_A= 25°C, V_DD= 3.3 V (unless otherwise noted)

PARAMETER

ANALOG SWITCH

TEST CONDITIONS

MIN

TYP

MAX UNIT

25°C

V_S= 0 V to V_DD

R_ON

On-resistance

I_SD= 10 mA

Refer to On-Resistance

–40°C to +85°C

–40°C to +125°C

25°C

0.15

V_S= 0 V to V_DD

I_SD= 10 mA

Refer to On-Resistance

On-resistance matching between

channels

ΔR_ON

–40°C to +85°C

–40°C to +125°C

25°C

3.5

V_S= 0 V to V_DD

I_SD= 10 mA

Refer to On-Resistance

R_ON

FLAT

On-resistance flatness

–40°C to +85°C

–40°C to +125°C

25°C

V_DD= 3.3 V

Switch Off

V_D= 3 V / 1 V

V_S= 1 V / 3 V

±5

–40°C to +85°C

–25

–40

I_S(OFF)

Source off leakage current⁽¹⁾

–40°C to +125°C

Refer to Off-Leakage Current

V_DD= 3.3 V

Switch On

V_D= V_S= 3 V / 1 V

Refer to On-Leakage Current

25°C

±15

I_D(ON)

I_S(ON)

–40°C to +85°C

–50

–80

Channel on leakage current

–40°C to +125°C

LOGIC INPUTS (SEL)

V_IH

V_IL

Input logic high

Input logic low

–40°C to +125°C

1.35

5.5

0.8

I_IH

I_IL

Input leakage current

25°C

±0.005

µA

I_IH

I_IL

-40°C to 125°C

±0.05

C_IN

Logic input capacitance

25°C

–40°C to +125°C

POWER SUPPLY

25°C

0.003

µA

I_DDV_DDsupply current

Logic inputs = 0 V or 5.5 V

–40°C to +125°C

0.8

(1) When V_Sis 3 V, V_Dis 1 V or when V_Sis 1 V, V_Dis 3 V.

TMUX1219

ZHCSJR5 –MAY 2019

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Electrical Characteristics (V_DD= 3.3 V ±10 %) (continued)

at T_A= 25°C, V_DD= 3.3 V (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

DYNAMIC CHARACTERISTICS

25°C

V_S= 2 V

t_TRAN

Switching time between channels R_L= 200 Ω, C_L= 15 pF

–40°C to +85°C

–40°C to +125°C

25°C

Refer to Transition Time

V_S= 2 V

t_OPEN

(BBM)

Break before make time

Charge Injection

R_L= 200 Ω, C_L= 15 pF

Refer to Break-Before-Make

–40°C to +85°C

–40°C to +125°C

V_D= 1 V

R_S= 0 Ω, C_L= 1 nF

Refer to Charge Injection

Q_C

25°C

–6

–65

–45

–65

–45

R_L= 50 Ω, C_L= 5 pF

f = 1 MHz

Refer to Off Isolation

O_ISO

Off Isolation

Crosstalk

R_L= 50 Ω, C_L= 5 pF

f = 10 MHz

Refer to Off Isolation

R_L= 50 Ω, C_L= 5 pF

f = 1 MHz

Refer to Crosstalk

X_TALK

R_L= 50 Ω, C_L= 5 pF

f = 10 MHz

Refer to Crosstalk

R_L= 50 Ω, C_L= 5 pF

Refer to Bandwidth

Bandwidth

25°C

250

MHz

C_SOFF

Source off capacitance

On capacitance

f = 1 MHz

C_SON

C_DON

f = 1 MHz

TMUX1219

www.ti.com.cn

ZHCSJR5 –MAY 2019

6.7 Electrical Characteristics (V_DD= 1.8 V ±10 %)

at T_A= 25°C, V_DD= 1.8 V (unless otherwise noted)

PARAMETER

ANALOG SWITCH

TEST CONDITIONS

MIN

TYP

MAX UNIT

25°C

V_S= 0 V to V_DD

R_ON

On-resistance

I_SD= 10 mA

Refer to On-Resistance

–40°C to +85°C

–40°C to +125°C

25°C

0.4

±5

V_S= 0 V to V_DD

I_SD= 10 mA

Refer to On-Resistance

On-resistance matching between

channels

ΔR_ON

–40°C to +85°C

–40°C to +125°C

25°C

1.5

V_DD= 1.98 V

Switch Off

V_D= 1.62 V / 1 V

V_S= 1 V / 1.62 V

Refer to Off-Leakage Current

–40°C to +85°C

–25

–40

I_S(OFF)

Source off leakage current⁽¹⁾

Channel on leakage current

–40°C to +125°C

V_DD= 1.98 V

Switch On

V_D= V_S= 1.62 V / 1 V

Refer to On-Leakage Current

25°C

±15

I_D(ON)

I_S(ON)

–40°C to +85°C

–50

–80

–40°C to +125°C

LOGIC INPUTS (SEL)

V_IH

V_IL

Input logic high

Input logic low

–40°C to +125°C

1.07

5.5

0.68

I_IH

I_IL

Input leakage current

25°C

±0.005

µA

I_IH

I_IL

–40°C to +125°C

±0.05

C_IN

Logic input capacitance

25°C

–40°C to +125°C

POWER SUPPLY

25°C

0.001

µA

I_DDV_DDsupply current

Logic inputs = 0 V or 5.5 V

–40°C to +125°C

0.6

(1) When V_Sis 1.62 V, V_Dis 1 V or when V_Sis 1 V, V_Dis 1.62 V.

TMUX1219

ZHCSJR5 –MAY 2019

www.ti.com.cn

Electrical Characteristics (V_DD= 1.8 V ±10 %) (continued)

at T_A= 25°C, V_DD= 1.8 V (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

DYNAMIC CHARACTERISTICS

25°C

V_S= 1 V

t_TRAN

Transition time between channels R_L= 200 Ω, C_L= 15 pF

–40°C to +85°C

–40°C to +125°C

25°C

Refer to Transition Time

V_S= 1 V

t_OPEN

(BBM)

Break before make time

Charge Injection

R_L= 200 Ω, C_L= 15 pF

Refer to Break-Before-Make

–40°C to +85°C

–40°C to +125°C

V_D= 1 V

R_S= 0 Ω, C_L= 1 nF

Refer to Charge Injection

Q_C

25°C

–3

–65

–45

–65

–45

R_L= 50 Ω, C_L= 5 pF

f = 1 MHz

Refer to Off Isolation

O_ISO

Off Isolation

Crosstalk

R_L= 50 Ω, C_L= 5 pF

f = 10 MHz

Refer to Off Isolation

R_L= 50 Ω, C_L= 5 pF

f = 1 MHz

Refer to Crosstalk

X_TALK

R_L= 50 Ω, C_L= 5 pF

f = 10 MHz

Refer to Crosstalk

Bandwidth

R_L= 50 Ω, C_L= 5 pF

25°C

250

MHz

C_SOFF

Source off capacitance

f = 1 MHz

C_SON

C_DON

On capacitance

f = 1 MHz

25°C

TMUX1219

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ZHCSJR5 –MAY 2019

6.8 Electrical Characteristics (V_DD= 1.2 V ±10 %)

at T_A= 25°C, V_DD= 1.2 V (unless otherwise noted)

PARAMETER

ANALOG SWITCH

TEST CONDITIONS

MIN

TYP

MAX UNIT

25°C

V_S= 0 V to V_DD

R_ON

On-resistance

I_SD= 10 mA

Refer to On-Resistance

–40°C to +85°C

–40°C to +125°C

25°C

105

0.4

±5

V_S= 0 V to V_DD

I_SD= 10 mA

Refer to On-Resistance

On-resistance matching between

channels

ΔR_ON

–40°C to +85°C

–40°C to +125°C

25°C

1.5

V_DD= 1.32 V

Switch Off

V_D= 1 V / 0.8 V

V_S= 0.8 V / 1 V

Refer to Off-Leakage Current

–40°C to +85°C

–25

–40

I_S(OFF)

Source off leakage current⁽¹⁾

Channel on leakage current

–40°C to +125°C

V_DD= 1.32 V

Switch On

V_D= V_S= 1 V / 0.8 V

Refer to On-Leakage Current

25°C

±15

I_D(ON)

I_S(ON)

–40°C to +85°C

–50

–80

–40°C to +125°C

LOGIC INPUTS (SEL)

V_IH

V_IL

Input logic high

Input logic low

–40°C to +125°C

0.96

5.5

0.36

I_IH

I_IL

Input leakage current

25°C

±0.005

µA

I_IH

I_IL

–40°C to +125°C

±0.05

C_IN

Logic input capacitance

25°C

–40°C to +125°C

POWER SUPPLY

25°C

0.003

µA

I_DDV_DDsupply current

Logic inputs = 0 V or 5.5 V

–40°C to +125°C

0.5

(1) When V_Sis 1 V, V_Dis 0.8 V or when V_Sis 0.8 V, V_Dis 1 V.

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Electrical Characteristics (V_DD= 1.2 V ±10 %) (continued)

at T_A= 25°C, V_DD= 1.2 V (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

DYNAMIC CHARACTERISTICS

25°C

V_S= 1 V

t_TRAN

Transition time between channels R_L= 200 Ω, C_L= 15 pF

–40°C to +85°C

–40°C to +125°C

25°C

190

Refer to Transition Time

V_S= 1 V

t_OPEN

(BBM)

Break before make time

Charge Injection

R_L= 200 Ω, C_L= 15 pF

Refer to Break-Before-Make

–40°C to +85°C

–40°C to +125°C

V_D= 1 V

R_S= 0 Ω, C_L= 1 nF

Refer to Charge Injection

Q_C

25°C

–2

–65

–45

–65

–45

R_L= 50 Ω, C_L= 5 pF

f = 1 MHz

Refer to Off Isolation

O_ISO

Off Isolation

Crosstalk

R_L= 50 Ω, C_L= 5 pF

f = 10 MHz

Refer to Off Isolation

R_L= 50 Ω, C_L= 5 pF

f = 1 MHz

Refer to Crosstalk

X_TALK

R_L= 50 Ω, C_L= 5 pF

f = 10 MHz

Refer to Crosstalk

Bandwidth

R_L= 50 Ω, C_L= 5 pF

25°C

250

MHz

C_SOFF

Source off capacitance

f = 1 MHz

C_SON

C_DON

On capacitance

f = 1 MHz

25°C

TMUX1219

www.ti.com.cn

ZHCSJR5 –MAY 2019

6.9 Typical Characteristics

at T_A= 25°C, V_DD= 5 V (unless otherwise noted)

V_DD= 1.08V

T_A= 125èC

T_A= 85èC

V_DD= 1.62 V

V_DD= 3 V

V_DD= 4.5 V

T_A= 25èC

T_A= -40èC

0.5

1.5

2.5

3.5

4.5

0.5

1.5

2.5

Source or Drain Voltage (V)

D001

D002

T_A= 25°C

V_DD= 3 V

图 1. On-Resistance vs Source or Drain Voltage

图 2. On-Resistance vs Source or Drain Voltage

500

400

300

200

100

Rising

Falling

V_DD= 3.3 V

V_DD= 5 V

0.5

1.5

2.5

3.5

4.5

0.5

1.5

2.5

3.5

4.5

5.5

Logic Voltage (V)

V_DD- Supply Voltage (V)

D003

D004

T_A= 25°C

图 3. Supply Current vs Logic Voltage

图 4. T_transitionvs Supply Voltage

-10

-20

-30

-40

-50

-60

-70

-80

-90

-1

-2

-3

-4

-5

-6

-7

-8

100k

10M

100M

10M

100M

Frequency (Hz)

D005

D006

T_A= 25°C

图 5. Crosstalk and Off-Isolation vs Frequency

图 6. Frequency Response

TMUX1219

ZHCSJR5 –MAY 2019

www.ti.com.cn

7 Parameter Measurement Information

7.1 On-Resistance

The on-resistance of a device is the ohmic resistance between the source (Sx) and drain (D) pins of the device.

The on-resistance varies with input voltage and supply voltage. The symbol R_ONis used to denote on-resistance.

The measurement setup used to measure R_ONis shown in 图 7. Voltage (V) and current (I_SD) are measured

using this setup, and R_ONis computed with R_ON= V / I_SD

I_SD

V_S

图 7. On-Resistance Measurement Setup

7.2 Off-Leakage Current

Source leakage current is defined as the leakage current flowing into or out of the source pin when the switch is

off. This current is denoted by the symbol I_S(OFF)

The setup used to measure off-leakage current is shown in 图 8.

V_DD

I_{s (OFF)}

V_S

V_D

GND

图 8. Off-Leakage Measurement Setup

TMUX1219

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ZHCSJR5 –MAY 2019

7.3 On-Leakage Current

Source on-leakage current is defined as the leakage current flowing into or out of the source pin when the switch

is on. This current is denoted by the symbol I_S(ON)

Drain on-leakage current is defined as the leakage current flowing into or out of the drain pin when the switch is

on. This current is denoted by the symbol I_D(ON)

Either the source pin or drain pin is left floating during the measurement. 图 9 shows the circuit used for

measuring the on-leakage current, denoted by I_S(ON)or I_D(ON)

V_DD

I_{S (ON)}

I_{D (ON)}

N.C.

V_S

V_D

GND

图 9. On-Leakage Measurement Setup

7.4 Transition Time

Transition time is defined as the time taken by the output of the device to rise or fall 10% after the logic control

signal has risen or fallen past the logic threshold. The 10% transition measurement is utilized to provide the

timing of the device. System level timing can then account for the time constant added from the load resistance

and load capacitance. 图 10 shows the setup used to measure transition time, denoted by the symbol t_TRANSITION

V_DD

0.1…F

V_DD

Logic

t_f< 5ns

t_r< 5ns

Control

(V_SEL

V_IH

)

V_IL

V_S

OUTPUT

0 V

R_L

C_L

t_TRANSITION

SEL

90%

OUTPUT

V_SEL

10%

GND

0 V

图 10. Transition-Time Measurement Setup

TMUX1219

ZHCSJR5 –MAY 2019

www.ti.com.cn

7.5 Break-Before-Make

Break-before-make delay is a safety feature that prevents two inputs from connecting when the device is

switching. The output first breaks from the on-state switch before making the connection with the next on-state

switch. The time delay between the break and the make is known as break-before-make delay. 图 11 shows the

setup used to measure break-before-make delay, denoted by the symbol t_OPEN(BBM)

V_DD

0.1…F

V_DD

Logic

Control

t_r< 5ns

t_f< 5ns

V_S

OUTPUT

(V_SEL

)

0 V

R_L

C_L

90%

Output

SEL

t_BBM

t_BBM2

0 V

V_SEL

t_{OPEN (BBM)}= min ( t_BBM1, t_BBM2)

GND

图 11. Break-Before-Make Delay Measurement Setup

7.6 Charge Injection

The TMUX1219 has a transmission-gate topology. Any mismatch in capacitance between the NMOS and PMOS

transistors results in a charge injected into the drain or source during the falling or rising edge of the gate signal.

The amount of charge injected into the source or drain of the device is known as charge injection, and is denoted

by the symbol Q_C. 图 12 shows the setup used to measure charge injection from Drain (D) to Source (Sx).

V_DD

V_SS

0.1…F

V_SS

V_DD

V_SEL

N.C.

V_D

OUTPUT

V_OUT

0 V

C_L

Output

V_OUT

SEL

V_S

Q_C= C_L

V_OUT

V_SEL

GND

图 12. Charge-Injection Measurement Setup

TMUX1219

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ZHCSJR5 –MAY 2019

7.7 Off Isolation

Off isolation is defined as the ratio of the signal at the drain pin (D) of the device when a signal is applied to the

source pin (Sx) of an off-channel. 图 13 shows the setup used to measure, and the equation used to calculate off

isolation.

0.1µF

NETWORK

V_DD

ANALYZER

V_S

50Q

V_SIG

V_OUT

R_L

50Q

S_X

GND

R_L

50Q

图 13. Off Isolation Measurement Setup

≈

∆

’

◊

V_OUT

V_S

Off Isolation = 20 ∂ Log

(1)

7.8 Crosstalk

Crosstalk is defined as the ratio of the signal at the drain pin (D) of a different channel, when a signal is applied

at the source pin (Sx) of an on-channel. 图 14 shows the setup used to measure, and the equation used to

calculate crosstalk.

0.1µF

NETWORK

V_DD

ANALYZER

V_OUT

R_L

50Q

V_S

R_L

50Q

V_SIG

GND

图 14. Crosstalk Measurement Setup

≈

∆

’

◊

V_OUT

V_S

Channel-to-Channel Crosstalk = 20 ∂ Log

(2)

TMUX1219

ZHCSJR5 –MAY 2019

www.ti.com.cn

7.9 Bandwidth

Bandwidth is defined as the range of frequencies that are attenuated by less than 3 dB when the input is applied

to the source pin (Sx) of an on-channel, and the output is measured at the drain pin (D) of the device. 图 15

shows the setup used to measure bandwidth.

0.1µF

NETWORK

V_DD

ANALYZER

V_S

50Q

V_SIG

V_OUT

R_L

50Q

S_X

GND

R_L

50Q

图 15. Bandwidth Measurement Setup

TMUX1219

www.ti.com.cn

ZHCSJR5 –MAY 2019

8 Detailed Description

8.1 Functional Block Diagram

The TMUX1219 is an 2:1 (SPDT), 1-channel switch where the input is controlled with a single select (SEL)

control pin.

TMUX1219

SEL

图 16. TMUX1219 Functional Block Diagram

8.2 Feature Description

8.2.1 Bidirectional Operation

The TMUX1219 conducts equally well from source (Sx) to drain (D) or from drain (D) to source (Sx). The device

has very similar characteristics in both directions and supports both analog and digital signals.

8.2.2 Rail to Rail Operation

The valid signal path input/output voltage for TMUX1219 ranges from GND to V_DD

8.2.3 1.8 V Logic Compatible Inputs

The TMUX1219 has 1.8-V logic compatible control for the logic control input (SEL). The logic input threshold

scales with supply but still provides 1.8-V logic control when operating at 5.5 V supply voltage. 1.8-V logic level

inputs allow the TMUX1219 to interface with processors that have lower logic I/O rails and eliminates the need

for an external translator, which saves both space and BOM cost. For more information on 1.8 V logic

implementations refer to Simplifying Design with 1.8 V logic Muxes and Switches

8.2.4 Fail-Safe Logic

The TMUX1219 supports Fail-Safe Logic on the control input pin (SEL) allowing for operation up to 5.5 V,

regardless of the state of the supply pin. This feature allows voltages on the control pin to be applied before the

supply pin, protecting the device from potential damage. Fail-Safe Logic minimizes system complexity by

removing the need for power supply sequencing on the logic control pins. For example, the Fail-Safe Logic

feature allows the select pin of the TMUX1219 to be ramped to 5.5 V while V_DD= 0 V. Additionally, the feature

enables operation of the TMUX1219 with V_DD= 1.2 V while allowing the select pin to interface with a logic level

of another device up to 5.5 V.

8.3 Device Functional Modes

The select (SEL) pin of the TMUX1219 controls which source channel is connected to the drain of the device.

When a signal path is not selected, that source pin is in high impedance mode (HI-Z). The control pin can be as

high as 5.5 V.

8.4 Truth Tables

表 1. TMUX1219 Truth Table

CONTROL LOGIC (SEL)

Selected Source (Sx) Connected To Drain (D) Pin

TMUX1219

ZHCSJR5 –MAY 2019

www.ti.com.cn

9 Application and Implementation

注

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

9.1 Application Information

The TMUX12xx family offers good system performance across a wide operating supply (1.08V to 5.5V). These

devices include 1.8V logic compatible control input pins that enable operation in systems with 1.8V I/O rails.

Additionally, the control input pin supports Fail-Safe Logic which allows for operation up to 5.5V, regardless of

the state of the supply pin. This protection stops the logic pins from back-powering the supply rail. These

features of the TMUX12xx, a family of general purpose multiplexers and switches, reduce system complexity,

board size, and overall system cost.

9.2 Typical Application

9.2.1 Switchable Operational Amplifier Gain Setting

One example application of the TMUX1219 is to change an Op Amp from unity gain setting to an inverting

amplifier configuration. Utilizing a switch allows a system to have a configurable gain and allows the same

architecture to be utilized across the board for various inputs to the system. 图 17 shows the TMUX1219

configured for gain setting application.

Input

Output

Unity Gain

Inverting

TLV9001

1.8 V

SEL

TMUX1219

图 17. Switchable Op Amp Gain Setting

9.2.1.1 Design Requirements

This design example uses the parameters listed in 表 2.

表 2. Design Parameters

PARAMETERS

Input Signal

VALUES

0 V to 2.75 V

Mux Supply (V_DD

)

2.75 V

Op Amp Supply (V₊/ V_-)

Mux I/O signal range

Control logic thresholds

±2.75 V

0 V to V_DD(Rail to Rail)

1.8 V compatible (up to 5.5V)

TMUX1219

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ZHCSJR5 –MAY 2019

9.2.1.2 Detailed Design Procedure

The application shown in 图 17 demonstrates how to use a single control input and toggle between gain settings

of -1 and +1. If switching between inverting and unity gain is not required, the TMUX1219 can be utilized in the

feedback path to select different feedback resistors and provide scalable gain settings for configurable signal

conditioning.

The TMUX1219 can be operated without any external components except for the supply decoupling capacitors.

The select pin is recommended to have a weak pull-down or pull-up resistor to ensure the input is in a known

state. All inputs to the switch must fall within the recommend operating conditions of the TMUX1219 including

signal range and continuous current. For this design with a supply of 2.75 V the signal range can be 0 V to 2.75

V and the max continuous current can be 30 mA.

9.2.1.3 Application Curve

V_DD= 1.08V

V_DD= 1.62 V

V_DD= 3 V

V_DD= 4.5 V

0.5

1.5

2.5

3.5

4.5

Source or Drain Voltage (V)

D001

T_A= 25°C

图 18. On-Resistance vs Source or Drain Voltage

9.2.2 Input Control for Power Amplifier

Another application of the TMUX1219 is for input control of a power amplifier. Utilizing a switch allows a system

to control when the DAC is connected to the power amplifier, and can stop biasing the power amplifier by

switching the gate to GND. 图 19 shows the TMUX1219 configured for control of the power amplifier.

RF Input

RF Output

5 V

TMUX1219

0 V

DAC

1.8 V

SEL

图 19. Input Control of Power Amplifier

TMUX1219

ZHCSJR5 –MAY 2019

www.ti.com.cn

9.2.2.1 Design Requirements

This design example uses the parameters listed in 表 2.

表 3. Design Parameters

PARAMETERS

Supply (V_DD

VALUES

5 V

)

Mux I/O signal range

0 V to V_DD(Rail to Rail)

1.8 V compatible (up to 5.5V)

Control logic thresholds

9.2.2.2 Detailed Design Procedure

The application shown in 图 19 demonstrates how to toggle between the DAC output and GND for control of a

power amplifier using a single control input. The DAC output is utilized to bias the gate of the power amplifier and

can be disconnected from the circuit using the select pin of the switch. The TMUX1219 can support 1.8-V logic

signals on the control input, allowing the device to interface with low logic controls of an FPGA or MCU. The

TMUX1219 can be operated without any external components except for the supply decoupling capacitors. The

select pin is recommended to have a weak pull-down or pull-up resistor to ensure the input is in a known state.

All inputs to the switch must fall within the recommend operating conditions of the TMUX1219 including signal

range and continuous current. For this design with a supply of 5 V the signal range can be 0 V to 5 V and the

max continuous current can be 30 mA.

9.2.2.3 Application Curve

A key parameter for this application is the transition time of the device. Faster transition time allows the system to

toggle between input sources at a faster rate and allows the output to settle to the final value. The TMUX1219

has a transition time that varies with supply voltage and is shown in 图 20

Rising

Falling

0.5

1.5

2.5

3.5

4.5

5.5

V_DD- Supply Voltage (V)

D004

T_A= 25°C

图 20. T_transitionvs Supply Voltage

10 Power Supply Recommendations

The TMUX1219 operates across a wide supply range of 1.08 V to 5.5 V. Do not exceed the absolute maximum

ratings because stresses beyond the listed ratings can cause permanent damage to the devices.

Power-supply bypassing improves noise margin and prevents switching noise propagation from the V_DDsupply to

other components. Good power-supply decoupling is important to achieve optimum performance. For improved

supply noise immunity, use a supply decoupling capacitor ranging from 0.1 μF to 10 μF from V_DDto ground.

Place the bypass capacitors as close to the power supply pins of the device as possible using low-impedance

connections. TI recommends using multi-layer ceramic chip capacitors (MLCCs) that offer low equivalent series

resistance (ESR) and inductance (ESL) characteristics for power-supply decoupling purposes. For very sensitive

systems, or for systems in harsh noise environments, avoiding the use of vias for connecting the capacitors to

the device pins may offer superior noise immunity. The use of multiple vias in parallel lowers the overall

inductance and is beneficial for connections to ground planes.

TMUX1219

www.ti.com.cn

ZHCSJR5 –MAY 2019

11 Layout

11.1 Layout Guidelines

11.1.1 Layout Information

When a PCB trace turns a corner at a 90° angle, a reflection can occur. A reflection occurs primarily because of

the change of width of the trace. At the apex of the turn, the trace width increases to 1.414 times the width. This

increase upsets the transmission-line characteristics, especially the distributed capacitance and self–inductance

of the trace which results in the reflection. Not all PCB traces can be straight and therefore some traces must

turn corners. 图 21 shows progressively better techniques of rounding corners. Only the last example (BEST)

maintains constant trace width and minimizes reflections.

WORST

BETTER

BEST

1W min.

图 21. Trace Example

Route high-speed signals using a minimum of vias and corners which reduces signal reflections and

impedance changes. When a via must be used, increase the clearance size around it to minimize its

capacitance. Each via introduces discontinuities in the signal’s transmission line and increases the chance of

picking up interference from the other layers of the board. Be careful when designing test points, through-

hole pins are not recommended at high frequencies.

图 22 illustrates an example of a PCB layout with the TMUX1219. Some key considerations are:

•

Decouple the V_DDpin with a 0.1-µF capacitor, placed as close to the pin as possible. Make sure that the

capacitor voltage rating is sufficient for the V_DDsupply.

•

Keep the input lines as short as possible.

Use a solid ground plane to help reduce electromagnetic interference (EMI) noise pickup.

Do not run sensitive analog traces in parallel with digital traces. Avoid crossing digital and analog traces if

possible, and only make perpendicular crossings when necessary.

11.2 Layout Example

Via to

GND plane

TMUX1219

Wide (low inductance)

trace for power

图 22. TMUX1219 Layout Example

TMUX1219

ZHCSJR5 –MAY 2019

www.ti.com.cn

12 器件和文档支持

12.1 文档支持

12.1.1 相关文档

德州仪器 (TI)，《使用低 CON 多路复用器改善稳定性问题》。

德州仪器 (TI)，《使用 1.8V 逻辑多路复用器和开关简化设计》。

德州仪器 (TI)，《利用关断保护信号开关消除电源排序》。

德州仪器 (TI)，《高电压模拟多路复用器的系统级保护》。

12.2 接收文档更新通知

要接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我进行注册，即可每周接收产

品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

12.3 社区资源

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective

contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of

Use.

TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration

among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help

solve problems with fellow engineers.

Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and

contact information for technical support.

12.4 商标

E2E is a trademark of Texas Instruments.

12.5 静电放电警告

ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可

能会损坏集成电路。

ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可

能会导致器件与其发布的规格不相符。

12.6 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

13 机械、封装和可订购信息

以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且

不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。

PACKAGE OPTION ADDENDUM

www.ti.com

10-Dec-2020

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

TMUX1219DBVR

TMUX1219DCKR

ACTIVE

SOT-23

SC70

DBV

DCK

3000 RoHS & Green

NIPDAU

Level-1-260C-UNLIM

-40 to 125

26IT

1F5

NIPDAU

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

10-Dec-2020

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

5-Jun-2020

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

TMUX1219DBVR

TMUX1219DCKR

SOT-23

SC70

DBV

DCK

3000

178.0

9.0

2.4

2.5

1.2

4.0

8.0

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

5-Jun-2020

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

TMUX1219DBVR

TMUX1219DCKR

SOT-23

SC70

DBV

DCK

3000

180.0

18.0

Pack Materials-Page 2

PACKAGE OUTLINE

DBV0006A

SOT-23 - 1.45 mm max height

SMALL OUTLINE TRANSISTOR

3.0

2.6

0.1 C

1.75

1.45

1.45 MAX

PIN 1

INDEX AREA

2X 0.95

1.9

3.05

2.75

0.50

0.25

C A B

0.15

0.00

0.2

(1.1)

TYP

0.25

GAGE PLANE

0.22

0.08

TYP

0.6

0.3

TYP

SEATING PLANE

4214840/C 06/2021

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. Body dimensions do not include mold flash or protrusion. Mold flash and protrusion shall not exceed 0.25 per side.

4. Leads 1,2,3 may be wider than leads 4,5,6 for package orientation.

5. Refernce JEDEC MO-178.

www.ti.com

EXAMPLE BOARD LAYOUT

DBV0006A

SOT-23 - 1.45 mm max height

SMALL OUTLINE TRANSISTOR

PKG

6X (1.1)

6X (0.6)

SYMM

2X (0.95)

(R0.05) TYP

(2.6)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:15X

SOLDER MASK

OPENING

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

METAL

EXPOSED METAL

0.07 MIN

ARROUND

0.07 MAX

ARROUND

NON SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4214840/C 06/2021

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com

EXAMPLE STENCIL DESIGN

DBV0006A

SOT-23 - 1.45 mm max height

SMALL OUTLINE TRANSISTOR

PKG

6X (1.1)

6X (0.6)

SYMM

2X(0.95)

(R0.05) TYP

(2.6)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

SCALE:15X

4214840/C 06/2021

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

9. Board assembly site may have different recommendations for stencil design.

www.ti.com

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